text
stringlengths 1
2.1M
|
|---|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:46:43 05/03/2016
// Design Name:
// Module Name: uart_top1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_instance(
clk,
rst_n,
rs232_rx,
rs232_tx,
data_ok,
uart_ctl
);
input clk; // 50mhz
input rst_n;
input rs232_rx; // RS232 rec
input [2:0] uart_ctl;
output rs232_tx; // RS232 transfer
output data_ok;
////////////////
parameter DELAY_N = 15;
wire [2:0] uart_ctl;
wire [7:0] data_in, data_out;
wire data_in_sign, data_out_sign;
wire data_valid;
reg [DELAY_N - 1: 0] rst_cnt;
wire rst_wire ;
assign rst_wire = rst_cnt[DELAY_N - 1];
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
rst_cnt <= 'h0;
end
else begin
if(~rst_cnt[DELAY_N - 1]) rst_cnt <= rst_cnt + 1'b1;
end
end
my_uart_tx8to8 tx_inst (
.clk(clk),
.rst_n(rst_wire),
.uart_ctl(uart_ctl),
.data_out(data_out),
.data_sign(data_out_sign),
.data_valid(data_valid),
.rs_tx(rs232_tx)
);
my_uart_rx8to8 rx_inst(
.clk(clk),
.rst_n(rst_wire),
.uart_ctl(uart_ctl),
.rs_rx(rs232_rx),
.data_in(data_in),
.data_sign(data_in_sign)
);
data_deal data_deal (
.clk(clk),
.rst_n(rst_wire),
.data_in(data_in),
.data_in_sign(data_in_sign),
.data_out(data_out),
.data_out_sign(data_out_sign),
.data_valid(data_valid),
.data_ok(data_ok)
);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP checksum calculation module
*/
module udp_checksum_gen #
(
parameter PAYLOAD_FIFO_DEPTH = 2048,
parameter HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [7:0] s_udp_payload_axis_tdata,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [7:0] m_udp_payload_axis_tdata,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status signals
*/
output wire busy
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives a UDP frame with header fields in parallel and payload on
an AXI stream interface, calculates the length and checksum, then produces the
header fields in parallel along with the UDP payload in a separate AXI stream.
*/
parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_SUM_HEADER_1 = 3'd1,
STATE_SUM_HEADER_2 = 3'd2,
STATE_SUM_HEADER_3 = 3'd3,
STATE_SUM_PAYLOAD = 3'd4,
STATE_FINISH_SUM = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg shift_payload_in;
reg [31:0] checksum_part;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [31:0] checksum_reg = 32'd0, checksum_next;
reg [47:0] eth_dest_mac_reg = 48'd0;
reg [47:0] eth_src_mac_reg = 48'd0;
reg [15:0] eth_type_reg = 16'd0;
reg [3:0] ip_version_reg = 4'd0;
reg [3:0] ip_ihl_reg = 4'd0;
reg [5:0] ip_dscp_reg = 6'd0;
reg [1:0] ip_ecn_reg = 2'd0;
reg [15:0] ip_identification_reg = 16'd0;
reg [2:0] ip_flags_reg = 3'd0;
reg [12:0] ip_fragment_offset_reg = 13'd0;
reg [7:0] ip_ttl_reg = 8'd0;
reg [15:0] ip_header_checksum_reg = 16'd0;
reg [31:0] ip_source_ip_reg = 32'd0;
reg [31:0] ip_dest_ip_reg = 32'd0;
reg [15:0] udp_source_port_reg = 16'd0;
reg [15:0] udp_dest_port_reg = 16'd0;
reg hdr_valid_reg = 0, hdr_valid_next;
reg s_udp_hdr_ready_reg = 1'b0, s_udp_hdr_ready_next;
reg s_udp_payload_axis_tready_reg = 1'b0, s_udp_payload_axis_tready_next;
reg busy_reg = 1'b0;
/*
* UDP Payload FIFO
*/
wire [7:0] s_udp_payload_fifo_tdata;
wire s_udp_payload_fifo_tvalid;
wire s_udp_payload_fifo_tready;
wire s_udp_payload_fifo_tlast;
wire s_udp_payload_fifo_tuser;
wire [7:0] m_udp_payload_fifo_tdata;
wire m_udp_payload_fifo_tvalid;
wire m_udp_payload_fifo_tready;
wire m_udp_payload_fifo_tlast;
wire m_udp_payload_fifo_tuser;
axis_fifo #(
.DEPTH(PAYLOAD_FIFO_DEPTH),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_udp_payload_fifo_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(s_udp_payload_fifo_tvalid),
.s_axis_tready(s_udp_payload_fifo_tready),
.s_axis_tlast(s_udp_payload_fifo_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(s_udp_payload_fifo_tuser),
// AXI output
.m_axis_tdata(m_udp_payload_fifo_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(m_udp_payload_fifo_tvalid),
.m_axis_tready(m_udp_payload_fifo_tready),
.m_axis_tlast(m_udp_payload_fifo_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(m_udp_payload_fifo_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
assign s_udp_payload_fifo_tdata = s_udp_payload_axis_tdata;
assign s_udp_payload_fifo_tvalid = s_udp_payload_axis_tvalid && shift_payload_in;
assign s_udp_payload_axis_tready = s_udp_payload_fifo_tready && shift_payload_in;
assign s_udp_payload_fifo_tlast = s_udp_payload_axis_tlast;
assign s_udp_payload_fifo_tuser = s_udp_payload_axis_tuser;
assign m_udp_payload_axis_tdata = m_udp_payload_fifo_tdata;
assign m_udp_payload_axis_tvalid = m_udp_payload_fifo_tvalid;
assign m_udp_payload_fifo_tready = m_udp_payload_axis_tready;
assign m_udp_payload_axis_tlast = m_udp_payload_fifo_tlast;
assign m_udp_payload_axis_tuser = m_udp_payload_fifo_tuser;
/*
* UDP Header FIFO
*/
reg [HEADER_FIFO_ADDR_WIDTH:0] header_fifo_wr_ptr_reg = {HEADER_FIFO_ADDR_WIDTH+1{1'b0}}, header_fifo_wr_ptr_next;
reg [HEADER_FIFO_ADDR_WIDTH:0] header_fifo_rd_ptr_reg = {HEADER_FIFO_ADDR_WIDTH+1{1'b0}}, header_fifo_rd_ptr_next;
reg [47:0] eth_dest_mac_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [47:0] eth_src_mac_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] eth_type_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [3:0] ip_version_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [3:0] ip_ihl_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [5:0] ip_dscp_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [1:0] ip_ecn_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] ip_identification_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [2:0] ip_flags_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [12:0] ip_fragment_offset_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [7:0] ip_ttl_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] ip_header_checksum_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [31:0] ip_source_ip_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [31:0] ip_dest_ip_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_source_port_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_dest_port_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_length_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [15:0] udp_checksum_mem[(2**HEADER_FIFO_ADDR_WIDTH)-1:0];
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg [15:0] m_udp_source_port_reg = 16'd0;
reg [15:0] m_udp_dest_port_reg = 16'd0;
reg [15:0] m_udp_length_reg = 16'd0;
reg [15:0] m_udp_checksum_reg = 16'd0;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
// full when first MSB different but rest same
wire header_fifo_full = ((header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH] != header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH]) &&
(header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0] == header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire header_fifo_empty = header_fifo_wr_ptr_reg == header_fifo_rd_ptr_reg;
// control signals
reg header_fifo_write;
reg header_fifo_read;
wire header_fifo_ready = !header_fifo_full;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_udp_length_reg + 16'd20;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = 8'h11;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// Write logic
always @* begin
header_fifo_write = 1'b0;
header_fifo_wr_ptr_next = header_fifo_wr_ptr_reg;
if (hdr_valid_reg) begin
// input data valid
if (~header_fifo_full) begin
// not full, perform write
header_fifo_write = 1'b1;
header_fifo_wr_ptr_next = header_fifo_wr_ptr_reg + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
header_fifo_wr_ptr_reg <= {HEADER_FIFO_ADDR_WIDTH+1{1'b0}};
end else begin
header_fifo_wr_ptr_reg <= header_fifo_wr_ptr_next;
end
if (header_fifo_write) begin
eth_dest_mac_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_dest_mac_reg;
eth_src_mac_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_src_mac_reg;
eth_type_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= eth_type_reg;
ip_version_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_version_reg;
ip_ihl_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ihl_reg;
ip_dscp_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_dscp_reg;
ip_ecn_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ecn_reg;
ip_identification_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_identification_reg;
ip_flags_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_flags_reg;
ip_fragment_offset_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_fragment_offset_reg;
ip_ttl_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_ttl_reg;
ip_header_checksum_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_header_checksum_reg;
ip_source_ip_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_source_ip_reg;
ip_dest_ip_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= ip_dest_ip_reg;
udp_source_port_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= udp_source_port_reg;
udp_dest_port_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= udp_dest_port_reg;
udp_length_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= frame_ptr_reg;
udp_checksum_mem[header_fifo_wr_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]] <= checksum_reg[15:0];
end
end
// Read logic
always @* begin
header_fifo_read = 1'b0;
header_fifo_rd_ptr_next = header_fifo_rd_ptr_reg;
m_udp_hdr_valid_next = m_udp_hdr_valid_reg;
if (m_udp_hdr_ready || !m_udp_hdr_valid) begin
// output data not valid OR currently being transferred
if (!header_fifo_empty) begin
// not empty, perform read
header_fifo_read = 1'b1;
m_udp_hdr_valid_next = 1'b1;
header_fifo_rd_ptr_next = header_fifo_rd_ptr_reg + 1;
end else begin
// empty, invalidate
m_udp_hdr_valid_next = 1'b0;
end
end
end
always @(posedge clk) begin
if (rst) begin
header_fifo_rd_ptr_reg <= {HEADER_FIFO_ADDR_WIDTH+1{1'b0}};
m_udp_hdr_valid_reg <= 1'b0;
end else begin
header_fifo_rd_ptr_reg <= header_fifo_rd_ptr_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
end
if (header_fifo_read) begin
m_eth_dest_mac_reg <= eth_dest_mac_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_eth_src_mac_reg <= eth_src_mac_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_eth_type_reg <= eth_type_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_version_reg <= ip_version_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ihl_reg <= ip_ihl_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_dscp_reg <= ip_dscp_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ecn_reg <= ip_ecn_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_identification_reg <= ip_identification_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_flags_reg <= ip_flags_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_fragment_offset_reg <= ip_fragment_offset_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_ttl_reg <= ip_ttl_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_header_checksum_reg <= ip_header_checksum_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_source_ip_reg <= ip_source_ip_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_ip_dest_ip_reg <= ip_dest_ip_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_source_port_reg <= udp_source_port_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_dest_port_reg <= udp_dest_port_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_length_reg <= udp_length_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
m_udp_checksum_reg <= udp_checksum_mem[header_fifo_rd_ptr_reg[HEADER_FIFO_ADDR_WIDTH-1:0]];
end
end
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
s_udp_hdr_ready_next = 1'b0;
s_udp_payload_axis_tready_next = 1'b0;
store_udp_hdr = 1'b0;
shift_payload_in = 1'b0;
frame_ptr_next = frame_ptr_reg;
checksum_next = checksum_reg;
hdr_valid_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state
s_udp_hdr_ready_next = header_fifo_ready;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
frame_ptr_next = 0;
// 16'h0011 = zero padded type field
// 16'h0010 = header length times two
checksum_next = 16'h0011 + 16'h0010;
s_udp_hdr_ready_next = 1'b0;
state_next = STATE_SUM_HEADER_1;
end else begin
state_next = STATE_IDLE;
end
end
STATE_SUM_HEADER_1: begin
// sum pseudo header and header
checksum_next = checksum_reg + ip_source_ip_reg[31:16] + ip_source_ip_reg[15:0];
state_next = STATE_SUM_HEADER_2;
end
STATE_SUM_HEADER_2: begin
// sum pseudo header and header
checksum_next = checksum_reg + ip_dest_ip_reg[31:16] + ip_dest_ip_reg[15:0];
state_next = STATE_SUM_HEADER_3;
end
STATE_SUM_HEADER_3: begin
// sum pseudo header and header
checksum_next = checksum_reg + udp_source_port_reg + udp_dest_port_reg;
frame_ptr_next = 8;
state_next = STATE_SUM_PAYLOAD;
end
STATE_SUM_PAYLOAD: begin
// sum payload
shift_payload_in = 1'b1;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
// checksum computation for payload - alternately store and accumulate
// add 2 for length calculation (two length fields in pseudo header)
if (frame_ptr_reg[0]) begin
checksum_next = checksum_reg + {8'h00, s_udp_payload_axis_tdata} + 2;
end else begin
checksum_next = checksum_reg + {s_udp_payload_axis_tdata, 8'h00} + 2;
end
frame_ptr_next = frame_ptr_reg + 1;
if (s_udp_payload_axis_tlast) begin
state_next = STATE_FINISH_SUM;
end else begin
state_next = STATE_SUM_PAYLOAD;
end
end else begin
state_next = STATE_SUM_PAYLOAD;
end
end
STATE_FINISH_SUM: begin
// add MSW (twice!) for proper ones complement sum
checksum_part = checksum_reg[15:0] + checksum_reg[31:16];
checksum_next = ~(checksum_part[15:0] + checksum_part[16]);
hdr_valid_next = 1;
state_next = STATE_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_udp_hdr_ready_reg <= 1'b0;
s_udp_payload_axis_tready_reg <= 1'b0;
hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
hdr_valid_reg <= hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
end
frame_ptr_reg <= frame_ptr_next;
checksum_reg <= checksum_next;
// datapath
if (store_udp_hdr) begin
eth_dest_mac_reg <= s_eth_dest_mac;
eth_src_mac_reg <= s_eth_src_mac;
eth_type_reg <= s_eth_type;
ip_version_reg <= s_ip_version;
ip_ihl_reg <= s_ip_ihl;
ip_dscp_reg <= s_ip_dscp;
ip_ecn_reg <= s_ip_ecn;
ip_identification_reg <= s_ip_identification;
ip_flags_reg <= s_ip_flags;
ip_fragment_offset_reg <= s_ip_fragment_offset;
ip_ttl_reg <= s_ip_ttl;
ip_header_checksum_reg <= s_ip_header_checksum;
ip_source_ip_reg <= s_ip_source_ip;
ip_dest_ip_reg <= s_ip_dest_ip;
udp_source_port_reg <= s_udp_source_port;
udp_dest_port_reg <= s_udp_dest_port;
end
end
endmodule
|
/*
* CameraOneFrame architecture
*
* Copyright (c) 2014,
* Luca Maggiani <[email protected]>,
* Scuola Superiore Sant'Anna (http://www.sssup.it) and
* Consorzio Nazionale Interuniversitario per le Telecomunicazioni
* (http://www.cnit.it).
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of the nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module matrix_prod(
clk_i,
reset_n_i,
sclr_i,
pix01_i,
pix10_i,
pix12_i,
pix21_i,
sin_i,
cos_i,
dv0_i,
dv1_i,
dv2_i,
data_o
);
parameter DATA_WIDTH = 8;
parameter COEF_WIDTH = 9;
input clk_i;
input reset_n_i;
input dv0_i;
input dv1_i;
input dv2_i;
input sclr_i;
input [DATA_WIDTH-1:0] pix01_i, pix10_i, pix12_i, pix21_i;
input [COEF_WIDTH-1:0] sin_i;
input [COEF_WIDTH-1:0] cos_i;
output [((COEF_WIDTH + DATA_WIDTH)+1):0] data_o;
/* Internal register definitions */
reg signed [DATA_WIDTH:0] tmpsin;
reg signed [DATA_WIDTH:0] tmpcos;
reg signed [(COEF_WIDTH + DATA_WIDTH):0] multsin;
reg signed [(COEF_WIDTH + DATA_WIDTH):0] multcos;
reg signed [((COEF_WIDTH + DATA_WIDTH)+1):0] finaladd;
//~ reg dv_d1, dv_d2;
/* Internal wire definitions */
wire signed [COEF_WIDTH-1:0] sin_wire;
wire signed [COEF_WIDTH-1:0] cos_wire;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
tmpsin <= {(DATA_WIDTH+1){1'b0}};
else if (dv0_i)
tmpsin <= pix21_i - pix01_i;
else
tmpsin <= tmpsin;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
tmpcos <= {(DATA_WIDTH+1){1'b0}};
else if (dv0_i)
tmpcos <= pix10_i - pix12_i;
else
tmpcos <= tmpcos;
//~ always@(posedge clk_i or negedge reset_n_i)
//~ if (reset_n_i == 0)
//~ begin
//~ dv_d1 <= 0;
//~ dv_d2 <= 0;
//~ end
//~ else if (dv_i)
//~ begin
//~ dv_d1 <= dv_i;
//~ dv_d2 <= dv_d1;
//~ end
assign sin_wire = sin_i;
assign cos_wire = cos_i;
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
begin
multsin <= {(COEF_WIDTH + DATA_WIDTH + 1){1'b0}};
multcos <= {(COEF_WIDTH + DATA_WIDTH + 1){1'b0}};
end
else if (dv1_i)
begin
multsin <= tmpsin * sin_wire;
multcos <= tmpcos * cos_wire;
end
always@(posedge clk_i or negedge reset_n_i)
if (reset_n_i == 0)
begin
finaladd <= {((COEF_WIDTH + DATA_WIDTH)+2){1'b0}};
end
else if (dv2_i)
begin
finaladd <= multsin + multcos;
end
assign data_o = (finaladd > 0) ? finaladd : (~finaladd + 1'b1);
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_addr_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// The address for the memory and the various user commands can be given
// through this module. It instantiates the block RAM which stores all the
// information in particular sequence. The data stored should be in a
// sequence starting from LSB:
// column address, row address, bank address, commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_addr_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
output reg [2:0] app_af_cmd,
output reg [30:0] app_af_addr,
output reg app_af_wren
);
// RAM initialization patterns
// NOTE: Not all bits in each range may be used (e.g. in an application
// using only 10 column bits, bits[11:10] of ROM output will be unused
// COLUMN = [11:0]
// ROW = [27:12]
// BANK = [30:28]
// CHIP = [31]
// COMMAND = [35:32]
localparam RAM_INIT_00 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_01 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_02 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_03 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_04 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_05 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_06 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INIT_07 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INITP_00 = {128'h11111111_00000000_11111111_00000000,
128'h11111111_00000000_11111111_00000000};
reg wr_addr_en_r1;
reg [2:0] af_cmd_r;
reg [30:0] af_addr_r;
reg af_wren_r;
wire [15:0] ramb_addr;
wire [35:0] ramb_dout;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [5:0] wr_addr_cnt;
reg wr_addr_en_r0;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//*****************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//***************************************************************************
// ADDRESS generation for Write and Read Address FIFOs:
// ROM with address patterns
// 512x36 mode is used with addresses 0-127 for storing write addresses and
// addresses (128-511) for storing read addresses
// INIP_OO: read 1
// INIP_OO: write 0
//***************************************************************************
assign ramb_addr = {5'b00000, wr_addr_cnt, 5'b00000};
RAMB36 #
(
.READ_WIDTH_A (36),
.READ_WIDTH_B (36),
.DOA_REG (1), // register to help timing
.INIT_00 (RAM_INIT_00),
.INIT_01 (RAM_INIT_01),
.INIT_02 (RAM_INIT_02),
.INIT_03 (RAM_INIT_03),
.INIT_04 (RAM_INIT_04),
.INIT_05 (RAM_INIT_05),
.INIT_06 (RAM_INIT_06),
.INIT_07 (RAM_INIT_07),
.INITP_00 (RAM_INITP_00)
)
u_wr_rd_addr_lookup
(
.CASCADEOUTLATA (),
.CASCADEOUTLATB (),
.CASCADEOUTREGA (),
.CASCADEOUTREGB (),
.DOA (ramb_dout[31:0]),
.DOB (),
.DOPA (ramb_dout[35:32]),
.DOPB (),
.ADDRA (ramb_addr),
.ADDRB (16'h0000),
.CASCADEINLATA (),
.CASCADEINLATB (),
.CASCADEINREGA (),
.CASCADEINREGB (),
.CLKA (clk),
.CLKB (clk),
.DIA (32'b0),
.DIB (32'b0),
.DIPA (4'b0),
.DIPB (4'b0),
.ENA (1'b1),
.ENB (1'b1),
.REGCEA (1'b1),
.REGCEB (1'b1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (4'b0000),
.WEB (4'b0000)
);
// register backend enables / FIFO enables
// write enable for Command/Address FIFO is generated 2 CC after WR_ADDR_EN
// (takes 2 CC to come out of test RAM)
always @(posedge clk)
if (rst_r1) begin
app_af_wren <= 1'b0;
wr_addr_en_r0 <= 1'b0;
wr_addr_en_r1 <= 1'b0;
af_wren_r <= 1'b0;
end else begin
wr_addr_en_r0 <= wr_addr_en;
wr_addr_en_r1 <= wr_addr_en_r0;
af_wren_r <= wr_addr_en_r1;
app_af_wren <= af_wren_r;
end
// FIFO addresses
always @(posedge clk) begin
af_addr_r <= {30{1'b0}};
af_addr_r[COL_WIDTH-1:0] <= ramb_dout[COL_WIDTH-1:0];
af_addr_r[ROW_WIDTH+COL_WIDTH-1:COL_WIDTH]
<= ramb_dout[ROW_WIDTH+11:12];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1:ROW_WIDTH+COL_WIDTH]
<= ramb_dout[BANK_WIDTH+27:28];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH]
<= ramb_dout[31];
// only reads and writes are supported for now
af_cmd_r <= {1'b0, ramb_dout[33:32]};
app_af_cmd <= af_cmd_r;
app_af_addr <= af_addr_r;
end
// address input for RAM
always @ (posedge clk)
if (rst_r1)
wr_addr_cnt <= 6'b000000;
else if (wr_addr_en)
wr_addr_cnt <= wr_addr_cnt + 1;
endmodule
|
`timescale 1 ns / 1 ps
module axis_bram_reader #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10,
parameter CONTINUOUS = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [BRAM_ADDR_WIDTH-1:0] int_data_reg;
reg int_enbl_reg, int_enbl_next;
wire [BRAM_ADDR_WIDTH-1:0] sum_cntr_wire;
wire int_comp_wire, int_tlast_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_data_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_addr_reg <= int_addr_next;
int_data_reg <= cfg_data;
int_enbl_reg <= int_enbl_next;
end
end
assign sum_cntr_wire = int_addr_reg + 1'b1;
assign int_comp_wire = int_addr_reg < int_data_reg;
assign int_tlast_wire = ~int_comp_wire;
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS
always @*
begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_enbl_reg & int_comp_wire)
begin
int_addr_next = sum_cntr_wire;
end
if(m_axis_tready & int_enbl_reg & int_tlast_wire)
begin
int_addr_next = {(BRAM_ADDR_WIDTH){1'b0}};
end
end
end
else
begin : STOP
always @*
begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_enbl_reg & int_comp_wire)
begin
int_addr_next = sum_cntr_wire;
end
if(m_axis_tready & int_enbl_reg & int_tlast_wire)
begin
int_enbl_next = 1'b0;
end
end
end
endgenerate
assign sts_data = int_addr_reg;
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = int_enbl_reg;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready & int_enbl_reg ? int_addr_next : int_addr_reg;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tb_cmd_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:13 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: STAN
//Design Name: PRBS_Generator
//Purpose: This PRBS is using one to many feedback mechanism because it always
// has a single level XOR(XNOR) for feedback. The TAP is chosen from the table
// that listed in xapp052. The TAPS position can be defined in parameter
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module tg_prbs_gen #
(
parameter PRBS_WIDTH = 64, // // "SEQUENTIAL_BURST"
parameter START_ADDR = 32'h00000000,
parameter DMODE = "READ",
parameter PRBS_OFFSET = 0,
parameter [PRBS_WIDTH-1:0] TAPS= 32'h80200003 //32'b10000000_00100000_00000000_00000011// [31,21,1,0]
// 16 taps: [15,14,12,3] : 16'b11010000_00001000
// 64 taps: [63,62,60,59]: {{8'b11011000}, {56'b0}}
)
(
input clk_i,
input clk_en,
input rst,
// input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH-1:0] prbs_seed_i,
output initialize_done,
output [PRBS_WIDTH-1:0] prbs_o, // generated address
output reg [3:0] prbs_shift_value,
output [31:0] ReSeedcounter_o
);
wire prbs_seed_ld;
reg [PRBS_WIDTH - 1:0] Next_LFSR_Reg;
reg [PRBS_WIDTH - 1:0] LFSR_Reg;
reg [PRBS_WIDTH-1:0] counterA;
reg Bits0_9_zero, Feedback;
integer i;
reg [PRBS_WIDTH - 1:0] ReSeedcounter;
reg [10:0] freerun_counters;
reg init_setup;
wire prbs_clk_en1;
wire prbs_clk_en2;
always @ (posedge clk_i)
begin
if (rst)
freerun_counters <= 'b0;
else if (freerun_counters <= 128 || init_setup)
freerun_counters <= freerun_counters + 1'b1;
end
always @ (posedge clk_i)
begin
if (rst)
counterA <= 'b0;
// else if (clk_en || init_setup || )
else if (prbs_clk_en1)
counterA <= counterA + 1'b1;
end
assign initialize_done = ~init_setup;
always @ (posedge clk_i)
begin
if (rst)
init_setup <= 'b0;
else if ( freerun_counters <= PRBS_OFFSET + 255 )
init_setup <= 1'b1;
else
init_setup <= 1'b0;
end
/*always @ (posedge clk_i)
begin
if (rst)
prbs_shift_value <= 'b0;
else if (freerun_counters == PRBS_OFFSET + 4 )
prbs_shift_value <= LFSR_Reg[3:0];
end
*/
assign ReSeedcounter_o = {{(32-PRBS_WIDTH){1'b0}},ReSeedcounter};
always @ (posedge clk_i)
begin
if (rst)
ReSeedcounter <= 'b0;
else if (prbs_clk_en1)
if (ReSeedcounter == {PRBS_WIDTH {1'b1}})
ReSeedcounter <= 'b0;
else
ReSeedcounter <= ReSeedcounter + 1'b1;
end
assign prbs_clk_en1 = clk_en | init_setup ;
assign prbs_clk_en2 = clk_en | init_setup ;
always @ (posedge clk_i)
begin
if (rst ) begin
// add a fixed non zero value to prevent to load a zero value to the LFSR.
LFSR_Reg[3:0] <= prbs_seed_i[3:0] | 4'h5;
LFSR_Reg[PRBS_WIDTH-1:4] <= prbs_seed_i[PRBS_WIDTH-1:4];
// LFSR_Reg <= prbs_seed_i;
end
else if (prbs_clk_en2) begin
// if ( PRBS_OFFSET == 0)
// $display("prbs_value = 0x%h",LFSR_Reg);
LFSR_Reg <= Next_LFSR_Reg;
prbs_shift_value <= {prbs_shift_value[2:0],LFSR_Reg[PRBS_WIDTH-1]};
end
end
always @ (LFSR_Reg)
begin :LFSR_Feedback
Bits0_9_zero = ~| LFSR_Reg[PRBS_WIDTH-2:0];
Feedback = LFSR_Reg[PRBS_WIDTH-1]^Bits0_9_zero;
// Feedback = LFSR_Reg[PRBS_WIDTH-1] ;
// for (i = 1; i <= PRBS_WIDTH - 1; i = i+1)
for (i = PRBS_WIDTH - 1; i >= 1 ; i = i-1)
if (TAPS[i - 1] == 1)
Next_LFSR_Reg[i]= LFSR_Reg[i-1] ^ Feedback ;
else
Next_LFSR_Reg[i] = LFSR_Reg[i-1];
Next_LFSR_Reg[0] = Feedback ;//LFSR_Reg[PRBS_WIDTH-1];// always use the last stage for feedback
end
assign prbs_o = LFSR_Reg;
endmodule
|
// Raster_Laser_Projector_X_Axis_Subsystem.v
// Generated using ACDS version 16.1 200
`timescale 1 ps / 1 ps
module Raster_Laser_Projector_X_Axis_Subsystem (
input wire clk_clk, // clk.clk
input wire hsync_reset_reset_n, // hsync_reset.reset_n
input wire hsync_target_clk, // hsync_target.clk
input wire reset_reset_n // reset.reset_n
);
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> PI_Controller_0:reset
PI_Controller pi_controller_0 (
.clk (clk_clk), // clock.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.control (), // control_out.ctrl
.error () // error.error
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds_2 #(
// Range = 8-24
parameter DDS_DW = 16,
// Range = 8-24
parameter PHASE_DW = 16,
// Set 1 for CORDIC or 2 for Polynomial
parameter DDS_TYPE = 1,
// Range = 8-24
parameter CORDIC_DW = 16,
// Range = 8-24 ( make sure CORDIC_PHASE_DW < CORDIC_DW)
parameter CORDIC_PHASE_DW = 16) (
// interface
input clk,
input dds_format,
input [PHASE_DW-1:0] dds_phase_0,
input [ 15:0] dds_scale_0,
input [PHASE_DW-1:0] dds_phase_1,
input [ 15:0] dds_scale_1,
output [ DDS_DW-1:0] dds_data);
// Local parameters
localparam CORDIC = 1;
localparam POLYNOMIAL = 2;
// The width for Polynomial DDS is fixed (16)
localparam DDS_D_DW = (DDS_TYPE == CORDIC) ? CORDIC_DW : 16;
localparam DDS_P_DW = (DDS_TYPE == CORDIC) ? CORDIC_PHASE_DW : 16;
// concatenation or truncation width
localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW);
// internal registers
reg [ DDS_DW-1:0] dds_data_width = 0;
reg [DDS_D_DW-1:0] dds_data_rownd = 0;
reg [DDS_D_DW-1:0] dds_data_int = 0;
reg [ 15:0] dds_scale_0_d = 0;
reg [ 15:0] dds_scale_1_d = 0;
reg [ DDS_DW-1:0] dds_data_out = 0;
// internal signals
wire [DDS_D_DW-1:0] dds_data_0_s;
wire [DDS_D_DW-1:0] dds_data_1_s;
wire [DDS_P_DW-1:0] dds_phase_0_s;
wire [DDS_P_DW-1:0] dds_phase_1_s;
generate
// dds channel output
assign dds_data = dds_data_out;
// output data format
always @(posedge clk) begin
dds_data_out[DDS_DW-1] <= dds_data_width[DDS_DW-1] ^ dds_format;
dds_data_out[DDS_DW-2: 0] <= dds_data_width[DDS_DW-2: 0];
end
// set desired data width
always @(posedge clk) begin
if (DDS_DW < DDS_D_DW) begin // truncation
// fair rownding
dds_data_rownd <= dds_data_int + {(C_T_WIDTH){dds_data_int[DDS_D_DW-1]}};
dds_data_width <= dds_data_rownd[DDS_D_DW-1:DDS_D_DW-DDS_DW];
end else begin // concatenation
dds_data_width <= dds_data_int << C_T_WIDTH;
end
end
// dual tone
always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s;
end
always @(posedge clk) begin
dds_scale_0_d <= dds_scale_0;
dds_scale_1_d <= dds_scale_1;
end
// phase
if (DDS_P_DW > PHASE_DW) begin
assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}};
assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}};
end else begin
assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW];
end
// dds-1
ad_dds_1 #(
.DDS_TYPE(DDS_TYPE),
.DDS_D_DW(DDS_D_DW),
.DDS_P_DW(DDS_P_DW))
i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0_s),
.scale (dds_scale_0_d),
.dds_data (dds_data_0_s));
// dds-2
ad_dds_1 #(
.DDS_TYPE(DDS_TYPE),
.DDS_D_DW(DDS_D_DW),
.DDS_P_DW(DDS_P_DW))
i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1_s),
.scale (dds_scale_1_d),
.dds_data (dds_data_1_s));
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
module quick_spi_hard_le_lsb_testbench;
reg clk;
reg rst_n;
wire end_of_transaction;
wire[7:0] incoming_data;
reg[15:0] outgoing_data;
wire mosi;
reg miso;
wire sclk;
wire[1:0] ss_n;
reg enable;
reg start_transaction;
reg operation;
integer sclk_toggle_count;
reg[8:0] incoming_data_buffer;
reg spi_clock_phase;
initial begin
clk <= 1'b0;
rst_n <= 1'b0;
rst_n <= #50 1'b1;
outgoing_data <= {8'b11001100, 8'b10000010};
end
always @ (posedge clk)
begin
if(!rst_n)
begin
outgoing_data <= {8'b11001100, 8'b10000010};
enable <= 1'b1;
start_transaction <= 1'b1;
operation <= 1'b0;
miso <= 1'b0;
sclk_toggle_count <= 0;
incoming_data_buffer <= {8'b10010101, 1'b1};
spi_clock_phase <= 1'b1;
end
else
begin
if(end_of_transaction)
begin
operation <= ~operation;
sclk_toggle_count <= 0;
spi_clock_phase <= 1'b1;
incoming_data_buffer <= {8'b10010101, 1'b1};
miso <= 1'b0;
end
else
begin
if(sclk_toggle_count > 36)
begin
if(!spi_clock_phase)
begin
miso <= incoming_data_buffer[0];
incoming_data_buffer <= incoming_data_buffer >> 1;
end
end
sclk_toggle_count <= sclk_toggle_count + 1;
spi_clock_phase <= ~spi_clock_phase;
end
end
end
quick_spi_hard #
(
.BYTES_ORDER(0), // little endian,
.BITS_ORDER(0) // LSB First
)
spi
(
.clk(clk),
.reset_n(rst_n),
.enable(enable),
.start_transaction(start_transaction),
.slave(2'b01),
.operation(operation),
.end_of_transaction(end_of_transaction),
.incoming_data(incoming_data),
.outgoing_data(outgoing_data),
.mosi(mosi),
.miso(miso),
.sclk(sclk),
.ss_n(ss_n)
);
always #25 clk <= ~clk;
endmodule
|
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr1;
reg [width:0] temp_expr2;
reg r_reset_n;
reg fire_2state;
wire fire_2state_comb;
always @(last_test_expr or test_expr or `OVL_RESET_SIGNAL or r_reset_n)begin
if(`OVL_RESET_SIGNAL == 1'b0 || r_reset_n)begin
temp_expr1 = {(width+1){1'b0}};
temp_expr2 = {(width+1){1'b0}};
end
else begin
temp_expr1 = {1'b0,last_test_expr} - {1'b0,test_expr};
temp_expr2 = {1'b0,test_expr} - {1'b0,last_test_expr};
end
end
// assign fire_2state
always @(posedge clk) begin
fire_2state <= 1'b0;
if(`OVL_RESET_SIGNAL != 1'b0)
if(r_reset_n && (last_test_expr != test_expr))
// 2's complement result
if(!((temp_expr1 >= min && temp_expr1 `LTEQ max) || (temp_expr2 >= min && temp_expr2 `LTEQ max)))
fire_2state <= 1'b1;
end
// assign r_reset_n, the previous value of reset_n
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b0)
r_reset_n <= `OVL_RESET_SIGNAL;
else
r_reset_n <= 0;
// assign last_test_expr, the previous value of test_expr
always @(posedge clk)
if (`OVL_RESET_SIGNAL != 1'b0)
last_test_expr <= test_expr;
else
last_test_expr <= {width{1'b0}};
assign fire_2state_comb = `OVL_RESET_SIGNAL & enable & r_reset_n & (last_test_expr != test_expr) & !((temp_expr1 >= min && temp_expr1 `LTEQ max) | (temp_expr2 >= min && temp_expr2 `LTEQ max));
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_one_cold (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 32;
parameter inactive = `OVL_INACTIVE_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_ONE_COLD";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_one_cold_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_one_cold_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_one_cold_psl_logic.v"
`else
`endmodule // ovl_one_cold
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_2_V
`define SKY130_FD_SC_LP__A21OI_2_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_2_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes 'success' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* 'success' is not available until the next clock cycle.
*
* Prioritised inputs
* ==================
*
* [priority_support = 0 | 1]
*
* Input requested are prioritized by associated 'req_priority' input,
* may be anything from a single bit to N-bits wide.
*
* e.g. for 16 priority levels:
*
* parameter priority_support = 1;
* parameter type priority_type = bit unsigned [3:0];
*
* Note: The priority input is ignored if the associated request is
* not asserted.
*
*/
//#################################
// NOT IMPLEMENTED YET:
//
// - parameter GRANT_HOLD
// don't update matrix state until request
// assoc. with current grant is released
// - winning request will hold grant for as long as it is asserted
//
// - parameter PRIORITIZE first F inputs -
// inputs 0..F are priority inputs
// input 0 will be granted if requested
// input 1 will be granted (if input 0 is not asserted)
// ..etc to input F
//
// weighted arbiter,....
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
input [size-1:0] request;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
assign req=request;
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state <= '1; //-1;
next_state<='1; //-1;
end else begin
// **************************************************
// Multistage Arbiter with Late Success Notification (multistage==2)
// **************************************************
if (multistage==2) begin
update<=|req;
if (|req) begin
// This 'next_state' will only be used on next clock cycle if
// 'success' is asserted
next_state <= new_state;
end
if (update) begin
current_state <= state;
end
end else begin
// ************************************
// Multistage Arbiter (multistage==1)
// ************************************
// check request was ultimately successful before updating arbiter state
// we know about success before the next clock cycle.
if ((multistage==1)&!success) begin
// request was not ultimately successful, don't update priorities
end else begin
// **********************************
// Basic Arbiter (multistage==0)
// **********************************
// Update state whenever at least one request has been made
if (|req) begin
current_state<=new_state;
end
end
end
end
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : ex_stage.v
-- DESCRIPTION : EXXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module ex_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
input wire int_detect, // èÝo
/********** tH[fBO **********/
output wire [`WordDataBus] fwd_data, // tH[fBOf[^
/********** ID/EXpCvCWX^ **********/
input wire [`WordAddrBus] id_pc, // vOJE^
input wire id_en, // pCvCf[^ÌLø
input wire [`AluOpBus] id_alu_op, // ALUIy[V
input wire [`WordDataBus] id_alu_in_0, // ALUüÍ 0
input wire [`WordDataBus] id_alu_in_1, // ALUüÍ 1
input wire id_br_flag, // ªòtO
input wire [`MemOpBus] id_mem_op, // Iy[V
input wire [`WordDataBus] id_mem_wr_data, // «Ýf[^
input wire [`CtrlOpBus] id_ctrl_op, // §äWX^Iy[V
input wire [`RegAddrBus] id_dst_addr, // ÄpWX^«ÝAhX
input wire id_gpr_we_, // ÄpWX^«ÝLø
input wire [`IsaExpBus] id_exp_code, // áOR[h
/********** EX/MEMpCvCWX^ **********/
output wire [`WordAddrBus] ex_pc, // vOJE^
output wire ex_en, // pCvCf[^ÌLø
output wire ex_br_flag, // ªòtO
output wire [`MemOpBus] ex_mem_op, // Iy[V
output wire [`WordDataBus] ex_mem_wr_data, // «Ýf[^
output wire [`CtrlOpBus] ex_ctrl_op, // §äWX^Iy[V
output wire [`RegAddrBus] ex_dst_addr, // ÄpWX^«ÝAhX
output wire ex_gpr_we_, // ÄpWX^«ÝLø
output wire [`IsaExpBus] ex_exp_code, // áOR[h
output wire [`WordDataBus] ex_out // Ê
);
/********** ALUÌoÍ **********/
wire [`WordDataBus] alu_out; // ZÊ
wire alu_of; // I[ot[
/********** ZÊÌtH[fBO **********/
assign fwd_data = alu_out;
/********** ALU **********/
alu alu (
.in_0 (id_alu_in_0), // üÍ 0
.in_1 (id_alu_in_1), // üÍ 1
.op (id_alu_op), // Iy[V
.out (alu_out), // oÍ
.of (alu_of) // I[ot[
);
/********** pCvCWX^ **********/
ex_reg ex_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** ALUÌoÍ **********/
.alu_out (alu_out), // ZÊ
.alu_of (alu_of), // I[ot[
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
.int_detect (int_detect), // èÝo
/********** ID/EXpCvCWX^ **********/
.id_pc (id_pc), // vOJE^
.id_en (id_en), // pCvCf[^ÌLø
.id_br_flag (id_br_flag), // ªòtO
.id_mem_op (id_mem_op), // Iy[V
.id_mem_wr_data (id_mem_wr_data), // «Ýf[^
.id_ctrl_op (id_ctrl_op), // §äWX^Iy[V
.id_dst_addr (id_dst_addr), // ÄpWX^«ÝAhX
.id_gpr_we_ (id_gpr_we_), // ÄpWX^«ÝLø
.id_exp_code (id_exp_code), // áOR[h
/********** EX/MEMpCvCWX^ **********/
.ex_pc (ex_pc), // vOJE^
.ex_en (ex_en), // pCvCf[^ÌLø
.ex_br_flag (ex_br_flag), // ªòtO
.ex_mem_op (ex_mem_op), // Iy[V
.ex_mem_wr_data (ex_mem_wr_data), // «Ýf[^
.ex_ctrl_op (ex_ctrl_op), // §äWX^Iy[V
.ex_dst_addr (ex_dst_addr), // ÄpWX^«ÝAhX
.ex_gpr_we_ (ex_gpr_we_), // ÄpWX^«ÝLø
.ex_exp_code (ex_exp_code), // áOR[h
.ex_out (ex_out) // Ê
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_8_V
`define SKY130_FD_SC_LP__EBUFN_8_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_8_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 15
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_xbar_3,axi_crossbar_v2_1_15_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_1_xbar_3,axi_crossbar_v2_1_15_axi_crossbar,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000c40000000000000000000000,C_M_AXI_ADDR_WIDTH=0x0000000d0000001d,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_\
WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_M_AXI_READ_CONNECTIVITY=0xFFFFFFFFFFFFFFFF,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x00000000,C_S_AXI_WRITE_ACCEPTANCE=0x00000002,C_S_AXI_READ_ACCEPTANCE=0x00000002,C_M_AXI_WRITE_ISSUING=0x0000000200000008,C_M_AXI_READ_ISSUING=0x0000000200000008,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000,C_\
CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_3 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [63:0] [127:64]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [7:0] [15:8]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [63:0] [127:64]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H00000000c40000000000000000000000),
.C_M_AXI_ADDR_WIDTH(64'H0000000d0000001d),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000002),
.C_S_AXI_READ_ACCEPTANCE(32'H00000002),
.C_M_AXI_WRITE_ISSUING(64'H0000000200000008),
.C_M_AXI_READ_ISSUING(64'H0000000200000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
`timescale 1ns/1ps
module ip_checksum_ttl
#(parameter DATA_WIDTH = 64)
(
//--- datapath interface
input [DATA_WIDTH-1:0] in_data,
input in_wr,
//--- interface to preprocess
input word_ETH_IP_VER,
input word_IP_LEN_ID,
input word_IP_FRAG_TTL_PROTO,
input word_IP_CHECKSUM_SRC_HI,
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- interface to process
output ip_checksum_vld,
output ip_checksum_is_good,
output ip_hdr_has_options,
output ip_ttl_is_good,
output [7:0] ip_new_ttl,
output [15:0] ip_new_checksum, // new checksum assuming decremented TTL
input rd_checksum,
// misc
input reset,
input clk
);
//---------------------- Wires and regs---------------------------
reg [19:0] checksum_word_0, checksum_word_1;
reg [19:0] in_word_0_0, in_word_0_1, in_word_0_2;
reg [19:0] in_word_1_0, in_word_1_1, in_word_1_2;
wire [19:0] next_sum_0, next_sum_1;
reg [16:0] adjusted_checksum;
reg checksum_done;
wire empty;
reg [7:0] ttl_new;
reg ttl_good;
reg hdr_has_options;
reg add_carry_1, add_carry_2;
//------------------------- Modules-------------------------------
fallthrough_small_fifo #(.WIDTH(27), .MAX_DEPTH_BITS(2))
arp_fifo
(.din ({&checksum_word_0[15:0], adjusted_checksum[15:0], ttl_good, ttl_new, hdr_has_options}), // {IP good, new checksum}
.wr_en (checksum_done), // Write enable
.rd_en (rd_checksum), // Read the next word
.dout ({ip_checksum_is_good, ip_new_checksum, ip_ttl_is_good, ip_new_ttl, ip_hdr_has_options}),
.full (),
.nearly_full (),
.prog_full (),
.empty (empty),
.reset (reset),
.clk (clk)
);
//------------------------- Logic -------------------------------
assign ip_checksum_vld = !empty;
/* MUX the additions to save adder logic */
assign next_sum_0 = in_word_0_0 + in_word_0_1 + in_word_0_2;
assign next_sum_1 = in_word_1_0 + in_word_1_1 + in_word_1_2;
always @(*) begin
in_word_0_0 = {4'h0, in_data[31:16]};
in_word_0_1 = {4'h0, in_data[15:0]};
in_word_0_2 = checksum_word_0;
in_word_1_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_1_1 = {4'h0, in_data[DATA_WIDTH-17:DATA_WIDTH-32]};
in_word_1_2 = checksum_word_1;
if(word_ETH_IP_VER) begin
in_word_0_0 = 20'h0;
in_word_0_2 = 20'h0;
end
if(word_IP_DST_LO) begin
in_word_0_0 = {4'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]};
in_word_0_1 = checksum_word_1;
end
if(add_carry_1 | add_carry_2) begin
in_word_0_0 = 20'h0;
in_word_0_1 = {16'h0, checksum_word_0[19:16]};
in_word_0_2 = {4'h0, checksum_word_0[15:0]};
end
if(word_IP_LEN_ID) begin
in_word_1_2 = 20'h0;
end
end // always @ (*)
// checksum logic. 16bit 1's complement over the IP header.
// --- see RFC1936 for guidance.
// 1's compl add: do a 2's compl add and then add the carry out
// as if it were a carry in.
// Final checksum (computed over the whole header incl checksum)
// is in checksum_a and valid when IP_checksum_valid is 1
// If checksum is good then it should be 0xffff
always @(posedge clk) begin
if(reset) begin
checksum_word_0 <= 20'h0; // does the addition for the low 32 bits
checksum_word_1 <= 20'h0; // does the addition for the high 32 bits
adjusted_checksum <= 17'h0; // calculates the new chksum
checksum_done <= 0;
add_carry_1 <= 0;
add_carry_2 <= 0;
ttl_new <= 0;
ttl_good <= 0;
hdr_has_options <= 0;
end
else begin
/* make sure the version is correct and there are no options */
if(word_ETH_IP_VER) begin
hdr_has_options <= (in_data[15:8]!=8'h45);
end
if(word_IP_FRAG_TTL_PROTO) begin
ttl_new <= (in_data[15:8]==8'h0) ? 8'h0 : in_data[15:8] - 1'b1;
ttl_good <= (in_data[15:8] > 8'h1);
end
if(word_ETH_IP_VER | word_IP_FRAG_TTL_PROTO | word_IP_SRC_DST |
word_IP_DST_LO | add_carry_1 | add_carry_2) begin
checksum_word_0 <= next_sum_0;
end
if(word_IP_LEN_ID | word_IP_CHECKSUM_SRC_HI) begin
checksum_word_1 <= next_sum_1;
end
// see RFC 1141
if(word_IP_CHECKSUM_SRC_HI) begin
adjusted_checksum <= {1'h0, in_data[DATA_WIDTH-1:DATA_WIDTH-16]} + 17'h0100; // adjust for the decrement in TTL
end
if(word_IP_DST_LO) begin
adjusted_checksum <= {1'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];
add_carry_1 <= 1;
end
else begin
add_carry_1 <= 0;
end
if(add_carry_1) begin
add_carry_2 <= 1;
end
else begin
add_carry_2 <= 0;
end
if(add_carry_2) begin
checksum_done <= 1;
end
else begin
checksum_done <= 0;
end
// synthesis translate_off
// If we have any carry left in top 4 bits then algorithm is wrong
if (checksum_done && checksum_word_0[19:16] != 4'h0) begin
$display("%t %m ERROR: top 4 bits of checksum_word_0 not zero - algo wrong???",
$time);
#100 $stop;
end
// synthesis translate_on
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // IP_checksum
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="-3000" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 15.1 cbx_altclkbuf 2016:02:01:19:04:59:SJ cbx_altiobuf_bidir 2016:02:01:19:04:59:SJ cbx_altiobuf_in 2016:02:01:19:04:59:SJ cbx_altiobuf_out 2016:02:01:19:04:59:SJ cbx_altpll 2016:02:01:19:04:59:SJ cbx_altpll_avalon 2016:02:01:19:04:59:SJ cbx_cycloneii 2016:02:01:19:04:59:SJ cbx_lpm_add_sub 2016:02:01:19:04:59:SJ cbx_lpm_compare 2016:02:01:19:04:59:SJ cbx_lpm_counter 2016:02:01:19:04:59:SJ cbx_lpm_decode 2016:02:01:19:04:59:SJ cbx_lpm_mux 2016:02:01:19:04:59:SJ cbx_lpm_shiftreg 2016:02:01:19:04:59:SJ cbx_mgl 2016:02:01:19:07:00:SJ cbx_nadder 2016:02:01:19:04:59:SJ cbx_stratix 2016:02:01:19:05:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_stratixiii 2016:02:01:19:05:00:SJ cbx_stratixv 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 15.1 cbx_mgl 2016:02:01:19:07:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 15.1 cbx_mgl 2016:02:01:19:07:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module wasca_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //wasca_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
wasca_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //wasca_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="-3000" compensate_clock="CLK0" device_family="MAX10" inclk0_input_frequency=20000 intended_device_family="MAX 10" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 15.1 cbx_altclkbuf 2016:02:01:19:04:59:SJ cbx_altiobuf_bidir 2016:02:01:19:04:59:SJ cbx_altiobuf_in 2016:02:01:19:04:59:SJ cbx_altiobuf_out 2016:02:01:19:04:59:SJ cbx_altpll 2016:02:01:19:04:59:SJ cbx_cycloneii 2016:02:01:19:04:59:SJ cbx_lpm_add_sub 2016:02:01:19:04:59:SJ cbx_lpm_compare 2016:02:01:19:04:59:SJ cbx_lpm_counter 2016:02:01:19:04:59:SJ cbx_lpm_decode 2016:02:01:19:04:59:SJ cbx_lpm_mux 2016:02:01:19:04:59:SJ cbx_mgl 2016:02:01:19:07:00:SJ cbx_nadder 2016:02:01:19:04:59:SJ cbx_stratix 2016:02:01:19:05:00:SJ cbx_stratixii 2016:02:01:19:05:00:SJ cbx_stratixiii 2016:02:01:19:05:00:SJ cbx_stratixv 2016:02:01:19:05:00:SJ cbx_util_mgl 2016:02:01:19:04:59:SJ VERSION_END
//synthesis_resources = fiftyfivenm_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module wasca_altpll_0_altpll_3h92
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
fiftyfivenm_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 1,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 2,
pll7.clk1_phase_shift = "-3000",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //wasca_altpll_0_altpll_3h92
//synthesis_resources = fiftyfivenm_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module wasca_altpll_0
(
address,
areset,
c0,
c1,
clk,
locked,
phasedone,
read,
readdata,
reset,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
input clk;
output locked;
output phasedone;
input read;
output [31:0] readdata;
input reset;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
wasca_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
wasca_altpll_0_altpll_3h92 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //wasca_altpll_0
//VALID FILE
|
//==================================================================================================
// Filename : Testbench_FPUv2_Interface.v
// Created On : 2016-10-31 01:04:01
// Last Modified : 2016-10-31 01:04:11
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
module Testbench_FPU_Mark2();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg begin_operation;
reg ack_operation;
reg [2:0] operation;
//Oper_Start_in signals
reg [W-1:0] Data_1;
reg [W-1:0] Data_2;
reg [1:0] region_flag;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire operation_ready;
wire NaN_flag;
wire [W-1:0] op_result;
// LOS CODIGOS PARA LAS OPERACIONES
localparam [2:0] FPADD = 3'b000,
FPSUB = 3'b001,
FPCOS = 3'b010,
FPSEN = 3'b011,
FPMULT = 3'b100;
// LAS REGIONES DEL ANGULO
localparam [1:0] IoIV1 = 2'b00,
II = 2'b01,
III = 2'b10,
IoIV2 = 2'b11;
localparam [1:0] ROUNDING_MODE_TRUNCT = 2'b00,
ROUNDING_MODE_NEG_INF = 2'b01,
ROUNDING_MODE_POS_INF = 2'b10;
FPU_Interface2 #(
.W(W),
.EW(EW),
.SW(SW),
.SWR(SWR),
.EWR(EWR)
) inst_FPU_Interface (
.clk (clk),
.rst (rst),
.begin_operation (begin_operation),
.ack_operation (ack_operation),
.operation (operation),
.region_flag (region_flag),
.Data_1 (Data_1),
.Data_2 (Data_2),
.r_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.NaN_flag (NaN_flag),
.operation_ready (operation_ready),
.op_result (op_result),
.busy (busy)
);
reg [W-1:0] Array_IN_1 [0:(((2**PERIOD))-1)];
reg [W-1:0] Array_IN_2 [0:(((2**PERIOD))-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
begin_operation = 0;
ack_operation = 0;
Data_1 = 0;
Data_2 = 0;
`ifdef SINGLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
$readmemh("ADD/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/SINGLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
$readmemh("SUB/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/SINGLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
$readmemh("MULT/SINGLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/SINGLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
$readmemh("SIN/SINGLE/input_angles_hex.txt", Array_IN_1);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
$readmemh("COS/SINGLE/input_angles_hex.txt", Array_IN_1);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/SINGLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/SINGLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
`endif
`ifdef DOUBLE
$display("------------------------SUMA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SUMA--------------------------");
operation = FPADD;
$readmemh("ADD/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("ADD/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("ADD/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
$display("------------------------RSTA--------------------------");
$display("------------------------ --------------------------");
$display("------------------------RSTA--------------------------");
operation = FPSUB;
$readmemh("SUB/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("SUB/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SUB/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_PIPE(FileSaveData,(2**PERIOD));
$display("------------------------MULT--------------------------");
$display("------------------------ --------------------------");
$display("------------------------MULT--------------------------");
operation = FPMULT;
$readmemh("MULT/DOUBLE/Hexadecimal_A.txt", Array_IN_1);
$readmemh("MULT/DOUBLE/Hexadecimal_B.txt", Array_IN_2);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("MULT/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
$display("---------------------REGION I or IV--------------------------");
$display("------------------------ --------------------------");
$display("---------------------REGION I or IV-------------------");
region_flag = IoIV1;
$display("------------------------SENO--------------------------");
$display("------------------------ --------------------------");
$display("------------------------SENO--------------------------");
operation = FPSEN;
$readmemh("SIN/DOUBLE/input_angles_hex.txt", Array_IN_1);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("SIN/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
$display("------------------------COS--------------------------");
$display("------------------------ --------------------------");
$display("------------------------COS--------------------------");
operation = FPCOS;
$readmemh("COS/DOUBLE/input_angles_hex.txt", Array_IN_1);
r_mode = ROUNDING_MODE_TRUNCT;
FileSaveData = $fopen("COS/DOUBLE/RMODE_TRUNCATE/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_NEG_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_NEGINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
r_mode = ROUNDING_MODE_POS_INF;
FileSaveData = $fopen("COS/DOUBLE/RMODE_POSINF/ResultadoXilinxFLM.txt","w");
run_Arch2(FileSaveData,(2**PERIOD));
`endif
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
begin_operation = 0;
rst = 0;
#15 rst = 1;
#25 rst = 0;
// begin_operation = 0;
ack_operation = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
#(PERIOD/4) begin_operation = 1;
//Wait for the operation operation_ready
@(posedge operation_ready) begin
#(PERIOD+2);
ack_operation = 1;
#4;
$fwrite(FDataO,"%h\n",op_result);
end
@(negedge clk) begin
ack_operation = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
////////////////////////////TASK FOR THE PIPE ADDER/////////////////
////We need to read in a non-linear fashion, therefore
// we are going to write first the 3 first input operands,
// then, the normal running operation,
// and then the final procedure.
task run_PIPE;
input integer FData1;
input integer Vector_size2;
begin
begin_operation = 0;
rst = 0;
#15 rst = 1;
#25 rst = 0;
//begin_operation = 0;
contador = 0;
@(posedge clk)
begin_operation = 1;
@(posedge clk)
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
contador = contador + 1;
repeat(Vector_size2*2+6) @(posedge clk) begin
#(PERIOD/3);
if(~busy & ~rst) begin
Data_1 = Array_IN_1[contador];
Data_2 = Array_IN_2[contador];
contador = contador + 1;
end
if (operation_ready) begin
$fwrite(FData1,"%h\n",op_result);
end
end
begin_operation = 0;
$fclose(FData1);
end
endtask
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
mulAddRecF16_add (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
wire [16:0] recF16_1 = 'h08000;
mulAddRecFN#(5, 11)
mulAddRecFN(
control, 2'b0, a, recF16_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF32_add (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
wire [32:0] recF32_1 = 33'h080000000;
mulAddRecFN#(8, 24)
mulAddRecFN(
control, 2'b0, a, recF32_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF64_add (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
wire [64:0] recF64_1 = 65'h08000000000000000;
mulAddRecFN#(11, 53)
mulAddRecFN(
control, 2'b0, a, recF64_1, b, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] recF128_1 = 129'h080000000000000000000000000000000;
mulAddRecFN#(15, 113)
mulAddRecFN(
control, 2'b0, a, recF128_1, b, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF16_mul (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
wire [16:0] zeroAddend = {a[16] ^ b[16], 16'b0};
mulAddRecFN#(5, 11)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF32_mul (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
wire [32:0] zeroAddend = {a[32] ^ b[32], 32'b0};
mulAddRecFN#(8, 24)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF64_mul (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
wire [64:0] zeroAddend = {a[64] ^ b[64], 64'b0};
mulAddRecFN#(11, 53)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF128_mul (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
wire [128:0] zeroAddend = {a[128] ^ b[128], 128'b0};
mulAddRecFN#(15, 113)
mulAddRecFN(
control, 2'b0, a, b, zeroAddend, roundingMode, out, exceptionFlags
);
endmodule
module
mulAddRecF16 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [16:0] a,
input [16:0] b,
input [16:0] c,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(5, 11)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF32 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [32:0] a,
input [32:0] b,
input [32:0] c,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(8, 24)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF64 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [64:0] a,
input [64:0] b,
input [64:0] c,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(11, 53)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
module
mulAddRecF128 (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [128:0] a,
input [128:0] b,
input [128:0] c,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
mulAddRecFN#(15, 113)
mulAddRecFN(control, op, a, b, c, roundingMode, out, exceptionFlags);
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "gpio/gpio.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [15:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR
);
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h000f;
localparam GPIO_BASEADDR_DEV1 = 16'h1000;
localparam GPIO_HIGHADDR_DEV1 = 16'h100f;
localparam GPIO_BASEADDR_DEV2 = 16'h2000;
localparam GPIO_HIGHADDR_DEV2 = 16'h200f;
wire [7:0] IO;
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'b0000_1111)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(IO)
);
wire RESETB, TCK, TMS, TDI, TDO;
assign RESETB = IO[0];
assign TCK = IO[1];
assign TMS = IO[2];
assign TDI = IO[3];
assign IO[4] = TDO;
assign IO[7:5] = 0;
wire td_int;
wire [31:0] debug_reg1, debug_reg2;
jtag_tap i_jtag_tap1(.jtag_tms_i(TMS), .jtag_tck_i(TCK), .jtag_trstn_i(1'b1), .jtag_tdi_i(TDI), .jtag_tdo_o(td_int), .debug_reg(debug_reg2));
jtag_tap i_jtag_tap2(.jtag_tms_i(TMS), .jtag_tck_i(TCK), .jtag_trstn_i(1'b1), .jtag_tdi_i(td_int), .jtag_tdo_o(TDO), .debug_reg(debug_reg1));
wire D1_F1;
wire [5:0] D1_F2;
wire [3:0] D1_F3;
wire [20:0] D1_F4;
assign {D1_F4, D1_F3, D1_F2, D1_F1} = debug_reg1;
wire D2_F1;
wire [5:0] D2_F2;
wire [3:0] D2_F3;
wire [20:0] D2_F4;
assign {D2_F4, D2_F3, D2_F2, D2_F1} = debug_reg2;
gpio
#(
.BASEADDR(GPIO_BASEADDR_DEV1),
.HIGHADDR(GPIO_HIGHADDR_DEV1),
.IO_WIDTH(32),
.IO_DIRECTION(32'h00000000)
) i_gpio_dev2
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(debug_reg2)
);
gpio
#(
.BASEADDR(GPIO_BASEADDR_DEV2),
.HIGHADDR(GPIO_HIGHADDR_DEV2),
.IO_WIDTH(32),
.IO_DIRECTION(32'h00000000)
) i_gpio_dev1
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(debug_reg1)
);
initial begin
$dumpfile("jtag_gpio.vcd");
$dumpvars(0);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlymetal6s4s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_BEHAVIORAL_PP_V
|
module sram_ctrl_a(
input clk,
input clr,
input go,
input halt,
output reg we,
output [17:0] sram_addr,
output [2:0] pattern,
output reg en
);
reg[2:0] state;
parameter START = 4'b0000, ADDROUT = 4'b0001, DATAOUT = 4'b0010,
WRITE = 4'b0011, TEST1 = 4'b0100, WAIT_AND_GO = 4'b0101, READ = 4'b0110,
TEST2 = 4'b0111, HALT = 4'b1000;
reg [17:0] addrv;
reg [2:0] patternv;
assign sram_addr = addrv;
assign pattern = patternv;
always @(posedge clk or posedge clr)
begin
if (clr == 1)
begin
state <= START;
addrv = 0;
patternv = 0;
we <= 1;
en <= 0;
end
else
case(state)
START:
begin
we <= 1;
if (go == 1)
begin
addrv = 0;
en <= 1;
state <= ADDROUT;
end
else
state <= START;
end
ADDROUT:
begin
state <= DATAOUT;
we <= 1;
end
DATAOUT:
begin
state <= WRITE;
we <= 0;
end
WRITE:
begin
state <= TEST1;
we <= 1;
end
TEST1:
begin
we <= 1;
if (halt == 1)
state <= HALT;
else
begin
addrv = addrv + 1;
if (addrv == 0)
begin
state <= WAIT_AND_GO;
en <= 0;
end
else
state <= ADDROUT;
end
end
WAIT_AND_GO:
begin
we <= 1;
if (go == 1)
state <= WAIT_AND_GO;
else
state <= READ;
end
READ:
begin
we <= 1;
if (go == 1)
begin
state <= TEST2;
addrv = addrv + 1;
end
else
state <= READ;
end
TEST2:
begin
we <= 1;
if (addrv == 0)
begin
patternv = patternv + 1;
state <= START;
end
else
state <= WAIT_AND_GO;
end
HALT:
begin
state <= HALT;
end
default;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_BEHAVIORAL_V
|
`default_nettype none
`timescale 1ns / 1ps
`include "../src/iserdes_idelay_histogram.v"
`include "../src/idelay_calibrator.v"
`include "../src/error_counter.v"
`include "../src/message_formatter.v"
`include "../src/lfsr.v"
`include "../src/simpleuart.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 5000)
$finish;
// ============================================================================
wire dat_o;
reg dat_i;
always @(*) dat_i <= #1.1 dat_o;
iserdes_idelay_histogram #
(
)
dut
(
.CLK (CLK),
.RST (RST),
.UART_RX (1'b1),
.UART_TX (),
.O (dat_o),
.I (dat_i)
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_gen #
( parameter
CFG_DWIDTH_RATIO = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_REG_GRANT = 0,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_TCCD = 4,
CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT = 1,
CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE = 1,
CFG_ENABLE_BURST_GEN_OUTPUT_REG = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Interface
cfg_type,
cfg_burst_length,
cfg_tccd,
cfg_enable_burst_interrupt,
cfg_enable_burst_terminate,
// Arbiter Interface
arb_do_write,
arb_do_read,
arb_do_burst_chop,
arb_do_burst_terminate,
arb_do_auto_precharge,
arb_do_rmw_correct,
arb_do_rmw_partial,
arb_do_activate,
arb_do_precharge,
arb_do_precharge_all,
arb_do_refresh,
arb_do_self_refresh,
arb_do_power_down,
arb_do_deep_pdown,
arb_do_zq_cal,
arb_do_lmr,
arb_to_chipsel,
arb_to_chip,
arb_to_bank,
arb_to_row,
arb_to_col,
arb_localid,
arb_dataid,
arb_size,
// AFI Interface
bg_do_write_combi,
bg_do_read_combi,
bg_do_burst_chop_combi,
bg_do_burst_terminate_combi,
bg_do_activate_combi,
bg_do_precharge_combi,
bg_to_chip_combi,
bg_effective_size_combi,
bg_interrupt_ready_combi,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_zq_cal,
bg_do_lmr,
bg_to_chipsel,
bg_to_chip,
bg_to_bank,
bg_to_row,
bg_to_col,
bg_doing_write,
bg_doing_read,
bg_rdwr_data_valid,
bg_interrupt_ready,
bg_localid,
bg_dataid,
bg_size,
bg_effective_size
);
localparam AFI_INTF_LOW_PHASE = 0;
localparam AFI_INTF_HIGH_PHASE = 1;
input ctl_clk;
input ctl_reset_n;
// MMR Interface
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_ENABLE_BURST_INTERRUPT - 1 : 0] cfg_enable_burst_interrupt;
input [CFG_PORT_WIDTH_ENABLE_BURST_TERMINATE - 1 : 0] cfg_enable_burst_terminate;
// Arbiter Interface
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_auto_precharge;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_correct;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_rmw_partial;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_precharge_all;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_self_refresh;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_power_down;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_deep_pdown;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_do_zq_cal;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] arb_do_lmr;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] arb_to_chipsel;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] arb_to_chip;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] arb_to_bank;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] arb_to_row;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] arb_to_col;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] arb_localid;
input [CFG_DATA_ID_WIDTH - 1 : 0] arb_dataid;
input [CFG_INT_SIZE_WIDTH - 1 : 0] arb_size;
// AFI Interface
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
output bg_interrupt_ready_combi;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
output [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
output [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
output bg_doing_write;
output bg_doing_read;
output bg_rdwr_data_valid;
output bg_interrupt_ready;
output [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
output [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
output [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// AFI Interface
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] bg_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;
reg bg_doing_write;
reg bg_doing_read;
reg bg_rdwr_data_valid;
reg bg_interrupt_ready;
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
// Burst generation logic
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] int_to_col;
reg [2 : 0] int_col_address;
reg [2 : 0] int_address_left;
reg int_do_row_req;
reg int_do_col_req;
reg int_do_sideband_req;
reg int_do_auto_precharge;
reg int_do_rd_req;
reg int_do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_do_rmw_partial;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] size;
reg [CFG_DATA_ID_WIDTH - 1 : 0] dataid;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] to_col;
reg [2 : 0] col_address;
reg [2 : 0] address_left;
reg do_row_req;
reg do_col_req;
reg do_sideband_req;
reg do_auto_precharge;
reg do_rd_req;
reg do_wr_req;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_chop;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_rmw_partial;
reg doing_auto_precharge;
reg [3 : 0] max_local_burst_size;
reg [3 : 0] max_local_burst_size_divide_2;
reg [3 : 0] max_local_burst_size_minus_2;
reg [3 : 0] max_local_burst_size_divide_2_and_minus_2;
reg [3 : 0] burst_left;
reg current_valid;
reg delayed_valid;
reg combined_valid;
reg [3 : 0] max_burst_left;
reg delayed_doing;
reg last_is_write;
reg last_is_read;
// Burst interrupt logic
reg [CFG_PORT_WIDTH_TCCD - 2 : 0] n_prefetch;
reg int_allow_interrupt;
reg int_interrupt_enable_ready;
reg int_interrupt_disable_ready;
reg int_interrupt_gate;
// Burst terminate logic
reg int_allow_terminate;
reg int_do_burst_terminate;
reg int_do_burst_terminate_r;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_do_req;
reg doing_burst_terminate;
reg terminate_doing;
// RMW Info
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] delayed_do_rmw_partial;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_correct;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] combined_do_rmw_partial;
// Data ID
reg [CFG_DATA_ID_WIDTH - 1 : 0] delayed_dataid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] combined_dataid;
// Chip address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] rdwr_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] rdwr_to_chip;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] modified_to_chipsel;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] modified_to_chip;
// Column address
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] modified_to_col;
// Common
wire zero = 1'b0;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge_combi;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip_combi;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size_combi;
reg bg_interrupt_ready_combi;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] do_burst_terminate;
reg doing_write;
reg doing_read;
reg rdwr_data_valid;
reg interrupt_ready;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] effective_size;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Outputs
//
//--------------------------------------------------------------------------------------------------------
// Do signals
generate
if (CFG_ENABLE_BURST_GEN_OUTPUT_REG == 1)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (! ctl_reset_n)
begin
bg_do_write <= 0;
bg_do_read <= 0;
bg_do_auto_precharge <= 0;
bg_do_rmw_correct <= 0;
bg_do_rmw_partial <= 0;
bg_do_activate <= 0;
bg_do_precharge <= 0;
bg_do_precharge_all <= 0;
bg_do_refresh <= 0;
bg_do_self_refresh <= 0;
bg_do_power_down <= 0;
bg_do_deep_pdown <= 0;
bg_do_zq_cal <= 0;
bg_do_lmr <= 0;
bg_to_chip <= 0;
bg_to_chipsel <= 0;
bg_to_bank <= 0;
bg_to_row <= 0;
bg_localid <= 0;
bg_size <= 0;
bg_to_col <= 0;
bg_dataid <= 0;
bg_do_burst_chop <= 0;
bg_do_burst_terminate <= 0;
bg_doing_write <= 0;
bg_doing_read <= 0;
bg_rdwr_data_valid <= 0;
bg_interrupt_ready <= 0;
bg_effective_size <= 0;
end
else
begin
bg_do_write <= arb_do_write;
bg_do_read <= arb_do_read;
bg_do_auto_precharge <= arb_do_auto_precharge;
bg_do_rmw_correct <= combined_do_rmw_correct;
bg_do_rmw_partial <= combined_do_rmw_partial;
bg_do_activate <= arb_do_activate;
bg_do_precharge <= arb_do_precharge;
bg_do_precharge_all <= arb_do_precharge_all;
bg_do_refresh <= arb_do_refresh;
bg_do_self_refresh <= arb_do_self_refresh;
bg_do_power_down <= arb_do_power_down;
bg_do_deep_pdown <= arb_do_deep_pdown;
bg_do_zq_cal <= arb_do_zq_cal;
bg_do_lmr <= arb_do_lmr;
bg_to_chip <= modified_to_chip;
bg_to_chipsel <= modified_to_chipsel;
bg_to_bank <= arb_to_bank;
bg_to_row <= arb_to_row;
bg_localid <= arb_localid;
bg_size <= arb_size;
bg_to_col <= modified_to_col;
bg_dataid <= combined_dataid;
bg_do_burst_chop <= do_burst_chop;
bg_do_burst_terminate <= do_burst_terminate;
bg_doing_write <= doing_write;
bg_doing_read <= doing_read;
bg_rdwr_data_valid <= rdwr_data_valid;
bg_interrupt_ready <= interrupt_ready;
bg_effective_size <= effective_size;
end
end
end
else
begin
always @ (*)
begin
bg_do_write = arb_do_write;
bg_do_read = arb_do_read;
bg_do_auto_precharge = arb_do_auto_precharge;
bg_do_activate = arb_do_activate;
bg_do_precharge = arb_do_precharge;
bg_do_precharge_all = arb_do_precharge_all;
bg_do_refresh = arb_do_refresh;
bg_do_self_refresh = arb_do_self_refresh;
bg_do_power_down = arb_do_power_down;
bg_do_deep_pdown = arb_do_deep_pdown;
bg_do_zq_cal = arb_do_zq_cal;
bg_do_lmr = arb_do_lmr;
bg_to_chip = modified_to_chip;
bg_to_chipsel = modified_to_chipsel;
bg_to_bank = arb_to_bank;
bg_to_row = arb_to_row;
bg_localid = arb_localid;
bg_size = arb_size;
bg_do_burst_chop = do_burst_chop;
bg_do_burst_terminate = do_burst_terminate;
bg_doing_write = doing_write;
bg_doing_read = doing_read;
bg_rdwr_data_valid = rdwr_data_valid;
bg_interrupt_ready = interrupt_ready;
bg_effective_size = effective_size;
end
// To column
always @ (*)
begin
bg_to_col = modified_to_col;
end
// RMW info
always @ (*)
begin
bg_do_rmw_correct = combined_do_rmw_correct;
bg_do_rmw_partial = combined_do_rmw_partial;
end
// Data ID
always @ (*)
begin
bg_dataid = combined_dataid;
end
end
endgenerate
// Regardless whether CFG_ENABLE_BURST_GEN_OUTPUT_REG is 1/0
// following signals (inputs to rank_timer) need to be combi
always @ (*)
begin
bg_do_write_combi = arb_do_write;
bg_do_read_combi = arb_do_read;
bg_do_burst_chop_combi = do_burst_chop;
bg_do_burst_terminate_combi = do_burst_terminate;
bg_do_activate_combi = arb_do_activate;
bg_do_precharge_combi = arb_do_precharge;
bg_to_chip_combi = modified_to_chip;
bg_effective_size_combi = effective_size;
bg_interrupt_ready_combi = interrupt_ready;
end
generate
genvar i;
for (i = 0;i < CFG_AFI_INTF_PHASE_NUM;i = i + 1)
begin : afi_phase_loop
// Registered chip/chipsel address for read/write request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_to_chip [(i + 1) * CFG_MEM_IF_CHIP - 1 : i * CFG_MEM_IF_CHIP ] <= 0;
rdwr_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH] <= 0;
end
else
begin
if (arb_do_read[i] || arb_do_write[i])
begin
rdwr_to_chip [(i + 1) * CFG_MEM_IF_CHIP - 1 : i * CFG_MEM_IF_CHIP ] <= arb_to_chip [(i + 1) * CFG_MEM_IF_CHIP - 1 : i * CFG_MEM_IF_CHIP ];
rdwr_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH] <= arb_to_chipsel [(i + 1) * CFG_MEM_IF_CS_WIDTH - 1 : i * CFG_MEM_IF_CS_WIDTH];
end
end
end
end
endgenerate
always @ (*)
begin
if (do_burst_terminate)
begin
if (CFG_DWIDTH_RATIO != 2)
begin
modified_to_chip = rdwr_to_chip | arb_to_chip;
end
else
begin
modified_to_chip = rdwr_to_chip;
end
modified_to_chipsel = rdwr_to_chipsel;
end
else
begin
modified_to_chip = arb_to_chip;
modified_to_chipsel = arb_to_chipsel;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Outputs
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Generation Logic
//
// Doing read/write signal will indicate the "FULL" burst duration of a request
// Data Valid signal will indicate "VALID" burst duration of a request
//
// Example: Without address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Input Size ----X 1 X-----------------X 2 X-----------------X 3 X-----------------X 4 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal ____/ 1 \_________________/ 1 X 2 \___________/ 1 X 2 X 3 \_____/ 1 X 2 X 3 X 4 \_____
//
// Example: With address shifting (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 1 X-----------------X 2 X-----------------X 2 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 2 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 0 X-----------------------
// Output Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Output Valid Signal __________/ 1 \_______________________/ 1 \_________________/ 1 X 2 \_____
// <-----> <-----------> <----------->
// Offset Offset Offset
//
// Example: Burst chop for DDR3 only (maximum local burst size of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Input Request ----X W R X-----------------X W R X-----------------X W R X-----------------X W R X-----------------------
// Input Column Address [2 : 0] ----X 0 X-----------------X 1 X-----------------X 2 X-----------------X 3 X-----------------------
// Input Size ----X 1 X-----------------X 1 X-----------------X 1 X-----------------X 1 X-----------------------
//
// Output Column Address [2 : 0] ----X 0 X-----------------X 0 X-----------------X 2 X-----------------X 2 X-----------------------
// Output Burst Chop Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Output Doing Signal ____/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \___________/ 1 X 2 \_________________
// Output Valid Signal ____/ 1 \_______________________/ 1 \___________/ 1 \_______________________/ 1 \_________________
// <-----> <----->
// Offset Offset
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Maximum local burst size
//----------------------------------------------------------------------------------------------------
// Calculate maximum local burst size
// based on burst length and controller rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size_divide_2 <= 0;
max_local_burst_size_minus_2 <= 0;
max_local_burst_size_divide_2_and_minus_2 <= 0;
end
else
begin
max_local_burst_size_divide_2 <= max_local_burst_size / 2;
max_local_burst_size_minus_2 <= max_local_burst_size - 2'd2;
max_local_burst_size_divide_2_and_minus_2 <= (max_local_burst_size / 2) - 2'd2;
end
end
//----------------------------------------------------------------------------------------------------
// Address shifting
//----------------------------------------------------------------------------------------------------
// Column address
// we only require address [2 - 0] because the maximum supported
// local burst count is 8 which is BL of 16 in full rate
// we only take low phase of arb_to_col address because high and low phase is identical
always @ (*)
begin
int_col_address = 0;
if (cfg_type == `MMR_TYPE_DDR3 && do_burst_chop) // DDR3 and burst chop, we don't want address shifting during burst chop
begin
if (max_local_burst_size [2]) // max local burst of 4
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else
// max local burst of 1, 2 - address shifting in burst chop is not possible
// max local burst of 8 - not supported in DDR3, there is no BL 16 support in DDR3
int_col_address = 0;
end
else if (max_local_burst_size [0]) // max local burst of 1
int_col_address = 0;
else if (max_local_burst_size [1]) // max local burst of 2
int_col_address [0 ] = arb_to_col [(CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [2]) // max local burst of 4
int_col_address [1 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 1 : (CFG_DWIDTH_RATIO / 2)];
else if (max_local_burst_size [3]) // max local burst of 8
int_col_address [2 : 0] = arb_to_col [(CFG_DWIDTH_RATIO / 2) + 2 : (CFG_DWIDTH_RATIO / 2)];
end
always @ (*)
begin
col_address = int_col_address;
end
//----------------------------------------------------------------------------------------------------
// Command Info
//----------------------------------------------------------------------------------------------------
// To col address
always @ (*)
begin
int_to_col = arb_to_col;
end
// Row request
always @ (*)
begin
int_do_row_req = (|arb_do_activate) | (|arb_do_precharge);
end
// Column request
always @ (*)
begin
int_do_col_req = (|arb_do_write) | (|arb_do_read);
end
// Sideband request
always @ (*)
begin
int_do_sideband_req = (|arb_do_precharge_all) | (|arb_do_refresh) | (|arb_do_self_refresh) | (|arb_do_power_down) | (|arb_do_deep_pdown) | (|arb_do_zq_cal) | (|arb_do_lmr);
end
// Read and write request
always @ (*)
begin
int_do_rd_req = |arb_do_read;
int_do_wr_req = |arb_do_write;
end
// Auto precharge
always @ (*)
begin
int_do_auto_precharge = |arb_do_auto_precharge;
end
// Burst chop
always @ (*)
begin
int_do_burst_chop = arb_do_burst_chop;
end
// RMW info
always @ (*)
begin
int_do_rmw_correct = arb_do_rmw_correct;
int_do_rmw_partial = arb_do_rmw_partial;
end
// Other Info: size, dataid
always @ (*)
begin
int_size = arb_size;
int_dataid = arb_dataid;
end
always @ (*)
begin
size = int_size;
dataid = int_dataid;
to_col = int_to_col;
do_row_req = int_do_row_req;
do_col_req = int_do_col_req;
do_sideband_req = int_do_sideband_req;
do_rd_req = int_do_rd_req;
do_wr_req = int_do_wr_req;
do_auto_precharge = int_do_auto_precharge;
do_burst_chop = int_do_burst_chop;
do_rmw_correct = int_do_rmw_correct;
do_rmw_partial = int_do_rmw_partial;
end
// Keep track of auto-precharge signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_auto_precharge <= 1'b0;
end
else
begin
if (do_col_req && do_auto_precharge)
begin
doing_auto_precharge <= 1'b1;
end
else if (do_col_req && !do_auto_precharge)
begin
doing_auto_precharge <= 1'b0;
end
end
end
//----------------------------------------------------------------------------------------------------
// Address Count
//----------------------------------------------------------------------------------------------------
// Address counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
address_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address > 1'b1)
address_left <= col_address - 2'd2;
else
address_left <= 0;
end
else if (address_left != 0)
address_left <= address_left - 1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Valid Signal
//----------------------------------------------------------------------------------------------------
// Burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (col_address == 0) // no shifting required
begin
if (size > 1'b1)
burst_left <= size - 2'd2;
else
burst_left <= 0;
end
else if (col_address == 1'b1) // require shifting
begin
burst_left <= size - 1'b1;
end
else // require shifting
begin
burst_left <= size;
end
end
else if (address_left == 0 && burst_left != 0) // start decreasing only after addres shifting is completed
burst_left <= burst_left - 1'b1;
end
end
// Current valid signal
// when there is a column request and column address is "0"
// valid signal must be asserted along with column request
always @ (*)
begin
if (do_col_req && col_address == 0)
current_valid = 1'b1;
else
current_valid = 1'b0;
end
// Delayed valid signal
// when there is a column request with size larger than "1"
// valid signal will be asserted according to the request size
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_valid <= 0;
end
else
begin
if (do_col_req && ((col_address == 0 && size > 1) || col_address == 1'b1))
delayed_valid <= 1'b1;
else if (address_left == 0 && burst_left > 0)
delayed_valid <= 1'b1;
else
delayed_valid <= 1'b0;
end
end
// Combined valid signal
always @ (*)
begin
combined_valid = current_valid | delayed_valid;
end
// Read write valid signal
always @ (*)
begin
rdwr_data_valid = combined_valid;
end
//----------------------------------------------------------------------------------------------------
// Doing Signal
//----------------------------------------------------------------------------------------------------
// Maximum burst counting logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_burst_left <= 0;
end
else
begin
if (do_col_req)
begin
if (do_burst_chop[0]) // Arbiter will make sure to broadcast burst chop info to both bits (0 & 1)
begin
if (max_local_burst_size_divide_2 <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_divide_2_and_minus_2;
end
else
begin
if (max_local_burst_size <= 2)
max_burst_left <= 0;
else
max_burst_left <= max_local_burst_size_minus_2;
end
end
else if (max_burst_left != 0)
max_burst_left <= max_burst_left - 1'b1;
end
end
// Delayed doing signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_doing <= 0;
end
else
begin
if (do_col_req)
begin
if (max_local_burst_size <= 1'b1) //do not generate delayed_doing if max burst count is 1
delayed_doing <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
delayed_doing <= 1'b0;
else
delayed_doing <= 1'b1;
end
else if (max_burst_left > 0)
delayed_doing <= 1'b1;
else
delayed_doing <= 1'b0;
end
end
// Keep track of last commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b0;
end
else
begin
if (do_wr_req)
begin
last_is_write <= 1'b1;
last_is_read <= 1'b0;
end
else if (do_rd_req)
begin
last_is_write <= 1'b0;
last_is_read <= 1'b1;
end
end
end
// Doing write signal
always @ (*)
begin
if (do_rd_req)
doing_write = 1'b0;
else if (do_wr_req)
doing_write = ~terminate_doing;
else if (last_is_write)
doing_write = delayed_doing & ~terminate_doing;
else
doing_write = 1'b0;
end
// Doing read signal
always @ (*)
begin
if (do_wr_req)
doing_read = 1'b0;
else if (do_rd_req)
doing_read = ~terminate_doing;
else if (last_is_read)
doing_read = delayed_doing & ~terminate_doing;
else
doing_read = 1'b0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Generation Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
// Registered arb_do_rmw_* signal when there is a coumn request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_do_rmw_correct <= 0;
delayed_do_rmw_partial <= 0;
end
else
begin
if (do_col_req)
begin
delayed_do_rmw_correct <= do_rmw_correct;
delayed_do_rmw_partial <= do_rmw_partial;
end
end
end
// Prolong RMW information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
begin
combined_do_rmw_correct = do_rmw_correct;
combined_do_rmw_partial = do_rmw_partial;
end
else if (delayed_doing & ~terminate_doing)
begin
combined_do_rmw_correct = delayed_do_rmw_correct;
combined_do_rmw_partial = delayed_do_rmw_partial;
end
else
begin
combined_do_rmw_correct = 0;
combined_do_rmw_partial = 0;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [START] RMW Info
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Data ID
//
//--------------------------------------------------------------------------------------------------------
// Register data ID when there is a column request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
delayed_dataid <= 0;
end
else
begin
if (do_col_req)
delayed_dataid <= dataid;
end
end
// Prolong data ID information until doing signal is deasserted
always @ (*)
begin
if (do_col_req)
combined_dataid = dataid;
else if (delayed_doing)
combined_dataid = delayed_dataid;
else
combined_dataid = 0;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Data ID
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Column Address
//
//--------------------------------------------------------------------------------------------------------
// Change column address bit [2 : 0]
// see waveform examples in burst generation logic portion
always @ (*)
begin
modified_to_col = to_col;
// During burst chop in DDR3 only, retain original column address
// maximum local burst in DDR3 is 4 which is BL8 in full rate
if (do_burst_chop && cfg_type == `MMR_TYPE_DDR3)
begin
if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
else
begin
if (max_local_burst_size [0]) // max local burst of 1
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 0 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 0 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [1]) // max local burst of 2
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 1 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 1 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [2]) // max local burst of 4
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 2 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 2 : CFG_MEM_IF_COL_WIDTH] = 0;
end
else if (max_local_burst_size [3]) // max local burst of 8
begin
modified_to_col [(CFG_DWIDTH_RATIO / 4) + 3 : 0 ] = 0;
modified_to_col [(CFG_DWIDTH_RATIO / 4) + CFG_MEM_IF_COL_WIDTH + 3 : CFG_MEM_IF_COL_WIDTH] = 0;
end
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Column Address
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Interrupt
//
// DDR, DDR2, LPDDR and LPDDR2 specific
//
// This logic re-use most of the existing logic in burst generation section (valid signal)
// This signal will be used in rank timer block to gate can_read and can_write signals
//
// Example: (DDR2 full rate, burst length of 8, this will result in maximum local burst of 4)
//
// Clock ____/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
//
// Do Signal ____/ 1 \_________________/ 1 \_________________/ 1 \_________________/ 1 \_______________________
// Doing Signal ____/ 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 X 1 X 2 X 3 X 4 \_____
// Valid Signal ____/ 1 \_______________________/ 1 \_______________________/ 1 \_______________________/ 1 \_____
//
// Interrupt Ready (tCCD = 1) / HIGH \_____/ HIGH \___________/ HIGH \_________________/
// Interrupt Ready (tCCD = 2) / HIGH \_____/ HIGH \_____/ HIGH \_________________/ \_________________/
//
//--------------------------------------------------------------------------------------------------------
// n-prefetch architecture, related tCCD value (only support 1, 2 and 4)
// if tCCD is set to 1, command can be interrupted / terminated at every 2 memory burst boundary (1 memory clock cycle)
// if tCCD is set to 2, command can be interrupted / terminated at every 4 memory burst boundary (2 memory clock cycle)
// if tCCD is set to 4, command can be interrupted / terminated at every 8 memory burst boundary (4 memory clock cycle)
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
n_prefetch <= 0;
end
else
begin
n_prefetch <= cfg_tccd / (CFG_DWIDTH_RATIO / 2);
end
end
// For n_prefetch of 0 and 1, we will allow interrupt at any controller clock cycles
// for n_prefetch of n, we will allow interrupt at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_interrupt <= 1'b1;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR3) // DDR3 specific, interrupt masking is handled by setting read-to-read and write-to-write to BL/2
int_allow_interrupt <= 1'b1;
else
begin
if (n_prefetch <= 1) // allow interrupt at any clock cycle
begin
if (do_col_req && (((col_address == 0 && size > 1) || col_address != 0) || do_auto_precharge) && (CFG_REG_GRANT && max_local_burst_size > 2)) // only disable interrupt for native size larger than 2 (larger than BL4 in FR), only in CFG grant mode since we only can issue WRRD-NOP-WRRD in this mode
int_allow_interrupt <= 1'b0;
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0)
int_allow_interrupt <= 1'b1;
else if (max_burst_left <= 1'b1)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 2)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left [0] == 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] == 1'b0)))
int_allow_interrupt <= 1'b1;
else if (int_allow_interrupt && max_burst_left > 1'b1 && ((CFG_REG_GRANT && max_burst_left [0] != 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] != 1'b0))) // so that we don't allow interrupt at odd bursts
int_allow_interrupt <= 1'b0;
else if (max_burst_left <= 1'b1)
int_allow_interrupt <= 1'b1;
end
else if (n_prefetch == 4)
begin
if (do_col_req)
int_allow_interrupt <= 1'b0;
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b00)))
int_allow_interrupt <= 1'b1;
else if (int_allow_interrupt && max_burst_left > 1'b1 && ((CFG_REG_GRANT && max_burst_left [1 : 0] != 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] != 2'b00))) // so that we don't allow interrupt at odd bursts
int_allow_interrupt <= 1'b0;
else if (max_burst_left <= 1'b1)
int_allow_interrupt <= 1'b1;
end
end
end
end
// Interrupt info when interrupt feature is enabled
always @ (*)
begin
int_interrupt_enable_ready = int_allow_interrupt;
end
// Interrupt info when interrupt feature is disabled
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_interrupt_disable_ready <= 0;
end
else
begin
if (do_col_req)
begin
if (CFG_REG_GRANT)
begin
if (max_local_burst_size <= 2'd2) //do not generate int_interrupt_ready
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 3'd4)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
else
begin
if (max_local_burst_size <= 1'b1) //do not generate int_interrupt_ready if max burst count is 1
int_interrupt_disable_ready <= 1'b0;
else if (do_burst_chop && max_local_burst_size <= 2'd2)
int_interrupt_disable_ready <= 1'b0;
else
int_interrupt_disable_ready <= 1'b1;
end
end
else if (!CFG_REG_GRANT && max_burst_left > 0)
int_interrupt_disable_ready <= 1'b1;
else if ( CFG_REG_GRANT && max_burst_left > 1'b1)
int_interrupt_disable_ready <= 1'b1;
else
int_interrupt_disable_ready <= 1'b0;
end
end
// Assign to output ports
always @ (*)
begin
if (cfg_enable_burst_interrupt && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
begin
interrupt_ready = int_interrupt_enable_ready;
end
else
begin
interrupt_ready = ~int_interrupt_disable_ready;
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Interrupt
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Terminate
//
// LPDDR1 and LPDDR2 specific only
//
//--------------------------------------------------------------------------------------------------------
// For n_prefetch of 0 and 1, we will allow terminate at any controller clock cycles
// for n_prefetch of n, we will allow terminate at any n controller clock cycles interval
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else
begin
if (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2) // LPDDR1 and LPDDR2 only
begin
if (n_prefetch <= 1) // allow terminate at any clock cycle
begin
if (do_col_req && col_address != 0)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (do_col_req && !do_auto_precharge && col_address == 0 && size == 1'b1 && (CFG_REG_GRANT && max_local_burst_size > 2)) // only allow terminate for native size larger than 2 in non-registered mode
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 2)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)) && ((CFG_REG_GRANT && max_burst_left [0] == 1'b1) || (!CFG_REG_GRANT && max_burst_left [0] == 1'b0) || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
else if (n_prefetch == 4)
begin
if (do_col_req)
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
else if (!doing_auto_precharge && address_left == 0 && burst_left == 0 && ((CFG_REG_GRANT && max_burst_left > 1) || (!CFG_REG_GRANT && max_burst_left > 0)) && ((CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b11) || (!CFG_REG_GRANT && max_burst_left [1 : 0] == 2'b00) || int_allow_terminate == 1'b1))
begin
int_allow_terminate <= 1'b1;
if (!int_allow_terminate)
int_do_burst_terminate <= 1'b1;
else
int_do_burst_terminate <= 1'b0;
end
else
begin
int_allow_terminate <= 1'b0;
int_do_burst_terminate <= 1'b0;
end
end
end
else
begin
int_allow_terminate <= 1'b0;
end
end
end
// Registered version of do burst terminate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_do_burst_terminate_r <= 1'b0;
end
else
begin
int_do_burst_terminate_r <= int_do_burst_terminate;
end
end
// Effective size, actual issued size migh be smaller that maximum local burst size
// we need to inform rank timer about this information for efficient DQ bus turnaround operation
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_effective_size <= 0;
end
else
begin
if (do_col_req)
int_effective_size <= 1'b1;
else if (int_effective_size != {CFG_INT_SIZE_WIDTH{1'b1}})
int_effective_size <= int_effective_size + 1'b1;
end
end
// Terminate doing signal, this signal will be used to mask off doing_read or doing_write signal
// when we issue a burst terminate signal, we should also terminate doing_read and doing_write signal
// to prevent unwanted DQS toggle on the memory interface
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (do_col_req) // reset to "0" after another new column command is detected
doing_burst_terminate <= 1'b0;
else if (address_left == 0 && burst_left == 0 && max_burst_left > 0 && ((|do_burst_terminate) == 1'b1 || doing_burst_terminate == 1'b1))
doing_burst_terminate <= 1'b1;
else
doing_burst_terminate <= 1'b0;
end
end
always @ (*)
begin
if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
begin
terminate_doing = (|do_burst_terminate) | (doing_burst_terminate & !do_col_req);
end
else
begin
terminate_doing = zero;
end
end
// Burst terminate output ports
// set burst terminate signal to '0' when there is a do_col_req (in half and quarter rate)
// or both do_col_req and do_row_req (full rate) because this indicate there is a incoming command
// any command from arbiter is have higher priority compared to burst terminate command
always @ (*)
begin
if (CFG_DWIDTH_RATIO == 2)
int_do_req = do_col_req | do_row_req | do_sideband_req; // sideband request might interfere with burst terminate command as well
else
int_do_req = do_col_req | do_sideband_req; // sideband request might interfere with burst terminate command as well
end
generate
begin
if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
else
begin
// Use delayed version of burst terminate in REG_GRANT mode so that it won't terminate before interrupt can occur
do_burst_terminate [AFI_INTF_HIGH_PHASE] = (CFG_REG_GRANT) ? int_do_burst_terminate_r : int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_HIGH_PHASE] = 0;
end
end
end
else if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
always @ (*)
begin
do_burst_terminate = 0;
if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
begin
if (int_do_req)
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
else
begin
// Use delayed version of burst terminate in REG_GRANT mode so that it won't terminate before interrupt can occur
do_burst_terminate [AFI_INTF_LOW_PHASE] = (CFG_REG_GRANT) ? int_do_burst_terminate_r : int_do_burst_terminate;
end
end
else
begin
do_burst_terminate [AFI_INTF_LOW_PHASE] = 0;
end
end
end
end
endgenerate
// Effective size output ports
always @ (*)
begin
if (cfg_enable_burst_terminate && (cfg_type == `MMR_TYPE_LPDDR1 || cfg_type == `MMR_TYPE_LPDDR2))
begin
effective_size = int_effective_size;
end
else
begin
effective_size = {CFG_INT_SIZE_WIDTH{zero}};
end
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Terminate
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Burst Chop
//
// DDR3 specific only
//
//--------------------------------------------------------------------------------------------------------
// yyong generate
// yyong begin
// yyong if (CFG_DWIDTH_RATIO == 2)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size <= 2 && arb_to_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 4)
// yyong begin
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = 0;
// yyong
// yyong if (cfg_type == `MMR_TYPE_DDR3) // DDR3 only
// yyong begin
// yyong if (arb_size == 1)
// yyong do_burst_chop = arb_do_write | arb_do_read;
// yyong else
// yyong do_burst_chop = 0;
// yyong end
// yyong else // Other memory types
// yyong begin
// yyong do_burst_chop = 0;
// yyong end
// yyong end
// yyong end
// yyong else if (CFG_DWIDTH_RATIO == 8)
// yyong begin
// yyong // Burst chop is not available in quarter rate
// yyong always @ (*)
// yyong begin
// yyong do_burst_chop = {CFG_AFI_INTF_PHASE_NUM{zero}};
// yyong end
// yyong end
// yyong end
// yyong endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Burst Chop
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 23:33:19
// Design Name:
// Module Name: lab1_4_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bcdto7segment_dataflow(
input [3:0] x,
output [6:0] seg
);
assign #1 seg[6] = (x[2]&(~x[1])&(~x[0]))|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[5] = (x[2]&(~x[1])&x[0])|(x[2]&x[1]&(~x[0]));
assign #1 seg[4] = (~x[3])&(~x[2])&x[1]&(~x[0]);
assign #1 seg[3] = (x[2]&(~x[1])&(~x[0]))|(x[2]&x[1]&x[0])|((~x[3])&(~x[2])&(~x[1])&x[0]);
assign #1 seg[2] = (x[2]&(~x[1]))|x[0];
assign #1 seg[1] = (x[1]&x[0])|((~x[3])&(~x[2])&x[0])|((~x[3])&(~x[2])&x[1]);
assign #1 seg[0] = ((~x[3])&(~x[2])&(~x[1]))|(x[2]&x[1]&x[0]);
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// sbram_m20k.v: Single-bit width RAM using Altera's M20K //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module sbram_m20k
#( parameter DEPTH = 16384, // read depth > 16K
parameter IZERO = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(DEPTH)-1:0] wAddr , // write address
input wData , // write data
input [`log2(DEPTH)-1:0] rAddr , // read address
output rData ); // read data
localparam ADDRW = `log2(DEPTH); //
localparam nM20K = DEPTH/16384;
wire [nM20K-1:0] rDataAll;
reg [nM20K-1:0] M20KSel;
// binary to one-hot
always @(*) begin
M20KSel = 0 ;
M20KSel[wAddr[ADDRW-1:14]] = wEnb;
end
// generate and instantiate mixed-width BRAMs
genvar gi;
generate
for (gi=0 ; gi<nM20K ; gi=gi+1) begin: BRAMgi
mwram_m20k #( .WR_DW( 1 ), // write width
.RD_DW( 1 ), // read width
.IZERO( IZERO )) // initialize to zeros
mwram_m20k_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( M20KSel[gi] ), // write enable
.wAddr( wAddr[13:0] ), // write address [13:0]
.wData( wData ), // write data
.rAddr( rAddr[13:0] ), // read address [ 13:0]
.rData( rDataAll[gi] )); // read data [31:0]
end
endgenerate
assign rData = rDataAll[rAddr[ADDRW-1:14]];
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9467(
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay_clock
delay_clk,
// dma interface
adc_clk,
adc_valid,
adc_enable,
adc_data,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay clk
input delay_clk;
// dma interface
output adc_clk;
output adc_valid;
output adc_enable;
output [15:0] adc_data;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_clk;
wire up_rstn;
wire delay_rst;
// internal signals
wire [15:0] adc_data_s;
wire adc_or_s;
wire adc_ddr_edgesel_s;
wire [ 8:0] up_dld_s;
wire [44:0] up_dwdata_s;
wire [44:0] up_drdata_s;
wire delay_locked_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
//defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 32'd0;
up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
// main (device interface)
axi_ad9467_if #(
.PCORE_BUFTYPE (PCORE_BUFTYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// channel
axi_ad9467_channel #(.CHID(0)) i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dfmt_data (adc_data),
.adc_enable (adc_enable),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'b0),
.up_drp_ready (1'b0),
.up_drp_locked (1'b1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module RegisterTestBench;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] test_in,test_in2;
reg test_clk,test_reset,test_load,test_load2;
wire [31:0] test_out;
//module Register2(input [31:0] IN,IN2,input Clk, Reset,Load,Load2,output [31:0] OUT);
Register2 test_reg(.IN(test_in),
.IN2(test_in2),
.Clk(test_clk),
.Reset(test_reset),
.Load(test_load),
.Load2(test_load2),
.OUT(test_out));
reg Clk,Reset;
/*
generate
genvar i;
for (i=0; i<15; i=i+1) begin : dff
custom i_custom(
.clk(clk)
,.input(DFF_i[i])
,.output(DFF_o[i])
);
end
endgenerate
*/
initial fork
test_in=0 ; test_in2=0 ; test_clk=0 ; test_reset=1 ; test_load=0 ; test_load2=0 ;
#1 test_in=1;#1 test_in2=0; #1 test_reset=0 ; #1 test_load=1 ; #1 test_load2=0 ;
#2 test_in=1;#2 test_in2=0; #2 test_reset=0 ; #2 test_load=1 ; #2 test_load2=0 ;
#3 test_in=0;#3 test_in2=0; #3 test_reset=0 ; #3 test_load=0 ; #3 test_load2=0 ;
#4 test_in=0;#4 test_in2=1; #4 test_reset=0 ; #4 test_load=0 ; #4 test_load2=1 ;
#5 test_in=0;#5 test_in2=1; #5 test_reset=0 ; #5 test_load=0 ; #5 test_load2=1 ;
#6 test_in=0;#6 test_in2=1; #6 test_reset=0 ; #6 test_load=0 ; #6 test_load2=1 ;
#7 test_in=1;#7 test_in2=0; #7 test_reset=0 ; #7 test_load=0 ; #7 test_load2=1 ;
#8 test_in=1;#8 test_in2=0; #8 test_reset=0 ; #8 test_load=0 ; #8 test_load2=1 ;
#9 test_in=0;#9 test_in2=0; #9 test_reset=0 ; #9 test_load=0 ; #9 test_load2=1 ;
#10 test_in=0;#10 test_in2=1; #10 test_reset=0 ; #10 test_load=1 ; #10 test_load2=0 ;
#11 test_in=0;#11 test_in2=1; #11 test_reset=0 ; #11 test_load=1 ; #11 test_load2=0 ;
#12 test_in=0;#12 test_in2=1; #12 test_reset=0 ; #12 test_load=0 ; #12 test_load2=0 ;
join
always
#1 test_clk = ~test_clk;
initial #sim_time $finish; //Especifica cuando termina la simulacion
initial begin
$dumpfile("RegisterTestBench.vcd");
$dumpvars(0,RegisterTestBench);
$display(" Test Results" ); // imprime header
$monitor("T = %d,test_out = %d,test_in = %d,test_in2 = %d,test_clk = %d,test_reset = %d,test_load = %d,test_load2 = %d",$time,test_out,test_in,test_in2,test_clk,test_reset,test_load,test_load2 ); //imprime se~ales
end
endmodule
//iverilog Register2.v RegisterTestBench.v
//gtkwave RegisterTestBench.vcd
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_BLACKBOX_V
`define SKY130_FD_SC_HS__A311O_BLACKBOX_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_BLACKBOX_V
|
module IBUF (
(* iopad_external_pin *)
input I,
output O
);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
assign O = I;
specify
(I => O) = 0;
endspecify
endmodule
module OBUF (
input I,
(* iopad_external_pin *)
output O
);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
assign O = I;
specify
(I => O) = 0;
endspecify
endmodule
module SYN_OBUF(
input I,
(* iopad_external_pin *)
output O);
assign O = I;
endmodule
module SYN_IBUF(
output O,
(* iopad_external_pin *)
input I);
assign O = I;
endmodule
module OBUFDS (
input I,
(* iopad_external_pin *)
output O,
(* iopad_external_pin *)
output OB
);
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE";
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
parameter HAS_OSERDES = 0;
assign O = I;
assign OB = ~I;
endmodule
module OBUFTDS (
input I,
input T,
(* iopad_external_pin *)
output O,
(* iopad_external_pin *)
output OB
);
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE";
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
parameter HAS_OSERDES = 0;
assign O = (T == 1'b0) ? I : 1'bz;
assign OB = (T == 1'b0) ? ~I : 1'bz;
endmodule
module IOBUF (
(* iopad_external_pin *)
inout IO,
output O,
input I,
input T
);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter IBUF_LOW_PWR = 0;
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
assign IO = T ? 1'bz : I;
assign O = IO;
specify
(I => IO) = 0;
(IO => O) = 0;
endspecify
endmodule
module OBUFT (
(* iopad_external_pin *)
output O,
input I,
input T
);
parameter CAPACITANCE = "DONT_CARE";
parameter DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
assign O = T ? 1'bz : I;
specify
(I => O) = 0;
endspecify
endmodule
module IOBUFDS (
input I,
input T,
output O,
(* iopad_external_pin *)
inout IO,
(* iopad_external_pin *)
inout IOB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "SLOW";
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
endmodule
module IBUFDS_GTE2 (
output O,
output ODIV2,
input CEB,
(* iopad_external_pin *)
input I,
(* iopad_external_pin *)
input IB
);
parameter IO_LOC_PAIRS = ""; // Used by read_xdc.
endmodule
module GTPE2_CHANNEL (
(* iopad_external_pin *)
output GTPTXN,
(* iopad_external_pin *)
output GTPTXP,
(* iopad_external_pin *)
input GTPRXN,
(* iopad_external_pin *)
input GTPRXP,
output DRPRDY,
output EYESCANDATAERROR,
output PHYSTATUS,
output PMARSVDOUT0,
output PMARSVDOUT1,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output RXDLYSRESETDONE,
output RXELECIDLE,
output RXHEADERVALID,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPMARESETDONE,
output RXPRBSERR,
output RXRATEDONE,
output RXRESETDONE,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXGEARBOXREADY,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
output [14:0] DMONITOROUT,
output [15:0] DRPDO,
output [15:0] PCSRSVDOUT,
output [1:0] RXCLKCORCNT,
output [1:0] RXDATAVALID,
output [1:0] RXSTARTOFSEQ,
output [1:0] TXBUFSTATUS,
output [2:0] RXBUFSTATUS,
output [2:0] RXHEADER,
output [2:0] RXSTATUS,
output [31:0] RXDATA,
output [3:0] RXCHARISCOMMA,
output [3:0] RXCHARISK,
output [3:0] RXCHBONDO,
output [3:0] RXDISPERR,
output [3:0] RXNOTINTABLE,
output [4:0] RXPHMONITOR,
output [4:0] RXPHSLIPMONITOR,
input CFGRESET,
(* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
input CLKRSVD0,
(* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
input CLKRSVD1,
input DMONFIFORESET,
(* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
input DMONITORCLK,
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK,
input DRPEN,
input DRPWE,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTRESETSEL,
input GTRXRESET,
input GTTXRESET,
input PLL0CLK,
input PLL0REFCLK,
input PLL1CLK,
input PLL1REFCLK,
input PMARSVDIN0,
input PMARSVDIN1,
input PMARSVDIN2,
input PMARSVDIN3,
input PMARSVDIN4,
input RESETOVRD,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input RXDDIEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input RXGEARBOXSLIP,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFOVRDEN,
input RXLPMOSINTNTRLEN,
input RXLPMRESET,
input RXMCOMMAALIGNEN,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTNTRLEN,
input RXOSINTOVRDEN,
input RXOSINTPD,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input RXRATEMODE,
input RXSLIDE,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input RXUSERRDY,
(* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
input RXUSRCLK2,
(* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
input RXUSRCLK,
input SETERRSTATUS,
(* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
input SIGVALIDCLK,
input TX8B10BEN,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input TXDEEMPH,
input TXDETECTRX,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input TXINHIBIT,
input TXPCSRESET,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
(* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input TXPISOPD,
input TXPMARESET,
input TXPOLARITY,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input TXPRECURSORINV,
input TXRATEMODE,
input TXSTARTSEQ,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input TXUSERRDY,
(* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
input TXUSRCLK2,
(* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
input TXUSRCLK,
input [13:0] RXADAPTSELTEST,
input [15:0] DRPDI,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [19:0] TSTIN,
input [1:0] RXELECIDLEMODE,
input [1:0] RXPD,
input [1:0] RXSYSCLKSEL,
input [1:0] TXPD,
input [1:0] TXSYSCLKSEL,
input [2:0] LOOPBACK,
input [2:0] RXCHBONDLEVEL,
input [2:0] RXOUTCLKSEL,
input [2:0] RXPRBSSEL,
input [2:0] RXRATE,
input [2:0] TXBUFDIFFCTRL,
input [2:0] TXHEADER,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input [2:0] TXPRBSSEL,
input [2:0] TXRATE,
input [31:0] TXDATA,
input [3:0] RXCHBONDI,
input [3:0] RXOSINTCFG,
input [3:0] RXOSINTID0,
input [3:0] TX8B10BBYPASS,
input [3:0] TXCHARDISPMODE,
input [3:0] TXCHARDISPVAL,
input [3:0] TXCHARISK,
input [3:0] TXDIFFCTRL,
input [4:0] TXPIPPMSTEPSIZE,
input [4:0] TXPOSTCURSOR,
input [4:0] TXPRECURSOR,
input [6:0] TXMAINCURSOR,
input [6:0] TXSEQUENCE,
input [8:0] DRPADDR
);
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter integer ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
parameter [6:0] CFOK_CFG2 = 7'b0100000;
parameter [6:0] CFOK_CFG3 = 7'b0100000;
parameter [0:0] CFOK_CFG4 = 1'b0;
parameter [1:0] CFOK_CFG5 = 2'b00;
parameter [3:0] CFOK_CFG6 = 4'b0000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter integer CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter [0:0] CLK_COMMON_SWING = 1'b0;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter integer CLK_COR_MAX_LAT = 20;
parameter integer CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter integer CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
parameter [31:0] PMA_RSV = 32'h00000333;
parameter [31:0] PMA_RSV2 = 32'h00002050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [3:0] PMA_RSV4 = 4'b0000;
parameter [0:0] PMA_RSV5 = 1'b0;
parameter [0:0] PMA_RSV6 = 1'b0;
parameter [0:0] PMA_RSV7 = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter integer RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter integer RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [15:0] RXDLY_CFG = 16'h0010;
parameter [8:0] RXDLY_LCFG = 9'h020;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
parameter [3:0] RXLPM_CFG = 4'b0110;
parameter [0:0] RXLPM_CFG1 = 1'b0;
parameter [0:0] RXLPM_CM_CFG = 1'b0;
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084000;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [2:0] RXPI_CFG0 = 3'b000;
parameter [0:0] RXPI_CFG1 = 1'b0;
parameter [0:0] RXPI_CFG2 = 1'b0;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter integer RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_EN = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter integer SAS_MAX_COM = 64;
parameter integer SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter integer SATA_MAX_BURST = 8;
parameter integer SATA_MAX_INIT = 21;
parameter integer SATA_MAX_WAKE = 7;
parameter integer SATA_MIN_BURST = 4;
parameter integer SATA_MIN_INIT = 12;
parameter integer SATA_MIN_WAKE = 4;
parameter SATA_PLL_CFG = "VCO_3000MHZ";
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h0010;
parameter [8:0] TXDLY_LCFG = 9'h020;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084000;
parameter [15:0] TXPH_CFG = 16'h0400;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b000;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_EN = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
parameter IO_LOC_PAIRS = ""; // Used by read_xdc
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pix_pll_bt_1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pix_pll_bt_1 (
areset,
clkswitch,
inclk0,
inclk1,
c0,
locked);
input areset;
input clkswitch;
input inclk0;
input inclk1;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 clkswitch;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire5 = inclk1;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.clkswitch (clkswitch),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 52,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 59,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 26666,
altpll_component.inclk1_input_frequency = 26666,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pix_pll_bt_1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_USED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_USED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.primary_clock = "inclk0",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.switch_over_type = "MANUAL",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "42.548077"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "37.500"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "37.500"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "59"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "42.55000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pix_pll_bt_1.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "59"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "26666"
// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "26666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pix_pll_bt_1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`include "bsg_cache.vh"
module bsg_test_master
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(ways_p)
, localparam dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
, localparam ring_width_lp=`bsg_cache_pkt_width(addr_width_p, data_width_p)
, localparam rom_addr_width_lp=32
)
(
input clk_i
, input reset_i
, output logic [num_cache_p-1:0][dma_pkt_width_lp-1:0] dma_pkt_o
, output logic [num_cache_p-1:0] dma_pkt_v_o
, input [num_cache_p-1:0] dma_pkt_yumi_i
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_ready_o
, output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_yumi_i
, output logic done_o
);
// trace replay
//
// send trace: {opcode(5), addr, data}
// recv trace: {filler(5+32), data}
//
logic [num_cache_p-1:0] tr_v_li;
logic [num_cache_p-1:0][ring_width_lp-1:0] tr_data_li;
logic [num_cache_p-1:0] tr_ready_lo;
logic [num_cache_p-1:0] tr_v_lo;
logic [num_cache_p-1:0][ring_width_lp-1:0] tr_data_lo;
logic [num_cache_p-1:0] tr_yumi_li;
logic [num_cache_p-1:0][rom_addr_width_lp-1:0] rom_addr;
logic [num_cache_p-1:0][ring_width_lp+4-1:0] rom_data;
logic [num_cache_p-1:0] tr_done_lo;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) tr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(1'b1)
,.v_i(tr_v_li[i])
,.data_i(tr_data_li[i])
,.ready_o(tr_ready_lo[i])
,.v_o(tr_v_lo[i])
,.data_o(tr_data_lo[i])
,.yumi_i(tr_yumi_li[i])
,.rom_addr_o(rom_addr[i])
,.rom_data_i(rom_data[i])
,.done_o(tr_done_lo[i])
,.error_o()
);
bsg_trace_rom #(
.rom_addr_width_p(rom_addr_width_lp)
,.rom_data_width_p(ring_width_lp+4)
,.id_p(i)
) trace_rom (
.rom_addr_i(rom_addr[i])
,.rom_data_o(rom_data[i])
);
end
assign done_o = &tr_done_lo;
// cache
//
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
bsg_cache_pkt_s [num_cache_p-1:0] cache_pkt;
logic [num_cache_p-1:0] cache_v_li;
logic [num_cache_p-1:0] cache_ready_lo;
logic [num_cache_p-1:0][data_width_p-1:0] cache_data_lo;
logic [num_cache_p-1:0] cache_v_lo;
logic [num_cache_p-1:0] cache_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_cache #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
) cache (
.clk_i(clk_i)
,.reset_i(reset_i)
,.cache_pkt_i(cache_pkt[i])
,.v_i(cache_v_li[i])
,.ready_o(cache_ready_lo[i])
,.data_o(cache_data_lo[i])
,.v_o(cache_v_lo[i])
,.yumi_i(cache_yumi_li[i])
,.dma_pkt_o(dma_pkt_o[i])
,.dma_pkt_v_o(dma_pkt_v_o[i])
,.dma_pkt_yumi_i(dma_pkt_yumi_i[i])
,.dma_data_i(dma_data_i[i])
,.dma_data_v_i(dma_data_v_i[i])
,.dma_data_ready_o(dma_data_ready_o[i])
,.dma_data_o(dma_data_o[i])
,.dma_data_v_o(dma_data_v_o[i])
,.dma_data_yumi_i(dma_data_yumi_i[i])
,.v_we_o()
);
assign cache_pkt[i] = tr_data_lo[i];
assign cache_v_li[i] = tr_v_lo[i];
assign tr_yumi_li[i] = tr_v_lo[i] & cache_ready_lo[i];
assign tr_data_li[i] = {{(ring_width_lp-data_width_p){1'b0}}, cache_data_lo[i]};
assign tr_v_li[i] = cache_v_lo[i];
assign cache_yumi_li[i] = cache_v_lo[i] & tr_ready_lo[i];
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_test_master)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_BLACKBOX_V
`define SKY130_FD_SC_LP__A221O_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_4_V
`define SKY130_FD_SC_HD__O32A_4_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_4_V
|
`ifndef _iq_
`define _iq_
// instruction queue
module iq(
input clk,
input rst,
input inst1_in_valid,
input [31:0] inst1_in,
input inst2_in_valid,
input [31:0] inst2_in,
input [31:0] inst1_in_pc4,
input [31:0] inst2_in_pc4,
input in_branch_valid,
input [31:0] in_btb_pc_predict,
input in_direct_predict,
input stall_backend,
input mispredict,
input singlemode, // single width
output logic iq_empty,
output logic iq_full,
output logic branch_valid,
output logic [31:0] btb_pc_predict,
output logic direct_predict,
output logic inst1_out_valid,
output logic [31:0] inst1_out,
output logic [31:0] inst1_out_pc4,
output logic inst2_out_valid,
output logic [31:0] inst2_out,
output logic [31:0] inst2_out_pc4
);
typedef struct packed{
logic [31:0] inst;
logic [31:0] pc4;
logic branch_valid;
logic [31:0] btb_pc_predict;
logic direct_predict;
} iqStruct;
iqStruct iq_array [15:0] ;
logic [4:0] iq_head_ext;
logic [4:0] iq_tail_ext;
logic [3:0] iq_head;
logic [3:0] iq_tail;
logic iq_near_empty;
logic iq_near_full;
logic iq_real_empty;
logic iq_real_full;
assign iq_head = iq_head_ext[3:0];
assign iq_tail = iq_tail_ext[3:0];
assign iq_real_empty = (iq_head_ext == iq_tail_ext);
assign iq_near_empty = (iq_head_ext + 1 == iq_tail_ext);
assign iq_real_full = (iq_head_ext != iq_tail_ext) && (iq_head == iq_tail);
assign iq_near_full = (iq_head_ext != iq_tail_ext + 1) && (iq_head == iq_tail + 1);
assign iq_empty = iq_real_empty || iq_near_empty;
assign iq_full = iq_real_full || iq_near_full;
always @(posedge clk, negedge rst) begin
if (!rst) begin
iq_tail_ext <= 5'b0;
iq_head_ext <= 5'b0;
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
inst1_out <= 32'h0;
inst2_out <= 32'h0;
branch_valid <= 1'b0;
btb_pc_predict <= 32'h0;
direct_predict <= 1'b0;
for ( int i = 0; i < $size(iq_array) ; i++) begin
iq_array[i] <= {$size(iqStruct){1'b0}};
end
end
else if (mispredict) begin
iq_tail_ext <= 5'b0;
iq_head_ext <= 5'b0;
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
inst1_out <= 32'h0;
inst2_out <= 32'h0;
for ( int i = 0; i < $size(iq_array) ; i++) begin
iq_array[i] <= {$size(iqStruct){1'b0}};
end
end
else begin
// enqueue 2 instructions
if (inst1_in_valid && inst2_in_valid && !iq_near_full && !iq_real_full && !singlemode) begin
iq_array[iq_tail].inst <= inst1_in;
iq_array[iq_tail+1].inst <= inst2_in;
iq_array[iq_tail].pc4 <= inst1_in_pc4;
iq_array[iq_tail+1].pc4 <= inst2_in_pc4;
//fixme:only handle sigle instruction for branch now
iq_tail_ext <= iq_tail_ext + 2;
end
// enqueue 1 instruction
else if (inst1_in_valid && !inst2_in_valid && !iq_real_full) begin
iq_array[iq_tail].inst <= inst1_in;
iq_array[iq_tail].pc4 <= inst1_in_pc4;
iq_array[iq_tail].branch_valid <= in_branch_valid;
iq_array[iq_tail].btb_pc_predict <= in_btb_pc_predict;
iq_array[iq_tail].direct_predict <= in_direct_predict;
iq_tail_ext <= iq_tail_ext + 1;
end
if (stall_backend) begin
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
end
//dequeue 2 instructions
else if (!iq_near_empty && !iq_real_empty && !singlemode) begin
iq_head_ext <= iq_head_ext + 2;
inst1_out_valid <= 1'b1;
inst1_out <= iq_array[iq_head].inst;
inst1_out_pc4 <= iq_array[iq_head].pc4;
inst2_out_valid <= 1'b1;
inst2_out <= iq_array[iq_head+1].inst;
inst2_out_pc4 <= iq_array[iq_head+1].pc4;
end
//dequeue 1 instruction
else if ((iq_near_empty && !iq_real_empty && !singlemode) ||
(!iq_real_empty && singlemode)) begin
iq_head_ext <= iq_head_ext + 1;
inst1_out_valid <= 1'b1;
inst1_out <= iq_array[iq_head].inst;
inst1_out_pc4 <= iq_array[iq_head].pc4;
inst2_out_valid <= 1'b0;
branch_valid <= iq_array[iq_head].branch_valid;
btb_pc_predict <= iq_array[iq_head].btb_pc_predict;
direct_predict <= iq_array[iq_head].direct_predict;
end
else begin
inst1_out_valid <= 1'b0;
inst2_out_valid <= 1'b0;
end
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
endmodule // iq
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_TB_V
`define SKY130_FD_SC_HS__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hs__sdfrtn dut (.RESET_B(RESET_B), .D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_TB_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_protocol_converter_v2_1_7_axi_protocol_converter,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_v2_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_v2_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_v2_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_7_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp4.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp4(/*AUTOARG*/
// Outputs
scan_out, pcx_io_data_px_l,
// Inputs
shiftenable, scan_in, rclk, arbpc4_pcxdp_shift_px,
arbpc4_pcxdp_qsel1_pa, arbpc4_pcxdp_qsel0_pa,
arbpc4_pcxdp_q0_hold_pa, arbpc4_pcxdp_grant_pa, spc0_pcx_data_pa,
spc1_pcx_data_pa, spc2_pcx_data_pa, spc3_pcx_data_pa,
spc4_pcx_data_pa, spc5_pcx_data_pa, spc6_pcx_data_pa,
spc7_pcx_data_pa
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [7:0] scan_out; // From mac0 of pcx_dp_maca_r.v, ...
// End of automatics
output [`PCX_WIDTH-1:0] pcx_io_data_px_l; // From mac4 of pcx_dp_macc.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0] arbpc4_pcxdp_grant_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc4_pcxdp_q0_hold_pa;// To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc4_pcxdp_qsel0_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc4_pcxdp_qsel1_pa; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] arbpc4_pcxdp_shift_px; // To mac0 of pcx_dp_maca_r.v, ...
input rclk; // To mac0 of pcx_dp_maca_r.v, ...
input [7:0] scan_in; // To mac0 of pcx_dp_maca_r.v, ...
input shiftenable; // To mac7 of pcx_dp_maca_l.v
// End of automatics
input [`PCX_WIDTH-1:0] spc0_pcx_data_pa; // To mac0 of pcx_dp_maca.v
input [`PCX_WIDTH-1:0] spc1_pcx_data_pa; // To mac1 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc2_pcx_data_pa; // To mac2 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc3_pcx_data_pa; // To mac3 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc4_pcx_data_pa; // To mac4 of pcx_dp_macc.v
input [`PCX_WIDTH-1:0] spc5_pcx_data_pa; // To mac5 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc6_pcx_data_pa; // To mac6 of pcx_dp_macb.v
input [`PCX_WIDTH-1:0] spc7_pcx_data_pa; // To mac7 of pcx_dp_maca.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [129:0] pcx_col0_data_px_l; // From mac0 of pcx_dp_maca_r.v
wire [129:0] pcx_col1_data_px_l; // From mac1 of pcx_dp_macb_r.v
wire [129:0] pcx_col2_data_px_l; // From mac2 of pcx_dp_macb_r.v
wire [129:0] pcx_col3_data_px_l; // From mac3 of pcx_dp_macb_r.v
wire [129:0] pcx_col5_data_px_l; // From mac5 of pcx_dp_macb_l.v
wire [129:0] pcx_col6_data_px_l; // From mac6 of pcx_dp_macb_l.v
wire [129:0] pcx_col7_data_px_l; // From mac7 of pcx_dp_maca_l.v
wire [7:1] shiftenable_buf; // From mac1 of pcx_dp_macb_r.v, ...
// End of automatics
wire [5:0] unused;
/*
// DATAPATH ORGANISATION(pcx_dp4)
sparc0 sparc1 sparc2 sparc3 sparc4 sparc5 sparc6 sparc7
| | | | | | | |
| | | | | | | --ff-----> to IO Bridge
| | | | | | | | |
v v v v v v v | v
mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 -> mac6 <- mac7
(new)ar br br br cl bl bl al
(old)a b b b b b c a
*/
/*
pcx_dp_maca_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_maca_r mac0(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col0_data_px_l[129:0]), // Templated
.scan_out (scan_out[0]), // Templated
.shiftenable_buf (), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[0]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[0]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[0]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[0]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[0]), // Templated
.src_pcx_data_pa ({6'b000000,spc0_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[0]), // Templated
.shiftenable (shiftenable_buf[1])); // Templated
/*
pcx_dp_macb_r AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_r mac1(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col1_data_px_l[129:0]), // Templated
.scan_out (scan_out[1]), // Templated
.shiftenable_buf (shiftenable_buf[1]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[1]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[1]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[1]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[1]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[1]), // Templated
.src_pcx_data_pa ({6'b000000,spc1_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col0_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[1]), // Templated
.shiftenable (shiftenable_buf[2])); // Templated
pcx_dp_macb_r mac2(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col2_data_px_l[129:0]), // Templated
.scan_out (scan_out[2]), // Templated
.shiftenable_buf (shiftenable_buf[2]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[2]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[2]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[2]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[2]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[2]), // Templated
.src_pcx_data_pa ({6'b000000,spc2_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col1_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[2]), // Templated
.shiftenable (shiftenable_buf[3])); // Templated
pcx_dp_macb_r mac3(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col3_data_px_l[129:0]), // Templated
.scan_out (scan_out[3]), // Templated
.shiftenable_buf (shiftenable_buf[3]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[3]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[3]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[3]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[3]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[3]), // Templated
.src_pcx_data_pa ({6'b000000,spc3_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col2_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[3]), // Templated
.shiftenable (shiftenable_buf[4])); // Templated
/*
pcx_dp_macc_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l ({unused[5:0],pcx_io_data_px_l[`PCX_WIDTH-1:0]}),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_crit_px_l (pcx_col@"(- @ 1)"_data_px_l[129:0]),
.data_ncrit_px_l(pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macc_l mac4(/*AUTOINST*/
// Outputs
.data_out_px_l ({unused[5:0],pcx_io_data_px_l[`PCX_WIDTH-1:0]}), // Templated
.scan_out (scan_out[4]), // Templated
.shiftenable_buf (shiftenable_buf[4]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[4]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[4]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[4]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[4]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[4]), // Templated
.src_pcx_data_pa ({6'b000000,spc4_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_crit_px_l (pcx_col3_data_px_l[129:0]), // Templated
.data_ncrit_px_l (pcx_col5_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[4]), // Templated
.shiftenable (shiftenable_buf[5])); // Templated
/*
pcx_dp_macb_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.data_prev_px_l (pcx_col@"(+ @ 1)"_data_px_l[129:0]),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable_buf[@"(+ @ 1)"]));
*/
pcx_dp_macb_l mac5(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col5_data_px_l[129:0]), // Templated
.scan_out (scan_out[5]), // Templated
.shiftenable_buf (shiftenable_buf[5]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[5]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[5]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[5]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[5]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[5]), // Templated
.src_pcx_data_pa ({6'b000000,spc5_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col6_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[5]), // Templated
.shiftenable (shiftenable_buf[6])); // Templated
pcx_dp_macb_l mac6(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col6_data_px_l[129:0]), // Templated
.scan_out (scan_out[6]), // Templated
.shiftenable_buf (shiftenable_buf[6]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[6]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[6]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[6]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[6]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[6]), // Templated
.src_pcx_data_pa ({6'b000000,spc6_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.data_prev_px_l (pcx_col7_data_px_l[129:0]), // Templated
.rclk (rclk),
.scan_in (scan_in[6]), // Templated
.shiftenable (shiftenable_buf[7])); // Templated
/*
pcx_dp_maca_l AUTO_TEMPLATE(
// Outputs
.data_out_px_l (pcx_col@_data_px_l[129:0]),
.shiftenable_buf (shiftenable_buf[@]),
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[@]),
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[@]),
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[@]),
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[@]),
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[@]),
.src_pcx_data_pa({6'b000000,spc@_pcx_data_pa[`PCX_WIDTH-1:0]}),
.clk (clk),
//.tmb_l (tmb_l),
.scan_in (scan_in[@]),
.scan_out (scan_out[@]),
.shiftenable (shiftenable));
*/
pcx_dp_maca_l mac7(/*AUTOINST*/
// Outputs
.data_out_px_l (pcx_col7_data_px_l[129:0]), // Templated
.scan_out (scan_out[7]), // Templated
.shiftenable_buf (shiftenable_buf[7]), // Templated
// Inputs
.arb_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[7]), // Templated
.arb_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7]), // Templated
.arb_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7]), // Templated
.arb_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7]), // Templated
.arb_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[7]), // Templated
.src_pcx_data_pa ({6'b000000,spc7_pcx_data_pa[`PCX_WIDTH-1:0]}), // Templated
.rclk (rclk),
.scan_in (scan_in[7]), // Templated
.shiftenable (shiftenable)); // Templated
// Code start here
//
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/rp2a03.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Implementation of the RP2A03 chip for an fpga-based NES emulator. Contains a MOS-6502 CPU
* core, APU, sprite DMA engine, and joypad control logic.
***************************************************************************************************/
module rp2a03
(
input clk_in, // system clock
input rst_in, // system reset
// CPU signals.
input rdy_in, // ready signal
input [ 7:0] d_in, // data input bus
input nnmi_in, // /nmi interrupt signal (active low)
input nres_in, // /res interrupt signal (active low)
output [ 7:0] d_out, // data output bus
output [15:0] a_out, // address bus
output r_nw_out, // read/write select (write low)
output brk_out, // debug break signal
// Joypad signals.
input [7:0] i_jp1_state, //State of joypad 1
input [7:0] i_jp2_state, //State of joypad 2
// Audio signals.
input [ 3:0] mute_in, // disable autio channels
output audio_out, // pwm audio output
// HCI interface.
input [ 3:0] dbgreg_sel_in, // dbg reg select
input [ 7:0] dbgreg_d_in, // dbg reg data in
input dbgreg_wr_in, // dbg reg write select
output [ 7:0] dbgreg_d_out // dbg reg data out
);
//
// CPU: central processing unit block.
//
wire cpu_ready;
wire [ 7:0] cpu_din;
wire cpu_nirq;
wire [ 7:0] cpu_dout;
wire [15:0] cpu_a;
wire cpu_r_nw;
cpu cpu_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.nres_in (nres_in ),
.nnmi_in (nnmi_in ),
.nirq_in (cpu_nirq ),
.ready_in (cpu_ready ),
.brk_out (brk_out ),
.d_in (cpu_din ),
.d_out (cpu_dout ),
.a_out (cpu_a ),
.r_nw_out (cpu_r_nw ),
.dbgreg_wr_in (dbgreg_wr_in ),
.dbgreg_in (dbgreg_d_in ),
.dbgreg_sel_in (dbgreg_sel_in ),
.dbgreg_out (dbgreg_d_out )
);
//
// APU: audio processing unit block.
//
wire [7:0] audio_dout;
apu apu_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.mute_in (mute_in ),
.a_in (cpu_a ),
.d_in (cpu_dout ),
.r_nw_in (cpu_r_nw ),
.audio_out (audio_out ),
.d_out (audio_dout )
);
//
// JP: joypad controller block.
//
wire [7:0] jp_dout;
jp jp_blk(
.clk (clk_in ),
.rst (rst_in ),
.i_wr (~cpu_r_nw ),
.i_addr (cpu_a ),
.i_din (cpu_dout[0] ),
.o_dout (jp_dout ),
.i_jp1_state (i_jp1_state ),
.i_jp2_state (i_jp2_state )
);
/*
jp jp_blk(
.clk (clk_in ),
.rst (rst_in ),
.wr (~cpu_r_nw ),
.addr (cpu_a ),
.din (cpu_dout[0] ),
.dout (jp_dout ),
.jp_clk (jp_clk ),
.jp_latch (jp_latch ),
.jp_data1 (jp_data1_in ),
.jp_data2 (jp_data2_in )
);
*/
//
// SPRDMA: sprite dma controller block.
//
wire sprdma_active;
wire [15:0] sprdma_a;
wire [ 7:0] sprdma_dout;
wire sprdma_r_nw;
sprdma sprdma_blk(
.clk_in (clk_in ),
.rst_in (rst_in ),
.cpumc_a_in (cpu_a ),
.cpumc_din_in (cpu_dout ),
.cpumc_dout_in (cpu_din ),
.cpu_r_nw_in (cpu_r_nw ),
.active_out (sprdma_active ),
.cpumc_a_out (sprdma_a ),
.cpumc_d_out (sprdma_dout ),
.cpumc_r_nw_out (sprdma_r_nw )
);
assign cpu_ready = rdy_in & !sprdma_active;
assign cpu_din = d_in | jp_dout | audio_dout;
assign cpu_nirq = 1'b1;
assign d_out = (sprdma_active) ? sprdma_dout : cpu_dout;
assign a_out = (sprdma_active) ? sprdma_a : cpu_a;
assign r_nw_out = (sprdma_active) ? sprdma_r_nw : cpu_r_nw;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_TB_V
`define SKY130_FD_SC_MS__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ms__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_TB_V
|
/* Copyright 2015 TREVOR DAVID BLACK
* buffer.v
* buffer is designed to take the nibbles being sent from hf_decompression
* taking these nibbles and valids, it will then construct a buffer
* This buffer will shift out one bit at a time
* The problem with this implementation is that the buffer can fill up
* This is caused by 4 bits entering when 1 bit is shifted out
* The elegant solution to this problem is to also shift out 4 bits at a time
* This elegant solution reduces the buffer to meaninglessness
* So it will be deprecated from the final verilog build
*/
module buffer (
input wire [3:0] buff_in,
input wire buff_in_valid,
output reg buff_out,
output reg buff_out_valid,
output wire buffer_full,
input wire CLK,
input wire Reset
);
reg [31:0] buffer_array; // Effectively a shift register
reg [31:0] sp; // The stack pointer is grey coded for simplicity
assign buffer_full = sp[29]; // 4 bits beyond 29 would be an overflow
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
buffer_array <= 32'b0;
end
else begin
if (buff_in_valid) begin
buffer_array <= (sp[28]) ? ({buff_in[3:0], buffer_array[28:1]}) : (
(sp[27]) ? ({01'b0, buff_in[3:0], buffer_array[27:1]}) :
(sp[26]) ? ({02'b0, buff_in[3:0], buffer_array[26:1]}) :
(sp[25]) ? ({03'b0, buff_in[3:0], buffer_array[25:1]}) :
(sp[24]) ? ({04'b0, buff_in[3:0], buffer_array[24:1]}) :
(sp[23]) ? ({05'b0, buff_in[3:0], buffer_array[23:1]}) :
(sp[22]) ? ({06'b0, buff_in[3:0], buffer_array[22:1]}) :
(sp[21]) ? ({07'b0, buff_in[3:0], buffer_array[21:1]}) :
(sp[20]) ? ({08'b0, buff_in[3:0], buffer_array[20:1]}) :
(sp[19]) ? ({09'b0, buff_in[3:0], buffer_array[19:1]}) :
(sp[18]) ? ({10'b0, buff_in[3:0], buffer_array[18:1]}) :
(sp[17]) ? ({11'b0, buff_in[3:0], buffer_array[17:1]}) :
(sp[16]) ? ({12'b0, buff_in[3:0], buffer_array[16:1]}) :
(sp[15]) ? ({13'b0, buff_in[3:0], buffer_array[15:1]}) :
(sp[14]) ? ({14'b0, buff_in[3:0], buffer_array[14:1]}) :
(sp[13]) ? ({15'b0, buff_in[3:0], buffer_array[13:1]}) :
(sp[12]) ? ({16'b0, buff_in[3:0], buffer_array[12:1]}) :
(sp[11]) ? ({17'b0, buff_in[3:0], buffer_array[11:1]}) :
(sp[10]) ? ({18'b0, buff_in[3:0], buffer_array[10:1]}) :
(sp[09]) ? ({19'b0, buff_in[3:0], buffer_array[09:1]}) :
(sp[08]) ? ({20'b0, buff_in[3:0], buffer_array[08:1]}) :
(sp[07]) ? ({21'b0, buff_in[3:0], buffer_array[07:1]}) :
(sp[06]) ? ({22'b0, buff_in[3:0], buffer_array[06:1]}) :
(sp[05]) ? ({23'b0, buff_in[3:0], buffer_array[05:1]}) :
(sp[04]) ? ({24'b0, buff_in[3:0], buffer_array[04:1]}) :
(sp[03]) ? ({25'b0, buff_in[3:0], buffer_array[03:1]}) :
(sp[02]) ? ({26'b0, buff_in[3:0], buffer_array[02:1]}) :
(sp[01]) ? ({27'b0, buff_in[3:0], buffer_array[01:1]}) :
(sp[00]) ? ({28'b0, buff_in[3:0]}) : {29'b0, buff_in[3:1]} );
end
else begin
buffer_array <= {1'b0, buffer_array[31:1]};
end
end
end
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
buff_out <= 0;
buff_out_valid <= 0;
end
else begin
if(buff_in_valid) begin
buff_out_valid <= 1'b1;
buff_out <= (sp[0]) ? (buffer_array[0]) : (buff_in);
end else begin
buff_out_valid <= sp[0];
buff_out <= buffer_array[0];
end
end
end
always @ (posedge CLK or negedge Reset) begin
if(~Reset) begin
sp <= 32'b0;
end
else begin
if(buff_in_valid) begin
sp <= {sp[28:0] ,3'b0};
end
else begin
sp <= {1'b0, sp[31:1]};
end
end
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* $Id: Basics.v 13323 2010-07-24 15:57:30Z herbelin $ *)
(** Standard functions and combinators.
Proofs about them require functional extensionality and can be found
in [Combinators].
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
(** The polymorphic identity function is defined in [Datatypes]. *)
Implicit Arguments id [[A]].
(** Function composition. *)
Definition compose {A B C} (g : B -> C) (f : A -> B) :=
fun x : A => g (f x).
Hint Unfold compose.
Notation " g ∘ f " := (compose g f)
(at level 40, left associativity) : program_scope.
Open Local Scope program_scope.
(** The non-dependent function space between [A] and [B]. *)
Definition arrow (A B : Type) := A -> B.
(** Logical implication. *)
Definition impl (A B : Prop) : Prop := A -> B.
(** The constant function [const a] always returns [a]. *)
Definition const {A B} (a : A) := fun _ : B => a.
(** The [flip] combinator reverses the first two arguments of a function. *)
Definition flip {A B C} (f : A -> B -> C) x y := f y x.
(** Application as a combinator. *)
Definition apply {A B} (f : A -> B) (x : A) := f x.
(** Curryfication of [prod] is defined in [Logic.Datatypes]. *)
Implicit Arguments prod_curry [[A] [B] [C]].
Implicit Arguments prod_uncurry [[A] [B] [C]].
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_dtl_pad(bypass_enable ,so ,por_l ,clock_dr ,bypass_in ,
serial_in ,update_dr ,clk ,reset_l ,hiz_l ,ps_select ,out_type ,
shift_dr ,rst_io_l ,rst_val_up ,bso ,serial_out ,bsr_si ,rst_val_dn
,mode_ctl ,si ,oe ,data ,se ,up_open ,down_25 ,to_core ,ref ,pad ,
vddo ,cbu ,cbd ,sel_bypass );
input [8:1] cbu ;
input [8:1] cbd ;
output so ;
output bso ;
output serial_out ;
output to_core ;
input bypass_enable ;
input por_l ;
input clock_dr ;
input bypass_in ;
input serial_in ;
input update_dr ;
input clk ;
input reset_l ;
input hiz_l ;
input ps_select ;
input out_type ;
input shift_dr ;
input rst_io_l ;
input rst_val_up ;
input bsr_si ;
input rst_val_dn ;
input mode_ctl ;
input si ;
input oe ;
input data ;
input se ;
input up_open ;
input down_25 ;
input ref ;
input vddo ;
input sel_bypass ;
inout pad ;
wire pad_dn25_l ;
wire cmsi_clk_en_l ;
wire se_buf ;
wire q_up_pad ;
wire net82 ;
wire bsr_dn_l ;
wire so_bscan ;
wire q_dn_pad_l ;
wire rcvr_data_to_bsr ;
wire pad_clk_en_l ;
wire por ;
wire bsr_data_to_core ;
wire q_dn25_pad_l ;
wire cmsi_l ;
wire bsr_dn25_l ;
wire pad_up ;
wire bsr_up ;
wire pad_dn_l ;
bw_io_dtlhstl_rcv dtlhstl_rcv (
.out (to_core ),
.so (so ),
.pad (pad ),
.ref (ref ),
.clk (clk ),
.pad_clk_en_l (pad_clk_en_l ),
.cmsi_clk_en_l (cmsi_clk_en_l ),
.cmsi_l (cmsi_l ),
.se_buf (se_buf ),
.vddo (vddo ) );
bw_io_dtl_edgelogic dtl_edge (
.pad_clk_en_l (pad_clk_en_l ),
.cmsi_clk_en_l (cmsi_clk_en_l ),
.bsr_dn25_l (q_dn25_pad_l ),
.pad_dn_l (pad_dn_l ),
.pad_dn25_l (pad_dn25_l ),
.bsr_up (q_up_pad ),
.bsr_mode (mode_ctl ),
.bsr_data_to_core (bsr_data_to_core ),
.por_l (por_l ),
.bsr_dn_l (q_dn_pad_l ),
.se_buf (se_buf ),
.cmsi_l (cmsi_l ),
.por (por ),
.reset_l (reset_l ),
.sel_bypass (sel_bypass ),
.up_open (up_open ),
.oe (oe ),
.down_25 (down_25 ),
.clk (clk ),
.data (data ),
.se (se ),
.si (so_bscan ),
.pad_up (pad_up ) );
bw_io_dtl_bscan bscan (
.bypass_enable (bypass_enable ),
.q25_dn_pad_l (q_dn25_pad_l ),
.q_up_mux (bsr_up ),
.rst_val_dn (rst_val_dn ),
.q_dn_mux_l (bsr_dn_l ),
.mode_ctl (mode_ctl ),
.hiz_l (hiz_l ),
.rst_io_l (rst_io_l ),
.bsr_si (bsr_si ),
.clk (clk ),
.bsr_data_to_core (bsr_data_to_core ),
.shift_dr (shift_dr ),
.up_open (up_open ),
.sel_data_n (net82 ),
.q_up_pad (q_up_pad ),
.rcvr_data_to_bsr (rcvr_data_to_bsr ),
.clock_dr (clock_dr ),
.serial_out (serial_out ),
.down_25 (down_25 ),
.q_dn_pad_l (q_dn_pad_l ),
.bypass_in (bypass_in ),
.rst_val_up (rst_val_up ),
.update_dr (update_dr ),
.serial_in (serial_in ),
.bsr_so (bso ),
.ps_select (ps_select ),
.q25_dn_mux_l (bsr_dn25_l ),
.out_type (out_type ),
.se (se ) );
bw_io_dtl_drv dtl_drv (
.cbu ({cbu } ),
.cbd ({cbd } ),
.pad (pad ),
.sel_data_n (net82 ),
.pad_up (pad_up ),
.pad_dn_l (pad_dn_l ),
.pad_dn25_l (pad_dn25_l ),
.por (por ),
.bsr_up (bsr_up ),
.bsr_dn_l (bsr_dn_l ),
.bsr_dn25_l (bsr_dn25_l ),
.vddo (vddo ) );
bw_io_dtl_rcv_dc dc_rcv (
.so (rcvr_data_to_bsr ),
.pad (pad ),
.ref (ref ),
.vddo (vddo ) );
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: font.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module font (
address,
clock,
q);
input [10:0] address;
input clock;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire [5:0] q = sub_wire0[5:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({6{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "font.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 6,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "font.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "6"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "font.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q_a 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL font.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// chris_slave.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module chris_slave (
input wire [3:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire LEDR // LEDR.ledr
);
// TODO: Auto-generated HDL template
reg [31:0] reg_out;
assign avs_s0_readdata = reg_out;
reg Reg_Status_Read;
reg Reg_Status_Write;
reg [31:0] reg_value[8:0];
reg led_out;
reg [31:0] reg_status;
reg [31:0] reg_res;
//
//
//
assign avs_s0_waitrequest = Reg_Status_Read&Reg_Status_Write;
assign LEDR = led_out;
reg reg_module_caculation_end;
reg reg_modue_caculating_start;
reg reg_module_end;
reg reg_module_start;
convolution_core instance_convolution(.clk(clock_clk),
.reset(reset_reset),
.value0(reg_value[0]),
.value1(reg_value[1]),
.value2(reg_value[2]),
.value3(reg_value[3]),
.value4(reg_value[4]),
.value5(reg_value[5]),
.value6(reg_value[6]),
.value7(reg_value[7]),
.value8(reg_value[8]),
.caculating_start(reg_modue_caculating_start),
.caculating_done(reg_module_caculation_end),
.res_done(reg_module_end),
.ret(reg_res)
);
reg [3:0] reg_current_status, reg_next_status;
parameter IDLE = 4'b0001;
parameter CALCULATING = 4'b0010;
parameter WAITTING = 4'b0100;
parameter FINISH = 4'b1000;
// machine status
always@(posedge clock_clk)
begin
if(reset_reset)
reg_current_status <= IDLE;
else
reg_current_status <= reg_next_status;
end
// machine's next status
always@(reg_current_status or reg_read_done or reg_module_caculation_end or reg_write_done or reset_reset)
begin
if(reset_reset)
reg_next_status = IDLE;
else
begin
case(reg_current_status)
IDLE:reg_next_status = reg_read_done?CALCULATING:IDLE;
CALCULATING:reg_next_status = reg_module_caculation_end?WAITTING:CALCULATING;
WAITTING:reg_next_status = reg_write_done?FINISH:WAITTING;
FINISH: reg_next_status = IDLE;
default: reg_next_status = IDLE;
endcase
end
end
always@(posedge clock_clk) begin
if (reset_reset) begin
led_out <= 1'b0;
end else begin
case(reg_current_status)
IDLE: begin
reg_module_start<= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
end
CALCULATING: begin
led_out <= 1'b1;
reg_module_start <= 1'b1;
reg_modue_caculating_start <= 1'b1;
end
WAITTING:begin
reg_modue_caculating_start <= 1'b0;
reg_module_end <= 1'b1;
end
FINISH:begin
reg_module_start <= 1'b0;
reg_module_end <= 1'b0;
reg_modue_caculating_start <= 1'b0;
led_out <= 1'b0;
end
default:begin
end
endcase
end
end
// WRITE LOGIC
//
reg reg_read_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Write <= 1'b1;
reg_value[0] <= 32'h00000000;
reg_value[1] <= 32'h00000000;
reg_value[2] <= 32'h00000000;
reg_value[3] <= 32'h00000000;
reg_value[4] <= 32'h00000000;
reg_value[5] <= 32'h00000000;
reg_value[6] <= 32'h00000000;
reg_value[7] <= 32'h00000000;
reg_value[8] <= 32'h00000000;
reg_read_done <= 1'b0;
end else if (!avs_s0_waitrequest && avs_s0_write) begin
case (avs_s0_address[3:0])
4'b0000: reg_value[0] <= avs_s0_writedata;
4'b0001: reg_value[1] <= avs_s0_writedata;
4'b0010: reg_value[2] <= avs_s0_writedata;
4'b0011: reg_value[3] <= avs_s0_writedata;
4'b0100: reg_value[4] <= avs_s0_writedata;
4'b0101: reg_value[5] <= avs_s0_writedata;
4'b0110: reg_value[6] <= avs_s0_writedata;
4'b0111: reg_value[7] <= avs_s0_writedata;
4'b1000:begin
reg_value[8] <= avs_s0_writedata;
reg_read_done <= 1'b1; // read done;
end
endcase
Reg_Status_Write <= 1'b1;
end else if (avs_s0_waitrequest && avs_s0_write && reg_module_start == 1'b0)begin
Reg_Status_Write <= 1'b0;
end else begin
//revert reg_read_done to 0 at here when it's done /
if(reg_module_end) begin
reg_read_done <= 1'b0;
end
Reg_Status_Write <= 1'b1;
end
//
// x and z values are don't-care's
// READ LOGIC
reg reg_write_done;
always @(posedge clock_clk)
if (reset_reset) begin
Reg_Status_Read <= 1'b1;
end else if (!avs_s0_waitrequest && avs_s0_read) begin
Reg_Status_Read <= 1'b1;
reg_write_done <= 1'b1;
end else if(avs_s0_waitrequest && avs_s0_read && reg_module_caculation_end) begin
case (avs_s0_address[3:0])
4'b0000: reg_out <= reg_value[0];
4'b0001: reg_out <= reg_value[1];
4'b0010: reg_out <= reg_value[2];
4'b0011: reg_out <= reg_value[3];
4'b0100: reg_out <= reg_value[4];
4'b0101: reg_out <= reg_value[5];
4'b0110: reg_out <= reg_value[6];
4'b0111: reg_out <= reg_value[7];
4'b1000: reg_out <= reg_value[8];
4'b1001: reg_out <= reg_res;
default:reg_out <= 32'hffffffff;
endcase
Reg_Status_Read <= 1'b0;
end else begin
Reg_Status_Read <= 1'b1;
if (reg_module_end) begin
reg_write_done <= 1'b0;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ea_e
//
// Generated
// by: wig
// on: Wed Jun 7 16:54:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ea_e.v,v 1.5 2006/06/22 07:19:59 wig Exp $
// $Date: 2006/06/22 07:19:59 $
// $Log: inst_ea_e.v,v $
// Revision 1.5 2006/06/22 07:19:59 wig
// Updated testcases and extended MixTest.pl to also verify number of created files.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
//
// Generator: mix_0.pl Revision: 1.45 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ea_e
//
// No user `defines in this module
`define cp_lcmd_2_tolow_c 1'b0
module inst_ea_e
//
// Generated Module inst_ea
//
(
p_mix_c_addr_12_0_gi,
p_mix_c_bus_in_31_0_gi,
p_mix_cp_lcmd_2_6_6_gi,
p_mix_cp_lcmd_3_6_6_gi,
p_mix_cp_lcmd_6_6_gi,
p_mix_tmi_sbist_fail_11_10_gi,
p_mix_tmi_sbist_fail_9_0_go,
p_mix_unsplice_a1_no3_125_0_gi,
p_mix_unsplice_a1_no3_127_127_gi,
p_mix_unsplice_a2_all128_127_0_gi,
p_mix_unsplice_a3_up100_100_0_gi,
p_mix_unsplice_a4_mid100_99_2_gi,
p_mix_unsplice_a5_midp100_99_2_gi,
p_mix_unsplice_bad_a_1_1_gi,
p_mix_unsplice_bad_b_1_0_gi,
p_mix_v_select_2_2_gi,
p_mix_v_select_5_5_gi,
p_mix_widemerge_a1_31_0_gi,
p_mix_widesig_31_0_gi,
p_mix_widesig_r_0_gi,
p_mix_widesig_r_10_gi,
p_mix_widesig_r_11_gi,
p_mix_widesig_r_12_gi,
p_mix_widesig_r_13_gi,
p_mix_widesig_r_14_gi,
p_mix_widesig_r_15_gi,
p_mix_widesig_r_16_gi,
p_mix_widesig_r_17_gi,
p_mix_widesig_r_18_gi,
p_mix_widesig_r_19_gi,
p_mix_widesig_r_1_gi,
p_mix_widesig_r_20_gi,
p_mix_widesig_r_21_gi,
p_mix_widesig_r_22_gi,
p_mix_widesig_r_23_gi,
p_mix_widesig_r_24_gi,
p_mix_widesig_r_25_gi,
p_mix_widesig_r_26_gi,
p_mix_widesig_r_27_gi,
p_mix_widesig_r_28_gi,
p_mix_widesig_r_29_gi,
p_mix_widesig_r_2_gi,
p_mix_widesig_r_30_gi,
p_mix_widesig_r_3_gi,
p_mix_widesig_r_4_gi,
p_mix_widesig_r_5_gi,
p_mix_widesig_r_6_gi,
p_mix_widesig_r_7_gi,
p_mix_widesig_r_8_gi,
p_mix_widesig_r_9_gi,
video_i
);
// Generated Module Inputs:
input [12:0] p_mix_c_addr_12_0_gi;
input [31:0] p_mix_c_bus_in_31_0_gi;
input p_mix_cp_lcmd_2_6_6_gi;
input p_mix_cp_lcmd_3_6_6_gi;
input p_mix_cp_lcmd_6_6_gi;
input [1:0] p_mix_tmi_sbist_fail_11_10_gi;
input [125:0] p_mix_unsplice_a1_no3_125_0_gi;
input p_mix_unsplice_a1_no3_127_127_gi;
input [127:0] p_mix_unsplice_a2_all128_127_0_gi;
input [100:0] p_mix_unsplice_a3_up100_100_0_gi;
input [97:0] p_mix_unsplice_a4_mid100_99_2_gi;
input [97:0] p_mix_unsplice_a5_midp100_99_2_gi;
input p_mix_unsplice_bad_a_1_1_gi;
input [1:0] p_mix_unsplice_bad_b_1_0_gi;
input p_mix_v_select_2_2_gi;
input p_mix_v_select_5_5_gi;
input [31:0] p_mix_widemerge_a1_31_0_gi;
input [31:0] p_mix_widesig_31_0_gi;
input p_mix_widesig_r_0_gi;
input p_mix_widesig_r_10_gi;
input p_mix_widesig_r_11_gi;
input p_mix_widesig_r_12_gi;
input p_mix_widesig_r_13_gi;
input p_mix_widesig_r_14_gi;
input p_mix_widesig_r_15_gi;
input p_mix_widesig_r_16_gi;
input p_mix_widesig_r_17_gi;
input p_mix_widesig_r_18_gi;
input p_mix_widesig_r_19_gi;
input p_mix_widesig_r_1_gi;
input p_mix_widesig_r_20_gi;
input p_mix_widesig_r_21_gi;
input p_mix_widesig_r_22_gi;
input p_mix_widesig_r_23_gi;
input p_mix_widesig_r_24_gi;
input p_mix_widesig_r_25_gi;
input p_mix_widesig_r_26_gi;
input p_mix_widesig_r_27_gi;
input p_mix_widesig_r_28_gi;
input p_mix_widesig_r_29_gi;
input p_mix_widesig_r_2_gi;
input p_mix_widesig_r_30_gi;
input p_mix_widesig_r_3_gi;
input p_mix_widesig_r_4_gi;
input p_mix_widesig_r_5_gi;
input p_mix_widesig_r_6_gi;
input p_mix_widesig_r_7_gi;
input p_mix_widesig_r_8_gi;
input p_mix_widesig_r_9_gi;
input [3:0] video_i;
// Generated Module Outputs:
output [9:0] p_mix_tmi_sbist_fail_9_0_go;
// Generated Wires:
wire [12:0] p_mix_c_addr_12_0_gi;
wire [31:0] p_mix_c_bus_in_31_0_gi;
wire p_mix_cp_lcmd_2_6_6_gi;
wire p_mix_cp_lcmd_3_6_6_gi;
wire p_mix_cp_lcmd_6_6_gi;
wire [1:0] p_mix_tmi_sbist_fail_11_10_gi;
wire [9:0] p_mix_tmi_sbist_fail_9_0_go;
wire [125:0] p_mix_unsplice_a1_no3_125_0_gi;
wire p_mix_unsplice_a1_no3_127_127_gi;
wire [127:0] p_mix_unsplice_a2_all128_127_0_gi;
wire [100:0] p_mix_unsplice_a3_up100_100_0_gi;
wire [97:0] p_mix_unsplice_a4_mid100_99_2_gi;
wire [97:0] p_mix_unsplice_a5_midp100_99_2_gi;
wire p_mix_unsplice_bad_a_1_1_gi;
wire [1:0] p_mix_unsplice_bad_b_1_0_gi;
wire p_mix_v_select_2_2_gi;
wire p_mix_v_select_5_5_gi;
wire [31:0] p_mix_widemerge_a1_31_0_gi;
wire [31:0] p_mix_widesig_31_0_gi;
wire p_mix_widesig_r_0_gi;
wire p_mix_widesig_r_10_gi;
wire p_mix_widesig_r_11_gi;
wire p_mix_widesig_r_12_gi;
wire p_mix_widesig_r_13_gi;
wire p_mix_widesig_r_14_gi;
wire p_mix_widesig_r_15_gi;
wire p_mix_widesig_r_16_gi;
wire p_mix_widesig_r_17_gi;
wire p_mix_widesig_r_18_gi;
wire p_mix_widesig_r_19_gi;
wire p_mix_widesig_r_1_gi;
wire p_mix_widesig_r_20_gi;
wire p_mix_widesig_r_21_gi;
wire p_mix_widesig_r_22_gi;
wire p_mix_widesig_r_23_gi;
wire p_mix_widesig_r_24_gi;
wire p_mix_widesig_r_25_gi;
wire p_mix_widesig_r_26_gi;
wire p_mix_widesig_r_27_gi;
wire p_mix_widesig_r_28_gi;
wire p_mix_widesig_r_29_gi;
wire p_mix_widesig_r_2_gi;
wire p_mix_widesig_r_30_gi;
wire p_mix_widesig_r_3_gi;
wire p_mix_widesig_r_4_gi;
wire p_mix_widesig_r_5_gi;
wire p_mix_widesig_r_6_gi;
wire p_mix_widesig_r_7_gi;
wire p_mix_widesig_r_8_gi;
wire p_mix_widesig_r_9_gi;
wire [3:0] video_i;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [12:0] c_addr; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] c_bus_in; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] cp_lcmd; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] cp_lcmd_2; // __W_PORT_SIGNAL_MAP_REQ
wire [5:0] cp_lcmd_2_tolow;
wire [6:0] cp_lcmd_3; // __W_PORT_SIGNAL_MAP_REQ
wire [12:0] tmi_sbist_fail; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_a1_no3; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_a2_all128; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_a3_up100; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_a4_mid100; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_a5_midp100; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_bad_a; // __W_PORT_SIGNAL_MAP_REQ
wire [127:0] unsplice_bad_b; // __W_PORT_SIGNAL_MAP_REQ
wire [5:0] v_select; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] widemerge_a1; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] widesig; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_0; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_1; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_10; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_11; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_12; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_13; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_14; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_15; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_16; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_17; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_18; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_19; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_2; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_20; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_21; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_22; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_23; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_24; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_25; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_26; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_27; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_28; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_29; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_3; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_30; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_4; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_5; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_6; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_7; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_8; // __W_PORT_SIGNAL_MAP_REQ
wire widesig_r_9; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign c_addr = p_mix_c_addr_12_0_gi; // __I_I_BUS_PORT
assign c_bus_in = p_mix_c_bus_in_31_0_gi; // __I_I_BUS_PORT
assign cp_lcmd[6] = p_mix_cp_lcmd_6_6_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign cp_lcmd_2[6] = p_mix_cp_lcmd_2_6_6_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign cp_lcmd_2_tolow = `cp_lcmd_2_tolow_c;
assign cp_lcmd_3[6] = p_mix_cp_lcmd_3_6_6_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign tmi_sbist_fail[11:10] = p_mix_tmi_sbist_fail_11_10_gi[1:0]; // __I_I_SLICE_PORT
assign p_mix_tmi_sbist_fail_9_0_go[9:0] = tmi_sbist_fail[9:0]; // __I_O_SLICE_PORT
assign unsplice_a1_no3[125:0] = p_mix_unsplice_a1_no3_125_0_gi[125:0]; // __I_I_SLICE_PORT
assign unsplice_a1_no3[127] = p_mix_unsplice_a1_no3_127_127_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign unsplice_a2_all128 = p_mix_unsplice_a2_all128_127_0_gi; // __I_I_BUS_PORT
assign unsplice_a3_up100[100:0] = p_mix_unsplice_a3_up100_100_0_gi[100:0]; // __I_I_SLICE_PORT
assign unsplice_a4_mid100[99:2] = p_mix_unsplice_a4_mid100_99_2_gi[97:0]; // __I_I_SLICE_PORT
assign unsplice_a5_midp100[99:2] = p_mix_unsplice_a5_midp100_99_2_gi[97:0]; // __I_I_SLICE_PORT
assign unsplice_bad_a[1] = p_mix_unsplice_bad_a_1_1_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign unsplice_bad_b[1:0] = p_mix_unsplice_bad_b_1_0_gi[1:0]; // __I_I_SLICE_PORT
assign v_select[5] = p_mix_v_select_5_5_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign v_select[2] = p_mix_v_select_2_2_gi; // __I_I_SLICE_PORT // __W_SINGLE_BIT_SLICE
assign widemerge_a1 = p_mix_widemerge_a1_31_0_gi; // __I_I_BUS_PORT
assign widesig = p_mix_widesig_31_0_gi; // __I_I_BUS_PORT
assign widesig_r_0 = p_mix_widesig_r_0_gi; // __I_I_BIT_PORT
assign widesig_r_1 = p_mix_widesig_r_1_gi; // __I_I_BIT_PORT
assign widesig_r_10 = p_mix_widesig_r_10_gi; // __I_I_BIT_PORT
assign widesig_r_11 = p_mix_widesig_r_11_gi; // __I_I_BIT_PORT
assign widesig_r_12 = p_mix_widesig_r_12_gi; // __I_I_BIT_PORT
assign widesig_r_13 = p_mix_widesig_r_13_gi; // __I_I_BIT_PORT
assign widesig_r_14 = p_mix_widesig_r_14_gi; // __I_I_BIT_PORT
assign widesig_r_15 = p_mix_widesig_r_15_gi; // __I_I_BIT_PORT
assign widesig_r_16 = p_mix_widesig_r_16_gi; // __I_I_BIT_PORT
assign widesig_r_17 = p_mix_widesig_r_17_gi; // __I_I_BIT_PORT
assign widesig_r_18 = p_mix_widesig_r_18_gi; // __I_I_BIT_PORT
assign widesig_r_19 = p_mix_widesig_r_19_gi; // __I_I_BIT_PORT
assign widesig_r_2 = p_mix_widesig_r_2_gi; // __I_I_BIT_PORT
assign widesig_r_20 = p_mix_widesig_r_20_gi; // __I_I_BIT_PORT
assign widesig_r_21 = p_mix_widesig_r_21_gi; // __I_I_BIT_PORT
assign widesig_r_22 = p_mix_widesig_r_22_gi; // __I_I_BIT_PORT
assign widesig_r_23 = p_mix_widesig_r_23_gi; // __I_I_BIT_PORT
assign widesig_r_24 = p_mix_widesig_r_24_gi; // __I_I_BIT_PORT
assign widesig_r_25 = p_mix_widesig_r_25_gi; // __I_I_BIT_PORT
assign widesig_r_26 = p_mix_widesig_r_26_gi; // __I_I_BIT_PORT
assign widesig_r_27 = p_mix_widesig_r_27_gi; // __I_I_BIT_PORT
assign widesig_r_28 = p_mix_widesig_r_28_gi; // __I_I_BIT_PORT
assign widesig_r_29 = p_mix_widesig_r_29_gi; // __I_I_BIT_PORT
assign widesig_r_3 = p_mix_widesig_r_3_gi; // __I_I_BIT_PORT
assign widesig_r_30 = p_mix_widesig_r_30_gi; // __I_I_BIT_PORT
assign widesig_r_4 = p_mix_widesig_r_4_gi; // __I_I_BIT_PORT
assign widesig_r_5 = p_mix_widesig_r_5_gi; // __I_I_BIT_PORT
assign widesig_r_6 = p_mix_widesig_r_6_gi; // __I_I_BIT_PORT
assign widesig_r_7 = p_mix_widesig_r_7_gi; // __I_I_BIT_PORT
assign widesig_r_8 = p_mix_widesig_r_8_gi; // __I_I_BIT_PORT
assign widesig_r_9 = p_mix_widesig_r_9_gi; // __I_I_BIT_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eaa
inst_eaa_e inst_eaa (
.c_addr_i(c_addr),
.c_bus_i(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.mbist_clut_fail_o(tmi_sbist_fail[8]),
.mbist_fifo_fail_o(tmi_sbist_fail[9]),
.unsplice_a1_no3[127:4](unsplice_a1_no3[125:2]), // leaves 3 unconnected// __E_CANNOT_COMBINE_SPLICES
.unsplice_a1_no3[1:0](unsplice_a1_no3[1:0]), // leaves 3 unconnected// __E_CANNOT_COMBINE_SPLICES
.unsplice_a1_no3[2](unsplice_a1_no3[127]), // leaves 3 unconnected// __E_CANNOT_COMBINE_SPLICES
.unsplice_a2_all128(unsplice_a2_all128), // full 128 bit port
.unsplice_a3_up100(unsplice_a3_up100[100:0]), // connect 100 bits from 0
.unsplice_a4_mid100(unsplice_a4_mid100[99:2]), // connect mid 100 bits
.unsplice_a5_midp100(unsplice_a5_midp100[99:2]), // connect mid 100 bits
.unsplice_bad_b({ unsplice_bad_b[1:0], unsplice_bad_b[1:0] }), // // # conflict (x2) // __I_COMBINE_SPLICES
.video_p_0(video_i[0]),
.widemerge_a1_p(widemerge_a1),
.widesig_p({ widesig_r_30, widesig_r_29, widesig_r_28, widesig_r_27, widesig_r_26, widesig_r_25, widesig_r_24, widesig_r_23, widesig_r_22, widesig_r_21, widesig_r_20, widesig_r_19, widesig_r_18, widesig_r_17, widesig_r_16, widesig_r_15, widesig_r_14, widesig_r_13, widesig_r_12, widesig_r_11, widesig_r_10, widesig_r_9, widesig_r_8, widesig_r_7, widesig_r_6, widesig_r_5, widesig_r_4, widesig_r_3, widesig_r_2, widesig_r_1, widesig_r_0 }), // __I_BIT_TO_BUSPORT (x31) // __I_COMBINE_SPLICES
.widesig_p_0(widesig[0]),
.widesig_p_1(widesig[1]),
.widesig_p_10(widesig[10]),
.widesig_p_11(widesig[11]),
.widesig_p_12(widesig[12]),
.widesig_p_13(widesig[13]),
.widesig_p_14(widesig[14]),
.widesig_p_15(widesig[15]),
.widesig_p_16(widesig[16]),
.widesig_p_17(widesig[17]),
.widesig_p_18(widesig[18]),
.widesig_p_19(widesig[19]),
.widesig_p_2(widesig[2]),
.widesig_p_20(widesig[20]),
.widesig_p_21(widesig[21]),
.widesig_p_22(widesig[22]),
.widesig_p_23(widesig[23]),
.widesig_p_24(widesig[24]),
.widesig_p_25(widesig[25]),
.widesig_p_26(widesig[26]),
.widesig_p_27(widesig[27]),
.widesig_p_28(widesig[28]),
.widesig_p_29(widesig[29]),
.widesig_p_3(widesig[3]),
.widesig_p_30(widesig[30]),
.widesig_p_31(widesig[31]),
.widesig_p_4(widesig[4]),
.widesig_p_5(widesig[5]),
.widesig_p_6(widesig[6]),
.widesig_p_7(widesig[7]),
.widesig_p_8(widesig[8]),
.widesig_p_9(widesig[9])
// __E_PRINTCONN unsplice_bad_a => unsplice_bad_a
);
// End of Generated Instance Port Map for inst_eaa
// Generated Instance Port Map for inst_eab
inst_eab_e inst_eab (
.c_add(c_addr),
.c_bus_in(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.v_select({ v_select[5], 1'b0, 1'b0, v_select[2], 1'b0, 1'b0 }), // // RequestBusinterface:RequestBus#6(VPU)VPUinterface (x2) // __I_BIT_TO_BUSPORT (x4) // __I_COMBINE_SPLICES
.video_p_1(video_i[1])
);
// End of Generated Instance Port Map for inst_eab
// Generated Instance Port Map for inst_eac
inst_eac_e inst_eac (
.adp_bist_fail(tmi_sbist_fail[0]),
.c_addr(c_addr),
.c_bus_in(c_bus_in), // CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
.cp_lcmd({ cp_lcmd[6], 6'b000000 }), // __W_PORT // // GuestBusLBC(memorymappedI/O)Interface // __I_COMBINE_SPLICES
.cp_lcmd_2({ cp_lcmd_2[6], cp_lcmd_2_tolow }), // __W_PORT // // Second way to wire to zero / GuestBusLBC(memorymappedI/O)Interface // __I_COMBINE_SPLICES
.cp_lcmd_p({ cp_lcmd_3[6], 6'b000000 }), // __W_PORT // // Signal name != port name // __I_COMBINE_SPLICES
.cpu_bist_fail(tmi_sbist_fail[1]),
.cvi_sbist_fail0(tmi_sbist_fail[10]),
.cvi_sbist_fail1(tmi_sbist_fail[11]),
.ema_bist_fail(tmi_sbist_fail[7]),
.ga_sbist_fail0(tmi_sbist_fail[8]),
.ga_sbist_fail1(tmi_sbist_fail[9]),
.ifu_bist_fail(tmi_sbist_fail[6]),
.mcu_bist_fail(tmi_sbist_fail[2]),
.pdu_bist_fail0(tmi_sbist_fail[3]),
.pdu_bist_fail1(tmi_sbist_fail[4]),
.tsd_bist_fail(tmi_sbist_fail[5]),
.video_p_2(video_i[2])
);
// End of Generated Instance Port Map for inst_eac
// Generated Instance Port Map for inst_ead
inst_ead_e inst_ead (
.video_p_3(video_i[3])
);
// End of Generated Instance Port Map for inst_ead
endmodule
//
// End of Generated Module rtl of inst_ea_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_64_1.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module asyn_64_1 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty);
input aclr;
input [0:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [0:0] q;
output rdempty;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "1"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 1 0 INPUT NODEFVAL "data[0..0]"
// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 1 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_64_1_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_TB_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_TB_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__macro_sparecell.v"
module top();
// Inputs are registered
reg VGND;
reg VNB;
reg VPB;
reg VPWR;
// Outputs are wires
wire LO;
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hd__macro_sparecell dut (.VGND(VGND), .VNB(VNB), .VPB(VPB), .VPWR(VPWR), .LO(LO));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_TB_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire sys_clk_p,
input wire sys_clk_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// Clock and reset
wire sys_clk_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_ibufgds_inst(
.I(sys_clk_p),
.IB(sys_clk_n),
.O(sys_clk_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 450 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.100),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(sys_clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
wire ledu_int;
wire ledl_int;
wire ledd_int;
wire ledr_int;
wire ledc_int;
wire [7:0] led_int;
wire uart_rxd_int;
wire uart_txd_int;
wire uart_rts_int;
wire uart_cts_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_txd,
uart_rts}),
.out({uart_txd_int,
uart_rts_int})
);
assign ledu = ledu_int;
assign ledl = ledl_int;
assign ledd = ledd_int;
assign ledr = ledr_int;
assign ledc = ledc_int;
//assign led = led_int;
assign uart_rxd = uart_rxd_int;
assign uart_cts = uart_cts_int;
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire phy_sgmii_mgtrefclk;
wire phy_sgmii_txoutclk;
wire phy_sgmii_userclk2;
IBUFDS_GTXE1
phy_sgmii_ibufds_mgtrefclk (
.CEB (1'b0),
.I (phy_sgmii_clk_p),
.IB (phy_sgmii_clk_n),
.O (phy_sgmii_mgtrefclk),
.ODIV2 ()
);
BUFG
phy_sgmii_bufg_userclk2 (
.I (phy_sgmii_txoutclk),
.O (phy_sgmii_userclk2)
);
assign phy_gmii_clk_int = phy_sgmii_userclk2;
sync_reset #(
.N(4)
)
sync_reset_pcspma_inst (
.clk(phy_gmii_clk_int),
.rst(rst_125mhz_int),
.out(phy_gmii_rst_int)
);
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_eth_pcs_pma_v11_5_block
eth_pcspma (
// Transceiver Interface
.mgtrefclk (phy_sgmii_mgtrefclk),
.gtx_reset_clk (clk_125mhz_int),
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
.txoutclk (phy_sgmii_txoutclk),
.userclk2 (phy_sgmii_userclk2),
.pma_reset (rst_125mhz_int),
// GMII Interface
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Management: Alternative to MDIO Interface
.configuration_vector (pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (pcspma_an_config_vector),
.an_restart_config (1'b0),
.link_timer_value (9'd50),
// Speed Control
.speed_is_10_100 (pcspma_status_speed != 2'b10),
.speed_is_100 (pcspma_status_speed == 2'b01),
// General IO's
.status_vector (pcspma_status_vector),
.reset (rst_125mhz_int),
.signal_detect (1'b1)
);
// SGMII interface debug:
// SW1:1 (sw[0]) off for payload byte, on for status vector
// SW1:2 (sw[1]) off for LSB of status vector, on for MSB
assign led = sw[7] ? (sw[6] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk_125mhz(clk_125mhz_int),
.rst_125mhz(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.ledu(ledu_int),
.ledl(ledl_int),
.ledd(ledd_int),
.ledr(ledr_int),
.ledc(ledc_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_3_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_3_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333374} /><PLL domain={Memory} vco={1066.666748} /><PLL domain={IO} vco={1000.000000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
module processing_system7_v5_3_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484"
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TD_I,
//# #9 JTAG_TD_I and JTAG_TD_O should be separate
output PJTAG_TD_T,
output PJTAG_TD_O,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [31:0] TRACE_DATA,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input [3:0] FTMT_F2P_TRIG,
output [3:0] FTMT_F2P_TRIGACK,
input [31:0] FTMT_F2P_DEBUG,
input [3:0] FTMT_P2F_TRIGACK,
output [3:0] FTMT_P2F_TRIG,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TD_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_3_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// EMIO PJTAG
assign PJTAG_TD_T = ~ PJTAG_TD_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TD_O),
.EMIOPJTAGTDTN (PJTAG_TD_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL),
.EMIOTRACEDATA (TRACE_DATA),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK (FTMT_F2P_TRIGACK),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG (FTMT_P2F_TRIG ),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TD_I),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG (FTMT_F2P_TRIG ),
.FTMTP2FTRIGACK (FTMT_P2F_TRIGACK),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TD_O),
.EMIOPJTAGTDTN (PJTAG_TD_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL),
.EMIOTRACEDATA (TRACE_DATA),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK (FTMT_F2P_TRIGACK),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG (FTMT_P2F_TRIG ),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TD_I),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG (FTMT_F2P_TRIG ),
.FTMTP2FTRIGACK (FTMT_P2F_TRIGACK),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_3_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_BEHAVIORAL_PP_V
|
// file: TemperatureMonitor_tb.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//----------------------------------------------------------------------------
// System Monitor wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// System Monitor wizard. Input clock is generated in this testbench.
//----------------------------------------------------------------------------
// This testbench does not implement checking of averaging and calibration
// Bipolar signals are applied with Vn = 0
`timescale 1ps/1ps
`define wait_drdy @(negedge DRDY_TB)
module TemperatureMonitor_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20*ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
// Input clock generation
always begin
DCLK_TB = #(PER1/2) ~DCLK_TB;
end
// Start of the testbench
initial
begin
$display ("Single channel avereraging is enabled");
$display ("This TB does not verify averaging");
$display ("Please increase the simulation duration to see complete waveform") ;
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
$display ("No status signals are pulled out to monitor the test status");
$display ("Simulation Stopped.");
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
TemperatureMonitor_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "nios_system_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 9: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
** -----------------------------------------------------------------------------**
** quantizator353.v
**
** Quantizator module for JPEG compressor
**
** Copyright (C) 2002-2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
`timescale 1ns/1ps
// will add extracted DC (8 bits) to data from DCT here that will make data 12 bits (signed) long.
// It will be possible to make a sequincial multiplier for DC - but I'll skip this opportunity now.
//********** TODO: switch to 16-bit tables instead of the 12-bit ones **************
module quantizator(clk, // pixel clock
en, // enable (0 resets counter)
sclk, // system clock, twqe, twce, ta,tdi - valid @negedge (ra, tdi - 2 cycles ahead
twqe, // enable write to a quantization table
twce, // enable write to a coring table
ta, // [6:0] table address
tdi, // [15:0] table data in (8 LSBs - quantization data)
// readback, // readback data
ctypei, // component type input (Y/C)
dci, // [7:0] - average value in a block - subtracted before DCT
first_stb, //this is first stb pulse in a frame
stb, // strobe that writes ctypei, dci
tsi, // table (quality) select [2:0]
pre_start,// marks first input pixel (one before)
first_in, // first block in (valid @ start)
first_out, // valid @ ds
di, // [11:0] pixel data in (signed)
do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
dv, // data out valid
ds, // data out strobe (one ahead of the start of dv)
dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
// dc_tdo_stb,
dcc_en, // enable dcc (sync to beginning of a new frame)
hfc_sel, // hight frequency components select [2:0] (includes components with both numbers >=hfc_sel
// hfc_sel == 3'h7 - now high frequency output - just 3 words - brightness and 2 color diffs
color_first, // first MCU in a frame
coring_num, // coring table pair number (0..7)
dcc_vld, // single cycle when dcc_data is valid
dcc_data, // [15:0] dc component data out (for reading by software)
n000, // input [7:0] number of zero pixels (255 if 256) - to be multiplexed with dcc
n255); // input [7:0] number of 0xff pixels (255 if 256) - to be multiplexed with dcc
input clk;
input en;
input sclk;
input twqe;
input twce;
input [ 8:0] ta;
input [15:0] tdi;
input ctypei;
input [ 8:0] dci; // now normal signed number
input first_stb; //this is first stb pulse in a frame
input stb;
input [ 2:0] tsi;
input pre_start;
input first_in; // first block in (valid @ start)
output first_out; // valid @ ds
input [12:0] di;
output[12:0] do;
output dv;
output ds;
output [15:0] dc_tdo;
input dcc_en;
input [2:0] hfc_sel;
input color_first;
input [2:0] coring_num; // Coring table number (0..7)
output dcc_vld;
output[15:0] dcc_data;
input [7:0] n000;
input [7:0] n255;
wire [3:0] tdco; // coring table output
reg [3:0] tbac; // coring memory table number (LSB - color)
reg coring_range; // input <16, use coring LUT
wire [15:0] tdo;
reg [ 9:0] tba; // table output (use) address
wire [15:0] zigzag_q;
reg wpage,
rpage;
wire [5:0] zwa;
reg [5:0] zra;
reg [12:0] qdo;
reg [12:0] qdo0;
reg zwe;
reg [12:0] d1;
reg [12:0] d2,d3; // registered data in, converted to sign+ absolute value
wire [27:0] qmul;
wire start_a;
reg [15:0] tdor;
reg [20:0] qmulr; // added 7 bits to total8 fractional for biasing/zero bin
wire start_out;
wire start_z;
reg ds;
reg dv;
reg [ 8:0] dc1; // registered DC average - with restored sign
// for fifo for ctype, dc
wire ctype;
wire [8:0] dc;
wire next_dv;
reg [ 5:0] start;
wire [15:0] dcc_data;
wire dcc_stb;
reg dcc_vld;
reg dcc_run;
reg dcc_first;
reg dcc_Y;
reg [1:0] ctype_prev;
reg [12:0] dcc_acc;
reg [12:0] hfc_acc;
wire hfc_en;
reg hfc_copy; // copy hfc_acc to dcc_acc
wire [10:0] d2_dct; // 11 bits enough, convetred to positive (before - 0 was in the middle - pixel value 128) - dcc only
reg sel_satnum; // select saturation numbers - dcc only
reg twqe_d; //twqe delayed (write MSW)
reg twce_d; //twce delayed (write MSW)
reg [15:0] dc_tdo;
reg [15:0] pre_dc_tdo;
wire copy_dc_tdo;
wire first_in; // first block in (valid @ pre_start)
reg first_interm, first_out; // valid @ ds
wire [2:0] ts;
wire [2:0] coring_sel;
reg [2:0] block_mem_ra;
reg [2:0] block_mem_wa;
reg [2:0] block_mem_wa_save;
reg [15:0] block_mem[0:7];
wire [15:0] block_mem_o=block_mem[block_mem_ra[2:0]];
assign dc[8:0]= block_mem_o[8:0];
assign ctype= block_mem_o[9];
assign ts[2:0]= block_mem_o[12:10];
assign coring_sel[2:0]= block_mem_o[15:13];
assign start_a=start[5];
assign start_z=start[4];
assign dcc_stb=start[2];
always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {coring_num[2:0],tsi[2:0], ctypei, dci[8:0]};
if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
if (stb && first_stb) block_mem_wa_save[2:0] <= block_mem_wa[2:0];
if (!en) block_mem_ra[2:0] <= 3'h0;
else if (pre_start) block_mem_ra[2:0] <= first_in?block_mem_wa_save[2:0]:(block_mem_ra[2:0] +1);
end
assign d2_dct[10:0]={!d2[11] ^ ctype_prev[0], d2[9:0]};
assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
assign do[12:0]=zigzag_q[12:0];
// assign qmul[23:0]=tdor[11:0]*d3[11:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin
d1[12:0] <= di[12:0];
//inv_sign
// dc1[8:0] <= start[0]?{{2{~dc[7]}},dc[6:0]}:9'b0; // sync to d1[8:0]ctype valid at start, not later
dc1[8:0] <= start[0]?dc[8:0]:9'b0; // sync to d1[8:0]ctype valid at start, not later
d2[12:0] <= {dc1[8],dc1[8:0],3'b0} + d1[12:0];
d3[12] <= d2[12];
d3[11:0] <= d2[12]? -d2[11:0]:d2[11:0];
if (start[0] || !en) tba[9:6] <= {ts[2:0],ctype};
/// TODO - make sure ctype switches at needed time (compensate if needed) *****************************************
if (start[3] || !en) tbac[3:0] <= {coring_sel[2:0],ctype}; // table number to use
if (start[0]) tba[5:0] <= 6'b0;
else if (tba[5:0]!=6'h3f) tba[5:0] <= tba[5:0]+1;
tdor[15:0] <= tdo[15:0]; // registered table data out
if (start[3]) pre_dc_tdo[15:0] <= tdor[15:0]; //16-bit q. tables)
if (copy_dc_tdo) dc_tdo[15:0] <= pre_dc_tdo[15:0];
qmulr[19:0] <= qmul[27:8]; // absolute value
qmulr[20] <= d3[12]; // sign
qdo0[12] <= qmulr[20]; // sign
// tdco[3:0] - same timing as qdo0;
// use lookup table from 8 bits of absolute value (4.4 - 4 fractional) to calculate 4 bit coring output that would replace output
// if input is less thahn 16. For larger values the true rounding will be used.
// Absolute values here have quantization coefficients already applied, so we can use the same coring table for all DCT coefficients.
// there are be 16 tables - 8 Y/C pairs to switch
qdo0[11:0] <= qmulr[19:8] + qmulr[7]; // true rounding of the absolute value
coring_range<= !(|qmulr[19:12]) && !(&qmulr[11:7]) ; // valid with qdo0
// qdo[11:0] <= coring_range? {8'h0,tdco[3:0]}:qdo0[11:0];
qdo[11:0] <= coring_range? (qdo0[12]?-{8'h0,tdco[3:0]}:{8'h0,tdco[3:0]}):(qdo0[12]?-qdo0[11:0]:qdo0[11:0]);
qdo[12] <= qdo0[12] && (!coring_range || (tdco[3:0]!=4'h0));
if (start_out) rpage <= wpage;
if (start_out) zra[5:0] <= 6'b0;
else if (zra[5:0]!=6'h3f) zra[5:0] <=zra[5:0]+1; // conserving energy
ds <= start_out;
dv <= next_dv;
if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm;
// zwe???
zwe <= en && (start_a || (zwe && (zwa[5:0]!=6'h3f)));
if (!en) wpage <= 1'b0;
else if (start_a) wpage <= ~wpage;
end
always @ (posedge clk) begin
sel_satnum <= dcc_run && (start[0]? (ctype_prev[1:0]==2'b10): sel_satnum);
hfc_copy <= dcc_run && (hfc_sel[2:0]!=3'h7) && (tba[5:0]==6'h1f) && ctype_prev[0] && ctype_prev[1];
start[5:0] <= {start[4:0], pre_start}; // needed?
if (!dcc_en) dcc_run <= 1'b0;
else if (start[0]) dcc_run <= 1'b1;
if (!dcc_en) ctype_prev[1:0] <= 2'b11;
else if (start[0]) ctype_prev[1:0] <= {ctype_prev[0],ctype && dcc_run};
if (dcc_stb || hfc_copy) dcc_acc[12:0] <= hfc_copy?
hfc_acc[12:0]:
{(d2_dct[10]&&ctype_prev[0]),(d2_dct[10]&&ctype_prev[0]),d2_dct[10:0]}+((ctype_prev[0] || ctype_prev[1])?13'h0:dcc_acc[12:0]);
if (!dcc_run || hfc_copy) hfc_acc <=13'b0;
else if (hfc_en) hfc_acc <= hfc_acc + {2'b0, d3[10:0]};
if (dcc_stb) dcc_first <= color_first && dcc_run && dcc_stb && ctype && !ctype_prev[0];
if (dcc_stb) dcc_Y <= dcc_run && dcc_stb && ctype && !ctype_prev[0];
dcc_vld <= (dcc_run && dcc_stb && (ctype || ctype_prev[0] || sel_satnum)) || hfc_copy;
end
SRL16 i_hfc_en (.Q(hfc_en), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(clk),
.D(((tba[2:0]>hfc_sel[2:0]) || (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0])); // dly=1+1
zigzag i_zigzag( .clk(clk),
.start(start_z),
.q(zwa[5:0]));
always @ (negedge sclk) twqe_d <= twqe;
always @ (negedge sclk) twce_d <= twce;
RAMB16_S18_S18 i_quant_table (
.DOA(tdo[15:0]), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({tba[9:6],tba[2:0],tba[5:3]}), // Port A 10-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.DOB(), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({ta[8:0],twqe_d}), // Port B 10-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(tdi[15:0]), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(1'b1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(twqe || twqe_d) // Port B Write Enable Input
);
RAMB16_S4_S18 i_coring_table (
.DOA(tdco[3:0]), // Port A 4-bit Data Output
.ADDRA({tbac[3:0],qmulr[11:4]}), // Port A 12-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(4'b0), // Port A 4-bit Data Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.DOB(), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({ta[8:0],twce_d}), // Port B 10-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(tdi[15:0]), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(1'b1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(twce || twce_d) // Port B Write Enable Input
);
RAMB16_S18_S18 i_zigzagbuf (
.DOA(), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({3'b0,wpage,zwa[5:0]}), // Port A 10-bit Address Input
.CLKA(clk), // Port A Clock
.DIA({3'b0,qdo[12:0]}), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(zwe), // Port A Write Enable Input
.DOB(zigzag_q[15:0]), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({3'b0,rpage,zra[5:0]}), // Port B 10-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(16'b0), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(next_dv), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
// Alternative ZigZag distributed ROM. More convinient, but extra resources. Use upper half of quantization table to save slices.
module zigzag (clk,
start,
q);
input clk, start;
output [5:0] q;
reg [5:0] a;
reg [5:0] q;
wire [4:0] rom_a;
wire [5:0] rom_q;
assign rom_a[4:0]=a[5]?(~a[4:0]):a[4:0];
always @ (posedge clk) begin
if (start) a[5:0] <= 6'b0;
// else a[5:0] <= a[5:0]+1; // may add if (a[5:0]!=6'h3f) to make cleaner simulation and conserve energy
else if (a[5:0]!=6'h3f) a[5:0] <= a[5:0]+1;
q[5:0] <= a[5]? (~rom_q[5:0]):rom_q[5:0];
end
ROM32X1 #(.INIT(32'hC67319CC)) i_z0 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[0]));
ROM32X1 #(.INIT(32'h611A7896)) i_z1 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[1]));
ROM32X1 #(.INIT(32'h6357A260)) i_z2 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[2]));
ROM32X1 #(.INIT(32'h4A040C18)) i_z3 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[3]));
ROM32X1 #(.INIT(32'h8C983060)) i_z4 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[4]));
ROM32X1 #(.INIT(32'hF0E0C080)) i_z5 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[5]));
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: test_engine_nic_output_block
-- Description: Bloque de salida de la interfaz de red. Se encarga de la
interaccion entre el elemento de procesamiento y el
router.
Este modulo toma el resultado del elemento de
procesamiento y lo empaquete en flits para su transporte
a travez de la red.
-- Dependencies: -- system.vh
-- test_engine_nic_output_control_unit.v
-- Parameters: -- CHANNEL_WIDTH: Numero de lineas de comunicacion
entre la interfaz de red y el
router.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 30 de noviembre 2015: Creacion
*/
`include "system.vh"
module test_engine_nic_output_block
(
input wire clk,
input wire reset,
// -- inputs from pn ----------------------------------------- >>>>>
input wire done_strobe_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] wordC_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] wordD_din,
input wire [`CHANNEL_WIDTH-1:0] shifted_header_din,
// -- to input block ----------------------------------------- >>>>>
output wire zero_credits_dout,
// -- output port -------------------------------------------- >>>>>
input wire credit_in_din,
output reg [`CHANNEL_WIDTH-1:0] output_channel_dout
);
/*
-- Instancia: test_engine_nic_output_control_unit
-- Descripcion: Unidad de control para el bloque de salida de la
interfaz de red. Este bloque se encarga de organizar la
salida de flits para su transporte por medio del router
de un nodo.
El control de creditos se encuentra implementado dentro
de este modulo.
*/
wire [2:0] output_selector;
test_engine_nic_output_control_unit test_engine_nic_output_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.done_strobe_din (done_strobe_din),
// -- outputs -------------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
.output_selector_dout (output_selector)
);
/*
-- Registros
-- Descripcion: Registros de captura del resultado del elemento de
procesamiento. Estos registros (64 bits c/u)
almacenan el resultado del procesamiento, previo a
su liberacion a la red.
*/
reg [(2* `CHANNEL_WIDTH)-1:0] wordC_reg;
reg [(2* `CHANNEL_WIDTH)-1:0] wordD_reg;
always @(posedge clk)
if (done_strobe_din)
wordC_reg <= wordC_din;
always @(posedge clk)
if (done_strobe_din)
wordD_reg <= wordD_din;
/*
-- Multiplexor
-- Descripcion: Multiplexor para la seleccion del flit que saldra
a la red durante el siguiente ciclo de reloj.
Los datos de entrada para el multiplexor, son los
registros de resultado del PE y el flit de cabecera
modificado.
Si no existe transito de flits el multiplexor, este
mantiene el canal de salida en un valor de 0.
*/
always @(*)
begin
output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
case (output_selector)
3'b101: output_channel_dout = shifted_header_din;
3'b100: output_channel_dout = wordC_reg[`CHANNEL_WIDTH-1:0]; //-- Flit de datos 1
3'b011: output_channel_dout = wordC_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH]; //-- Flit de datos 2
3'b010: output_channel_dout = wordD_reg[`CHANNEL_WIDTH-1:0]; //-- Flit de datos 3
3'b001: output_channel_dout = wordD_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH]; //-- Flit de datos 4
3'b000: output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
endcase
end
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
test_engine_nic_output_block nic_output_block
(
.clk (clk),
.reset (reset),
// -- inputs from PE ----------------------------------------- >>>>>
.done_strobe_din (done_strobe_din),
.wordC_din (wordC_din),
.wordD_din (wordD_din),
.shifted_header_din (shifted_header_din),
// -- to input block ----------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
// -- output port -------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout)
);
*/
|
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// pseudo-random packet source
//==============================================================================
module packet_source
(clk, reset, router_address, channel, flit_valid, flow_ctrl, run, error, count_down, DoS_detected);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
parameter initial_seed = 0;
// maximum number of packets to generate (-1 = no limit)
parameter max_packet_count = 1000;
// packet injection rate (percentage of cycles)
parameter packet_rate = 25;
// width of packet count register
parameter packet_count_reg_width = 32;
// select packet length mode (0: uniform random, 1: bimodal)
parameter packet_length_mode = 0;
// select network topology
parameter topology = `TOPOLOGY_FBFLY;
// total buffer size per port in flits
parameter buffer_size = 32;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// nuber of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 2;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of nodes
parameter num_nodes = 64;
// number of dimensions in network
parameter num_dimensions = 2;
// number of nodes per router (a.k.a. concentration factor)
parameter num_nodes_per_router = 4;
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select individual port
localparam port_idx_width = clogb(num_ports);
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// select type of flow control
parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
// make incoming flow control signals bypass the output VC state tracking
// logic
parameter flow_ctrl_bypass = 1;
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
// maximum payload length (in flits)
parameter max_payload_length = 4;
// minimum payload length (in flits)
parameter min_payload_length = 0;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// enable link power management
parameter enable_link_pm = 1;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flit payload data
parameter flit_data_width = 64;
// channel width
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// total number of bits required for routing-related information
localparam route_info_width = lar_info_width + dest_info_width + 1;
// total number of bits required for storing header information
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
route_info_width :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
route_info_width :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(route_info_width + payload_length_width) :
-1;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// select flit buffer management scheme
parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
// EXPERIMENTAL:
// for dynamic buffer management, only reserve a buffer slot for a VC while
// it is active (i.e., while a packet is partially transmitted)
// (NOTE: This is currently broken!)
parameter disable_static_reservations = 0;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
// which router port is this packet source attached to?
parameter port_id = 0;
// which dimension does the current input port belong to?
localparam curr_dim = port_id / num_neighbors_per_dim;
// maximum packet length (in flits)
localparam max_packet_length = 1 + max_payload_length;
// total number of bits required to represent maximum packet length
localparam packet_length_width = clogb(max_packet_length);
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input [0:router_addr_width-1] router_address;
output [0:channel_width-1] channel;
wire [0:channel_width-1] channel;
output flit_valid;
wire flit_valid;
input [0:flow_ctrl_width-1] flow_ctrl;
input run;
output error;
wire error;
integer seed = initial_seed;
integer i;
reg new_packet;
//Modified for DoS attack
input [31:0] count_down;
input DoS_detected;
always @(posedge clk, posedge reset)
begin
/* if (router_address == 4'b0000 && count_down != 0 && DoS_detected)
new_packet <= 0;
else if (router_address == 4'b0000)
new_packet
<= ($dist_uniform(seed, 0, 99) < 80) && run && !reset;
else*/
new_packet
<= ($dist_uniform(seed, 0, 99) < packet_rate) && run && !reset;
end
wire waiting_packet_count_zero;
wire packet_ready;
assign packet_ready = new_packet & ~waiting_packet_count_zero;
generate
if(max_packet_count >= 0)
begin
wire [0:packet_count_reg_width-1] waiting_packet_count_s;
wire [0:packet_count_reg_width-1] waiting_packet_count_q;
assign waiting_packet_count_s
= waiting_packet_count_q - packet_ready;
c_dff
#(.width(packet_count_reg_width),
.reset_value(max_packet_count),
.reset_type(reset_type))
waiting_packet_countq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(waiting_packet_count_s),
.q(waiting_packet_count_q));
assign waiting_packet_count_zero = ~|waiting_packet_count_q;
end
else
assign waiting_packet_count_zero = 1'b0;
endgenerate
wire packet_sent;
wire ready_packet_count_zero;
wire [0:packet_count_reg_width-1] ready_packet_count_s;
wire [0:packet_count_reg_width-1] ready_packet_count_q;
assign ready_packet_count_s
= run ?
ready_packet_count_q - (packet_sent & ~ready_packet_count_zero) +
packet_ready :
{packet_count_reg_width{1'b0}};
c_dff
#(.width(packet_count_reg_width),
.reset_type(reset_type))
ready_packet_countq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(ready_packet_count_s),
.q(ready_packet_count_q));
assign ready_packet_count_zero = ~|ready_packet_count_q;
wire flit_head;
wire flit_tail;
wire [0:flit_data_width-1] flit_data;
wire [0:num_vcs-1] sel_ovc;
rtr_channel_output
#(.num_vcs(num_vcs),
.packet_format(packet_format),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.reset_type(reset_type))
cho
(.clk(clk),
.reset(reset),
.active(flit_valid),
.flit_valid_in(flit_valid),
.flit_head_in(flit_head),
.flit_tail_in(flit_tail),
.flit_data_in(flit_data),
.flit_sel_in_ovc(sel_ovc),
.channel_out(channel));
wire fc_event_valid;
wire [0:num_vcs-1] fc_event_sel_ovc;
rtr_flow_ctrl_input
#(.num_vcs(num_vcs),
.flow_ctrl_type(flow_ctrl_type),
.reset_type(reset_type))
fci
(.clk(clk),
.reset(reset),
.active(1'b1),
.flow_ctrl_in(flow_ctrl),
.fc_event_valid_out(fc_event_valid),
.fc_event_sel_out_ovc(fc_event_sel_ovc));
wire flit_valid_s, flit_valid_q;
assign flit_valid_s = flit_valid;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_validq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(flit_valid_s),
.q(flit_valid_q));
wire flit_head_s, flit_head_q;
assign flit_head_s = flit_head;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_headq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(flit_head_s),
.q(flit_head_q));
wire flit_tail_s, flit_tail_q;
assign flit_tail_s = flit_tail;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_tailq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(flit_tail_s),
.q(flit_tail_q));
wire [0:num_vcs-1] flit_sel_ovc_s, flit_sel_ovc_q;
assign flit_sel_ovc_s = sel_ovc;
c_dff
#(.width(num_vcs),
.reset_type(reset_type))
flit_sel_ovcq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(flit_sel_ovc_s),
.q(flit_sel_ovc_q));
wire fc_active;
wire [0:num_vcs-1] empty_ovc;
wire [0:num_vcs-1] almost_full_ovc;
wire [0:num_vcs-1] full_ovc;
wire [0:num_vcs-1] full_prev_ovc;
wire [0:num_vcs*2-1] fcs_errors_ovc;
rtr_fc_state
#(.num_vcs(num_vcs),
.buffer_size(buffer_size),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.mgmt_type(fb_mgmt_type),
.disable_static_reservations(disable_static_reservations),
.reset_type(reset_type))
fcs
(.clk(clk),
.reset(reset),
.active(1'b1),
.flit_valid(flit_valid_q),
.flit_head(flit_head_q),
.flit_tail(flit_tail_q),
.flit_sel_ovc(flit_sel_ovc_q),
.fc_event_valid(fc_event_valid),
.fc_event_sel_ovc(fc_event_sel_ovc),
.fc_active(fc_active),
.empty_ovc(empty_ovc),
.almost_full_ovc(almost_full_ovc),
.full_ovc(full_ovc),
.full_prev_ovc(full_prev_ovc),
.errors_ovc(fcs_errors_ovc));
wire [0:num_vcs-1] elig_ovc;
genvar ovc;
generate
for(ovc = 0; ovc < num_vcs; ovc = ovc + 1)
begin:ovcs
wire allocated;
wire allocated_s, allocated_q;
assign allocated_s = allocated;
c_dff
#(.width(1),
.reset_type(reset_type))
allocatedq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(allocated_s),
.q(allocated_q));
wire flit_sent;
assign flit_sent = flit_valid_q & flit_sel_ovc_q[ovc];
assign allocated = flit_sent ? ~flit_tail_q : allocated_q;
wire empty;
assign empty = empty_ovc[ovc];
wire full;
assign full = full_ovc[ovc];
wire elig;
case(elig_mask)
`ELIG_MASK_NONE:
assign elig = ~allocated;
`ELIG_MASK_FULL:
assign elig = ~allocated & ~full;
`ELIG_MASK_USED:
assign elig = ~allocated & empty;
endcase
assign elig_ovc[ovc] = elig;
end
endgenerate
wire full;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
full_sel
(.select(sel_ovc),
.data_in(full_ovc),
.data_out(full));
wire elig;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
elig_sel
(.select(sel_ovc),
.data_in(elig_ovc),
.data_out(elig));
wire flit_pending_q;
wire flit_sent;
assign flit_sent = flit_pending_q & ~full & (elig | ~flit_head);
wire flit_kill;
assign flit_valid = flit_sent & ~flit_kill;
assign packet_sent = flit_tail & flit_sent;
wire flit_pending_s;
assign flit_pending_s
= (flit_pending_q & ~packet_sent) | ~ready_packet_count_zero;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_pendingq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(flit_pending_s),
.q(flit_pending_q));
reg [0:flit_data_width-1] data_q;
always @(posedge clk, posedge reset)
begin
if(reset | flit_valid)
for(i = 0; i < flit_data_width; i = i + 1)
data_q[i] <= $dist_uniform(seed, 0, 1);
end
wire [0:header_info_width-1] header_info;
assign flit_data[0:header_info_width-1]
= flit_head ? header_info : data_q[0:header_info_width-1];
assign flit_data[header_info_width:flit_data_width-1]
= data_q[header_info_width:flit_data_width-1];
reg [0:dest_info_width-1] dest_info;
wire [0:num_message_classes*num_resource_classes-1] sel_mc_orc;
c_mat_mult
#(.dim1_width(num_message_classes*num_resource_classes),
.dim2_width(num_vcs_per_class),
.dim3_width(1),
.prod_op(`BINARY_OP_AND),
.sum_op(`BINARY_OP_OR))
sel_mc_orc_mmult
(.input_a(sel_ovc),
.input_b({num_vcs_per_class{1'b1}}),
.result(sel_mc_orc));
wire [0:num_message_classes-1] sel_mc;
c_mat_mult
#(.dim1_width(num_message_classes),
.dim2_width(num_resource_classes),
.dim3_width(1),
.prod_op(`BINARY_OP_AND),
.sum_op(`BINARY_OP_OR))
sel_mc_mmult
(.input_a(sel_mc_orc),
.input_b({num_resource_classes{1'b1}}),
.result(sel_mc));
wire [0:num_resource_classes*num_message_classes-1] sel_orc_mc;
c_interleave
#(.width(num_message_classes*num_resource_classes),
.num_blocks(num_message_classes))
sel_orc_mc_intl
(.data_in(sel_mc_orc),
.data_out(sel_orc_mc));
wire [0:num_resource_classes-1] sel_orc;
c_mat_mult
#(.dim1_width(num_resource_classes),
.dim2_width(num_message_classes),
.dim3_width(1),
.prod_op(`BINARY_OP_AND),
.sum_op(`BINARY_OP_OR))
sel_orc_mmult
(.input_a(sel_orc_mc),
.input_b({num_message_classes{1'b1}}),
.result(sel_orc));
wire [0:num_ports-1] route_op;
wire [0:num_resource_classes-1] route_orc;
rtr_routing_logic
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.routing_type(routing_type),
.dim_order(dim_order))
rtl
(.router_address(router_address),
.sel_mc(sel_mc),
.sel_irc(sel_orc),
.dest_info(dest_info),
.route_op(route_op),
.route_orc(route_orc));
wire [0:port_idx_width-1] route_port;
c_encode
#(.num_ports(num_ports))
route_port_enc
(.data_in(route_op),
.data_out(route_port));
wire [0:lar_info_width-1] lar_info;
assign lar_info[0:port_idx_width-1] = route_port;
generate
if(num_resource_classes > 1)
begin
wire [0:resource_class_idx_width-1] route_rcsel;
c_encode
#(.num_ports(num_resource_classes))
route_rcsel_enc
(.data_in(route_orc),
.data_out(route_rcsel));
assign lar_info[port_idx_width:
port_idx_width+resource_class_idx_width-1]
= route_rcsel;
end
endgenerate
assign header_info[0:lar_info_width-1] = lar_info;
wire [0:num_resource_classes*router_addr_width-1] dest_info_addresses;
assign dest_info_addresses
= dest_info[0:num_resource_classes*router_addr_width-1];
wire [0:router_addr_width-1] rc_dest;
c_select_1ofn
#(.num_ports(num_resource_classes),
.width(router_addr_width))
rc_dest_sel
(.select(sel_orc),
.data_in(dest_info_addresses),
.data_out(rc_dest));
wire [0:addr_width-1] source_address;
assign source_address[0:router_addr_width-1] = router_address;
wire [0:router_addr_width-1] curr_dest_addr;
generate
case(routing_type)
`ROUTING_TYPE_PHASED_DOR:
begin
if(port_id >= (num_ports - num_nodes_per_router))
begin
assign flit_kill
= (dest_info[dest_info_width-addr_width:
dest_info_width-1] ==
source_address);
end
else
begin
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
wire flit_kill_base;
if(connectivity == `CONNECTIVITY_LINE)
assign flit_kill_base
= (((port_id % 2) == 0) &&
(rc_dest[curr_dim*dim_addr_width:
(curr_dim+1)*dim_addr_width-1] <
router_address[curr_dim*
dim_addr_width:
(curr_dim+1)*
dim_addr_width-1])) ||
(((port_id % 2) == 1) &&
(rc_dest[curr_dim*dim_addr_width:
(curr_dim+1)*dim_addr_width-1] >
router_address[curr_dim*
dim_addr_width:
(curr_dim+1)*
dim_addr_width-1]));
else
assign flit_kill_base = 1'b0;
if((dim_order == `DIM_ORDER_ASCENDING) &&
(curr_dim > 0))
begin
assign flit_kill
= (rc_dest[0:curr_dim*dim_addr_width-1] !=
router_address[0:curr_dim*
dim_addr_width-1]) ||
flit_kill_base;
end
else if((dim_order == `DIM_ORDER_DESCENDING) &&
(curr_dim < (num_dimensions - 1)))
begin
assign flit_kill
= (rc_dest[(curr_dim+1)*dim_addr_width:
router_addr_width-1] !=
router_address[(curr_dim+1)*dim_addr_width:
router_addr_width-1]) ||
flit_kill_base;
end
else if(dim_order == `DIM_ORDER_BY_CLASS)
begin
// FIXME: add implementation here!
initial
begin
$display({"ERROR: The packet source module ",
"does not properly support class-",
"based dimension order traversal ",
"in the flit kill logic yet."});
$stop;
end
end
else
begin
assign flit_kill = flit_kill_base;
end
end
`CONNECTIVITY_FULL:
begin
assign flit_kill
= ((dim_order == `DIM_ORDER_ASCENDING) &&
(rc_dest[0:(curr_dim+1)*dim_addr_width-1] !=
router_address[0:(curr_dim+1)*dim_addr_width-1])) ||
((dim_order == `DIM_ORDER_DESCENDING) &&
(rc_dest[curr_dim*dim_addr_width:
router_addr_width-1] !=
router_address[curr_dim*dim_addr_width:
router_addr_width-1]));
end
endcase
end
end
endcase
endgenerate
reg [0:router_addr_width-1] random_router_address;
integer d;
generate
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] node_address;
if(port_id >= (num_ports - num_nodes_per_router))
assign node_address = port_id - (num_ports - num_nodes_per_router);
else
assign node_address = {node_addr_width{1'b0}};
assign source_address[router_addr_width:addr_width-1] = node_address;
reg [0:node_addr_width-1] random_node_address;
always @(posedge clk, posedge reset)
begin
if(reset | packet_sent)
begin
for(d = 0; d < num_dimensions; d = d + 1)
random_router_address[d*dim_addr_width +: dim_addr_width]
= (router_address[d*dim_addr_width +: dim_addr_width] +
$dist_uniform(seed, 0, num_routers_per_dim-1)) %
num_routers_per_dim;
random_node_address
= (node_address +
$dist_uniform(seed,
((port_id >=
(num_ports - num_nodes_per_router)) &&
(random_router_address ==
router_address)) ? 1 : 0,
num_nodes_per_router - 1)) %
num_nodes_per_router;
dest_info[dest_info_width-addr_width:dest_info_width-1]
= {random_router_address, random_node_address};
end
end
end
else
begin
always @(posedge clk, posedge reset)
begin
if(reset | packet_sent)
begin
for(d = 0; d < num_dimensions - 1; d = d + 1)
random_router_address[d*dim_addr_width +: dim_addr_width]
= (router_address[d*dim_addr_width +: dim_addr_width] +
$dist_uniform(seed, 0, num_routers_per_dim-1)) %
num_routers_per_dim;
random_router_address[router_addr_width-dim_addr_width:
router_addr_width-1]
= router_address[router_addr_width-dim_addr_width:
router_addr_width-1];
random_router_address[router_addr_width-dim_addr_width:
router_addr_width-1]
= (router_address[router_addr_width-dim_addr_width:
router_addr_width-1] +
$dist_uniform(seed,
((port_id >=
(num_ports - num_nodes_per_router)) &&
(random_router_address ==
router_address)) ? 1 : 0,
num_routers_per_dim - 1)) %
num_routers_per_dim;
dest_info[dest_info_width-addr_width:dest_info_width-1]
= random_router_address;
end
end
end
if(num_resource_classes > 1)
begin
reg [0:router_addr_width-1] last_router_address;
reg [0:router_addr_width-1] random_intm_address;
always @(random_router_address)
begin
last_router_address = random_router_address;
for(i = num_resource_classes - 2; i >= 0; i = i - 1)
begin
for(d = 0; d < num_dimensions - 1; d = d + 1)
random_intm_address[d*dim_addr_width +: dim_addr_width]
= (last_router_address[d*dim_addr_width +:
dim_addr_width] +
$dist_uniform(seed, 0, num_routers_per_dim-1)) %
num_routers_per_dim;
random_intm_address[router_addr_width-dim_addr_width:
router_addr_width-1]
= last_router_address[router_addr_width-dim_addr_width:
router_addr_width-1];
random_intm_address[router_addr_width-dim_addr_width:
router_addr_width-1]
= (last_router_address[router_addr_width-dim_addr_width:
router_addr_width-1] +
$dist_uniform(seed, (random_router_address ==
last_router_address) ? 1 : 0,
num_routers_per_dim - 1)) %
num_routers_per_dim;
dest_info[i*router_addr_width +: router_addr_width]
= random_intm_address;
last_router_address = random_intm_address;
end
end
end
assign header_info[lar_info_width:
route_info_width-2]
= dest_info;
//PRIV mode
reg priv;
always @(posedge clk)
priv <= ($dist_uniform(seed, 0, 99) < 10);
assign header_info[route_info_width-1] = priv;
if(max_payload_length > 0)
begin
reg [0:packet_length_width-1] random_length_q;
reg [0:packet_length_width-1] flit_count_q;
reg tail_q;
always @(posedge clk, posedge reset)
begin
case(packet_length_mode)
0:
random_length_q <= $dist_uniform(seed, min_payload_length,
max_payload_length);
1:
random_length_q <= ($dist_uniform(seed, 0, 1) < 1) ?
min_payload_length :
max_payload_length;
endcase
if(reset)
begin
flit_count_q <= min_payload_length;
tail_q <= (min_payload_length == 0);
end
else if(packet_sent)
begin
flit_count_q <= random_length_q;
tail_q <= ~|random_length_q;
end
else if(flit_sent)
begin
flit_count_q <= flit_count_q - |flit_count_q;
tail_q <= ~|(flit_count_q - |flit_count_q);
end
end
wire head_s, head_q;
assign head_s = (head_q & ~flit_sent) | packet_sent;
c_dff
#(.width(1),
.reset_value(1'b1),
.reset_type(reset_type))
headq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(head_s),
.q(head_q));
assign flit_head = head_q;
assign flit_tail = tail_q;
if((packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) &&
(payload_length_width > 0))
begin
wire [0:payload_length_width-1] payload_length;
assign payload_length = (flit_count_q - min_payload_length);
assign header_info[route_info_width:
route_info_width+
payload_length_width-1]
= payload_length;
end
end
else
begin
assign flit_head = 1'b1;
assign flit_tail = 1'b1;
end
if(num_vcs > 1)
begin
reg [0:vc_idx_width-1] random_vc;
always @(posedge clk, posedge reset)
begin
if(reset | packet_sent)
random_vc <= $dist_uniform(seed, 0, num_vcs-1);
end
c_decode
#(.num_ports(num_vcs))
sel_ovc_dec
(.data_in(random_vc),
.data_out(sel_ovc));
assign curr_dest_addr
= dest_info[((random_vc / num_vcs_per_class) %
num_resource_classes)*router_addr_width +:
router_addr_width];
end
else
begin
assign sel_ovc = 1'b1;
assign curr_dest_addr = dest_info[0:router_addr_width-1];
end
endgenerate
assign error = |fcs_errors_ovc;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_saturation_enbkb_div_u
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1];
//------------------------Body---------------------------
assign quot = dividend_tmp[in0_WIDTH];
assign remd = remd_tmp[in0_WIDTH];
// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
always @(posedge clk)
begin
if (ce) begin
dividend_tmp[0] <= dividend;
divisor_tmp[0] <= divisor;
remd_tmp[0] <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < in0_WIDTH; i = i + 1)
begin : loop
if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0];
else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
always @(posedge clk)
begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
divisor_tmp[i+1] <= divisor_tmp[i];
remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
end
end
end
endgenerate
endmodule
module hls_saturation_enbkb_div
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
//------------------------Instantiation------------------
hls_saturation_enbkb_div_u #(
.in0_WIDTH ( in0_WIDTH ),
.in1_WIDTH ( in1_WIDTH ),
.out_WIDTH ( out_WIDTH )
) hls_saturation_enbkb_div_u_0 (
.clk ( clk ),
.reset ( reset ),
.ce ( ce ),
.dividend ( dividend_u ),
.divisor ( divisor_u ),
.quot ( quot_u ),
.remd ( remd_u )
);
//------------------------Body---------------------------
assign dividend_u = dividend0;
assign divisor_u = divisor0;
always @(posedge clk)
begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
end
end
always @(posedge clk)
begin
if (ce) begin
quot <= quot_u;
remd <= remd_u;
end
end
endmodule
`timescale 1 ns / 1 ps
module hls_saturation_enbkb(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
wire[dout_WIDTH - 1:0] sig_remd;
hls_saturation_enbkb_div #(
.in0_WIDTH( din0_WIDTH ),
.in1_WIDTH( din1_WIDTH ),
.out_WIDTH( dout_WIDTH ))
hls_saturation_enbkb_div_U(
.dividend( din0 ),
.divisor( din1 ),
.quot( dout ),
.remd( sig_remd ),
.clk( clk ),
.ce( ce ),
.reset( reset ));
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module eim_debug(
input wire bclk_i,
input wire bclk_dll,
input wire adv_in,
input wire rw_in,
input wire cs1_in,
input wire [2:0] a_in,
input wire [15:0] din_in,
input wire oe_in,
input wire eim_trig_ena,
input wire eim_mon_reset,
input wire eim_mon_adv,
output wire mon_empty,
output wire mon_full,
output wire [23:0] mon_data,
input wire bclk_reset
);
wire pretrig_full;
wire pretrig_almost_full;
wire [23:0] pretrig_d;
eim_pretrigger eim_pre (
.wr_clk(bclk_i), // input wr_clk
.rd_clk(bclk_dll), // input rd_clk
.din({1'b0,oe_in,adv_in,rw_in,cs1_in,a_in[2:0],din_in[15:0]}), // input [22 : 0] din
.wr_en(1'b1), // input wr_en
.rd_en(pretrig_full | pretrig_almost_full), // input rd_en
.dout(pretrig_d[23:0]), // output [23 : 0] dout
.full(pretrig_full), // output full
.almost_full(pretrig_almost_full),
// .empty(empty), // output empty
// .underflow(underflow), // output underflow
// .rd_data_count(rd_data_count) // output [7 : 0] rd_data_count
.rst(bclk_reset) // input rst
);
wire mon_trig;
reg mon_wren;
reg mon_oneshot;
assign mon_trig = eim_trig_ena & !cs1_in; // trigger on CS1 going active
// trigger state machine: wait for trigger; then fill the FIFO; then hold until reset
always @(posedge bclk_dll) begin
if(eim_mon_reset) begin
mon_oneshot <= 1'b0;
mon_wren <= 1'b0;
end else begin
if(mon_trig && !mon_wren && !mon_oneshot) begin // init then catch trigger
mon_wren <= 1'b1;
mon_oneshot <= 1'b1; // ignore future triggers
end else if( mon_oneshot && mon_wren ) begin // next state after trigger, write until full
mon_oneshot <= 1'b1;
if(mon_full) begin
mon_wren <= 1'b0; // once full, disable mon_wren
end else begin
mon_wren <= 1'b1;
end
end else if( mon_oneshot && !mon_wren ) begin // this is the terminal state from logging
mon_oneshot <= 1'b1;
mon_wren <= 1'b0;
end else begin // we reach this case if oneshot hasn't fired yet, e.g. waiting for tigger event
mon_oneshot <= 1'b0;
mon_wren <= 1'b0;
end
end // else: !if(eim_mon_reset)
end // always @ (posedge bclk_dll)
reg eim_mon_pulse;
reg [1:0] eim_mon_adv_d;
always @(posedge bclk_dll) begin
eim_mon_adv_d[0] <= eim_mon_adv;
eim_mon_adv_d[1] <= eim_mon_adv_d[0];
eim_mon_pulse <= !eim_mon_adv_d[1] & eim_mon_adv_d[0];
end
//// TODO: add almost_full to FIFO and map mon_full to almost_full to avoid overflow-by-one
eim_monitor eim_mon (
.wr_clk(bclk_dll), // input wr_clk
.rd_clk(bclk_dll), // input rd_clk
.din(pretrig_d[23:0]), // input [21 : 0] din
.wr_en(mon_wren), // input wr_en
.rd_en(eim_mon_pulse), // input rd_en
.dout(mon_data[23:0]), // output [21 : 0] dout
.almost_full(mon_full), // output full
// .overflow(overflow), // output overflow
.empty(mon_empty), // output empty
// .rd_data_count(rd_data_count) // output [9 : 0] rd_data_count
.rst(bclk_reset | eim_mon_reset) // input rst
);
endmodule // eim_debug
|
`define bsg_nand_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_ND2D1BWP_b``bits nand_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_nand #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_nand_macro(34) else
`bsg_nand_macro(33) else
`bsg_nand_macro(32) else
`bsg_nand_macro(31) else
`bsg_nand_macro(30) else
`bsg_nand_macro(29) else
`bsg_nand_macro(28) else
`bsg_nand_macro(27) else
`bsg_nand_macro(26) else
`bsg_nand_macro(25) else
`bsg_nand_macro(24) else
`bsg_nand_macro(23) else
`bsg_nand_macro(22) else
`bsg_nand_macro(21) else
`bsg_nand_macro(20) else
`bsg_nand_macro(19) else
`bsg_nand_macro(18) else
`bsg_nand_macro(17) else
`bsg_nand_macro(16) else
`bsg_nand_macro(15) else
`bsg_nand_macro(14) else
`bsg_nand_macro(13) else
`bsg_nand_macro(12) else
`bsg_nand_macro(11) else
`bsg_nand_macro(10) else
`bsg_nand_macro(9) else
`bsg_nand_macro(8) else
`bsg_nand_macro(7) else
`bsg_nand_macro(6) else
`bsg_nand_macro(5) else
`bsg_nand_macro(4) else
`bsg_nand_macro(3) else
`bsg_nand_macro(2) else
`bsg_nand_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i & b_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nand)
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 45,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 161,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "45"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.866669"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "161"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90908000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "45"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "161"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXBP_BLACKBOX_V
|
/*--------------------
Original Author: Yuma Ueda
Contact Point: [email protected]
ram.v
Created: 12/19/2019
Copyright 2019 Yuma Ueda
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
--------------------*/
`include "defs.v"
module RAM (
input wire [31:0] addr, write_data,
input wire memwrite,
input wire [1:0] storeops,
output wire [31:0] read_data,
input wire CLK, reset
);
reg [7:0] ram [`RAM_COL_MAX-1:0];
always @(posedge CLK) begin
if (reset) begin : rst
integer i;
for (i = 0; i < `RAM_COL_MAX; i = i + 1) begin
ram[i] <= 0;
end
end
else if (memwrite) begin
do_store();
end
end
assign read_data = {
ram[addr],
ram[addr+1],
ram[addr+2],
ram[addr+3]
};
task store_byte;
begin
ram[addr] <= write_data[7:0];
end
endtask
task store_half_word;
begin
ram[addr] <= write_data[15:8];
ram[addr+1] <= write_data[7:0];
end
endtask
task store_word;
begin
ram[addr] <= write_data[31:24];
ram[addr+1] <= write_data[23:16];
ram[addr+2] <= write_data[15: 8];
ram[addr+3] <= write_data[ 7: 0];
end
endtask
task do_store;
begin
(* full_case *)
case (storeops)
`STORE_B: store_byte();
`STORE_H: store_half_word();
`STORE_W: store_word();
endcase
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_1_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_1_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog wrapper for dlybuf4s15kapwr with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlybuf4s15kapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr_1 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlybuf4s15kapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlybuf4s15kapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_1_V
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of K580VT57 DMA controller
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580vt57.v
//
// Warning: This realization is not fully operational.
module k580vt57
(
input clk,
input ce_dma,
input reset,
input [3:0] iaddr,
input [7:0] idata,
input [3:0] drq,
input iwe_n,
input ird_n,
input hlda,
output hrq,
output [3:0] dack,
output [7:0] odata,
output [15:0] oaddr,
output owe_n,
output ord_n,
output oiowe_n,
output oiord_n
);
parameter ST_IDLE = 0;
parameter ST_WAIT = 1;
parameter ST_T1 = 2;
parameter ST_T2 = 3;
parameter ST_T3 = 4;
parameter ST_T4 = 5;
parameter ST_T5 = 6;
parameter ST_T6 = 7;
reg [3:0] ack;
reg [2:0] state;
reg [1:0] channel;
reg [7:0] mode;
reg [3:0] chstate;
reg [15:0] chaddr[3:0];
reg [15:0] chtcnt[3:0];
reg ff,exiwe_n;
assign dack = ack;
assign hrq = state!=ST_IDLE;
assign odata = {4'd0, chstate};
assign oaddr = chaddr[channel];
assign owe_n = chtcnt[channel][14]==0 || state!=ST_T2;
assign ord_n = chtcnt[channel][15]==0 || (state!=ST_T1 && state!=ST_T2);
assign oiowe_n = chtcnt[channel][15]==0 || state!=ST_T2;
assign oiord_n = chtcnt[channel][14]==0 || (state!=ST_T1 && state!=ST_T2);
wire[3:0] mdrq = drq & mode[3:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; ff <= 0; mode <= 0; exiwe_n <= 1;
chstate <= 0; ack <= 0;
end else begin
exiwe_n <= iwe_n;
if (iwe_n && ~exiwe_n) begin
ff <= ~(ff|iaddr[3]);
case({ff, iaddr})
5'b00000: chaddr[0][7:0] <= idata;
5'b00001: chtcnt[0][7:0] <= idata;
5'b00010: chaddr[1][7:0] <= idata;
5'b00011: chtcnt[1][7:0] <= idata;
5'b00100: begin chaddr[2][7:0] <= idata; if(mode[7]) chaddr[3][7:0] <= idata; end
5'b00101: begin chtcnt[2][7:0] <= idata; if(mode[7]) chtcnt[3][7:0] <= idata; end
5'b00110: chaddr[3][7:0] <= idata;
5'b00111: chtcnt[3][7:0] <= idata;
5'b10000: chaddr[0][15:8] <= idata;
5'b10001: chtcnt[0][15:8] <= idata;
5'b10010: chaddr[1][15:8] <= idata;
5'b10011: chtcnt[1][15:8] <= idata;
5'b10100: begin chaddr[2][15:8] <= idata; if(mode[7]) chaddr[3][15:8] <= idata; end
5'b10101: begin chtcnt[2][15:8] <= idata; if(mode[7]) chtcnt[3][15:8] <= idata; end
5'b10110: chaddr[3][15:8] <= idata;
5'b10111: chtcnt[3][15:8] <= idata;
5'b01000: {ff,mode} <= {1'b0,idata};
5'b11000: {ff,mode} <= {1'b0,idata};
default: ;
endcase
end
if(ce_dma) begin
case (state)
ST_IDLE: begin
if (|mdrq) state <= ST_WAIT;
end
ST_WAIT: begin
if (hlda) state <= ST_T1;
casex (mdrq[3:0])
4'b1xxx: channel <= 3;
4'b01xx: channel <= 2;
4'b001x: channel <= 1;
4'b0001: channel <= 0;
4'b0000: state <= ST_IDLE;
endcase
end
ST_T1: begin
state <= ST_T2;
ack[channel] <= 1;
end
ST_T2: begin
ack[channel] <= 0;
if(!chtcnt[channel][13:0]) begin
chstate[channel] <= 1;
if (mode[7] && channel==2) begin
chaddr[channel] <= chaddr[3];
chtcnt[channel][13:0] <= chtcnt[3][13:0];
end
end else begin
chaddr[channel] <= chaddr[channel]+1'b1;
chtcnt[channel][13:0] <= chtcnt[channel][13:0]+14'h3FFF;
end
state <= ST_T3;
end
ST_T3: begin
state <= |mdrq ? ST_WAIT : ST_IDLE;
end
endcase
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_FUNCTIONAL_V
|
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 c1 c2 clk configupdate locked phasecounterselect phasedone phasestep phaseupdown read readdata reset scanclk scanclkena scandata scandataout scandone write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=62500 clk1_duty_cycle=50 clk1_multiply_by=9 clk1_phase_shift="0" clk2_divide_by=10 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 16.1 cbx_altclkbuf 2016:11:22:18:30:39:SJ cbx_altiobuf_bidir 2016:11:22:18:30:39:SJ cbx_altiobuf_in 2016:11:22:18:30:39:SJ cbx_altiobuf_out 2016:11:22:18:30:39:SJ cbx_altpll 2016:11:22:18:30:39:SJ cbx_altpll_avalon 2016:11:22:18:30:39:SJ cbx_cycloneii 2016:11:22:18:30:39:SJ cbx_lpm_add_sub 2016:11:22:18:30:39:SJ cbx_lpm_compare 2016:11:22:18:30:39:SJ cbx_lpm_counter 2016:11:22:18:30:39:SJ cbx_lpm_decode 2016:11:22:18:30:39:SJ cbx_lpm_mux 2016:11:22:18:30:39:SJ cbx_lpm_shiftreg 2016:11:22:18:30:39:SJ cbx_mgl 2016:11:22:19:17:36:SJ cbx_nadder 2016:11:22:18:30:39:SJ cbx_stratix 2016:11:22:18:30:39:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_stratixiii 2016:11:22:18:30:39:SJ cbx_stratixv 2016:11:22:18:30:39:SJ cbx_util_mgl 2016:11:22:18:30:39:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//altera_std_synchronizer CBX_SINGLE_OUTPUT_FILE="ON" clk din dout reset_n
//VERSION_BEGIN 16.1 cbx_mgl 2016:11:22:19:17:36:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_util_mgl 2016:11:22:18:30:39:SJ VERSION_END
//dffpipe CBX_SINGLE_OUTPUT_FILE="ON" DELAY=3 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 16.1 cbx_mgl 2016:11:22:19:17:36:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_util_mgl 2016:11:22:18:30:39:SJ VERSION_END
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module Raster_Laser_Projector_altpll_0_dffpipe_l2c
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
tri1 clrn;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dffe4a;
reg [0:0] dffe5a;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe4a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe4a <= {1{1'b1}};
else if (clrn == 1'b0) dffe4a <= 1'b0;
else if (ena == 1'b1) dffe4a <= (d & (~ sclr));
// synopsys translate_off
initial
dffe5a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe5a <= {1{1'b1}};
else if (clrn == 1'b0) dffe5a <= 1'b0;
else if (ena == 1'b1) dffe5a <= (dffe4a & (~ sclr));
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (dffe5a & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //Raster_Laser_Projector_altpll_0_dffpipe_l2c
//synthesis_resources = reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module Raster_Laser_Projector_altpll_0_stdsync_sv6
(
clk,
din,
dout,
reset_n) /* synthesis synthesis_clearbox=1 */;
input clk;
input din;
output dout;
input reset_n;
wire [0:0] wire_dffpipe3_q;
Raster_Laser_Projector_altpll_0_dffpipe_l2c dffpipe3
(
.clock(clk),
.clrn(reset_n),
.d(din),
.q(wire_dffpipe3_q));
assign
dout = wire_dffpipe3_q;
endmodule //Raster_Laser_Projector_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=62500 clk1_duty_cycle=50 clk1_multiply_by=9 clk1_phase_shift="0" clk2_divide_by=10 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 16.1 cbx_altclkbuf 2016:11:22:18:30:39:SJ cbx_altiobuf_bidir 2016:11:22:18:30:39:SJ cbx_altiobuf_in 2016:11:22:18:30:39:SJ cbx_altiobuf_out 2016:11:22:18:30:39:SJ cbx_altpll 2016:11:22:18:30:39:SJ cbx_cycloneii 2016:11:22:18:30:39:SJ cbx_lpm_add_sub 2016:11:22:18:30:39:SJ cbx_lpm_compare 2016:11:22:18:30:39:SJ cbx_lpm_counter 2016:11:22:18:30:39:SJ cbx_lpm_decode 2016:11:22:18:30:39:SJ cbx_lpm_mux 2016:11:22:18:30:39:SJ cbx_mgl 2016:11:22:19:17:36:SJ cbx_nadder 2016:11:22:18:30:39:SJ cbx_stratix 2016:11:22:18:30:39:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_stratixiii 2016:11:22:18:30:39:SJ cbx_stratixv 2016:11:22:18:30:39:SJ cbx_util_mgl 2016:11:22:18:30:39:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module Raster_Laser_Projector_altpll_0_altpll_udh2
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll7_clk;
wire wire_pll7_fbout;
wire wire_pll7_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll7_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll7
(
.activeclock(),
.areset(areset),
.clk(wire_pll7_clk),
.clkbad(),
.fbin(wire_pll7_fbout),
.fbout(wire_pll7_fbout),
.inclk(inclk),
.locked(wire_pll7_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.clk1_divide_by = 62500,
pll7.clk1_duty_cycle = 50,
pll7.clk1_multiply_by = 9,
pll7.clk1_phase_shift = "0",
pll7.clk2_divide_by = 10,
pll7.clk2_duty_cycle = 50,
pll7.clk2_multiply_by = 1,
pll7.clk2_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
pll7.operation_mode = "normal",
pll7.pll_type = "auto",
pll7.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //Raster_Laser_Projector_altpll_0_altpll_udh2
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module Raster_Laser_Projector_altpll_0
(
address,
areset,
c0,
c1,
c2,
clk,
configupdate,
locked,
phasecounterselect,
phasedone,
phasestep,
phaseupdown,
read,
readdata,
reset,
scanclk,
scanclkena,
scandata,
scandataout,
scandone,
write,
writedata) /* synthesis synthesis_clearbox=1 */;
input [1:0] address;
input areset;
output c0;
output c1;
output c2;
input clk;
input configupdate;
output locked;
input [3:0] phasecounterselect;
output phasedone;
input phasestep;
input phaseupdown;
input read;
output [31:0] readdata;
input reset;
input scanclk;
input scanclkena;
input scandata;
output scandataout;
output scandone;
input write;
input [31:0] writedata;
wire wire_stdsync2_dout;
wire [4:0] wire_sd1_clk;
wire wire_sd1_locked;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg pfdena_reg;
wire wire_pfdena_reg_ena;
reg prev_reset;
wire w_locked;
wire w_pfdena;
wire w_phasedone;
wire w_pll_areset_in;
wire w_reset;
wire w_select_control;
wire w_select_status;
Raster_Laser_Projector_altpll_0_stdsync_sv6 stdsync2
(
.clk(clk),
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
Raster_Laser_Projector_altpll_0_altpll_udh2 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
.inclk({{1{1'b0}}, clk}),
.locked(wire_sd1_locked));
// synopsys translate_off
initial
pfdena_reg = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) pfdena_reg <= {1{1'b1}};
else if (wire_pfdena_reg_ena == 1'b1) pfdena_reg <= writedata[1];
assign
wire_pfdena_reg_ena = (write & w_select_control);
// synopsys translate_off
initial
prev_reset = 0;
// synopsys translate_on
always @ ( posedge clk or posedge reset)
if (reset == 1'b1) prev_reset <= 1'b0;
else prev_reset <= w_reset;
assign
c0 = wire_sd1_clk[0],
c1 = wire_sd1_clk[1],
c2 = wire_sd1_clk[2],
locked = wire_sd1_locked,
phasedone = 1'b0,
readdata = {{30{1'b0}}, (read & ((w_select_control & w_pfdena) | (w_select_status & w_phasedone))), (read & ((w_select_control & w_pll_areset_in) | (w_select_status & w_locked)))},
scandataout = 1'b0,
scandone = 1'b0,
w_locked = wire_stdsync2_dout,
w_pfdena = pfdena_reg,
w_phasedone = 1'b1,
w_pll_areset_in = prev_reset,
w_reset = ((write & w_select_control) & writedata[0]),
w_select_control = ((~ address[1]) & address[0]),
w_select_status = ((~ address[1]) & (~ address[0]));
endmodule //Raster_Laser_Projector_altpll_0
//VALID FILE
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CacheBlockRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CacheBlockRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Fast Multisource Pulse Registration System
// Ben Gamari (2011)
module register(
reg_clk, reg_addr, reg_data, reg_wr,
clk, value
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input clk;
output [31:0] value;
reg [31:0] value;
initial value = 32'h0;
always @(posedge reg_clk)
if (reg_addr == ADDR && reg_wr)
value <= reg_data;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule
module readonly_register(
reg_clk, reg_addr, reg_data, reg_wr,
value
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input [31:0] value;
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule
module counter_register(
reg_clk, reg_addr, reg_data, reg_wr,
increment_clk, increment
);
parameter ADDR = 1;
input reg_clk;
input [15:0] reg_addr;
inout [31:0] reg_data;
input reg_wr;
input increment_clk;
input increment;
reg [31:0] my_value;
initial my_value = 32'h0;
reg [31:0] value;
reg reset;
initial reset = 0;
always @(posedge increment_clk)
begin
my_value <= reset ? 0 : my_value + increment;
end
always @(posedge reg_clk)
begin
value <= my_value;
if (reg_addr == ADDR && reg_wr)
reset <= 1;
else if (reset)
reset <= 0;
end
assign reg_data = (reg_addr == ADDR && !reg_wr) ? value : 32'hZZ;
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v98ea37 = 240000,
parameter v0105d5 = 1,
parameter v315560 = 20,
parameter v0f02ae = -2
) (
input v68e749,
input vclk,
output [7:0] vb5f8d6
);
localparam p3 = v98ea37;
localparam p7 = v0f02ae;
localparam p10 = v315560;
localparam p20 = v0105d5;
wire [0:7] w0;
wire w1;
wire w2;
wire [0:2] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w8;
wire w9;
wire [0:7] w11;
wire [0:7] w12;
wire [0:7] w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
wire w21;
wire w22;
wire w23;
wire w24;
wire w25;
wire w26;
wire [0:7] w27;
wire w28;
wire w29;
wire [0:7] w30;
wire [0:7] w31;
wire w32;
wire w33;
wire w34;
wire w35;
wire w36;
wire w37;
wire [0:7] w38;
wire [0:7] w39;
wire [0:7] w40;
wire [0:7] w41;
assign vb5f8d6 = w0;
assign w2 = v68e749;
assign w21 = vclk;
assign w22 = vclk;
assign w23 = vclk;
assign w24 = vclk;
assign w25 = vclk;
assign w26 = vclk;
assign w22 = w21;
assign w23 = w21;
assign w23 = w22;
assign w24 = w21;
assign w24 = w22;
assign w24 = w23;
assign w25 = w21;
assign w25 = w22;
assign w25 = w23;
assign w25 = w24;
assign w26 = w21;
assign w26 = w22;
assign w26 = w23;
assign w26 = w24;
assign w26 = w25;
assign w29 = w28;
assign w30 = w5;
assign w31 = w5;
assign w31 = w30;
assign w32 = w17;
assign w34 = w33;
assign w35 = w33;
assign w35 = w34;
assign w36 = w33;
assign w36 = w34;
assign w36 = w35;
assign w39 = w6;
assign w40 = w6;
assign w40 = w39;
v75c864 v645c43 (
.va8064a(w0),
.v5a2634(w1),
.v1336f1(w4)
);
vfebcfe vd146ce (
.v9fb85f(w1)
);
v888484 #(
.v42e61f(p20)
) vdc3fb2 (
.vd9601b(w2),
.v64879c(w19),
.vfde3d7(w21)
);
vbce541 #(
.va04f5d(p3)
) v47bd3e (
.v4642b6(w16),
.v6dda25(w22)
);
v857d2e v449769 (
.v19a59f(w5),
.v6dda25(w23),
.vccca56(w29),
.vec26ff(w41)
);
v9c1f69 v71f96f (
.v1045ee(w4),
.vcc8c7c(w30)
);
vcb23aa ve224a5 (
.veb2f59(w5),
.v39966a(w40),
.v62bf25(w41)
);
v89d234 v55be45 (
.vb1c024(w6),
.v39f831(w8),
.vf892a0(w9),
.v41eb95(w24)
);
vcb23aa vec74fb (
.veb2f59(w6),
.v39966a(w27),
.v62bf25(w38)
);
vffc517 #(
.vc5c8ea(p7)
) v30a629 (
.va0aeac(w12)
);
v1bbb5b v64a91b (
.v9d2a6a(w8),
.v2a1cbe(w11),
.v2d3366(w35),
.v9d7ae8(w38)
);
v873425 v8ee855 (
.vcbab45(w9),
.v0e28cb(w28),
.v3ca442(w36)
);
vffc517 #(
.vc5c8ea(p10)
) v76838a (
.va0aeac(w11)
);
v89d234 v7825c7 (
.v39f831(w12),
.v41eb95(w25),
.vb1c024(w27),
.vf892a0(w33)
);
v78be07 va08ca8 (
.v2ce16c(w15),
.vcc8c7c(w39)
);
vb2762a vecb412 (
.v715730(w13),
.v4642b6(w14),
.vf191e6(w31)
);
vba518e vc58236 (
.v0e28cb(w14),
.v3ca442(w15),
.vcbab45(w37)
);
vba518e v50132d (
.v0e28cb(w16),
.vcbab45(w28),
.v3ca442(w32)
);
v4c1570 vf52c7c (
.v4642b6(w17),
.v6dda25(w26),
.v27dec4(w34),
.v92a149(w37)
);
v3676a0 v91794b (
.v0e28cb(w17),
.vcbab45(w18)
);
vba518e v496601 (
.v0e28cb(w18),
.v3ca442(w19),
.vcbab45(w33)
);
vda0861 vf481a4 (
.vffb58f(w13)
);
endmodule
//---- Top entity
module v75c864 (
input v5a2634,
input [2:0] v1336f1,
output [7:0] va8064a
);
wire w0;
wire [0:7] w1;
wire [0:2] w2;
assign w0 = v5a2634;
assign va8064a = w1;
assign w2 = v1336f1;
v75c864_v45bd49 v45bd49 (
.i(w0),
.o(w1),
.sel(w2)
);
endmodule
//---------------------------------------------------
//-- Demux-3-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Demultiplexor de 1 bit, de 3 a 8 (salida de bus)
//---------------------------------------------------
module v75c864_v45bd49 (
input i,
input [2:0] sel,
output [7:0] o
);
assign o = i << sel;
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module v888484 #(
parameter v9d2d5b = 0,
parameter v42e61f = 0
) (
input vfde3d7,
input vd9601b,
output v157a67,
output v64879c
);
localparam p4 = v9d2d5b;
localparam p5 = v42e61f;
wire w0;
wire w1;
wire w2;
wire w3;
wire w6;
wire w7;
assign w0 = vd9601b;
assign v157a67 = w1;
assign v64879c = w3;
assign w6 = vfde3d7;
assign w7 = vfde3d7;
assign w2 = w1;
assign w7 = w6;
v31e84e v9cfc0f (
.ve78ab8(w2),
.v3487af(w3),
.ved8395(w7)
);
v0b641d #(
.v17ea21(p4),
.v803182(p5)
) v6ca512 (
.v27dec4(w0),
.v4642b6(w1),
.v25ab12(w6)
);
endmodule
//---------------------------------------------------
//-- Button-tic
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Button-tic: Configurable button that emits a tic when it is pressed
//---------------------------------------------------
//---- Top entity
module v31e84e (
input ved8395,
input ve78ab8,
output v3487af
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign w0 = ve78ab8;
assign w1 = ved8395;
assign w4 = ve78ab8;
assign v3487af = w5;
assign w4 = w0;
v053dc2 v1bde40 (
.vf54559(w0),
.va4102a(w1),
.ve8318d(w2)
);
v3676a0 v9d4cda (
.v0e28cb(w2),
.vcbab45(w3)
);
vba518e v57aa83 (
.v0e28cb(w3),
.v3ca442(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- Rising-edge-detector
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v0b641d #(
parameter v17ea21 = 0,
parameter v803182 = 0
) (
input v25ab12,
input v27dec4,
output v4642b6
);
localparam p2 = v803182;
localparam p4 = v17ea21;
wire w0;
wire w1;
wire w3;
wire w5;
wire w6;
wire w7;
wire w8;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v25ab12;
assign w8 = v25ab12;
assign w8 = w7;
v6c3aff #(
.v2fb6e5(p4)
) v67ee04 (
.v758f58(w0),
.vedbc89(w6)
);
vf718a5 v5e6bb3 (
.v6a82dd(w3),
.vd4e5d7(w5),
.v444878(w8)
);
vdc93d6 v71ab2a (
.ve7f5e6(w0),
.v3c12b5(w1),
.v717e81(w7)
);
vad96dc #(
.v6a9fe4(p2)
) vc0a9e9 (
.v27dec4(w1),
.v4642b6(w3)
);
endmodule
//---------------------------------------------------
//-- Button
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Configurable button (pull-up on/off. Not on/off)
//---------------------------------------------------
//---- Top entity
module v6c3aff #(
parameter v2fb6e5 = 1
) (
input vedbc89,
output v758f58
);
localparam p2 = v2fb6e5;
wire w0;
wire w1;
assign w0 = vedbc89;
assign v758f58 = w1;
v6c3aff_v34955f #(
.ON(p2)
) v34955f (
.i(w0),
.o(w1)
);
endmodule
//---------------------------------------------------
//-- Pull-upx1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- FPGA internal pull-up configuration on the input port
//---------------------------------------------------
module v6c3aff_v34955f #(
parameter ON = 0
) (
input i,
output o
);
// 1-Pull up
//-- Place the IO block, configured as
//-- input with pull-up
SB_IO
#(
.PIN_TYPE(6'b 1010_01),
//-- The pull-up is activated or not
//-- depeding on the ON parameter
.PULLUP(ON)
) input_pin (
//--- Input pin
.PACKAGE_PIN(i),
//-- Block output
.D_IN_0(o),
//-- Configured as input
.OUTPUT_ENABLE(1'b0),
//-- Not used
.D_OUT_0(1'b0)
);
endmodule
//---- Top entity
module vf718a5 (
input v444878,
input v6a82dd,
output vd4e5d7
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign w2 = v444878;
assign w3 = v444878;
assign w4 = v444878;
assign vd4e5d7 = w5;
assign w6 = v6a82dd;
assign w7 = v6a82dd;
assign w3 = w2;
assign w4 = w2;
assign w4 = w3;
assign w7 = w6;
v93adf6 ve5d8ab (
.v9afc1f(w0),
.va4102a(w2),
.ve8318d(w5),
.vf54559(w6)
);
v413e4a v93d042 (
.ve37344(w0),
.ve556f1(w1),
.v6dda25(w3)
);
v332488 vf5eed3 (
.v3487af(w1),
.ved8395(w4),
.ve78ab8(w7)
);
endmodule
//---------------------------------------------------
//-- Debouncer-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Remove the rebound on a mechanical switch
//---------------------------------------------------
//---- Top entity
module v93adf6 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
input v9afc1f,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
wire w4;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
assign w4 = v9afc1f;
v93adf6_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3),
.load(w4)
);
endmodule
//---------------------------------------------------
//-- Reg-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 1bit register (implemented in verilog)
//---------------------------------------------------
module v93adf6_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
input load,
output q
);
reg q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module v413e4a (
input v6dda25,
input ve556f1,
output [15:0] v49911e,
output ve37344
);
wire w0;
wire [0:15] w1;
wire [0:15] w2;
wire w3;
wire [0:15] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v49911e = w4;
assign ve37344 = w5;
assign w4 = w1;
vbc711b v8fa00b (
.v782748(w0),
.v3f90b8(w1),
.vc320da(w2),
.v6dda25(w3)
);
v8ecd59 v9392cd (
.v2f9d57(w1),
.vd7988b(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 16-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module vbc711b (
input v6dda25,
input v782748,
input [15:0] vc320da,
output [15:0] v3f90b8
);
wire [0:15] w0;
wire [0:15] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w0 = vc320da;
assign v3f90b8 = w1;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v5c75f6 vbdef88 (
.v4de61b(w2),
.v50034e(w6),
.v6dda25(w13),
.v782748(w17)
);
v5c75f6 v6188f9 (
.v4de61b(w3),
.v50034e(w7),
.v6dda25(w12),
.v782748(w16)
);
v852bc8 vd47660 (
.v91b9c1(w0),
.v527ffb(w2),
.v71a717(w3),
.v0b337e(w4),
.vfc89f9(w5)
);
v401a28 v3ef916 (
.v14a530(w1),
.vcc76e8(w6),
.vd531e6(w7),
.v7ef7d6(w8),
.v1447f2(w9)
);
v5c75f6 v9f7443 (
.v4de61b(w4),
.v50034e(w8),
.v6dda25(w11),
.v782748(w15)
);
v5c75f6 vd2d6b6 (
.v4de61b(w5),
.v50034e(w9),
.v6dda25(w10),
.v782748(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x16
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x16: 16 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v852bc8 (
input [15:0] v91b9c1,
output [3:0] vfc89f9,
output [3:0] v0b337e,
output [3:0] v71a717,
output [3:0] v527ffb
);
wire [0:15] w0;
wire [0:3] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
assign w0 = v91b9c1;
assign v527ffb = w1;
assign v71a717 = w2;
assign v0b337e = w3;
assign vfc89f9 = w4;
v852bc8_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2),
.o2(w3),
.o3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size
//---------------------------------------------------
module v852bc8_v9a2a06 (
input [15:0] i,
output [3:0] o3,
output [3:0] o2,
output [3:0] o1,
output [3:0] o0
);
assign o3 = i[15:12];
assign o2 = i[11:8];
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module v401a28 (
input [3:0] v1447f2,
input [3:0] v7ef7d6,
input [3:0] vd531e6,
input [3:0] vcc76e8,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:3] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
assign v14a530 = w0;
assign w1 = vcc76e8;
assign w2 = vd531e6;
assign w3 = v7ef7d6;
assign w4 = v1447f2;
v401a28_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2),
.i2(w3),
.i3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-quarter: Join the four same buses into an 16-bits Bus
//---------------------------------------------------
module v401a28_v9a2a06 (
input [3:0] i3,
input [3:0] i2,
input [3:0] i1,
input [3:0] i0,
output [15:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v8ecd59 #(
parameter v6c5139 = 1
) (
input [15:0] v2f9d57,
output v4642b6,
output [15:0] vd7988b
);
localparam p1 = v6c5139;
wire w0;
wire [0:15] w2;
wire [0:15] w3;
assign v4642b6 = w0;
assign w2 = v2f9d57;
assign vd7988b = w3;
v265696 #(
.vd73390(p1)
) v76123a (
.v4642b6(w0),
.v36f2dd(w2),
.vc068fb(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-16bit: Increment a 16-bits number by one
//---------------------------------------------------
//---- Top entity
module v265696 #(
parameter vd73390 = 0
) (
input [15:0] v36f2dd,
output v4642b6,
output [15:0] vc068fb
);
localparam p1 = vd73390;
wire w0;
wire [0:15] w2;
wire [0:15] w3;
wire [0:15] w4;
assign v4642b6 = w0;
assign w3 = v36f2dd;
assign vc068fb = w4;
v651fa3 #(
.vc5c8ea(p1)
) vdd8fa2 (
.vcd9338(w2)
);
vbc66d7 vce7ab7 (
.v4642b6(w0),
.v1489e0(w2),
.v603a9a(w3),
.v2c4251(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-16bit: Adder of 16-bit operand and 16-bit constant
//---------------------------------------------------
//---- Top entity
module v651fa3 #(
parameter vc5c8ea = 0
) (
output [15:0] vcd9338
);
localparam p0 = vc5c8ea;
wire [0:15] w1;
assign vcd9338 = w1;
v651fa3_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 16-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 16-bits generic constant
//---------------------------------------------------
module v651fa3_v465065 #(
parameter VALUE = 0
) (
output [15:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module vbc66d7 (
input [15:0] v1489e0,
input [15:0] v603a9a,
output v4642b6,
output [15:0] v2c4251
);
wire w0;
wire w1;
wire [0:15] w2;
wire [0:15] w3;
wire [0:15] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
assign v4642b6 = w0;
assign w2 = v603a9a;
assign w3 = v1489e0;
assign v2c4251 = w4;
v306ca3 v0a29fe (
.v91b9c1(w2),
.vef5eee(w9),
.vd3ef3b(w10)
);
v306ca3 vb0a6ce (
.v91b9c1(w3),
.vef5eee(w7),
.vd3ef3b(w8)
);
vcb23aa v8e0bba (
.v4642b6(w1),
.v62bf25(w6),
.v39966a(w8),
.veb2f59(w10)
);
vc3c498 v917bbf (
.v4642b6(w0),
.vb9cfc3(w1),
.veeaa8e(w5),
.v45c6ee(w7),
.v20212e(w9)
);
v8cc49c v03c3e3 (
.v14a530(w4),
.vb334ae(w5),
.v2b8a97(w6)
);
endmodule
//---------------------------------------------------
//-- Adder-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-16bits: Adder of two operands of 16 bits
//---------------------------------------------------
//---- Top entity
module v306ca3 (
input [15:0] v91b9c1,
output [7:0] vef5eee,
output [7:0] vd3ef3b
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign w0 = v91b9c1;
assign vef5eee = w1;
assign vd3ef3b = w2;
v306ca3_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-half: Split the 16-bits bus into two buses of the same size
//---------------------------------------------------
module v306ca3_v9a2a06 (
input [15:0] i,
output [7:0] o1,
output [7:0] o0
);
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module vcb23aa (
input [7:0] v39966a,
input [7:0] veb2f59,
output v4642b6,
output [7:0] v62bf25
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
assign w0 = veb2f59;
assign w1 = v39966a;
assign v62bf25 = w4;
assign v4642b6 = w5;
v6bdcd9 vd88c66 (
.vcc8c7c(w0),
.v651522(w9),
.v2cc41f(w10)
);
v6bdcd9 v26a0bb (
.vcc8c7c(w1),
.v651522(w7),
.v2cc41f(w8)
);
v25966b v9ea427 (
.v817794(w3),
.v4642b6(w6),
.v0550b6(w8),
.v24708e(w10)
);
vafb28f vc75346 (
.v515fe7(w2),
.v3c88fc(w3),
.va9ac17(w4)
);
va1ce30 v40c17f (
.v817794(w2),
.v4642b6(w5),
.vb9cfc3(w6),
.v0550b6(w7),
.v24708e(w9)
);
endmodule
//---------------------------------------------------
//-- Adder-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-8bits: Adder of two operands of 8 bits
//---------------------------------------------------
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module va1ce30 (
input [3:0] v0550b6,
input [3:0] v24708e,
input vb9cfc3,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
assign w11 = vb9cfc3;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w13),
.v82de4f(w17)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w14),
.vda577d(w17),
.v3f8943(w18),
.v64d863(w19)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w12),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w12),
.v82de4f(w14)
);
vad119b v3599be (
.v4642b6(w0),
.v8e8a67(w2),
.v0ef266(w11),
.v27dec4(w16),
.v82de4f(w19)
);
endmodule
//---------------------------------------------------
//-- AdderC-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-4bits: Adder of two operands of 4 bits and Carry in
//---------------------------------------------------
//---- Top entity
module vc3c498 (
input [7:0] v45c6ee,
input [7:0] v20212e,
input vb9cfc3,
output v4642b6,
output [7:0] veeaa8e
);
wire w0;
wire w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
wire [0:3] w11;
assign w1 = vb9cfc3;
assign w2 = v45c6ee;
assign w3 = v20212e;
assign veeaa8e = w4;
assign v4642b6 = w7;
v6bdcd9 v8d795a (
.vcc8c7c(w3),
.v651522(w10),
.v2cc41f(w11)
);
v6bdcd9 v23dbc5 (
.vcc8c7c(w2),
.v651522(w8),
.v2cc41f(w9)
);
vafb28f vef3a58 (
.va9ac17(w4),
.v3c88fc(w5),
.v515fe7(w6)
);
va1ce30 v0ff71a (
.v4642b6(w0),
.vb9cfc3(w1),
.v817794(w5),
.v0550b6(w9),
.v24708e(w11)
);
va1ce30 v12f94f (
.vb9cfc3(w0),
.v817794(w6),
.v4642b6(w7),
.v0550b6(w8),
.v24708e(w10)
);
endmodule
//---------------------------------------------------
//-- AdderC-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-8bits: Adder of two operands of 8 bits and Carry in
//---------------------------------------------------
//---- Top entity
module v8cc49c (
input [7:0] vb334ae,
input [7:0] v2b8a97,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign v14a530 = w0;
assign w1 = v2b8a97;
assign w2 = vb334ae;
v8cc49c_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-half: Join the two same halves into an 16-bits Bus
//---------------------------------------------------
module v8cc49c_v9a2a06 (
input [7:0] i1,
input [7:0] i0,
output [15:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v332488 (
input ved8395,
input ve78ab8,
output v3487af
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve78ab8;
assign w1 = ved8395;
assign v3487af = w2;
assign w4 = ve78ab8;
assign w4 = w0;
vd12401 v456da5 (
.vcbab45(w2),
.v0e28cb(w3),
.v3ca442(w4)
);
v053dc2 vdfab80 (
.vf54559(w0),
.va4102a(w1),
.ve8318d(w3)
);
endmodule
//---------------------------------------------------
//-- Edges-detector
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input
//---------------------------------------------------
//---- Top entity
module vdc93d6 (
input v717e81,
input ve7f5e6,
output v3c12b5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve7f5e6;
assign v3c12b5 = w2;
assign w3 = v717e81;
assign w4 = v717e81;
assign w4 = w3;
v053dc2 vbb75a1 (
.vf54559(w0),
.ve8318d(w1),
.va4102a(w4)
);
v053dc2 vf6c433 (
.vf54559(w1),
.ve8318d(w2),
.va4102a(w3)
);
endmodule
//---------------------------------------------------
//-- Sync-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Sync 1-bit input with the system clock domain
//---------------------------------------------------
//---- Top entity
module vad96dc #(
parameter v6a9fe4 = 0
) (
input v27dec4,
output v4642b6
);
localparam p0 = v6a9fe4;
wire w1;
wire w2;
wire w3;
assign w2 = v27dec4;
assign v4642b6 = w3;
vd12401 v5b01c7 (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w3)
);
v6b14d5 #(
.vc5c8ea(p0)
) v94e17e (
.v268bfc(w1)
);
endmodule
//---------------------------------------------------
//-- not-wire-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Select positive or negative logic for the input (0=positive, 1=negative)
//---------------------------------------------------
//---- Top entity
module v6b14d5 #(
parameter vc5c8ea = 0
) (
output v268bfc
);
localparam p0 = vc5c8ea;
wire w1;
assign v268bfc = w1;
v6b14d5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 1-bit-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 1-bit generic constant (0/1)
//---------------------------------------------------
module v6b14d5_v465065 #(
parameter VALUE = 0
) (
output k
);
assign k = VALUE;
endmodule
//---- Top entity
module vbce541 #(
parameter va04f5d = 16777216
) (
input v6dda25,
output v4642b6
);
localparam p1 = va04f5d;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire w4;
wire w5;
assign v4642b6 = w0;
assign w5 = v6dda25;
assign w4 = w0;
vef98b5 #(
.vc5c8ea(p1)
) v4016e8 (
.ve70c2d(w3)
);
vd84ae0 v45b714 (
.v4642b6(w0),
.va89056(w2),
.v06bdfb(w3)
);
v97d607 v2299cf (
.v9e1c43(w2),
.ve556f1(w4),
.v6dda25(w5)
);
endmodule
//---------------------------------------------------
//-- sysclk_divN_24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- sysclk_divN_24bits: Generate a signal from the division of the system clock by N. (24-bits precision) (N = 2,3,4,..,0x1000000))
//---------------------------------------------------
//---- Top entity
module vef98b5 #(
parameter vc5c8ea = 1
) (
output [23:0] ve70c2d
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign ve70c2d = w1;
vef98b5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-k-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits k-1 constant (Input values: 1,2,...,h1000000). It returns the value input by the user minus 1. Outputs: 0,1,2,...,FFFFFF
//---------------------------------------------------
module vef98b5_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE-1;
endmodule
//---- Top entity
module vd84ae0 (
input [23:0] v06bdfb,
input [23:0] va89056,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:23] w4;
wire [0:23] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
wire [0:7] w11;
assign v4642b6 = w0;
assign w4 = v06bdfb;
assign w5 = va89056;
vb2762a vb6832a (
.v4642b6(w1),
.v715730(w8),
.vf191e6(w11)
);
vb2762a v302658 (
.v4642b6(w2),
.v715730(w7),
.vf191e6(w10)
);
vae245c v9196c7 (
.vcbab45(w0),
.v3ca442(w1),
.v0e28cb(w2),
.v033bf6(w3)
);
v6fef69 vb1e577 (
.v9804b7(w5),
.vd83cb2(w9),
.v243fb2(w10),
.va2a3a1(w11)
);
v6fef69 v62b64f (
.v9804b7(w4),
.vd83cb2(w6),
.v243fb2(w7),
.va2a3a1(w8)
);
vb2762a v9a65c6 (
.v4642b6(w3),
.v715730(w6),
.vf191e6(w9)
);
endmodule
//---------------------------------------------------
//-- comp2-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-24bit: Comparator of two 24-bit numbers
//---------------------------------------------------
//---- Top entity
module vb2762a (
input [7:0] v715730,
input [7:0] vf191e6,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w3 = v715730;
assign w4 = vf191e6;
v438230 v577a36 (
.v4642b6(w2),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w2)
);
v6bdcd9 v921a9f (
.vcc8c7c(w4),
.v651522(w7),
.v2cc41f(w8)
);
v6bdcd9 v8cfa4d (
.vcc8c7c(w3),
.v651522(w5),
.v2cc41f(w6)
);
v438230 vfc1765 (
.v4642b6(w1),
.v693354(w5),
.v5369cd(w7)
);
endmodule
//---------------------------------------------------
//-- comp2-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-8bit: Comparator of two 8-bit numbers
//---------------------------------------------------
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module vae245c (
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v033bf6;
assign w1 = v0e28cb;
assign w2 = v3ca442;
assign vcbab45 = w4;
vba518e v19b5b0 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
vba518e vf3ef0f (
.v3ca442(w2),
.v0e28cb(w3),
.vcbab45(w4)
);
endmodule
//---------------------------------------------------
//-- AND3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6fef69 (
input [23:0] v9804b7,
output [7:0] vd83cb2,
output [7:0] v243fb2,
output [7:0] va2a3a1
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:23] w3;
assign v243fb2 = w0;
assign vd83cb2 = w1;
assign va2a3a1 = w2;
assign w3 = v9804b7;
v6fef69_v9a2a06 v9a2a06 (
.o1(w0),
.o2(w1),
.o0(w2),
.i(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-one-third: Split the 24-bits bus into three buses of the same size
//---------------------------------------------------
module v6fef69_v9a2a06 (
input [23:0] i,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v97d607 (
input v6dda25,
input ve556f1,
output [23:0] v9e1c43,
output ve37344
);
wire w0;
wire [0:23] w1;
wire [0:23] w2;
wire w3;
wire [0:23] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v9e1c43 = w4;
assign ve37344 = w5;
assign w4 = w1;
v5495b5 v5e4c9c (
.v782748(w0),
.vb02eea(w1),
.v15c6e6(w2),
.v6dda25(w3)
);
v9c4559 v62e821 (
.v005b83(w1),
.v53d485(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 24-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v5495b5 (
input v6dda25,
input v782748,
input [23:0] v15c6e6,
output [23:0] vb02eea
);
wire [0:23] w0;
wire [0:23] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign vb02eea = w0;
assign w1 = v15c6e6;
assign w8 = v6dda25;
assign w9 = v6dda25;
assign w10 = v6dda25;
assign w11 = v782748;
assign w12 = v782748;
assign w13 = v782748;
assign w9 = w8;
assign w10 = w8;
assign w10 = w9;
assign w12 = w11;
assign w13 = w11;
assign w13 = w12;
v6fef69 vad6f1d (
.v9804b7(w1),
.va2a3a1(w5),
.v243fb2(w6),
.vd83cb2(w7)
);
v33e50d vba7365 (
.v6d326e(w0),
.v77c6e9(w2),
.vf7d213(w3),
.vba04ee(w4)
);
vcf4344 v13ddeb (
.vc1f0d2(w2),
.vd85d4e(w5),
.v6dda25(w10),
.v782748(w13)
);
vcf4344 v08e1bd (
.vc1f0d2(w3),
.vd85d4e(w6),
.v6dda25(w9),
.v782748(w12)
);
vcf4344 v5c3b0f (
.vc1f0d2(w4),
.vd85d4e(w7),
.v6dda25(w8),
.v782748(w11)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x24: 24 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v33e50d (
input [7:0] vba04ee,
input [7:0] vf7d213,
input [7:0] v77c6e9,
output [23:0] v6d326e
);
wire [0:23] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
assign v6d326e = w0;
assign w1 = vf7d213;
assign w2 = v77c6e9;
assign w3 = vba04ee;
v33e50d_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2),
.i2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-one-third: Join the three buses into an 24-bits Bus
//---------------------------------------------------
module v33e50d_v9a2a06 (
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [23:0] o
);
assign o = {i2, i1, i0};
endmodule
//---- Top entity
module vcf4344 (
input v6dda25,
input v782748,
input [7:0] vd85d4e,
output [7:0] vc1f0d2
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w2 = vd85d4e;
assign vc1f0d2 = w3;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v5c75f6 vbdef88 (
.v50034e(w0),
.v4de61b(w1),
.v6dda25(w7),
.v782748(w9)
);
v6bdcd9 vc95779 (
.v2cc41f(w1),
.vcc8c7c(w2),
.v651522(w4)
);
vafb28f v618315 (
.v3c88fc(w0),
.va9ac17(w3),
.v515fe7(w5)
);
v5c75f6 v6188f9 (
.v4de61b(w4),
.v50034e(w5),
.v6dda25(w6),
.v782748(w8)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x08: Eight D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v9c4559 #(
parameter v6c5139 = 1
) (
input [23:0] v005b83,
output v4642b6,
output [23:0] v53d485
);
localparam p1 = v6c5139;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
assign v4642b6 = w0;
assign w2 = v005b83;
assign v53d485 = w3;
v44c099 #(
.vd73390(p1)
) v8c0045 (
.v4642b6(w0),
.vd90f46(w2),
.v8826c0(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-24bit: Increment a 24-bits number by one
//---------------------------------------------------
//---- Top entity
module v44c099 #(
parameter vd73390 = 0
) (
input [23:0] vd90f46,
output v4642b6,
output [23:0] v8826c0
);
localparam p1 = vd73390;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire [0:23] w4;
assign v4642b6 = w0;
assign v8826c0 = w2;
assign w3 = vd90f46;
v4c802f #(
.vc5c8ea(p1)
) ve78914 (
.v8513f7(w4)
);
v91404d v19ed8b (
.v4642b6(w0),
.vb5c06c(w2),
.v7959e8(w3),
.vb5a2f2(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-24bit: Adder of 24-bit operand and 24-bit constant
//---------------------------------------------------
//---- Top entity
module v4c802f #(
parameter vc5c8ea = 0
) (
output [23:0] v8513f7
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign v8513f7 = w1;
v4c802f_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits generic constant
//---------------------------------------------------
module v4c802f_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v91404d (
input [23:0] vb5a2f2,
input [23:0] v7959e8,
output v4642b6,
output [23:0] vb5c06c
);
wire w0;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
wire [0:15] w5;
wire [0:23] w6;
wire [0:15] w7;
wire [0:23] w8;
wire [0:15] w9;
wire [0:7] w10;
wire [0:23] w11;
wire [0:7] w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
assign v4642b6 = w4;
assign w6 = v7959e8;
assign w8 = vb5a2f2;
assign vb5c06c = w11;
vcb23aa v8e0bba (
.v4642b6(w0),
.v62bf25(w2),
.v39966a(w16),
.veb2f59(w17)
);
vc3c498 v917bbf (
.vb9cfc3(w0),
.veeaa8e(w1),
.v4642b6(w3),
.v45c6ee(w14),
.v20212e(w15)
);
v8cc49c v03c3e3 (
.vb334ae(w1),
.v2b8a97(w2),
.v14a530(w5)
);
vab13f0 v43653c (
.vb18564(w6),
.vf0a06e(w7),
.v5246f6(w17)
);
v306ca3 v177126 (
.v91b9c1(w7),
.vef5eee(w13),
.vd3ef3b(w15)
);
vab13f0 vf15711 (
.vb18564(w8),
.vf0a06e(w9),
.v5246f6(w16)
);
v306ca3 vf9ed57 (
.v91b9c1(w9),
.vef5eee(w12),
.vd3ef3b(w14)
);
vc3c498 vf0db78 (
.vb9cfc3(w3),
.v4642b6(w4),
.veeaa8e(w10),
.v45c6ee(w12),
.v20212e(w13)
);
va52e3b v67022b (
.vbf8961(w5),
.vf7d213(w10),
.v6d326e(w11)
);
endmodule
//---------------------------------------------------
//-- Adder-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-24bits: Adder of two operands of 24 bits
//---------------------------------------------------
//---- Top entity
module vab13f0 (
input [23:0] vb18564,
output [15:0] vf0a06e,
output [7:0] v5246f6
);
wire [0:23] w0;
wire [0:15] w1;
wire [0:7] w2;
assign w0 = vb18564;
assign vf0a06e = w1;
assign v5246f6 = w2;
vab13f0_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-16-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-16-8: Split the 24-bits bus into two buses of 16 and 8 wires
//---------------------------------------------------
module vab13f0_v9a2a06 (
input [23:0] i,
output [15:0] o1,
output [7:0] o0
);
assign o1 = i[23:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module va52e3b (
input [7:0] vf7d213,
input [15:0] vbf8961,
output [23:0] v6d326e
);
wire [0:15] w0;
wire [0:23] w1;
wire [0:7] w2;
assign w0 = vbf8961;
assign v6d326e = w1;
assign w2 = vf7d213;
va52e3b_v9a2a06 v9a2a06 (
.i0(w0),
.o(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-8-16 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-8-16: Join the two buses into an 24-bits Bus
//---------------------------------------------------
module va52e3b_v9a2a06 (
input [7:0] i1,
input [15:0] i0,
output [23:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule
//---------------------------------------------------
//-- Reg-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x08: 8-bits register
//---------------------------------------------------
//---- Top entity
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule
//---------------------------------------------------
//-- Reg-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x04: 4-bits register
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v9c1f69 (
input [7:0] vcc8c7c,
output [2:0] v1045ee,
output [4:0] v52d10b
);
wire [0:7] w0;
wire [0:4] w1;
wire [0:2] w2;
assign w0 = vcc8c7c;
assign v52d10b = w1;
assign v1045ee = w2;
v9c1f69_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-3-5
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-3-5: Split the 8-bits bus into two buses of 3 and 5 wires
//---------------------------------------------------
module v9c1f69_v9a2a06 (
input [7:0] i,
output [2:0] o1,
output [4:0] o0
);
assign o1 = i[7:5];
assign o0 = i[4:0];
endmodule
//---- Top entity
module v89d234 #(
parameter v422d28 = 0
) (
input v41eb95,
input [7:0] v39f831,
input vf892a0,
output [7:0] vb1c024
);
localparam p0 = v422d28;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
assign vb1c024 = w1;
assign w2 = v39f831;
assign w3 = vf892a0;
assign w4 = v41eb95;
v89d234_v9148cb #(
.INI(p0)
) v9148cb (
.q(w1),
.d(w2),
.load(w3),
.clk(w4)
);
endmodule
//---------------------------------------------------
//-- Registro
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Registro de 8 bits
//---------------------------------------------------
module v89d234_v9148cb #(
parameter INI = 0
) (
input clk,
input [7:0] d,
input load,
output [7:0] q
);
localparam N = 8;
reg [N-1:0] q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 8-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 8-bits generic constant (0-255)
//---------------------------------------------------
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule
//---------------------------------------------------
//-- 8-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (8-bit channels)
//---------------------------------------------------
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module v78be07 (
input [7:0] vcc8c7c,
output v2ce16c,
output [6:0] vdb77b6
);
wire [0:7] w0;
wire [0:6] w1;
wire w2;
assign w0 = vcc8c7c;
assign vdb77b6 = w1;
assign v2ce16c = w2;
v78be07_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-1-7
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of 1 and 7 wires
//---------------------------------------------------
module v78be07_v9a2a06 (
input [7:0] i,
output o1,
output [6:0] o0
);
assign o1 = i[7];
assign o0 = i[6:0];
endmodule
//---- Top entity
module v4c1570 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule
//---------------------------------------------------
//-- RS-FF-set
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RS-FF-set. RS Flip-flop with priority set
//---------------------------------------------------
//---- Top entity
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule
//---------------------------------------------------
//-- 8bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 8bits constant value: 0
//---------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 14:26:00
// Design Name:
// Module Name: decoder_74138_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decoder_74138_dataflow_tb(
);
reg [2:0] x;
reg g1, g2a_n, g2b_n;
wire [7:0] y;
integer k;
decoder_74138_dataflow DUT (.g1(g1), .g2a_n(g2a_n), .g2b_n(g2b_n), .x(x), .y(y));
initial
begin
x = 0; g1 = 0; g2a_n = 1; g2b_n = 1;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 1; g2a_n = 0; g2b_n = 1;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 0; g2a_n = 1; g2b_n = 0;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 1; g2a_n = 0; g2b_n = 0;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_controlFlagsOut (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 1: 0] in_port;
input reset_n;
wire clk_en;
wire [ 1: 0] data_in;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {2 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
module vga_text(
vidon,
hc,
vc,
M,
SW,
rom_addr,
R,
G,
B
);
input vidon;
input [9:0] hc;
input [9:0] vc;
input [15:0] M;
input [7:0] SW;
output [3:0] rom_addr;
output [7:0] R;
output [7:0] G;
output [7:0] B;
localparam hbp = 144 /*10'b0010010000*/, // Horizontal Back Porch = 144 (128+16)
vbp = 31 /*10'b0000011111*/, // Vertical Back Porch = 31 (2+29)
w = 16, // Width of the sprite
h = 16; // Height of the sprite
reg [10:0] C1, R1; // Upper and left-hand corner position of the screen
reg [10:0] rom_addrr, rom_pix; // Rom Address and Rom Pixels
reg spriteon;
reg [7:0] Rr, Gg, Bb;
// Assignments
assign rom_addr = rom_addrr[3:0];
assign R = Rr;
assign G = Gg;
assign B = Bb;
wire [10:0] j = rom_pix;
// Get C1 and R1 using switches
always @(SW)
begin
C1 <= {2'b00, SW[3:0], 5'b00001}; // Get C1 (Horizontal)
R1 <= {2'b00, SW[7:4], 5'b00001}; // Get R1 (Vertical))
rom_addrr <= vc - vbp - R1; // Determines the address for rom to be displayed
rom_pix <= hc - hbp - C1; // Determines the pixel to be displayed
end
// Set spriteon
always @ *
begin
spriteon <= (((hc > C1 + hbp) && (hc < C1 + hbp + w) && (vc > R1 + vbp) && (vc < R1 + vbp + h)) ? 1'b1 : 1'b0);
end
// Display Sprite
always @ (spriteon, vidon, rom_pix, M)
begin
Rr <= 9'bz;
Gg <= 9'bz;
Bb <= 9'bz;
if(spriteon == 1'b1 && vidon == 1'b1)
begin
Rr <= {M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j]};
Gg <= {M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j]};
Bb <= {M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j],M[j]};
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref,
rx_sync,
rx_data_p,
rx_data_n,
spi_csn,
spi_clk,
spi_sdio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref;
output rx_sync;
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
output spi_csn;
output spi_clk;
inout spi_sdio;
// internal registers
reg dma_0_wr = 'd0;
reg [63:0] dma_0_data = 'd0;
reg dma_1_wr = 'd0;
reg [63:0] dma_1_data = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire rx_ref_clk;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire adc_clk;
wire [127:0] rx_gt_data;
wire adc_0_enable_a;
wire [31:0] adc_0_data_a;
wire adc_0_enable_b;
wire [31:0] adc_0_data_b;
wire adc_1_enable_a;
wire [31:0] adc_1_data_a;
wire adc_1_enable_b;
wire [31:0] adc_1_data_b;
assign spi_csn = spi0_csn[0];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
// pack & unpack here
always @(posedge adc_clk) begin
case ({adc_0_enable_b, adc_0_enable_a})
2'b11: begin
dma_0_wr <= 1'b1;
dma_0_data[63:48] <= adc_0_data_b[31:16];
dma_0_data[47:32] <= adc_0_data_a[31:16];
dma_0_data[31:16] <= adc_0_data_b[15: 0];
dma_0_data[15: 0] <= adc_0_data_a[15: 0];
end
2'b10: begin
dma_0_wr <= ~dma_0_wr;
dma_0_data[63:48] <= adc_0_data_b[31:16];
dma_0_data[47:32] <= adc_0_data_b[15: 0];
dma_0_data[31:16] <= dma_0_data[63:48];
dma_0_data[15: 0] <= dma_0_data[47:32];
end
2'b01: begin
dma_0_wr <= ~dma_0_wr;
dma_0_data[63:48] <= adc_0_data_a[31:16];
dma_0_data[47:32] <= adc_0_data_a[15: 0];
dma_0_data[31:16] <= dma_0_data[63:48];
dma_0_data[15: 0] <= dma_0_data[47:32];
end
default: begin
dma_0_wr <= 1'b0;
dma_0_data[63:48] <= 16'd0;
dma_0_data[47:32] <= 16'd0;
dma_0_data[31:16] <= 16'd0;
dma_0_data[15: 0] <= 16'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_1_enable_b, adc_1_enable_a})
2'b11: begin
dma_1_wr <= 1'b1;
dma_1_data[63:48] <= adc_1_data_b[31:16];
dma_1_data[47:32] <= adc_1_data_a[31:16];
dma_1_data[31:16] <= adc_1_data_b[15: 0];
dma_1_data[15: 0] <= adc_1_data_a[15: 0];
end
2'b10: begin
dma_1_wr <= ~dma_1_wr;
dma_1_data[63:48] <= adc_1_data_b[31:16];
dma_1_data[47:32] <= adc_1_data_b[15: 0];
dma_1_data[31:16] <= dma_1_data[63:48];
dma_1_data[15: 0] <= dma_1_data[47:32];
end
2'b01: begin
dma_1_wr <= ~dma_1_wr;
dma_1_data[63:48] <= adc_1_data_a[31:16];
dma_1_data[47:32] <= adc_1_data_a[15: 0];
dma_1_data[31:16] <= dma_1_data[63:48];
dma_1_data[15: 0] <= dma_1_data[47:32];
end
default: begin
dma_1_wr <= 1'b0;
dma_1_data[63:48] <= 16'd0;
dma_1_data[47:32] <= 16'd0;
dma_1_data[31:16] <= 16'd0;
dma_1_data[15: 0] <= 16'd0;
end
endcase
end
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
assign spi_adc_clk = spi_clk;
assign spi_clk_clk = spi_clk;
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_0_data_a (adc_0_data_a),
.adc_0_data_b (adc_0_data_b),
.adc_0_enable_a (adc_0_enable_a),
.adc_0_enable_b (adc_0_enable_b),
.adc_0_valid_a (),
.adc_0_valid_b (),
.adc_1_data_a (adc_1_data_a),
.adc_1_data_b (adc_1_data_b),
.adc_1_enable_a (adc_1_enable_a),
.adc_1_enable_b (adc_1_enable_b),
.adc_1_valid_a (),
.adc_1_valid_b (),
.adc_clk (adc_clk),
.dma_0_data (dma_0_data),
.dma_0_sync (1'b1),
.dma_0_wr (dma_0_wr),
.dma_1_data (dma_1_data),
.dma_1_sync (1'b1),
.dma_1_wr (dma_1_wr),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_gt_data (rx_gt_data),
.rx_gt_data_0 (rx_gt_data[63:0]),
.rx_gt_data_1 (rx_gt_data[127:64]),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:14:25 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire DP_OP_15J58_122_5662_n65, DP_OP_15J58_122_5662_n64,
DP_OP_15J58_122_5662_n63, DP_OP_15J58_122_5662_n62,
DP_OP_15J58_122_5662_n61, n30, n31, n32, n33, n34, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66,
n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94,
n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106,
n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117,
n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139,
n140;
wire [6:5] BIGGER16_lower_in2_signed;
AFCSIHCONX2TS DP_OP_15J58_122_5662_U72 ( .A(in1[5]), .B(
BIGGER16_lower_in2_signed[5]), .CS(DP_OP_15J58_122_5662_n65), .CO0N(
DP_OP_15J58_122_5662_n64), .CO1N(DP_OP_15J58_122_5662_n63) );
AFCSHCINX2TS DP_OP_15J58_122_5662_U71 ( .CI1N(DP_OP_15J58_122_5662_n63), .B(
BIGGER16_lower_in2_signed[6]), .A(in1[6]), .CI0N(
DP_OP_15J58_122_5662_n64), .CS(DP_OP_15J58_122_5662_n65), .CO1(
DP_OP_15J58_122_5662_n61), .CO0(DP_OP_15J58_122_5662_n62), .S(res[6])
);
OAI2BB1X2TS U46 ( .A0N(n89), .A1N(n32), .B0(n87), .Y(res[16]) );
NAND2XLTS U47 ( .A(n78), .B(n96), .Y(n97) );
OR2X2TS U48 ( .A(n86), .B(in1[15]), .Y(n32) );
XNOR2X2TS U49 ( .A(n82), .B(in2[14]), .Y(n83) );
NAND2X1TS U50 ( .A(n84), .B(n30), .Y(n82) );
NOR2XLTS U51 ( .A(n137), .B(n76), .Y(n73) );
CLKINVX1TS U52 ( .A(n110), .Y(n63) );
NOR2X2TS U53 ( .A(n114), .B(n119), .Y(n106) );
NAND2X1TS U54 ( .A(n72), .B(n30), .Y(n68) );
INVX2TS U55 ( .A(in2[12]), .Y(n75) );
NAND2BX1TS U56 ( .AN(n57), .B(n56), .Y(n58) );
NAND2X2TS U57 ( .A(n60), .B(in1[8]), .Y(n120) );
NOR2X2TS U58 ( .A(n60), .B(in1[8]), .Y(n119) );
NOR2X2TS U59 ( .A(n72), .B(in2[11]), .Y(n76) );
NAND2BX1TS U60 ( .AN(n56), .B(n57), .Y(n54) );
NAND2X2TS U61 ( .A(n67), .B(n66), .Y(n72) );
NOR2X1TS U62 ( .A(n51), .B(n137), .Y(n53) );
INVX2TS U63 ( .A(in2[10]), .Y(n66) );
NAND2X1TS U64 ( .A(n44), .B(add_sub), .Y(n37) );
INVX2TS U65 ( .A(in2[8]), .Y(n52) );
NOR2X2TS U66 ( .A(n34), .B(n137), .Y(n36) );
NAND2X1TS U67 ( .A(n49), .B(n30), .Y(n50) );
BUFX3TS U68 ( .A(add_sub), .Y(n30) );
XNOR2X2TS U69 ( .A(n48), .B(n66), .Y(n62) );
OAI21XLTS U70 ( .A0(n113), .A1(n119), .B0(n120), .Y(n118) );
ADDHXLTS U71 ( .A(in2[0]), .B(in1[0]), .CO(n129), .S(res[0]) );
NAND2X2TS U72 ( .A(n92), .B(n91), .Y(n94) );
OR2X4TS U73 ( .A(n81), .B(in2[13]), .Y(n84) );
NAND2X2TS U74 ( .A(n62), .B(in1[10]), .Y(n110) );
XOR2X1TS U75 ( .A(n102), .B(n101), .Y(res[12]) );
INVX2TS U76 ( .A(n103), .Y(n71) );
OAI21X1TS U77 ( .A0(n113), .A1(n109), .B0(n108), .Y(n112) );
NAND2X2TS U78 ( .A(n81), .B(n30), .Y(n77) );
NAND2X2TS U79 ( .A(n76), .B(n75), .Y(n81) );
NAND2X4TS U80 ( .A(n55), .B(n54), .Y(n59) );
NOR2X4TS U81 ( .A(n49), .B(in2[9]), .Y(n67) );
NOR2X4TS U82 ( .A(n44), .B(n43), .Y(n138) );
NAND3X2TS U83 ( .A(n42), .B(n41), .C(n40), .Y(n43) );
INVX4TS U84 ( .A(add_sub), .Y(n137) );
NAND2X2TS U85 ( .A(n32), .B(n87), .Y(n88) );
NOR2X4TS U86 ( .A(n83), .B(in1[14]), .Y(n90) );
NAND2X2TS U87 ( .A(n83), .B(in1[14]), .Y(n91) );
NAND2X2TS U88 ( .A(n79), .B(in1[13]), .Y(n96) );
XNOR2X2TS U89 ( .A(n85), .B(in2[15]), .Y(n86) );
OR2X2TS U90 ( .A(n79), .B(in1[13]), .Y(n78) );
OAI21X2TS U91 ( .A0(n84), .A1(in2[14]), .B0(n30), .Y(n85) );
AOI21X2TS U92 ( .A0(n31), .A1(n107), .B0(n63), .Y(n64) );
NAND2X2TS U93 ( .A(n74), .B(in1[12]), .Y(n99) );
NOR2X2TS U94 ( .A(n74), .B(in1[12]), .Y(n98) );
OR2X2TS U95 ( .A(n70), .B(in1[11]), .Y(n69) );
NAND2X2TS U96 ( .A(n31), .B(n106), .Y(n65) );
INVX6TS U97 ( .A(n123), .Y(n113) );
NAND2X6TS U98 ( .A(n59), .B(n58), .Y(n123) );
XOR2X1TS U99 ( .A(n55), .B(n46), .Y(res[7]) );
XOR2X1TS U100 ( .A(BIGGER16_lower_in2_signed[5]), .B(n136), .Y(res[5]) );
NOR2X2TS U101 ( .A(n67), .B(n137), .Y(n48) );
MX2X4TS U102 ( .A(DP_OP_15J58_122_5662_n62), .B(DP_OP_15J58_122_5662_n61),
.S0(DP_OP_15J58_122_5662_n65), .Y(n55) );
NAND2X2TS U103 ( .A(n124), .B(n30), .Y(n33) );
NAND2X4TS U104 ( .A(n34), .B(n35), .Y(n44) );
XNOR2X4TS U105 ( .A(n50), .B(in2[9]), .Y(n61) );
XNOR2X2TS U106 ( .A(n73), .B(n75), .Y(n74) );
NOR2X8TS U107 ( .A(in2[0]), .B(in2[1]), .Y(n34) );
XNOR2X2TS U108 ( .A(n53), .B(n52), .Y(n60) );
INVX2TS U109 ( .A(n96), .Y(n80) );
OR2X2TS U110 ( .A(n44), .B(in2[3]), .Y(n124) );
INVX2TS U111 ( .A(in1[7]), .Y(n57) );
OAI21X2TS U112 ( .A0(n114), .A1(n120), .B0(n115), .Y(n107) );
XNOR2X2TS U113 ( .A(n77), .B(in2[13]), .Y(n79) );
AND2X2TS U114 ( .A(in1[2]), .B(n128), .Y(n38) );
NOR2X4TS U115 ( .A(n61), .B(in1[9]), .Y(n114) );
NAND2X2TS U116 ( .A(n61), .B(in1[9]), .Y(n115) );
OR2X2TS U117 ( .A(n62), .B(in1[10]), .Y(n31) );
INVX2TS U118 ( .A(n107), .Y(n108) );
NAND2X2TS U119 ( .A(n70), .B(in1[11]), .Y(n103) );
NAND2X2TS U120 ( .A(n86), .B(in1[15]), .Y(n87) );
XOR2X1TS U121 ( .A(n56), .B(in1[7]), .Y(n46) );
XNOR2X1TS U122 ( .A(n123), .B(n122), .Y(res[8]) );
NAND2X1TS U123 ( .A(n121), .B(n120), .Y(n122) );
XNOR2X1TS U124 ( .A(n118), .B(n117), .Y(res[9]) );
NAND2X1TS U125 ( .A(n116), .B(n115), .Y(n117) );
INVX2TS U126 ( .A(n114), .Y(n116) );
XNOR2X1TS U127 ( .A(n112), .B(n111), .Y(res[10]) );
NAND2X1TS U128 ( .A(n31), .B(n110), .Y(n111) );
INVX2TS U129 ( .A(n106), .Y(n109) );
XNOR2X1TS U130 ( .A(n105), .B(n104), .Y(res[11]) );
NAND2X1TS U131 ( .A(n69), .B(n103), .Y(n104) );
NAND2X1TS U132 ( .A(n100), .B(n99), .Y(n102) );
INVX2TS U133 ( .A(n98), .Y(n100) );
XNOR2X1TS U134 ( .A(n97), .B(n95), .Y(res[13]) );
INVX2TS U135 ( .A(n90), .Y(n92) );
NAND2X1TS U136 ( .A(n47), .B(n30), .Y(n45) );
NAND2X2TS U137 ( .A(n138), .B(n139), .Y(n47) );
NOR2X1TS U138 ( .A(n138), .B(n137), .Y(n140) );
NOR2X4TS U139 ( .A(n47), .B(in2[7]), .Y(n51) );
XNOR2X2TS U140 ( .A(n37), .B(in2[3]), .Y(n132) );
XNOR2X2TS U141 ( .A(n33), .B(in2[4]), .Y(n134) );
XNOR2X2TS U142 ( .A(n45), .B(in2[7]), .Y(n56) );
XNOR2X2TS U143 ( .A(n125), .B(in2[5]), .Y(BIGGER16_lower_in2_signed[5]) );
OAI21X2TS U144 ( .A0(n124), .A1(in2[4]), .B0(n30), .Y(n125) );
XNOR2X4TS U145 ( .A(n36), .B(n35), .Y(n128) );
INVX2TS U146 ( .A(n119), .Y(n121) );
INVX4TS U147 ( .A(in2[2]), .Y(n35) );
CMPR32X2TS U148 ( .A(n38), .B(in1[3]), .C(n132), .CO(n39) );
ADDFHX4TS U149 ( .A(n134), .B(in1[4]), .CI(n39), .CO(
DP_OP_15J58_122_5662_n65) );
INVX2TS U150 ( .A(in2[4]), .Y(n42) );
INVX2TS U151 ( .A(in2[3]), .Y(n41) );
INVX2TS U152 ( .A(in2[5]), .Y(n40) );
INVX2TS U153 ( .A(in2[6]), .Y(n139) );
NAND2X4TS U154 ( .A(n51), .B(n52), .Y(n49) );
OAI21X4TS U155 ( .A0(n65), .A1(n113), .B0(n64), .Y(n105) );
XNOR2X2TS U156 ( .A(n68), .B(in2[11]), .Y(n70) );
AOI21X4TS U157 ( .A0(n105), .A1(n69), .B0(n71), .Y(n101) );
OAI21X4TS U158 ( .A0(n101), .A1(n98), .B0(n99), .Y(n95) );
AOI21X4TS U159 ( .A0(n95), .A1(n78), .B0(n80), .Y(n93) );
OAI21X4TS U160 ( .A0(n93), .A1(n90), .B0(n91), .Y(n89) );
XNOR2X1TS U161 ( .A(n89), .B(n88), .Y(res[15]) );
XOR2X1TS U162 ( .A(n94), .B(n93), .Y(res[14]) );
NAND2X1TS U163 ( .A(add_sub), .B(in2[0]), .Y(n126) );
XNOR2X1TS U164 ( .A(n126), .B(in2[1]), .Y(n130) );
CMPR32X2TS U165 ( .A(in1[2]), .B(n128), .C(n127), .CO(n131), .S(res[2]) );
CMPR32X2TS U166 ( .A(in1[1]), .B(n130), .C(n129), .CO(n127), .S(res[1]) );
CMPR32X2TS U167 ( .A(in1[3]), .B(n132), .C(n131), .CO(n133), .S(res[3]) );
CMPR32X2TS U168 ( .A(in1[4]), .B(n134), .C(n133), .CO(n135), .S(res[4]) );
XOR2X1TS U169 ( .A(in1[5]), .B(n135), .Y(n136) );
XNOR2X1TS U170 ( .A(n140), .B(n139), .Y(BIGGER16_lower_in2_signed[6]) );
initial $sdf_annotate("Approx_adder_GeArN8R2P4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_2_V
`define SKY130_FD_SC_MS__O2BB2AI_2_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_2_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_umult.v
// /___/ /\ Timestamp: Fri Oct 02 08:35:52 2020
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// # of Modules : 1
// Design Name : gsu_umult
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gsu_umult (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [15 : 0] p;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000011 ;
wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000003 (
.A({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , a[7], a[6],
a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , b[7], b[6],
b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ,
p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8], p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]})
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000011 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
11/08/2011
fixed the wb_ack to be 0 when nothing is selected
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
[email protected]
*/
`timescale 1ns/1ps
module wishbone_interconnect (
clk,
rst,
i_m_we,
i_m_cyc,
i_m_sel,
i_m_stb,
o_m_ack,
i_m_dat,
o_m_dat,
i_m_adr,
o_m_int,
//virtual slave master 0
o_s0_we,
o_s0_cyc,
o_s0_sel,
o_s0_stb,
i_s0_ack,
o_s0_dat,
i_s0_dat,
o_s0_adr,
i_s0_int,
//virtual slave master 0
o_s1_we,
o_s1_cyc,
o_s1_sel,
o_s1_stb,
i_s1_ack,
o_s1_dat,
i_s1_dat,
o_s1_adr,
i_s1_int
);
parameter ADDR_0 = 8'h00;
parameter ADDR_1 = 8'h01;
parameter ADDR_FF = 8'hFF;
//state
//control signals
input clk;
input rst;
//wishbone slave signals
input i_m_we;
input i_m_stb;
input i_m_cyc;
input [3:0] i_m_sel;
input [31:0] i_m_adr;
input [31:0] i_m_dat;
output reg [31:0] o_m_dat = 32'h0;
output reg o_m_ack = 1'h0;
output o_m_int;
output o_s0_we;
output o_s0_stb;
output o_s0_cyc;
output [3:0] o_s0_sel;
output [31:0] o_s0_adr;
output [31:0] o_s0_dat;
input [31:0] i_s0_dat;
input i_s0_ack;
input i_s0_int;
output o_s1_we;
output o_s1_stb;
output o_s1_cyc;
output [3:0] o_s1_sel;
output [31:0] o_s1_adr;
output [31:0] o_s1_dat;
input [31:0] i_s1_dat;
input i_s1_ack;
input i_s1_int;
//this should be parameterized
wire [7:0]slave_select;
assign slave_select = i_m_adr[31:24];
wire [31:0] interrupts;
/*
initial begin
$monitor("%t, int: %h, i_s0_int: %h, s1_int: %h", $time, interrupts, s0_int, s1_int);
$monitor ("%t adr: %h, stb: %h, ack: %h", $time, i_m_adr, i_m_stb, o_m_ack);
end
*/
//data
always @ (slave_select or i_s0_dat or i_s1_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
default: begin
//$display("WBI: interrupt address selected");
o_m_dat <= interrupts;
end
endcase
end
//ack
always @ (slave_select or i_s0_ack or i_s1_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int
//set up the interrupts flags
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
//set all other interrupts to zero
assign interrupts[31:2] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0 , i_m_adr[23:0]}: 0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0 , i_m_adr[23:0]}: 0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 0;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_flow_control.v
// /___/ /\ Date Last Modified: $Date: 2010/12/13 23:13:50 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex 6
//Design Name: DDR2/DDR3
//Purpose: This module is the main flow control between cmd_gen.v,
// write_data_path and read_data_path modules.
//Reference:
//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface.
//
//*****************************************************************************
`timescale 1ps/1ps
module memc_flow_control #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter NUM_DQ_PINS = 32,
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 4,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3"
)
(
input clk_i,
input [9:0] rst_i,
input [3:0] data_mode_i,
input [5:0] cmds_gap_delay_value,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [BL_WIDTH - 1:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
input mcb_wr_full_i,
output reg [2:0] cmd_o,
output [31:0] addr_o,
output reg [BL_WIDTH-1:0] bl_o,
output cmd_en_o, // interface to write data path module
// *** interface to qdr ****
output reg qdr_rd_cmd_o,
// *************************
input mcb_wr_en_i,
input last_word_wr_i,
input wdp_rdy_i,
output reg wdp_valid_o,
output reg wdp_validB_o,
output reg wdp_validC_o,
output [31:0] wr_addr_o,
output [BL_WIDTH-1:0] wr_bl_o,
// interface to read data path module
input rdp_rdy_i,
output reg rdp_valid_o,
output [31:0] rd_addr_o,
output [BL_WIDTH-1:0] rd_bl_o
);
//FSM State Defination
localparam READY = 5'b00001,
READ = 5'b00010,
WRITE = 5'b00100,
CMD_WAIT = 5'b01000,
REFRESH_ST = 5'b10000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101; // this defination is local to this traffic gen and is not defined
reg cmd_fifo_rdy;
wire cmd_rd;
wire cmd_wr; // need equation
wire cmd_others;
reg push_cmd;
//reg xfer_cmd;
reg rd_vld ;
reg wr_vld;
reg cmd_rdy;
reg [31:0] addr_r;
reg [2:0] bank_cnt;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [BL_WIDTH - 1:0] bl_reg;
reg [BL_WIDTH :0] cmd_counts;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [4:0] current_state;
reg [4:0] next_state;
reg [3:0] tstpointA;
reg push_cmd_r;
reg wait_done;
reg cmd_en_r1 ;
reg wr_in_progress,wr_in_progress_r;
reg wrcmd_in_progress;
//reg [10:0] INC_COUNTS;
reg push_cmd_valid;
reg wr_path_full_r;
reg rdcmd_in_progress;
//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4;
localparam MEM_BURST_INT = MEM_BURST_LEN ;
reg[5:0] commands_delay_counters;
reg goahead;
reg cmd_rdy_latch;
reg cmd_en_r2; // Spartan 6 use only
reg [3:0] addr_INC;
reg [8*50:0] flow_command;
always @ (posedge clk_i) begin
if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6" )
addr_INC <= #TCQ 0;
else // *** need to uncomment this for Fuji
addr_INC <= #TCQ MEM_BURST_LEN[3:0]; // *** need to uncomment this for Fuji
end
initial begin
addr_r = 'b0;
end
/*
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
*/
// mcb_command bus outputs
always @(posedge clk_i) begin
if (rst_i[0] ) begin
commands_delay_counters <= 5'b00000;
goahead <= 1'b1;
end
else if (cmds_gap_delay_value == 5'd0)
goahead <= 1'b1;
else if ((wr_in_progress || wrcmd_in_progress || rdcmd_in_progress || cmd_rdy_o) ) begin
commands_delay_counters <= 5'b00000;
goahead <= 1'b0;
end
else
if (commands_delay_counters == cmds_gap_delay_value) begin
commands_delay_counters <= commands_delay_counters ;
goahead <= 1'b1;
end
else
commands_delay_counters <= commands_delay_counters + 1'b1;
end
assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ;
always @ (posedge clk_i) begin
cmd_rdy_o <= #TCQ cmd_rdy;
end
//generate
//if (FAMILY == "VIRTEX6") begin
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i))
cmd_en_r1 <= #TCQ 1'b0;
else if ( rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR" ||
mcb_wr_en_i && MEM_TYPE == "QDR")
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full )
cmd_en_r1 <= #TCQ 1'b0;
end
//end endgenerate
generate
if (FAMILY == "SPARTAN6") begin
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_en_r2 <= #TCQ 1'b0;
else
cmd_en_r2 <= cmd_en_r1;
end
end endgenerate
// QDR rd command generation
always @ (posedge clk_i)
begin
if (rst_i[8])
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (cmd_counts == 0 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1)
qdr_rd_cmd_o <= #TCQ 1'b0;
else if ( rdcmd_in_progress )
qdr_rd_cmd_o <= #TCQ 1'b1;
else if (!mcb_cmd_full)
qdr_rd_cmd_o <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (cmd_en_r1 || mcb_cmd_full)//(xfer_cmd)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[9]) begin
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
//else if (xfer_cmd && current_state == READ ) begin // this one has bug
else if (push_cmd_r && current_state == READ ) begin
cmd_o <= #TCQ cmd_i;
bl_o <= #TCQ bl_i - 1'b1;
end
else if ( push_cmd_r && current_state == WRITE) begin
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
always @ (posedge clk_i)
if (push_cmd)
addr_reg <= #TCQ addr_i;
always @ (posedge clk_i)
begin
if (push_cmd && cmd_rd) begin
addr_r <= #TCQ addr_i;
end
else if (push_cmd_r && current_state != READ) begin
addr_r <= #TCQ addr_reg;
end
//else if (xfer_cmd ) begin
else if ((wrcmd_in_progress && ~mcb_cmd_full)|| (rdcmd_in_progress && cmd_en_r1 && ~mcb_cmd_full)) begin
if (cmd_en_r1) begin
// for V6, BL 8, BL 4
addr_r[31:0] <= addr_o + addr_INC;
end
end
end
//assign addr_o[24:0] = addr_r[24:0];
//assign addr_o[27:25] = bank_cnt;
//assign addr_o[31:28] = addr_r[31:28];
//assign addr_o[8:0] = addr_r[8:0];
//assign addr_o[31:9] = 'b0;
assign addr_o = addr_r;
// go directly to wr_datapath and rd_datapath modules
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i ;
assign wr_bl_o = bl_i ;
always @ (posedge clk_i)
begin
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
end
always @ (posedge clk_i)
begin
rdp_valid_o <= rdp_valid;
end
// internal control siganls
always @ (posedge clk_i)
begin
if (rst_i[8])
wait_done <= #TCQ 1'b1;
else if (push_cmd_r)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")
wait_done <= #TCQ 1'b0;
end
//
always @ (posedge clk_i)
begin
push_cmd_r <= #TCQ push_cmd;
end
always @ (posedge clk_i)
if (push_cmd)
begin
cmd_reg <= #TCQ cmd_i;
bl_reg <= #TCQ bl_i - 1'b1;
end
always @ (posedge clk_i)
begin
if (push_cmd)
if (bl_i == 0)
if (MEM_BURST_LEN == 8)
if (nCK_PER_CLK == 4)
cmd_counts <= #TCQ {1'b1, {BL_WIDTH-1{1'b0}}};
else
if (FAMILY == "SPARTAN6")
cmd_counts <= bl_i ;
else
cmd_counts <= #TCQ {1'b1, {BL_WIDTH-2{1'b0}}};
else// not tested yet in MEM_BURST_LEN == 4
cmd_counts <= {(BL_WIDTH -1){1'b1}} ;//- 2;//63;
else
if (MEM_BURST_LEN == 8)
if (nCK_PER_CLK == 4)
cmd_counts <= bl_i ;
else
if (FAMILY == "SPARTAN6")
cmd_counts <= bl_i ;
else
cmd_counts <= {1'b0,bl_i[BL_WIDTH-2:1]};
else // not tested yet in MEM_BURST_LEN == 4
cmd_counts <= bl_i ;//- 1 ;// {1'b0,bl_i[5:1]} -2;
else if ((wrcmd_in_progress || rdcmd_in_progress ) && cmd_en_r1 && ~mcb_cmd_full)
if (MEM_BURST_LEN == 8 && cmd_counts > 0)
// cmd_counts <= cmd_counts - 2;
if (FAMILY == "VIRTEX6")
cmd_counts <= cmd_counts - 1'b1;
else
if (wrcmd_in_progress)
cmd_counts <= cmd_counts - 1'b1;
else
cmd_counts <= 0;
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i ) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;
reg cmd_wr_pending_r1;
always @ (posedge clk_i)
begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)
//else if ( last_word_wr_i && !cmd_fifo_rdy)
else if ( last_word_wr_i )
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd)//xfer_cmd)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
// corner case if fixed read command with fixed bl 64
always @ (posedge clk_i)
begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i )
wr_in_progress <= #TCQ 1'b0;
else if (push_cmd && cmd_wr)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
wrcmd_in_progress <= #TCQ 1'b0;
//else if (last_word_wr_i )
else if (cmd_wr && push_cmd )
wrcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts == 0 || cmd_counts == 1)
wrcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
rdcmd_in_progress <= #TCQ 1'b0;
else if (cmd_rd && push_cmd)
rdcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts <= 1)
rdcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i[0])
current_state <= #TCQ 4'b0001;
else
current_state <= #TCQ next_state;
end
// mcb_flow_control statemachine
always @ (*)
begin
push_cmd = 1'b0;
// xfer_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state)
READY:
begin
if(rdp_rdy_i && cmd_rd && ~mcb_cmd_full) //rdp_rdy_i comes from read_data path
begin
next_state = READ;
push_cmd = 1'b1;
// xfer_cmd = 1'b0;
rdp_valid = 1'b1;
cmd_rdy = 1'b1;
end
else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full)
begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
end
else if ( cmd_others && cmd_fifo_rdy)
begin
next_state = REFRESH_ST;
push_cmd = 1'b1;
// xfer_cmd = 1'b0;
cmd_rdy = 1'b0;
end
else
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
end
end
REFRESH_ST : begin
if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )
begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
wdp_valid = 1'b0;
// xfer_cmd = 1'b1;
// tstpointA = 4'b0101;
end
else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
begin
next_state = WRITE;
push_cmd = 1'b1;
// xfer_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
// tstpointA = 4'b0110;
end
else if (cmd_fifo_rdy && cmd_others)
begin
push_cmd = 1'b1;
// xfer_cmd = 1'b1;
end
else if (!cmd_fifo_rdy)
begin
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else
next_state = READ;
cmd_rdy = 1'b0;
end
READ: begin
if (rdcmd_in_progress )
begin
next_state = READ;
push_cmd = 1'b0;
rdp_valid = 1'b0;
wdp_valid = 1'b0;
tstpointA = 4'b0101;
end
else if (!rdp_rdy_i )
begin
next_state = READ;
push_cmd = 1'b0;
tstpointA = 4'b0111;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead)
begin
// next_state = READY;//CMD_WAIT;
next_state = CMD_WAIT;
tstpointA = 4'b1001;
end
else if (goahead)
next_state = READY;
cmd_rdy = 1'b0;
end
WRITE: begin // for write, always wait until the last_word_wr
if ( wr_in_progress || wrcmd_in_progress || push_cmd_r )
begin
next_state = WRITE;
tstpointA = 4'b0001;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
push_cmd = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i && goahead)
begin
// next_state = READY;// CMD_WAIT;
next_state = CMD_WAIT;
push_cmd = 1'b0;
tstpointA = 4'b0011;
end
else if (goahead) begin
next_state = READY;
tstpointA = 4'b0100;
end
cmd_rdy = 1'b0;
end
CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress)
begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
tstpointA = 4'b1010;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
rdp_valid = 1'b0;
tstpointA = 4'b1011;
end
else if (cmd_fifo_rdy && cmd_wr && goahead && (wait_done || cmd_wr_pending_r1))
begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
tstpointA = 4'b1100;
end
else
begin
next_state = CMD_WAIT;
tstpointA = 4'b1110;
cmd_rdy = 1'b0;
end
default:
begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
end
endcase
end
//synthesis translate_off
always @(current_state) begin
casex (current_state)
5'b00001 : begin flow_command = "READY"; end
5'b00010 : begin flow_command = "READ" ; end
5'b00100 : begin flow_command = "WRITE"; end
5'b01000 : begin flow_command = "CMD_WAIT" ; end
5'b10000 : begin flow_command = "REFRESH_ST"; end
endcase
end
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_M_V
`define SKY130_FD_SC_LP__OR3B_M_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_m (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_m (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_M_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:40:40 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[12:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[12:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[12:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [12:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [12:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [12:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [12:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : timer.v
// Description : Picoblaze Timer Module
// Author : Philip Tracton
// Created On : Thu May 28 22:54:35 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 28 22:54:35 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module timer (/*AUTOARG*/
// Outputs
timer_interrupt,
// Inputs
clk, timer_count, timer_enable, timer_interrupt_clear
) ;
input clk;
input [31:0] timer_count;
input timer_enable;
input timer_interrupt_clear;
output timer_interrupt;
//
// Registers
//
reg [31:0] count = 32'h0000_0000;
reg timer_interrupt = 1'b0;
reg interrupt = 1'b0;
//
// Wires
//
assign timer_expired = (count >= timer_count);
always @(posedge clk)
if (timer_enable && !timer_expired) begin
count <= count + 1;
end else begin
count <= 32'h0000_0000;
end
//
// Interrupt
//
always @(posedge clk)
if (timer_enable & !timer_interrupt_clear) begin
interrupt <= timer_expired;
end else begin
interrupt <= 1'b0;
end
endmodule // timer
|
//////////////////////////////////////////////////////////////////
// //
// Top Level testbench //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the system, ddr3 memory model and tb_uart //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`define AMBER_A25_CORE
`define AMBER_LOAD_MAIN_MEM
`timescale 1 ps / 1 ps
`include "system_config_defines.v"
`include "global_defines.v"
module tb();
`include "debug_functions.v"
`include "system_functions.v"
`include "memory_configuration.v"
reg sysrst;
`ifdef XILINX_VIRTEX6_FPGA
reg clk_533mhz;
`endif
reg clk_200mhz;
reg clk_25mhz;
reg [31:0] clk_count = 'd0;
integer log_file;
`ifdef AMBER_LOAD_MAIN_MEM
integer main_mem_file;
reg [31:0] main_mem_file_address;
reg [31:0] main_mem_file_data;
reg [127:0] main_mem_file_data_128;
reg [31:0] ecc_mem_file_ecc_32;
integer main_mem_line_count;
reg [22:0] mm_ddr3_addr;
`endif
integer boot_mem_file;
reg [31:0] boot_mem_file_address;
reg [31:0] boot_mem_file_data;
reg [127:0] boot_mem_file_data_128;
integer boot_mem_line_count;
integer fgets_return;
reg [120*8-1:0] line;
reg [120*8-1:0] aligned_line;
integer timeout = 0;
wire [12:0] ddr3_addr;
wire [2:0] ddr3_ba;
wire ddr3_ck_p;
wire ddr3_ck_n;
wire [15:0] ddr3_dq;
wire [1:0] ddr3_dqs_p;
wire [1:0] ddr3_dqs_n;
wire [1:0] ddr3_dm;
wire ddr3_ras_n;
wire ddr3_cas_n;
wire ddr3_we_n;
wire ddr3_cke;
wire ddr3_odt;
wire ddr3_reset_n;
`ifdef XILINX_SPARTAN6_FPGA
wire mcb3_rzq;
wire mcb3_zio;
`endif
tri1 md; // bi-directional phy config data
wire mdc; // phy config clock
wire uart0_cts;
wire uart0_rx;
wire uart0_rts;
wire uart0_tx;
wire [3:0] eth_mtxd;
wire eth_mtxdv;
wire eth_mtxerr;
wire [3:0] eth_mrxd;
wire eth_mrxdv;
// ======================================
// Instantiate FPGA
// ======================================
system u_system (
// Clocks and resets
.brd_rst ( sysrst ),
.brd_clk_p ( clk_200mhz ),
.brd_clk_n ( ~clk_200mhz ),
`ifdef XILINX_VIRTEX6_FPGA
.sys_clk_p ( clk_533mhz ),
.sys_clk_n ( ~clk_533mhz ),
`endif
// UART 0 signals
.o_uart0_cts ( uart0_cts ),
.o_uart0_rx ( uart0_rx ),
.i_uart0_rts ( uart0_rts ),
.i_uart0_tx ( uart0_tx ),
// DDR3 signals
.ddr3_dq ( ddr3_dq ),
.ddr3_addr ( ddr3_addr ),
.ddr3_ba ( ddr3_ba ),
.ddr3_ras_n ( ddr3_ras_n ),
.ddr3_cas_n ( ddr3_cas_n ),
.ddr3_we_n ( ddr3_we_n ),
.ddr3_odt ( ddr3_odt ),
.ddr3_reset_n ( ddr3_reset_n ),
.ddr3_cke ( ddr3_cke ),
.ddr3_dm ( ddr3_dm ),
.ddr3_dqs_p ( ddr3_dqs_p ),
.ddr3_dqs_n ( ddr3_dqs_n ),
.ddr3_ck_p ( ddr3_ck_p ),
.ddr3_ck_n ( ddr3_ck_n ),
`ifdef XILINX_VIRTEX6_FPGA
.ddr3_cs_n ( ddr3_cs_n ),
`endif
`ifdef XILINX_SPARTAN6_FPGA
.mcb3_rzq ( mcb3_rzq ),
.mcb3_zio ( mcb3_zio ),
`endif
// Ethernet MII signals
.mtx_clk_pad_i ( clk_25mhz ),
.mtxd_pad_o ( eth_mrxd ),
.mtxen_pad_o ( eth_mrxdv ),
.mtxerr_pad_o ( ),
.mrx_clk_pad_i ( clk_25mhz ),
.mrxd_pad_i ( eth_mtxd ),
.mrxdv_pad_i ( eth_mtxdv ),
.mrxerr_pad_i ( eth_mtxerr ),
.mcoll_pad_i ( 1'd0 ),
.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY
.phy_reset_n ( ),
// Ethernet Management Data signals
.md_pad_io ( md ),
.mdc_pad_o ( mdc ),
// LEDs
.led ( )
);
// ======================================
// Instantiate Ethernet Test Device
// ======================================
eth_test u_eth_test(
.md_io ( md ),
.mdc_i ( mdc ),
.mtx_clk_i ( clk_25mhz ),
.mtxd_o ( eth_mtxd ),
.mtxdv_o ( eth_mtxdv ),
.mtxerr_o ( eth_mtxerr ),
.mrxd_i ( eth_mrxd ),
.mrxdv_i ( eth_mrxdv )
);
// ======================================
// Instantiate DDR3 Memory Model
// ======================================
`ifdef XILINX_FPGA
ddr3_model_c3 #(
.DEBUG ( 0 ) // Set to 1 to enable debug messages
)
u_ddr3_model (
.ck ( ddr3_ck_p ),
.ck_n ( ddr3_ck_n ),
.cke ( ddr3_cke ),
`ifdef XILINX_VIRTEX6_FPGA
.cs_n ( ddr3_cs_n ),
`else
.cs_n ( 1'b0 ),
`endif
.ras_n ( ddr3_ras_n ),
.cas_n ( ddr3_cas_n ),
.we_n ( ddr3_we_n ),
.dm_tdqs ( ddr3_dm ),
.ba ( ddr3_ba ),
.addr ( {1'd0, ddr3_addr} ),
.dq ( ddr3_dq ),
.dqs ( ddr3_dqs_p ),
.dqs_n ( ddr3_dqs_n ),
.tdqs_n ( ),
.odt ( ddr3_odt ),
.rst_n ( ddr3_reset_n )
);
`endif
// ======================================
// Instantiate Testbench UART
// ======================================
tb_uart u_tb_uart (
.i_uart_cts_n ( uart0_cts ), // Clear To Send
.i_uart_rxd ( uart0_rx ),
.o_uart_rts_n ( uart0_rts ), // Request to Send
.o_uart_txd ( uart0_tx )
);
// ======================================
// Global module for xilinx hardware simulations
// ======================================
`ifdef XILINX_FPGA
`define GLBL
glbl glbl();
`endif
// ======================================
// Clock and Reset
// ======================================
// 200 MHz clock
initial
begin
clk_200mhz = 1'd0;
// Time unit is pico-seconds
forever #2500 clk_200mhz = ~clk_200mhz;
end
`ifdef XILINX_VIRTEX6_FPGA
// 400 MHz clock
initial
begin
clk_533mhz = 1'd0;
// Time unit is pico-seconds
forever #938 clk_533mhz = ~clk_533mhz;
end
`endif
// 25 MHz clock
initial
begin
clk_25mhz = 1'd0;
forever #20000 clk_25mhz = ~clk_25mhz;
end
initial
begin
sysrst = 1'd1;
#40000
sysrst = 1'd0;
end
// ======================================
// Counter of system clock ticks
// ======================================
always @ ( posedge `U_SYSTEM.sys_clk )
clk_count <= clk_count + 1'd1;
// ======================================
// Initialize Boot Memory
// ======================================
initial
begin
`ifndef XILINX_FPGA
$display("Load boot memory from %s", `BOOT_MEM_FILE);
boot_mem_line_count = 0;
boot_mem_file = $fopen(`BOOT_MEM_FILE, "r");
if (boot_mem_file == 0)
begin
`TB_ERROR_MESSAGE
$display("ERROR: Can't open input file %s", `BOOT_MEM_FILE);
end
if (boot_mem_file != 0)
begin
fgets_return = 1;
while (fgets_return != 0)
begin
fgets_return = $fgets(line, boot_mem_file);
boot_mem_line_count = boot_mem_line_count + 1;
aligned_line = align_line(line);
// if the line does not start with a comment
if (aligned_line[120*8-1:118*8] != 16'h2f2f)
begin
// check that line doesnt start with a '@' or a blank
if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
begin
$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
`BOOT_MEM_FILE, boot_mem_line_count, aligned_line[118*8-1:117*8]);
`TB_ERROR_MESSAGE
end
if (aligned_line[120*8-1:119*8] != 8'h00)
begin
boot_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
`ifdef AMBER_A25_CORE
boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]];
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]] =
insert_32_into_128 ( boot_mem_file_address[3:2],
boot_mem_file_data_128,
boot_mem_file_data );
`else
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:2]] = boot_mem_file_data;
`endif
`ifdef AMBER_LOAD_MEM_DEBUG
$display ("Load Boot Mem: PAddr: 0x%08x, Data 0x%08x",
boot_mem_file_address, boot_mem_file_data);
`endif
end
end
end
$display("Read in %1d lines", boot_mem_line_count);
end
`endif
// Grab the test name from memory
timeout = `AMBER_TIMEOUT ;
$display("log file %s, timeout %0d, test name %0s ", `AMBER_LOG_FILE, timeout, `AMBER_TEST_NAME );
log_file = $fopen(`AMBER_LOG_FILE, "a");
end
// ======================================
// Initialize Main Memory
// ======================================
`ifdef AMBER_LOAD_MAIN_MEM
initial
begin
$display("Load main memory from %s", `MAIN_MEM_FILE);
`ifdef XILINX_FPGA
// Wait for DDR3 initialization to complete
$display("Wait for DDR3 initialization to complete before loading main memory");
#70000000
$display("Done waiting at %d ticks", `U_TB.clk_count);
`endif
main_mem_file = $fopen(`MAIN_MEM_FILE, "r");
// Read RAM File
main_mem_line_count = 0;
if (main_mem_file == 0)
begin
$display("ERROR: Can't open input file %s", `MAIN_MEM_FILE);
`TB_ERROR_MESSAGE
end
if (main_mem_file != 0)
begin
fgets_return = 1;
while (fgets_return != 0)
begin
fgets_return = $fgets(line, main_mem_file);
main_mem_line_count = main_mem_line_count + 1;
aligned_line = align_line(line);
// if the line does not start with a comment
if (aligned_line[120*8-1:118*8] != 16'h2f2f)
begin
// check that line doesnt start with a '@' or a blank
if (aligned_line[120*8-1:119*8] != 8'h40 && aligned_line[120*8-1:119*8] != 8'h00)
begin
$display("Format ERROR in input file %s, line %1d. Line must start with a @, not %08x",
`MAIN_MEM_FILE, main_mem_line_count, aligned_line[118*8-1:117*8]);
`TB_ERROR_MESSAGE
end
if (aligned_line[120*8-1:119*8] != 8'h00)
begin
main_mem_file_address = hex_chars_to_32bits (aligned_line[119*8-1:111*8]);
main_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
`ifdef XILINX_FPGA
mm_ddr3_addr = {main_mem_file_address[13:11], main_mem_file_address[26:14], main_mem_file_address[10:4]};
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
tb.u_ddr3_model.memory [mm_ddr3_addr] =
insert_32_into_128 ( main_mem_file_address[3:2],
main_mem_file_data_128,
main_mem_file_data );
`ifdef AMBER_LOAD_MEM_DEBUG
main_mem_file_data_128 = tb.u_ddr3_model.memory [mm_ddr3_addr];
$display ("Load DDR3: PAddr: 0x%08x, DDR3 Addr 0x%08h, Data 0x%032x",
main_mem_file_address, mm_ddr3_addr, main_mem_file_data_128);
`endif
`else
// Fast simulation model of main memory
// U_RAM - Can either point to simple or Xilinx DDR3 model.
// Set in hierarchy_defines.v
main_mem_file_data_128 = `U_RAM [main_mem_file_address[31:4]];
`U_RAM [main_mem_file_address[31:4]] =
insert_32_into_128 ( main_mem_file_address[3:2],
main_mem_file_data_128,
main_mem_file_data );
//`U_ECC_MEM [main_mem_file_address[31:4]] = 0;
ecc_mem_file_ecc_32 = `U_ECC_MEM [main_mem_file_address[31:4]];
`U_ECC_MEM [main_mem_file_address[31:4]] =
insert_8_into_32 (main_mem_file_address[3:2],
ecc_mem_file_ecc_32,
ecc40_32(main_mem_file_data));
`ifdef AMBER_LOAD_MEM_DEBUG
if( `U_RAM[main_mem_file_address[31:4]][127] !== 1'bx ) begin
$display ("Load RAM: PAddr: 0x%08x, Data 0x%08x",
main_mem_file_address, `U_RAM [main_mem_file_address[31:4]]);
$display ("Load ECC: PAddr: 0x%08x, Data 0x%08x",
main_mem_file_address[31:4], `U_ECC_MEM [main_mem_file_address[31:4]]);
end
`endif
`endif
end
end
end
$display("Read in %1d lines", main_mem_line_count);
end
end
`endif
dumpvcd u_dumpvcd();
// ======================================
// Terminate Test
// ======================================
`ifdef AMBER_A25_CORE
`include "a25_localparams.v"
`include "a25_functions.v"
`else
`include "a23_localparams.v"
`include "a23_functions.v"
`endif
reg testfail;
wire test_status_set;
wire [31:0] test_status_reg;
/* Add system status */
wire system_status_set;
initial
begin
testfail = 1'd0;
end
assign test_status_set = `U_TEST_MODULE.test_status_set;
assign test_status_reg = `U_TEST_MODULE.test_status_reg;
assign system_status_set = `U_ARBITER.status_set;
always @*
begin
if ( system_status_set || test_status_set || testfail )
begin
if ( test_status_reg == 32'd17 && !testfail )
begin
display_registers;
$display("++++++++++++++++++++");
$write("Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
$display("++++++++++++++++++++");
$fwrite(`U_TB.log_file,"Passed %s %0d ticks\n", `AMBER_TEST_NAME, `U_TB.clk_count);
$finish;
end
else
begin
display_registers;
if ( testfail )
begin
$display("++++++++++++++++++++");
$write("Failed %s\n", `AMBER_TEST_NAME);
$display("++++++++++++++++++++");
$fwrite(`U_TB.log_file,"Failed %s\n", `AMBER_TEST_NAME);
$finish;
end
else
if( system_status_set )
begin
$display("++++++++++++++++++++");
$write("Failed %s - EDC has detected a memory error\n", `AMBER_TEST_NAME);
$display("++++++++++++++++++++");
$fwrite(`U_TB.log_file,"Failed %s - EDC has detected a memory error\n", `AMBER_TEST_NAME);
$finish;
end
else
begin
$display("++++++++++++++++++++");
if (test_status_reg >= 32'h8000)
$write("Failed %s - with error 0x%08x\n", `AMBER_TEST_NAME, test_status_reg);
else
$write("Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
$display("++++++++++++++++++++");
if (test_status_reg >= 32'h8000)
$fwrite(`U_TB.log_file,"Failed %s - with error 0x%08h\n", `AMBER_TEST_NAME, test_status_reg);
else
$fwrite(`U_TB.log_file,"Failed %s - with error on line %1d\n", `AMBER_TEST_NAME, test_status_reg);
$finish;
end
end
end
end
// ======================================
// Timeout
// ======================================
always @ ( posedge `U_SYSTEM.sys_clk )
if ( timeout != 0 )
if (`U_TB.clk_count >= timeout)
begin
`TB_ERROR_MESSAGE
$display("Timeout Error. Edit $AMBER_BASE/hw/tests/timeouts.txt to change the timeout");
end
// ======================================
// Tasks
// ======================================
task display_registers;
begin
$display("");
$display("----------------------------------------------------------------------------");
$display("Amber Core");
case (`U_EXECUTE.status_bits_mode)
FIRQ: $display(" User > FIRQ IRQ SVC");
IRQ: $display(" User FIRQ > IRQ SVC");
SVC: $display(" User FIRQ IRQ > SVC");
default: $display(" > User FIRQ IRQ SVC");
endcase
$display("r0 0x%08x", `U_REGISTER_BANK.r0);
$display("r1 0x%08x", `U_REGISTER_BANK.r1);
$display("r2 0x%08x", `U_REGISTER_BANK.r2);
$display("r3 0x%08x", `U_REGISTER_BANK.r3);
$display("r4 0x%08x", `U_REGISTER_BANK.r4);
$display("r5 0x%08x", `U_REGISTER_BANK.r5);
$display("r6 0x%08x", `U_REGISTER_BANK.r6);
$display("r7 0x%08x", `U_REGISTER_BANK.r7);
$display("r8 0x%08x 0x%08x ", `U_REGISTER_BANK.r8, `U_REGISTER_BANK.r8_firq);
$display("r9 0x%08x 0x%08x ", `U_REGISTER_BANK.r9, `U_REGISTER_BANK.r9_firq);
$display("r10 0x%08x 0x%08x ", `U_REGISTER_BANK.r10, `U_REGISTER_BANK.r10_firq);
$display("r11 0x%08x 0x%08x ", `U_REGISTER_BANK.r11, `U_REGISTER_BANK.r11_firq);
$display("r12 0x%08x 0x%08x ", `U_REGISTER_BANK.r12, `U_REGISTER_BANK.r12_firq);
$display("r13 0x%08x 0x%08x 0x%08x 0x%08x",
`U_REGISTER_BANK.r13,
`U_REGISTER_BANK.r13_firq,
`U_REGISTER_BANK.r13_irq,
`U_REGISTER_BANK.r13_svc);
$display("r14 (lr) 0x%08x 0x%08x 0x%08x 0x%08x",
`U_REGISTER_BANK.r14,
`U_REGISTER_BANK.r14_firq,
`U_REGISTER_BANK.r14_irq,
`U_REGISTER_BANK.r14_svc);
$display("r15 (pc) 0x%08x", {6'd0,`U_REGISTER_BANK.r15,2'd0});
$display("");
$display("Status Bits: N=%d, Z=%d, C=%d, V=%d, IRQ Mask %d, FIRQ Mask %d, Mode = %s",
`U_EXECUTE.status_bits_flags[3],
`U_EXECUTE.status_bits_flags[2],
`U_EXECUTE.status_bits_flags[1],
`U_EXECUTE.status_bits_flags[0],
`U_EXECUTE.status_bits_irq_mask,
`U_EXECUTE.status_bits_firq_mask,
mode_name (`U_EXECUTE.status_bits_mode) );
$display("----------------------------------------------------------------------------");
$display("");
end
endtask
// ======================================
// Functions
// ======================================
function [127:0] insert_32_into_128;
input [1:0] pos;
input [127:0] word128;
input [31:0] word32;
begin
case (pos)
2'd0: insert_32_into_128 = {word128[127:32], word32};
2'd1: insert_32_into_128 = {word128[127:64], word32, word128[31:0]};
2'd2: insert_32_into_128 = {word128[127:96], word32, word128[63:0]};
2'd3: insert_32_into_128 = {word32, word128[95:0]};
endcase
end
endfunction
function [31:0] insert_8_into_32;
input [1:0] pos;
input [31:0] word32;
input [7:0] word8;
begin
case (pos)
2'd0: insert_8_into_32 = {word32[31:8], word8};
2'd1: insert_8_into_32 = {word32[31:16], word8, word32[7:0]};
2'd2: insert_8_into_32 = {word32[31:24], word8, word32[15:0]};
2'd3: insert_8_into_32 = {word8, word32[23:0]};
endcase
end
endfunction
function [7:0] ecc40_32;
input [31:0] data;
begin
ecc40_32[7] = ^ (data & 32'b10101010_10101010_11000000_11000000);
ecc40_32[6] = ^ (data & 32'b01010101_01010101_00110000_00110000);
ecc40_32[5] = ^ (data & 32'b11111111_00000000_00001100_00001100);
ecc40_32[4] = ^ (data & 32'b00000000_11111111_00000011_00000011);
ecc40_32[3] = ^ (data & 32'b11000000_11000000_11111111_00000000);
ecc40_32[2] = ^ (data & 32'b00110000_00110000_00000000_11111111);
ecc40_32[1] = ^ (data & 32'b00001100_00001100_10101010_10101010);
ecc40_32[0] = ^ (data & 32'b00000011_00000011_01010101_01010101);
end
endfunction
endmodule
|
// -*- Mode: Verilog -*-
// Filename : uart_echo_pb.v
// Description : UART Echo with Picoblaze and UART that came with it
// Author : Philip Tracton
// Created On : Wed May 27 17:15:49 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed May 27 17:15:49 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module uart_echo_pb (/*AUTOARG*/
// Outputs
TX,
// Inputs
CLK_IN, RESET_IN, RX
) ;
input CLK_IN;
input RESET_IN;
input RX;
output TX;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CLK_OUT; // From syscon of system_controller.v
wire RESET_OUT; // From syscon of system_controller.v
// End of automatics
/*AUTOREG*/
wire TX;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire [7:0] uart_data_out;
//
// System Controller
//
system_controller syscon(/*AUTOINST*/
// Outputs
.CLK_OUT (CLK_OUT),
.RESET_OUT (RESET_OUT),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN));
//
// Picoblaze CPU
//
cpu Picoblaze(
// Outputs
.port_id (port_id[7:0]),
.out_port (out_port[7:0]),
.write_strobe (write_strobe),
.read_strobe (read_strobe),
.interrupt_ack (interrupt_ack),
// Inputs
.clk (CLK_OUT),
.in_port (in_port[7:0]),
.interrupt (interrupt),
.kcpsm6_sleep (kcpsm6_sleep),
.cpu_reset (RESET_OUT));
assign in_port = uart_data_out;
assign interrupt = uart_irq;
assign kcpsm6_sleep = 0;
//
// UART
//
pb_uart uart(
// Outputs
.TX(TX),
.data_out(uart_data_out),
.interrupt(uart_irq),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.RX(RX),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe)
) ;
endmodule // uart_echo_pb
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: msu_databuf.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module msu_databuf (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [7:0] data;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 14,
altsyncram_component.widthad_b = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 14 0 INPUT NODEFVAL "rdaddress[13..0]"
// Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
// Retrieval info: CONNECT: @address_b 0 0 14 0 rdaddress 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL msu_databuf_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module xor_48_salt(
input [47:0] X,
input [59:0] Y,
output reg [47:0] Dout,
input CLK
);
wire [47:0] Xtmp;
always @(posedge CLK)
begin
Dout <= Xtmp ^ Y[47:0];
end
assign Xtmp = {(X[47:36] & (~Y[59:48])) | (Y[59:48] & X[23:12]), X[35:24], (X[23:12] & (~Y[59:48])) | (Y[59:48] & X[47:36]), X[11:0]};
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Wed Apr 30 22:30:36 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_adc/clk_adc_funcsim.v
// Design : clk_adc
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_adc
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire locked;
clk_adcclk_adc_clk_wiz U0
(.clk_250Mhz(clk_250Mhz),
.clk_in1_n(clk_in1_n),
.clk_in1_p(clk_in1_p),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_adc_clk_wiz" *)
module clk_adcclk_adc_clk_wiz
(clk_in1_p,
clk_in1_n,
clk_250Mhz,
locked);
input clk_in1_p;
input clk_in1_n;
output clk_250Mhz;
output locked;
wire clk_250Mhz;
wire clk_250Mhz_clk_adc;
wire clk_in1_clk_adc;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_n;
(* DIFF_TERM=0 *) (* IBUF_LOW_PWR *) wire clk_in1_p;
wire clkfbout_buf_clk_adc;
wire clkfbout_clk_adc;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_adc),
.O(clkfbout_buf_clk_adc));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUFDS #(
.DQS_BIAS("FALSE"),
.IOSTANDARD("DEFAULT"))
clkin1_ibufgds
(.I(clk_in1_p),
.IB(clk_in1_n),
.O(clk_in1_clk_adc));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_250Mhz_clk_adc),
.O(clk_250Mhz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(4.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(4.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(236.250000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_adc),
.CLKFBOUT(clkfbout_clk_adc),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_adc),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_250Mhz_clk_adc),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire buf_Q ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_FUNCTIONAL_PP_V
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
//*****************************************************************************
// Filename : axi4s_video_mst.v
// Description : This module is a Master-Transmitter model based on
// Video over AXI4-Stream Specification v1.5 &
// Video and Imaging IP Standard Data File Format v1.2 .
//
// Available user tasks :
// start() -> enable module & start transmission of video data
// stop() -> disable module & stop transmission of video data
// pause() -> pause/disable module w/o losing active settings
// resume() -> resume/enable module to where it paused
// throttle_on() -> enable data throttling using tvalid
// throttle_off() -> disable data throttling
// debug_on() -> turn on debug displays
// debug_off() -> turn off debug displays
// use_file(<filepath>) -> specify stimuli filepath.
// set_throttle_valid(num) -> specify width of tvalid high when throttle is on
// set_throttle_wait(num) -> specify width of tvalid low when throttle is on
// set_eol_phase(N) -> when N=0, normal EOL timing
// -> when N>0, late EOL generation
// -> when N<0, early EOL generation
// set_sof_phase(N) -> when N=0, normal SOF timing
// -> when N>0, late SOF generation
// -> when N<0, <NOT SUPPORTED>
// poll_line_num(N) -> when N=0, return current line number
// -> when N>0, if N==current line number, return 1
// -> if N!=current line number, return 0
// poll_frame_num(N) -> when N=0, return current frame number
// -> when N>0, if N==current frame number, return 1
// -> if N!=current frame number, return 0
//
//-----------------------------------------------------------------------------
// Ver Date Modified by Modification
//-----------------------------------------------------------------------------
// 1.0 27/10/2011 reinald Initial code.
// 1.1 06/12/2011 reinald Added pause() & resume() tasks.
// Added poll_line_num() & poll_frame_num().
// 1.2 14/12/2011 reinald Added additional port "aclken" that masks
// aclk and suspends module operation.
// 1.3 21/12/2011 reinald Added debug displays in pause() & resume().
// Modified implementation of SOF & EOL
// generation to pad dummy pixel data on
// late EOL/SOF and adjust correct pixel data
// for early EOL.
// Modified use_file() argument.
// 1.4 03/01/2012 reinald added warning messages when total received
// pixels do not match header details.
//
// 1.5 30/01/2012 reinald Fixed bug on YUV422 format chroma swap.
//
// 1.6 14/05/2012 reinald Added configurable drive delay for all
// output ports.
// Fixed tvalid sampling issue due to falling
// edge. Sampling always set at clock rise.
// Driving edge configurable by parameter.
// Modified for iSim & ncsim support.
//
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module axi4s_video_mst
#(
parameter module_id = "AXI4-S Video Master 1",
parameter drive_edge = "rise", //only "rise" & "fall" are valid
parameter datawidth = 32, //must be multiple of 8
parameter tuserwidth = 1,
parameter tdestwidth = 1,
parameter tid_width = 1,
parameter drive_dly = 0 // drive delay for all output ports
)
(
input aclk,
input aclken,
input aresetn,
input tready,
output reg [datawidth-1: 0] tdata,
output reg tvalid,
output reg eol,
output reg [tuserwidth-1: 0] sof,
output reg [tdestwidth-1: 0] tdest,
output reg [tid_width-1: 0] tid,
output reg [(datawidth/8)-1: 0] tstrb,
output reg [(datawidth/8)-1: 0] tkeep,
output reg EOF
);
reg [datawidth-1: 0] tdata_d0;
reg tvalid_d0;
reg eol_d0;
reg [tuserwidth-1: 0] sof_d0;
reg [tdestwidth-1: 0] tdest_d0;
reg [tid_width-1: 0] tid_d0;
reg [(datawidth/8)-1: 0] tstrb_d0;
reg [(datawidth/8)-1: 0] tkeep_d0;
always @(tdata_d0) #(drive_dly) tdata = tdata_d0;
always @(tvalid_d0) #(drive_dly) tvalid = tvalid_d0;
always @(eol_d0) #(drive_dly) eol = eol_d0;
always @(sof_d0) #(drive_dly) sof = sof_d0;
always @(tdest_d0) #(drive_dly) tdest = tdest_d0;
always @(tid_d0) #(drive_dly) tid = tid_d0;
always @(tstrb_d0) #(drive_dly) tstrb = tstrb_d0;
always @(tkeep_d0) #(drive_dly) tkeep = tkeep_d0;
// module control
reg enable = 0;
reg debug = 0;
reg throttle = 0;
reg [31:0] throttlewidth = 10;
reg [31:0] throttlewait = 5;
reg [50*8:0] file_name = "./stimuli/stimuli_1.txt";
// container for file read data
reg [63:0] file_data;
// containers for pixel components
integer compA;
integer compB;
integer compC;
integer compD;
// containers for header data
integer header_mode;
integer header_frames;
integer header_field;
integer header_rows;
integer header_cols;
integer header_bpp;
// variables for file handle operations
integer file_handler;
integer file_eof;
integer isim_eof;
// variables for flow control
integer timeout_ctr;
integer timeout;
integer pixel_count =0;
integer line_count =0;
integer frame_count =0;
integer eol_count =0;
integer sof_count =0;
reg eol_on =0;
reg sof_on =0;
integer throttle_data_cnt;
integer throttle_wait_cnt;
integer sof_phase = 0;
integer eol_phase = 0;
reg fetch_new_data;
reg pending_tx;
reg tvalid_state;
integer remove_count=0;
reg ramp_gen = 0;
integer ramp_rows = 128;
integer ramp_cols = 128;
integer ramp_frames = 1;
reg skip_sof = 0;
//events
event aclk_rise;
event aclk_fall;
event aresetn_rise;
event aresetn_fall;
always @(posedge aclk) if(aclken) -> aclk_rise;
always @(negedge aclk) if(aclken) -> aclk_fall;
always @(posedge aresetn) -> aresetn_rise;
always @(negedge aresetn) -> aresetn_fall;
initial
begin
if((drive_edge != "rise")&&(drive_edge != "fall"))
begin
$display("@%10t : [%s] \"%s\" is not a valid drive_edge parameter value ...", $time, module_id, drive_edge);
$finish;
end
init;
end
//=============//
// USER TASKS //
//=============//
task init;
begin
tdata_d0 = 0;
tvalid_d0 = 0;
sof_d0 = 0;
eol_d0 = 0;
tstrb_d0 = 1;
tkeep_d0 = 1;
tdest_d0 = 0;
tid_d0 = 0;
EOF = 0;
throttle_data_cnt = throttlewidth;
throttle_wait_cnt = throttlewait;
file_data = 0;
enable = 0;
debug = 0;
throttle = 0;
eol_phase = 0;
sof_phase = 0;
timeout_ctr = 0;
timeout = 10000;
end
endtask
task use_file;
input [50*8:0] filenum;
begin
ramp_gen = 0;
file_name = filenum;
$display("@%10t : [%s] attaching %s ...", $time, module_id, file_name);
end
endtask
task is_ramp_gen;
input integer ramp_row_v;
input integer ramp_col_v;
input integer ramp_frame_v;
begin
ramp_rows = ramp_row_v;
ramp_cols = ramp_col_v;
ramp_frames = ramp_frame_v;
ramp_gen = 1;
end
endtask
task skip_sof_on;
begin
skip_sof =1;
end
endtask
task skip_sof_off;
begin
skip_sof =0;
end
endtask
task start;
begin
EOF = 0;
tvalid_d0 = 0;
pixel_count = 0;
line_count = 0;
frame_count = 0;
eol_count = 0;
sof_count = 0;
eol_on = 0;
sof_on = 0;
fetch_new_data = 1;
pending_tx = 0;
isim_eof = 0;
timeout_ctr = 0;
if(!ramp_gen)
begin
file_handler = $fopen(file_name, "r");
if (file_handler == 0)
begin
$display("ERROR : %s cannot be opened.... Simulation Stopped", file_name);
$finish;
end
//GET THE MODE
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_mode = file_data;
//GET THE NUMBER OF FRAMES
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_frames = file_data;
//GET THE FIELD THAT COMES FIRST
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_field = file_data;
//GET THE NUMBER OF ROWS
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_rows = file_data;
//GET THE NUMBER OF COLUMNS
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_cols = file_data;
//GET THE NUMBER OF BITS
file_eof = $fscanf(file_handler,"%s",file_data);
file_eof = $fscanf(file_handler,"%d",file_data);
header_bpp = file_data;
end
else
begin
header_mode = 0;
header_frames = ramp_frames;
header_field = 0;
header_rows = ramp_rows;
header_cols = ramp_cols;
end
enable = 1;
$display("@%10t : [%s] STARTED", $time, module_id);
end
endtask
task stop;
begin
if(!ramp_gen)
begin
if(pixel_count > 0)
begin
$fclose(file_handler);
pixel_count = 0;
end
end
enable = 0;
$display("@%10t : [%s] STOPPED", $time, module_id);
EOF = 0;
end
endtask
task pause;
begin
tvalid_state = tvalid_d0;
enable = 0;
tvalid_d0 = 0;
tvalid = 0;
if(debug) $display("@%10t : [%s] PAUSED TX", $time, module_id);
end
endtask
task resume;
begin
tvalid = tvalid_state;
tvalid_d0 = tvalid_state;
enable = 1;
if(debug) $display("@%10t : [%s] RESUME TX", $time, module_id);
end
endtask
function integer poll_line_num;
input [31:0] a;
begin
if(a==0) poll_line_num = (((pixel_count)/header_cols) + 1);
else if(a == ((pixel_count)/header_cols) + 1) poll_line_num = 1;
else poll_line_num = 0;
end
endfunction
function integer poll_frame_num;
input [31:0] a;
begin
if(a==0) poll_frame_num = (((pixel_count)/(header_cols*header_rows)) + 1);
else if(a == ((pixel_count)/(header_cols*header_rows) + 1)) poll_frame_num = 1;
else poll_frame_num = 0;
end
endfunction
task debug_on;
begin
$display("@%10t : [%s] Debug Messages ON", $time, module_id);
debug = 1;
end
endtask
task debug_off;
begin
$display("@%10t : [%s] Debug Messages OFF", $time, module_id);
debug = 0;
end
endtask
task throttle_on;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Turned ON", $time, module_id);
end
throttle = 1;
throttle_data_cnt = throttlewidth;
throttle_wait_cnt = throttlewait;
end
endtask
task throttle_off;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Turned OFF", $time, module_id);
end
throttle = 0;
end
endtask
task set_throttle_valid;
input [31:0] width;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Width set to %d", $time, module_id, width);
end
throttlewidth = width;
throttle_data_cnt = width;
end
endtask
task set_throttle_wait;
input [31:0] width;
begin
if(debug)
begin
$display("@%10t : [%s] Data Throttle Wait set to %d", $time, module_id, width);
end
throttlewait = width;
throttle_wait_cnt = width;
end
endtask
task set_sof_phase;
input integer switch;
begin
if(switch < 0)
begin
sof_phase = 0;
$display("@%10t : [%s] (%d) Negative SOF Phase not supported. SOF Phase will be set to 0", $time, module_id, switch);
end
else
sof_phase = switch;
if(debug)
begin
$display("@%10t : [%s] SOF Phase set to %d", $time, module_id, sof_phase);
end
end
endtask
task set_eol_phase;
input integer switch;
begin
if(debug)
begin
$display("@%10t : [%s] EOL Phase set to %d", $time, module_id, switch);
end
eol_phase = switch;
end
endtask
//=================//
// INTERNAL TASKS //
//=================//
task drive_output;
integer cntr;
begin
if(drive_edge == "fall") @aclk_fall;
tdata_d0 <= file_data;
tvalid_d0 <= 1;
// SOF GENERATION
if(sof_count > 0)
sof_count <= sof_count - 1;
if((sof_on)&&(!skip_sof))
sof_d0<= 1;
else
sof_d0<= 0;
// EOL GENERATION
if(eol_on)
eol_d0 <= 1;
else
eol_d0 <= 0;
if(debug)
begin
$display("@%10t : [%s] Tx Data = %8h", $time, module_id, file_data);
end
end
endtask
task undrive_output;
begin
if(drive_edge == "fall") @aclk_fall;
tvalid_d0 <= 0;
sof_d0 <= 0;
eol_d0 <= 0;
end
endtask
task fetch_data;
begin
if(!ramp_gen)
begin
file_data = 0;
end
// FOR SOF PHASE ALIGNMENT
if((sof_phase > 0) && (pixel_count%(header_cols*header_rows) == 0) && (sof_count==0))
sof_count = sof_phase + 1;
if(pixel_count%(header_cols*header_rows) == 0)
begin
if((sof_phase == 0)||((sof_count == 1)&&(sof_phase >0)))
begin
sof_on = 1;
sof_count = 0;
end
else
sof_on = 0;
end
else
sof_on = 0;
// FOR EOL PHASE ALIGNMENT
if(((eol_phase == 0) && ((pixel_count+1)%header_cols == 0)) ||
((eol_phase < 0) && ((pixel_count+1)%header_cols == header_cols+eol_phase)))
eol_on = 1;
if(((eol_phase == 0) && ((pixel_count+1)%header_cols != 0)) ||
((eol_phase < 0) && ((pixel_count+1)%header_cols != header_cols+eol_phase)))
eol_on = 0;
if((eol_phase > 0) && ((pixel_count+1)%header_cols == 1) && (pixel_count >= header_cols))
begin
eol_count = eol_phase;
end
if(eol_count > 0)
begin
if(eol_count == 1)
eol_on = 1;
else
eol_on = 0;
eol_count = eol_count-1;
if(debug) $display("@%10t : [%s] Padding extra pixel for late eol ", $time, module_id);
end
else
begin
if((eol_phase < 0) && ((pixel_count+1)%header_cols == header_cols+eol_phase)) remove_count =eol_phase;
else remove_count = 0;
for(remove_count=remove_count; (remove_count<=0)&&(sof_count==0); remove_count=remove_count+1)
begin
if(!ramp_gen)
begin
file_data = 0;
case(header_mode)
0,4,11,100,104,111 : begin
file_eof = $fscanf(file_handler,"%d", compA); //Mono
if(compA == 16777215) compA = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
if((header_mode == 4)||(header_mode == 11)||(header_mode == 104)||(header_mode == 111))
begin
file_eof = $fscanf(file_handler,"%d", compB); //alpha or motion
if(compB == 16777215) compB = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
file_data = compB;
file_data = file_data << header_bpp;
end
file_data = file_data + compA;
end
8,9,10,108,109,110 : begin
file_eof = $fscanf(file_handler,"%d", compA); //R
file_eof = $fscanf(file_handler,"%d", compB); //G
file_eof = $fscanf(file_handler,"%d", compC); //B
if(compA == 16777215) compA = 0; //Don't Care place holder 16777215.
if(compB == 16777215) compB = 0; //Don't Care place holder 16777215.
if(compC == 16777215) compC = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
if((header_mode == 9)||(header_mode == 10)||(header_mode == 109)||(header_mode == 110))
begin
file_eof = $fscanf(file_handler,"%d", compD); //alpha or motion
if(compD == 16777215) compD = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
file_data = compD;
file_data = file_data << header_bpp;
end
file_data = file_data + compA;
file_data = file_data << header_bpp;
file_data = file_data + compC;
file_data = file_data << header_bpp;
file_data = file_data + compB;
end
3,7,103,107 : begin
file_eof = $fscanf(file_handler,"%d", compA); //Y
file_eof = $fscanf(file_handler,"%d", compB); //Cb
file_eof = $fscanf(file_handler,"%d", compC); //Cr
if(compA == 16777215) compA = 0; //Don't Care place holder 16777215.
if(compB == 16777215) compB = 0; //Don't Care place holder 16777215.
if(compC == 16777215) compC = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
if((header_mode == 7)||(header_mode == 107))
begin
file_eof = $fscanf(file_handler,"%d", compD); //alpha or motion
if(compD == 16777215) compD = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
file_data = compD;
file_data = file_data << header_bpp;
end
file_data = file_data + compC;
file_data = file_data << header_bpp;
file_data = file_data + compB;
file_data = file_data << header_bpp;
file_data = file_data + compA;
end
1,2,5,6,101,102,105,106 : begin
file_eof = $fscanf(file_handler,"%d", compA); //Y
file_eof = $fscanf(file_handler,"%d", compB); //Cr or Cb
if(compA == 16777215) compA = 0; //Don't Care place holder 16777215.
if(compB == 16777215) compB = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
if((header_mode == 5)||(header_mode == 6)||(header_mode == 105)||(header_mode == 106))
begin
file_eof = $fscanf(file_handler,"%d", compC); //alpha or motion
if(compC == 16777215) compC = 0; //Don't Care place holder 16777215.
isim_eof = $feof(file_handler);
file_data = compC;
file_data = file_data << header_bpp;
end
file_data = file_data + compB;
file_data = file_data << header_bpp;
file_data = file_data + compA;
end
default : begin
$display("@%10t : [%s] MODE is UNKNOWN... Data set to 0x0", $time, module_id);
end
endcase
end
else
begin
file_data = file_data+1;
if(frame_count > ramp_frames) isim_eof = 1;
end
pixel_count = pixel_count+1;
line_count = pixel_count/header_cols + 1;
frame_count = pixel_count/(header_cols*header_rows) + 1;
end
end
end
endtask
//================//
// RESET FUNCTION //
//================//
always @(negedge aresetn)
begin
//aresetn assertion//
if(debug == 1)
begin
$display("@%10t : [%s] RESET asserted...", $time, module_id);
end
EOF <= 0;
tdata_d0 <= 0;
undrive_output;
if(pixel_count > 0)
begin
$fclose(file_handler);
pixel_count = 0;
end
enable = 0;
timeout_ctr = 0;
@aresetn_rise;
if(debug == 1)
begin
$display("@%10t : [%s] RESET deasserted...", $time, module_id);
end
end
//==============================================//
// MAIN FUNCTION //
//==============================================//
//NOTE: sampling is always @rising edge of aclk //
// drive edge depends on drive_edge setting //
//==============================================//
always @(aclk_rise)
begin
//normal operation//
if ((EOF === 1'h0)&&(enable))
begin
if(pending_tx == 1)
begin
if(tready == 1)
begin
pending_tx = 0;
timeout_ctr <= 0;
end
else
begin
if(timeout_ctr > timeout)
begin
$display("@%10t : [%s] TIMEOUT ERROR : TREADY has not asserted for %d cycles .. Terminating the test....", $time, module_id, timeout);
$finish;
end
else timeout_ctr <= timeout_ctr + 1;
end
end
if(pending_tx == 0)
begin
if(fetch_new_data == 1)
begin
fetch_data;
end
if(isim_eof == 0)
begin
if((throttle==1)&&(throttle_wait_cnt > 0)&&(throttle_data_cnt==0))
begin
throttle_wait_cnt <= throttle_wait_cnt - 1;
fetch_new_data <= 0;
undrive_output;
end
else
begin
pending_tx <= 1;
fetch_new_data <= 1;
drive_output;
if(throttle == 1)
begin
if((throttle_data_cnt == 0)&&(throttle_wait_cnt == 0))
begin
throttle_data_cnt <= throttlewidth - 1;
throttle_wait_cnt <= throttlewait;
end
else
begin
throttle_data_cnt <= throttle_data_cnt - 1;
end
end
end
end
else // if(isim_eof == 1)
begin
if(!ramp_gen)
begin
$fclose(file_handler);
$display("@%10t : [%s] TOTAL PIXELS TRANSMITTED = %8d", $time, module_id, pixel_count-1);
$display("@%10t : [%s] DATA TX FINISHED", $time, module_id);
if((pixel_count-1)!=(header_cols*header_rows*header_frames))
$display("@%10t : [%s] WARNING : TOTAL PIXELS TRANSMITTED DO NOT MATCH FILE HEADER", $time, module_id);
end
pixel_count <= 0;
pending_tx <= 0;
enable <= 0;
EOF <= 1;
undrive_output;
end
end
end
else tvalid_d0 <= 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 2,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_add_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_add_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_63,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_63,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
inq_rnd_mode,
inq_id,
inq_fcc,
inq_add,
add_dest_rdy,
a1stg_in2_neq_in1_frac,
a1stg_in2_gt_in1_frac,
a1stg_in2_eq_in1_exp,
a1stg_expadd1,
a2stg_expadd,
a2stg_frac2hi_neq_0,
a2stg_frac2lo_neq_0,
a2stg_exp,
a3stg_fsdtoix_nx,
a3stg_fsdtoi_nx,
a2stg_frac2_63,
a4stg_exp,
add_of_out_cout,
a4stg_frac_neq_0,
a4stg_shl_data_neq_0,
a4stg_frac_dbl_nx,
a4stg_frac_sng_nx,
a1stg_expadd2,
a1stg_expadd4_inv,
a3stg_denorm,
a3stg_denorm_inv,
a4stg_denorm_inv,
a3stg_exp,
a4stg_round,
a3stg_lead0,
a4stg_rnd_frac_40,
a4stg_rnd_frac_39,
a4stg_rnd_frac_11,
a4stg_rnd_frac_10,
a4stg_frac_38_0_nx,
a4stg_frac_9_0_nx,
arst_l,
grst_l,
rclk,
add_pipe_active,
a1stg_denorm_sng_in1,
a1stg_denorm_dbl_in1,
a1stg_denorm_sng_in2,
a1stg_denorm_dbl_in2,
a1stg_norm_sng_in1,
a1stg_norm_dbl_in1,
a1stg_norm_sng_in2,
a1stg_norm_dbl_in2,
a1stg_step,
a1stg_stepa,
a1stg_sngop,
a1stg_intlngop,
a1stg_fsdtoix,
a1stg_fstod,
a1stg_fstoi,
a1stg_fstox,
a1stg_fdtoi,
a1stg_fdtox,
a1stg_faddsubs,
a1stg_faddsubd,
a1stg_fdtos,
a2stg_faddsubop,
a2stg_fsdtoix_fdtos,
a2stg_fitos,
a2stg_fitod,
a2stg_fxtos,
a2stg_fxtod,
a3stg_faddsubop,
a3stg_faddsubopa,
a4stg_dblop,
a6stg_fadd_in,
add_id_out_in,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
a6stg_fcmpop,
a6stg_step,
a3stg_sub_in,
add_sign_out,
add_cc_out,
a4stg_in_of,
add_exc_out,
a2stg_frac1_in_frac1,
a2stg_frac1_in_frac2,
a1stg_2nan_in_inv,
a1stg_faddsubop_inv,
a2stg_frac1_in_qnan,
a2stg_frac1_in_nv,
a2stg_frac1_in_nv_dbl,
a2stg_frac2_in_frac1,
a2stg_frac2_in_qnan,
a2stg_shr_cnt_in,
a2stg_shr_cnt_5_inv_in,
a2stg_shr_frac2_shr_int,
a2stg_shr_frac2_shr_dbl,
a2stg_shr_frac2_shr_sng,
a2stg_shr_frac2_max,
a2stg_sub_step,
a2stg_fracadd_frac2_inv_in,
a2stg_fracadd_frac2_inv_shr1_in,
a2stg_fracadd_frac2,
a2stg_fracadd_cin_in,
a3stg_exp_7ff,
a3stg_exp_ff,
a3stg_exp_add,
a2stg_expdec_neq_0,
a3stg_exp10_0_eq0,
a3stg_exp10_1_eq0,
a3stg_fdtos_inv,
a4stg_fixtos_fxtod_inv,
a4stg_rnd_frac_add_inv,
a4stg_shl_cnt_in,
a4stg_rnd_sng,
a4stg_rnd_dbl,
add_frac_out_rndadd,
add_frac_out_rnd_frac,
add_frac_out_shl,
a4stg_to_0,
add_exp_out_expinc,
add_exp_out_exp,
add_exp_out_exp1,
add_exp_out_expadd,
a4stg_to_0_inv,
se,
si,
so
);
parameter
FADDS= 8'h41,
FADDD= 8'h42,
FSUBS= 8'h45,
FSUBD= 8'h46,
FCMPS= 8'h51,
FCMPD= 8'h52,
FCMPES= 8'h55,
FCMPED= 8'h56,
FSTOX= 8'h81,
FDTOX= 8'h82,
FSTOI= 8'hd1,
FDTOI= 8'hd2,
FSTOD= 8'hc9,
FDTOS= 8'hc6,
FXTOS= 8'h84,
FXTOD= 8'h88,
FITOS= 8'hc4,
FITOD= 8'hc8;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_63; // request operand 1[63]
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_63; // request operand 2[63]
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input [1:0] inq_fcc; // request cc ID to op pipes
input inq_add; // add pipe request
input add_dest_rdy; // add result req accepted for CPX
input a1stg_in2_neq_in1_frac; // operand 2 fraction != oprnd 1 frac
input a1stg_in2_gt_in1_frac; // operand 2 fraction > oprnd 1 frac
input a1stg_in2_eq_in1_exp; // operand 2 exponent == oprnd 1 exp
input [11:0] a1stg_expadd1; // exponent adder 1 output- add 1 stage
input [11:0] a2stg_expadd; // exponent adder- add 2 stage
input a2stg_frac2hi_neq_0; // fraction 2[62:32]in add 2 stage != 0
input a2stg_frac2lo_neq_0; // fraction 2[31:11] in add 2 stage != 0
input [11:0] a2stg_exp; // exponent- add 2 stage
input a3stg_fsdtoix_nx; // inexact result for flt -> ints
input a3stg_fsdtoi_nx; // inexact result for flt -> 32b ints
input a2stg_frac2_63; // fraction 2 bit[63]- add 2 stage
input [11:0] a4stg_exp; // exponent- add 4 stage
input add_of_out_cout; // fraction rounding adder carry out
input a4stg_frac_neq_0; // fraction != 0- add 4 stage
input a4stg_shl_data_neq_0; // left shift result != 0- add 4 stage
input a4stg_frac_dbl_nx; // inexact double precision result
input a4stg_frac_sng_nx; // inexact single precision result
input [5:0] a1stg_expadd2; // exponent adder 2 output- add 1 stage
input [10:0] a1stg_expadd4_inv; // exponent adder 4 output- add 1 stage
input a3stg_denorm; // denorm output- add 3 stage
input a3stg_denorm_inv; // result is not a denorm- add 3 stage
input a4stg_denorm_inv; // 0 the exponent
input [10:0] a3stg_exp; // exponent- add 3 stage
input a4stg_round; // round the result- add 4 stage
input [5:0] a3stg_lead0; // leading 0's count- add 3 stage
input a4stg_rnd_frac_40; // rounded fraction[40]- add 4 stage
input a4stg_rnd_frac_39; // rounded fraction[39]- add 4 stage
input a4stg_rnd_frac_11; // rounded fraction[11]- add 4 stage
input a4stg_rnd_frac_10; // rounded fraction[10]- add 4 stage
input a4stg_frac_38_0_nx; // inexact single precision result
input a4stg_frac_9_0_nx; // inexact double precision result
input arst_l; // global asynchronous reset- asserted low
input grst_l; // global synchronous reset- asserted low
input rclk; // global clock
output add_pipe_active; // add pipe is executing a valid instr
output a1stg_denorm_sng_in1; // select line to normalized fraction 1
output a1stg_denorm_dbl_in1; // select line to normalized fraction 1
output a1stg_denorm_sng_in2; // select line to normalized fraction 2
output a1stg_denorm_dbl_in2; // select line to normalized fraction 2
output a1stg_norm_sng_in1; // select line to normalized fraction 1
output a1stg_norm_dbl_in1; // select line to normalized fraction 1
output a1stg_norm_sng_in2; // select line to normalized fraction 2
output a1stg_norm_dbl_in2; // select line to normalized fraction 2
output a1stg_step; // add pipe load
output a1stg_stepa; // add pipe load- copy
output a1stg_sngop; // single precision operation- add 1 stg
output a1stg_intlngop; // integer/long input- add 1 stage
output a1stg_fsdtoix; // float to integer convert- add 1 stg
output a1stg_fstod; // fstod- add 1 stage
output a1stg_fstoi; // fstoi- add 1 stage
output a1stg_fstox; // fstox- add 1 stage
output a1stg_fdtoi; // fdtoi- add 1 stage
output a1stg_fdtox; // fdtox- add 1 stage
output a1stg_faddsubs; // add/subtract single- add 1 stg
output a1stg_faddsubd; // add/subtract double- add 1 stg
output a1stg_fdtos; // fdtos- add 1 stage
output a2stg_faddsubop; // float add or subtract- add 2 stage
output a2stg_fsdtoix_fdtos; // float to integer convert- add 2 stg
output a2stg_fitos; // fitos- add 2 stage
output a2stg_fitod; // fitod- add 2 stage
output a2stg_fxtos; // fxtos- add 2 stage
output a2stg_fxtod; // fxtod- add 2 stage
output a3stg_faddsubop; // denorm compare lead0[10] input select
output [1:0] a3stg_faddsubopa; // denorm compare lead0[10] input select
output a4stg_dblop; // double precision operation- add 4 stg
output a6stg_fadd_in; // add pipe output request next cycle
output [9:0] add_id_out_in; // add pipe output ID next cycle
output [1:0] add_fcc_out; // add pipe input fcc passed through
output a6stg_dbl_dst; // float double result- add 6 stage
output a6stg_sng_dst; // float single result- add 6 stage
output a6stg_long_dst; // 64bit integer result- add 6 stage
output a6stg_int_dst; // 32bit integer result- add 6 stage
output a6stg_fcmpop; // compare- add 6 stage
output a6stg_step; // advance the add pipe
output a3stg_sub_in; // subtract in main adder- add 3 stage
output add_sign_out; // add sign output
output [1:0] add_cc_out; // add pipe result- condition
output a4stg_in_of; // add overflow- select exp out
output [4:0] add_exc_out; // add pipe result- exception flags
output a2stg_frac1_in_frac1; // select line to a2stg_frac1
output a2stg_frac1_in_frac2; // select line to a2stg_frac1
output a1stg_2nan_in_inv; // 2 NaN inputs- a1 stage
output a1stg_faddsubop_inv; // add/subtract- a1 stage
output a2stg_frac1_in_qnan; // make fraction 1 a QNaN
output a2stg_frac1_in_nv; // NV- make a new QNaN
output a2stg_frac1_in_nv_dbl; // NV- make a new double prec QNaN
output a2stg_frac2_in_frac1; // select line to a2stg_frac2
output a2stg_frac2_in_qnan; // make fraction 2 a QNaN
output [5:0] a2stg_shr_cnt_in; // right shift count input- add 1 stage
output a2stg_shr_cnt_5_inv_in; // right shift count input[5]- add 1 stg
output a2stg_shr_frac2_shr_int; // select line to a3stg_frac2
output a2stg_shr_frac2_shr_dbl; // select line to a3stg_frac2
output a2stg_shr_frac2_shr_sng; // select line to a3stg_frac2
output a2stg_shr_frac2_max; // select line to a3stg_frac2
output a2stg_sub_step; // select line to a3stg_frac2
output a2stg_fracadd_frac2_inv_in; // sel line to main adder input 2
output a2stg_fracadd_frac2_inv_shr1_in; // sel line to main adder in 2
output a2stg_fracadd_frac2; // select line to main adder input 2
output a2stg_fracadd_cin_in; // carry in to main adder- add 1 stage
output a3stg_exp_7ff; // select line to a3stg_exp
output a3stg_exp_ff; // select line to a3stg_exp
output a3stg_exp_add; // select line to a3stg_exp
output a2stg_expdec_neq_0; // exponent will be < 54
output a3stg_exp10_0_eq0; // exponent[10:0]==0- add 3 stage
output a3stg_exp10_1_eq0; // exponent[10:1]==0- add 3 stage
output a3stg_fdtos_inv; // double to single convert- add 3 stg
output a4stg_fixtos_fxtod_inv; // int to single/double cvt- add 4 stg
output a4stg_rnd_frac_add_inv; // select line to a4stg_rnd_frac
output [9:0] a4stg_shl_cnt_in; // postnorm shift left count- add 3 stg
output a4stg_rnd_sng; // round to single precision- add 4 stg
output a4stg_rnd_dbl; // round to double precision- add 4 stg
output add_frac_out_rndadd; // select line to add_frac_out
output add_frac_out_rnd_frac; // select line to add_frac_out
output add_frac_out_shl; // select line to add_frac_out
output a4stg_to_0; // result to max finite on overflow
output add_exp_out_expinc; // select line to add_exp_out
output add_exp_out_exp; // select line to add_exp_out
output add_exp_out_exp1; // select line to add_exp_out
output add_exp_out_expadd; // select line to add_exp_out
output a4stg_to_0_inv; // result to infinity on overflow
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire a1stg_in1_51;
wire a1stg_in1_54;
wire a1stg_in1_63;
wire a1stg_in1_50_0_neq_0;
wire a1stg_in1_53_32_neq_0;
wire a1stg_in1_exp_eq_0;
wire a1stg_in1_exp_neq_ffs;
wire a1stg_in2_51;
wire a1stg_in2_54;
wire a1stg_in2_63;
wire a1stg_in2_50_0_neq_0;
wire a1stg_in2_53_32_neq_0;
wire a1stg_in2_exp_eq_0;
wire a1stg_in2_exp_neq_ffs;
wire a1stg_denorm_sng_in1;
wire a1stg_denorm_dbl_in1;
wire a1stg_denorm_sng_in2;
wire a1stg_denorm_dbl_in2;
wire a1stg_norm_sng_in1;
wire a1stg_norm_dbl_in1;
wire a1stg_norm_sng_in2;
wire a1stg_norm_dbl_in2;
wire a1stg_snan_sng_in1;
wire a1stg_snan_dbl_in1;
wire a1stg_snan_sng_in2;
wire a1stg_snan_dbl_in2;
wire a1stg_qnan_sng_in1;
wire a1stg_qnan_dbl_in1;
wire a1stg_qnan_sng_in2;
wire a1stg_qnan_dbl_in2;
wire a1stg_snan_in1;
wire a1stg_snan_in2;
wire a1stg_qnan_in1;
wire a1stg_qnan_in2;
wire a1stg_nan_sng_in1;
wire a1stg_nan_dbl_in1;
wire a1stg_nan_sng_in2;
wire a1stg_nan_dbl_in2;
wire a1stg_nan_in1;
wire a1stg_nan_in2;
wire a1stg_nan_in;
wire a1stg_2nan_in;
wire a1stg_inf_sng_in1;
wire a1stg_inf_dbl_in1;
wire a1stg_inf_sng_in2;
wire a1stg_inf_dbl_in2;
wire a1stg_inf_in1;
wire a1stg_inf_in2;
wire a1stg_2inf_in;
wire a1stg_infnan_sng_in1;
wire a1stg_infnan_dbl_in1;
wire a1stg_infnan_sng_in2;
wire a1stg_infnan_dbl_in2;
wire a1stg_infnan_in1;
wire a1stg_infnan_in2;
wire a1stg_infnan_in;
wire a1stg_2zero_in;
wire a1stg_step;
wire a1stg_stepa;
wire [7:0] a1stg_op_in;
wire [7:0] a1stg_op;
wire a1stg_sngop;
wire [3:0] a1stg_sngopa;
wire a1stg_dblop;
wire [3:0] a1stg_dblopa;
wire [1:0] a1stg_rnd_mode;
wire [4:0] a1stg_id;
wire [1:0] a1stg_fcc;
wire a1stg_fadd;
wire a1stg_dbl_dst;
wire a1stg_sng_dst;
wire a1stg_long_dst;
wire a1stg_int_dst;
wire a1stg_intlngop;
wire a1stg_faddsubop;
wire a1stg_fsubop;
wire a1stg_fsdtox;
wire a1stg_fcmpesd;
wire a1stg_fcmpsd;
wire a1stg_faddsub_dtosop;
wire a1stg_fdtoix;
wire a1stg_fstoix;
wire a1stg_fsdtoix;
wire a1stg_fixtosd;
wire a1stg_fstod;
wire a1stg_fstoi;
wire a1stg_fstox;
wire a1stg_fdtoi;
wire a1stg_fdtox;
wire a1stg_fsdtoix_fdtos;
wire a1stg_fitos;
wire a1stg_fitod;
wire a1stg_fxtos;
wire a1stg_fcmpop;
wire a1stg_f4cycop;
wire a1stg_fixtos_fxtod;
wire a1stg_faddsubs_fdtos;
wire a1stg_faddsubs;
wire a1stg_faddsubd;
wire a1stg_fdtos;
wire a1stg_fistod;
wire a1stg_fixtos;
wire a1stg_fxtod;
wire a1stg_opdec_36;
wire [34:28] a1stg_opdec;
wire [3:0] a1stg_opdec_24_21;
wire [8:0] a1stg_opdec_19_11;
wire [9:0] a1stg_opdec_9_0;
wire fixtosd_hold;
wire [30:0] a2stg_opdec_in;
wire a2stg_opdec_36;
wire [34:28] a2stg_opdec;
wire [3:0] a2stg_opdec_24_21;
wire [8:0] a2stg_opdec_19_11;
wire [9:0] a2stg_opdec_9_0;
wire [1:0] a2stg_rnd_mode;
wire [4:0] a2stg_id;
wire [1:0] a2stg_fcc;
wire a2stg_fadd;
wire a2stg_long_dst;
wire a2stg_faddsubop;
wire a2stg_fsubop;
wire a2stg_faddsub_dtosop;
wire a2stg_fdtoix;
wire a2stg_fstoix;
wire a2stg_fsdtoix;
wire a2stg_fstod;
wire a2stg_fstoi;
wire a2stg_fstox;
wire a2stg_fdtoi;
wire a2stg_fdtox;
wire a2stg_fsdtoix_fdtos;
wire a2stg_fitos;
wire a2stg_fitod;
wire a2stg_fxtos;
wire a2stg_fcmpop;
wire a2stg_fixtos_fxtod;
wire a2stg_fdtos;
wire a2stg_fxtod;
wire a3stg_opdec_36;
wire [34:29] a3stg_opdec;
wire a3stg_opdec_24;
wire a3stg_opdec_21;
wire [9:0] a3stg_opdec_9_0;
wire [1:0] a3stg_rnd_mode;
wire [4:0] a3stg_id;
wire [1:0] a3stg_fcc;
wire a3stg_fadd;
wire a3stg_int_dst;
wire a3stg_faddsubop;
wire [1:0] a3stg_faddsubopa;
wire a3stg_fsdtoix;
wire a3stg_f4cycop;
wire a3stg_fixtos_fxtod;
wire a3stg_fdtos;
wire a4stg_opdec_36;
wire [34:29] a4stg_opdec;
wire a4stg_opdec_24;
wire a4stg_opdec_21;
wire a4stg_opdec_9;
wire [7:0] a4stg_opdec_7_0;
wire [1:0] a4stg_rnd_mode_in;
wire [1:0] a4stg_rnd_mode;
wire [1:0] a4stg_rnd_mode2;
wire [9:0] a4stg_id_in;
wire [9:0] a4stg_id;
wire [1:0] a4stg_fcc;
wire a4stg_dblop;
wire a4stg_fadd;
wire a4stg_faddsubop;
wire a4stg_faddsub_dtosop;
wire a4stg_fsdtoix;
wire a4stg_fcmpop;
wire a4stg_fixtos_fxtod;
wire a4stg_faddsubs_fdtos;
wire a4stg_faddsubs;
wire a4stg_faddsubd;
wire a4stg_fdtos;
wire a4stg_fistod;
wire [34:30] a5stg_opdec;
wire a5stg_opdec_9;
wire a5stg_opdec_7;
wire a5stg_opdec_1;
wire a5stg_opdec_0;
wire [9:0] a5stg_id;
wire a5stg_fadd;
wire a5stg_fixtos_fxtod;
wire a5stg_fixtos;
wire a5stg_fxtod;
wire [34:30] a6stg_opdec_in;
wire a6stg_opdec_in_9;
wire a6stg_fadd_in;
wire [34:30] a6stg_opdec;
wire a6stg_opdec_9;
wire [9:0] add_id_out_in;
wire [9:0] add_id_out;
wire [1:0] add_fcc_out_in;
wire [1:0] add_fcc_out;
wire a6stg_fadd;
wire a6stg_dbl_dst;
wire a6stg_sng_dst;
wire a6stg_long_dst;
wire a6stg_int_dst;
wire a6stg_fcmpop;
wire a6stg_hold;
wire a6stg_step;
wire a1stg_sub;
wire a2stg_sign1;
wire a2stg_sign2;
wire a2stg_sub;
wire a2stg_in2_neq_in1_frac;
wire a2stg_in2_gt_in1_frac;
wire a2stg_in2_eq_in1_exp;
wire a2stg_in2_gt_in1_exp;
wire a2stg_nan_in;
wire a2stg_nan_in2;
wire a2stg_snan_in2;
wire a2stg_qnan_in2;
wire a2stg_snan_in1;
wire a2stg_qnan_in1;
wire a2stg_2zero_in;
wire a2stg_2inf_in;
wire a2stg_in2_eq_in1;
wire a2stg_in2_gt_in1;
wire a3stg_sub_in;
wire a2stg_faddsub_sign;
wire a3stg_sign_in;
wire a3stg_sign;
wire a2stg_cc_1;
wire a2stg_cc_0;
wire [1:0] a2stg_cc;
wire [1:0] a3stg_cc;
wire a4stg_sign_in;
wire a4stg_sign;
wire a4stg_sign2;
wire [1:0] a4stg_cc;
wire add_sign_out;
wire [1:0] add_cc_out_in;
wire [1:0] add_cc_out;
wire a1stg_nv;
wire a2stg_nv;
wire a1stg_of_mask;
wire a2stg_of_mask;
wire a3stg_nv_in;
wire a3stg_nv;
wire a3stg_of_mask;
wire a2stg_nx_tmp1;
wire a2stg_nx_tmp2;
wire a2stg_nx_tmp3;
wire a3stg_a2_expadd_11;
wire a3stg_nx_tmp1;
wire a3stg_nx_tmp2;
wire a3stg_nx_tmp3;
wire a3stg_nx;
wire a4stg_nv_in;
wire a4stg_nv;
wire a4stg_nv2;
wire a4stg_of_mask_in;
wire a4stg_of_mask;
wire a4stg_of_mask2;
wire a4stg_nx_in;
wire a4stg_nx;
wire a4stg_nx2;
wire add_nv_out;
wire a4stg_in_of;
wire add_of_out_tmp1_in;
wire add_of_out_tmp1;
wire add_of_out_tmp2;
wire add_of_out;
wire a4stg_uf;
wire add_uf_out;
wire add_nx_out_in;
wire add_nx_out;
wire [4:0] add_exc_out;
wire a2stg_frac1_in_frac1;
wire a2stg_frac1_in_frac2;
wire a1stg_2nan_in_inv;
wire a1stg_faddsubop_inv;
wire a2stg_frac1_in_qnan;
wire a2stg_frac1_in_nv;
wire a2stg_frac1_in_nv_dbl;
wire a2stg_frac2_in_frac1;
wire a2stg_frac2_in_qnan;
wire a1stg_exp_diff_add1;
wire a1stg_exp_diff_add2;
wire a1stg_exp_diff_5;
wire [10:0] a1stg_exp_diff;
wire [5:0] a1stg_clamp63;
wire [5:0] a2stg_shr_cnt_in;
wire a2stg_shr_cnt_5_inv_in;
wire a2stg_shr_frac2_shr_int;
wire a2stg_shr_frac2_shr_dbl;
wire a2stg_shr_frac2_shr_sng;
wire a2stg_shr_frac2_max;
wire a2stg_sub_step;
wire a1stg_faddsub_clamp63_0;
wire a2stg_fracadd_frac2_inv_in;
wire a2stg_fracadd_frac2_inv_shr1_in;
wire a2stg_fracadd_frac2_in;
wire a2stg_fracadd_frac2;
wire a2stg_fracadd_cin_in;
wire a3stg_exp_7ff;
wire a3stg_exp_ff;
wire a3stg_exp_add;
wire a2stg_expdec_neq_0;
wire a3stg_exp10_0_eq0;
wire a3stg_exp10_1_eq0;
wire a3stg_fdtos_inv;
wire a4stg_fixtos_fxtod_inv;
wire a4stg_rnd_frac_add_inv;
wire [9:0] a4stg_shl_cnt_in;
wire a4stg_rnd_sng;
wire a4stg_rnd_dbl;
wire a4stg_rndup_sng;
wire a4stg_rndup_dbl;
wire a4stg_rndup;
wire a5stg_rndup;
wire add_frac_out_rndadd;
wire add_frac_out_rnd_frac;
wire add_frac_out_shl;
wire a4stg_to_0;
wire add_exp_out_expinc;
wire add_exp_out_exp;
wire add_exp_out_exp1;
wire add_exp_out_expadd;
wire a4stg_to_0_inv;
wire add_pipe_active_in;
wire add_pipe_active;
dffrl_async #(1) dffrl_add_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (add_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!add_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_a1stg_in1_51 (
.din (inq_in1_51),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_54 (
.din (inq_in1_54),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_63 (
.din (inq_in1_63),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_63),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_51 (
.din (inq_in2_51),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_54 (
.din (inq_in2_54),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_63 (
.din (inq_in2_63),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_63),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_denorm_sng_in1= a1stg_in1_exp_eq_0 && a1stg_sngopa[0];
assign a1stg_denorm_dbl_in1= a1stg_in1_exp_eq_0 && a1stg_dblopa[0];
assign a1stg_denorm_sng_in2= a1stg_in2_exp_eq_0 && a1stg_sngopa[0];
assign a1stg_denorm_dbl_in2= a1stg_in2_exp_eq_0 && a1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_norm_sng_in1= (!a1stg_in1_exp_eq_0) && a1stg_sngopa[0];
assign a1stg_norm_dbl_in1= (!a1stg_in1_exp_eq_0) && a1stg_dblopa[0];
assign a1stg_norm_sng_in2= (!a1stg_in2_exp_eq_0) && a1stg_sngopa[0];
assign a1stg_norm_dbl_in2= (!a1stg_in2_exp_eq_0) && a1stg_dblopa[0];
///////////////////////////////////////////////////////////////////////////////
//
// Nan add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_snan_sng_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_54)
&& a1stg_in1_53_32_neq_0 && a1stg_sngopa[1];
assign a1stg_snan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_51)
&& a1stg_in1_50_0_neq_0 && a1stg_dblopa[1];
assign a1stg_snan_sng_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_54)
&& a1stg_in2_53_32_neq_0 && a1stg_sngopa[1];
assign a1stg_snan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_51)
&& a1stg_in2_50_0_neq_0 && a1stg_dblopa[1];
assign a1stg_qnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_54
&& a1stg_sngopa[1];
assign a1stg_qnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_51
&& a1stg_dblopa[1];
assign a1stg_qnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_54
&& a1stg_sngopa[1];
assign a1stg_qnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_51
&& a1stg_dblopa[1];
assign a1stg_snan_in1= a1stg_snan_sng_in1 || a1stg_snan_dbl_in1;
assign a1stg_snan_in2= a1stg_snan_sng_in2 || a1stg_snan_dbl_in2;
assign a1stg_qnan_in1= a1stg_qnan_sng_in1 || a1stg_qnan_dbl_in1;
assign a1stg_qnan_in2= a1stg_qnan_sng_in2 || a1stg_qnan_dbl_in2;
assign a1stg_nan_sng_in1= (!a1stg_in1_exp_neq_ffs)
&& (a1stg_in1_54 || a1stg_in1_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_nan_dbl_in1= (!a1stg_in1_exp_neq_ffs)
&& (a1stg_in1_51 || a1stg_in1_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_nan_sng_in2= (!a1stg_in2_exp_neq_ffs)
&& (a1stg_in2_54 || a1stg_in2_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_nan_dbl_in2= (!a1stg_in2_exp_neq_ffs)
&& (a1stg_in2_51 || a1stg_in2_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_nan_in1= a1stg_nan_sng_in1 || a1stg_nan_dbl_in1;
assign a1stg_nan_in2= a1stg_nan_sng_in2 || a1stg_nan_dbl_in2;
assign a1stg_nan_in= a1stg_nan_in1 || a1stg_nan_in2;
assign a1stg_2nan_in= a1stg_nan_in1 && a1stg_nan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Infinity add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_inf_sng_in1= (!a1stg_in1_exp_neq_ffs)
&& (!a1stg_in1_54) && (!a1stg_in1_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_inf_dbl_in1= (!a1stg_in1_exp_neq_ffs)
&& (!a1stg_in1_51) && (!a1stg_in1_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_inf_sng_in2= (!a1stg_in2_exp_neq_ffs)
&& (!a1stg_in2_54) && (!a1stg_in2_53_32_neq_0)
&& a1stg_sngopa[2];
assign a1stg_inf_dbl_in2= (!a1stg_in2_exp_neq_ffs)
&& (!a1stg_in2_51) && (!a1stg_in2_50_0_neq_0)
&& a1stg_dblopa[2];
assign a1stg_inf_in1= a1stg_inf_sng_in1 || a1stg_inf_dbl_in1;
assign a1stg_inf_in2= a1stg_inf_sng_in2 || a1stg_inf_dbl_in2;
assign a1stg_2inf_in= a1stg_inf_in1 && a1stg_inf_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan add inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_infnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_sngopa[3];
assign a1stg_infnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_dblopa[3];
assign a1stg_infnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_sngopa[3];
assign a1stg_infnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_dblopa[3];
assign a1stg_infnan_in1= a1stg_infnan_sng_in1 || a1stg_infnan_dbl_in1;
assign a1stg_infnan_in2= a1stg_infnan_sng_in2 || a1stg_infnan_dbl_in2;
assign a1stg_infnan_in= a1stg_infnan_in1 || a1stg_infnan_in2;
///////////////////////////////////////////////////////////////////////////////
//
// Zero inputs.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// correctly detect case where both single precision operands are zero
// assign a1stg_2zero_in= a1stg_in1_exp_eq_0 && (!a1stg_in1_51)
// && (!a1stg_in1_50_0_neq_0)
// && a1stg_in2_exp_eq_0 && (!a1stg_in2_51)
// && (!a1stg_in2_50_0_neq_0);
assign a1stg_2zero_in =
a1stg_in1_exp_eq_0 &&
(!a1stg_in1_54 || a1stg_dblopa[3]) && // (!bit54 ) || dp
(!a1stg_in1_53_32_neq_0 || a1stg_dblopa[3]) && // (!bit53 && !bit52) || dp
(!a1stg_in1_51) &&
(!a1stg_in1_50_0_neq_0) &&
a1stg_in2_exp_eq_0 &&
(!a1stg_in2_54 || a1stg_dblopa[3]) && // (!bit54 ) || dp
(!a1stg_in2_53_32_neq_0 || a1stg_dblopa[3]) && // (!bit53 && !bit52) || dp
(!a1stg_in2_51) &&
(!a1stg_in2_50_0_neq_0);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point add control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add input stage.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_step= (!fixtosd_hold) && (!a6stg_hold);
assign a1stg_stepa= a1stg_step;
assign a1stg_op_in[7:0]= ({8{inq_add}}
& inq_op[7:0]);
dffre #(8) i_a1stg_op (
.din (a1stg_op_in[7:0]),
.en (a1stg_step),
.rst (reset),
.clk (rclk),
.q (a1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_sngop (
.din (inq_op[0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_sngop),
.se (se),
.si (),
.so ()
);
dffe #(4) i_a1stg_sngopa (
.din ({4{inq_op[0]}}),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_sngopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a1stg_dblop (
.din (inq_op[1]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe #(4) i_a1stg_dblopa (
.din ({4{inq_op[1]}}),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_dblopa[3:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_a1stg_id (
.din (inq_id[4:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a1stg_fcc (
.din (inq_fcc[1:0]),
.en (a1stg_step),
.clk (rclk),
.q (a1stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_fadd= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED)
|| (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
|| (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
|| (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD)
|| (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
|| (a1stg_op[7:0]==FSTOD) || (a1stg_op[7:0]==FDTOS);
assign a1stg_dbl_dst= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FXTOD)
|| (a1stg_op[7:0]==FSTOD);
assign a1stg_sng_dst= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
|| (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_long_dst= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
assign a1stg_int_dst= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FDTOI);
assign a1stg_intlngop= (!(a1stg_sngopa[3] || a1stg_dblop));
assign a1stg_faddsubop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fsubop= (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fsdtox= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fcmpesd= (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
assign a1stg_fcmpsd= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD);
assign a1stg_faddsub_dtosop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_fdtoix= (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fstoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX);
assign a1stg_fsdtoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
assign a1stg_fixtosd= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
|| (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD);
assign a1stg_fstod= (a1stg_op[7:0]==FSTOD);
assign a1stg_fstoi= (a1stg_op[7:0]==FSTOI);
assign a1stg_fstox= (a1stg_op[7:0]==FSTOX);
assign a1stg_fdtoi= (a1stg_op[7:0]==FDTOI);
assign a1stg_fdtox= (a1stg_op[7:0]==FDTOX);
assign a1stg_fsdtoix_fdtos= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
|| (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_fitos= (a1stg_op[7:0]==FITOS);
assign a1stg_fitod= (a1stg_op[7:0]==FITOD);
assign a1stg_fxtos= (a1stg_op[7:0]==FXTOS);
assign a1stg_fcmpop= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
|| (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
assign a1stg_f4cycop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
|| (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
|| (a1stg_op[7:0]==FDTOS) || (a1stg_op[7:0]==FSTOD)
|| (a1stg_op[7:0]==FITOD);
assign a1stg_fixtos_fxtod= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
|| (a1stg_op[7:0]==FXTOD);
assign a1stg_faddsubs_fdtos= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
|| (a1stg_op[7:0]==FDTOS);
assign a1stg_faddsubs= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS);
assign a1stg_faddsubd= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD);
assign a1stg_fdtos= (a1stg_op[7:0]==FDTOS);
assign a1stg_fistod= (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FSTOD);
assign a1stg_fixtos= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS);
assign a1stg_fxtod= (a1stg_op[7:0]==FXTOD);
assign a1stg_opdec_36 = a1stg_dblop;
assign a1stg_opdec[34:28] =
{a1stg_fadd,
a1stg_dbl_dst,
a1stg_sng_dst,
a1stg_long_dst,
a1stg_int_dst,
a1stg_faddsubop,
a1stg_fsubop};
assign a1stg_opdec_24_21[3:0] =
{a1stg_faddsub_dtosop,
a1stg_fdtoix,
a1stg_fstoix,
a1stg_fsdtoix};
assign a1stg_opdec_19_11[8:0] =
{a1stg_fstod,
a1stg_fstoi,
a1stg_fstox,
a1stg_fdtoi,
a1stg_fdtox,
a1stg_fsdtoix_fdtos,
a1stg_fitos,
a1stg_fitod,
a1stg_fxtos};
assign a1stg_opdec_9_0[9:0] =
{a1stg_fcmpop,
a1stg_f4cycop,
a1stg_fixtos_fxtod,
a1stg_faddsubs_fdtos,
a1stg_faddsubs,
a1stg_faddsubd,
a1stg_fdtos,
a1stg_fistod,
a1stg_fixtos,
a1stg_fxtod};
assign fixtosd_hold= a2stg_fixtos_fxtod
&& (!(a1stg_op[7] && (!a1stg_op[1]) && (!a1stg_op[0])
&& (a1stg_op[2] || (!a1stg_op[6]))));
assign a2stg_opdec_in[30:0]= {31{(!fixtosd_hold)}}
& {a1stg_opdec_36, a1stg_opdec[34:28],
a1stg_opdec_24_21[3:0], a1stg_opdec_19_11[8:0],
a1stg_opdec_9_0[9:0]};
dffre #(31) i_a2stg_opdec (
.din (a2stg_opdec_in[30:0]),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a2stg_opdec_36, a2stg_opdec[34:28], a2stg_opdec_24_21[3:0],
a2stg_opdec_19_11[8:0], a2stg_opdec_9_0[9:0]}),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a2stg_rnd_mode (
.din (a1stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_a2stg_id (
.din (a1stg_id[4:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a2stg_fcc (
.din (a1stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_fadd= a2stg_opdec[34];
assign a2stg_long_dst= a2stg_opdec[31];
assign a2stg_faddsubop= a2stg_opdec[29];
assign a2stg_fsubop= a2stg_opdec[28];
assign a2stg_faddsub_dtosop= a2stg_opdec_24_21[3];
assign a2stg_fdtoix= a2stg_opdec_24_21[2];
assign a2stg_fstoix= a2stg_opdec_24_21[1];
assign a2stg_fsdtoix= a2stg_opdec_24_21[0];
assign a2stg_fstod= a2stg_opdec_19_11[8];
assign a2stg_fstoi= a2stg_opdec_19_11[7];
assign a2stg_fstox= a2stg_opdec_19_11[6];
assign a2stg_fdtoi= a2stg_opdec_19_11[5];
assign a2stg_fdtox= a2stg_opdec_19_11[4];
assign a2stg_fsdtoix_fdtos= a2stg_opdec_19_11[3];
assign a2stg_fitos= a2stg_opdec_19_11[2];
assign a2stg_fitod= a2stg_opdec_19_11[1];
assign a2stg_fxtos= a2stg_opdec_19_11[0];
assign a2stg_fcmpop= a2stg_opdec_9_0[9];
assign a2stg_fixtos_fxtod= a2stg_opdec_9_0[7];
assign a2stg_fdtos= a2stg_opdec_9_0[3];
assign a2stg_fxtod= a2stg_opdec_9_0[0];
dffre #(19) i_a3stg_opdec (
.din ({a2stg_opdec_36, a2stg_opdec[34:29], a2stg_opdec_24_21[3],
a2stg_opdec_24_21[0], a2stg_opdec_9_0[9:0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
a3stg_opdec_21, a3stg_opdec_9_0[9:0]}),
.se (se),
.si (),
.so ()
);
dffre #(2) i_a3stg_faddsubopa (
.din ({2{a2stg_faddsubop}}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q (a3stg_faddsubopa[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a3stg_rnd_mode (
.din (a2stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_a3stg_id (
.din (a2stg_id[4:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a3stg_fcc (
.din (a2stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_fadd= a3stg_opdec[34];
assign a3stg_int_dst= a3stg_opdec[30];
assign a3stg_faddsubop= a3stg_opdec[29];
assign a3stg_fsdtoix= a3stg_opdec_21;
assign a3stg_f4cycop= a3stg_opdec_9_0[8];
assign a3stg_fixtos_fxtod= a3stg_opdec_9_0[7];
assign a3stg_fdtos= a3stg_opdec_9_0[3];
dffre #(18) i_a4stg_opdec (
.din ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
a3stg_opdec_21, a3stg_opdec_9_0[9], a3stg_opdec_9_0[7:0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a4stg_opdec_36, a4stg_opdec[34:29], a4stg_opdec_24,
a4stg_opdec_21, a4stg_opdec_9, a4stg_opdec_7_0[7:0]}),
.se (se),
.si (),
.so ()
);
assign a4stg_rnd_mode_in[1:0]= ({2{a3stg_f4cycop}}
& a3stg_rnd_mode[1:0])
| ({2{(!a3stg_f4cycop)}}
& a4stg_rnd_mode2[1:0]);
dffe #(2) i_a4stg_rnd_mode (
.din (a4stg_rnd_mode_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a4stg_rnd_mode2 (
.din (a3stg_rnd_mode[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_rnd_mode2[1:0]),
.se (se),
.si (),
.so ()
);
assign a4stg_id_in[9:0]= {(a3stg_id[4:2]==3'o7),
(a3stg_id[4:2]==3'o6),
(a3stg_id[4:2]==3'o5),
(a3stg_id[4:2]==3'o4),
(a3stg_id[4:2]==3'o3),
(a3stg_id[4:2]==3'o2),
(a3stg_id[4:2]==3'o1),
(a3stg_id[4:2]==3'o0),
a3stg_id[1:0]};
dffe #(10) i_a4stg_id (
.din (a4stg_id_in[9:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_id[9:0]),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a4stg_fcc (
.din (a3stg_fcc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_fcc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add stages 4 and 5.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_dblop= a4stg_opdec_36;
assign a4stg_fadd= a4stg_opdec[34];
assign a4stg_faddsubop= a4stg_opdec[29];
assign a4stg_faddsub_dtosop= a4stg_opdec_24;
assign a4stg_fsdtoix= a4stg_opdec_21;
assign a4stg_fcmpop= a4stg_opdec_9;
assign a4stg_fixtos_fxtod= a4stg_opdec_7_0[7];
assign a4stg_faddsubs_fdtos= a4stg_opdec_7_0[6];
assign a4stg_faddsubs= a4stg_opdec_7_0[5];
assign a4stg_faddsubd= a4stg_opdec_7_0[4];
assign a4stg_fdtos= a4stg_opdec_7_0[3];
assign a4stg_fistod= a4stg_opdec_7_0[2];
dffre #(9) i_a5stg_opdec (
.din ({a4stg_opdec[34:30], a4stg_opdec_9, a4stg_opdec_7_0[7],
a4stg_opdec_7_0[1], a4stg_opdec_7_0[0]}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a5stg_opdec[34:30], a5stg_opdec_9, a5stg_opdec_7,
a5stg_opdec_1, a5stg_opdec_0}),
.se (se),
.si (),
.so ()
);
dffe #(10) i_a5stg_id (
.din (a4stg_id[9:0]),
.en (a6stg_step),
.clk (rclk),
.q (a5stg_id[9:0]),
.se (se),
.si (),
.so ()
);
assign a5stg_fadd= a5stg_opdec[34];
assign a5stg_fixtos_fxtod= a5stg_opdec_7;
assign a5stg_fixtos= a5stg_opdec_1;
assign a5stg_fxtod= a5stg_opdec_0;
assign a6stg_opdec_in[34:30] = ({5{a5stg_fixtos_fxtod}}
& a5stg_opdec[34:30])
| ({5{((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))}}
& a4stg_opdec[34:30]);
assign a6stg_opdec_in_9 = (a5stg_fixtos_fxtod
& a5stg_opdec_9)
| (((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))
& a4stg_opdec_9);
assign a6stg_fadd_in= (a5stg_fixtos_fxtod && a6stg_step && (!reset)
&& a5stg_fadd)
|| ((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod)
&& a6stg_step && (!reset) && a4stg_fadd)
|| ((!a6stg_step) && (!reset) && a6stg_fadd);
dffre #(6) i_a6stg_opdec (
.din ({a6stg_opdec_in[34:30], a6stg_opdec_in_9}),
.en (a6stg_step),
.rst (reset),
.clk (rclk),
.q ({a6stg_opdec[34:30], a6stg_opdec_9}),
.se (se),
.si (),
.so ()
);
assign add_id_out_in[9:0]= ({10{((!a5stg_fixtos_fxtod) && a6stg_step)}}
& a4stg_id[9:0])
| ({10{(a5stg_fixtos_fxtod && a6stg_step)}}
& a5stg_id[9:0])
| ({10{(!a6stg_step)}}
& add_id_out[9:0]);
dff #(10) i_add_id_out (
.din (add_id_out_in[9:0]),
.clk (rclk),
.q (add_id_out[9:0]),
.se (se),
.si (),
.so ()
);
assign add_fcc_out_in[1:0]= ({2{a4stg_fcmpop}}
& a4stg_fcc);
dffe #(2) i_add_fcc_out (
.din (add_fcc_out_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (add_fcc_out[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- add pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign a6stg_fadd= a6stg_opdec[34];
assign a6stg_dbl_dst= a6stg_opdec[33];
assign a6stg_sng_dst= a6stg_opdec[32];
assign a6stg_long_dst= a6stg_opdec[31];
assign a6stg_int_dst= a6stg_opdec[30];
assign a6stg_fcmpop= a6stg_opdec_9;
assign a6stg_hold= a6stg_fadd && (!add_dest_rdy);
assign a6stg_step= (!a6stg_hold);
// Austin update
// Power management update
assign add_pipe_active_in = // add pipe is executing a valid instr
a1stg_fadd || a2stg_fadd || a3stg_fadd || a4stg_fadd || a5stg_fadd || a6stg_fadd;
dffre #(1) i_add_pipe_active (
.din (add_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (add_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign and exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_sub= (a1stg_fsubop ^ (a1stg_in1_63 ^ a1stg_in2_63))
&& (!a1stg_fdtos)
&& (!(a1stg_faddsubop && a1stg_nan_in));
dffe #(1) i_a2stg_sign1 (
.din (a1stg_in1_63),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sign1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_sign2 (
.din (a1stg_in2_63),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sign2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_sub (
.din (a1stg_sub),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_sub),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_in2_neq_in1_frac (
.din (a1stg_in2_neq_in1_frac),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_neq_in1_frac),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_in2_gt_in1_frac (
.din (a1stg_in2_gt_in1_frac),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_gt_in1_frac),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_in2_eq_in1_exp (
.din (a1stg_in2_eq_in1_exp),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_eq_in1_exp),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_in2_gt_in1_exp (
.din (a1stg_expadd1[11]),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_in2_gt_in1_exp),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_nan_in (
.din (a1stg_nan_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nan_in),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_nan_in2 (
.din (a1stg_nan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nan_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_snan_in2 (
.din (a1stg_snan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_qnan_in2 (
.din (a1stg_qnan_in2),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_snan_in1 (
.din (a1stg_snan_in1),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_qnan_in1 (
.din (a1stg_qnan_in1),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_2zero_in (
.din (a1stg_2zero_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_2zero_in),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a2stg_2inf_in (
.din (a1stg_2inf_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_2inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_in2_eq_in1= a2stg_in2_eq_in1_exp && (!a2stg_in2_neq_in1_frac);
assign a2stg_in2_gt_in1= a2stg_in2_gt_in1_exp
|| (a2stg_in2_eq_in1_exp && a2stg_in2_neq_in1_frac
&& a2stg_in2_gt_in1_frac);
assign a3stg_sub_in= a2stg_sub
&& (!a2stg_nan_in)
&& (!(a2stg_fsdtoix && (!a2stg_expadd[11])));
assign a2stg_faddsub_sign= (a2stg_sign1
&& (!a2stg_nan_in)
&& (a2stg_sign2 ^ a2stg_fsubop)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| (a2stg_sign1
&& (!a2stg_nan_in)
&& (!a2stg_in2_eq_in1)
&& (!a2stg_in2_gt_in1)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| ((!a2stg_in2_eq_in1)
&& a2stg_in2_gt_in1
&& (!a2stg_nan_in)
&& (a2stg_sign2 ^ a2stg_fsubop)
&& (!(a2stg_2inf_in && a2stg_sub)))
|| (a2stg_sign2
&& (a2stg_snan_in2
|| (a2stg_qnan_in2 && (!a2stg_snan_in1))))
|| (a2stg_sign1
&& ((a2stg_snan_in1 && (!a2stg_snan_in2))
|| (a2stg_qnan_in1 && (!a2stg_nan_in2))))
|| ((a2stg_rnd_mode[1:0]==2'b11)
&& a2stg_in2_eq_in1
&& (a2stg_sign1 ^ (a2stg_sign2 ^ a2stg_fsubop))
&& (!a2stg_nan_in)
&& (!a2stg_2inf_in));
assign a3stg_sign_in= (a2stg_faddsubop && a2stg_faddsub_sign)
|| ((!a2stg_faddsubop) && a2stg_sign2);
dffe #(1) i_a3stg_sign (
.din (a3stg_sign_in),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_sign),
.se (se),
.si (),
.so ()
);
assign a2stg_cc_1= ((a2stg_sign2 && (!a2stg_2zero_in) && a2stg_sub)
|| ((!a2stg_in2_eq_in1) && (!a2stg_sub)
&& (a2stg_in2_gt_in1 ^ (!a2stg_sign2)))
|| a2stg_nan_in)
&& a2stg_fcmpop;
assign a2stg_cc_0= (((!a2stg_sign2) && (!a2stg_2zero_in) && a2stg_sub)
|| ((!a2stg_in2_eq_in1) && (!a2stg_sub)
&& (a2stg_in2_gt_in1 ^ a2stg_sign2))
|| a2stg_nan_in)
&& a2stg_fcmpop;
assign a2stg_cc[1:0]= {a2stg_cc_1, a2stg_cc_0};
dffe #(2) i_a3stg_cc (
.din (a2stg_cc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_cc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_sign_in= (a3stg_f4cycop && a3stg_sign)
|| ((!a3stg_f4cycop) && a4stg_sign2);
dffe #(1) i_a4stg_sign (
.din (a4stg_sign_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_sign),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a4stg_sign2 (
.din (a3stg_sign),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_sign2),
.se (se),
.si (),
.so ()
);
dffe #(2) i_a4stg_cc (
.din (a3stg_cc[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_cc[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add sign logic.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_add_sign_out (
.din (a4stg_sign),
.en (a6stg_step),
.clk (rclk),
.q (add_sign_out),
.se (se),
.si (),
.so ()
);
assign add_cc_out_in[1:0]= ({2{a4stg_fcmpop}}
& a4stg_cc[1:0]);
dffe #(2) i_add_cc_out (
.din (add_cc_out_in[1:0]),
.en (a6stg_step),
.clk (rclk),
.q (add_cc_out[1:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_nv= (a1stg_faddsubop
&& ((a1stg_2inf_in && a1stg_sub)
|| a1stg_snan_in1
|| a1stg_snan_in2))
|| (a1stg_fstod && a1stg_snan_in2)
|| (a1stg_fdtos && a1stg_snan_in2)
|| (a1stg_fcmpesd && a1stg_nan_in)
|| (a1stg_fcmpsd
&& (a1stg_snan_in1 || a1stg_snan_in2));
dffe #(1) i_a2stg_nv (
.din (a1stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_nv),
.se (se),
.si (),
.so ()
);
assign a1stg_of_mask= (!(a1stg_faddsub_dtosop && a1stg_infnan_in));
dffe #(1) i_a2stg_of_mask (
.din (a1stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_nv_in= ((!a2stg_expadd[11])
&& a2stg_fsdtoix
&& ((!a2stg_sign2)
|| (|a2stg_expadd[10:0])
|| a2stg_frac2hi_neq_0
|| (a2stg_long_dst && a2stg_frac2lo_neq_0)))
|| a2stg_nv;
dffe #(1) i_a3stg_nv (
.din (a3stg_nv_in),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a3stg_of_mask (
.din (a2stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_of_mask),
.se (se),
.si (),
.so ()
);
assign a2stg_nx_tmp1= (a2stg_fdtoix && (|a2stg_exp[11:10]))
|| (a2stg_fstoix && (|a2stg_exp[11:7]));
assign a2stg_nx_tmp2= ((a2stg_fdtoix && (!(|a2stg_exp[11:10])))
|| (a2stg_fstoix && (!(|a2stg_exp[11:7]))))
&& ((|a2stg_exp[10:1])
|| a2stg_frac2hi_neq_0
|| a2stg_frac2lo_neq_0
|| a2stg_frac2_63);
assign a2stg_nx_tmp3= (a2stg_exp[11:0]==12'h41f)
&& a2stg_sign2
&& (!a2stg_frac2hi_neq_0)
&& a2stg_frac2lo_neq_0
&& a2stg_fdtoi;
dffe #(1) i_a3stg_a2_expadd_11 (
.din (a2stg_expadd[11]),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_a2_expadd_11),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a3stg_nx_tmp1 (
.din (a2stg_nx_tmp1),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a3stg_nx_tmp2 (
.din (a2stg_nx_tmp2),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a3stg_nx_tmp3 (
.din (a2stg_nx_tmp3),
.en (a6stg_step),
.clk (rclk),
.q (a3stg_nx_tmp3),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_nx= (a3stg_a2_expadd_11
&& ((a3stg_nx_tmp1
&& ((a3stg_fsdtoi_nx && a3stg_int_dst)
|| a3stg_fsdtoix_nx))
|| a3stg_nx_tmp2))
|| a3stg_nx_tmp3;
assign a4stg_nv_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_nv)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_nv2);
dffe #(1) i_a4stg_nv (
.din (a4stg_nv_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nv),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a4stg_nv2 (
.din (a3stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nv2),
.se (se),
.si (),
.so ()
);
assign a4stg_of_mask_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_of_mask)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_of_mask2);
dffe #(1) i_a4stg_of_mask (
.din (a4stg_of_mask_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_of_mask),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a4stg_of_mask2 (
.din (a3stg_of_mask),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_of_mask2),
.se (se),
.si (),
.so ()
);
assign a4stg_nx_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
&& a3stg_nx)
|| ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
&& a4stg_nx2);
dffe #(1) i_a4stg_nx (
.din (a4stg_nx_in),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nx),
.se (se),
.si (),
.so ()
);
dffe #(1) i_a4stg_nx2 (
.din (a3stg_nx),
.en (a6stg_step),
.clk (rclk),
.q (a4stg_nx2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add exception logic.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_add_nv_out (
.din (a4stg_nv),
.en (a6stg_step),
.clk (rclk),
.q (add_nv_out),
.se (se),
.si (),
.so ()
);
assign a4stg_in_of= ((a4stg_exp[11] || (&a4stg_exp[10:0]))
&& a4stg_faddsubd
&& a4stg_of_mask)
|| (((|a4stg_exp[11:8]) || (&a4stg_exp[7:0]))
&& a4stg_faddsubs_fdtos
&& a4stg_of_mask);
assign add_of_out_tmp1_in= ((&a4stg_exp[10:1]) && a4stg_rndup && a4stg_round
&& a4stg_faddsubd
&& a4stg_of_mask)
|| ((&a4stg_exp[7:1]) && a4stg_rndup
&& (a4stg_round || a4stg_fdtos)
&& a4stg_faddsubs_fdtos
&& a4stg_of_mask);
dffe #(1) i_add_of_out_tmp1 (
.din (add_of_out_tmp1_in),
.en (a6stg_step),
.clk (rclk),
.q (add_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_add_of_out_tmp2 (
.din (a4stg_in_of),
.en (a6stg_step),
.clk (rclk),
.q (add_of_out_tmp2),
.se (se),
.si (),
.so ()
);
assign add_of_out= add_of_out_tmp2
|| (add_of_out_tmp1 && add_of_out_cout);
assign a4stg_uf= ((!(|a4stg_exp[10:0]))
&& a4stg_frac_neq_0
&& (a4stg_round || a4stg_fdtos)
&& a4stg_faddsub_dtosop)
|| (a4stg_faddsubop
&& (!(a4stg_round || a4stg_fdtos))
&& (!a4stg_denorm_inv)
&& a4stg_shl_data_neq_0);
dffe #(1) i_add_uf_out (
.din (a4stg_uf),
.en (a6stg_step),
.clk (rclk),
.q (add_uf_out),
.se (se),
.si (),
.so ()
);
assign add_nx_out_in= (a4stg_of_mask
&& a4stg_frac_dbl_nx
&& (a4stg_faddsubd || a5stg_fxtod)
&& ((!a4stg_faddsubd) || a4stg_round))
|| (a4stg_of_mask
&& a4stg_frac_sng_nx
&& (a4stg_faddsubs_fdtos || a5stg_fixtos)
&& ((!a4stg_faddsubs) || a4stg_round))
|| a4stg_nx;
dffe #(1) i_add_nx_out (
.din (add_nx_out_in),
.en (a6stg_step),
.clk (rclk),
.q (add_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign add_exc_out[4:0]= {add_nv_out, add_of_out, add_uf_out, 1'b0, add_nx_out};
assign add_exc_out[4:0] =
{add_nv_out,
add_of_out,
add_uf_out,
1'b0,
(add_nx_out || add_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Add pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add normalization and special input injection.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_frac1_in_frac1= a1stg_snan_in2
|| (a1stg_qnan_in2 && (!a1stg_snan_in1));
assign a2stg_frac1_in_frac2= a1stg_faddsubop
&& ((!a1stg_2nan_in)
|| a1stg_snan_in2
|| (a1stg_qnan_in2 && (!a1stg_snan_in1)));
assign a1stg_2nan_in_inv= (!a1stg_2nan_in);
assign a1stg_faddsubop_inv= (!a1stg_faddsubop);
assign a2stg_frac1_in_qnan= (a1stg_nan_in
|| (a1stg_2inf_in && a1stg_sub))
&& a1stg_faddsubop;
assign a2stg_frac1_in_nv= a1stg_2inf_in && a1stg_sub && a1stg_faddsubop;
assign a2stg_frac1_in_nv_dbl= a1stg_2inf_in && a1stg_sub && a1stg_faddsubd;
assign a2stg_frac2_in_frac1= a1stg_faddsubop && (!a1stg_infnan_in);
assign a2stg_frac2_in_qnan= a1stg_snan_in2 && (!a1stg_faddsubop);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe right shift count
// count calculation.
//
// Add stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_exp_diff_add1= a1stg_faddsub_dtosop && (!a1stg_expadd1[11]);
assign a1stg_exp_diff_add2= a1stg_faddsubop && a1stg_expadd1[11];
assign a1stg_exp_diff_5= (!a1stg_expadd2[5]) && a1stg_fsdtox;
assign a1stg_exp_diff[10:0]= ({11{a1stg_exp_diff_add1}}
& a1stg_expadd1[10:0])
| ({11{a1stg_exp_diff_add2}}
& (~a1stg_expadd4_inv[10:0]))
| ({11{a1stg_fsdtoix}}
& {5'b0, a1stg_exp_diff_5, (~a1stg_expadd2[4:0])});
assign a1stg_clamp63[5:0]= a1stg_exp_diff[5:0] | {6{(|a1stg_exp_diff[10:6])}};
assign a2stg_shr_cnt_in[5:0]= a1stg_clamp63[5:0];
assign a2stg_shr_cnt_5_inv_in= (!a1stg_clamp63[5]);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe right shift.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_shr_frac2_shr_int= a2stg_faddsub_dtosop && a6stg_step;
assign a2stg_shr_frac2_shr_dbl= ((a2stg_fdtox && (|a2stg_exp[11:10]))
|| (a2stg_fstox && (|a2stg_exp[11:7])))
&& a6stg_step;
assign a2stg_shr_frac2_shr_sng= ((a2stg_fdtoi && (|a2stg_exp[11:10]))
|| (a2stg_fstoi && (|a2stg_exp[11:7])))
&& a6stg_step;
assign a2stg_shr_frac2_max= a2stg_fsdtoix && a6stg_step;
assign a2stg_sub_step= a2stg_sub && a6stg_step;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe adder.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a1stg_faddsub_clamp63_0= (|(({6{a1stg_expadd1[11]}}
& (~{a1stg_expadd4_inv[10:6],
a1stg_expadd4_inv[0]}))
| ({6{(!a1stg_expadd1[11])}}
& {a1stg_expadd1[10:6], a1stg_expadd1[0]})));
assign a2stg_fracadd_frac2_inv_in= (a1stg_fixtosd && a1stg_in2_63)
|| (a1stg_faddsubop && a1stg_sub
&& (!a1stg_faddsub_clamp63_0));
assign a2stg_fracadd_frac2_inv_shr1_in= a1stg_faddsubop && a1stg_sub
&& a1stg_faddsub_clamp63_0;
assign a2stg_fracadd_frac2_in= (a1stg_fixtosd && (!a1stg_in2_63))
|| a1stg_fstod
|| (a1stg_faddsubop && (!a1stg_sub));
dffe #(1) i_a2stg_fracadd_frac2 (
.din (a2stg_fracadd_frac2_in),
.en (a6stg_step),
.clk (rclk),
.q (a2stg_fracadd_frac2),
.se (se),
.si (),
.so ()
);
assign a2stg_fracadd_cin_in= (a1stg_fixtosd && a1stg_in2_63)
|| (a1stg_faddsubop && a1stg_sub);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe exponent adjustment.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_exp_7ff= a2stg_fstod && (&a2stg_exp[7:0]);
assign a3stg_exp_ff= a2stg_fdtos && (&a2stg_exp[10:0]);
assign a3stg_exp_add= (a2stg_fstod && (!(&a2stg_exp[7:0])))
|| (a2stg_fdtos && (!(&a2stg_exp[10:0])));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- add pipe exponent decode- used to identify denorm results.
//
// Add stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign a2stg_expdec_neq_0= a2stg_faddsubop && (a2stg_exp[10:0]<11'h36);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic
// - add pipe main adder
// - add pipe exponent increment/decrement adjustment
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a3stg_exp10_0_eq0= (a3stg_exp[10:0]==11'b0);
assign a3stg_exp10_1_eq0= (a3stg_exp[10:1]==10'b0);
assign a3stg_fdtos_inv= (!a3stg_fdtos);
assign a4stg_fixtos_fxtod_inv= (!a4stg_fixtos_fxtod);
assign a4stg_rnd_frac_add_inv= (!(a3stg_fsdtoix
|| (a3stg_faddsubop && a3stg_exp10_0_eq0)));
///////////////////////////////////////////////////////////////////////////////
//
// Control logic- add pipe left shift count.
//
// Add stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_shl_cnt_in[9:0]= ({10{a3stg_denorm}}
& {(a3stg_exp[5:4]==2'b11),
(a3stg_exp[5:4]==2'b10),
(a3stg_exp[5:4]==2'b01),
(a3stg_exp[5:4]==2'b00),
a3stg_exp[5:0]})
| ({10{a3stg_denorm_inv}}
& {(a3stg_lead0[5:4]==2'b11),
(a3stg_lead0[5:4]==2'b10),
(a3stg_lead0[5:4]==2'b01),
(a3stg_lead0[5:4]==2'b00),
a3stg_lead0[5:0]});
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe rounding adder.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_rnd_sng= a5stg_fixtos || a4stg_faddsubs_fdtos;
assign a4stg_rnd_dbl= a5stg_fxtod || a4stg_faddsubd;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe fraction output.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign a4stg_rndup_sng= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
&& a4stg_frac_sng_nx)
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign
&& a4stg_frac_sng_nx)
|| ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_39
&& (a4stg_frac_38_0_nx || a4stg_rnd_frac_40));
assign a4stg_rndup_dbl= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
&& a4stg_frac_dbl_nx)
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign
&& a4stg_frac_dbl_nx)
|| ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_10
&& (a4stg_frac_9_0_nx || a4stg_rnd_frac_11));
assign a4stg_rndup= (a4stg_faddsubd && a4stg_rndup_dbl)
|| (a4stg_faddsubs && a4stg_rndup_sng)
|| (a4stg_fdtos && a4stg_rndup_sng && a4stg_of_mask);
assign a5stg_rndup= (a5stg_fxtod && a4stg_rndup_dbl)
|| (a5stg_fixtos && a4stg_rndup_sng);
assign add_frac_out_rndadd= (a4stg_faddsubop && a4stg_round && a4stg_rndup
&& (!a4stg_in_of))
|| (a4stg_fdtos && a4stg_rndup && (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && a5stg_rndup);
assign add_frac_out_rnd_frac= (a4stg_faddsubop && a4stg_round && (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a4stg_fdtos && (!a4stg_rndup) && (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && (!a5stg_rndup))
|| a4stg_fsdtoix;
assign add_frac_out_shl= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
|| a4stg_fistod;
assign a4stg_to_0= (!((a4stg_rnd_mode==2'b00)
|| ((a4stg_rnd_mode==2'b10) && (!a4stg_sign))
|| ((a4stg_rnd_mode==2'b11) && a4stg_sign)));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines and control logic- add pipe exponent output.
//
// Add stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign add_exp_out_expinc= (a4stg_faddsubop && a4stg_round && a4stg_rndup
&& (!a4stg_in_of))
|| (a4stg_fdtos && a4stg_rndup
&& (!a4stg_in_of))
|| (a5stg_fixtos_fxtod && a5stg_rndup);
assign add_exp_out_exp= (a4stg_faddsubop && a4stg_round
&& (!a4stg_in_of))
|| (a4stg_fdtos
&& (!a4stg_in_of))
|| a5stg_fixtos_fxtod;
assign add_exp_out_exp1= (a4stg_faddsubop && a4stg_round
&& (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a4stg_fdtos
&& (!a4stg_rndup)
&& (!a4stg_in_of))
|| (a5stg_fixtos_fxtod
&& (!a5stg_rndup));
assign add_exp_out_expadd= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
|| a4stg_fistod;
assign a4stg_to_0_inv= (!a4stg_to_0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.