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11942458 | DETAILED DESCRIPTION OF THE EMBODIMENTS Semiconductor packages according to the present inventive concepts will be described hereinafter with reference to the accompanying drawings. FIG.1illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts.FIG.2illustrates an enlarged view of a region ‘A’ ofFIG.1.FIG.3illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the FIG. inventive concepts. Referring toFIGS.1and2, a first package substrate100may be provided. The first package substrate100may include one or more substrate interconnection layers sequentially stacked. Each of the substrate interconnection layers may include a first substrate insulating layer110and a first substrate interconnection pattern120in the first substrate insulating layer110. The first substrate interconnection pattern120of one substrate interconnection layer may be electrically connected to the first substrate interconnection pattern120of another substrate interconnection layer adjacent thereto. As used herein, items described as being “electrically connected” are configured such that an electrical signal can be passed from one item to the other. Therefore, a passive electrically conductive component (e.g., a wire, pad, internal electrical line, etc.) physically connected to a passive electrically insulative component (e.g., a prepreg layer of a printed circuit board, an electrically insulative adhesive connecting two device, an electrically insulative underfill or mold layer, etc.) is not electrically connected to that component. Moreover, items that are “directly electrically connected,” to each other are electrically connected through one or more passive elements, such as, for example, wires, pads, internal electrical lines, through vias, etc. As such, directly electrically connected components do not include components electrically connected through active elements, such as transistors or diodes. Directly electrically connected elements may be directly physically connected and directly electrically connected. The first substrate insulating layer110may include or be formed of an insulating polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric (PID) may include or be formed of at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. The first substrate interconnection pattern120may be provided in the first substrate insulating layer110. The first substrate interconnection pattern120may have a damascene structure. For example, the first substrate interconnection pattern120may include a head portion and a tail portion which are connected to each other in one body. For example, the head portion and the tail portion of the first substrate interconnection pattern120may be integrally formed by the same process. The head portion may be an interconnection portion or pad portion horizontally extending in the first package substrate100. A horizontal direction in this disclosure may be a direction parallel a top surface of the first package substrate100. The tail portion may be a via portion vertically extending and connecting interconnection lines (e.g., the interconnection portion(s) and/or the pad portion(s)) in the first package substrate100. The first substrate interconnection pattern120may have a T-shaped cross section. A top surface of the first substrate interconnection pattern120(i.e., a top surface of the head portion of the first substrate interconnection pattern120) may be exposed at a top surface of the first substrate insulating layer110. The head portion of the first substrate interconnection pattern120of an uppermost one of the substrate interconnection layers may correspond to a first substrate pad122for mounting a semiconductor chip on the first package substrate100. A bottom surface of the first substrate interconnection pattern120(i.e., a bottom surface of the tail portion of the first substrate interconnection pattern120) may be exposed at a bottom surface of the first substrate insulating layer110. The tail portion may be electrically/directly connected to the head portion of the first substrate interconnection pattern120of the substrate interconnection layer disposed thereunder. The first substrate interconnection pattern120may include or be formed of a conductive material. For example, the first substrate interconnection pattern120may include or be formed of copper (Cu). Even though not shown in the drawings, a barrier layer may be disposed between the first substrate insulating layer110and the first substrate interconnection pattern120. The barrier layer may conformally cover a side surface and a bottom surface of the first substrate interconnection pattern120. A gap between the first substrate interconnection pattern120and the first substrate insulating layer110(i.e., a thickness of the barrier layer) may range from 50 Å to 1000 Å. The barrier layer may include or be formed of a metal such as titanium (Ti) or tantalum (Ta) and/or may include or be formed of a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN). A second substrate pad124may be provided under a lowermost one of the substrate interconnection layers. The second substrate pad124may be electrically/directly connected to the first substrate interconnection pattern120. The second substrate pad124may include or be formed of a conductive material. For example, the second substrate pad124may include or be formed of copper (Cu). A substrate passivation layer130may be provided under the lowermost substrate interconnection layer. The substrate passivation layer130may cover the whole of a bottom surface of the first package substrate100, e.g., on which second substrate pads124are not formed. For example, the second substrate pads124may be exposed at a bottom surface of the substrate passivation layer130. External terminals140may be provided on the exposed second substrate pads124, respectively. The external terminals140may include or may be solder balls or solder bumps. A first device200and a second device300may be disposed on the first package substrate100. The first device200may be disposed on a top surface of the first package substrate100. The first device200may be a semiconductor chip. For example, the first device200may be a memory chip. Alternatively, the first device200may be a logic chip. The first device200may be disposed face-up on the first package substrate100. For example, the first device200may have a back surface200bfacing the first package substrate100and a front surface200aopposite to the back surface200b. In the present specification, the front surface may be a surface correspond to an active surface of an integrated device in a semiconductor chip and may be defined as a surface on which pads of the semiconductor chip are formed. The back surface may be defined as another surface opposite to the front surface. For example, the front surface200aof the first device200may be an active surface of the semiconductor chip and the back surface200bof the semiconductor chip may be an opposite surface to the active surface. The first device200may include a first base layer210, a first circuit layer220and a first passivation layer230provided on both surfaces of the first base layer210, respectively, and at least one first via240penetrating the first base layer210. The first base layer210may include or be formed of silicon (Si). An integrated device or integrated circuits may be formed in an upper portion of the first base layer210. The first circuit layer220may be provided on a top surface of the first base layer210. The first circuit layer220may be electrically connected to the integrated device or integrated circuits formed in the first base layer210. For example, the first circuit layer220may include a first circuit pattern224provided in a first insulating pattern222, and the first circuit pattern224may be electrically/directly connected to the integrated device or integrated circuits formed in the first base layer210. A portion of the first circuit pattern224may be exposed at a top surface of the first circuit layer220, and the exposed portion of the first circuit pattern224may correspond to a first chip pad224of the first device200(hereinafter, the first chip pad and the first circuit pattern will be indicated by the same reference numeral ‘224’ for the purpose of ease and convenience in explanation, e.g., the first chip pad may be a portion of the first circuit pattern224). A top surface200a(i.e., the front surface) of the first device200, at which the first circuit layer220is provided, may be an active surface of the first device200. The first passivation layer230may be provided on a bottom surface of the first base layer210. The first passivation layer230may include or be formed of an insulating material. For example, the first passivation layer230may include or be formed of silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON). The first via240may vertically penetrate the first base layer210and the first passivation layer230. One end of the first via240may be exposed at a bottom surface of the first passivation layer230. A bottom surface of the first via240may be coplanar with the bottom surface of the first passivation layer230(e.g., the back surface200bof the first device200). The bottom surface of the first via240and the bottom surface of the first passivation layer230may be substantially flat. The first via240may extend toward the front surface200aof the first device200from the one end of the first via240. Another end of the first via240may be electrically/directly connected to the first circuit layer220. The first via240may be electrically/directly connected to the first circuit pattern224of the first circuit layer220. Terms such as “same,” “equal,” “planar,” “flat,” or “coplanar,” as used herein encompass identically or near identically including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. The first device200may be mounted on the first package substrate100. For example, the first passivation layer230of the first device200may face the first package substrate100. Here, a first chip terminal (or a first connection terminal)250may be provided under the first via240of the first device200. The first device200may be mounted on the first package substrate100through the first chip terminal250. The first chip terminal250may electrically connect the first via240of the first device200to the first substrate pad122of the first package substrate100. For example, the first chip terminal250may contact the first via240and the first substrate pad122. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. In certain embodiments, an additional chip pad may further be provided on the bottom surface of the first device200as necessary. The additional chip pad may be provided on the bottom surface of the first passivation layer230to be electrically/directly connected to the first via240. In this case, the first chip terminal250may be provided on the additional chip pad and may electrically/directly connect the additional chip pad to the first substrate pad122. A first chip bump260may be provided on the front surface200aof the first device200. The first chip bump260may be electrically connected to the first circuit layer220. For example, the first chip bump260may be electrically connected to and/or contact the exposed first chip pad224of the first circuit pattern224. A thickness of the first chip bump260may range from 0.1 mm to 10 mm. A width of the first chip bump260in a horizontal direction may be substantially uniform from its bottom to its top. The first chip bump260may include or be formed of copper (Cu). Even though not shown in the drawings, the first chip bump260may further include a seed layer. The seed layer may cover a bottom surface of the first chip bump260. The seed layer may be disposed between the first chip bump260and the first circuit pattern224of the first device200. Alternatively, the seed layer may cover the bottom surface and side surfaces of the first chip bump260. The seed layer may extend from between the first chip bump260and the first circuit pattern224of the first device200onto the side surfaces of the first chip bump260. The second device300may be disposed on the top surface of the first package substrate100. The second device300may be laterally spaced apart from the first device200. The second device300may include or may be a passive device. For example, the second device300may include or may be a capacitor, a resistor, or a combination thereof. The second device300may be disposed face-up on the first package substrate100. For example, the second device300may have a back surface300bfacing the first package substrate100and a front surface300aopposite to the back surface300b. The second device300may include a second base layer310and a second circuit layer320provided on a top surface of the second base layer310. The second base layer310may include silicon (Si). The passive device may be formed in an upper portion of the second base layer310. The second circuit layer320may be provided on the top surface of the second base layer310. The second circuit layer320may be electrically connected to the passive device formed in the second base layer310. For example, the second circuit layer320may include a second circuit pattern provided in a second insulating pattern, and the second circuit pattern may be electrically connected to and/or contact the passive device formed in the second base layer310. A portion of the second circuit pattern may be exposed at a top surface of the second circuit layer320, and the exposed portion of the second circuit pattern may correspond to a second chip pad of the second device300. A top surface300a(i.e., the front surface) of the second device300, at which the second circuit layer320is provided, may be an active surface of the second device300. A second chip bump360may be provided on the front surface300aof the second device300. The second chip bump360may be electrically connected to the second circuit layer320. For example, the second chip bump360may be electrically connected to and/or contact the exposed second chip pad of the second circuit pattern. A thickness of the second chip bump360may range from 0.1 mm to 10 mm. The second chip bump360may include or be formed of copper (Cu). The second device300may be adhered to the first package substrate100. For example, the second device300may be adhered to the top surface of the first package substrate100by using an adhesive film370. The adhesive film370may be provided on a bottom surface of the second base layer310of the second device300. For example, the adhesive film370may be formed of an inorganic adhesive or a polymer adhesive. For example, the polymer adhesive may include or may be a thermosetting polymer or a thermoplastic polymer. A first molding part410may be provided on the first package substrate100. The first molding part410may cover the top surface of the first package substrate100. The first molding part410may surround the first device200and the second device300, e.g., in a plan view. The first molding part410may cover/contact side surfaces of the first device200and side surfaces of the second device300and may cover/contact the front surface200aof the first device200and the front surface300aof the second device300. The first molding part410may surround the first chip bump260and the second chip bump360but may expose a top surface of the first chip bump260and a top surface of the second chip bump360. A top surface of the first molding part410may be coplanar with the top surface of the first chip bump260and the top surface of the second chip bump360. A bottom surface of the first molding part410may be lower than the bottom surface of the first device200and the bottom surface of the second device300. The first molding part410may include or be formed of an insulating material such as an epoxy molding compound (EMC). A first through-electrode420may be provided on the first package substrate100. The first through-electrode420may be disposed at a side of the first device200, at a side of the second device300, and/or between the first device200and the second device300. For the purpose of ease and convenience in explanation, the first through-electrode420disposed at a side of the first device200or the second device300may be defined as a first sub-through-electrode422, and the first through-electrode420disposed between the first and second devices200and300may be defined as a second sub-through-electrode424. The first sub-through-electrode422may be disposed at a side of a third device600to be described later when viewed in a plan view, and the second sub-through-electrode424may be disposed under the third device600to be described later. The first through-electrode420may vertically penetrate the first molding part410. The first through-electrode420may extend toward the first package substrate100and an end of the first through-electrode420may be connected to the first substrate interconnection pattern120of the first package substrate100. A bottom surface of the first through-electrode420may be coplanar with the bottom surface of the first molding part410. Another end of the first through-electrode420may be exposed at the top surface of the first molding part410. A top surface of the first through-electrode420may be coplanar with the top surface of the first molding part410, the top surface of the first chip bump260and the top surface of the second chip bump360. A width of the first through-electrode420in a horizontal direction may decrease in a direction approaching the first package substrate100. Alternatively, the width of the first through-electrode420may be substantially uniform from its bottom to its top. A redistribution layer500may be provided on the first molding part410. The redistribution layer500may include a plurality of stacked redistribution regions (e.g., sublayers). Each of the redistribution regions may include a redistribution insulating pattern510and a redistribution pattern520provided in the redistribution insulating pattern510. The redistribution pattern520of one redistribution region may be electrically connected to the redistribution pattern520of another redistribution region adjacent thereto. A lowermost redistribution pattern522of a lowermost redistribution region may be exposed at a bottom surface of the lowermost redistribution insulating pattern510, and the exposed portion of the lowermost redistribution pattern522may correspond to a first redistribution pad522of the redistribution layer500(hereinafter, the first redistribution pad and the lowermost redistribution pattern are indicated by the same reference numeral ‘522’ for the purpose of ease and convenience in explanation). An uppermost redistribution pattern524of an uppermost redistribution region may be exposed at a top surface of the redistribution insulating pattern510, and the exposed portion of the uppermost redistribution pattern524may correspond to a second redistribution pad524of the redistribution layer500(hereinafter, the second redistribution pad and the uppermost redistribution pattern are indicated by the same reference numeral ‘524’ for the purpose of ease and convenience in explanation). The redistribution layer500may be electrically connected to the first device200, the second device300, and the first through-electrode420. For example, the first chip bump260, the second chip bump360and the first through-electrode420may be electrically/directly connected to tail portions of the first redistribution pads522of the redistribution layer500. The first redistribution pads522of the redistribution layer500may be in contact with the first chip bump260, the second chip bump360and the first through-electrode420. The redistribution layer500may be electrically/directly connected to the first device200through the first chip bump260, may be electrically/directly connected to the second device300through the second chip bump360and may be electrically/directly connected to the first package substrate100through the first through-electrode420. The first device200is disposed face-up inFIG.1. However, embodiments of the inventive concepts are not limited thereto. As illustrated inFIG.3, a semiconductor package12may include a first device200disposed face-down on the first package substrate100. For example, the first device200may have a front surface facing the first package substrate100and a back surface opposite to the front surface. An integrated device or integrated circuits may be formed in a lower portion of a first base layer210. A first circuit layer220may be provided on a bottom surface of the first base layer210. The first circuit layer220may be electrically connected to the integrated device or integrated circuits formed in the first base layer210. A bottom surface (i.e., the front surface) of the first device200, at which the first circuit layer220is provided, may be an active surface of the first device200. A portion of the first circuit pattern224may be exposed at a bottom surface of the first circuit layer220, and the exposed portion of the first circuit pattern224of the first circuit layer220may correspond to a pad of the first device200. A first passivation layer230may be provided on a top surface of the first base layer210. The first via240may vertically penetrate the first base layer210and the first passivation layer230. One end of the first via240may be exposed at a top surface of the first passivation layer230. The first device200may be mounted on the first package substrate100. For example, the first circuit layer220of the first device200may face the first package substrate100. Here, a first chip terminal255may be provided under the first circuit pattern224of the first device200. The first device200may be mounted on the first package substrate100through the first chip terminal255. The first chip terminal255may electrically connect the first circuit pattern224of the first device200to the first substrate pad122of the first package substrate100. For example, the first chip terminal255may contact the first circuit pattern224at its top end and may contact the first substrate pad122at its bottom end. A first molding part410may be provided on the first package substrate100. The first molding part410may surround the first device200and the second device300, e.g., in a plan view. The first molding part410may cover side surfaces of the first device200and side surfaces of the second device300and may cover the front surface300aof the second device300. A top surface of the first molding part410may be coplanar with a top surface of the first device200. The top surface of the first molding part410may be coplanar with the top surface of the second chip bump360. The redistribution layer500may be electrically connected to the first device200, the second device300, and the first through-electrode420. For example, the first via240of the first device200, the second chip bump360of the second device300and the first through-electrode420may be electrically connected to and/or contact the redistribution patterns520of the lowermost redistribution region (e.g., sub-layer) of the redistribution layer500. Hereinafter, the embodiments ofFIGS.1and2will be described continuously as examples. Referring again toFIGS.1and2, a third device600may be disposed on the redistribution layer500. The third device600may be disposed on a top surface of the redistribution layer500. The third device600may be a semiconductor chip. For example, the third device600may be a logic chip. The third device600may include or may be a processing unit such as a central processing unit (CPU), a graphic processing unit (GPU), or a neural processing unit (NPU). The third device600may be disposed face-down on the redistribution layer500. For example, the third device600may have a front surface facing the redistribution layer500and a back surface opposite to the front surface. The third device600may vertically overlap with the first device200and the second device300. For example, the third device600may cover the first device200and the second device300, e.g., in a plan view. A width of the third device600may be greater than a width of the first device200and a width of the second device300. The width of the third device600may be greater than a sum of the width of the first device200and the width of the second device300. However, embodiments of the inventive concepts are not limited thereto. In certain embodiments, the sum of the width of the first device200and the width of the second device300may be greater than the width of the third device600. The third device600may include a third base layer610and a third circuit layer620provided on a surface of the third base layer610. The third base layer610may include or be formed of silicon (Si). An integrated device or integrated circuits may be formed in a lower portion of the third base layer610. The third circuit layer620may be provided on a bottom surface of the third base layer610. The third circuit layer620may be electrically connected to the integrated device or integrated circuits formed in the third base layer610. For example, the third circuit layer620may include a third circuit pattern624provided in a third insulating pattern622, and the third circuit pattern624may be electrically/directly connected to the integrated device or integrated circuits formed in the third base layer610. A portion of the third circuit pattern624may be exposed at a bottom surface of the third circuit layer620, and the exposed portion of the third circuit pattern624may correspond to a third chip pad624of the third device600(hereinafter, the third chip pad and the third circuit pattern will be indicated by the same reference numeral ‘624’ for the purpose of ease and convenience in explanation). A bottom surface (i.e., the front surface) of the third device600, at which the third circuit layer620is provided, may be an active surface of the third device600. The third device600may be mounted on the redistribution layer500. For example, the third circuit layer620of the third device600may face the redistribution layer500. Here, a second chip terminal (or a second connection terminal)650may be provided under the exposed third chip pad624of the third circuit pattern624of the third device600. The third device600may be mounted on the redistribution layer500through the second chip terminal650. The second chip terminal650may electrically connect the third chip pad624of the third device600to the second redistribution pad524of the redistribution layer500. For example, the second chip terminal650may contact the third chip pad624on its top surface and may contact the second redistribution pad524on its bottom surface. The third device600may be electrically/directly connected to the first device200and the second device300through the second chip terminals650and the redistribution layer500. The third device600may be electrically/directly connected to the first package substrate100through the second chip terminal650, the redistribution layer500and the second sub-through-electrode424. According to the embodiments of the inventive concepts, the first device200, the second device300and the third device600may be mounted directly and/or electrically connected to the redistribution layer500, e.g., without using wire bonding, e.g., with flip-chip bonding method. For example, the active surface of the first device200and the active surface of the second device300may face the active surface of the third device600, and the first device200and the second device300may be electrically/directly connected to the third device600by using only the redistribution layer500. Thus, electrical connection distances between the third device600and the first and second devices200and300may be reduced or shortened (e.g., comparing with other connection structures/methods), and electrical characteristics of a semiconductor package10may be improved. In addition, the third device600may be connected directly/electrically to the first package substrate100by using the first through-electrode420, and thus an electrical connection distance between the third device600and the first package substrate100may be shortened. For example, the third device600may be electrically connected to the first package substrate100through the first through-electrode420without any intervening semiconductor chips in the electrical signal path therebetween. Furthermore, the first and second devices200and300having small sizes may be disposed under the third device600having a large size, and thus an area required for arrangement of the first to third devices200,300and600may be reduced. As a result, a small semiconductor package may be realized. A second molding part430may be provided on the redistribution layer500. The second molding part430may cover the top surface of the redistribution layer500. The second molding part430may surround the third device600, e.g., in a plan view. The second molding part430may cover side surfaces of the third device600and may cover the back surface of the third device600. The second molding part430may include or be formed of an insulating material such as an epoxy molding compound (EMC). A second through-electrode440may be provided on the redistribution layer500. The second through-electrode440may be disposed at a side of the third device600. The second through-electrode440may vertically penetrate the second molding part430. The second through-electrode440may extend toward the redistribution layer500to be electrically connected to the redistribution pattern520of the redistribution layer500. For example, and end of the second through-electrode440may contact the redistribution pattern520. A bottom surface of the second through-electrode440may be coplanar with a bottom surface of the second molding part430. Another end of the second through-electrode440may be exposed at a top surface of the second molding part430. A top surface of the second through-electrode440may be coplanar with the top surface of the second molding part430. A width of the second through-electrode440may decrease in a direction approaching the redistribution layer500. Alternatively, the width of the second through-electrode440may be substantially uniform from its bottom to its top. The second through-electrode440may be electrically/directly connected to the first package substrate100through the redistribution layer500and the first sub-through-electrode422. A second package substrate700may be provided on the second molding part430. The second package substrate700may include or be formed of one or more substrate interconnection layers sequentially stacked. Each of the substrate interconnection layers may include a second substrate insulating layer710and a second substrate interconnection pattern720in the second substrate insulating layer710. The second substrate interconnection pattern720of one substrate interconnection layer may be electrically connected to the second substrate interconnection pattern720of another substrate interconnection layer adjacent thereto. The second substrate insulating layer710may include or be formed of an insulating polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric (PID) may include at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. The second substrate interconnection pattern720may be provided in the second substrate insulating layer710. The second substrate interconnection pattern720may have a damascene structure. For example, the second substrate interconnection pattern720may have a T-shaped cross section. The second substrate interconnection pattern720of a lowermost one of the substrate interconnection layers may be electrically connected to and/or contact the second through-electrode440. The second substrate interconnection pattern720may include or be formed of a conductive material. For example, the second substrate interconnection pattern720may include or be formed of copper (Cu). The second package substrate700may be omitted as necessary. The semiconductor package10may be provided as described above. FIG.4illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.4, a semiconductor package14may not include the redistribution layer500ofFIG.1. An intermediate layer550may be disposed between the first molding part410and the second molding part430. The intermediate layer550may include an intermediate insulating layer540and intermediate pads530. The intermediate pads530may be disposed on the top surface of the first molding part410. The intermediate pads530may be electrically/directly connected to the first device200, the second device300and the first through-electrodes420. For example, a first intermediate pad of the intermediate pads530may be located on the first chip bump260of the first device200. A second intermediate pad of the intermediate pads530may be located on the second chip bump360of the second device300. A third intermediate pad of the intermediate pads530may be located on the first through-electrode420. The intermediate pads530may include or be formed of a conductive material such as copper (Cu). Even though not shown in the drawings, a seed layer may be provided on a bottom surface of each of the intermediate pads530. For example, the seed layers may be disposed between the first molding part410and the intermediate pads530, between the first device200and the intermediate pads530and between the second device300and the intermediate pads530. The intermediate insulating layer540may be disposed on the first molding part410. The intermediate insulating layer540may surround the intermediate pads530, e.g., in a plan view. Top surfaces of the intermediate pads530may be exposed at a top surface of the intermediate insulating layer540. For example, the top surfaces of the intermediate pads530may be coplanar with the top surface of the intermediate insulating layer540. The intermediate insulating layer540may include or be formed of a photoimageable dielectric (PID). For example, the photoimageable dielectric (PID) may include or be formed of at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, and a benzocyclobutene-based polymer. The third device600may be disposed on the intermediate layer550. The third device600may be disposed on a top surface of the intermediate layer550. The third device600may be disposed face-down on the intermediate layer550. The third device600may include the third base layer610and the third circuit layer620provided on a surface of the third base layer610. The third device600may be mounted on the intermediate layer550. For example, the third circuit layer620of the third device600may face the intermediate layer550. The second chip terminals650may be provided under the exposed third circuit patterns of the third device600. The third device600may be mounted on the intermediate pads530of the intermediate layer550through the second chip terminals650. The second chip terminals650may electrically/directly connect the third circuit layer620of the third device600to the intermediate pads530of the intermediate layer550. The second molding part430may be provided on the intermediate layer550. The second molding part430may cover the top surface of the intermediate layer550. The second molding part430may surround the third device600, e.g., in a plan view. The second through-electrode440may be provided on the intermediate layer550. The second through-electrode440may be disposed at a side of the third device600. For example, the second through-electrode440may be laterally spaced apart from the third device600. The second through-electrode440may vertically penetrate the second molding part430. The second through-electrode440may extend toward the intermediate layer550to be electrically connected to the intermediate pad530of the intermediate layer550. For example, an end of the second through-electrode440may contact the intermediate pad530. According to the embodiments of the inventive concepts, the first device200, the second device300and the third device600may be mounted directly and/or electrically connected to the intermediate layer550without using wire bonding, e.g., using flip-chip bonding method. For example, the active surface of the first device200and the active surface of the second device300may face the active surface of the third device600, and the first device200and the second device300may be electrically/directly connected to the third device600by using only the intermediate layer550. Thus, electrical connection distances between the third device600and the first and second devices200and300may be reduced or shortened (e.g., comparing with other connection structures/methods), and electrical characteristics of the semiconductor package14may be improved. In addition, the first device200and the second device300may be electrically/directly connected to the third device600by using the intermediate pads530provided in a single layer, and thus distances between the third device600and the first and second devices200and300may be reduced/minimized. As a result, a small semiconductor package may be realized. FIG.5illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.5, a semiconductor package16may not include the redistribution layer500ofFIG.1. The third device600may be disposed on the first molding part410. The third device600may be disposed on the top surface of the first molding part410. The bottom surface of the third device600may be in contact with the top surface of the first molding part410. The third device600may be disposed face-down on the first molding part410. The third device600may include the third base layer610and the third circuit layer620provided on a surface of the third base layer610. The third device600may be electrically connected to the first device200, the second device300and the first through-electrode420. For example, the exposed third circuit patterns of the third device600may be in contact with the first chip bump260of the first device200, the second chip bump360of the second device300and the first through-electrode420. The second molding part430may be provided on the first molding part410. The second molding part430may be in contact with the top surface of the first molding part410. The second molding part430may surround the third device600, e.g., in a plan view. The second through-electrode440may be provided on the first molding part410. The second through-electrode440may be disposed at a side of the third device600. For example, the second through-electrode may be laterally spaced apart from the third device600. The second through-electrode440may vertically penetrate the second molding part430. The second through-electrode440may extend toward the first package substrate100to be in contact with the first sub-through-electrode422of the first through-electrodes420. For example, an end of the second through-electrode440may contact the first sub-through electrode422. According to the embodiments of the inventive concepts, the first device200and the second device300may be mounted directly and/or electrically connected to the third device600without wire bonding, e.g., with flip-chip bonding method as shown inFIG.5. For example, the active surface of the first device200and the active surface of the second device300may face the active surface of the third device600, and the first chip bump260of the first device200and the second chip bump360of the second device300may be connected directly to the third circuit layer620of the third device600. Thus, electrical connection distances between the third device600and the first and second devices200and300may be reduced or shortened (e.g., comparing with other type of connections between semiconductor chips), and electrical characteristics of the semiconductor package16may be improved. In addition, the first and second devices200and300may be connected directly to the third device600without an additional intermediate component, and thus a small semiconductor package may be realized. FIG.6illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.6, a semiconductor package may include a lower package10and an upper package20. For example, the semiconductor package may be a package-on-package (PoP) in which the upper package20is mounted on the lower package10. The lower package10may have the same or similar structure as the semiconductor package10ofFIGS.1and2, the semiconductor package12ofFIG.3, the semiconductor package14ofFIG.4or the semiconductor package16ofFIG.5. The descriptions to the semiconductor packages ofFIGS.1to5may also be applied to the lower package10. The upper package20may include an upper package substrate810, an upper semiconductor chip820, and an upper molding part830. The upper package substrate810may be disposed on the second package substrate700. Here, the upper package substrate810may be vertically spaced apart from the second package substrate700. For example, an air gap may be formed between the upper package substrate810and the second package substrate700as shown inFIG.6. The upper package substrate810may be a printed circuit board (PCB) having conductive patterns. Alternatively, the upper package substrate810may have a structure in which insulating layers and interconnection layers are alternately stacked. The upper package substrate810may be mounted on the second package substrate700. For example, substrate terminals (or package connection terminals)812may be disposed under the upper package substrate810. For example, the upper package substrate810may be electrically connected to the second package700through the substrate terminals812interposed therebetween. For example, the substrate terminals812may contact the second substrate interconnection patterns720of the second package substrate700. The substrate terminals812may include or may be solder balls or solder bumps. At least one upper semiconductor chip820may be disposed on the upper package substrate810. When a plurality of upper semiconductor chips820are provided in the upper package20, the upper semiconductor chips820may be spaced apart from each other, e.g., in a plan view. For example, the upper semiconductor chips820may be laterally spaced apart from each other. The upper semiconductor chip820may be mounted on a top surface of the upper package substrate810. For example, the upper semiconductor chip820may be mounted on substrate pads of the upper package substrate810by a wire bonding method. In certain embodiments, the upper semiconductor chip820may be electrically connected to the upper package substrate810by bonding wires822. However, embodiments of the inventive concepts are not limited thereto. In certain embodiments, the upper semiconductor chip820may be mounted on the upper package substrate810by other mounting component(s) such as solder balls or solder bumps. For example, the upper semiconductor chip820may be a logic chip or a memory chip. The upper semiconductor chip820may be electrically connected to the external terminals140of the first package substrate100through the upper package substrate810, the second package substrate700, the second through-electrode440, the redistribution layer500and the first through-electrode420and may be electrically connected to the first, second and third devices200,300and600through the upper package substrate810, the second package substrate700, the second through-electrode440and the redistribution layer500. A single upper semiconductor chip820is illustrated inFIG.6. However, two or more upper semiconductor chips820may be provided in the upper package20. The upper molding part830may be provided on the upper package substrate810. The upper molding part830may surround the upper semiconductor chip820on the top surface of the upper package substrate810. For example, the upper semiconductor chip820may be embedded in the upper molding part830on the upper package substrate810. FIG.7illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.7, the lower package10may not include the second package substrate700ofFIG.6. The second molding part430may have recess regions432formed in the top surface of the second molding part430. The recess regions432may be located on the second through-electrodes440. For example, top surfaces of the second through-electrodes440may be exposed at bottom surfaces of the recess regions432. The upper package substrate810may be disposed on the second molding part430. The upper package substrate810may be vertically spaced apart from the second molding part430. For example, an air gap may be formed between the upper package substrate810and the second molding part430as shown inFIG.6. The upper package substrate810may be electrically/directly connected to the second through-electrodes440. For example, substrate terminals812may be disposed under the upper package substrate810. The substrate terminals812may be inserted in the recess regions432of the second molding part430to be electrically connected to the second through-electrodes440. For example, the substrate terminals812may contact the second through-electrodes440. FIG.8illustrates a cross-sectional view showing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.8, the lower package10may not include the second package substrate700ofFIG.6and the second through-electrode440ofFIG.6. The second molding part430may have through-holes434vertically penetrating the second molding part430. The through-holes434may expose the top surface of the redistribution layer500(e.g., the redistribution pads524of the redistribution layer500). The upper package substrate810may be disposed on the second molding part430. The upper package substrate810may be vertically spaced apart from the second molding part430. For example, an air gap may be formed between the upper package substrate810and the second molding part430as shown inFIG.8. The upper package substrate810may be electrically/directly connected to the redistribution layer500. For example, substrate terminals814may be disposed under the upper package substrate810. The substrate terminals814may be inserted in the through-holes434of the second molding part430to be electrically connected to and/or contact the redistribution pads524of the redistribution layer500. FIGS.9to16illustrate cross-sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.9, a carrier substrate900may be provided. The carrier substrate900may be an insulating substrate including or made of a glass or a polymer or may be a conductive substrate including or made of a metal. Even though not shown in the drawings, the carrier substrate900may have an adhesive member provided on a top surface of the carrier substrate900. For example, the adhesive member may include or may be an adhesive tape. A first package substrate100may be formed on the carrier substrate900. Hereinafter, the formation of the first package substrate100will be described in detail. A lower insulating layer130may be provided on the carrier substrate900. The lower insulating layer130may include or be formed of an insulating polymer or a photoimageable dielectric (PID). The lower insulating layer130may correspond to the substrate passivation layer130described with reference toFIG.1. Second substrate pads124may be formed in the lower insulating layer130. For example, the lower insulating layer130may be patterned to form openings for forming the second substrate pads124, a seed layer may be conformally formed in each of the openings, and a plating process using the seed layer as a seed may be performed to form the second substrate pad124filling each of the openings. A first substrate insulating layer110may be formed on the lower insulating layer130. The first substrate insulating layer110may be formed by a coating process such as a spin coating process or a slit coating process. The first substrate insulating layer110may include or be formed of a photoimageable dielectric (PID). For example, the photoimageable dielectric (PID) may include or be formed of at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, and a benzocyclobutene-based polymer. Openings may be formed in the first substrate insulating layer110. For example, the first substrate insulating layer110may be patterned to form the openings. Each of the openings may have a T-shaped cross section. Each of the openings may expose the second substrate pad124. First substrate interconnection patterns120may be formed. For example, a barrier layer and a conductive layer may be formed on the first substrate insulating layer110to fill the openings, and then, a planarization process may be performed on the conductive layer and the barrier layer to form the first substrate interconnection patterns120. A substrate interconnection layer having the first substrate insulating layer110and the first substrate interconnection patterns120may be formed as described above. The process of forming the substrate interconnection layer may be repeated to form the first package substrate100in which the substrate interconnection layers are stacked. The first substrate interconnection pattern120of an uppermost one of the substrate interconnection layers may correspond to a first substrate pad122of the first package substrate100. Referring toFIG.10, first through-electrodes420may be formed on the first package substrate100. For example, a sacrificial layer may be formed on the first package substrate100, via holes penetrating the sacrificial layer to expose the first substrate pads122may be formed, and then, the first through-electrodes420may be formed by filling the via holes with a conductive material. Thereafter, the sacrificial layer may be removed. A first device200may be provided. Components of the first device200may be the same as or similar to those described with reference toFIG.1. For example, the first device200may include a first base layer210, a first circuit layer220provided on an active surface of the first base layer210, a first passivation layer230provided on an inactive surface of the first base layer210, and first vias240penetrating the first base layer210and the first passivation layer230to be connected to the first circuit layer220. First chip bumps260may be formed on the first device200. For example, a mask pattern having openings exposing first circuit patterns224of the first circuit layer220may be formed on the first circuit layer220, a seed layer may be conformally formed in each of the openings, and a plating process using the seed layer as a seed may be performed to form the first chip bumps260filling the openings, respectively. The first device200may be mounted on the first package substrate100. For example, first chip terminals250may be provided on the first vias240of the first device200. The first device200may be aligned in such a way that the first chip terminals250are located on the first substrate pads122of the first package substrate100, and then, a reflow process may be performed to connect the first chip terminals250to the first vias240and the first substrate pads122. For example, the first chip terminals250and the first vias240may be connected by a reflow soldering process. A second device300may be provided. Components of the second device300may be the same as or similar to those described with reference toFIG.1. For example, the second device300may include a second base layer310and a second circuit layer320provided on an active surface of the second base layer310. Second chip bumps360may be formed on the second device300. For example, a mask pattern having openings exposing circuit patterns of the second circuit layer320may be formed on the second circuit layer320, a seed layer may be conformally formed in each of the openings, and a plating process using the seed layer as a seed may be performed to form the second chip bumps360filling the openings, respectively. The second device300may be adhered onto the first package substrate100. For example, an adhesive film370may be provided on an inactive surface of the second base layer310of the second device300. The second device300may be located on the first package substrate100, and then, the second device300may be pressed on the first package substrate100. A first molding part410may be formed on the first package substrate100. For example, a molding material may be formed on the top surface of the first package substrate100to cover the first device200and the second device300, and the molding material may be hardened to form the first molding part410. The first molding part410may cover and/or contact a top surface and side surfaces of the first device200, a top surface and side surfaces of the second device300, and top surfaces and side surfaces of the first and second chip bumps260and360. The first molding part410may surround the first through-electrode420. Referring toFIG.11, a portion of the first molding part410may be removed. For example, the first molding part410may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the first molding part410. Thus, the top surface of the first molding part410may be planarized. The thinning process may be performed until the top surfaces of the first and second chip bumps260and360are exposed. An upper portion of the first molding part410may be removed by the thinning process. Upper portions of the first chip bumps260, upper portions of the second chip bumps360and upper portions of the first through-electrodes420may also be removed by the thinning process as necessary. After the thinning process, the first chip bumps260and the second chip bumps360may be exposed at a top surface of the first molding part410. After the thinning process, top surfaces of the first through-electrodes420may be exposed. The top surfaces of the first chip bumps260, the top surfaces of the second chip bumps360, the top surfaces of the first through-electrodes420and the top surface of the first molding part410may be substantially flat and may be substantially coplanar with each other. Referring toFIG.12, a redistribution layer500may be formed on the first molding part410. For example, a redistribution insulating pattern510may be formed on the first molding part410. The redistribution insulating pattern510may include or be formed of an insulating polymer or a photoimageable dielectric (PID). Redistribution patterns520may be formed in the redistribution insulating pattern510. For example, the redistribution insulating pattern510may be patterned to form openings for forming the redistribution patterns520, a seed layer may be conformally formed in each of the openings, and a plating process may be performed using the seed layer as a seed to form the redistribution patterns520filling the openings. The openings may expose the first through-electrodes420, the first chip bumps260, and the second chip bumps360. Thus, the redistribution patterns520may be electrically connected to and/or contact the first through-electrodes420, the first chip bumps260, and the second chip bumps360. One redistribution region (e.g., a redistribution sub-layer) may be formed as described above. Another redistribution insulating pattern510may be formed on the one redistribution region. The other redistribution insulating pattern510may be formed by a coating process such as a spin coating process or a slit coating process. The other redistribution insulating pattern510may include or be formed of a photoimageable dielectric (PID). Openings exposing the redistribution patterns520of the one redistribution region provided thereunder may be formed in the other redistribution insulating pattern510, a seed layer may be conformally formed in each of the openings, and a plating process may be performed using the seed layer as a seed to form redistribution patterns520filling the openings. As described above, other redistribution regions (e.g., sub-layers) may be formed on the one redistribution region. An uppermost redistribution pattern524of an uppermost redistribution region may be exposed at a top surface of the redistribution insulating pattern510, and the exposed portion of the uppermost redistribution pattern524may correspond to a second redistribution pad524of the redistribution layer500(hereinafter, the second redistribution pad and the uppermost redistribution pattern are indicated by the same reference numeral ‘524’ for the purpose of ease and convenience in explanation). However, the inventive concepts are not limited to the above embodiments in which the redistribution layer500is formed. In certain embodiments, an intermediate layer550may be formed on the first molding part410. For example, an intermediate insulating layer540may be formed on the first molding part410. The intermediate insulating layer540may include or be formed of an insulating polymer or a photoimageable dielectric (PID). Intermediate pads530may be formed in the intermediate insulating layer540. For example, the intermediate insulating layer540may be patterned to form openings for forming the intermediate pads530, a seed layer or barrier layer may be conformally formed in each of the openings, and a plating process may be performed using the seed layer or barrier layer as a seed to form the intermediate pads530filling the openings. Alternatively, a seed layer or barrier layer may be formed on the first molding part410, a sacrificial layer may be formed on the seed layer or barrier layer and then may be patterned to form openings for forming the intermediate pads530, and a plating process may be performed using the seed layer or barrier layer in the openings as a seed to form the intermediate pads530filling the openings. Thereafter, the sacrificial layer may be removed, and the seed layer or barrier layer may be patterned using the intermediate pads530as masks. Thus, the seed layer or barrier layer may remain between the first molding part410and each of the intermediate pads530. Thereafter, the intermediate insulating layer540surrounding the intermediate pads530may be formed on the first molding part410. In these cases, the semiconductor package described with reference toFIG.4may be manufactured. Hereinafter, the embodiments ofFIG.12will be described continuously as examples. Referring toFIG.14, second through-electrodes440may be formed on the redistribution layer500. For example, a sacrificial layer may be formed on the redistribution layer500, via holes penetrating the sacrificial layer to expose second redistribution pads524of the redistribution layer500may be formed, and then, the second through-electrodes440may be formed by filling the via holes with a conductive material. Thereafter, the sacrificial layer may be removed. A third device600may be provided. Components of the third device600may be the same as or similar to those described with reference toFIG.1. For example, the third device600may include a third base layer610and a third circuit layer620provided on an active surface of the third base layer610. The third device600may be mounted on the redistribution layer500. For example, second chip terminals650may be provided on the third circuit layer620of the third device600. The third device600may be aligned in such a way that the second chip terminals650are located on the second redistribution pads524of the redistribution layer500, and then, a reflow process may be performed to connect the second chip terminals650to the third circuit layer620and the redistribution layer500. For example, the second chip terminals650may be electrically connected to the third circuit layer620and to the redistribution layer500by a reflow soldering process. Referring toFIG.15, a second molding part430may be formed on the redistribution layer500. For example, a molding material may be formed on the top surface of the redistribution layer500to cover the third device600, and the molding material may be hardened to form the second molding part430. The second molding part430may cover and/or contact a top surface and side surfaces of the third device600and may surround the second through-electrode440. For example, the second molding part430may contact side surfaces of the second through-electrode440. Thereafter, a portion of the second molding part430may be removed. For example, the second molding part430may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the second molding part430. Thus, the top surface of the second molding part430may be planarized. An upper portion of the second molding part430may be removed by the thinning process. Upper portions of the second through-electrodes440may also be removed by the thinning process as necessary. After the thinning process, top surfaces of the second through-electrodes440may be exposed. The top surfaces of the second through-electrodes440and the top surface of the second molding part430may be substantially flat and may be substantially coplanar with each other. Referring toFIG.16, a second package substrate700may be formed on the second molding part430. For example, a second substrate insulating layer710may be formed on the second molding part430. The second substrate insulating layer710may include or be formed of an insulating polymer or a photoimageable dielectric (PID). Second substrate interconnection patterns720may be formed in the second substrate insulating layer710. For example, the second substrate insulating layer710may be patterned to form openings for forming the second substrate interconnection patterns720, a seed layer may be conformally formed in each of the openings, and a plating process may be performed using the seed layer as a seed to form the second substrate interconnection patterns720filling the openings. The openings may expose the second through-electrodes440. Thus, the second substrate interconnection patterns720may be electrically connected to and/or contact the second through-electrodes440. One substrate interconnection layer may be formed as described above. Another second substrate insulating layer710may be formed on the one substrate interconnection layer. The other second substrate insulating layer710may be formed by a coating process such as a spin coating process or a slit coating process. The other second substrate insulating layer710may include or be formed of a photoimageable dielectric (PID). Openings exposing the second substrate interconnection patterns720of the one substrate interconnection layer provided thereunder may be formed in the other second substrate insulating layer710, a seed layer may be conformally formed in each of the openings, and a plating process may be performed using the seed layer as a seed to form second substrate interconnection patterns720filling the openings. As described above, other substrate interconnection layers may be formed on the one substrate interconnection layer. However, the inventive concepts are not limited to the above embodiments in which the second package substrate700is formed. Referring again toFIG.1, the carrier substrate900may be removed. Thus, the lower insulating layer130and the second substrate pads124of the first package substrate100may be exposed. Thereafter, external terminals140may be provided on the exposed second substrate pads124, respectively. The semiconductor package10described with reference toFIG.1may be manufactured as described above. Referring toFIG.6, an upper package20may be provided. The upper package20may include an upper package substrate810, an upper semiconductor chip820, and an upper molding part830. For example, the upper semiconductor chip820may be mounted on the upper package substrate810, and then, an insulating material may be formed on the upper package substrate810to form the upper molding part830covering the upper semiconductor chip820. For example, the upper molding part830may contact a top surface and side surfaces of the upper semiconductor chip820. The upper package20may be mounted on the second package substrate700. For example, substrate terminals812may be provided on a bottom surface of the upper package substrate810. The upper package20may be aligned on the second package substrate700in such a way that the substrate terminals812face the second package substrate700, and then, a reflow process may be performed to connect the substrate terminals812to the second package substrate700and the upper package substrate810. For example, the substrate terminals812may be electrically connected to the second package substrate700and to the upper package substrate810by a reflow soldering process. The semiconductor package described with reference toFIG.6may be manufactured as described above. FIGS.17and18illustrate cross-sectional views showing a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concepts. Referring toFIG.17, a third device600may be provided on the resultant structure ofFIG.12. Components of the third device600may be the same as or similar to those described with reference toFIG.1. For example, the third device600may include or be formed of a third base layer610and a third circuit layer620provided on an active surface of the third base layer610. The third device600may be mounted on the redistribution layer500. For example, second chip terminals650may be provided on the third circuit layer620of the third device600. The third device600may be aligned in such a way that the second chip terminals650are located on the second redistribution pads524of the redistribution layer500, and then, a reflow process may be performed to connect the second chip terminals650to the third circuit layer620and the redistribution layer500. For example, the second chip terminals650may be electrically connected to the third circuit layer620and to the redistribution layer500by a reflow soldering process. Thereafter, a second molding part430may be formed on the redistribution layer500. For example, a molding material may be formed on the top surface of the redistribution layer500to cover the third device600, and the molding material may be hardened to form the second molding part430. The second molding part430may cover and/or contact a top surface and side surfaces of the third device600. Referring toFIG.18, through-holes434may be formed in the second molding part430. The through-holes434may expose the redistribution patterns524of the redistribution layer500. For example, a mask pattern may be formed on the second molding part430, and then, the second molding part430may be patterned using the mask pattern as an etch mask to form the through-holes434. Referring again toFIG.15, second through-electrodes440may be formed in the through-holes434(seeFIG.18) of the second molding part430. For example, a seed layer may be formed on the second molding part430to conformally cover inner surfaces of the through-holes434, and then, a plating process may be performed using the seed layer as a seed to form the second through-electrodes440filling the through-holes434. Subsequent processes may be the same as or similar to those described with reference toFIGS.16,1and6. For example, the second package substrate700may be formed on the second molding part430. The upper package20may be mounted on the second package substrate700as necessary. In certain embodiments, the second through-electrode440and the second package substrate700may not be formed. Referring again toFIG.8, the upper package20may be provided on the resultant structure ofFIG.18. The upper package20may include an upper package substrate810, an upper semiconductor chip820, and an upper molding part830. For example, the upper semiconductor chip820may be mounted on the upper package substrate810, and then, an insulating material may be formed on the upper package substrate810to form the upper molding part830covering the upper semiconductor chip820. For example, the upper molding part830may contact a top surface and side surfaces of the upper semiconductor chip820. The upper package20may be mounted on the redistribution layer500. For example, substrate terminals814may be provided on a bottom surface of the upper package substrate810. The upper package20may be disposed on the second molding part430in such a way that the substrate terminals814face the second molding part430. At this time, the upper package20may be aligned on the second molding part430in such a way that positions of the substrate terminals814correspond to and/or vertically overlap those of the through-holes434, respectively. The substrate terminals814may be inserted into the through-holes434to be in contact with the second redistribution pads524of the redistribution layer500. Thereafter, a reflow process may be performed to connect the substrate terminals814to the redistribution layer500and the upper package substrate810. For example, the substrate terminals814may be electrically connected to the redistribution layer500and to the upper package substrate810by a reflow soldering process. The semiconductor package described with reference toFIG.8may be manufactured as described above. In the semiconductor package according to the embodiments of the inventive concepts, electrical connection distances between the third device and the first and second devices may be reduced or shortened. In addition, an electrical connection distance between the third device and the first package substrate may be reduced or shortened. Thus, the electrical characteristics of the semiconductor package may be improved. Furthermore, an area required for arrangement of the first to third devices may be reduced, and distances between the third device and the first and second devices may be reduced. Thus, a small semiconductor package may be realized. | 71,443 |
11942459 | DETAILED DESCRIPTION The present subject matter will now be described more fully hereinafter with reference to the accompanying Figures, in which representative embodiments are shown. The present subject matter can, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to describe and enable one of skill in the art. Referring toFIG.1, there is shown a cross-sectional side view of a semiconductor device package with exposed bond wires, generally designated100, in accordance with an exemplary embodiment of the present disclosure. The semiconductor device package100may include a first semiconductor device package102and a second semiconductor device package104electrically connected to one another. The first semiconductor device package102may include a first substrate106, one or more semiconductor dies108a-108d, and bond wires110a-110b, all of which being at least partially encapsulated within a first mold compound112. The second semiconductor device package104may include a second substrate114, one or more semiconductor dies116a-116d, and bond wires118a-118d, all of which being at least partially encapsulated within a second mold compound120. The first mold compound112and/or second mold compound120may include, for example, an epoxy molding compound (EMC) or other encapsulant material known in the art. The first semiconductor device package102and/or second semiconductor device package104may be any type of semiconductor device, such as a system-in-package (SiP). In one nonlimiting example, the first semiconductor device package102and/or second semiconductor device package104is a storage device (e.g., a secure digital (SD) card or a MultiMediaCard (MMC)) and the semiconductor dies108a-108dand116a-116dare NAND memory dies. In some embodiments, the semiconductor device package100may be any type of semiconductor device, such as an SiP, or package-on-package (PoP). In some embodiments, the first substrate106may be a mechanical base support for the first semiconductor device packages102and an electrical interface (or electrical circuit) that provides access to the semiconductor dies108a-108dhoused within the first semiconductor device package102. For example, the first substrate106may include a plurality of metal layers disposed within the first substrate106, including at least one layer for routing data using conductive (e.g., copper) traces, a ground layer, and/or a power layer. In some embodiments, the first substrate106includes a top planar surface122upon which at least one of the semiconductor dies108a-108dand/or other elements are mounted. Each of the semiconductor dies108a-108dmay include a top planar surface that is substantially parallel to the top planar surface122of the first substrate. The first semiconductor device package102may include one or more solder balls124mounted on a bottom planar surface126of the first substrate106and in electrical communication with the first substrate106. The one or more solder balls124may be configured to electrically and/or mechanically couple the first semiconductor device package102may be to one or more other electrical components (not shown) exterior to the first semiconductor device package102. In some embodiments, the second substrate114may be a mechanical base support for the second semiconductor device package104and an electrical interface that provides access to the semiconductor dies116a-116dhoused within the second semiconductor device package104. For example, the second substrate114may include a plurality of metal layers disposed within the second substrate114, including at least one layer for routing data using conductive (e.g., copper) traces, a ground layer, and/or a power layer. In some embodiments, the second substrate114includes a top planar surface128upon which at least one of the semiconductor dies116a-116dand/or other elements are mounted. The second semiconductor device package104may include one or more solder balls130mounted on a bottom planar surface132of the second substrate114and in electrical communication with the second substrate114. The one or more solder balls130may be configured to electrically and/or mechanically couple the second semiconductor device package104to the first semiconductor device package102, as discussed in more detail below. In some embodiments, the semiconductor dies108a-108dare stacked, one on top of the other and the bottom most semiconductor die108ais coupled to the top planar surface122of the first substrate106. For example, semiconductor die108ais coupled to the top planar surface122of the first substrate106, semiconductor die108bis coupled to the top surface of semiconductor die108a, and so on. Although only four semiconductor dies108a-108dare shown, it will be understood that the first semiconductor device package102may include fewer than four or greater than four semiconductor dies. For example, the first semiconductor device package102may include between one and twenty-four semiconductor dies, stacked one on top of the other, similar to what is shown inFIG.1. Similarly, the semiconductor dies116a-116dmay be stacked, one on top of the other, and the bottom most semiconductor die116amay be coupled to the top planar surface128of the second substrate114. Although only four semiconductor dies116a-116dare shown included in the second semiconductor device package104, it will be understood that fewer than four or greater than four semiconductor dies may be included in the second semiconductor device package104. For example, the second semiconductor device package104may include between one and twenty-four semiconductor dies, stacked one on top of the other, similar to what is shown inFIG.1. In some embodiments, the first semiconductor device package102includes a controller109configured to provide electrical communication with the semiconductor dies108a-108dand/or semiconductor dies116a-116d. In some embodiments, the controller109is an application specific integrated circuit (ASIC) chip configured to control the functionality of the semiconductor dies108a-108dand/or semiconductor dies116a-116d. In some embodiments, the controller109is electrically connected to the substrate106by one or more bond wires111. In other embodiments, the controller109is a flip-chip die that is mounted on and electrically connected to the first substrate106using flip chip mounting. Each semiconductor die108a-108dmay be electrically connected to the adjacent semiconductor dies108a-108dand/or the first substrate106via one the corresponding bond wires110a-110d. For example, semiconductor die108ais electrically connected to the first substrate106by bond wire110a, semiconductor die108bis electrically connected to semiconductor die108aby bond wire110b, and so on. In this manner, the semiconductor dies108a-108dmay be in electrical communication with one another, the first substrate106, and/or the controller109. Similarly, semiconductor dies116a-116dmay be electrically connected to the adjacent semiconductor dies116a-116dand/or the second substrate114via the corresponding bond wires118a-118d. For example, semiconductor die116ais electrically connected to the second substrate114by bond wire118a, semiconductor die116bis electrically connected to semiconductor die116aby bond wire118b, and so on. In this manner, the semiconductor dies116a-116dmay be in electrical communication with one another and with the second substrate114. In some embodiments, one or more of the bond wires110a-110dare configured to electrically couple the first semiconductor device package102to the second semiconductor device package104. For example, bond wire110dmay be at least partially exposed along a surface of the first molding compound112such that an electrical connection between the first semiconductor device package102and second semiconductor device package104may be formed via the bond wire110d. In some embodiments, the first semiconductor device package102includes one or more conductive pads134mounted to the surface of the first molding compound112where the bond wire110dis at least partially exposed. For example, a portion of the bond wire110dis exposed along a top planar surface136of the first molding compound112and the conductive pads134are mounted on the top planar surface136of the first molding compound112. The top planar surface136of the first molding compound112may be substantially parallel to the top planar surface122of the first substrate106and/or to the top planar surfaces of the semiconductor dies108a-108d. The first molding compound112may include a side planar surface137that is substantially perpendicular to the top planar surface136of the first molding compound, top planar surface122of the first substrate106and/or the top planar surfaces of the semiconductor dies108a-108d. At least one of the conductive pads134may be positioned along the top planar surface136of the first molding compound112such that the conductive pad134is electrically connected to the portion of the bond wire110dthat is exposed along the top planar surface136of the first molding compound112. Referring toFIGS.1-2, the bond wire110dmay include a first portion138a, a second portion138bopposite the first portion138a, and an intermediate portion138cextending between the first portion138aand second portion138b. The first portion138a, second portion138b, and intermediate portion138cmay be integrally formed such that the bond wire110dis a unitary construct. The first portion138aand second portion138bmay be first and second ends of the bond wire110d. In some embodiments, the first portion138ais connected (e.g., physically connected and/or electrically connected) to the uppermost semiconductor die (e.g., semiconductor die108d) of the first semiconductor device package102. The second portion138bmay be connected (e.g., physically and/or electrically connected) to the adjacent semiconductor die (e.g., semiconductor die108c) positioned below the upper most semiconductor die. The uppermost semiconductor die may be positioned above the top planar surface122of the first substrate106and below the top planar surface136of the first molding compound112. As such, the adjacent semiconductor die (e.g., semiconductor die108c) may be positioned between the uppermost semiconductor die and the top planar surface122of the first substrate106. In some embodiments, the intermediate portion138cof the bond wire110dis exposed along a surface of first molding compound112such that one or more other components may be electrically connected to the intermediate portion138c. For example, the intermediate portion138cmay be exposed along a top planar surface136of the first molding compound112such that the first molding compound112does not cover the intermediate portion138c. In this manner, the intermediate portion138cmay act as an electrical interface surface exposed at the top planar surface136of the first molding compound112that one or more other components (e.g., conductive pad134) may be electrically connected to. In some embodiments, the intermediate portion138cextends along the top planar surface136of the first molding compound112by a length L1. The length L1of the intermediate portion138cmay be greater than the diameter of a cross-section of the bond wire110d. In some embodiments, the length L1of the intermediate portion138cis about four to twenty times greater than the diameter of the bond wire110d. For example, the diameter of the bond wire110dmay be about 25 micrometers and the length L1may be about 200 micrometers. In some embodiments, the length L1of the intermediate portion138cis at least 100 micrometers. InFIG.2, the intermediate portion138cis illustrated as being generally parallel to the top planar surface136of the first molding compound112, however, it will be understood that the intermediate section138cmay have an irregular or uneven shape. For example, the intermediate portion138cmay be generally curved or bent along the length L1. The length L1of the intermediate portion138cbeing greater than the diameter of the bond wire110dmay increase the surface area exposed at the top planar surface136of the first molding compound112that may act as an electrical interface as compared to conventional semiconductor device packages. For example, in conventional semiconductor device packages, the semiconductor dies are electrically connected to one another via bond wires that are similar to the bond wires110a-110d, except that the bond wires of the conventional semiconductor device package are entirely encapsulated by a molding compound. In order to provide an electrical interface surface that is exposed at a surface of the molding compound, a vertical bond wire is typically provided. The vertical bond wire is typically connected to a semiconductor die and extends vertically upward from that semiconductor die to the top planar surface of a molding compound that encapsulates the components of the semiconductor device package. A terminal end of the vertical bond wire is typically exposed at the top planar surface of the molding compound to allow one or more other components to be electrically connected to the vertical bond wire. As such, the terminal end of the vertical bond wire that acts as an electrical interface surface has a generally circular shape defined by the diameter of the vertical bond wire. Put another way, the vertical bond wire has a generally circular cross-sectional shape defined by the diameter of the vertical bond wire. Furthermore, the vertical bond wire is generally perpendicular relative to a top planar surface of the molding compound, and therefore the electrical interface surface is also generally circular and has a surface area defined by the diameter of the vertical bond wire. In the embodiments of the present disclosure discussed above, the intermediate portion138cof the bond wire110dis not oriented vertically relative to the top planar surface136of the first molding compound. Instead, the intermediate portion138cextends along a portion of the top planar surface136of the first molding compound112by length L1. In this manner, the intermediate portion138cof the bond wire110dprovides a greater electrical interface surface area as compared to a conventional semiconductor device package that includes a vertical bond wire for providing the electrical interface surface. In some embodiments, the bond wire110dmay be less prone to wire sweep, during flowing of the first molding compound112, as compared to a vertical bond wire included in a conventional semiconductor device package. For example, in conventional semiconductor device packages, vertical bond wires are often prone to wire sweep during flowing of the molding compound that encapsulates the components of the conventional semiconductor device package. The bond wire110daccording to the present disclosure is mechanically and electrically connected at opposing ends (e.g., the first portion138aand second portion138b) to semiconductor dies108c-108d, whereas a vertical bond wire is mechanically and electrically connected at a single end. In this manner, the bond wire110dmay be less prone to wire sweep than the vertical bond wire of a conventional semiconductor device package. In some embodiments, one or more of the conductive pads134may be in electrical communication with the intermediate portion138cof the bond wire110d. For example, at least one of the conductive pads134may be positioned on the top planar surface136of the first molding compound112along at least a portion of the length L1of the intermediate portion138cof the bond wire110d. In this manner, at least one of the conductive pads134may be electrically connected to the bond wire110d. As such, the conductive pad134may be in electrical communication with the components of the first semiconductor device package102(e.g., the first substrate106, controller109, and/or semiconductor dies108a-108d) via bond wire110d. In some embodiments, the conductive pad134may be bonded to the intermediate portion138cof the bond wire110d. In some embodiments, the second semiconductor device package104is electrically connected to the first semiconductor device package102via the conductive pads134. The solder balls130of the second semiconductor device package104may be bonded to the conductive pads134of the first semiconductor device package102such that the solder balls130and conductive pads134are in electrical communication with one another. As discussed above, at least one of the conductive pads134is electrically connected to the intermediate portion138cof bond wire110d. As such, at least one of the solder balls130that is included in the second semiconductor device package104may be electrically connected to the conductive pad134that is electrically connected to the exposed intermediate portion138cof bond wire110d. In this manner, the first semiconductor device package102and second semiconductor device package104may be electrically connected to one another via the conductive pad134that is electrically connected to the intermediate portion138cof bond wire110dand the corresponding solder ball130. As such, electrical signals may be transmitted between the first semiconductor package102and second semiconductor device package104. In some embodiments, the semiconductor device package100includes an underfill140between the first semiconductor device package102and the second semiconductor device package104. In some embodiments, the underfill140may be configured to provide a mechanical bond between the first semiconductor device package102and the second semiconductor device package104and protect the solder balls130, exposed portions of the bond wires (e.g., intermediate section138cof bond wire110d), and conductive pads134from mechanical stress, and/or provide increased heat transfer capabilities. The underfill140may be provided in the space between the top planar surface136of the first molding compound112and the bottom planar surface132of the second substrate114and at least partially encapsulate the solder balls130, intermediate section138cof bond wire110dand the conductive pads134. In some embodiments, the underfill140is comprised of a polymer. Although only two semiconductor device packages are shown inFIG.1, it will be understood that additional semiconductor device packages may be stacked, one on top of the other, and electrically connected to one another similar to what is shown inFIG.1. For example, inFIG.1, a portion of the bond wire, proximate to the top planar surface of the second molding compound120, (e.g., a portion of bond wire118d) may be exposed at the top planar surface similar to how the intermediate portion138cof bond wire110dis exposed at the top planar surface136of the first molding compound112. One or more conductive pads, similar to conductive pads134, may be coupled to the top planar surface of the second molding compound120, at least one of which may be electrically connected to the exposed portion of bond wire118d. A third semiconductor device package, generally similar to either the first semiconductor device package102or second semiconductor device package104, may be electrically connected to the second semiconductor device package104via the conductive pad connected to the exposed portion of bond wire118d. In some embodiments, this structure may be repeated until a desired number of semiconductor dies and/or semiconductor device packages are included in the semiconductor device package100. In some embodiments, the risk of die bending and/or collapse of semiconductor dies108a-108dand,116a-116dincluded in the semiconductor device package100may be prevented, or at least reduced, when compared to conventional semiconductor device packages. Die bending and/or collapse may refer to instances where one or more semiconductor dies included in a semiconductor device package bend or deform due to limited area, excess weight caused by a large number of stacked dies and/or lack of mechanical support. For example, conventional semiconductor device packages often include a number of semiconductor dies stacked one on top of the other in a staircase-like pattern within a limited space. As the number of semiconductor dies, stacked one on top of the other is increased within a limited space, the risk of die bending and/or collapse also increases. By providing semiconductor dies in electrical communication with one another, as described above with reference to the semiconductor device package100of the present disclosure, the risk of die bending and/or collapse may be prevented, or at least reduced. For example, the semiconductor device package100provides additional mechanical support, via at least the multiple substrates (e.g., first substrate106, second substrate114) disposed between different stacks of semiconductor dies (e.g., between semiconductor dies108a-108dand semiconductor dies116a-116d). Referring toFIG.3, there is shown a cross-sectional side view of a combined semiconductor device package, generally designated200, in accordance with another exemplary embodiment of the present disclosure. The combined semiconductor device package200may include a first semiconductor device package202and a second semiconductor device package204in electrical communication with one another. The first semiconductor device package202may include a first substrate206, one or more semiconductor dies208a-208d, and a controller209. The semiconductor dies208a-208dmay be electrically connected to one another and/or to the first substrate206via bond wires210a-210d. For example, semiconductor dies208a-208dare electrically connected one to another via bond wires210b-210dand semiconductor die208ais electrically connected to the first substrate206via bond wire210a. Similarly, the controller209may be electrically connected to the first substrate206via bond wire(s)211. In some embodiments, the semiconductor dies208a-208d, controller209, bond wires210a-210dand/or bond wires211are at least partially encapsulated by a first molding compound212. The first molding compound212may include, for example, an EMC or other encapsulant material known in the art. The second semiconductor device package204may be generally the same as the first semiconductor device package202. For example, the second semiconductor device package204may include a second substrate214, one or more semiconductor dies216a-216d, and a controller219. The semiconductor dies216a-216dmay be electrically connected to one another and/or to the second substrate214via bond wires218a-218d. For example, semiconductor dies216a-216dare electrically connected, one to another via bond wires218b-218dand semiconductor die216ais electrically connected to the second substrate214via bond wire218a. Similarly, the controller219may be electrically connected to the second substrate214via bond wire(s)221. In some embodiments, the semiconductor dies216a-216d, controller219, bond wires218a-218dand/or bond wire(s)221are at least partially encapsulated by a second molding compound220. The second molding compound220may include, for example, an EMC or other encapsulant material known in the art. Both the first semiconductor device package202and second semiconductor device package204may be similar to the first semiconductor device package102described above, with reference toFIGS.1-2, except that at least one of the bond wires is exposed at a side planar surface of the respective molding compound rather than a top planar surface. For sake of brevity, not all functionality of the substrates206,214, semiconductor dies208a-208d,216a-216d, controllers209,219, and molding compounds212,220will be discussed. It will be understood though that the functionality of each may be generally the same as substrate106, semiconductor dies108a-108d, controller109, and molding compound112as discussed above with reference toFIGS.1-2. The bond wires210a-210dand218a-218dmay be generally the same as bond wires110a-110dexcept that at least one bond wire of each set of bond wires210a-210dand218a-218dmay be partially exposed at a side planar surface222of the first molding compound212and a side planar surface224of the second molding compound220respectively. The side planar surface222of the first molding compound212and side planar surface224of the second molding compound220may be substantially perpendicular to the top planar surfaces207,215of the first and second substrates206,214, respectively. The side planar surfaces222,224may be substantially perpendicular to top planar surfaces223,225of the first and second molding compounds212,220. In some embodiments, by exposing at least a portion of the bond wires210aand218a, the first and second semiconductor device packages202and204may be electrically coupled to a third substrate226in the vertical orientation shown inFIG.3. For example, the third substrate226may include a top planar surface234that is oriented generally perpendicular to a top planar surface207of the first substrate206and/or the top planar surface215of the second substrate214. The exposed portions of bond wires210aand218awill be better understood with reference toFIG.4, which illustrates a side cross-sectional view of the first semiconductor device package202in a horizontal orientation. As mentioned above, the first and second semiconductor device packages202and204are generally the same and as such, only the first semiconductor device package202, will be described for sake of brevity. However, it will be understood that the following description of the first semiconductor device package202may apply to the second semiconductor device package204and the corresponding components thereof. The bond wire210amay be at least partially exposed along a side planar surface222of the first molding compound212such that the bond wire210ais electrically connected to a conductive pad and/or redistribution layer (RDL)228coupled to the side planar surface222of the first molding compound212. In some embodiments, the RDL228electrically couples the semiconductor dies208a-208dto the first substrate206. For example, the bond wire210amay have a first portion227aelectrically connected to the semiconductor die208aand a second portion227bat least partially exposed at the side planar surface222of the first molding compound212. The RDL228may be electrically connected to the exposed area of the second portion227bsuch that the RDL228is in electrically coupled to the semiconductor die208avia bond wire210a. As such, bond wires210b-210dmay electrically couple the remaining semiconductor dies208b-208dto the RDL228. The RDL228may be electrically connected to the first substrate206such that the semiconductor dies208a-208dare electrically coupled to the first substrate206via the RDL228. Referring toFIG.5, there is shown a cross-sectional side view of a portion of the first semiconductor die202with a bond wire410apartially exposed at the side planar surface of the molding compound212. The bond wire410amay be generally the same as bond wire210a, except that bond wire410aincludes an intermediate portion427cthat is exposed at the side planar surface222of the molding compound212. The first portion427aof the bond wire may be electrically connected to semiconductor die208aand the second portion427bmay be electrically connected to the top planar surface207of the first substrate206. The intermediate portion427cmay be the portion of the bond wire410athat extends between the first portion427aand second portion427band that is exposed at the side planar surface222of the first molding compound212. In some embodiments, the intermediate portion427cis exposed along a length L2of the first molding compound212such that a conductive pad or the RDL228may be electrically connected to the intermediate portion427c. The RDL228, when electrically connected to the intermediate portion427c, may be in electrical communication with at least the first substrate206and semiconductor dies208a-208d. In some embodiments, the length L2is greater than a cross-section of the bond wire410a. In some embodiments, the length L2is at least 100 micrometers. The benefits of exposing a bond wire along a length of the molding compound are discussed above with reference toFIGS.1-2and bond wire110dand it will be understood that the same benefits apply to the bond wire410a. Therefore, said benefits will not be discussed again for sake of brevity. Referring toFIGS.3-5, it will be understood that the first and second semiconductor device packages202and204may include a bond wire exposed similar to bond wire210aand/or410a. For example, in one embodiment, the first semiconductor device package202may include bond wire410ahaving the exposed intermediate portion427cand the second semiconductor device package may include bond wire218a, which has generally the same configuration as bond wire210a. In another embodiment, the first semiconductor device package202may include bond wire410aand the bond wire218aof the second semiconductor device package204may have generally the same configuration as bond wire410a. It will be understood that any combination of bond wire configurations may be used in the semiconductor device packages included in the combined semiconductor device package200. In some embodiments, there is a solder ball230electrically connected to the RDL228for electrically coupling the first semiconductor device package202to the third substrate226. For example, the third substrate226may include a conductive pad and/or RDL232electrically connected to a top planar surface234of the third substrate226. The solder ball230may be electrically connected to the RDL228of the first semiconductor device package202and RDL232of the third substrate226. In this manner, the first semiconductor device package202may be in electrical communication with the first substrate226. Similarly, the second semiconductor device package204may include an RDL236electrically connected to bond wire218a, similar to how RDL228is electrically connected to bond wire210aas described above with reference toFIG.4. The second semiconductor device package204may include a solder ball238electrically connected to the RDL236. There may be a second RDL240electrically connected to the top planar surface234of the third substrate226, and the solder ball238may be electrically connected to the second RDL240such that the second semiconductor device package204is electrically coupled to the third substrate226. As such, the first semiconductor device package202and second semiconductor device package204may be in electrical communication with one another via the third substrate226. In some embodiments, the RDL228and corresponding solder ball230of the first semiconductor device package202are a first RDL228and a first solder ball230, and the semiconductor device package202includes additional RDLs and solder balls configured to be electrically connected to the third substrate226. For example, the first semiconductor device package202may include a second RDL242and a second solder ball244electrically connected to the second RDL242. The second RDL242may be coupled to the side planar surface222of the first molding compound212and spaced from the first RDL228. The third substrate226may include a third RDL246electrically connected to the top planar surface234, and the second solder ball244may be electrically connected to the third RDL246. In this manner, the first and second RDLs228,242and corresponding solder balls230,244may mechanically and electrically couple the first semiconductor device package202to the third substrate226. In some embodiments, an underfill (not shown) is provided between the top planar surface234of the third substrate226and side planar surface222of the first molding compound212to provide additional mechanical support between the first semiconductor device package202and the third substrate226. The second semiconductor device package204may include one or more additional redistribution layers and corresponding solder balls to mechanically and electrically couple the second semiconductor device package204to the third substrate226similar to the first semiconductor device package202. For example, the RDL236and solder ball238may be a first RDL236and first solder ball238of the second semiconductor device package204. There may be a second RDL248, a second solder ball250included in the second semiconductor device package204and a fourth RDL252electrically connected to the top planar surface234of the third substrate226. Similar to the first semiconductor device package202, the second solder ball250may be electrically connected to the second RDL248of the second semiconductor device package204and the fourth RDL252of the third substrate226. In this manner, the first and second RDLs236,248and corresponding solder balls238,250may mechanically and electrically couple the second semiconductor device package204to the third substrate226. In some embodiments, an underfill (not shown) is provided between the top planar surface234of the third substrate226and the side planar surface224of the second molding compound220to provide additional mechanical support between the second semiconductor device package204and the third substrate226. Although two semiconductor device packages (e.g., first and second semiconductor device packages202,204) are shown inFIG.3, it will be understood that the combined semiconductor device package200may include any number of semiconductor device packages coupled to the third substrate226and in electrical communication with one another. For example, a third semiconductor device package, generally the same as the first and/or second semiconductor device packages202,204, may be electrically connected to the third substrate226in generally the same manner as discussed above such that the third semiconductor device package is in electrical communication with the first and second semiconductor device packages202,204. In some embodiments, the combined semiconductor device package200may include between two to twenty semiconductor device packages, electrically connected to the third substrate226and in electrical communication with one another. Referring toFIG.6, there is shown a side cross-sectional view of a combined semiconductor device package300in accordance with another embodiment of the present disclosure. The combined semiconductor device package300may include a first semiconductor device package302and a second semiconductor device package304electrically connected thereto. The first semiconductor device package302may be generally the same as the first and/or second semiconductor device packages202,204as discussed above with reference toFIGS.3-5. For example, the first semiconductor device package302may include a first substrate306having coupled thereto semiconductor dies308a-308d, controller309, bond wires310a-310d, and bond wire(s)311, each of which being at least partially encapsulated by a first molding compound312. The first substrate306, semiconductor dies308a-308d, controller309, bond wires310a-310and bond wire(s)311may be generally the same as substrate206, semiconductor dies208a-208d, controller209, bond wires210a-210d, and bond wire(s)211and will not be described for sake of brevity and so as not to obscure aspects of the present disclosure. The first semiconductor device package302may include an RDL328that is generally the same as RDL228except that RDL328is not directly connected to the first substrate306. For example, RDL328may be electrically connected to the portion of bond wire310athat is exposed at the side planar surface322of the first molding compound312such that the RDL328is not electrically connected to the substrate306. In some embodiments, there is a solder ball330electrically connected to the RDL328. The second semiconductor device package304may include second substrate314having a top planar surface315and at least one semiconductor die316electrically connected thereto via one or more bond wires318. The semiconductor die316may be a ASIC chip or a memory die (e.g., a NAND die). In some embodiments, the semiconductor die316is a flip-chip die that is mounted on and electrically connected to the second substrate314using flip chip mounting. In some embodiments, the semiconductor die316is or includes a capacitor or a resistor. In some embodiments, the semiconductor die316and bond wires318are at least partially encapsulated by a second molding compound320. The second molding compound320may include an EMC or other encapsulant materials known in the art. In some embodiments, the top planar surface315of the second substrate314is oriented generally perpendicular to a top planar surface307of the first substrate306. In some embodiments, the solder ball330is electrically connected to the second substrate314. In this manner, the first semiconductor device package302and second semiconductor device package304may be electrically coupled. In some embodiments, by providing a semiconductor die316that is oriented generally perpendicular to the semiconductor dies308a-308dand/or the first substrate306, the overall length of the semiconductor device package300may be reduced. For example, if semiconductor die316were oriented generally parallel to the first substrate306, the overall length of the semiconductor device package300may be greater than when the semiconductor die316and substrate314are oriented generally perpendicularly. Referring toFIGS.7A-7Hthere is illustrated a method of assembling the semiconductor device package100discussed above with reference toFIGS.1-2. Referring toFIG.7A, the first substrate106may be provided with one or more components (e.g., the semiconductor dies108a-108d, controller109, bond wires110a-110d) coupled thereto. The bond wires110a-110dmay be electrically connected to the corresponding semiconductor dies108a-108dand substrate106, respectively. The first substrate106and the components coupled thereto may be positioned above a mold103, including the first molding compound112and a release film113positioned between the mold103and the first molding compound112. Put another way, the release film113may be positioned along a bottom surface of the mold103such that the first molding compound112is above the release film113. In some embodiments, the first molding compound112is in a liquid or flowable state such that the first substrate106and the components coupled thereto may be immersed in the first molding compound112. In other embodiments, the first molding compound112is provided in the form of a powder such that the mold103may be compressed onto the first substrate106and the components coupled thereto, thereby causing the first molding compound112to transition from a powder state to a liquid or semi-liquid state. Referring toFIG.7B, the mold103may be compressed onto the first substrate106and the components coupled thereto such that the molding compound112at least partially encapsulates the semiconductor dies108a-108d, controller109, and bond wires110a-110d. In some embodiments, a portion of the bond wire110dabuts and/or extends into the release film113such that the portion of the bond wire110dis not encapsulated by the first molding compound112. For example, the portion of bond wire110dnot encapsulated may be the intermediate portion138cas described with reference inFIG.2. In some embodiments, the length of the bond wire110d, the dimensions of the mold103, and/or the volume of the first molding compound112provided in the mold103may be adjusted such that the portion of the bond wire110dnot encapsulated by the first molding compound112is adjusted (e.g., increased or decreased). The liquid molding compound112may be subsequently cured or hardened such that the liquid mold compound112hardens to protect the first substrate106, semiconductor dies108a-108d, controller109, and/or bond wires110a-110d. Referring toFIG.7C, the release film113may be removed and the first substrate106with at least partially encapsulated components may be removed from the mold103. In this manner a semiconductor device package having a bond wire exposed at a surface of the molding compound may be assembled. For example, what is shown inFIG.7Cis the first semiconductor device package102, discussed above with reference toFIGS.1-2, without the solder balls124coupled to the bottom of the first substrate106. Although inFIGS.7A-7Cthe assembly of the first semiconductor device package102is illustrated, it will be understood that a similar assembly may be performed to assemble any of the semiconductor packages shown inFIGS.3-6. For example, the first semiconductor device package202may be assembled according to the assembly illustrated inFIGS.7A-7C. As shown inFIGS.7A-7B, the release film113extends across the bottom surface and side surfaces of the mold103. In this manner, the release film113covers the side surfaces of the molding compound thereby allowing a portion of one or more bond wires (e.g., bond wire210a, bond wire310a, bond wire410a) to abut and/or extend into the release film113. As such, the portion of the bond wires that abuts and/or extends into the release film113may not be encapsulated by the molding compound thereby allowing that portion to be exposed at a side surface of the molding compound. Referring toFIG.7D, a removable mask142may be positioned on the top planar surface136of the first molding compound112. The removable mask142may be configured to be removed from the top planar surface136of the first molding compound112. The removable mask142may define one or more apertures144positioned along and extending through the removable mask142. In some embodiments, one or more of the apertures144is positioned above the exposed portion of bond wire110dsuch that the exposed portion of the bond wire110dis positioned within the aperture144when the removable mask142is coupled to the top planar surface136of the first molding compound112. InFIG.7D, the removable mask142defines five apertures144that are generally the same size and shape, however, it will be understood that the removable mask142may define fewer than five apertures or more than five apertures, at least one of which may have a different shape, size and/or orientation than another. The one or more apertures may define the position, orientation, and/or shape of one or more conductive elements (e.g., conductive pads134shown inFIG.7E) to be formed on the top planar surface136of the first molding compound112. In some embodiments, the one or more conductive pads134may be formed through a sputtering process. For example, ions146of a conductive material (e.g., copper) may be provided during the sputtering process. The ions146may be deposited onto the portions of the top planar surface136of the first molding compound112where apertures144are located. Put another way, the apertures144may act as openings on the removable mask142such that portions of the top planar surface136of the first molding compound112are not covered by the removable mask142. In this manner, the ions146may be deposited onto the top planar surface136of the first molding compound to form one or more conductive elements (e.g., conductive pads134). In some embodiments, the removable mask142may define one or more channels (not shown) extending between the apertures144such that during the sputtering process, ions146may be deposited onto the top planar surface136of the first molding compound112, via the channels, to form electrical connections between the conductive pads134. Referring toFIG.7E, there is shown a top elevational illustration of the first semiconductor device package102. The removable mask142may be removed from the top planar surface136of the first molding compound112subsequent to the sputtering process. As shown, there are multiple conductive pads134coupled to the top planar surface136of the first molding compound112. Some of the conductive pads (e.g., first conductive pads134a) may be electrically connected to the exposed portion (e.g., the intermediate section138c) of the bond wire110d. The remaining conductive pads (e.g., second conductive pads134b) may be coupled to the top planar surface136of the first molding compound112such that they are not directly connected to the intermediate section138cof the bond wire110d. InFIG.7E, there is a plurality of exposed bond wires generally the same as bond wire110dand it will be understood that each may function generally the same as bond wire110d. In some embodiments, there is an electrical connection (e.g., a trace148) formed between a first conductive pad134aand at least one of the second conductive pads134b. As mentioned above, the removable mask142may include channels (not shown) that define a path for the traces148that extend between the first conductive pads134aand the corresponding second conductive pad(s)134b. The trace(s)148may be formed through the sputtering process illustrated inFIG.7D. In some embodiments, not all of the second conductive pads134bmay be electrically coupled to a corresponding first conductive pad134avia a trace148. Similarly, not all of the first conductive pads134amay be electrically coupled to a corresponding second conductive pad134bvia a trace148. For example, inFIG.7Ethere are thirteen first conductive pads134aand twenty second conductive pads134b. Some of the second conductive pads134bdo not have a trace148electrically connecting the second conductive pad134bto a first conductive pad134a. Similarly, there is a first conductive pad134athat is not electrically connected to a second conductive pad134bvia a trace148. It will be understood that the first conductive pad134aand second conductive pad134band traces148shown inFIG.7Eare examples and that any desired configuration of first and second conductive pads134a,134band traces148may be included. For example, the number of first conductive pads134a, and/or second conductive pads134bmay be different from what is shown inFIG.7E. Similarly, the paths of and/or connections formed by traces148may be different from what is shown inFIG.7E. InFIG.7E, the first conductive pads134aare smaller than the second conductive pads134b, however it will be understood that the first and second conductive pads134a,134bmay be generally the same size and/or shape. Referring toFIG.7F, one or more solder balls124may be coupled to the bottom planar surface126of the first substrate106. In some embodiments, the solder balls124are mechanically and electrically connected to the substrate106such that the solder balls124are in electrical communication with the components of the first semiconductor device package102, as described above in more detail with reference toFIGS.1-2. Referring toFIG.7G, another semiconductor device package (e.g., second semiconductor device package104) may be coupled to the first semiconductor device package102. In some embodiments, the first semiconductor device package102and second semiconductor device package104are electrically coupled to one another, as discussed in more detail with reference toFIGS.1-2. As such the mechanical and/or electrical coupling of the first and second semiconductor device packages102,104will not be described in further detail here for the sake of brevity and so as not to obscure aspects of the present disclosure. Referring toFIG.7H, a liquid underfill140may be provided between the first semiconductor device package102and the second semiconductor device package104via a nozzle150. For example, the nozzle150may be positioned such that an outlet of the nozzle150faces the space between the first semiconductor device package102and the second semiconductor device package104. The liquid underfill140may be flowed through the outlet of the nozzle150such that the underfill140encapsulates the components connecting the first and second semiconductor device packages102,104. In this manner the semiconductor device package100may be assembled. The underfill140is described above with reference toFIGS.1-2and will not be described again for sake of brevity and so as not to obscure aspects of the present disclosure. Referring toFIGS.8A-8B, there is illustrated an alternative assembly of a semiconductor device package (e.g., the first semiconductor device package102) having an exposed bond wire. InFIG.8A, the substrate102, and the components coupled thereto, may be at least partially encapsulated by the first molding compound112in a manner similar to what is illustrated inFIGS.7A-7Bexcept that the top planar surface136of the first molding compound112may entirely encapsulate the bond wire110d. In some embodiments, the molding compound112may be exposed to an etching process (e.g., chemical etching, laser etching, plasma etching), such that a layer of the molding compound112is removed. In this manner, the top planar surface136may be moved closer to the substrate106such that the bond wire110dis at least partially exposed at the top planar surface136of the first molding compound112(as shown inFIGS.7C and8B). The assembly of the combined semiconductor device package100may subsequently include the steps illustrated inFIGS.7D-7H. It will be appreciated by those skilled in the art that changes could be made to the exemplary embodiments shown and described above without departing from the broad inventive concepts thereof. It is understood, therefore, that this invention is not limited to the exemplary embodiments shown and described, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the claims. For example, specific features of the exemplary embodiments may or may not be part of the claimed invention and various features of the disclosed embodiments may be combined. The words “right”, “left”, “lower” and “upper” designate directions in the drawings to which reference is made. Unless specifically set forth herein, the terms “a”, “an” and “the” are not limited to one element but instead should be read as meaning “at least one”. It is to be understood that at least some of the figures and descriptions of the invention have been simplified to focus on elements that are relevant for a clear understanding of the invention, while eliminating, for purposes of clarity, other elements that those of ordinary skill in the art will appreciate may also comprise a portion of the invention. However, because such elements are well known in the art, and because they do not necessarily facilitate a better understanding of the invention, a description of such elements is not provided herein. Further, to the extent that the methods of the present invention do not rely on the particular order of steps set forth herein, the particular order of the steps should not be construed as limitation on the claims. Any claims directed to the methods of the present invention should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the steps may be varied and still remain within the spirit and scope of the present invention. | 51,099 |
11942460 | DETAILED DESCRIPTION Semiconductor device assemblies having a reduced overall volume (e.g., package height) and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device assembly includes a package substrate having a front side and a backside, a controller die connected to the front side of the package substrate, and a stack of semiconductor dies on the controller die. The controller die has a first longitudinal footprint, and the stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The semiconductor device also includes a passive electrical component on the front side of the package substrate (e.g., a passive capacitor) and positioned at least partially within the second longitudinal footprint. The passive electrical component and the controller die support the stack of semiconductor dies. In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology. As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation. Further, although discussed primarily as passive capacitors herein, other passive electrical components may limit the reductions in height of the semiconductor devices disclosed below. Accordingly, the solutions discussed herein with respect to the passive capacitors may also be applied to various other passive components (e.g., resistors, inductors, transformers, or other electrical components) in a semiconductor device. FIG.1Ais a cross sectional view, andFIG.1Bis a top plan view, of a semiconductor assembly100(the “assembly100”) configured without the present technology. With reference toFIG.1A, the assembly100includes a package substrate102having a front side104and a back side106opposite the front side104, a first semiconductor die108(sometimes referred to as the “first die108”) attached to a central portion of the front side104by a die-attach film110, and spacers112attached to the front side104in a pattern around the first die108. The package substrate102can be an interposer substrate, such as a printed circuit board, dielectric spacer, semiconductor die, or another suitable substrate. The spacers112can be silicon or ceramic support columns. The first die108and/or the spacers112can be attached to the package substrate102using die-attach materials such as die-attach films110, epoxies, tapes, pastes, or other suitable materials. As further illustrated inFIG.1A, the assembly100includes a stack of second semiconductor dies114a-f(referred collectively as “second dies114” or “die stack114”) attached to an upper surface109of the first die108and an upper surface113of the spacers112. In the illustrated embodiment, each second die214is attached to the semiconductor die beneath it by a die-attach film116. In other embodiments, each second die114can be attached using various other die-attach materials (e.g., other attach films, epoxies, tapes, pastes, or other suitable materials). Further, each second die114is electrically connected to the package substrate102through a connector118(e.g., wire bonds) bonded to a bond site120(e.g., bond pads) at the front side104of the package substrate102. The assembly100also includes capacitors122(e.g., passive capacitors) attached to a peripheral portion of the front side104and electrically connected to one or more of the bond sites120at the front side104. In some embodiments, the package substrate102can also include various redistribution structures126. In various embodiments, the redistribution structures126can connect the bond sites120to the first die108and/or one or more interconnection elements124on the back side106of the package substrate102. The first semiconductor die108and the second semiconductor dies in the assembly100can each have integrated circuits or components, data storage elements, processing components, and/or other features manufactured on semiconductor substrates. For example, the first and second semiconductor dies108,114can include integrated memory circuitry and/or logic circuitry, which can include various types of semiconductor components and functional features, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, other forms of integrated circuit memory, processing circuits, imaging components, and/or other semiconductor features. In some embodiments, the first and second semiconductor dies108,114can be identical (e.g., memory dies manufactured to have the same design and specifications), but in other embodiments the first semiconductor dies108can be different than the second semiconductor dies114(e.g., different types of memory dies or a combination of controller, logic, and/or memory dies). In one embodiment, for example, the first semiconductor die108can be a controller die, while the second semiconductor dies114are memory and/or other logic dies under the control of the first die108. As further illustrated inFIG.1, the capacitors122have a first height H1while the combination of the first die108and the stack of second semiconductor dies114has a second height H2less than the first height H1. As a result, no matter how thin the second semiconductor dies114are made, the capacitors122define the height of the assembly100. The capacitors122are accordingly the limiting factor in scaling down the overall package height of the assembly100. FIG.2Ais a cross-sectional sideview, andFIG.2Bis a top plan view, of a semiconductor assembly200(the “assembly200”) configured in accordance with some embodiments of the present technology. The assembly200includes a package substrate202having a front side204and a back side206. A first die208is attached to a central portion of the front side204, and a stack of second dies214a-f(referred to collectively as “second dies214” or “die stack214”) is attached to the first die208. The second semiconductor dies214are electrically connected to the package substrate202through connectors218and bond sites220. The assembly200also includes one or more capacitors222sized to fit underneath the die stack214. In the illustrated embodiment, the assembly200includes two or more low-profile capacitors222positioned at least partially underneath the bottom of the die stack214. At least one of the capacitors222is positioned between the first die208and a first edge203aof the substrate202, and at least one of the capacitors222is positioned between the first die208and a second edge203bof the substrate202. That is, while the first die208is positioned in a central portion of the substrate, the capacitors222are positioned in a second portion circumferentially surrounding the central portion. In some embodiments, the assembly200can include four capacitors222but the assembly can have a different number of capacitors222. The number of capacitors222is based on the total capacitance requirement of the assembly200. Accordingly, in various embodiments, the assembly200can include various other numbers of capacitors222(e.g., one capacitor, two capacitors, eight capacitors, or any suitable number of capacitors). Further, in some embodiments, the capacitors222can be selected based on additional parameters such as operating temperature range, capacitance tolerance (e.g., variation in capacitance), size tolerance (variation in size such as height, length, and/or width), voltage rating, and/or other factors. As illustrated inFIG.2A, the capacitors222have a height H3. In some embodiments, the height H3can be generally equal to the height of the combination of the first die208and a die-attach film210so that the upper surface213aof the capacitors222is generally parallel with the upper surface209of the first die208when a lower surface213bof the capacitors222is attached to the substrate202. In these embodiments, the capacitors222are sized to at least partially support the weight of the stack of second dies214. Further, in these embodiments, the height tolerance of the capacitors222can be a substantial factor in the selection of the capacitors222because too much variation in size can cause the stack of second dies214to be unstable, thereby undermining the structural integrity of the assembly200. Since the capacitors222are placed underneath the die stack214, the overall height of the assembly200can be generally equal to the combined height H2of the die stack214and the first die208. As a result, the die thickness of each semiconductor die214becomes a significant factor in the overall package height of the assembly200insert of the capacitor height. Further, as illustrated with reference toFIG.2B, the capacitors222may be wider and/or longer than the tall capacitors122shown inFIG.1so that the capacitors222can fit under the die stack214and provide the total capacitance required for the assembly200. Accordingly, an overall footprint232of the assembly200can be reduced compared to the overall footprint132of the assembly100ofFIG.1. In the embodiment illustrated inFIG.2B, the capacitors222are placed completely within the footprint230. In some embodiments, this placement can allow the overall footprint232to be generally equal to the footprint230of the die stack214. In other embodiments, the capacitors222can also be partially outside of the footprint230. That is, locating the capacitors underneath the second dies214allows the assembly200to shrink in both overall height and overall footprint232. The volume of the assembly200can accordingly be significantly reduced, and/or the capacity and/or speed of the resulting electronic devices can be increased, as discussed in more detail below with respect toFIGS.7and8. FIGS.3-8illustrate various aspects of the assembly configured in accordance with embodiments of the present technology. In each of the illustrated embodiments, the assembly200includes the package substrate202having the front side204and the back side206. The first die208is attached to a central portion of the front side204, one or more capacitors222surround the first die208, and the second dies214are attached to the top of the first die108and the capacitors222 FIG.3is a cross-sectional sideview of the assembly200ofFIG.2Ain accordance with some embodiments of the present technology. The assembly200includes a larger number of capacitors222at least partially within the footprint230of the die stack214. In some embodiments, additional capacitors222can be used to provide the desired total capacitance requirement of the assembly200. In some embodiments, additional capacitors222can be used to further support the stack of die stack214. As a result, the additional capacitors222can increase the stability of the die stack214and thereby improve the durability of the assembly200. FIG.4is a cross-sectional sideview of the assembly200ofFIG.2Ain accordance with some embodiments of the present technology. In the illustrated embodiment, the assembly200also includes spacers212positioned at least partially within the footprint230of the die stack214. The spacers212can be used in combination with the capacitors222to support the die stack214within the footprint230to increase the stability of the die stack214and thereby improve the durability of the assembly200. In some embodiments, the spacers212can be used to support the die stack214in place of the capacitors222, for example when the height of the capacitors222is less than the height of the first die208. As further illustrated inFIG.4, the spacers212can be positioned in a third portion of the substrate202circumferentially outside of the second portion of the substrate202in which the capacitors222are positioned. In various other embodiments, the spacers212and capacitors222can be organized in various other ways. For example, the capacitors222can be positioned circumferentially outside of the spacers212relative to the first die208; the capacitors222and the spacers212can be randomly organized circumferentially outwards relative to the first die208; or the capacitors222and the spacers212can be arranged equidistant from the first die208. FIG.5is a cross-sectional sideview of the assembly200ofFIG.2Ain accordance with some embodiments of the present technology. In the illustrated embodiment, the assembly200also includes an encapsulant material540at least partially encasing each of the capacitors222. The encapsulant material540can provide mechanical support to the stack of second dies214and/or insulation and/or mechanical protection to the capacitors222. For example, the encapsulant material540can be a polyester, a cellulosic material, a thermoset material, or other suitable material. The encapsulant material540can disperse the weight of the die stack214and thereby increase the lifespan of the elements of the assembly200bearing the weight. The encapsulant material540can also stabilize the stack of second dies214, thereby increasing the lifespan of the assembly200. In some embodiments, the encapsulant material540can be more accurately tailored to the height of the first die208to account for differences in height among capacitors222as passive devices may not be manufactured to precise dimensions. For example, the encapsulant material540can be used to accurately match the height of the first die208. FIG.6is a cross-sectional sideview of the assembly200ofFIG.2Ain accordance with embodiments of the present technology in which the assembly200includes a first encapsulant material640encasing both the capacitors222and the first die208and a second encapsulant material650encasing the other semiconductor elements in the assembly200. In some embodiments, the first encapsulant material640can have a footprint642generally equal to the footprint230of the die stack214. In some embodiments, the first encapsulant material640supports and stabilizes the die stack214over a greater area to increase the lifespan of the assembly200. The first encapsulant material640can have a height H4larger than the height of the first die208and the capacitors222such that an upper surface644of the spacer material can be planarized to provide a very planar surface to which the stack of second dies214is attached. In some embodiments, the first encapsulant material640has multiple heights. For example, one portion of the first encapsulant material640can have a first height generally corresponding to the height of the capacitors222and another portion of the encapsulated material640can have a second height different than the first height generally corresponding to the height of the first die208. The variation in height can be used, for example, to expose the upper surface209(FIG.2A) of the first die208for electrical connection. The first encapsulant material640can also protect and/or electrically isolate the first die208to further extend the lifespan of the assembly200. The second encapsulant material650can further protect and/or insulate any exposed portions of the capacitors222. FIGS.7and8are cross-sectional side views of the assembly200ofFIG.2Ain accordance with embodiments of the present technology.FIG.7shows the die stack214including four semiconductor dies214a-d. As a result, the height H5of the stack of second dies214and the first die208can be reduced as compared to the embodiment of the assembly200illustrated inFIG.2.FIG.8shows the stack of second dies214three semiconductor dies214a-c. As a result, the height H6of the stack of second dies214and the first die208is further reduced compared to the embodiment of the assembly200illustrated inFIG.7. In some embodiments of the present technology, a plurality of assemblies200can be used in a single computing system. In some embodiments, the reduction in the overall footprint232of each assembly200can be used in conjunction with the height reductions illustrated inFIGS.7and8to select between packing additional semiconductor dies into a longitudinal area, reducing the size of the longitudinal area, and/or reducing the height of each assembly200in the longitudinal area. For example, because the overall footprint232is small more assemblies200can be packed into a longitudinal area. Accordingly, if the number of second semiconductor dies214a-N in the stack does not change, more semiconductor dies are packed in the longitudinal area. Alternatively, in some embodiments, the height of each assembly can be relatively low as illustrated inFIGS.7and8, while the total number of semiconductor dies in the longitudinal area does not change. In some embodiments, sufficient space can be gained through the reduction in the overall footprint232of each assembly200to allow the height of each assembly to be reduced while the total number of semiconductor dies increases. In these embodiments, the size of the electronic device can shrink while the capacity and/or speed of the resulting electronic device increases. FIGS.9A-9Eillustrate the assembly200ifFIG.2Aat various stages of a method of manufacturing in accordance with some embodiments of the present technology.FIG.9Ais a cross-sectional sideview of the assembly200ofFIG.2Abefore any of the semiconductor elements have been attached to the package substrate202. In the illustrated embodiment, the bond sites220have been formed on the front side204of the package substrate202and the interconnect elements224have been attached to the back side206of the package substrate202. In some embodiments, the interconnect elements224can be attached to the back side206at various other points in the method. For example, in some embodiments, the method can attach the interconnect elements224after the assembly200is otherwise complete. FIG.9Bis a cross-sectional sideview of the assembly200ofFIG.2Aafter the capacitors222have been mounted (e.g., positioned, and/or placed, attached, etc.) on the front side204of the package substrate202in accordance with some embodiments of the present technology. In some embodiments, the capacitors222can be adhered to the front side204of the package substrate202by various attach films, epoxies, tapes, pastes, and/or other suitable materials. In some embodiments, the method includes encasing the capacitors222with an encapsulant material (for example as shown inFIG.5). The method can also include planarizing an upper surface of the encapsulant material (e.g., through a planarization process). By covering the capacitors222before any other elements are added to the assembly200, the method can reduce the potential of damaging the other elements from the planarization. FIG.9Cis a cross-sectional sideview of the assembly200ofFIG.2Aafter the first die208has been mounted to the front side204of the package substrate202in accordance with some embodiments of the present technology. In some embodiments, the method includes covering the capacitors222and the first die208with an encapsulant material (for example as shown inFIG.6) and optionally planarizing an upper surface of the encapsulant material. As disclosed above, by encapsulating both the capacitors222and the first die208and then planarizing an upper surface of the encapsulant material, the stability of the assembly200is expected to be enhanced. The method can optionally include mounting spacers212to front side204of the package substrate202, such as described above with respect toFIG.4. The spacers are expected to support the die stack214. In some embodiments, the spacers212are used when the variation in the height of the capacitors222is outside of a tolerance range for the assembly200. FIG.9Dis a cross-sectional sideview of the assembly200ofFIG.2Aafter two second semiconductor dies214a,214bhave been attached to the capacitors222and the first die208. The second semiconductor dies214a,214bcan be attached using a die-attach film216. In various other embodiments, the second semiconductor dies214a,214bcan be attached using other adhesive films, epoxies, tapes, pastes, or other suitable materials. In the illustrated embodiment, the lowermost second semiconductor die214ahas a footprint larger than the footprint of the first die208. Accordingly, the lowermost second semiconductor die214acan be positioned to be supported by the capacitors222and the first die208(e.g., the lowermost second die114ais centered above the capacitors222and the first die208). In some embodiments, the lowermost second semiconductor die214ais positioned to distribute the overall weight of the die stack214. The lowermost semiconductor die214acan accordingly be positioned to generally distribute the weight of the lowermost semiconductor die214aand/or the full die stack214evenly across the capacitors22and the first die208. As further illustrated byFIG.9D, the next second semiconductor die214bcan be attached to the lowermost second semiconductor die214aand positioned to leave at least a portion of an upper surface of the lowermost second semiconductor die214aexposed for electrically connecting the lowermost second semiconductor die214ato the package substrate202(e.g., using the connectors218illustrated inFIG.2A). In some embodiments, the second semiconductor dies214a,214bcan alternatively be stacked in direct alignment with each other and electrically connected using through-silicon vias (TSVs) and/or flip-chip bonding. Further, the second semiconductor dies114a,214bcan be electrically connected to the first die208using through-silicon vias (TSVs), flip-chip bonding, and/or through a one or more wire bonds on an uppermost semiconductor die connected to the package substrate202. FIG.9Eis a cross-sectional sideview of the assembly200ofFIG.2Aafter four additional second semiconductor dies214c-fhave been stacked (e.g., mounted above) on top of the second semiconductor dies214a,214b. Each of the additional second semiconductor dies214c-fcan be attached using the die-attach film216and positioned to at least partially expose the upper surface of the immediately lower second semiconductor dies214b-eto which they are attached. The additional second semiconductor dies214c-fcan alternatively be stacked in direct alignment with each other (e.g., with no overhang or exposed portions) and electrically connected using through-silicon vias (TSVs) and/or flip-chip bonding. In some embodiments, the die stack214can be configured such that its weight is distributed evenly among the capacitors222and the first die208. For example, in the illustrated embodiment, the lowermost second semiconductor die214aand the uppermost second semiconductor die214fare generally centered over the capacitors222and the first die208, while the middle second semiconductor dies214b-dare sequentially offset from each other by equal distances on both sides. Any one of the semiconductor devices having the features described above with reference toFIGS.2A-8can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system1000shown schematically inFIG.10. The system1000can include a memory1090substantially as described above (e.g., SRAM, DRAM, flash, and/or other memory devices), a power supply1092, a drive1094, a processor1096, and/or other subsystems or components1098. The semiconductor devices described above with reference toFIGS.2A-9can be included in any of the elements shown inFIG.10. For example, the memory1090can be a DDR5 DIMM. The resulting system1000can be configured to perform any of a wide variety of suitable computing, processing, storage, sensing, imaging, and/or other functions. Accordingly, representative examples of the system1000include, without limitation, computers and/or other data processors, such as desktop computers, laptop computers, Internet appliances, hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablets, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of the system1000include lights, cameras, vehicles, etc. With regard to these and other example, the system1000can be housed in a single unit or distributed over multiple interconnected units, e.g., through a communication network. The components of the system1000can accordingly include local and/or remote memory storage devices and any of a wide variety of suitable computer-readable media. From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. Furthermore, certain aspects of the present technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. For example, the various embodiments described with reference toFIGS.2A-9may be combined to incorporate different numbers of stacked semiconductor dies (e.g., three dies, five dies, six dies, eight dies, etc.) that are laterally offset in different manners. Accordingly, the invention is not limited except as by the appended claims. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein. | 26,549 |
11942461 | DESCRIPTION OF PREFERRED EMBODIMENTS In order to make the purpose, technical solutions, and effects of this application clearer, the following further describes this application in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and not used to limit the application. In the drawings, the sizes of certain layers and regions are exaggerated for better understanding and ease of description. As shown inFIG.1,FIG.1is a primary schematic structural view of a bezel-less display panel provided by an embodiment of the present application. The bezel-less display panel is divided into a first display area101, a second display area102around the first display area101, and a third display area103around the second display area102. Each of the first display area101and the second display area102is provided with a plurality of subpixel driving thin-film transistors (TFTs) (not shown). The subpixel driving TFTs in the first display area101have a distribution density equal to a distribution density of the subpixel driving TFTs in the second display area102. It should be noted thatFIG.1is a schematic view showing a subpixel driving circuit104in the first display area101and a subpixel driving circuit105in the second display area102, wherein the subpixel driving circuit104includes at least one of the subpixel driving TFTs, and the subpixel driving circuit105also includes at least one of the subpixel driving TFTs. Since details of the subpixel driving circuits104and105are not the focus of this application, a detailed structural view is not provided, nor is it described in detail. The subpixel driving circuits104and105are required only to drive light-emitting subpixels, and circuit details are not limited in this application. In addition, it should be noted that the subpixel driving circuits104and105are generally located below light-emitting subpixels106and107, and for easy understanding of their relative positions,FIGS.1and2are both drawn from a top view angle. In addition, due to the top view angle, the subpixel driving circuits104,105and the light-emitting subpixels106,107have a partially overlapping configuration. Please refer toFIGS.1and2. Each of the first display area101, the second display area102, and the third display area103is provided with a plurality of light-emitting subpixels106,107,108. A distribution density of the light-emitting subpixels106in the first display area101is greater than that of the light-emitting subpixels107in the second display area102. Please refer toFIG.2. There are no subpixel driving TFTs provided in the third display area103. Some of the subpixel driving TFTs (arranged in a subpixel driving circuit2041) in the second display area102are connected to the light-emitting subpixels107in the second display area102, respectively. The other subpixel driving TFTs (arranged in a subpixel driving circuit2042) in the second display area102are connected to the light-emitting subpixels202,205in the third display area103through a plurality of metal lines203,206. It should be noted that bezel-less displaying can be achieved by setting a distribution density of the subpixel driving TFTs (arranged in a subpixel driving circuit204) in the second display area102equal to a distribution density of the subpixel driving TFTs (arranged in a subpixel driving circuit104) in the first display area101, and a distribution density of the light-emitting subpixels107in the second display area102less than a distribution density of the light-emitting subpixels106in the first display area101. That is, the light-emitting subpixels107in the second display area102are only connected to some of the subpixel driving TFTs (arranged in a subpixel driving circuit2041) in the second display area102. Furthermore, the third display area103is not provided with any subpixel driving TFT, and the light-emitting subpixels202,205in the third display area103are connected to the other subpixel driving TFTs (arranged in a subpixel driving circuit2042) in the second display area102through the metal lines203,206, so that configuration of gate lines and driving circuits is not influenced. In one embodiment, a sum of number of the light-emitting subpixels107in the second display area102and number of the light-emitting subpixels202,205in the third display area103is equal to number of the subpixel driving TFTs (arranged in the subpixel driving circuit204) in the second display area102. That is, each of the light-emitting subpixels107in the second display area102and each of the light-emitting subpixels202,205in the third display are 103 correspond to the subpixel driving TFTs (arranged in the subpixel driving circuit204) in the second display area102. Each of the subpixel driving TFTs is corresponding to one of the light-emitting subpixels. In the embodiment of the present application, a distribution density of the light-emitting subpixels in the second display area102is reduced, and some of the light-emitting subpixels are distributed to cross to the third display area103(corresponding to an outer frame area in prior art), so that a complete full screen display can be achieved, and splicing marks can be prevented when forming a spliced large-sized panel. In one embodiment, the bezel-less display panel further includes a source driving circuit109, which is configured to control a voltage (gray scale value) of the light-emitting subpixels to display corresponding brightness. Since the source driving circuit109is generally located in the third display area103(corresponding to an outer frame area in prior art), the third display area103is not available to be provided with a subpixel driving circuit, causing the conventional outer frame area to be incapable of displaying, and a size of the conventional outer frame area is very difficult to be reduced. In order to overcome the above-mentioned problem, the present application is to dispose some of the light-emitting subpixels in the third display area103(corresponding to the conventional outer frame area). The light-emitting subpixels202,205in the third display area103are connected to the other subpixel driving TFTs (arranged in the subpixel driving circuit2042) in the second display area102through the metal lines203,206, thereby to achieve bezel-less display and to prevent configuration of gate lines and driving circuits from being influenced. Please refer toFIG.1. In one embodiment, the light-emitting subpixels include a plurality of red subpixels110, a plurality of green subpixels111, and a plurality of blue subpixels112. Specifically, one of the red subpixels110, two of the green subpixels111, and one of the blue subpixels112cooperatively define a pixel unit. The light-emitting subpixels are arranged in an array and are configured with a plurality of the pixel units comprising a first pixel unit113and a second pixel unit114. In the first pixel unit113, two of the green subpixels111are located on a same side, and one of the red subpixels110and one of the blue subpixels112are located on another side. In the second pixel unit114, two of the green subpixels111are located on a same side, and one of the red subpixels110and one of the blue subpixels112are located on another side, wherein the one of the blue subpixels112is located above the one of the red subpixels110. Any row of the pixel units is configured with a plurality of the first pixel units and the second pixel units arranged in a repeating order of the first pixel unit113to the second pixel unit114. In one embodiment, each of the light-emitting subpixels is circular, triangular, or rectangular in shape. For example, inFIG.1, the red subpixel110and the blue subpixel112are both rectangular in shape, and the green subpixel111is circular in shape. In one embodiment, each of the green subpixels111has a light-emitting area less than a light-emitting area of each of the red subpixels110and blue subpixels112. It should be noted that since brightness of the red subpixel110and the blue subpixel112is attenuated faster and the lifespan is shorter, the red subpixel110and the blue subpixel112is configured with a larger area, so that the brightness attenuation and lifetime of the three types of pixels are uniform. Please refer toFIG.4. In one embodiment, the green subpixels111are disposed corresponding to middle and lower positions with respect to the red subpixels110and the blue subpixels112. Specifically, taking the second pixel unit114as an example, one of the green subpixels111corresponds to a position between the red subpixel110and the blue sub-pixel112, and the other green subpixel111corresponds to a lower position of the red subpixel110. As a whole, the green subpixels111are disposed in staggered relationship with the red subpixels110and the blue subpixels112. The green subpixels111are disposed to correspond to positions between the red subpixels110and the blue subpixels112. As shown inFIG.2, it is a primary schematic structural view of a bezel-less display panel provided by another embodiment of the present application. The bezel-less display panel is divided into a first display area101, a second display area102around the first display area101, and a third display area103around the second display area102. A plurality of the subpixel driving TFTs106in the first display area101are connected to a plurality of subpixel driving TFTs of a plurality of the subpixel driving circuits104in the first display area101through a plurality of metal lines201, respectively. The second display area102includes a first straight area1021and a first corner area1022, and the third display area103includes a second straight area1031and a second corner area1032. The light-emitting subpixels202in the second straight area1031are connected to the subpixel driving TFTs of the subpixel driving circuits204in the first straight area1021through a plurality of the metal lines203, respectively. The light-emitting subpixels205in the second corner area1032are connected to the subpixel driving TFTs of a plurality of subpixel driving circuits207in the first corner area1022through a plurality of the metal lines206, respectively. In one embodiment, the metal lines203configured to connect the light-emitting subpixels202in the second straight area1031to the subpixel driving TFTs in the first straight area1021are arranged substantially in a horizontal direction (left and right sides) or in a vertical direction (upper and lower sides). The metal lines203inFIG.2are not drawn in a horizontal direction for the reason of easy understanding. The metal lines206configured to connect the light-emitting subpixels205in the second corner area1032to the subpixel driving TFTs in the first corner area1022are arranged in an oblique direction, wherein a first angle a is formed between the oblique direction and the horizontal direction or the vertical direction. The first angle a is an acute angle. Specifically, the first angle a is greater than 0 degree and less than or equal to 45 degrees. It should be noted that in the embodiment, the second display area102is divided into the first straight area1021and the first corner area1022, the third display area103is divided into the second straight area1031and the second corner area1032, then the light-emitting subpixels202in the second straight area1031are connected to the subpixel driving TFTs in the first straight area1021. The light-emitting subpixels205in the second corner area1032are connected to the subpixel driving TFTs in the first corner area1022. That is, by transversely or longitudinally arranging the light-emitting subpixels in the first straight area1021, and by disposing the light-emitting subpixels in the first corner area1022at the first angle a in the oblique direction, all the light-emitting subpixels can be evenly arranged, and display quality can be improved. As shown inFIG.2, in one embodiment, the bezel-less display panel further includes the source driving circuit109and a gate driver on array (GOA) driving circuit208. The GOA driving circuit208is configured to control switching on or switching off of any row of the light-emitting subpixels. The GOA driving circuit208includes at least a GOA TFT (corresponding to a GOA TFT312inFIG.3). Since the GOA driving circuit208is generally configured in the third display area103(corresponding to a conventional outer frame area), the third display area103is not available for disposing of a subpixel driving circuit, thereby causing the conventional outer frame area to be incapable of displaying, and a size of the conventional outer frame area is very difficult to be reduced. In order to overcome the above-mentioned problem, the present application is to dispose some of the light-emitting subpixels in the third display area103(corresponding to the conventional outer frame area). The light-emitting subpixels in the third display area103are connected to the other subpixel driving TFTs in the second display area102through the metal lines, thereby to achieve bezel-less display and to prevent configuration of gate lines and driving circuits from being influenced. As shown inFIG.3, it is a schematic cross-sectional view of a second display area and a third display area of a bezel-less display panel provided by the present application. From the figure, you can clearly see various components of this application and relative positional relationships between the various components. The bezel-less display panel includes a buffer layer301, a subpixel driving circuit105disposed on the buffer layer301and corresponding to the second display area102, a subpixel driving TFT disposed in the subpixel driving circuit105, the GOA TFT312on the buffer layer301and corresponding to the third display area103, a planarization layer313disposed on the subpixel driving circuit105and the GOA TFT312, and a pixel electrode314disposed on the planarization layer313, a pixel definition layer316disposed on the planarization layer313, a light-emitting subpixel317disposed on the pixel electrode314and corresponding to the second display area102, a light-emitting subpixel318disposed on the pixel electrode314and corresponding of the third display area103, and a supporting spacer319disposed on the pixel definition layer316. A substrate (not shown) may be disposed below the buffer layer301. The subpixel driving TFT located in the subpixel driving circuit105includes an active layer302, a first insulating layer303disposed on the active layer302, a first metal layer304disposed on the first insulating layer303, a second insulating layer305disposed on the first metal layer304, a second metal layer306disposed on the second insulating layer305, a third insulating layer307disposed on the second metal layer306, and a source308and a drain309disposed on the third insulating layer307. The source308is connected to one end of the active layer302through a first via310, and the drain309is connected to the other end of the active layer302through a second via311. The pixel electrode314is connected to the source308through a third via315. It should be noted that the light-emitting subpixel318in the third display area103is connected to the subpixel driving TFTs of the subpixel driving circuit105in the second display area102through a metal line320. Specifically, the metal line320described here may be disposed on the same layer as the pixel electrode314, and the light-emitting subpixel318in the third display area103is connected to the source308through the metal line320. The embodiment of the present application utilizes the subpixel driving TFTs of the subpixel driving circuit105in the second display area102to control the light-emitting subpixels in the third display area103, so that bezel-less display can be achieved and configuration of gate lines and driving circuits will not be influenced. It should be noted that the third display area103may not be provided with a thin-film transistor. That is, the GOA TFT312can be configured in other ways, and is not limited to the disclosure of the present application. Please refer toFIG.5. An embodiment of the present application provides a display device10, including a back frame11, and a bezel-less display panel12disposed on the back frame11, wherein the bezel-less display panel12is the bezel-less display panel provided in the above-mentioned embodiments. Please refer toFIGS.1and2for details, which are not repeated here. Please refer toFIG.6. An embodiment of the present application provides a splice-type display device20, including a back frame21, and a plurality of bezel-less display panels22. The plurality of bezel-less display panels22are disposed on the back frame21and spliced into a display surface, wherein each of the bezel-less display panels22is the bezel-less display panel provided by the above-mentioned embodiments. Please refer toFIGS.1and2for details, which are not repeated here. It should be noted that each one of the bezel-less display panels can work independently. There are no splicing marks occurred in a splice-type display panel when using the bezel-less display panels provided by the embodiments of the present application, thereby preventing adverse influence on display performance. Accordingly, based on a bezel-less display panel provided by the embodiment of the present application, a display area of a display panel is divided into a first display area, a second display area around the first display area, and a third display area around the second display area. A plurality of subpixel driving TFTs provided in the first display area have a distribution density equal to a distribution density of a plurality of subpixel driving TFTs provided in the second display area. A distribution density of light-emitting subpixels in the first display area is greater than that of the light-emitting subpixels in the second display area. The third display area is not provided with a subpixel driving TFT. Some of the subpixel driving TFTs in the second display area are connected to the light-emitting subpixels in the second display area, and the other subpixel driving TFTs in the second display area are connected to the light-emitting subpixels in the third display area. In this manner, a bezel-less display can be achieved, a screen aspect ratio, as well as a product application range, can be increased, and display differences caused by splicing marks can be prevented, thereby overcoming technical problems with conventional display panels which have a low screen aspect ratio caused by outer frames being incapable of displaying, and which form splicing marks when being configured to be spliced into a large-sized display, adversely affecting display performance. It can be understood that for those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solutions and inventive concepts of the present application, and all these changes or substitutions shall fall within the protection scope of the appended claims of the present application. | 19,161 |
11942462 | DETAILED DESCRIPTION OF THE EMBODIMENT It should be noted that, wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Referring toFIGS.2and3,FIG.2is an exploded schematic diagram of an optical navigation module100according to one embodiment of the present disclosure, andFIG.3is a combined perspective view of the optical navigation module100shown inFIG.2. The optical navigation module100includes an optical package13and a reflective structure15, wherein the reflective structure covers on the optical package13and is configured to reflect incident light Lin and illumination light Lout (described hereinafter). The reflective structure15is made, for example, by molding, and a cross section of the reflective structure15is larger than, equal to or smaller than that of the optical package13without particular limitations as long as the light propagating therein is reflected. The optical package13includes a light emitting chip131and an image sensor133. The image sensor133includes, for example, a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor or other sensors for converting optical energy to electric signals. The image sensor133has a sensor surface133S, and the incident light Lin impinges on the sensor surface133S. The light emitting chip131includes, for example, a light emitting diode or a laser diode, and is configured to emit illumination light Lout toward a normal line direction n of the sensor surface133S, wherein the illumination light Lout is configured to provide light required by the image sensor133in capturing images. The method of encapsulating a light emitting chip and an image sensor in an optical package is known to the art and thus details thereof are not described herein. The reflective structure15includes a first reflective portion151, a second reflective portion153, a detection plane155and a detection opening1551, wherein when the reflective structure15is covered on the optical package13, the detection plane155is substantially perpendicular to the sensor surface133S, but not limited thereto. In other embodiments, the detection plane155is a tilt surface. The detection opening1551is located at the detection plane155and opposite to an object O, e.g. a tracking surface. The detection opening1551is for the illumination light Lout emitted from the light emitting chip131to leave the reflective structure15and for the reflected light from the object O (i.e. the incident light Lin) to enter the reflective structure15. A shape and size of the detection opening1551do not have particular limitations as long as the light can leave and enter therethrough. The object O is fixed or movable with respect to the detection opening1551according to different applications. The first reflective portion151and the second reflective portion153are formed inside the reflective structure15. The first reflective portion151has a first end151feand a second end151se, wherein the first end151feof the first reflective portion151is substantially aligned with the image sensor133(preferably aligned with the sensor surface133S thereof) and the second end151seof the first reflective portion151connects to the detection opening1551. The first reflective portion151is configured to reflect incident light Lin to impinge on the sensor surface133S, wherein the incident light Lin parallel to the sensor surface133S is reflected to perpendicular to the sensor surface133S. As mentioned above, the incident light Lin is generated by the object O from reflecting the illumination light Lout. More specifically, the reflective structure15further includes, in the first reflective portion151(e.g. at the region filled with inclined lines), at least one of a reflective surface, a prism having one surface thereof being a reflective surface and a diffractive optical element (DOE) having one surface thereof being a reflective surface configured to reflect the light propagating therein, e.g. the incident light Lin. The reflective surface is formed by coating a reflective layer on an inner surface of the first reflective portion151, wherein the reflective layer is a metal layer, a non-metal layer or a combination thereof without particular limitations as long as a target spectrum (e.g. a sensing spectrum of the image sensor133) is effectively reflected. The prism is, for example, a total internal reflective (TIR) prism which is disposed at a suitable position in the first reflective portion151. The second reflective portion153has a first end153feand a second end153se, wherein the first end153feof the second reflective portion153is substantially aligned with the light emitting chip131and the second end153seof the second reflective portion153connects to the detection opening1551. The second reflective portion153is configured to reflect the illumination light Lout in the normal line direction n emitted by the light emitting chip131to parallel to the sensor surface133S and eject from the reflective structure15, i.e. through the detection opening1551. More specifically, the reflective structure15further includes, in the second reflective portion153(e.g. at the region filled with inclined lines), at least one of a reflective surface, a prism having one surface thereof being a reflective surface and a diffractive optical element having one surface thereof being a reflective surface configured to reflect the light propagating therein, e.g. the illumination light Lout in the normal line direction n emitted by the light emitting chip131. The formation of the reflective surface, prism and diffractive optical element of the second reflective portion153is similar to that of the first reflective portion151. The first reflective portion151and the second reflective portion153are separated by a wall157arranged therebetween. In the above embodiments, the reflective surface, prism and diffractive optical element is formed, e.g. by coating a reflective layer, or disposing a reflective mirror, a prism having one surface thereof being a reflective surface or a diffractive optical element having one surface thereof being a reflective surface manufactured separately, after the reflective structure15is formed by a molding process. It should be mentioned that although in the present disclosure the reflective structure15is substantially shown to be a rectangular cylinder, it is only intended to illustrate but not to limit the present disclosure. In some embodiments, the detection plane155of the reflective structure15includes two detection openings which respectively connect to the second end of the first reflective portion151and the second end of the second reflective portion153according to different applications. It should be mentioned that althoughFIGS.2and3show that the reflective structure15is a single structure and includes both the first reflective portion151and the second reflective portion153, they are only intended to illustrate but not to limit the present disclosure. In other embodiments, the reflective structure15is formed by two molding structures which respectively include the first reflective portion151and the second reflective portion153. Referring toFIG.4, it is a side view of an optical navigation module100according to one embodiment of the present disclosure. The optical navigation module100further includes a substrate11, for example, but not limited to, a printed circuit board (PCB) or a flexible circuit board (FCB), for disposing the optical package13. For example, the substrate11has an upper surface11S on which a plurality of traces and electronic components are formed. The optical package13is disposed on the upper surface11A and electrically connected to the substrate11, e.g. via a plurality of conductive pins135. When the optical package13is disposed on the substrate11, the sensor surface133S of the image sensor133is substantially parallel to the upper surface11S of the substrate11, wherein the method of electrically connecting an optical package to a substrate is known to the art and thus details thereof are not described herein. Accordingly, the light emitting chip131emits illumination light Lout toward a normal line direction n of the upper surface11S of the substrate11. By employing the reflective structure15, the illumination light Lout (e.g. reflected illumination light) emitted from the light emitting chip131ejects out a range of the optical package13from a side (e.g. the right side shown inFIG.4) of the optical package13, and the incident light Lin from outside (e.g. the reflected light from the object O) is incident into the range of the optical package13from the same side of the optical package13. Referring toFIG.5, it is another schematic diagram of an optical navigation module100according to one embodiment of the present disclosure. The optical navigation module100further includes a condensing lens19configured to focus the reflected incident light so as to improve the sensing efficiency of the image sensor133, wherein the condensing lens19is a biconvex lens or a plano-convex lens without particular limitations as long as it has the light focusing function. In some embodiments, the optical navigation module100further includes an intermediate layer17sandwiched between the optical package13and the reflective structure15(referring toFIG.4), and the condensing lens19is formed in the intermediate layer17, wherein the intermediate layer17is further configured as a protection layer of the image sensor133, e.g. a glass layer or a transparent plastic layer, but not limited thereto. In other embodiments, the condensing lens19is integrated with the reflective structure15, e.g. at the first end of the first reflective portion15, so as to opposite to the image sensor133. In other embodiments, the condensing lens19is directly integrated with the optical package13and aligned with the image sensor133. It should be mentioned that althoughFIGS.2-4show that the optical navigation module100includes a reflective structure15covering on the optical package13, they are only intended to illustrate but not to limit the present disclosure. In some embodiments, the optical navigation module100does not include the reflective structure15but further includes two light reflective elements disposed on the optical package13or the substrate11(e.g. via supporting members). For example, referring toFIG.4again, when the reflective structure15is not included, the optical navigation module100includes a first light reflective element161and a second light reflective element163, wherein the first light reflective element161and the second light reflective element163are reflective mirrors, prisms having one surface thereof being a reflective surface or diffractive optical elements having one surface thereof being a reflective surface. For example,FIG.5shows that the first light reflective element161is a reflective mirror, and the second light reflective element163is similar to the first light reflective element161without showing inFIG.5. The first light reflective element161is configured to reflect incident light parallel to the upper surface11S of the substrate11to perpendicular to the upper surface11S of the substrate11to impinge on the sensor surface133S, wherein a function of the first light reflective element161is similar to that of the first reflective portion151. The second light reflective element163is configured to reflect illumination light in the normal line direction n emitted by the light emitting chip131to parallel to the upper surface11S of the substrate11, wherein a function of the second light reflective element163is similar to that of the second reflective portion153. It should be mentioned that the spatial relationship between the incident light Lin and the illumination light Lout shown inFIG.4is only intended to illustrate but not to limit the present disclosure. Referring toFIG.5again, it schematically shows a transverse distance Dh between the object O and the first light reflective element161(or the first reflective portion151), and a vertical distance Dv between the image sensor133and the first light reflective element161(or the first reflective portion151), wherein the vertical distance Dv is adjustable. More specifically, a vertical distance between the reflective structure15and the optical package13is adjustable, or a vertical distance between the first light reflective element161and the optical package13is adjustable. As mentioned above, a condensing lens19is disposed between the first light reflective element161(or the first reflective portion151) and the image sensor133for improving the sensing efficiency. In some embodiments, the optical navigation module100further includes a processor111, e.g. a microprocessor, a digital signal processor, a micro controller or the like, disposed on the substrate11and electrically connected to the substrate11, wherein the processor111is configured to adjust the vertical distance Dv via at least one motor (e.g. the miniature electric motor or pizoelectric motor, but not limited to)113, e.g. controlled by a user or automatically controlled according to the image quality of images captured by the image sensor133. In this embodiment, rising or reducing a height of the first light reflective element161(or the reflective structure15) changes the vertical distance Dv from the optical package13to further change an optimum transverse distance Dh (i.e. the tracking distance) thereby realizing the object of adjusting the tracking distance. For example, table 1 shows the relationship between the transverse distance Dh and the vertical distance Dv, but the present disclosure is not limited thereto. TABLE 1transverse distancevertical distanceDh (mm)Dv(mm)4.404.344.104.583.704.833.355.073.005.322.655.572.355.82 In addition, it should be mentioned that in the optical navigation module100according to the present disclosure, light parallel to the sensor surface133S (or the upper surface11S) is referred to that a main propagation direction of the light is parallel to the sensor surface133S (or the upper surface11S) but has a deviation between, for example, about +/−10 degrees from the sensor surface133S (or the upper surface11S) according to different applications; and light perpendicular to the sensor surface133S (or the upper surface11S) is referred to that a main propagation direction of the light is perpendicular to the sensor surface133S (or the upper surface11S) but has a deviation between, for example, about +/−10 degrees from the normal line direction n of the sensor surface133S (or the upper surface11S) according to different applications. It should be mentioned that although in the present disclosure the optical package13is shown to include both the image sensor133and the light emitting chip131, it is only intended to illustrate but not to limit the present disclosure. In some embodiments, when an external light source existing outside of the optical navigation module100or environmental light is strong enough, the optical package100includes only the image sensor133without including the light emitting chip131according to different applications. As mentioned above, the conventional optical navigation system is not designed to detect a tracking surface or an object not parallel to a main board thereof, and thus a separate circuit board is required to be connected to the main board such that it has high cost and needs complicated handling. Therefore, the present disclosure further provides an optical navigation module (FIGS.2-5) that employs a reflective structure to change propagating directions of illumination light and incident light such that it is able to detect a tracking surface or an object at an arbitrary angle with respect to the main board to lower cost and save space. Although the disclosure has been explained in relation to its preferred embodiment, it is not used to limit the disclosure. It is to be understood that many other possible modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the disclosure as hereinafter claimed. | 16,206 |
11942463 | DETAILED DESCRIPTION Hereinafter, the example embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG.1is a schematic block diagram illustrating a semiconductor device according to example embodiments. Referring toFIG.1, a semiconductor device10may include a memory cell array20and a peripheral circuit30. The peripheral circuit30may include a row decoder32, a page buffer34, an input/output (I/O) buffer35, a control logic36, and a voltage generator37. The memory cell array20may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells. The plurality of memory cells may be connected to the row decoder32through a string select line SSL, word lines WL, and a ground select line GSL, and may be connected to the page buffer34through bit lines BL. In example embodiments, a plurality of memory cells arranged in an identical row may be connected to an identical word line WL, and a plurality of memory cells arranged in an identical column may be connected to an identical bit line BL. The row decoder32may decode an address ADDR, having been input, and may thus generate and transmit driving signals of the word line WL. The row decoder32may provide a word line voltage, generated by the voltage generator37, to a selected word line WL and unselected word lines WL, in response to control of the control logic36. The page buffer34is connected to the memory cell array20through the bit lines BL, and thus read information stored in the memory cells. The page buffer34may temporarily store data to be stored in the memory cells, or may sense data, stored in the memory cell, according to a mode of operation. The page buffer34may include a column decoder and a sense amplifier. The column decoder may selectively activate bit lines BL of the memory cell array20, while the sense amplifier may sense a voltage of a bit line BL, selected by the column decoder, and may thus read data, stored in a memory cell, having been selected. The I/O buffer35may receive data DATA and transfer the data to the page buffer34during a programming operations, and may output the data DATA, transferred by the page buffer34, externally, during a reading operation. The I/O buffer35may transmit address or command, having been input, to the control logic36. The control logic36may control operation of the row decoder32and the page buffer34. The control logic36may receive a control signal and an external voltage, transmitted from an external source, and may be operated according to a control signal, having been received. The control logic36may control reading, writing, and/or erasing operations in response to the control signals. The voltage generator37may generate voltages, for example, programming voltage, reading voltage, erasing voltage, and the like, required for an internal operation using an external voltage. The voltage, generated by the voltage generator37, may be transferred to the memory cell array20through the row decoder32. FIG.2is an equivalent circuit diagram of a cell array of a semiconductor device according to example embodiments. Referring toFIG.2, the memory cell array20may include a plurality of memory cell strings S, each of which includes memory cells MC connected to each other in series, and a ground select transistor GST and string select transistors SST1and SST2connected to both ends of the memory cells MC in series. The plurality of memory cell strings S may be connected to respective bit lines BL0to BL2in parallel. The plurality of memory cell strings S may be connected to a common source line CSL in common. The plurality of memory cell strings S may be disposed between the plurality of bit lines BL0to BL2and a single common source line CSL. In an example embodiment, a plurality of common source lines CSL may be arranged two-dimensionally. The memory cells MC, connected to each other in series, may be controlled by word lines WL0to WLn for selecting the memory cells MC. Each of the memory cells MC may include a data storage element. Gate electrodes of the memory cells MC, arranged at substantially the same distance from the common source line CSL, may be commonly connected to one of the word lines WL0to WLn and may be in an equipotential state. Alternatively, even when the gate electrodes of the memory cells MC are arranged at substantially the same distance from the common source line CSL, gate electrodes, disposed in different rows or columns, may be controlled independently. The ground select transistor GST may be controlled by a ground select line GSL, and may be connected to a common source line CSL. The string select transistors SST1and SST2may be controlled by the string select lines SSL1and SSL2, and may be connected to the bit lines BL0to BL2.FIG.2illustrates a structure in which a single ground select transistor GST and two string select transistors SST1and SST2are connected to the plurality of memory cells MC connected to each other in series, respectively. In a different manner, a single string select transistor, each of string select transistors SST1and SST2, or a plurality of ground select transistors GST may also be connected to the memory cells MC. One or more dummy lines DWL or buffer lines may be further disposed between an uppermost word line WLn, among the word lines WL0to WLn, and the string select lines SSL1and SSL2. In an example embodiment, one or more dummy lines DWL may also be disposed between a lowermost word line WL0and the ground select line GSL. In the present specification, the term “dummy” may have the same or similar structure and shape to that of other components, and may only be used to refer to a component present as a pattern without a practical function within a device (e.g., it may be connected to memory cells whose stored information is ignored by a host or controller). When a signal is applied to the string select transistors SST1and SST2through the string select lines SSL1and SSL2, a signal, applied through the bit lines BL0to BL2, may be transmitted to the memory cells MC, connected to each other in series, and a data reading operation and a data writing operation may be performed. Moreover, a predetermined erasing voltage is applied through a substrate, so an erasing operation for erasing data, written on the memory cells MC, may be performed. In an example embodiment, the memory cell array20may include at least one dummy memory cell string, electrically isolated from the bit lines BL0to BL2. FIG.3is a schematic plan view illustrating a semiconductor device according to example embodiments. InFIG.3, main components of a memory cell region CELL of the semiconductor device100are only illustrated for the sake of understanding.FIG.4is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments.FIG.4illustrates a cross section cut along line I-I′ ofFIG.3. Referring toFIGS.3and4, the semiconductor device100may include a first substrate structure S1and a second substrate structure S2, vertically stacked. The first substrate structure S1may include a memory cell region CELL, while the second substrate structure S2may include a peripheral circuit region PERI. In the first substrate structure S1, as illustrated inFIG.3, the memory cell region CELL may include a substrate201, such as a semiconductor substrate that may be referred to as a first or second substrate, having a cell array region CAR, which is a first region, and a cell connection region CTR, which is a second region, gate electrodes230stacked on the substrate201, interlayer insulating layers220alternately stacked with the gate electrodes230, gate separation regions SR extended while passing through a stacked structure of the gate electrodes230, upper separation regions SS passing through a portion of the gate electrodes230, channels CH disposed to pass through the gate electrodes230, and a cell region insulating layer290covering the gate electrodes230. The memory cell region CELL may further include channel regions240, gate dielectric layers245, channel insulating layers250, and channel pads255, in the channels CH. The memory cell region CELL may further include cell contact plugs260, through contact plugs261, first conductive plugs262, bit lines270and270a, second conductive plugs264, and first bonding pads280, which are wiring structures for applying a signal to the channels CH and the gate electrodes230. The cell array region CAR of the substrate201may be a region in which the gate electrodes230are vertically stacked and channels CH are disposed, and may be a region corresponding to the memory cell array20ofFIG.1, while the cell connection region CTR may be a region in which the gate electrodes230are extended lengthwise by different lengths, and may correspond to a region for electrically connecting the memory cell array20to the peripheral circuit ofFIG.1. An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width. The cell connection region CTR may be disposed in at least one end of the cell array region CAR in at least one direction, for example, and an X-direction. The substrate201may have the upper surface extending in the X-direction and a Y-direction. The upper surface may generally be referred to as a first surface. It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, for example as a naming convention. Thus, a first element, component, region, layer or section discussed in one section of the specification could be termed a second element, component, region, layer or section in another section of the specification or in the claims without departing from the teachings of the present invention. In addition, in certain cases, even if a term is not described using “first,” “second,” etc., in the specification, it may still be referred to as “first” or “second” in a claim in order to distinguish different claimed elements from each other. The substrate201may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. For example, the substrate201may be provided as a single crystal layer or an epitaxial layer. The substrate201may be referred to as a memory cell region semiconductor substrate. The gate electrodes230may be stacked and spaced apart from each other perpendicular to the substrate201, thereby forming a stacked structure together with the interlayer insulating layers220. The gate electrodes230may include a lower gate electrode231, forming a gate of the ground select transistor GST ofFIG.2, memory gate electrodes232to236, forming a plurality of memory cells MC, and upper gate electrodes237and238, forming a gate of the string select transistors SST1and SST2. The number of the memory gate electrodes232to236, forming the memory cells MC, may be determined depending on capacity of the semiconductor device100. According to an example embodiment, the upper and lower gate electrodes231,237, and238of the string select transistors SST1and SST1and the ground select transistor GST may be provided in an amount of one or two or more, and may have the same or different structure from that of the gate electrodes230of the memory cells MC. Some gate electrodes230, for example, memory gate electrodes232to236, adjacent to the upper or lower gate electrode231,237, and238, may be dummy gate electrodes. The gate electrodes230may be stacked and spaced apart from each other perpendicular to the cell array region CAR, and may extend lengthwise by different lengths from the cell array region CAR into the cell connection region CTR to form a stepped staircase structure. The gate electrodes230are stepped in the X-direction as illustrated inFIG.4, and may be disposed to be stepped in the Y-direction. Due to the stepped portion, a lower gate electrode230is extended longer than an upper gate electrode230, so the gate electrodes230may provide contact regions CP exposed upwardly. The gate electrodes230may be connected to the cell contact plugs260in the contact regions CP, respectively. The contact regions CP may be referred to and described as word line connection pads. As described below, in some embodiments, the word line connection pads, or contact regions CP, may include raised portions, and may be described as raised pad portions. As illustrated inFIG.3, the gate electrodes230may be disposed to be separated from each other in the Y-direction by gate separation regions SR extending in the X-direction. Gate electrodes230, between a pair of gate separation regions SR continuously extending in the X-direction among the gate separation regions SR, may form a single memory block, but a range of a memory block is not limited thereto. A portion of the gate electrodes230, for example, memory gate electrodes232to236may form a single layer in a single memory block. The interlayer insulating layers220may be disposed between the gate electrodes230. The interlayer insulating layers220may also be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of the substrate201and to extend lengthwise in the X-direction, in a manner similar to the gate electrodes230. The interlayer insulating layers220may contain an insulating material, such as silicon oxide or silicon nitride. The gate separation regions SR may be disposed to pass through the gate electrodes230in the cell array region CAR and the cell connection region CTR and to extend in the X-direction. The gate separation regions SR may be arranged parallel to each other. In the gate separation regions SR, a continuously extended pattern and an intermittently extended pattern may be alternately disposed in the Y-direction. However, the arrangement order, the number, and the like, of the gate separation regions SR, are not limited to those illustrated inFIG.3. The gate separation regions SR may pass through the entirety of the gate electrodes230, stacked on the substrate201, and may be connected to the substrate201. The common source line CSL, described with reference toFIG.2, may be disposed in the gate separation regions SR, and the dummy common source line may be disposed in at least a portion of the gate separation regions. However, the common source line CSL may be disposed in the substrate201, according to example embodiments. Upper separation regions SS may extend in the X-direction between the gate separation regions SR. The upper separation regions SS may be disposed in a portion of the cell connection region CTR and the cell array region CAR, to pass through a portion of gate electrodes230, including the upper gate electrodes237and238, among the gate electrodes230. The upper gate electrodes237and238, separated by the upper separation regions SS, may form different string select lines SSL1and SSL2(seeFIG.2). The upper separation regions SS may include an insulating layer. The upper separation regions SS, may separate, for example, a total of three gate electrodes230, including the upper gate electrodes237and238, from each other in the Y-direction. However, the number of the gate electrodes230, separated by the upper separation regions SS, may be variously changed in example embodiments. In example embodiments, the substrate structure S1may further include insulating layers separating lower gate electrodes231among the gate electrodes230. For example, the insulating layer may be disposed to separate lower gate electrodes231in a region between the gate separation regions SR, spaced apart from each other on a straight line and arranged intermittently. The channels CH may be spaced apart from each other in rows and columns on the cell array region CAR. The channels CH may be disposed to form a grid pattern or disposed in a zigzag form in a direction. The channel CH may have a columnar shape, and may have an inclined side surface narrowing towards the substrate201according to aspect ratios. In example embodiments, dummy channels may be further disposed in an end portion of the cell array region CAR, adjacent to the cell connection region CTR, and the cell connection region CTR. A channel region240may be disposed in the channels CH. In the channel CH, the channel region240may have an annular form surrounding the channel insulating layer250, formed therein. However, the channel region may have a columnar shape without the channel insulating layer250, such as a cylinder or a prism, according to an example embodiment. The channel region240may be connected to an epitaxial layer207in a lower portion of the channel region. The channel region240may contain a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be a material undoped with an impurity, or a material containing a p-type or n-type impurity. Channels CH, disposed on a straight line in the Y-direction between the gate separation regions SR and the upper separation region SS, may be connected to different bit lines270, according to arrangement of an upper wiring structure connected to the channel pad255. Channel pads255may be disposed in an upper portion of the channel region240in the channels CH. The channel pads255may be disposed to cover an upper surface of the channel insulating layer250and to be electrically connected to the channel region240. The channel pads255may include, for example, doped polycrystalline silicon. The gate dielectric layer245may be disposed between the gate electrodes230and the channel region240. Although not specifically illustrated, the gate dielectric layer245may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel region240. The tunneling layer may allow a charge to tunnel to the charge storage layer, and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material or combinations thereof. In example embodiments, at least a portion of the gate dielectric layer245may be extended in a horizontal direction along the gate electrodes230. The epitaxial layer207may be disposed on the substrate201in a lower end of the channels CH, and may be disposed in a side surface of at least one gate electrode230. The epitaxial layer207may be disposed in a recessed region of the substrate201. A level of an upper surface of the epitaxial layer207may be higher than a level of an upper surface of a lowermost gate electrode231and may be lower than a level of a lower surface of a gate electrode232located thereabove, but it is not limited to that illustrated in the drawings. In example embodiments, the epitaxial layer207may be omitted. In this case, the channel region240may be directly connected to the substrate201or may be connected to another conductive layer on the substrate201. The memory cell region CELL may further include cell contact plugs260, through contact plugs261, first conductive plugs262, bit lines270, and wiring lines270a, second conductive plugs264, and first bonding pads280, which are wiring structures for electrical connection with the second substrate structure S2. The wiring structures described above may include a conductive material. The wiring structures may include, for example, tungsten (W), aluminum (Al), copper (Cu), a tungsten nitride (WN), a tantalum nitride (TaN), a titanium nitride (TiN), or combinations thereof. The cell contact plugs260may pass through the cell region insulating layer290to be connected to the gate electrodes230in the contact regions CP. The cell contact plugs260may have a cylindrical shape. In example embodiments, the cell contact plugs260may have an inclined side surface narrowing towards the substrate201according to aspect ratios. Thus, the first cell contact plugs260may have a tapered shape that tapers toward the first substrate201. According to example embodiments, some of the cell contact plugs260, connected to certain gate electrodes230, may be dummy contact plugs. The through contact plugs261may extend vertically to pass through the cell region insulating layer290to be connected to the substrate201, and may be connected to the second substrate structure S2through the first bonding pad280at an upper end. The first conductive plugs262may be disposed on the channels CH, the cell contact plugs260, and the through contact plugs261. The bit lines270and wiring lines270amay be disposed between the first cell contact plugs262and the second cell contact plugs264at an upper end of the first conductive plugs262. The bit lines270and wiring lines270amay include bit lines270connected to the channels CH, and bit lines270aconnected to lower contact plugs262, and the bit lines270, connected to the channels CH, may correspond to the bit lines BL0to BL2ofFIG.2(noting thatFIG.2Ais just a representative portion of the overall semiconductor device100, and does not show the same number of first bit lines asFIG.4). The wiring lines270a, connected to the first conductive plugs262, do not function as bit lines, and may include wiring lines formed at the same vertical level, in the same process as that of the bit lines270connected to the channels CH. The wiring lines270a, connected to the first conductive plugs262, are illustrated as being disposed on all gate electrodes230, but are not limited thereto. The second conductive plugs264are disposed on the bit lines270and wiring lines270a, and may be connected to the first bonding pads280in an upper portion. The first bonding pads280are disposed on the second conductive plugs264, and an upper surface of the first bonding pads may be exposed to an upper surface of the first substrate structure S1through the first cell region insulating layer290. The first bonding pads280may serve as a bonding layer for bonding the first substrate structure S1and the second substrate structure S2. Bonding pads, or other pads, as described herein, are formed of conductive material and have a substantially flat, or planar, outer surface. The first bonding pads280may have a large planar area as compared with other wiring structures, in order to be bonded with the second substrate structure S2and to provide an electrical connection path thereby. The first bonding pads280may be disposed to vertically overlap with the bit lines270and the cell contact plugs261in a Z-direction on the bit lines270and the cell contact plugs261, electrically connected to each other, but are not limited thereto. The first bonding pads280may be arranged in a constant pattern in each of the cell array region CAR and the cell connection region CTR. The first bonding pads280may be disposed at the same level (e.g., vertical level) in the cell array region CAR and the cell connection region CTR, and may have the same or different sizes. Moreover, the first bonding pads280may be arranged in the same or different patterns in each of the cell array region CAR and the cell connection region CTR. The first bonding pads280may have, for example, a quadrangular, circular, or elliptical shape, on a plane, but are not limited thereto. The first bonding pads280may include a conductive material, for example, copper (Cu). The cell region insulating layer290may be formed of an insulating material. In example embodiments, the cell region insulating layer290may include a bonding dielectric layer to a predetermined thickness at an upper end in which the first bonding pad280is disposed. The bonding dielectric layer is disposed on a lower surface of the second substrate structure S2, so dielectric-dielectric bonding may be performed thereon. The bonding dielectric layer may function as a diffusion barrier layer of the first bonding pad280, and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In the second substrate structure S2, the peripheral circuit region PERI may include a base substrate101, circuit elements120disposed on the base substrate101, a passivation layer150, circuit contact plugs160, circuit wiring lines170, and second bonding pads180. The base substrate101, which may be a semiconductor substrate and may be described as a first or second substrate or a peripheral circuit substrate, may have the upper surface extending in the X-direction and a Y-direction. A first surface of the base substrate101may face the substrate201. The base substrate101may have separate element separation layers formed therein such that an active region may be defined. A portion of the active region may have source/drain regions105disposed therein and including an impurity. The base substrate101may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the base substrate101may be provided as a single crystal bulk wafer. The circuit elements120may include, for example, a horizontal transistor. Each of the circuit elements120may include a circuit gate dielectric layer122, a spacer layer124, and a circuit gate electrode125. The source/drain regions105may be disposed in the base substrate101on both sides of the circuit gate electrode125. The passivation layer150may be disposed on a surface in which the circuit elements120are not disposed in the base substrate101, for example, a second surface of the base substrate101opposite the first surface that faces the substrate201. The passivation layer150may serve to protect the semiconductor device100from external moisture, impurities, and the like. A pad region IO for electrical connection to an outside may be formed in the passivation layer150, and the pad region IO may pass through the base substrate101to expose a wiring structure. However, a structure of the pad region IO is not limited thereto, and may be variously changed in example embodiments. The passivation layer150may include an insulating material. The peripheral region insulating layer190may be disposed on the circuit element120on the base substrate101. The circuit contact plugs160may pass through the peripheral region insulating layer190to be connected to the source/drain regions105, and may include first to third circuit contact plugs162,164, and166, sequentially positioned from the base substrate101. The circuit contact plugs160may allow an electrical signal to be applied to the circuit element120. In a region not illustrated, the circuit contact plugs160may be connected even to the circuit gate electrode125. The circuit wiring lines170may be connected to the circuit contact plugs160, and may include first to third circuit wiring lines172,174, and176, forming a plurality of layers. The second bonding pads180are disposed to be connected to the third circuit contact plugs166, and one surface of the second bonding pads180, a lower surface inFIG.4, facing the first substrate structure S1, may be exposed to a lower surface of the second substrate structure S2through the peripheral region insulating layer190. In some embodiments, the lower surface of the second bonding pads180(e.g., a surface facing the first substrate structure S1) is exposed to an outside of the second substrate structure S2and is coplanar with a surface of the peripheral region insulating layer190. The second bonding pads180may serve as a bonding layer for bonding the first substrate structure S1and the second substrate structure S2, with the first bonding pads280. The second bonding pads180may have a large planar area as compared with other wiring structures, in order to be bonded with the first substrate structure S1and to provide an electrical connection path thereby. The second bonding pads180may be disposed in a position corresponding to that of the first bonding pads280(e.g., to vertically overlap), and may have a size the same as or similar to that of the first bonding pads280. The second bonding pads180may include a conductive material, for example, copper (Cu). The first substrate structure S1and the second substrate structure S2may be bonded by bonding of the first bonding pads280and the second bonding pads180, for example, copper (Cu)-to-copper (Cu) bonding. The first bonding pads280and the second bonding pads180may have an area relatively larger than that of other configurations of the wiring structure, so reliability of the electrical connection between the first substrate structure S1and the second substrate structure S2may be improved. In example embodiments, the first substrate structure S1and the second substrate structure S2, may be bonded by hybrid bonding due to bonding of the first bonding pads280and the second bonding pads180, and dielectric-to-dielectric bonding of the cell region insulating layer290and the peripheral region insulating layer190, disposed around the first bonding pads280and the second bonding pads180. FIGS.5A and5Bare layout diagrams illustrating a portion of a semiconductor device according to example embodiments.FIGS.5A and5Billustrate a layout of a main configuration in the cell array region CAR ofFIG.3. Referring toFIG.5A, in a cell array region CAR1, arrangement on the plane, of the bit lines270, the second conductive plugs264, and the first bonding pads280, sequentially stacked, is illustrated. In the cell array region CAR1, a portion in the Y-direction is only illustrated. The bit lines270have a line shape extending in the Y-direction. For example, two bit lines may be disposed over an upper portion of a single channel CH. The first bonding pads280may be disposed over an upper portion of the bit lines270, and at least one first bonding pad280may be connected to each bit line270. The first bonding pads280may be disposed to vertically overlap the bit line270connected thereto, and may be connected to the bit line270through the second conductive plug264. Thus, the first bonding pads280may be disposed on a region in which the bit lines270are arranged. The second conductive plug264is illustrated as a quadrangle, but is not limited thereto, and may have various shapes such as an elongated, elliptical, or circular shape. Moreover, in example embodiments, the second conductive plug264extends in the Y-direction along the first bit line270, and may be disposed longer than the first bonding pad280. The first bonding pads280may be arranged to form a diagonal pattern. For example, the first bonding pads280may form parallel rows formed on the bit lines270, for example extending in a diagonal direction with respect to the extension direction of the bit lines270. The first bonding pads280may be disposed to vertically overlap a plurality of respective bit lines270in the X-direction, by way of example. The first bonding pads280may be disposed on the bit lines270, shifted in the X-direction and adjacent to each other, in the Y-direction. The first bonding pads280may have a first length L1, which may be greater than a length of the channel CH. Hereinafter, unless otherwise stated, a “length” in connection with channels or bonding pads as viewed from the Z-direction indicates a maximum length or maximum width. The first bonding pads280have a first pitch D1in the X-direction, and have a second pitch D2in the Y-direction. Here, a “pitch” indicates a length between the centers of components adjacent to each other on a plane. When the components are spaced apart from each other, a “pitch” indicates a length, the sum of a maximum length of a component and a minimum distance between components. For example, when a region in which all bit lines270are disposed has a length in the Y-direction, greater than a length in the X-direction, the second pitch D2may be greater than the first pitch D1. However, the relative sizes of the first pitch D1and the second pitch D2are not limited thereto. In example embodiments, the first pitch D1and the second pitch D2may be determined in consideration of a size of the cell array region CAR1, the number and a size of the bit lines270, a size of the first bonding pads280, and the like. The first pitch D1and the second pitch D2may range from several hundred nanometers to several micrometers, for example, from about 500 nm to about 3 μm. Referring toFIG.5B, in a cell array region CAR2, first bonding pads280may be disposed in a zigzag or hexagonal form, in a manner different from an example embodiment ofFIG.5A. The first bonding pads280may have a second length L2, equal to or greater than the first length L1of an example embodiment ofFIG.5A, by way of example. The first bonding pads280have a third pitch D3in the X-direction, and have a fourth pitch D4in a diagonal-direction. The third pitch D3and the fourth pitch D4may be equal to each other, but are not limited thereto. In the case of the first bonding pads280, at least one first bonding pad280may be connected for each bit line270. However, in an example embodiment, at least some of the first bonding pads280may not be symmetrically disposed over a bit line270to which the first bonding pad280is connected to (e.g., to have a center point vertically overlapping the bit line270), and may be disposed in a region of which the center is shifted in the X-direction from the line270. In this case, the first bonding pads280may be disposed to vertically overlap a bit line270connected thereto, but are they are not limited thereto. In example embodiments, the first bonding pads280may be disposed in a region in which the channels CH (seeFIGS.3and4) are not disposed, or may be disposed in a region in which the bit lines270are not disposed. In this case, the first bonding pads280may be connected to the bit lines270by an additional wiring line. The extended arrangement of the first bonding pads280described above is not limited to a case in which the first bonding pads280are disposed in a zigzag form in an example embodiment, and may be applied to both of example embodiments in which the first bonding pads are disposed regularly in rows and columns, and example embodiments in which the first bonding pads are disposed irregularly. FIGS.6A to6Dare schematic partially enlarged views illustrating a semiconductor device according to example embodiments.FIG.6Aillustrates an enlarged region A ofFIG.4, andFIGS.6B to6Dillustrate an enlarged region corresponding to the region A ofFIG.4. Referring toFIG.6A, arrangement of a wiring structure on an upper portion of the channel CH is enlarged and illustrated. As described above with reference toFIG.4, the first conductive plug262, the first bit line270, the second conductive plug264, and the first bonding pad280are sequentially disposed on an upper portion of the channel CH. Referring toFIG.6B, a wiring structure may include a first conductive plug262, a third conductive plug263, a bit line270, a second conductive plug264, and a first bonding pad280, sequentially stacked on an upper portion of the channel CH. In this example embodiment, a third conductive plug263may be further disposed between the first conductive plug262and the bit line270. The third conductive plug263may have a diameter smaller than a diameter of the first conductive plug262in a lower portion, but is not limited thereto. Referring toFIG.6C, a wiring structure may include a fourth conductive plug265, a first cell wiring line275, a first conductive plug262, a bit line270, a second conductive plug264, and a first bonding pad280, sequentially stacked on an upper portion of the channel CH. In this example embodiment, a fourth conductive plug265and a first cell wiring line275may be further disposed between the channel CH and the first conductive plug262. The first cell wiring line275may be a line disposed between the first conductive plug262and the fourth conductive plug265. Thus, according to example embodiments, even when a channel CH in a lower portion and a first bonding pad180in an upper portion are not disposed to vertically overlap, the channel and the first bonding pad may be connected using the first cell wiring line275. Moreover, the first cell wiring line275may be used for rewiring between the channel CH and the bit line270. Referring toFIG.6D, a wiring structure may include a first conductive plug262, a bit line270, a second conductive plug264, a second cell wiring line277, a fifth conductive plug266, and a first bonding pad280, sequentially stacked on an upper portion of the channel CH. In other words, in an example embodiment, the second cell wiring line277and the fifth conductive plug266may be further disposed between the second conductive plug264and the first bonding pad280. In example embodiments, even when a channel CH in a lower portion and a first bonding pad280in an upper portion are not disposed in parallel in a vertical direction, the channel and the first bonding pad may be connected using the second cell wiring line277. As described above, a structure and form of the wiring structure, disposed on an upper portion of the channels CH, may be variously changed in example embodiments. FIG.7is a layout diagram illustrating a portion of a semiconductor device according to example embodiments.FIG.7illustrates a layout of a main configuration in the cell connection region CTR ofFIG.3. Referring toFIG.7, in a cell connection region CTR1, arrangement on the plane, of the gate electrodes230, the cell contact plugs260, and the first connection pads280is illustrated. The gate electrodes230, as described with reference toFIG.3, may have a form separated along the Y-direction in a certain region by the gate separation regions SR and the upper separation regions SS. InFIG.7, a case in which the number of stacked gate electrodes230is large, as compared with example embodiments ofFIGS.3and4. The gate electrodes230are extended to different lengths in the X-direction to be stepped, and may also be stepped in the Y-direction. The illustrated region corresponds to a single memory block, but is not limited thereto. The contact regions CP corresponds to respective regions stepped in relation to adjacent regions, and different contact regions CP at adjacent vertical levels may have the same or different sizes (e.g., same or different lengths and/or widths from a plan view). Also, different contact regions CP at the same vertical level may have the same or different sizes (e.g., same or different lengths and/or widths from a plan view). A minimum width of each contact region CP may be a first width W1in the X-direction or may be a second width W2in the Y-direction, and the first width W1and the second width W2may be equal or different. At least one of the cell contact plugs260may be disposed in each of the contact regions CP. At least one cell contact plug260may be connected to a single gate electrode230. Each of the first cell contact plugs260may be continuously formed pillars extending between a first contact plug262and a corresponding gate electrode230. At least some of the cell contact plugs260, exceeding one per the gate electrode230, may correspond to a dummy cell contact plug or arrangement thereof may be able to be omitted. The first connection pads280are illustrated to have a circular shape on a plane, but they are not limited thereto, and may have various shapes such as quadrangular, elliptical shapes, and the like according to example embodiments. Pads, as described herein, are formed of conductive material and have a substantially flat, or planar, outer surface. A maximum length L3of the first connection pads280may be less than the first width W1and the second width W2of each contact region CP, so that from a top-down view, each cell contact contact region CP surrounds at least one respective first connection pad280. Thus, a pitch of the first connection pads280may be equal to or less than a pitch of the contact regions CP. In this case, as illustrated in the drawings, each of the first connection pads280may be disposed on the cell contact plug260in each contact region CP. Thus, the first connection pads280may be disposed to vertically overlap the cell contact plug260on an upper portion of the cell contact plug260connected thereto. In example embodiments, when a pitch of the first connection pads280is less than a pitch of the contact regions CP, all the first connection pads280may also be arranged on a region of the cell connection region CTR1, in which the gate electrodes230are disposed. FIGS.8A to8Care layout diagrams illustrating a portion of a semiconductor device according to example embodiments.FIGS.8A to8Cillustrate a layout of a main configuration in the cell connection region CTR ofFIG.3. Referring toFIGS.8A to8C, in the cell connection region CTR, arrangement on the plane, of the gate electrodes230, the cell contact plugs260, and the first connection pads280is illustrated. In the cell connection regions CTR2, CTR3, and CTR4ofFIGS.8A to8C, in a manner different fromFIG.7, a layout is illustrated of a case in which at least one of a seventh pitch D7and an eighth pitch D8of the first connection pads280is greater than a fifth pitch D5or a sixth pitch D6, pitches of some of the contact regions CP in the X-direction and the Y-direction, respectively. Two memory blocks, adjacent to each other, are illustrated inFIGS.8A to8C. However, the form of gate electrodes230and the number of contact regions CP, determining a single memory block, may be changed variously in example embodiments. In two memory blocks adjacent to each other (e.g., in the Y-direction), cell contact plugs260are disposed in a first memory block in a first region (e.g., an upper portion ofFIG.8A), and cell contact plugs260are not disposed in a second memory block in a second region (e.g., lower portion ofFIG.8A). In this case, the second memory block in the second region may be connected to cell contact plugs260at another end in the X-direction. Thus, a first group of first connection pads280may be electrically connected to cell contact plugs260disposed in a first memory block in a first region at one end of the gate electrodes230in the X-direction, and a second group of first connection pads280may be electrically connected to cell contact plugs260disposed in a second memory block in a second region at an opposite end of the gate electrodes230in the X-direction. In the cell connection region CTR2ofFIG.8A, the first connection pads280may be arranged in rows and columns and in a constant pattern. In an example embodiment, a length L4of the first connection pads280may be greater than a length L3in an example embodiment ofFIG.7, but is not limited thereto. In the cell connection region CTR3ofFIG.8B, the first connection pads280may be arranged in a zigzag or hexagonal shape. In an example embodiment, a length L5of the first connection pads280may be greater than a length L4in an example embodiment ofFIG.8A, but is not limited thereto. In the case of example embodiments ofFIGS.8A and8B, when the number of cell contact plugs260to be connected is relatively large, the first connection pads280may be disposed to be extended outwardly of the cell connection regions CTR2and CTR3. For example, at least a portion of the first connection pads280may be arranged in an outer region of the cell connection regions CTR2and CTR3in the X-direction. In the cell connection region CTR4ofFIG.8C, the first connection pads280may be arranged in a zigzag or hexagonal form. However, in the cell connection region CTR4in an example embodiment, the form of the contact regions CP, provided by the gate electrodes230, may be different from that in an example embodiment ofFIG.8B. According to the stacking order, the gate electrodes230may form the first pad region P1, the second pad region P2, and the third pad region P3. The second pad region P2is only formed of gate electrodes230that form part of a memory cell, and the second pad region P2may be disposed repeatedly a plurality of times, between the first pad region P1and the third pad region P3according to the number of gate electrodes230. In the case of the first pad region P1and the third pad region P3, dummy gate electrodes may be included according to example embodiments, the number of cell contact plugs260to be connected is small, and/or density of cell contact plugs260may be low, relatively. On the other hand, in the case of the second pad region P2, cell contact plugs260are used to be connected to respective contact regions CP, and the second pad region P2may thus be a region in which density of the cell contact plugs260is relatively high. The second pad region P2may include first regions P2ain three columns and a second region P2bin one column, extended in the Y-direction. The first region P2amay be a region defined by a first area (e.g., rectangular area) in which a first group of contact regions CP is disposed along the Y-direction, and the second region P2bmay be a region defined by a second area (e.g., rectangular) in which a second group of contact regions CP is disposed along the Y-direction. Therefore, each of the first region P2aand the second region P2bmay denote contact regions CP formed in a column of a single memory block in the Y-direction. A width W3of the second region P2bin the X-direction may be greater than a width W1of a first region P2a. For example, a width W3of the second region P2bmay be about 2 to about 5 times greater than a width W1of a first region P2a. The width W3of the second region P2bin the X-direction may be greater than the length L5of the first connection pad280, and the width W1of a first region P2amay be less than the length L5of the first connection pad280. The second region P2bmay include an extension region ER, which has a width in the X-direction greater than a width W1of a first region P2a, and in which cell contact plugs260are not disposed. As described above, a second region P2bis periodically disposed between sets of first regions P2a, so an area in which the first connection pads280are disposed may be secured. In example embodiments, when a pitch of the first connection pads280is relatively large, at least a portion of the first regions P2amay not overlap the first connection pads280. For example, at least portions of the various contact regions CP within the first regions P2amay not vertically overlap any first connection pads280. However, even in this case, the second regions P2bmay be disposed to overlap the first connection pads280in at least portions of each second region P2b. In example embodiments, the relative number of the first regions P2aand the second regions P2b, that is, a period in which the second region P2bis disposed or a ratio of the number of first regions P2ato second regions P2bmay be varied, and may be determined in consideration of the number of cell contact plugs260, a size of the first connection pads280, a size of the contact regions CP, and the like. Moreover, in example embodiments, contact regions CP in one column including an extension region ER may be disposed, not only in the second pad region P2, but also in the first pad region P1and the third pad region P3. Contact regions CP described herein may also be described as gate electrode pads, wherein each contact region CP, whether it has a length and width of one unit (e.g., forming a square shape inFIGS.8A-8C) or whether it includes an extension region, forms a gate electrode pad, and thus may have a length, for example in the X-direction, of more than one unit (e.g., two, three, four, etc., units). In the second pad region P2, a portion of the first connection pads280may be disposed on the first regions P2a, and a portion thereof may be disposed on the second region P2bin both sides or one side of the first regions P2a. The number of first connection pads280disposed on an upper portion of a single contact region CP in a first region P2a, may be less than the number of the first connection pads280disposed on an upper portion of a single contact region CP in the second region P2b. Here, “the number of the first connection pads280” may refer to an average number of the first connection pads280, disposed per contact region CP. For example, a density per contact region CP of the first connection pads280may be greater in the second region P2b, as compared with that in a first region P2a. In this regard, as described above, because the second region P2bhas a relatively greater width. According to example embodiments, in a first region P2aand a second region P2b, the first connection pads280may be disposed at different densities per unit area, and a density on the second region P2bmay be relatively greater. As can be seen from above, contact regions CP can include a plurality of sets of a first group of contact regions (e.g., sets of the columns labeled P2a) and a plurality of sets of a second group of contact regions (e.g., sets of the column labeled P2b). Therefore, the contact regions CP can include multiple groupings of two different types of contact regions, each grouping of the same type having the same layout from a top down view. Groupings of the first type can be periodically disposed between groupings of the second type, from a top down view. To summarize certain features, as can be seen from the examples ofFIG.7andFIGS.8A-8C. InFIG.7, the size or pitch of a connection pad280may be smaller than the size or pitch of one unit of a word line connection pad. Therefore, each of the connection pads280can be disposed above a respective word line connection pad.FIGS.8A through8Cdepict cases in which the size or pitch of the connection pads280is larger than the size or pitch of a unit of the word line connection pad. InFIGS.8A through8C, the connection pads280can be disposed above the word line connection pads of an adjacent memory block. As one example, in this case, gate electrodes230of the adjacent block can be connected to contact plugs260at an opposite end of the gate electrodes230along the x-direction. More specifically, InFIGS.8A and8B, two types of disposition patterns of the connection pads280for a memory block are shown. In these embodiments, some of the connection pads280may be arranged in an outer region of the cell connection region CTR2/CTR3, because the number of the connection pads280may need to be the same as the number of the word line connection pads. Therefore, the connection pads280are disposed beyond the cell connection region CTR2/CTR3for example, outside of an area defined by the word line connection pads of the memory block. InFIG.8C, an elongated word line connection pad (P2bregion) is used to dispose the connection pads280within the cell connection region CTR4. As shown inFIG.8C, word line connection pads may have irregular patterns in an upper portion (P1) and a lower portion (P3) of a stack of the word line connection pads. However, word line connection pads may have regular pattern in the middle (P2) of the stack. Therefore, P1inFIG.8Cmay represent a first group of word line connection pads in a first word line connection pad region (or in a first section of connection region CTR), and P3may represent a third group of word line connection pads in a third word line connection pad region (or in a third section of connection region CTR). P2may represent a second group of word line connection pads in a second word line connection pad region (or in a second section of connection region CTR), and P2may include a repeated pattern of word line connection pads between P1and P3, according to the number of gate electrodes230included. For example, in the second word line connection pad region (P2), the elongated region (P2b) can be part of a word line connection pad provided after every three word line connection pads in the X-direction that have a unit size (e.g., in regions P2a). So a repeated pattern may include a number of word line connection pads (e.g.,3) that have a unit size, followed by a word line connection pad that has a size greater than a unit size (e.g., a unit size plus an extension region ER). As a result, an area for disposition of all of the connection pads280can be secured by inserting the region P2b, and the connection pads280can be disposed regularly above the word line connection pads for the memory block. In an example embodiment, the first connection pads280are not located directly over an upper portion of the cell contact plugs260connected thereto, and may be connected to the cell contact plugs260through a separate wiring line. This will be described below in more detail with reference toFIG.9. FIG.9is a layout diagram illustrating a portion of a semiconductor device according to example embodiments.FIG.9illustrates a layout of a main configuration in a portion of a cell connection region CTR4ofFIG.8C. Referring toFIG.9, a second pad region P2of the cell connection region CTR4ofFIG.8Cis enlarged and illustrated. Each of first connection pads280may be disposed to vertically overlap the first region P2aconnected thereto or the second region P2bconnected thereto, and may be disposed not to overlap a first region P2aconnected thereto or the second region P2bconnected thereto. The first connection pads280may be connected to the cell contact plugs260through wiring lines270a. In detail, the cell contact plugs260are connected to the first conductive plugs262, respectively, as illustrated inFIG.4, and may be connected to the second conductive plugs264, disposed to be spaced apart from each other in the X-direction and the Y-direction, by the wiring lines270a, as illustrated inFIG.9. Thus, the first conductive plugs262may be connected to the first connection pads280disposed on an upper portion of the second conductive plugs264. In example embodiments, a wiring structure between the first connection pads280and the cell contact plugs260may be variously changed. A vertical structure of the wiring structure will be described below in more detail with reference toFIGS.10A to10C. A horizontal structure, for example, wiring lines270amay be disposed in maximum three columns or three rows on a single first region P2a. In some embodiments a plurality of first regions P2amay be referred to as a set of first region P2a, and each column of the set of first regions P2amay be referred to as a first region. Thus, the wiring lines270amay be disposed on a plane in various forms within the range described above. The first connection pads280may be arranged to form different patterns by selecting the arrangement of the first connection pads280in the cell array regions CAR described above with reference toFIGS.5A and5B, and the arrangement of the first connection pads280in the cell connection regions CTR described above with reference toFIGS.8A to8C, one by one. However, according to example embodiments, the first connection pads280may be arranged to form one pattern as a whole while selecting the arrangements of the example embodiments in two regions one by one. FIGS.10A to10Care schematic partially enlarged views illustrating a semiconductor device according to example embodiments.FIG.10Aillustrates an enlarged region B ofFIG.4, andFIGS.10B and10Cillustrate an enlarged region corresponding to the region B ofFIG.4. Referring toFIG.10A, arrangement of wiring structures on an upper portion of the cell contact plug260is enlarged and illustrated. As described above with reference toFIG.4, the first conductive plug262, the wiring line270a, the second conductive plug264, and the first bonding pad280are sequentially disposed on an upper portion of the cell contact plug260. The wiring line270a, disposed in an upper portion of the cell contact plug260, is not a layer serving as bit lines BL0to BL2as illustrated inFIG.2in a semiconductor device, but may be a layer serving as a wiring line for vertical connection. Referring toFIG.10B, a wiring structure may include a first conductive plug262, a third conductive plug263, a wiring line270a, a second conductive plug264, and a first bonding pad280, sequentially stacked on an upper portion of the cell contact plug260. In this an example embodiment, a third conductive plug263may be further disposed between the first conductive plug262and the wiring line270a. Referring toFIG.10C, a wiring structure may include a first conductive plug262, a third conductive plug263, a second conductive plug264, and a first bonding pad280, sequentially stacked on an upper portion of the cell contact plug260. In this example embodiment, a third conductive plug263may be further disposed between the first conductive plug262and the second conductive plug264, and the wiring line270amay not be disposed. As described above, a structure and form of the wiring structure, disposed on an upper portion of the cell contact plug260, may be variously changed in example embodiments. Structures of a wiring structure on an upper portion of the channel CH described above with reference toFIGS.6A to6Dmay be applied to that on the cell contact plug260, and example embodiments described above with reference toFIGS.10A and10B, including the wiring line270a, may be applied to that in an upper portion of the channel CH. Moreover, in a single semiconductor device, structures of wiring structures disposed on an upper portion of the channel CH and an upper portion of the cell contact plug260are not necessarily the same, and different wiring structures may be provided thereon. FIG.11is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Referring toFIG.11, in a semiconductor device100a, the first bonding pads280and the second bonding pads180of the first substrate structure S1and the second substrate structure S2may have different sizes on an upper portion of the channel CH and on an upper portion of the cell contact plug260. As such, the first bonding pads280and the second bonding pads180may have different sizes in regions corresponding to the cell array region CAR and the cell connection region CTR ofFIG.3. The first bonding pads280and the second bonding pads180may have a sixth length L6on an upper portion of the channel CH, and may have a seventh length L7on an upper portion of the cell contact plug260, greater than the sixth length L6. This embodiment may provide an arrangement considering a difference in number per unit area of the first bonding pads280and the second bonding pads180, in the cell array region CAR and the cell connection region CTR. For example, when the number per unit area of the first bonding pads280and the second bonding pads180in the cell connection region CTR, is relatively small, the first bonding pads280and the second bonding pads180in the cell connection region CTR are formed relatively large, so areas of the first bonding pads280and the second bonding pads180per unit area, may be similarly controlled. According to example embodiments, bonding pads on an upper portion of the channel CH may be able to be formed relatively large. FIG.12is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Referring toFIG.12, the semiconductor device200may include a first substrate structure S1and a second substrate structure S2, vertically stacked. The first substrate structure S1may include all of a first memory cell region CELL1and a peripheral circuit region PERI, in a manner different from the example embodiment ofFIG.4. The second substrate structure S2may include an additional second memory cell region CELL2. Hereinafter, descriptions of the configuration of reference numerals the same as those ofFIG.4are applied equally, and thus a duplicate description thereof will be omitted. The first substrate structure S1may have a structure in which the first memory cell region CELL1is disposed on the peripheral circuit region PERI, and is thus electrically connected thereto. For the connection described above, the first substrate structure S1may further include a through wiring insulating layer295. The through wiring insulating layer295may be disposed to pass through the gate electrodes230and the interlayer insulating layers220from an upper portion of the gate electrodes230. A cell contact plug261may be disposed in the through wiring insulating layer295. A cell contact plug261, passing through the through wiring insulating layer295, may pass through the substrate201to be directly connected to circuit wiring lines170of the peripheral circuit region PERI. The cell contact plug261, passing through the through wiring insulating layer295, may be insulated from the substrate201by a side insulating layer292. The second memory cell region CELL2may have a structure the same as or similar to that of the first memory cell region CELL1. For example, the arrangement of a wiring structure including the cell contact plugs260in the second memory cell region CELL2may be different from that in the first memory cell region CELL1. The second memory cell region CELL2may include second bonding pads380. The second bonding pads380may be bonded to the first bonding pads280of the first substrate structure S1, thereby connecting the first substrate structure S1to the second substrate structure S2. The first bonding pads280and the second bonding pads380may have the structure and arrangement, such as described above with reference toFIGS.5A to10C. In the semiconductor device200, the bit lines270of the first memory cell region CELL1and the second memory cell region CELL2may be electrically connected to each other by a wiring structure including the first bonding pads280and the second bonding pads380. Moreover, at least a portion of the gate electrodes230of the first memory cell region CELL1and the second memory cell region CELL2may be electrically connected to each other by a wiring structure including the first bonding pads280and the second bonding pads380. FIG.13is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Referring toFIG.13, the semiconductor device300may include a first substrate structure S1, a third substrate structure S3, and a second substrate structure S2, sequentially and vertically stacked. The first substrate structure S1may include a first memory cell region CELL1, the third substrate structure S3may include a peripheral circuit region PERI, and the second substrate structure S2may include a second memory cell region CELL2. Hereinafter, descriptions overlapping those ofFIGS.4and12will be omitted. The peripheral circuit region PERI further includes circuit through contact plugs161passing through a base substrate101, as well as third bonding pads180A and fourth bonding pads180B exposed to an upper surface and a lower surface through a first peripheral region insulating layer190and a second peripheral region insulating layer195. The circuit through contact plugs161may connect the third bonding pads180A to the fourth bonding pads180B, disposed on both surfaces of the base substrate101, respectively. The circuit through contact plugs161may pass through the base substrate101and a portion of the first peripheral region insulating layers190. The circuit through contact plugs161may be insulated from the base substrate101by a substrate insulating layer140disposed on a portion of a side surface. The third bonding pads180A and the fourth bonding pads180B are disposed on both surfaces of the third substrate structure S3, respectively, and may be connected to each other through the circuit through contact plugs161, the second circuit wiring lines174, and the third circuit contact plugs166. The fourth bonding pads180B may be disposed to be in contact with an upper surface of the base substrate101. The third bonding pads180A may be bonded to the first bonding pads280of the first substrate structure S1, and the fourth bonding pads180B may be bonded to the second bonding pads380of the second substrate structure S2. Thus, the third bonding pads180A are electrically connected to the first bit lines270and the first cell contact plugs260, and the fourth bonding pads180B may be electrically connected to the second bit lines370and the second cell contact plugs360. Thus, the first substrate structure S1, the second substrate structure S2, and the third substrate structure S3may be electrically connected to each other through the third bonding pads180A and the fourth bonding pads180B. The first bonding pads280, the second bonding pads380, the third bonding pads180A, and the fourth bonding pads180B may have the structure and arrangement such as described above with reference toFIGS.5A to10C. FIGS.14A to14Hare schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to example embodiments.FIGS.14A to14Hillustrate a region corresponding toFIG.4. Referring toFIG.14A, for formation of the memory cell region CELL of the first substrate structure S1, sacrificial layers225and interlayer insulating layers220are alternately stacked on a substrate201, and a portion of the sacrificial layers225and the interlayer insulating layers220may be removed to allow the sacrificial layers225to be extended in different lengths, for example to have a stepped staircase structure. The substrate201may be a single crystal silicon wafer. The sacrificial layers225may be a layer to be replaced with gate electrodes230through a subsequent process. The sacrificial layers225may be formed of a material to be etched with etching selectivity with respect to the interlayer insulating layers220. For example, the interlayer insulating layer220may include at least one of silicon oxide and silicon nitride, and the sacrificial layers225may include a material selected from silicon, silicon oxide, silicon carbide, and silicon nitride, different from that of the interlayer insulating layer220. In example embodiments, all of thicknesses of the interlayer insulating layers220may be the same, but in other embodiments, the thicknesses of the different interlayer insulating layers220may not be the same. Then, in order to allow sacrificial layers225in an upper portion of the layer stack to be extended shorter than sacrificial layers225in a lower portion, a photolithography process and an etching process for the sacrificial layers225and the interlayer insulating layers220may be repeatedly performed. Thus, the sacrificial layers225may have a stepped form. In example embodiments, sacrificial layers225may be formed to have a relatively thick thickness at an end portion (not shown inFIG.14A), and a process therefor may be further performed. Then, a cell region insulating layer290covering an upper portion of a stacked structure of the sacrificial layers225and the interlayer insulating layers220may be provided. Referring toFIG.14B, channels CH passing through a stacked structure of the sacrificial layers225and the interlayer insulating layers220may be provided. For formation of the channels CH, first, the stacked structure may be anisotropically etched to form channel holes. Due to a height of the stacked structure, a side wall of the channel holes CH may not be perpendicular to an upper surface of the substrate201. In example embodiments, the channel holes may be formed to recess a portion of the substrate201. Then, the epitaxial layer207, the channel region240, the gate dielectric layer245, the channel insulating layer250, and the channel pads255are formed in the channel holes, thereby forming channels CH. The epitaxial layer207may be formed using a selective epitaxial growth (SEG) process. The epitaxial layers207may include a single layer or a plurality of layers. The epitaxial layers207may contain polycrystalline silicon (Si), monocrystalline Si, polycrystalline germanium (Ge) or monocrystalline Ge that are doped with or do not include an impurity. The gate dielectric layer245may be formed to have a uniform thickness using ALD or CVD. In the operation described above, at least a portion, vertically extended along the channel region240, of the gate dielectric layer245, may be provided. The channel region240may be formed on the gate dielectric layer245in the channels CH. The insulating layer250may be formed to fill the channels CH, and may be an insulating material. However, according to example embodiments, rather than the channel insulating layer250, a conductive material may fill a space of the channel region240. The channel pads255may be formed of a conductive material, for example, polycrystalline silicon. Referring toFIG.14C, openings, passing through a stacked structure of the sacrificial layers225and the interlayer insulating layers220, are provided, and the sacrificial layers225may be removed through the openings. The openings may be provided in the form of a trench, extending in the X-direction in a region, not illustrated, along the gate separation regions SR ofFIG.3. The sacrificial layers225may be removed selectively with respect to the interlayer insulating layers220, using, for example, wet etching. Thus, a portion of side walls of the channels CH may be exposed between the interlayer insulating layers220. Referring toFIG.14D, gate electrodes230are provided in a region from which the sacrificial layers225are removed. A conductive material is embedded in the region, from which the sacrificial layers225are removed, to provide the gate electrodes230. The gate electrodes230may contain metal, polycrystalline silicon or a metal silicide material. In example embodiments, before the gate electrodes230are provided, when a region, horizontally extended on the substrate201along the gate electrodes230, of the gate dielectric layer245, is provided, the region described above may be provided first. Then, in a region not illustrated, a source conductive layer, serving as a common source line CSL ofFIG.2, may be provided in the openings. However, the source conductive layer is not necessarily formed in the openings, and may be formed in the substrate201. Referring toFIG.14E, a wiring structure, which is the cell contact plugs260, through contact plugs261, first conductive plugs262, bit lines270wiring lines270a, second conductive plugs264, and first bonding pads280, are provided on the gate electrodes230. The cell contact plugs260and the through contact plug261may be formed by etching the cell region insulating layer290to form a contact hole, and embedding a conductive material, on each of the contact regions CP and the substrate201. The first conductive plugs262may be formed by etching the cell region insulating layer290and depositing a conductive material on the channel pads255, the cell contact plugs260, and the through contact plug261. The bit lines270and wiring lines270amay be formed through deposition and patterning processes of a conductive material, or by forming a single layer, an insulating layer forming the cell region insulating layer290, and then patterning it and depositing a conductive material. The second conductive plugs264may be formed by etching the cell region insulating layer290and depositing a conductive material on the bit lines270and wiring lines270a. The first bonding pads280may be formed through, for example, a deposition and patterning processes of a conductive material on the second conductive plugs264. An upper surface of the first bonding pads280may be exposed through the cell region insulating layer290, and the first bonding pads may form a portion of an upper surface of the first substrate structure S1. According to example embodiments, the upper surface of the first bonding pads280may be provided in the form further protruding upwardly, as compared with an upper surface of the cell region insulating layer290. Due to the operation described above, a memory cell region CELL is completed, and the first substrate structure S1may be ultimately prepared. Referring toFIG.14F, for formation of the second substrate structure S2, circuit elements120and circuit wiring structures are formed on the base substrate101, thereby forming a peripheral circuit region PERI. First, a circuit gate dielectric layer122and a circuit gate electrode125may be sequentially formed on the base substrate101. The circuit gate dielectric layer122and the circuit gate electrode125may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer122may be formed of silicon oxide, and the circuit gate electrode layer125may be formed of at least one of polycrystalline silicon or metal silicide, but an example embodiment is not limited thereto. Then, the spacer layer124and the source/drain regions105may be formed on both side walls of the circuit gate dielectric layer122and the circuit gate electrode125. According to example embodiments, the spacer layer124may be formed of a plurality of layers. Then, the source/drain regions105may be formed by performing an ion implantation process. The circuit contact plugs160of the circuit wiring structures may be provided by forming a portion of the peripheral region insulating layer190, etching and removing a portion and embedding a conductive material. The circuit wiring lines170may be provided by depositing and patterning a conductive material, by way of example. The peripheral region insulating layer190may be formed of a plurality of insulating layers. The peripheral region insulating layer190may be ultimately provided to cover the circuit elements120and the circuit wiring structures, by forming a portion in respective operations for formation of the circuit wiring structures and forming a portion in an upper portion of the third circuit wiring line176. Referring toFIG.14G, the second substrate structure S2is bonded to the first substrate structure S1. For example, the first substrate structure S1and the second substrate structure S2may be connected to each other by bonding the first bonding pads280and the second bonding pads180by applying pressure. The second substrate structure S2may be bonded to the first substrate structure S1by inverting the second substrate structure to allow the second bonding pads180to face downwardly. The first substrate structure S1and the second substrate structure S2may be directly bonded without intervention of an adhesive such as a separate adhesive layer. For example, bonding of the first bonding pads280and the second bonding pads180at an atomic level may be provided by applying a pressure as described above. In this manner, the first bonding pads280and the second bonding pads180contact each other. According to example embodiments, before bonding, in order to enhance bonding force, a surface treatment process such as a hydrogen plasma treatment may be further performed on an upper surface of the first substrate structure S1and a lower surface of the second substrate structure S2. In example embodiments, when the cell region insulating layer290includes the bonding dielectric layer described above in an upper portion and the second substrate structure S2also has the same layer, a bonding force may be further secured due to not only bonding between the first bonding pads280and the second bonding pads180, but also dielectric bonding between the bonding dielectric layers. Referring toFIG.14H, a passivation layer150may be formed on the base substrate101of the second substrate structure S2. The passivation layer150may be formed through a deposition process on the base substrate101exposed upwardly by the bonding process. Then, as illustrated inFIG.5, the passivation layer150and the base substrate101are removed from some regions, thereby exposing a wiring structure in a lower portion to provide a pad region IO. Thus, the semiconductor device100ofFIG.5may be ultimately manufactured. Each set of plugs or wiring lines described herein and shown in the figures to be at the same vertical level may be formed in a single process for forming the structures at that vertical level. FIG.15is a block diagram illustrating an electronic device including a semiconductor device according to example embodiments. Referring toFIG.15, an electronic device1000according to an example embodiment may include a communications unit1010, an input unit1020, an output unit1030, a memory1040, and a processor1050. The communications unit1010may include a wired/wireless communications module such as a wireless Internet module, a local communications module, a global positioning system (GPS) module, or a mobile communications module. The wired/wireless communications module included in the communications unit1010may be connected to an external communications network based on various communications standards to transmit and receive data. The input unit1020may include a mechanical switch, a touchscreen, a voice recognition module, and the like, as a module provided for a user to control operations of the electronic device1000, and may further include various sensor modules to which a user may input data. The output unit1030may output information processed by the electronic device1000in an audio or video format, and the memory1040may store a program for processing or control of the processor1050, or data. The memory1040may include one or more semiconductor devices according to various example embodiments as described above with reference toFIGS.2to13, and may be embedded in the electronic device1000or may communicate with the processor1050through a separate interface. The processor1050may control operations of each component included in the electronic device1000. The processor1050may perform control and processing associated with a voice call, a video call, data communications, and the like, or may conduct control and processing for multimedia reproduction and management. Moreover, the processor1050may process the input from a user via the input unit1020and output the result thereof through the output unit1030, and may store data, required for controlling an operation of the electronic device1000, in the memory1040or retrieve the data from the memory1040. As set forth above, according to example embodiments of the present inventive concept, arrangement of bonding pads is optimized in a structure in which two or more substrate structures are bonded, so a semiconductor device having improved reliability may be provided. While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure, as defined by the appended claims. | 79,280 |
11942464 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. According to some embodiments, a first package component is bonded to a second package component by a multi-shot reflow process. The first and second package components may be, e.g., wafers, and each contain a plurality of package regions. In the multi-shot reflow process, the package regions of the package components are sequentially heated by a laser beam. Each laser shot completely overlaps at least one package region, and may partially overlap other adjacent package regions. The multi-shot reflow process allows the first and second package components to be bonded together by directly heating only the top package component. Indirect heating of the bottom package component may be reduced, which may help reduce wafer warpage. Further, the parameters of the different laser shots may be varied to help further reduce wafer warpage. FIGS.1through10illustrate cross-sectional views of intermediate steps during a process for forming a first package component100, in accordance with some embodiments. A first package region100A and a second package region100B are illustrated, and a first package101(seeFIG.19) is formed in each of the package regions100A and100B. The first packages101may also be referred to as integrated fan-out (InFO) packages. InFIG.1, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. The carrier substrate102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate102may be a wafer, such that multiple packages can be formed on the carrier substrate102simultaneously. The release layer104may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer104is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer104may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer104may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate102, or may be the like. The top surface of the release layer104may be leveled and may have a high degree of planarity. InFIG.2, a back-side redistribution structure106is formed on the release layer104. In the embodiment shown, the back-side redistribution structure106includes a dielectric layer108, a metallization pattern110(sometimes referred to as redistribution layers or redistribution lines), and a dielectric layer112. The back-side redistribution structure106is optional, and in some embodiments only the dielectric layer108is formed. The dielectric layer108is formed on the release layer104. The bottom surface of the dielectric layer108may be in contact with the top surface of the release layer104. In some embodiments, the dielectric layer108is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer108is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer108may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. The metallization pattern110is formed on the dielectric layer108. As an example to form metallization pattern110, a seed layer is formed over the dielectric layer108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern110. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern110. The dielectric layer112is formed on the metallization pattern110and the dielectric layer108. In some embodiments, the dielectric layer112is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer112is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer112may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer112is then patterned to form openings114exposing portions of the metallization pattern110. The patterning may be by an acceptable process, such as by exposing the dielectric layer112to light when the dielectric layer112is a photo-sensitive material or by etching using, for example, an anisotropic etch. It should be appreciated that the back-side redistribution structure106may include any number of dielectric layers and metallization patterns. Additional dielectric layers and metallization patterns may be formed by repeating the processes for forming the metallization pattern110and dielectric layer112. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically couple the various conductive lines. InFIG.3, through vias116are formed in the openings114and extending away from the topmost dielectric layer of the back-side redistribution structure106(e.g., the dielectric layer112in the illustrated embodiment). As an example to form the through vias116, a seed layer is formed over the back-side redistribution structure106, e.g., on the dielectric layer112and portions of the metallization pattern110exposed by the openings114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to conductive vias. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the through vias116. InFIG.4, integrated circuit dies126are adhered to the dielectric layer112by an adhesive128. The integrated circuit dies126may be logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof. Also, in some embodiments, the integrated circuit dies126may be different sizes (e.g., different heights and/or surface areas), and in other embodiments, the integrated circuit dies126may be the same size (e.g., same heights and/or surface areas). Before being adhered to the dielectric layer112, the integrated circuit dies126may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit dies126. For example, the integrated circuit dies126each include a semiconductor substrate130, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate130and may be interconnected by interconnect structures132formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate130to form an integrated circuit. The integrated circuit dies126further comprise pads134, such as aluminum pads, to which external connections are made. The pads134are on what may be referred to as respective active sides of the integrated circuit dies126. Passivation films136are on the integrated circuit dies126and on portions of the pads134. Openings extend through the passivation films136to the pads134. Die connectors138, such as conductive pillars (for example, comprising a metal such as copper), extend through the openings in the passivation films136and are mechanically and electrically coupled to the respective pads134. The die connectors138may be formed by, for example, plating, or the like. The die connectors138electrically couple the respective integrated circuits of the integrated circuit dies126. A dielectric material140is on the active sides of the integrated circuit dies126, such as on the passivation films136and the die connectors138. The dielectric material140laterally encapsulates the die connectors138, and the dielectric material140is laterally coterminous with the respective integrated circuit dies126. The dielectric material140may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like. The adhesive128is on back-sides of the integrated circuit dies126and adheres the integrated circuit dies126to the back-side redistribution structure106, such as the dielectric layer112. The adhesive128may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive128may be applied to a back-side of the integrated circuit dies126or may be applied over the surface of the carrier substrate102. For example, the adhesive128may be applied to the back-side of the integrated circuit dies126before singulating to separate the integrated circuit dies126. Although one integrated circuit die126is illustrated as being adhered in each of the first package region100A and the second package region100B, it should be appreciated that more integrated circuit dies126may be adhered in each package region. For example, multiple integrated circuit dies126may be adhered in each region. Further, the integrated circuit dies126may vary in size. In some embodiments, the integrated circuit die126may be dies with a large footprint, such as system-on-chip (SoC) devices. In embodiments where the integrated circuit die126have a large footprint, the space available for the through vias116in the package regions may be limited. Use of the back-side redistribution structure106allows for an improved interconnect arrangement when the package regions have limited space available for the through vias116. InFIG.5, an encapsulant142is formed on the various components. After formation, the encapsulant142laterally encapsulates the through vias116and integrated circuit dies126. The encapsulant142may be a molding compound, epoxy, or the like. The encapsulant142may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate102such that the through vias116and/or the integrated circuit dies126are buried or covered. The encapsulant142is then cured. InFIG.6, a planarization process is performed on the encapsulant142to expose the through vias116and the die connectors138. The planarization process may also grind the dielectric material140. Top surfaces of the through vias116, die connectors138, dielectric material140, and encapsulant142are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. In some embodiments, the planarization may be omitted, for example, if the through vias116and die connectors138are already exposed. InFIG.7, a front-side redistribution structure144is formed over the through vias116, encapsulant142, and integrated circuit dies126. The front-side redistribution structure144includes dielectric layers146,150,154, and158; metallization patterns148,152, and156; and under bump metallurgies (UBMs)160. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure144is shown as an example. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure144. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated. As an example to form the front-side redistribution structure144, the dielectric layer146is deposited on the encapsulant142, through vias116, and die connectors138. In some embodiments, the dielectric layer146is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer146may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer146is then patterned. The patterning forms openings exposing portions of the through vias116and the die connectors138. The patterning may be by an acceptable process, such as by exposing the dielectric layer146to light when the dielectric layer146is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer146is a photo-sensitive material, the dielectric layer146can be developed after the exposure. The metallization pattern148is then formed. The metallization pattern148includes conductive lines on and extending along the major surface of the dielectric layer146. The metallization pattern148further includes conductive vias extending through the dielectric layer146to be physically and electrically connected to the through vias116and the integrated circuit dies126. To form the metallization pattern148, a seed layer is formed over the dielectric layer146and in the openings extending through the dielectric layer146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern148. The patterning forms openings through the photo resist to expose the seed layer. A conductive material is then formed in the openings of the photo resist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern148. The photo resist and portions of the seed layer on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The dielectric layer150is deposited on the metallization pattern148and dielectric layer146. The dielectric layer150may be formed in a manner similar to the dielectric layer146, and may be formed of the same material as the dielectric layer146. The metallization pattern152is then formed. The metallization pattern152includes conductive lines on and extending along the major surface of the dielectric layer150. The metallization pattern152further includes conductive vias extending through the dielectric layer150to be physically and electrically connected to the metallization pattern148. The metallization pattern152may be formed in a manner similar to the metallization pattern148, and may be formed of the same material as the metallization pattern148. The dielectric layer154is deposited on the metallization pattern152and dielectric layer150. The dielectric layer154may be formed in a manner similar to the dielectric layer146, and may be formed of the same material as the dielectric layer146. The metallization pattern156is then formed. The metallization pattern156includes conductive lines on and extending along the major surface of the dielectric layer154. The metallization pattern156further includes conductive vias extending through the dielectric layer154to be physically and electrically connected to the metallization pattern152. The metallization pattern156may be formed in a manner similar to the metallization pattern148, and may be formed of the same material as the metallization pattern148. The dielectric layer158is deposited on the metallization pattern156and dielectric layer154. The dielectric layer158may be formed in a manner similar to the dielectric layer146, and may be formed of the same material as the dielectric layer146. The UBMs160are optionally formed on and extending through the dielectric layer158. As an example to form the UBMs160, the dielectric layer158may be patterned to form openings exposing portions of the metallization pattern156. The patterning may be by an acceptable process, such as by exposing the dielectric layer158to light when the dielectric layer158is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer158is a photo-sensitive material, the dielectric layer158can be developed after the exposure. The openings for the UBMs160may be wider than the openings for the conductive via portions of the metallization patterns148,152, and156. A seed layer is formed over the dielectric layer158and in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBMs160. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the UBMs160. In embodiments where the UBMs160are formed differently, more photoresist and patterning steps may be utilized. InFIG.8, conductive connectors162are formed on the UBMs160. The conductive connectors162may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors162may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors162are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors162comprise metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. InFIG.9, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the back-side redistribution structure106, e.g., the dielectric layer108. In accordance with some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer104so that the release layer104decomposes under the heat of the light and the carrier substrate102can be removed. The structure is then flipped over and placed on a tape. InFIG.10, conductive connectors164are formed extending through the dielectric layer108to contact the metallization pattern110. Openings are formed through the dielectric layer108to expose portions of the metallization pattern110. The openings may be formed, for example, using laser drilling, etching, or the like. The conductive connectors164are formed in the openings. In some embodiments, the conductive connectors164comprise flux and are formed in a flux dipping process. In some embodiments, the conductive connectors164comprise a conductive paste such as solder paste, silver paste, or the like, and are dispensed in a printing process. In some embodiments, the conductive connectors164are formed in a manner similar to the conductive connectors162, and may be formed of the same material as the conductive connectors162. FIGS.11through18illustrate cross-sectional views of intermediate steps during a process for bonding the first package component100to a second package component200, in accordance with some embodiments. A first package region200A and a second package region200B are illustrated, and a second package201(seeFIG.19) is formed in each of the package regions200A and200B. InFIG.11, the second package component200is provided or produced. In the embodiment shown, the same types of packages are formed in the package components100and200. In some embodiments, different types of packages are formed in the package components100and200. In the embodiment shown, the package components100and200are both InFO packages. The second package component200has conductive connectors166, which are similar to the conductive connectors162of the first package component100. InFIG.12, the second package component200is aligned with the first package component100. Respective package regions of each of the package components100and200are aligned. For example, the first package regions100A and200A are aligned, and the second package regions100B and200B are aligned. The package components100and200are pressed together such that the conductive connectors166of the second package component200contact the conductive connectors164of the first package component100. FIGS.13through18illustrate a reflow process, which includes a plurality of laser shots and hence a plurality of reflow processes. The reflow process shown inFIGS.13through18is thus referred to as a multi-shot reflow process. The plurality of laser shots are performed using a laser beam52, which is generated by a laser beam generator54. In each of the laser shots, the laser beam52is projected on one region of the top surface of the second package component200, so that heat is absorbed by the second package component200and conducted through the second package component200to the conductive connectors164and166, causing the reflow of the conductive connectors164and166to form conductive connectors168. The laser beam generator54is configured to generate the laser beam52, and the laser beam52is emitted out of an emitter of the laser beam generator54. The laser beam52is larger than a typical laser beam. For example, the laser beam52may have a size in the range of from about 0.03×0.03 mm2to about 100×100 mm2. For example, the laser beam generator54is configured to enlarge a small laser beam to a desirable larger size. Furthermore, as illustrated inFIGS.15,16,17A,17B, and17C, the laser beam52may cover a rectangular region. The power of different portions of the laser beam52is substantially uniform, for example, with a variation smaller than about 10 percent throughout the rectangular region. In each of the laser shots, the conductive connectors164and166covered by the laser beam52are reflowed substantially simultaneously. InFIG.13, a first laser shot52A is performed at a first region40A of the second package component200. The first region40A includes components of the package components100and200which are directly in the projecting path of the first laser shot52A. In accordance with some embodiments, the first region40A completely overlaps the first package region200A (seeFIG.12), and is larger than the first package region200A. For example, the first region40A also partially overlaps the second package region200B. When the laser beam52is projected on the first region40A of the second package component200, the first region40A is heated, and the heat is transferred to the conductive connectors164and166directly under the first region40A. The first laser shot52A is performed until the conductive connectors164and166in the first region40A are molten and reflowed to form conductive connectors168. The conductive connectors164and166outside of the first region40A (e.g., not in the projecting path of laser beam52) are heated less than the conductive connectors164and166inside of the first region40A, and are not reflowed. The duration and the unit power (e.g., the power per unit area) of the first laser shot52A is controlled such that a majority of the conductive connectors164and166outside of the first region40A are not molten and hence are not reflowed. Accordingly, the duration of the first laser shot52A is long enough to melt the conductive connectors164and166inside of the first region40A, and short enough so that at least the majority of (or all of) of the conductive connectors164and166outside of the first region40A are not molten. A small number of conductive connectors164and166that are outside of and close to the first region40A may also be molten, for example, due to process variations or increased process margins. The unit power of the laser beam52is also selected to be high enough to melt the conductive connectors164and166inside of the first region40A, and low enough so that the conductive connectors164and166outside of the first region40A are not molten. In some embodiments, the duration of the laser shot is in the range of from about 2 seconds to about 30 seconds. The unit power may be in the range of from about 0.1 watts/mm2to about 0.7 watts/mm2. It should be appreciated that the length of time and unit power needed to melt the conductive connectors164and166is affected by a plurality of factors, which factors may include the unit power, the shot duration, the thickness of the second package component200, the materials and the thermal conductivity of the second package component200, and the like. In some embodiments, the conductive connectors164and166have a melting temperature higher than about 200° C., and may be in the range of from about 215° C. to about 230° C. The unit power of the laser shot may be adjusted to obtain a particular heating rate and peak temperature. In an embodiment, the peak temperature is in a range of from about 240° C. to about 250° C., and the heating rate is in a range of from about 0.5° C./second to about 50° C./second. After the conductive connectors164and166inside the first region40A are molten, and before the conductive connectors164and166outside the first region40A are molten, the first laser shot is ended. After the first laser shot52A, the laser beam52is turned off, and is stopped from being projected on the second package component200. Between the ending time of the first laser shot52A and the starting time of a second laser shot52B (seeFIG.14), a delay time may be implemented. During the delay, no laser shots are performed. The delay is long enough so that the reflowed conductive connectors168cool down and solidify. For example, the temperature of the conductive connectors168may drop into the range of from about 100° C. to about 150° C. after the delay time. The delay time may be in the range of from about 5 seconds to about 30 seconds. In some embodiments, cooling of the conductive connectors168is performed, such as air cooling. In such embodiments, the delay time may be adjusted to obtain a particular cooling rate. In some embodiments, the delay time is a predetermined period of time. In an embodiment, the cooling rate is greater than about 1° C./second. InFIG.14, a second laser shot52B is performed at a second region40B of the second package component200. The second region40B includes components of the package components100and200which are directly in the projecting path of the second laser shot52B. As a result, the conductive connectors164and166in the second region40B are reflowed. Most or all of the conductive connectors164and166outside of the second region40B do not receive adequate heat, and are not molten and not reflowed. A small number of conductive connectors164and166that are outside of and close to the second region40B may also be molten, for example, due to process variations or increased process margins. In some embodiments, the regions40A and40B overlap in an overlap region40AB. Some of the resulting conductive connectors168are disposed in the overlap region40AB. The conductive connectors168in the overlap region40AB are reflowed twice: once during the first laser shot52A, and once during the second laser shot52B. Other conductive connectors168outside of the overlap region40AB are reflowed once. Overlapping the regions40A and40B ensures that an entirety of the package regions200A and200B (seeFIG.12) are covered by the multiple laser shots, even when there are process variations such as misalignment in one of the laser shots. As such, all of the conductive connectors164and166will be reflowed. FIG.15illustrates a top view of the multi-shot reflow process. As shown, the laser shots52A and52B, each covering a rectangular region. The rectangular regions covered by the laser shots52A and52B may have the same size and shape. The combined region of the laser shots52A and52B fully covers the package regions200A and200B. The combined region may extend beyond the edges of the package regions200A and200B to provide enough process margin, so that all of the package regions200A and200B are covered by laser shots. As noted above, the overlap region40AB receives two laser shots. The conductive connectors168in the overlap region40AB are reflowed twice. In some embodiments, the overlap region40AB has a width W1in the range of from about 1 mm to about 5 mm. Inside this width W1, there may be a plurality of columns of the conductive connectors168, for example, more than ten columns, depending on the pitch of the conductive connectors168and the overlap width W1. The multi-shot reflow process results in the local heating of the second package component200in each of the shots, rather than globally heating the entirety of both package components100and200at the same time. When a laser shot is performed after a preceding shot has ended, the increased temperature caused by the preceding laser shots has already been reduced. Heating the package components100and200causes wafer warpage, and the magnitude of the warpage is related to the heating temperature. By performing more localized heating, the overall heating temperature may be reduced, and warpage of the package components100and200may be reduced. In addition, the laser shots52A and52B are projected on the second package component200, and the first package component100receives a very small dose (if any) of the laser beam directly. Accordingly, the first package component100is not heated significantly, and the corresponding warpage is reduced. In the example illustrated inFIGS.13and14, the regions40A and40B have an elongated top-view shape. In some embodiments, the regions40A and40B have other shapes. For example,FIG.16Aillustrates the package component200with multiple regions40having less-elongated shapes such as squares. The regions40may have any size or shape. In some embodiments, the regions40are 20 mm by 20 mm squares.FIG.16Bis a zoomed view of a region ofFIG.16A. The area shown inFIG.16Bmay be heated by a multi-shot reflow process that includes six laser shots52A through52F. Each of the laser shots52A through52F may overlap. As a result, center points42receive four laser shots. The overlap regions of the laser shots52A through52F may in combination form cross shapes. The order of the laser shots52A through52F may be adjusted to any order as desirable. FIGS.17A,17B, and17Cshow various laser shot patterns, in accordance with some embodiments. InFIG.17A, the regions40of the second package component200are heated in a back-and-forth sweep across the second package component200. Each row of the second package component200is sequentially heated, with each row being heated by sequentially heating each region40along the row. For example, regions40may be heated along an arrow44inFIG.17A. InFIG.17B, the regions40are divided into several groups. Each group is sequentially heated, with each group being heated by sequentially heating each region40in the group. For example, in the embodiment shown, the regions40are divided into two groups: a first group (including regions 1 through 9) and a second group (including regions A through K). Each of the regions in the first group are sequentially heated. After the regions in the first group are heated, each of the regions in the second group are sequentially heated. In some embodiments, the first and second groups are heated under the same heating conditions, e.g., the same duration, unit power, etc. of the laser beam52. In some embodiments, the first and second groups are heated under different heating conditions, e.g., different durations, unit powers, etc. of the laser beam52. InFIG.17C, only a subset of the regions40are heated. For example, a custom shape or pattern of regions40may be predetermined. Only selected regions46in the predetermined shape are heated, and remaining regions48are not heated. The unheated regions48may be regions where no devices are packaged, or may be regions that are indirectly heated due to process variations of the laser beam52. FIG.18illustrates a cross-sectional view of the conductive connectors168after formation. The conductive connectors168include conductive connectors168A and168B. The conductive connector168A is a connector that was reflowed twice (e.g., was in the overlap region40AB), and the conductive connector168B is a connector that was reflowed once (e.g., was in the one of the regions40or40B). During the multi-shot reflow process, inter-metallic compound (IMC) regions170A and170B are formed. The IMC regions170A and170B are compounds of the materials of the conductive connectors168and, respectively, the surface layers of the UBMs160and metallization pattern110. Depending on the structure and the materials of the various conductive materials, the IMC regions170A and170B may be compounds of solder with nickel, copper, titanium, palladium, gold, aluminum, or the like. The corresponding IMC regions170A and170B are separated from each other by, and in contact with, the portions of the corresponding conductive connectors168that are not compounded with the metallization pattern110and UBMs160. Due to the two (or more) reflow processes performed on the conductive connectors168A, the thicknesses T1of the IMC regions170A of the conductive connectors168A are greater than the thicknesses T2of the IMC regions170A of the conductive connectors168B. The ratio of T1:T2is greater than 1.0, and may be in the range of from about 1.2 to about 2.0. In accordance with some embodiments of the present disclosure, thickness T1is in the range of from about 7.2 μm to about 8 μm, and thickness T2is in the range of from about 4 μm to about 6 μm. Similarly, the thicknesses T3of the IMC regions170B of the conductive connectors168A are greater than the thicknesses T4of the IMC regions170B of the conductive connectors168B. The ratio of T3:T4is greater than 1.0 and may be in the range of from about 1.2 to about 2.0. In accordance with some embodiments of the present disclosure, thickness T3is in the range of from about 7.2 μm to about 8 μm, and thickness T4is in the range of from about 4 μm to about 6 μm. Although particular thicknesses are discussed, it should be appreciated that IMCs (such as the IMC regions170A and170B) may have varying or non-uniform thicknesses. As such, the IMC thicknesses discussed here may be average thicknesses. Although the conductive connectors168are shown as connecting the metallization pattern110and UBMs160, it should be appreciated that the conductive connectors168may be used to connect to any conductive features of the package components100and200. For example, the conductive connectors168may also physically connect to the through vias116, such as in embodiments where the back-side redistribution structure106is omitted. Likewise, the conductive connectors168may physically connect to the metallization pattern156, such as in embodiments where the UBMs160are omitted. Because the multi-shot reflow process reduces or avoids wafer warpage, the overall distance D1between the package components100and200may be more consistent across the different package regions. For example, the distance D1at edges of the package components100and200may be less than the distance D1at centers of the package components100and200. Further, the distance D1may vary by less than 5% across the diameter of the package components100and200. The conductive connectors168A with thicker IMC regions170A and170B may be allocated in strips that extend along the edge of the device packages in each respective package region (e.g., package regions200A and200B). In the resulting packages, there may be a single overlap strip or a plurality of overlap strips parallel to each other, which strips receive more than one (such as two or four) laser shots. After the multi-shot reflow process is completed, the package components100and200may be cleaned in a cleaning process. The cleaning process may be, e.g., a flux clean, which help remove residual material. The flux clean may be performed by flushing, rinsing, or soaking using hot water or a cleaning solvent. Further, an underfill or encapsulant may optionally be injected between the package components100and200, to surround the conductive connectors168. FIG.19illustrates a cross-sectional view of intermediate steps during a process for forming a package structure300, in accordance with some embodiments. The package structure300may be referred to a package-on-package (PoP) structure. A singulation process is performed by sawing along scribe line regions, e.g., between the package regions of the package components100and200. The sawing singulates the adjacent package regions100A,100B,200A, and200B from the package components100and200. The resulting singulated first packages101are from one of the first package region100A or the second package region100B, and the resulting singulated second packages201are from one of the first package region200A or the second package region200B. The packages101and201are then mounted to a package substrate302using the conductive connectors162. The package substrate302may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the package substrate302may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate302is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for package substrate302. The package substrate302may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the package structure300. The devices may be formed using any suitable methods. The package substrate302may also include metallization layers and vias (not shown) and bond pads304over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate302is substantially free of active and passive devices. In some embodiments, the conductive connectors162are reflowed to attach the first package101to the bond pads304. The conductive connectors162electrically and/or physically couple the package substrate302, including metallization layers in the package substrate302, to the first package101. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may be attached to the first package101(e.g., bonded to the bond pads304) prior to mounting on the package substrate302. In such embodiments, the passive devices may be bonded to a same surface of the first package101as the conductive connectors162. The conductive connectors162may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the first package101is attached to the package substrate302. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors162. In some embodiments, an underfill (not shown) may be formed between the first package101and the package substrate302and surrounding the conductive connectors162. The underfill may be formed by a capillary flow process after the first package101is attached or may be formed by a suitable deposition method before the first package101is attached. Embodiments may achieve advantages. By performing multi-shot reflow processes, the warpage of the package components100and200may be reduced, and defects such as cold joints and solder bridging may be eliminated. More flexibility may be afforded during manufacturing by selectively heating areas of the package components100and200. Manufacturing throughput may also be increased through the faster heating afforded by laser heating. In an embodiment, a method includes: aligning a first package component with a second package component, the first package component having a first region and a second region, the first region including a first conductive connector, the second region including a second conductive connector; performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region; and after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region. In some embodiments of the method, the first portion and the second portion of the top surface of the first package component partially overlap. In some embodiments of the method, the first conductive connector is heated by the second laser shot but is not reflowed by the second laser shot. In some embodiments of the method, performing the first laser shot includes: directing a laser beam at the first portion of the top surface of the first package component until the first conductive connector reflows; and after the first conductive connector reflows, turning off the laser beam until the first conductive connector solidifies. In some embodiments of the method, performing the second laser shot includes: after the first conductive connector solidifies, directing the laser beam at the second portion of the top surface of the first package component until the second conductive connector reflows. In some embodiments of the method, turning off the laser beam until the first conductive connector solidifies includes turning off the laser beam for a predetermined period of time, where the first conductive connector solidifies during the predetermined period of time. In some embodiments of the method, the first and second conductive connectors are disposed adjacent a bottom surface of the first package component, and where heat is transferred through the first package component to the first and second conductive connectors during the first and second laser shots. In some embodiments of the method, reflowing the first and second conductive connectors bonds the first package component to the second package component. In some embodiments, the method further includes: after the first package component is bonded to the second package component, singulating the first region from the second region to form a first device package. In some embodiments of the method, the first portion and the second portion of the top surface of the first package component overlap in a third region, the third region including a third conductive connector, the third conductive connector being reflowed by both the first laser shot and the second laser shot. In an embodiment, a method includes: providing a first package component and a second package component, the first package component including first regions, the second package component including second regions; aligning the first regions of the first package component with the second regions of the second package component; performing laser shots on a top surface of the first package component, each of the laser shots being performed sequentially, each respective laser shot of the laser shots overlapping a respective first region of the first regions and a respective second region of the second regions, a conductive material between the respective first region and the respective second region being reflowed by the respective laser shot; and after performing the laser shots, singulating the first regions of the first package component and the second regions of the second package component. In some embodiments of the method, performing the laser shots includes, for each respective laser shot: directing a laser beam at the respective first region of the first package component until the conductive material reflows, heat generated by the laser beam being transferred through the first package component to the conductive material; and after the conductive material reflows, turning off the laser beam until the conductive material cools. In some embodiments of the method, the laser shots are performed with the same unit power. In some embodiments of the method, the laser shots are performed for the same period of time. In some embodiments of the method, a first subset of the laser shots are performed with a first unit power and a second subset of the laser shots are performed with a second unit power, the second unit power being different from the first unit power. In some embodiments of the method, a first subset of the laser shots are performed for a first period of time and a second subset of the laser shots are performed for a second period of time, the second period of time being different from the first period of time. In some embodiments of the method, the laser shots are performed sequentially on all regions of the first package component. In some embodiments of the method, the laser shots are performed on a subset of regions of the first package component. In an embodiment, a package includes: a first package including a first conductive feature and a second conductive feature; a second package including a third conductive feature and a fourth conductive feature; a first conductive connector joining the third conductive feature to the first conductive feature; a first inter-metallic compound (IMC) between the first conductive connector and the first conductive feature, the first IMC having a first thickness; a second conductive connector joining the fourth conductive feature to the second conductive feature; and a second IMC between the second conductive connector and the second conductive feature, the second IMC having a second thickness less than the first thickness. In some embodiments of the package, the first package includes: a redistribution structure including the first conductive feature and the second conductive feature, the first and second conductive features being redistribution lines; an integrated circuit die on the redistribution structure; an encapsulant surrounding the integrated circuit die; and a conductive via extending through the encapsulant, the conductive via electrically connected to the integrated circuit die and the redistribution structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 56,033 |
11942465 | DETAILED DESCRIPTION In order to make the object, technical scheme and advantages of the present application clearer, the present application is further described in detail below in reference to drawings and embodiments. It should be understood that the specific embodiments described here are merely intended to explain the present application rather than limit the present application, so they have no technically substantive significance. Any structural modification, proportional relationship change or size adjustment shall still fall within the scope of the technical content disclosed in the present application without affecting the efficacy and object achieved by the present application. This section will describe the specific embodiments of the present application in detail, and the preferred embodiments of the present application are shown in the drawings. The purpose of the drawings is to supplement the description in the text of the specification with graphics, so that people can visually understand each technical feature and the overall technical scheme of the present application, but they cannot be understood as a limitation to the protection scope of the present application. In the description of the present application, “a plurality of” means one or more, while “multiple” means two or more. “greater than”, “less than”, “exceed” and the like should be understood as excluding this number, while “more than”, “less than”, “within” and the like should be understood as including this number. If described, “first” and “second” are merely intended to distinguish technical features rather than understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the precedence relationship of the indicated technical features. In order to facilitate understanding of an embedded structure provided by an embodiment of the present application, the specific structure will be described below with reference to the drawings. First, referring toFIG.2andFIG.3,FIG.2shows a schematic cross-sectional view of the whole structure of an embedded structure, andFIG.3shows a schematic cross-sectional view of the whole structure of another embodiment of the embedded structure. It can be seen fromFIG.2andFIG.3that an embedded structure mainly includes a dielectric layer100, which includes a first dielectric layer130and a second dielectric layer140. The dielectric layer100also includes a first surface110and a second surface120which are oppositely arranged. The dielectric material for producing the dielectric layer is generally one or a mixture of more of organic or inorganic dielectric materials, such as polyimide, epoxy resin, bismaleimide, triazine resin, ceramic filler and glass fiber, which are divided into a photosensitive type and a non-photosensitive type according to functional requirements at present. It can be understood that the photosensitive material can be selected as the dielectric material here. As shown inFIG.2, the embedded structure further includes devices200and terminals210embedded in the dielectric layer. The front of the device200is provided with the terminals210. The difference between the surface of the terminal210and the first surface110is within a set range, which is between 5 μm and 30 μm here, and different differences, such as 5 μm, 10 μm, 15 μm, 18 μm, 20 μm, 25 μm, 28 μm or 30 μm, may be selected. The surface of the terminal210is in the same direction as the first surface110, a non-terminal surface220is coplanar with the second surface120, and therefore this arrangement can further reduce the thickness of the packaged structure. It can be understood that the device200may be a die, an IC, a BGA or other active devices, among which the chip may be chips with different functions, such as a CPU chip, a radio-frequency driver chip or other processor chips, or the device200may be a passive device. When adopted, the passive device may be a capacitor, an inductor or a resistor. The dielectric layer100is arranged surrounding and wrapping the devices200, and the first surface110of the dielectric layer100is provided with a first circuit layer300, which is directly electrically connected to the terminals of the devices200. It can be understood that such a connection mode solves the problem that the existing scheme requires accurate application of solder, and because the devices and the circuit are integrally electroplated for connection, so the stability of connection between the devices and the circuit is ensured, ensuring good electrical signals. Opposite from the first circuit layer300, a second circuit layer310is arranged on the second surface120of the dielectric layer100, and is coplanar with the second surface120. As shown inFIG.2, the first circuit layer300and the second circuit layer310are connected through metal pillars400. The schematic diagram of the overall structure of an embedded structure shown inFIG.3is another embodiment of the present application, which is roughly the same as the main structure ofFIG.2, and the difference mainly lies in the sequence of implementation of the process flow, which will be discussed in detail in the subsequent preparation flow, and therefore will not be repeated here. It should be understood that although a specific structural schematic diagram of two devices200embedded in the dielectric layer100is shown inFIG.2orFIG.3, in the embodiments of the present application, the number of the devices200embedded in the dielectric layer100is not limited to two, but may be one, three or more. However, no matter how many devices200are embedded in the dielectric layer100, the devices200are connected to the other structural layers in the same way. It can also be understood that in the embodiments of the present application, the embedded structure is not limited to one layer, but may have two or more layers according to design requirements. However, no matter how many layers are designed, the overall structure designed is the same, having a first circuit layer300, a dielectric layer100surrounding and wrapping a plurality of devices200and metal pillars400and a second circuit layer310in sequence from the top down. It should be noted that the manufacturing method of the present application is illustrated by taking a layer of embedded structure wrapping two devices as an example. In order to facilitate understanding of the embedded structure provided by the embodiments of the present application, as shown inFIG.2, the first embodiment of the present application provides a method for preparing an embedded structure, and as shown inFIG.1a,the method includes the following steps. Preparing a temporary carrier board500; preparing a second circuit layer310on at least one of the upper surface and the lower surface of the temporary carrier board500, and preparing a first dielectric layer130to cover the second circuit layer310. As shown inFIG.4a,FIG.4bandFIG.4c, inFIG.4a, photoresist600is laminated on the surface of a protective layer540for the carrier board, exposed and developed to obtain a windowed pattern for the second circuit layer310; inFIG.4b, the second circuit layer310is electroplated, the photoresist is removed, and a dielectric material is laminated to form the first dielectric layer130, which is then pre-cured; and inFIG.4c, the first dielectric layer130is patterned to expose the upper surface of the second circuit layer310, and the dielectric material is completely hot-cured. In actual implementation, in order to ensure the effect of filling, the usage of the dielectric material is generally calculated according to an actually required filling amount. Here, the surface of the laminated dielectric material should be 5 μm to 20 μm higher than the surface of the second circuit layer310, and different differences, such as 5 μm, 10 μm, 15 μm, 18 μm or 20 μm, may be selected. One or a mixture of more of organic or inorganic dielectric materials, such as polyimide, epoxy resin, bismaleimide, triazine resin, ceramic filler and glass fiber, which are divided into photosensitive type dielectric materials and non-photosensitive type dielectric materials according to functional requirements at present, may be selected as the dielectric material. It should be noted that the present embodiment selects a photosensitive dielectric material to produce the dielectric layer100, because when the photosensitive material is used, the surface of the exposed circuit or copper pillars does not need to be processed by a thinning process (such as laser or drilling) after the to-be-exposed part of the circuit or the copper pillars are exposed by patterning, that is, only patterning is adopted, and therefore the efficiency of production is increased. After lamination and leveling, overall thinning is not needed, so that the dielectric layer100can become more even and the underlying devices will not be injured in actual implementation as well, thus increasing the yield. When used to be laminated, the photosensitive dielectric material only needs to be subjected to hot-curing by a heating platform or photocuring for a short time. If a non-photosensitive material is adopted as the dielectric material, a thinning process, such as grinding or plasma etching, may be adopted to thin the whole dielectric material on the upper surface of the circuit until the upper surface of the circuit is exposed, or the dielectric material on the upper surface of the circuit may be sintered by adopting laser sintering to obtain the needed upper surface of the circuit. As shown inFIG.4a, the carrier board is of a symmetrical structure with a middle organic layer510, a first metal layer520, a second metal layer530and a protective layer540in sequence from the middle to both sides. It can be understood that the organic layer510may be selected from organic materials such as PP, the first metal layer520may be selected from metal materials such as copper, the second metal layer530may be selected from metal materials such as copper, the first metal layer520and the second metal layer530are formed by physical lamination, and the protective layer540is formed by electroplating, the material of which may be, but is not limited to, cu, ti, ni, CuWTi, CuNiCu or CuTiCu. The thickness of each layer of the carrier board can be adjusted, and in this embodiment, it is calculated from the organic layer510. It should be noted that each layer may be selected from an 18 μm copper layer, a 3 μm copper layer and a 3-10 μm protective layer, and the metal of the protective layer may be nickel, titanium or the like. In actual preparation, since the carrier board is of the symmetrical structure, an embedded structure may be produced on each of the symmetrical surfaces of the carrier board. After the embedded structures are produced, the carrier board is divided into two substrates. Each substrate is a grid-like matrix array, including a plurality of units, with each unit having a device or a combination of more devices. Patterning and curing are performed on the first dielectric layer130to form a cavity230, devices200are mounted in the cavity230, and hot-curing is performed, wherein the surfaces of the devices200provided with terminals210face the openings of the cavity230. As shown inFIG.4candFIG.4d, the first dielectric layer130is patterned to obtain the cavity230for mounting the devices. The size of the cavity may be designed according to the size of the device, and an adhesive material240is applied to the bottom of the cavity. There exist many alternatives for the adhesive material240, which can be used to stick the devices and the underlying metal layers and is applied by dispensing or printing. The adhesive material240may be an organic or inorganic material, which is generally solder paste, silver paste, red glue or solder mask. In order to mount the device200, the device200is provided with the terminals210and a corresponding non-terminal surface220. During mounting, the non-terminal surface220of the device200is fixedly stuck to the adhesive material240, and the adhesive material240is hot-cured. A high-precision conventional SMT flow may be adopted for mounting coupled with heated reflow soldering. It can be understood that the adhesive material240may not be arranged, and by applying DAF (ultra-thin film adhesive) on the non-terminal surface220of the device, the DAF is directly stuck to the underlying metal layers by a heating platform during mounting. A second dielectric layer140is prepared, wherein the devices200are embedded in the second dielectric layer140, and the surface of the second dielectric layer140is higher than the surfaces of the terminals of the devices by a preset value. As shown inFIG.4e, the dielectric material is laminated and patterned to expose cavity windows250and a conductive a metal pillar pattern410, and the dielectric material is hot-cured. Here, in order to ensure the effect of filling, the usage of the dielectric material is calculated according to a filling amount to be higher than the upper surface of the device by a certain thickness. It can be understood that the thickness by which the second dielectric layer is higher than the surfaces of the terminals210is 5 μm to 30 μm, and different differences, such as 5 μm, 10 μm, 15 μm, 18 μm, 20 μm, 25 μm or 30 μm, may be selected. A first circuit layer300directly connected to the terminals210is prepared on the surface of the second dielectric layer140, and metal pillars400are produced through the second dielectric layer140, wherein the first circuit layer300is connected to the second circuit layer310through the metal pillars400. Referring toFIG.4fandFIG.4g, as shown inFIG.4f, a seed layer is produced on the surface of the second dielectric layer140, specifically the surfaces of the terminals210, the inner surface of the conductive metal pillar pattern410and the surface110of the second dielectric layer140. As shown inFIG.4g, photoresist600is laminated on the seed layer and patterned to expose a to-be-electroplated pattern for the first circuit layer300and a to-be-electroplated pattern for the conductive metal pillars400, and the pattern for the first circuit layer300and the pattern for the conductive metal pillars400are electroplated to obtain the first circuit layer300and the metal pillars400. It can be seen from the aforementioned steps that the first circuit layer300and the surfaces of the terminals210of the devices200are directly electrically connected through the seed layer by electroplating. It can be understood that such a connection mode solves the problem that the existing scheme requires accurate application of solder, and because the devices and the circuit are integrally electroplated for connection, so the stability of connection between the devices and the circuit is ensured, ensuring good electrical signals. The seed layer is produced by forming a metal seed layer320on the surface of the second dielectric layer140by electroless copper plating or sputtering. The commonly used metals for the seed layer are, but are not limited to, iron, copper, iron and alloy. The thickness of the seed layer is generally 0.8 μm to 5 μm. It can be understood that in the present embodiment, a metal sputtering method may be selected to sputter titanium with a thickness of 0.1 μm or copper with a thickness of 1 μm. The temporary carrier board500is divided to form a first-stage embedded structure. Solder masks700are formed on the both sides of the first-stage embedded structure, openings are formed in the solder masks700to expose the surfaces of the second circuit layer310and the first circuit layer300, and the surfaces of the second circuit layer310and the first circuit layer300are metallized. Specifically, referring toFIG.4h,FIG.4iandFIG.4j, as shown inFIG.4h, the photoresist600is removed, the seed layer320exposed on the surface of the second dielectric layer140is etched, the photoresist600is laminated to protect the circuit, and the whole board is divided after exposure. As shown inFIG.4i, during division, division is performed from the first metal layer520and the second metal layer530, and after a dividing surface550, the second metal layer530and the protective layer540are respectively etched, the photoresist600is removed. When the protective layer540is separately etched, because the protective layer of the carrier board is thin, which is 3 μm to 10 μm thick in the present embodiment, the metal of the protective layer may be nickel, titanium or the like, which is different from the metal used for the second metal layer530, so that different etchants may be used and the etching amount is small. Therefore, the influence on the circuit layer after etching the protective layer is relatively negligible. After division is complete, as shown inFIG.4j, solder masks are produced on the upper surface and the lower surface of the substrate. The production of the solder masks includes: substrate surface treatment, solder mask layer printing, hot pre-curing, exposure, development and hot curing. The upper surface and the lower surface of the substrate are then subjected to metal surface treatment to form metal surface layers330, and thereby a substrate with an embedded structure as shown inFIG.2is obtained. It should be noted that the flow of the steps of the manufacturing method for an embedded structure provided by the first embodiment of the present application is merely an exemplary specific flow for a layer of embedded structure, and more than one layer of embedded structure can be obtained by repeating the aforementioned steps according to need. According to a manufacturing method of another embodiment of the present application, a substrate with an embedded structure as shown inFIG.3can be produced. The manufacturing method (seeFIG.1b) is substantially the same as the preparation flow of the first embodiment of the present application, except that there are some differences in details, as shown in the following steps. Preparing a temporary carrier board500, preparing a second circuit layer310on at least one of the upper surface and the lower surface of the temporary carrier board500, and preparing a first dielectric layer130to cover the second circuit layer310. As shown inFIG.5a,FIG.5bandFIG.5c, inFIG.5a, photoresist600is laminated on the surface of a protective layer540for the carrier board, exposed and developed to obtain a windowed pattern for the second circuit layer310; inFIG.4i, the second circuit layer310is electroplated, the photoresist is removed, and a dielectric material is laminated to form the first dielectric layer130, which is then pre-cured; and inFIG.5c, the first dielectric layer130is patterned to expose the upper surface of the second circuit layer310, and the dielectric material is completely hot-cured. In actual implementation, in order to ensure the effect of filling, the usage of the dielectric material is generally calculated according to an actually required filling amount. Here, the surface of the laminated dielectric material should be 5 μm to 20 μm higher than the surface of the second circuit layer310, and different differences, such as 5 μm, 10 μm, 15 μm, 18 μm or 20 μm, may be selected. Patterning and curing the first dielectric layer130to expose the surface of the second circuit layer310, laminating and patterning photoresist600to obtain a metal pillar pattern410, and forming metal pillars400by electroplating; and removing the photoresist600to form a cavity230, mounting devices200in the cavity230, and performing hot-curing, wherein the surfaces of the devices200provided with the terminals210face the openings of the cavity230. Referring toFIG.5c,FIG.5d,FIG.5eandFIG.5f, as shown inFIG.5c, the first dielectric layer130is patterned to obtain the cavity230for mounting the devices, and after being laminated, the photoresist600is patterned to obtain the conductive metal pillar pattern410; as shown inFIG.5dandFIG.5e, the conductive metal pillars400are electroplated, and the photoresist600is removed; as shown inFIG.5f, an adhesive material240is applied on the bottom of the cavity230for the devices, the devices200are mounted, wherein the device200is provided with terminals210and a corresponding non-terminal surface220without terminals210, and during mounting, the non-terminal220of the device200is fixedly stuck to the adhesive material240, which is then hot-cured. It can be understood that the adhesive material240may not be arranged, and by applying a DAF (ultra-thin film adhesive) on the non-terminal surface220of the device, the DAF is directly stuck to the underlying metal layers by a heating platform during mounting. A second dielectric layer140is prepared, wherein the devices200are embedded in the second dielectric layer140, and the surface of the second dielectric layer140is higher than the surfaces of the terminals210by a preset value. Referring toFIG.5g, the dielectric material is laminated and patterned to expose cavity windows250and the upper surfaces of the metal pillars400, and the dielectric material is hot-cured. Here, in order to ensure the effect of filling, the usage of the dielectric material is calculated according to a filling amount to be higher than the upper surface of the device by a certain thickness. It can be understood that the thickness by which the second dielectric layer is higher than the surfaces of the terminals210is 5 μm to 30 μm, and different differences, such as 5 μm, 10 μm, 15 μm, 18 μm, 20 μm, 25 μm or 30 μm, may be selected. A first circuit layer300directly connected to the terminals210is prepared on the surface of the second dielectric layer140, wherein the first circuit layer300is connected to the second circuit layer310through the metal pillars400. Referring toFIG.5handFIG.5i, as shown inFIG.5h, a seed layer is produced on the surface of the second dielectric layer140, specifically the surfaces of the terminals210, the upper surfaces of the metal pillars400and the surface110of the second dielectric layer140. As shown inFIG.5i, photoresist600is laminated on the seed layer and patterned to expose a to-be-electroplated pattern for the first circuit layer300, and electroplating is performed to obtain the first circuit layer300. It can be seen from the aforementioned steps that the first circuit layer300and the surfaces of the terminals210of the devices200are directly electrically connected through the seed layer by electroplating. It can be understood that such a connection mode solves the problem that the existing scheme requires accurate application of solder, and because the devices and the circuit are integrally electroplated for connection, so the stability of connection between the devices and the circuit is ensured, ensuring good electrical signals. The preparation flow of the seed layer is the same as that of the seed layer in the first embodiment of the present application, and therefore will not be repeated here. Dividing the temporary carrier board to form a first-stage embedded structure; and Forming solder masks700on both sides of the first-stage embedded structure, making openings in the solder masks700to expose the surfaces of the second circuit layer310and the first circuit layer300, and metallizing the surfaces of the second circuit layer310and the first circuit layer300. Referring toFIG.5j,FIG.5kandFIG.45l,as shown inFIG.5j, the photoresist600is removed, the seed layer320exposed on the surface of the second dielectric layer140is etched, the photoresist600is laminated to protect the circuit, and the whole board is divided after exposure. As shown inFIG.5k, during division, division is performed from the first metal layer520and the second metal layer530, and after a dividing surface550, the second metal layer530and the protective layer540are respectively etched, the photoresist600is removed. When the protective layer540is separately etched, because the protective layer of the carrier board is thin, which is 3 μm to 10 μm thick in the present embodiment, the metal of the protective layer may be nickel, iron or the like, which is different from the metal used for the second metal layer530, so that different etchants may be used and the etching amount is small. Therefore, the influence on the circuit layer after etching the protective layer is relatively negligible. After division is complete, as shown inFIG.5l,solder masks are produced on the upper surface and the lower surface of the substrate, metal surface treatment is then performed to form metal surface layers330, and thereby a substrate with an embedded structure as shown inFIG.2is obtained. It should be noted that, according to need, a multilayer embedded structure substrate with a plurality of layers can be prepared by repeating some of the aforementioned intermediate steps. It can be concluded from the aforementioned flow that according to the embedded structure provided by the present application, the substrate with the device embedded structure can be produced by carrying out the preparation flow once, thus solving the problem that device embedding needs to be carried out in two steps in the existing technology. Therefore, compared with the existing technology, the present application reduces process steps, decreases the difficulty of manufacturing, improves the quality of products and reduces the manufacturing cost. Since the present application adopts the device embedding feature, it is convenient to monitor and inspect the quality of connection between the devices and the circuit through appearance monitoring in the process of manufacturing. By arranging the terminals upward, the device is connected to the carrying metal of the carrier board by applying the adhesive material or the DAF (ultra-thin film adhesive) on the whole back of the device, effectively solving the potential problem of defective filling between the circuit and the device as a result of the terminals facing downward. By arranging the terminals upward to connect the device200to the underlying carrier board through the adhesive material, the device200and the second circuit layer310are on the same reference plane, thus further reducing the overall thickness of the package. The preferred embodiments of the present application have been described in detail above with reference to the drawings. However, the present application is not limited to the aforementioned embodiments. Those skilled in the art can also make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements shall be included in the scope defined by the claims of the present application. | 26,812 |
11942466 | DETAILED DESCRIPTION A memory device and a method of manufacturing the memory device according to each of first and second embodiments will be described with reference toFIGS.1through28. The embodiments will be described in detail with reference to the drawings. In the following descriptions, the elements having the same function and configuration are denoted by the same reference numeral or sign. If the elements denoted by reference signs having numerals or letters at their ends (e.g. circuit, interconnects, and various voltages and signals) need not be distinguished from one another, the numerals or letters will be excluded. In general, according to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip. (1) First Embodiment A memory device of the first embodiment and a method for manufacturing the memory device will be described with reference toFIGS.1through16. (1a) Exemplary Configuration An exemplary configuration of the memory device of the first embodiment will be described with reference toFIGS.1through6. <Circuit Configuration> FIG.1is a block diagram showing an exemplary configuration example of the memory device of the first embodiment. The memory device of the first embodiment is, for example, a magnetic memory (for example, a domain wall memory). FIG.1shows a domain wall memory (also called a domain wall shift memory)1including a memory cell array (also called a memory area)100, a row control circuit110, a column control circuit120, a write circuit140, a read circuit150, a shift circuit160, an I/O circuit170, a voltage generation circuit180, a control circuit190, and the like. The memory cell array100includes a plurality of magnetic bodies (magnetic members)51and a plurality of interconnects. Each of the magnetic bodies51is connected to its corresponding one or more interconnects (e.g., word lines and bit lines). Data is stored in a memory cell MC in each of the magnetic bodies51. The row control circuit110controls a plurality of rows of the memory cell array100. The row control circuit110is supplied with an address decoding result (a row address). The row control circuit110sets a row (e.g., a word line) based on the address decoding result in a selected state. Hereinafter, the row (or word line) set in a selected state will be referred to as a selected row (or selected word line). Rows other than the selected row will be referred to as unselected rows (or unselected word lines). The row control circuit110includes, for example, a multiplexer (a word line selection circuit) and a word line driver, and the like. The column control circuit120controls a plurality of columns of the memory cell array100. The column control circuit120is supplied with an address decoding result (a column address) from the control circuit190. The column control circuit120sets a column (e.g., at least one bit line) based on the address decoding result in a selected state. Hereinafter, the column (or bit line) set in a selected state will be referred to as a selected column (or selected bit line). Columns other than the selected column will be referred to as unselected columns (or unselected bit lines). The column control circuit120includes a multiplexer (a bit line selection circuit), a bit line driver, and the like. The write circuit (also called a write control circuit or a write driver)140performs various types of control for write operation (writing of data). During write operation, the write circuit140supplies the memory cell array100with a write pulse formed by a current and/or a voltage. Accordingly, data is written to the memory cell array100(into the memory cell). For example, the write circuit140is connected to the memory cell array100via the row control circuit110. The write circuit140includes a voltage source and/or a current source, a pulse generation circuit, a latch circuit, and the like. The read circuit (also called a read control circuit or a read driver)150performs various types of control for read operation (reading of data). During read operation, the read circuit150supplies the memory cell array100with a read pulse (e.g., a read current). The read circuit150senses the potential or the current value of a bit line BL. Based on a result of the sensing, data is read from a magnetic body51. For example, the read circuit150is connected to the memory cell array100via the column control circuit120. The read circuit150includes a voltage source and/or a current source, a pulse generation circuit, a latch circuit, a sense amplifier circuit, and the like. The shift circuit (also called a shift control circuit or a shift driver)160performs various types of control for shift operation (shifting of data). During shift operation, the shift circuit160supplies the memory cell array100with a pulse (referred to as a shift pulse hereinafter) to move a domain wall (magnetic domain) in a magnetic body51. For example, the shift circuit160is connected to the memory cell array100via the row control circuit110and the column control circuit120. The shift circuit160includes a voltage source and/or a current source, a pulse generation circuit, and the like. Note that the write circuit140, read circuit150and shift circuit160are not limited to circuits which are independent of one another. For example, these circuits may have a common structural element that is mutually usable and may be arranged in the domain wall memory1as a single integrated circuit. The I/O circuit (input/output circuit)170is an interface circuit that transmits and receives a variety of signals. During write operation, the I/O circuit170transfers data DT from an external device (controller or host device)2to the write circuit140as write data. During read operation, the I/O circuit170transfers data, which is output from the memory cell array100to the read circuit150, to the external device2as read data. The I/O circuit170transfers an address ADR and a command CMD from the external device2to the control circuit190. The I/O circuit170transmits and receives various control signals CNT to and from the control circuit190and the external device2. The voltage generation circuit180generates voltages for a variety of operations of the memory cell array100using a power supply voltage provided from the external device2(or a power supply). For example, during write operation, the voltage generation circuit180outputs various voltages generated for the write operation to the write circuit140. During read operation, the voltage generation circuit180outputs various voltages generated for the read operation to the read circuit150. During shift operation, the voltage generation circuit180outputs various voltages generated for the shift operation to the shift circuit160. The control circuit (also called a state machine, a sequencer or an internal controller)190controls the operation of each circuit in the memory device1in response to the control signals CNT, address ADR and command CMD. The control circuit190includes, for example, a command decoder, an address decoder and a latch circuit. The command CMD is, for example, a signal indicative of an operation to be performed by the domain wall memory1. The address ADR is, for example, a signal indicative of the coordinates of at least one memory cell (hereinafter referred to as a selected cell) to be operated in the memory cell array100. The address ADR includes a row address and a column address of the selected cell. The control signals CNT are, for example, signals for controlling the operation timing between the magnetic memory1and the external device2and the internal operation timing of the magnetic memory1. FIG.2is a schematic diagram showing an exemplary configuration of a memory cell array in the domain wall memory of the first embodiment. In the domain wall memory of the first embodiment, a plurality of magnetic bodies51are provided in the memory cell array100, as shown inFIG.2. The magnetic bodies51are arranged in two dimensions in the memory cell array100in a substrate (not shown). Each of the magnetic bodies51extends in a direction (Z direction) perpendicular to the upper surface (X-Y plane) of the substrate. The Z direction is perpendicular to the X-Y plane. The Z direction intersects X and Y directions. A plurality of word lines WL and a plurality of bit lines BL are provided in the memory cell array100. The word lines WL are arranged in the Y direction. The word lines WL each extend in the X direction. The bit lines BL are arranged in the X direction. The bit lines BL each extend in the Y direction. The bit lines BL are provided above the word lines in the Z direction. Each of the magnetic bodies51is provided between its corresponding word line WL and bit line BL. One end of the magnetic body51is connected to the word line WL. The other end of the magnetic body51is connected to the bit line BL. The magnetic bodies51arranged in the X direction are connected to the same word line WL. The magnetic bodies51arranged in the Y direction are connected to the same bit line BL. For example, a reading element10and a switching element20are connected between a bit line BL and a magnetic body51. The reading element10is provided between the magnetic body51and the switching element20. The reading element10is electrically connected to the magnetic body51and the switching element20. For example, the reading element10is connected to the magnetic body51via a magnetic layer59. During read operation of the domain wall memory1, the reading element10functions as an element that reads data from the magnetic body51(also referred to as a reproducing element hereinafter). The switching element20is provided between the reading element10and the bit line BL. The switching element20is electrically connected to the reading element10and the bit line. The switching element20is used to control the connection between the magnetic body51and the bit line BL. When the switching element20is turned on, the magnetic body51is electrically connected to the bit line BL. When the switching element20is turned off, the magnetic body51is electrically disconnected from the bit line BL. For example, the on/off of the switching element20is controlled under the control of a difference in potential between the bit line BL and the word line WL. Accordingly, at least one magnetic body to be operated is selected from among the magnetic bodies51of the memory cell array100. A conductive layer (interconnect) WRL is provided above the magnetic layer59in the Z direction. The conductive layer WRL extends in the X direction, for example, in an area between the bit line BL and the magnetic layer59. The conductive layer WRL is provided across a plurality of magnetic layers59. The conductive layer WRL is an interconnect for writing data by the magnetic field writing method during write operation of the domain wall memory1(also referred to as a write interconnect hereinafter). During write operation of the magnetic field writing method, a write pulse (also referred to as a write current hereinafter) is supplied to the write interconnect WRL. The write current generates a magnetic field around the write interconnect WRL. The magnetic field is applied to the magnetic layer59. In accordance with the direction of the magnetic field, the directions of magnetization of the magnetic layer59and magnetization MM of the magnetic body51connected to the magnetic layer59are set. Accordingly, data is written to the magnetic body51. The direction of the magnetic field varies with the direction in which a write current flows through the write interconnect WRL. Therefore, the direction in which a write current flows through the write interconnect WRL is set in accordance with data to be written. A plurality of memory cells MC are provided in each of the magnetic bodies51. The memory cells MC are arranged in the Z direction in the magnetic body51. Thus, the memory cells MC are arranged in three dimensions in the memory cell array100. Each of the memory cells MC includes a cell portion (also referred to as a memory portion, a data retention portion or a cell area hereinafter)511. The cell portion511is an area (part) provided in the magnetic body51so as to correspond to a memory cell MC. The cell portion511is a magnetic area (magnetic portion) that may have magnetization MM. When a memory cell MC retains data, the cell portion511has magnetization MM. The data stored in the memory cell MC is associated with the direction of the magnetization MM of the cell portion511. The magnetic body51has perpendicular magnetic anisotropy or in-plane magnetic anisotropy. The direction of magnetization easy axis of the cell portion511corresponds to the magnetic anisotropy of the magnetic body51. Hereinafter, the configuration including at least one memory cell MC in a magnetic body51, a reading element10and a switching element20will be referred to as a memory cell unit (or memory cell string). <Memory Cell Unit> FIG.3is a schematic bird's eye view showing an exemplary configuration of the memory cell unit in the domain wall memory of the first embodiment.FIG.4is a schematic sectional view showing an exemplary configuration of the memory cell unit in the domain wall memory of the first embodiment. As shown inFIGS.3and4, the magnetic body51is provided above a substrate (also referred to as a base layer hereinafter)79in the Z direction. The magnetic body51includes a magnetic layer (also referred to as a domain wall movement layer). The magnetic body51is a magnetic layer having a cylindrical structure extending in the Z direction. For example, the magnetic body51is sandwiched between two insulators (not shown) in a direction parallel to the upper surface of the substrate79. Note that an area surrounded by the cylindrical magnetic body51may be provided with an air gap without being filled with the insulators. For example, the materials of the magnetic body51include at least one element selected from the group consisting of cobalt (Co), iron (Fe), nickel (Ni), manganese (Mn) and chromium (Cr) and at least one element selected from the group consisting of platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru) and rhodium (Rh). More specifically, the materials of the magnetic body51are CoPt, CoCrPt, FePt, CoPd, FePd and the like. Note that the materials of the magnetic body51are not limited to the above materials, but may include other magnetic materials. The magnetic layer59is provided to overlap the magnetic body51in the Z direction. For example, the magnetic layer59has a circular planar shape when viewed from the Z direction. However, the magnetic layer59may have a rectangular planar shape. The dimension of the magnetic layer59in a direction parallel to the surface of the substrate79is greater than dimension D3of the magnetic body51in the direction parallel to the surface of the substrate79. The magnetic layer59is connected to the magnetic body51. For example, the magnetic layer59is a layer that is continuous with the magnetic body51. The magnetization of the magnetic layer59varies according to that of the magnetic body51. For example, the magnetization direction of the magnetic layer59is the same as that of the cell portion511directly connected to the magnetic layer59. The cell portion511directly connected to the magnetic layer59corresponds to one (MCA) of the memory cells in the memory cell unit MU, which is located closest to the bit line. The memory cell MCA functions as a read cell during read operation and functions as a write cell during write operation. The read cell is a memory cell which temporarily retains data from a read-target memory cell during read operation. The write cell is a memory cell to which write data is temporarily written during write operation. A stacked body including the reading element10and the switching element20is provided on the magnetic layer59. The reading element10is a magnetoresistive effect element. The magnetoresistive effect element10is provided to overlap the magnetic layer59in the Z direction. For example, the magnetoresistive effect element10is disposed so as not to overlap the magnetic body51in the Z direction. The magnetoresistive effect element10is disposed on one end side of the magnetic layer59in the Y direction. The magnetoresistive effect element10is electrically connected to the magnetic layer59. For example, the magnetoresistive effect element10includes two magnetic layers11and12and a nonmagnetic layer13. The nonmagnetic layer13is provided between the two magnetic layers11and12in the Z direction. The two magnetic layers11and12and the nonmagnetic layer13form a magnetic tunnel junction (MTJ). Hereinafter, the magnetoresistive effect element10including a magnetic tunnel junction will be referred to as an MTJ element. The nonmagnetic layer13of the MTJ element10will be referred to as a tunnel barrier layer. The magnetic layers11and12are each a ferromagnetic layer including cobalt, iron, boron and the like. The magnetic layers11and12each may be a single-layer film or a multilayer film (e.g., an artificial lattice film). The tunnel barrier layer13is, for example, an insulating film including magnesium oxide. The tunnel barrier layer may be a single-layer film or a multilayer film. The magnetic layers11and12each have in-plane or perpendicular magnetic anisotropy. The magnetization easy axis direction of the magnetic layers11and12having in-plane magnetic anisotropy is substantially parallel to the layer surface (film surface) of the magnetic layers. In this case, each of the magnetic layers11and12has magnetization substantially parallel to the layer surface of the magnetic layer. The magnetization direction of the magnetic layers11and12having in-plane magnetic anisotropy is perpendicular to the arrangement direction (Z direction) of the magnetic layers11and12. The magnetization easy axis direction of the magnetic layers11and12having perpendicular magnetic anisotropy is substantially perpendicular to the layer surface (film surface) of the magnetic layers. In this case, each of the magnetic layers11and12has magnetization substantially perpendicular to the layer surface of the magnetic layer. The magnetization direction of the magnetic layers11and12having perpendicular magnetic anisotropy is parallel to the arrangement direction (Z direction) of the magnetic layers11and12. The magnetization direction of the magnetic layer11is variable. The magnetization direction of the magnetic layer12is invariable (fixed). Hereinafter, the magnetic layer11whose magnetization direction is variable will be referred to as a storage layer. Hereinafter, the magnetic layer12whose magnetization direction is invariable (fixed) will be referred to as a reference layer. Note that the storage layer11may be called a free layer, a magnetization free layer, or a magnetization variable layer. The reference layer12may be called a pin layer, a pinned layer, a magnetization invariable layer, or a magnetization fixed layer. The magnetization direction of the storage layer11and that of the magnetic layer59vary in conjunction with each other. For example, the magnetization direction of the storage layer11is the same as that of the magnetic layer59. Note that the magnetic layer59may be used as a storage layer of the MTJ element10. In this case, the nonmagnetic layer13is provided on the magnetic layer59such that the nonmagnetic layer13is brought into direct contact with the magnetic layer59without forming the magnetic layer11. In the first embodiment, “the magnetization direction of the reference layer (magnetic layer) is invariable or fixed” means that when a current, a voltage or magnetic energy (e.g., a magnetic field) which varies the magnetization direction of the storage layer is supplied to the magnetoresistive effect element10, the magnetization direction of the reference layer does not vary before or after the supply of the current, voltage or magnetic energy. The switching element20is provided above the MTJ element10in the Z direction. The switching element20is electrically connected to the MTJ element10through, for example, a contact plug CP1(or a conductive layer). The switching element20may be directly connected to the MTJ element10but not through any other member. The switching element20includes, for example, two electrodes21and22and a switching layer23. The switching layer23is provided between the two electrodes21and22. The electrode21is provided on the contact plug CP1in the Z direction. The switching layer23is provided on the electrode21in the Z direction. The electrode22is provided on the switching layer23in the Z direction. The material of the switching layer23is a transition metal oxide, a chalcogenide compound or the like. The switching element20switches an electrical connection between the memory cell unit MU and the bit line BL. As a result, the activation/deactivation (select/nonselection) of the memory cell unit MU can be controlled. The resistance state of the switching layer23changes to a high resistance state or a low resistance state according to the supplied current (or voltage). Thus, the switching element20is set in an ON state (a low resistance state, a conduction state) when the memory cell unit MU is supplied with a current that is equal to or larger than the threshold current of the switching element20(or a voltage that is higher than the threshold voltage of the switching element20). The switching element20is set in an OFF state (a high resistance state, a nonconduction state) when the memory cell unit MU is supplied with a current that is smaller than the threshold current of the switching element20. The switching element20in an OFF state electrically separates the memory cell unit MU from the bit line BL. The switching element20in an ON state can cause a current to flow through the memory cell MC. The switching element20in an ON state supplies the memory cell unit MU with a current flowing from the bit line BL toward the word line WL or a current flowing from the word line WL toward the bit line BL in accordance with a difference in potential between the bit line BL and the word line WL. As described above, the switching element20is an element capable of causing a current to flow through the memory cell unit MU bidirectionally. The conductive layer70is provided between the magnetic body51and the substrate79. The conductive layer70is provided on an insulating layer (not shown) covering the upper surface of the substrate79. The conductive layer70extends in the X direction. Note that a magnetic layer or a conductive layer may be provided between the conductive layer70and the magnetic body51. The conductive layer70is used as a word line WL. The conductive layer70as a word line WL is electrically connected to the row control circuit110. The activation/deactivation (selection/nonselection) of the word line WL is controlled by the row control circuit110. The conductive layer71is provided above the switching element20in the Z direction. The conductive layer71is electrically connected to the switching element20through a contact plug CP2. The conductive layer71extends in the Y direction. The conductive layer71is used as a bit line BL. The conductive layer71as a bit line BL is electrically connected to the column control circuit120. The activation/deactivation (selection/nonselection) of the bit line BL is controlled by the column control circuit120. A conductive layer75is provided in an insulating layer98between the magnetic layer59and the bit line BL. The conductive layer75is adjacent to the stacked body including the MTJ element10and the switching element20in the Y direction. The conductive layer75extends in the X direction. The conductive layer75is used as a write interconnect WRL. The conductive layer75as a write interconnect is electrically connected to the row control circuit110and the write circuit140. The activation/deactivation of the write interconnect75is controlled by the row control circuit110. The supply of write current PWR to the write interconnect WRL is controlled by the write circuit140. In the domain wall memory of the first embodiment, as shown inFIGS.3and4, the dimension of the magnetic body51(e.g., the diameter of the cylindrical magnetic layer) in a direction parallel to the upper surface of the substrate79(X or Y direction) varies periodically along the Z direction. The magnetic body51is constricted at predetermined intervals (periods) in the Z direction. In the first embodiment, the structure with periodic variations in dimension (periodic constriction) is called a constricted structure. The constricted structure includes a plurality of constricted portions. Hereinafter, constricted portions519of the magnetic body51will also be referred to as concave portions519. A range (area) including the concave portions519with certain dimensions in the Z direction is called a constricted area (or a domain wall existing area). For example, the constricted area has a certain range centered around the concave portions519. The concave portions519each have a certain dimension DB. Therefore, the constricted area may be considered to be the concave portions519. The dimension (diameter of the cylindrical portion) D1of each concave portion519in a direction parallel to the upper surface of the substrate (X or Y direction) is smaller than that of a portion other than the concave portion519in the constricted area. The dimension D1is the minimum dimension of the magnetic body51having a constricted structure in the X direction (or Y direction). The magnetic body51includes a plurality of portions511. Each of the portions511is provided between two concave portions519arranged in the Z direction. The portions511protrude from outside the cylindrical magnetic body in a direction parallel to the upper surface of the substrate79relative to the concave portions519. Hereinafter, the portions511will be referred to as convex portions511. The convex portions511substantially correspond to the cell portions of the memory cell MC. The convex portions511are each provided in an area (range) between two concave portions519of the magnetic body51. Hereinafter, the area (range) between the two concave portions519will be referred to as a cell area (magnetized area or domain wall movement area). Each of the convex portions511is provided between two concave portions (constricted areas)519in the Z direction. Each of the concave portions (constricted areas)519substantially corresponds to a boundary portions of adjacent memory cells MC in the Z direction. The convex portions511each have a dimension (diameter of the cylindrical portion) D2in a direction parallel to the upper surface of the substrate79(X or Y direction). The dimension D2is larger than the dimension D1of the concave portion519. For example, the dimension D2is the maximum dimension of the magnetic body51having a constricted structure in the X direction (or Y direction). The dimension of each convex portion (cell area)511in the X direction (or Y direction) gradually decreases from the central part of the convex portion511toward the concave portions519. The volume of the magnetic body (magnetic layer) of the concave portion519is smaller than that of the magnetic body of the convex portion511. Each convex portion (cell area)511in one magnetic body51may have magnetization (a magnetic domain). For example, the magnetic body51has perpendicular magnetic anisotropy. The film surface (layer surface) of the cylindrical magnetic body51is in the direction along the Z direction. Thus, the magnetization easy axis direction of the magnetic body51having perpendicular magnetic anisotropy intersects with the Z direction. When the magnetic body51has perpendicular magnetic anisotropy, for example, a magnetic layer having perpendicular magnetic anisotropy is used for the magnetic layers11and12of the MTJ element10. In this case, however, a magnetic layer having an in-plane magnetic anisotropy may be used for the magnetic layers11and12of the MTJ element10. Note that the magnetic body51may have in-plane magnetic anisotropy. In this case, the magnetization easy axis direction of the magnetic body51is parallel to the Z direction. When the magnetic body51has in-plane magnetic anisotropy, for example, a magnetic layer having in-plane magnetic anisotropy is used for the magnetic layers11and12of the MTJ element10. In this case, however, a magnetic layer having perpendicular magnetic anisotropy may be used for the magnetic layers11and12of the MTJ element10. <Exemplary Configuration> FIG.5is a sectional view showing an exemplary configuration of the magnetic memory of the first embodiment.FIG.5shows a section (Y-Z section) of the domain wall memory of the first embodiment, taken along the Y direction. FIG.6is a top view (plan view) showing an exemplary configuration of the magnetic memory of the first embodiment. As shown inFIG.5, the magnetic memory of the first embodiment has a bonding structure of two chips. In the first embodiment, a chip400including a memory cell array (also referred to as a memory cell array chip hereinafter) is bonded to a chip410including a memory control circuit CC (also referred to as a memory control circuit chip hereinafter). The memory cell array chip400overlies the memory control circuit chip410in the Z direction. The memory control circuit chip410includes a plurality of field effect transistors (also referred to simply as transistors) TR. The transistors TR constitute each of circuits110to190other than the memory cell array of the magnetic memory1. The transistors TR are provided in an area (hereinafter referred to as a circuit area) A5of the chip410. The transistors TR are arranged in an active area AA in a semiconductor substrate (e.g., a silicon substrate)41. The active area AA is a semiconductor region isolated by element isolation regions (insulating layers49) in the silicon substrate41. A well region45of a certain conductivity type is provided in the active area AA. The transistors TR are provided in the well region45. A gate electrode31of each transistor TR is provided above the well region45with a gate insulating layer30therebetween. The source/drain regions32aand32bof the transistor TR are provided in the well region45. The source/drain regions32aand32bsandwich a channel region of the transistor TR in a direction parallel to the upper surface of the substrate41. The gate electrode31is opposed to the channel region with the gate insulating layer30therebetween. The gate electrode31of the transistor TR is covered with an interlayer insulating layer39on the silicon substrate41. A plurality of plugs34and36, a conductive layer (interconnect)35and a pad38are provided in the interlayer insulating layer39. The plug (contact portion)34is provided on the source/drain region32(32a,32b). The conductive layer (intermediate interconnect)35is connected to the source/drain region32via the plug34. The plug (contact portion)36is provided on the conductive layer35. The pad38is connected to the conductive layer35via the plug36. For example, the memory control circuit chip410includes an area (referred to as an alignment mark area hereinafter) A6provided with an alignment mark991. The alignment mark area A6is adjacent to a circuit area A5in a direction parallel to the surface of the chip410. The memory cell array chip400is provided above the memory control circuit chip410in the Z direction. The memory cell array chip400includes a plurality of memory cell units MU as described above (seeFIGS.3and4). Each of the memory cell units MU includes a plurality of magnetic bodies51. The magnetic bodies51are provided in an insulating layer61. As shown inFIG.5, an area A1including a plurality of memory cell units MU (referred to as a memory cell array area hereinafter) is provided in the memory cell array chip (also referred to as an alumina plate hereinafter)400. In the memory cell array area A1, the magnetic bodies51are provided in holes910in the insulating layer61. For example, the insulating layer61is an aluminum oxide layer (e.g., a porous alumina layer). Hereinafter, the holes910in the alumina layer61will be referred to as alumina holes910. In each alumina hole910, the magnetic body51is provided between the alumina layer61and an insulating layer62. The magnetic bodies51extend in the Z direction. The magnetic bodies51are each shaped like a cylinder. The magnetic bodies51are periodically constricted in the Z direction. The dimension (diameter) of each magnetic body51in a direction parallel to the surface of the chip periodically varies along the Z direction. In the memory cell array area. A1, the alumina holes910(members51and62in the holes) are arranged at predetermined pitches Dp1. Each pitch Dp1is an interval between the centers of two alumina holes910in a direction (e.g., Y direction) parallel to the surface (upper surface) of the chip400. The reading element10and switching element20of the memory cell unit MU are provided between the magnetic body51and the memory control circuit chip410in the Z direction. The reading element10is connected to the magnetic body51via the magnetic layer59. The reading element10is connected to a interconnect71(bit line BL) via the switching element20. The write interconnect75(WRL) is provided between the magnetic layer59and the interconnect71in the Z direction. The reading element10, switching element20and interconnects71and75are covered with an interlayer insulating layer69. The interlayer insulating layer69is provided between the alumina layer61and the interlayer insulating layer39in the Z direction. The reading element10, switching element20and interconnects71and75are provided below the memory cell MC and above the memory control circuit chip410in the Z direction. A plurality of pads73are provided below the interconnect71in the Z direction. The pads73are connected to an interconnect (e.g., interconnect71) in the memory cell array chip400. The pads73are provided on a first surface (also referred to as a bonding surface) of the memory cell array chip400. One or more of the pads73are each in direct contact with the pad38of the memory control circuit chip410. Each memory cell unit MU is connected to a transistor TR (circuit) in the memory control circuit chip410via a pad73. The pads73and38function as pads for bonding the chips400and410(referred to as bonding pads hereinafter). For example, the chips400and410are bonded together by covalent bonding between the pads38and73and/or between the insulating layers39and69. Note that at least one of the pads73need not be connected to any components in the memory cell array chip400and at least one of the pads38need not be connected to any components in the memory control circuit chip410. A plurality of pads78and interconnects (e.g., word lines)70are provided on the surface (second surface of the memory cell array chip) opposed to the surface provided with the bonding pads73. The interlayer insulating layer79covers the second surface of the memory cell array chip400. The interconnects70are each connected to its corresponding magnetic body51. The interconnects70are covered with the interlayer insulating layer79. The pads78each function as an external connection terminal for connecting the magnetic memory to another device. The pads78are electrically connected to the interconnects (e.g., interconnects70) in the magnetic memory. Note that the memory control circuit chip410may be provided with an external connection terminal (not shown). In the first embodiment, an area A2including an alignment mark (referred to as an alignment mark area hereinafter) is provided at an end of the memory cell array chip (alumina plate)400. The alignment mark area A2is opposed to the alignment mark area A6of the memory control circuit chip410in the Z direction. In the alignment mark area A2, an alumina hole910A is provided in the alumina layer61. For example, in the alignment mark area A2, the alumina hole910A includes substantially the same as the members51and62in the alumina hole910of the memory cell array area A1. For example, in the alignment mark area A2, conductive layers55are provided to overlap the members51and62in the Z direction. The conductive layers55are provided on that side of the memory cell array chip400which is provided with the bonding pads73. A mark portion (mark member)990is provided in the alumina hole910A of the alignment mark area A2. For example, the mark portion990includes the magnetic body51, insulating layer62and conductive layer55. The alignment mark AM is formed using one or more mark portions990. In the first embodiment, alignment between members (e.g., alignment between a mask and a substrate during lithography) in a certain step at the time of forming the memory cell array chip400is performed using the alignment mark. AM of the memory cell array chip400. When two chips (wafers) are bonded together, alignment of the chips (wafers) is performed using the alignment mark AM of the memory cell array chip400and the alignment mark991of the memory control circuit chip410. In the alignment mark area A2, a plurality of alumina holes910A (members51and62in the holes910A) are arranged at predetermined pitches Dp2. Each pitch Dp2is an interval between the centers of two alumina holes910A in a direction (e.g., Y direction) parallel to the surface (supper surface) of the chip400. For example, the pitch Dp2is the same as the pitch Dp1. However, the pitch Dp2may be different from the pitch Dp1. For example, in the memory cell array chip400, at least one alumina hole910X is provided in an area A3between the memory cell array area A1and the alignment mark area A2. The configuration of the alignment mark area will be described with reference toFIG.6. FIG.6is a top view showing an exemplary configuration of the memory cell array chip (alumina plate) in the magnetic memory of the first embodiment.FIG.6shows a plane in which alumina holes910and910A are formed in the Z direction of the memory cell array chip400. As shown inFIG.6, the memory cell array area A1is provided in the memory cell array chip400. The magnetic body51of the memory cell unit MU is provided in the memory cell array area A1. The magnetic body51is provided in the hole (alumina hole)910in the alumina layer61. The alumina holes910and magnetic bodies51are arranged in the memory cell array area A1in a hexagonal lattice when viewed from the Z direction, for example. The hexagonal lattice arrangement is a layout in which components that form one lattice are arranged at the apexes of a hexagon and around the center thereof. The alumina holes910and magnetic bodies51are arranged regularly at certain pitches Dp1. For example, each pitch Dp1is an interval between the centers of adjacent two alumina holes in the Y direction when the chip400is viewed from the Z direction. FIG.6shows the pitch Dp1of the alumina holes (magnetic bodies) in the Y direction in the memory cell array area A1. With respect to the alumina holes910in the memory cell array area A1, however, the pitch of two alumina holes910arranged in the X direction and the pitch of two alumina holes910arranged obliquely to the X-Y plane are each set to a predetermined size. The alumina holes910each have a dimension. Da (a dimension from dimension D1to dimension D2) in a direction parallel to the X-Y plane. The alumina holes910A have substantially the same dimension Db. The alignment mark area A2is provided in the chip400so as to be adjacent to the memory cell array area A1in a direction parallel to the upper surface of the chip400. For example, the alignment mark area A2surrounds the memory cell array area A1in the direction parallel to the top surface of the chip400. The alignment mark area A2is a rectangular ring-shaped area. For example, the alignment mark area A2is provided in a dicing area of a wafer for forming the memory cell array chip (alumina plate)400. The memory cell array chip400is cut out of a wafer by dicing the wafer. In the alignment mark area A2, a plurality of alumina holes910A and a plurality of magnetic bodies51are arranged in a hexagonal lattice when viewed from the Z direction, for example, like the alumina holes910and magnetic bodies51in the memory cell array area A1. A magnetic body51and an insulating layer62are provided in each of the alumina holes910A. The internal components of the alumina holes910A are substantially the same as those of the alumina holes910. In the alignment mark area A2, however, in order to improve alignment accuracy, the conductive layers55may be provided to overlap the alumina holes910A (magnetic bodies51and insulating layers62) in the Z direction. For example, a conductive layer55, a magnetic body51and an insulating layer62constitute a mark portion990of the alignment mark. The alumina holes910A and magnetic bodies51are regularly arranged at certain pitches Dp2(e.g., Dp2=Dp1). For example, each pitch Dp2is an interval between the centers of adjacent two memory holes in the Y direction when the chip400is viewed from the Z direction. For example, at a position from the Z direction, dimension Db of the alumina hole910A in a direction parallel to the X-Y plane is the same as dimension Da of the alumina hole910in a direction parallel to the X-Y plane. The alumina holes910A have substantially the same dimension Db. FIG.6shows, in the alignment mark area A2, pitch Dp2of the alumina hole (magnetic body) in the Y direction. With respect to the alumina holes910A in the alignment mark area A2, however, the pitch of two alumina holes910A arranged in the X direction and the pitch of two alumina holes910A arranged obliquely to the X-Y plane are each set to a predetermined distance. Note that in the alignment mark area A2, the pitch Dp2between the alumina holes910A (embedded members51and62) may be different from the pitch Dp1between the alumina holes910. The dimensions Db of the alumina holes910A (embedded members51and62) may be different from the dimensions Da of the alumina holes910. The alignment mark AM is formed of one or more mark members (e.g., seven mark members constituting a hexagonal lattice)990. Note that in the alignment mark area A2, a plurality of alumina holes910B other than the alumina holes910A for forming the alignment mark AM may be arranged randomly at no predetermined pitches. The alumina holes910B need not have uniform dimensions. Accordingly, members51B and62B in each of the alumina holes910B are arranged randomly in the area A2. The members51B and62B do not have uniform dimensions. For example, an area A3(also referred to as an intermediate area hereinafter) is provided between the memory cell array area A1and the alignment mark area A2. The intermediate area A3surrounds the memory cell array area A1between the memory cell array area A1and the alignment mark area A2. The intermediate area A3includes a plurality of alumina holes910X. Each of the alumina holes910X includes a magnetic body51and an insulating layer62. The configuration of the intermediate area A3differs from that of the memory cell array area A1and that of the alignment mark area A2. In the intermediate area A3, the alumina holes910X are arranged randomly in no hexagonal lattice. In the intermediate area A3, the alumina holes910X are arranged irregularly. The intervals (pitches) between the aluminum holes910X are different from one another. For example, the internal members (magnetic bodies51and insulating layers62) of the alumina holes910X do not function as components of the memory device1. Hereinafter, the internal members51and62of the alumina holes910X will also be referred to as dummy members. In the intermediate area A3, the alumina holes910X may have different dimensions in a direction parallel to the X-Y plane. The alumina holes910X may have different dimensions (depths) in the Z direction. Hereinafter, the areas A1and A2in which the holes are arranged at predetermined pitches will also be referred to as regular alignment areas. The area A3in which the holes are irregularly aligned will also be referred to as an irregular alignment area (or a free alignment area). In the domain wall memory of the first embodiment, members (mark portions) for forming an alignment mark are regularly aligned at predetermined pitches in the alignment mark area A2. The mark portions are provided in the holes of an alumina layer formed by anodic oxidation. Note that the operation of the domain wall memory of the first embodiment is performed by the known technique. For example, in a read sequence of the domain wall memory, data to be read from a memory cell is shifted to a read cell by a shift operation. The data shifted to the read cell is read by the reading element (MTJ element)10. For example, in a write sequence of the domain wall memory, a write current that flows in a direction corresponding to write data is supplied to a write interconnect. The data is written to a write cell by a magnetic field generated from the write interconnect. The data written to the write cell is shifted to a memory cell to which the data is written, by a shift operation. (1b) Manufacturing Method A method for manufacturing a domain wall memory of the first embodiment will be described with reference toFIGS.7through15. FIG.7is an illustration of one step of a method for manufacturing a magnetic memory of the first embodiment. As shown inFIG.7, an aluminum layer60is formed on a first silicon substrate40(silicon wafer9). The thickness of the aluminum layer60is approximately several micrometers to several hundreds of micrometers, for example. It is preferable to use high-purity aluminum whose purity is 99.9% or higher for the aluminum layer60. The aluminum layer60is formed using sputtering, plating, chemical vapor deposition (CVD), bonding of an aluminum layer (aluminum substrate, aluminum foil) to the silicon substrate40, and the like. In the example ofFIG.7, the aluminum layer60is in direct contact with the silicon substrate40. However, a film of another material (e.g., an insulating layer) may be formed between the aluminum layer60and the silicon substrate40. In this case, the aluminum layer60is formed on the insulating layer covering the silicon substrate40. FIGS.8and9are illustrations of one step of the method for manufacturing the magnetic memory of the first embodiment.FIG.8is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment.FIG.9is a schematic top view (plan view) corresponding to the step shown inFIG.8. As illustrated inFIG.8, a resist mask90is formed on the surface (upper surface) of the aluminum layer60in the Z direction by lithography (e.g., photolithography). The resist mask90has a plurality of patterns (openings)901for forming a reaction starting point of anodic oxidation to the aluminum layer60. As shown inFIG.9, it is preferable that the patterns901of the resist mask90be laid out in a hexagonal lattice (hexagonal close-packed lattice). Each pattern901includes a hole pattern. The hole pattern901has a circular (elliptical) planar shape when viewed from the Z direction. The pitch DP (Dp1, Dp2) between hole patterns901is about several tens of nanometers to several hundreds of nanometers. The pitch DP is a distance between the centers of two patterns800in the Y direction. For example, the hole patterns901are formed in the memory cell array area A1and the alignment mark area (dicing area of the wafer9) A2. For example, no hole patterns are formed in the area A3between the memory cell array area A1and the alignment mark area A2. In addition, no hole patterns may be formed in an area other than the area of the alignment mark area A2where the alignment marks are arranged. It is preferable to planarize the upper surface of the aluminum layer60through a planarization process such as CMP before lithography. The upper surface of the aluminum layer60is etched by dry etching or wet etching using a resist mask90having hole patterns901as a mask. Thus, a recess900is formed in the upper surface of the aluminum layer60. The depth (the dimension in a direction perpendicular to the surface of the substrate40) Dz of the recess900is, for example, about several nanometers to several tens of nanometers. The recess900formed by etching serves as a reaction starting point for anodic oxidation of the aluminum layer60. As described above, in the first embodiment, the reaction starting point900for anodic oxidation of the aluminum layer60is formed in the memory cell array area A1and the alignment mark area (dicing area) A2. FIG.10is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As shown inFIG.10, anodic oxidation is performed for the aluminum layer. The aluminum layer and the silicon substrate40are immersed in an electrolyte solution (sulfuric acid, oxalic acid, phosphoric acid, etc.)891in an anodic oxidation device. In the electrolyte solution891, the silicon substrate40is set as an anode. A voltage (hereinafter referred to as anodic oxidation voltage) V1for anodic oxidation is applied to the silicon substrate40from a voltage circuit899. Thus, an alumina layer (aluminum oxide layer)61is formed above the silicon substrate40by oxidation of the aluminum layer. If the anodic oxidation voltage V1is optimized, holes (alumina holes)910and910A are formed in the alumina layer61(or the aluminum layer60) to extend in a direction (Z Direction) perpendicular to the upper surface of the silicon substrate40at substantially the same pitches Dp1and Dp2as the pits of the reaction starting point (recess)900formed in advance. During the anodic oxidation for the aluminum layer, the anodic oxidation voltage V1may be modulated periodically (at regular time intervals). In accordance with the magnitude of the anodic oxidation voltage V1, periodic constriction (recess)519is generated in the alumina holes910and910A. As a result, the alumina holes910and910A can be formed to have a constriction structure. The alumina holes910have a structure in which spherical spaces are connected in the Z direction. Furthermore, the depth (dimension in the Z direction) of the alumina hole910can be adjusted to a desired size by adjusting time for anodic oxidation. Thus, an unreacted aluminum layer60A may remain under the alumina holes910and910A. For example, the aluminum layer60A may be formed on the insulating layer on the silicon substrate40. Due to the presence of the aluminum layer60A, even though an insulating layer is present between the silicon substrate40and the aluminum layer60, the anodic oxidation voltage V1can be applied to the aluminum layer from the outer periphery of the substrate to the central part of the substrate via the unreacted aluminum layer60A if the aluminum layer is used as an electrode. When the alumina holes910and910A are formed to extend in the Z direction by anodic oxidation, an alumina barrier layer619is formed on the bottom of each of the alumina holes910and910A. As described above, the shape of the alumina holes is controlled by forming a reaction starting point in anodic oxidation for the aluminum layer and controlling the anodic oxidation voltage. Therefore, a plurality of alumina holes910and910A, which are arranged regularly (e.g., at predetermined pitches Dp1and Dp2), are formed in the memory cell array area A1and the alignment mark area A2. For example, the alumina hole910X is formed simultaneously with the alumina hole910in the intermediate area A3. The alumina hole910X is formed in the alumina layer61without any reaction starting point (recess). Thus, the alumina holes910X in the intermediate area A3are formed randomly in the area A3, unlike the alumina holes910in the areas A1and A2. Furthermore, the alumina holes910X in the intermediate area A3may vary in depth. FIG.11is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.11, in the memory cell array area A1and the alignment mark area A2, magnetic bodies (magnetic layers)51are formed in the alumina holes910and910A by CVD or Atomic layer deposition (ALD). For example, the formed magnetic body51has a cylindrical structure in the alumina holes910and910A. The structure of the formed magnetic bodies51depends upon the shape of the alumina holes910and910A. When the alumina holes910and910A have a periodic constriction as described above, the magnetic body51is periodically constricted. The magnetic bodies51have constricted portions (recesses)519at certain intervals in the Z direction. Protrusions511that protrude toward the outer surfaces of the magnetic bodies51are each provided between the recesses519arranged in the Z direction. As described above, in the constricted magnetic bodies51, the protrusions511and the recesses519are formed in the alumina holes910and910A such that they are arranged alternately in the Z direction. Insulating layers (e.g., a silicon oxide layers)62are each buried in a gap of the corresponding cylindrical magnetic layer51by CVD, ALD or coating. In the intermediate area A3, the magnetic bodies and insulating layers are formed in the alumina holes (not shown) by a step common to that of forming the magnetic bodies51and the insulating layers62in the areas A1and A2. In the intermediate area A3, a plurality of magnetic bodies (and insulating layers) are arranged at irregular pitches. The magnetic bodies51in the intermediate area A3are formed nonuniformly in its shapes. For example, in the alignment mark area A2, an upper portion of the magnetic body51in the alumina hole910is removed by etching. Accordingly, a recess is formed in the upper surface of the alumina layer61in the area A2. A conductive layer (e.g., a metal layer)55is formed in the recess above the magnetic material51. FIG.12is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.12, components10,20and59, interconnects71and75, interlayer insulating film68and the like of the memory cell unit are formed above a first surface of the alumina layer61by the known technique. For example, a plurality of magnetic layers59are formed on the upper surface of the alumina layer61by the known technique. Each of the magnetic layers59is connected to its corresponding magnetic body51. A write interconnect75is formed above each of the magnetic layers59. A reading element (e.g., an MTJ element)10is formed on the upper surface of each of the magnetic layers59in the Z direction. A switching element20is formed on the reading element10in the Z direction. A bit line71is formed above the alumina layer61so as to be connected to the switching element20. A plurality of pads (e.g., bonding pads)73are formed above the bit line71. Lithography (e.g., photolithography) is performed for patterning each of the components10,20,59,71and75. In the first embodiment, a mask for the lithography is aligned with the substrate40(wafer9) using the alignment mark AM (mark portion990in the hole910A) formed during anodic oxidation. FIG.13is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.13, a memory control circuit (CMOS circuit) CC is formed in a circuit area A5of a second silicon substrate41(wafer9A) by the known technique. For example, the gate insulating layer30and gate electrode31of the transistor TR are formed on the active area AA (well region45) of the silicon substrate41. The source/drain regions32(32a,32b) of the transistor TR are formed in the well region45. The plug36and interconnect are formed in the interlayer insulating film39covering the transistor TR. The pad38is formed above the upper surface of the second silicon substrate41. For example, the alignment mark991is formed in the alignment mark area (dicing area) A6of the silicon substrate41(wafer). Note that the process of forming the memory control circuit CC may be executed in parallel with the process of forming the memory cell array100, or may be executed before or after the process of forming the memory cell array100. The two silicon substrates (silicon wafers)40and41are bonded together. The upper surfaces (hereinafter referred to as bonded surfaces) of the silicon substrates40and41are bonded to each other. The silicon substrate40is bonded to the silicon substrate41such that the pad (e.g., bonding pad)73of the silicon substrate40is opposed to the pad (e.g., bonding pad)38of the silicon substrate41. For example, the bonding pad73is bonded to the bonding pad38such that the silicon substrate41is located below the silicon substrate40in the Z direction. The two silicon substrates40and41are bonded together by covalent bonding generated between the pads73and38(and covalent bonding generated between the interlayer insulating layers68and39). For example, in the first embodiment, when the silicon substrates40and41are bonded, they are aligned with each other using the alignment mark AM in the alumina layer61and the alignment mark991in the silicon substrate41. FIG.14is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.14, silicon on the upper side of the bonded two silicon substrates40and41(Here, the back surface of the first silicon substrate40) is removed by polishing such as back grinding. Thus, the unreacted aluminum layer60A is exposed. The silicon substrate (wafer)41supports the thinned substrate40. The unreacted aluminum layer60A is removed by etching (e.g., wet etching). Thus, the alumina barrier layer619(the bottom of the alumina hole910) above the magnetic body51in the Z direction is exposed. FIG.15is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.15, the exposed alumina barrier layer619is etched by wet etching using phosphoric acid, for example. Thus, the magnetic bodies51are exposed from the alumina holes910and910A. FIG.16is a schematic sectional view illustrating one step of the method for manufacturing the magnetic memory of the first embodiment. As illustrated inFIG.16, the magnetic bodies51and insulating layers62are planarized by CMP. At this time, the magnetic bodies51and insulating layers62are polished using the alumina layer61as a stopper layer. After that, the components of the magnetic memory such as electrodes, elements, interconnects and pads are formed by the known technique so as to be connected to the magnetic bodies51, as shown inFIG.5. For example, the interconnects (e.g., word lines WL) are formed to extend in the X direction on the second surface of the alumina layer61so as to be connected to the magnetic bodies51. The interlayer insulating layer79is formed on the alumina layer61to cover the interconnects70. A plurality of pads (external connection terminals)78are formed in the interlayer insulating layer79. The pads78are connected to the interconnects70,71and75and the like in the interlayer insulating layers68and79. In forming the interconnects70and pads78, the alignment mark AM of the memory cell array chip400may be used to align the mask for lithography with the wafer. Thus, the domain wall memory1of the first embodiment is formed with the memory control circuit chip (wafer)41as a support substrate. After that, the domain wall memory1of the first embodiment is chipped by dicing the wafer. At this time, some or all of the alignment marks of the alignment mark area A2in the dicing area may be cut out, and the alignment marks may be removed from the chips of the domain wall memory. The magnetic memory of the first embodiment is thus completed as described above. (c) Summary In the first embodiment, the magnetic memory has a structure in which two chips are bonded together. In a plurality of steps to be performed after a backgrinding step for silicon substrates (wafers) to forming memory cell array chips, a substrate for forming memory control circuit chips serves as a support substrate for the memory cell array chips formed by wafer backgrinding. In the first embodiment, therefore, even when a wafer having a large diameter is used as a substrate, no substrate handing problem occurs. In the magnetic memory of the first embodiment, the magnetic bodies51serving as memory units are provided in the holes910formed in the insulating layer61. The holes910are formed by anodic oxidation for the aluminum layer. In the magnetic memory of the first embodiment, the alignment mark AM is used in different steps of forming the magnetic memory. A general alignment mark is formed by transferring a resist pattern, which is formed simultaneously with a lithography step for the surface of a substrate (wafer), to the substrate by dry etching. When anodic oxidation is performed for the aluminum layer60on the wafer to form the holes, even if an alignment mark is formed on the surface of the aluminum layer60using a material before anodic oxidation, the shape of the alignment mark is deformed due to the volume expansion of aluminum close to the alignment mark when the aluminum is changed to alumina during anodic oxidation. The use of the alignment mark after the anodic oxidation step is not therefore preferable. In a step of forming a reaction starting point (recess) of anodic oxidation in the aluminum layer (e.g., a resist mask photolithography step), it is desirable to form an alignment mark for a lithography step. In the first embodiment, a member for forming the alignment mark AM is provided in the hole910A of the layer61formed by anodic oxidation. In the first embodiment, as shown inFIGS.6and8to12, the area A2in which the alignment mark AM is formed and the area A3in which no alignment mark is formed are provided separately in the memory cell array chip. The pattern990of the alignment mark AM is formed using, for example, the same hole pattern as a hole pattern for forming a memory unit (e.g., a magnetic body). In the first embodiment, the alignment mark AM includes mark portions990in a plurality of holes910A in a hexagonal lattice in the alignment mark area A2. In the alignment mark area A2, like the alumina holes (hole patterns)910for forming a memory unit, the alumina holes910A whose alignment is controlled are formed for an arrangement of the alignment mark AM by anodic oxidation. No alumina holes having a predetermined alignment are formed in the area A3where no alignment marks (and memory cell unit) are arranged. For example, in the area A3, a plurality of alumina holes910X are formed in the alumina layer61in an unaligned state (natural alignment state). In this case, according to the first embodiment, since anodic oxidation of aluminum occurs in the areas A2and A3(and A1), the alignment mark can be prevented from being deformed due to its volume expansion. In the first embodiment, the detection of the alignment mark so formed makes it possible to form, by the lithography, components such as switching elements and reading elements (write or read elements) in positions that overlap the alumina holes in the memory cell array area in the Z direction. According to the first embodiment, when an electrode connected to the magnetic layer is formed by lithography on the surface opposed to the bonding surface of a chip, the aluminum layer used for anodic oxidation does not exist on the opposed surface but changes into an alumina layer through which illumination light for alignment can be transmitted. In the present embodiment, therefore, the formed alignment mark can be detected from the surface opposed to the bonding surface of a chip. As a result, an electrode can be formed on the opposed surface by lithography for alignment using mark portions in the alumina holes. As described above, in the first embodiment, the alignment mark does not change in its shape. As a result, the accuracy of alignment in the manufacturing process of the magnetic memory is improved. It should be noted that not only the alignment mark but also, for example, a mark for measuring an overlay with a lithography layer to be performed after the anodic oxidation step, may be formed by substantially the same process as the formation of the alignment mark. When a layer to be oxidized by anodic oxidation is increased in its thickness, the rectilinearity of hole formation may be lost in a deep portion of the alumina hole (a portion opposed to the reaction starting point in the Z direction). Therefore, the boundary between the area A2in which the alignment of the alumina holes is controlled and the area A3in which it is not controlled may become unclear. In the first embodiment, a material other than alumina (e.g., a material having relatively high reflectivity, such as metal) may be embedded on the surface (bonding surface, reaction starting point forming surface) of the alumina hole where the boundary between the alignment mark area (regular alignment area) A2and the area (natural alignment area) A3is relatively clear. In the first embodiment, therefore, higher-accuracy alignment can be achieved. As described above, the memory device and the method for manufacturing of the memory device of the first embodiment can be improved in reliability of process of manufacturing the memory device. In addition, the memory device and the manufacturing method can improve the yield of devices to be manufactured. (2) Second Embodiment A memory device of the second embodiment and a method for manufacturing the memory device will be described with reference toFIGS.17through25. (2a) Exemplary Configuration FIG.17is a block diagram showing an exemplary configuration of the memory device of the second embodiment. The memory device of the second embodiment is a semiconductor memory. As shown inFIG.17, the semiconductor memory of the second embodiment includes a memory cell array100A and a memory control circuit (CMOS circuit) CCA. In the second embodiment, the semiconductor memory device is a dynamic random access memory (DRAM). In the DRAM1A of the second embodiment, the memory cell array100A differs in configuration from the memory cell array of the domain wall memory of the first embodiment. The memory cell array100A includes a plurality of memory cells MCd, a plurality of word lines WL and a plurality of bit lines BL. Each of the memory cells MCd is connected to at least one word line WL and at least one bit line BL. Each of the memory cells MCd can store data of one bit or more. Each of the memory cells MC of the DRAM1A includes a field effect transistor (also referred to as a cell transistor hereinafter) and a capacitive element (also referred to as a cell capacitor hereinafter). The DRAM1A of the second embodiment includes a row control circuit110, a column control circuit120, a read/write circuit145, an I/O circuit170, a control circuit190and the like as a memory control circuit (CMOS circuit) CCA. Substantially as in the first embodiment, the row control circuit110and column control circuit120control the rows (e.g., word lines) and columns of the memory cell array100A in accordance with an address ADR. Thus, a word line WL is selected and nonselected (activated/deactivated), a bit line BL is selected and nonselected (activated/deactivated), a word line WL and a bit line BL are supplied with a voltage, and the like. The read/write circuit145writes data to the memory cell array100A (write operation) and reads data from the memory cell array100A (read operation). During data writing, the read/write circuit145sends a signal (voltage or current) corresponding to the write data to the memory cell array100A via the column control circuit120. During data reading, the read/write circuit145receives a signal (voltage or current) corresponding to read data from the memory cell array100A via the column control circuit120. Note that a circuit for writing data and a circuit for reading data may be provided in the DRAM1A independently of each other. The I/O circuit (input/output circuit)170receives a command CMD, an address ADR, data (e.g., write data) DT, a plurality of control signals CNT and the like from an external device (e.g., a processor)2. The I/O circuit170sends the control signals CNT and data (e.g., read data) DT to a device outside the DRAM1A. In response to the command CMD and control signals CNT, the control circuit190controls other circuits110,120,145and170according to an operation to be performed by the DRAM1A. When the memory device1A is a DRAM, the control circuit190controls and performs refresh of data in the memory cell array100A (refresh operation) in addition to writing and reading of data. For example, the control circuit190controls the circuits110,120,145and170with timing synchronized with a clock signal CLK. As a result, data is written and read with timing synchronized with the clock signal CLK. The clock signal CLK is generated in the interior of the DRAM1A or supplied from the external device2. Note that the DRAM1A may further include a refresh control circuit, a clock generation circuit, an internal voltage generation circuit and the like. <Memory Cell Array> FIG.18is an equivalent circuit diagram illustrating an exemplary configuration of the memory cell array of the memory device of the second embodiment. As described above, the memory cell array100A includes a plurality of memory cells MCd. The memory cells MCd are arranged in matrix in the X-Y plane of the memory cell array100A. One terminal (one end) of each memory cell MCd is connected to its corresponding bit line BL. The other terminal (the other end) of the memory cell MCd is connected to a plate line (plate electrode) PL. The control terminal of the memory cell MCd is connected to its corresponding word line WL. The memory cells MCd arranged in the X direction are connected to a common word line WL. The memory cells MCd arranged in the Y direction are connected to a common bit line BL. The memory cells MCd for each control unit are connected to a common plate line PL. As described above, each of the memory cells MCd includes a cell capacitor80and a cell transistor81. The cell capacitor80holds a charge amount associated with data of one bit or more. The cell capacitor80functions as a memory element of the memory cell MCd. The cell transistor81switches a connection between a memory cell MCd and its corresponding bit line BL. The cell transistor81functions as a selection element of the memory cell MCd. One terminal (one source/drain) of the cell transistor81is connected to its corresponding bit line BL as a terminal of the memory cell MCd. The other terminal (the other source/drain) of the cell transistor81is connected to one terminal (one end) of the cell capacitor80via a node ND. The other terminal (the other end) of the cell capacitor80is connected to the plate line PL as a terminal of the memory cell MCd. The gate of the cell transistor81is connected to its corresponding word line WL. The gate of the cell transistor81serves as a control terminal of the memory cell MCd. FIG.19is a bird's eye view showing an exemplary configuration of a memory cell in the DRAM of the second embodiment. As shown inFIG.19, in the second embodiment, the cell transistor81overlaps the cell capacitor80in the Z direction. The Z direction is perpendicular to the X-Y plane. The Z direction intersects the X and Y directions. The cell capacitor80includes at least two electrodes801and803and an insulating layer802. The insulating layer (also referred to as a capacitor insulating layer hereinafter)802is provided between the two electrodes (also referred to as capacitor electrodes hereinafter)801and803. The capacitor electrode801is electrically connected to the plate line PL. The capacitor electrode803is connected to the source/drain of the cell transistor81. The capacitor insulating layer802and the capacitor electrode801are provided between the capacitor electrode803and the plate line PL. Thus, the capacitor electrode803is not in direct contact with the plate line PL. The cell transistor81includes at least a semiconductor layer810, a gate insulating layer811and a gate electrode812. The semiconductor layer (also referred to as a channel layer or a body portion hereinafter)810has a columnar structure extending in the Z direction. The gate electrode812is opposed to the side surface of the columnar semiconductor layer810with the gate insulating layer811therebetween. The gate insulating layer811is provided between the side of the semiconductor layer810and the gate electrode812. The channel region of the cell transistor81is provided in the semiconductor layer810. The two source/drain regions of the cell transistor81are provided in the semiconductor layer810. Hereinafter, the columnar semiconductor layer810will also be referred to as a semiconductor pillar (or channel pillar). In the second embodiment, the cell transistor81is a vertical transistor. One of the two source/drain regions is provided at one end (on the top) of the semiconductor layer810in the Z direction, and the other is provided at the other end (on the bottom) of the semiconductor layer810in the Z direction. The two source/drain regions of the vertical transistor81are arranged in the Z direction. One of the two source/drain regions is provided above the other in the Z direction. The source/drain region on the upper side of the cell transistor81is connected to the bit line BL. The source/drain region on the lower side of the cell transistor81is connected to the capacitor electrode803. Thus, the current path of the vertical cell transistor81extends along the Z direction. In the cell transistor81, current flows in the Z direction. In the second embodiment, the cell transistor81has a gate all around (CAA) structure. Regarding the cell transistor81with the GAA structure, the gate electrode812overlaps the entire side of the channel region in the semiconductor layer810. The gate electrode812annularly covers the side (plane along the Z direction) of the channel region through the gate insulating layer811. Thus, the cell transistor81has high gate electrostatic controllability. In the second embodiment, the cell capacitor80is provided in the alumina hole of the alumina layer61. <Exemplary Configuration> FIG.20is a sectional view showing an exemplary configuration of a DRAM of the second embodiment. InFIG.20, a section (Y-Z plane) of a DRAM1A along the Y direction is shown. As shown inFIG.20, the DRAM1A includes a plurality of chips400A and410which are bonded together, as in the magnetic memory of the first embodiment. The memory cell array chips400A are electrically connected to the memory control circuit CCA by pads73provided in the memory cell array chip400A and pads38provided in the memory control circuit chip410. Like in the first embodiment, the memory control circuit CCA is provided on the silicon substrate41. The memory cell array chips400A are provided above the memory control circuit chip410A in the Z direction. The memory cell array chip400A includes an alumina layer61. The alumina layer61overlaps a substrate (memory control chip) in the Z direction. The cell capacitor80is provided in the alumina layer61. The cell transistor81is provided below the alumina layer61in the Z direction. The cell transistor81is provided between the cell capacitor80and the memory control circuit CCA in the Z direction. The alumina layer61has a plurality of alumina holes911and911A. In the second embodiment, the alumina holes911and911A each have a quadrangular sectional structure when viewed from the X direction (or Y direction). In the second embodiment, however, the alumina holes911and911A may have a constricted structure as in the first embodiment. Like in the foregoing example of the first embodiment (seeFIG.6, for example), the memory cells MCd are arranged in the X-Y plane of the memory cell array100A by the layout (pattern) of a hexagonal lattice. With respect to the layout of seven memory cells MCd included within one unit of the hexagonal lattice, six of the seven memory cells MCd are located at their respective apexes of the hexagon and the remaining one memory cell MCd is located at the center of the hexagon. The cell capacitors80(alumina holes911) are arranged in the alumina layer (alumina plate)61in a hexagonal lattice. In a plurality of memory cells arranged in a hexagonal lattice, a memory cell MCd connected to one of adjacent two word lines WL in the Y direction is provided in a direction oblique to the Y direction (and X direction) with respect to a memory cell MCd connected to the other word line WL. A memory cell connected to a word line adjacent to one end of a word line in the Y direction is connected to the same bit line as a memory cell connected to a word line adjacent to the other end of the word line in the Y direction, and thus these memory cells are aligned on a straight line in the Y direction. The cell capacitor80is provided in an alumina layer61formed by anodic oxidation. The cell capacitor80includes two capacitor electrodes801and803, a capacitor insulating layer802and a storage node electrode (embedded electrode)804. The storage node electrode804is shaped like a column (or an elliptic cylinder). The storage node electrode804has a circular (or elliptical) planar shape when viewed from the Z direction. The capacitor electrode801is opposed to the side and the bottom of the storage node electrode804. The capacitor electrode801has a cylindrical (cup-shaped) structure. For example, the capacitor electrode801includes a cylindrical portion extending in the Z direction and a bottom portion having a circular (or elliptical) planar shape to which the cylindrical portion is connected. The capacitor electrode803is opposed to the side part and the bottom of the capacitor electrode801with the capacitor insulating layer802therebetween. The capacitor electrode803has a cylindrical (cup-shaped) structure. For example, the capacitor electrode803includes a cylindrical portion extending in the Z direction and a bottom portion having a circular (or elliptical) planar shape to which the cylindrical portion is connected. Note that the capacitor electrode803and the storage node electrode804may be a single structure made of one material. The capacitor insulating layer802is provided between the capacitor electrodes801and803. The capacitor insulating layer802is opposed to the side and the bottom of the capacitor electrode801. The capacitor insulating layer802has a cylindrical structure. For example, the capacitor insulating layer802includes a cylindrical portion extending in the Z direction and a bottom portion having a circular (or elliptical) planar shape to which the cylindrical portion is connected. The capacitor electrode801and capacitor insulating layer802are provided between the capacitor electrode803and plate electrode89(plate line PL). The capacitor electrode803is separated from the plate electrode89. The capacitor electrode801is directly connected to the plate electrode89. The capacitor electrodes801and803include a conductive compound layer (e.g., a titanium nitride layer). The capacitor insulating layer802includes a single-layered or multi-layered high dielectric layer (e.g., a zirconium oxide layer or an aluminum oxide layer). The storage node electrode804includes a metal layer (e.g., a tungsten layer) or a conductive semiconductor layer (e.g., a polysilicon layer). The plate electrode89includes a metal layer (e.g., a tungsten layer). Note that the materials of the members801,802,803,804and89are not limited to those described above. A plurality of cell transistors (vertical field effect transistors having a GAA structure)81are arranged in the X-Y plane in a hexagonal lattice. In each of the memory cells MC, the cell transistor81overlaps the capacitor80in the Z direction. Each cell transistor81includes a semiconductor layer810, a gate insulating layer811and a gate electrode812. The source/drain regions and channel region of the cell transistor81are provided in the semiconductor layer810. The semiconductor layer810has a columnar structure. The planar shape of the semiconductor layer810is circular. The semiconductor layer810extends in the Z direction. The semiconductor layer810includes at least one selected from a silicon layer, a germanium layer, a compound semiconductor layer and an oxide semiconductor layer. For example, when an oxide semiconductor layer such as InGaZnO is used in the semiconductor layer810, the cell transistor81is improved in its off-leak characteristics. The gate insulating layer811has a cylindrical structure. The gate insulating layer811covers the side of the semiconductor layer810. The cylindrical gate insulating layer811is concentric with the cylindrical semiconductor layer810. The gate insulating layer811is provided on the side of the semiconductor layer810(surface of the semiconductor layer810along the Z direction). The gate insulating layer811is provided between the semiconductor layer810and the gate electrode812. The gate insulating layer811includes, for example, at least one of a silicon oxide layer and a high dielectric insulating film. The gate insulating layer811may have a single layer structure or a stacked layer structure. The gate electrode812has a cylindrical structure. The semiconductor layer810penetrates the gate electrode812. The gate electrode812is opposed to the side of the semiconductor layer810with the gate insulating layer811therebetween. Part of the semiconductor layer810opposed to the gate electrode812serves as an effective channel region of the cell transistor81. The gate electrode812is connected to, for example, the conductive layer (referred to as a gate interconnect hereinafter)819. For example, the gate electrode812is continuous with the conductive layer819. The gate electrodes812of the cell transistors81adjacent to each other in the X direction (or an oblique direction parallel to the X-Y plane and intersecting the X and Y directions) are connected via the gate interconnect819. The gate electrode812and gate interconnect819function as word lines WL. The gate electrode812and gate interconnect819are, for example, a metal layer such as a tungsten layer, a conductive semiconductor layer, or a conductive compound layer. The bit lines BL are provided to overlap the cell transistors81in the Z direction. For example, each bit line BL is provided between its corresponding cell transistor81and the silicon substrate41in the Z direction. In the memory cell array area A1d, the alumina holes911are regularly arranged at predetermined pitches (spacings) Dp1. The alumina holes911are laid out in the X-Y plane in a hexagonal lattice. At one end of the memory cell array chip400A (alumina layer61) in the X (or Y) direction, the alignment mark area A2dis provided adjacent to the memory cell array area A1din the X (or Y) direction. Like in the first embodiment, in the second embodiment, a mark portion990dfor an alignment mark AMd is provided in the alignment mark area A2d. The mark portion990dincludes members801,802,803and804in one or more alumina holes in the alignment mark area A2d. In the alignment mark area A2d, a plurality of alumina holes911A (mark members990d) are regularly arranged at predetermined pitches (spacings) Dp2like the alumina holes911(cell capacitors80). The alumina holes911A are laid out in the X-Y plane in a hexagonal lattice. The alignment mark area A2dis provided in the dicing area of a wafer that has not been chipped in the memory cell array area A1d. In the memory cell array chip400A, an intermediate area (irregular alignment area) A3dis provided between the memory cell array area A1dand the alignment mark area A2d. The intermediate area A3dincludes a plurality of alumina holes911X. The alumina holes911X are arranged at random pitches in an irregular pattern. Note that the DRAM1A of the second embodiment performs a write sequence and a read sequence by known operation. The operation of the DRAM1A will not be described. (2b) Manufacturing Method The memory device (e.g., DRAM) of the second embodiment will be described with reference toFIGS.21through25. None ofFIGS.21through25shows holes to be formed in the intermediate area A3dor members in the holes. However, the members in the intermediate area A3dare formed substantially in the same manner as the members in the areas Aid and A2d, except for their shapes and dimensions. FIG.21is a schematic sectional view showing one step of the method for manufacturing the DRAM of the second embodiment. As shown inFIG.21, anodic oxidation is performed for an aluminum layer on which a reaction starting point (recess) is formed, by substantially the same process as that ofFIGS.8through10described above. An alumina layer61is thus formed on the silicon substrate40(wafer90). In the memory cell array area A1dand alignment mark area A2d, a plurality of alumina holes911and911A are formed in the alumina layer61at predetermined pitches Dp1and Dp2. In the second embodiment, anodic oxidation voltage V1is maintained without being modulated. Thus, the sectional shape of the alumina hole911A viewed from the X direction (or Y direction) is substantially quadrangular. A conductive layer (e.g., a titanium nitride layer)801A is formed in the alumina holes911and911A and on the upper surface of the alumina layer61by CVD or ALD. The conductive layer801A is a layer for forming the capacitor electrode801. The thickness of the conductive layer801A is controlled such that the alumina hole911A is not blocked by the conductive layer801A. The thickness of the conductive layer801A is about several nanometers. FIG.22is a schematic sectional view showing one step of the method for manufacturing the DRAM of the second embodiment. As shown inFIG.22, a conductive layer covering the upper surface of the alumina layer61is removed by wet etching or dry etching. Accordingly, the conductive layer (capacitor electrode)801is separated for each of the alumina holes911and911A. A high dielectric insulating layer (e.g., a zirconia oxide layer)802A is formed on the upper surface of the alumina layer61and on the conductive layer801by CVD or ALD. A conductive layer (e.g., a titanium nitride layer)803A is formed on the insulating layer802A by CVD or ALD. For example, the thickness of the insulating layer802A and that of the conductive layer803A are controlled such that the alumina holes911and911A are not blocked by the insulating layer802A and conductive layer803A. The thickness of each of the conductive layer803A and the insulating layer802A is about several nanometers. A conductive layer804A is formed on the conductive layer803A in the alumina holes911and911A. The alumina holes911and911A are embedded by the conductive layer804A. The conductive layer804A is a silicon layer, a silicon germanium layer or the like. FIG.23is a schematic sectional view showing one step of the method for manufacturing the DRAM of the second embodiment. As shown inFIG.23, the conductive layer on the upper surface of the alumina layer61is etched back by wet etching or dry etching. Accordingly, the conductive layers803and804are separated for each of the alumina holes911and911A. A cell capacitor80is formed in the alumina hole911. A mark portion990dis formed in the alumina hole911A at substantially the same time when the cell capacitor80is formed. In addition, like in the first embodiment, a conductive layer55may be formed on the upper portion (opening side of the alumina hole911A) of the alumina hole911A in order to clarify the boundary between adjacent areas A1and A3. As described above, in the second embodiment, the alumina holes911and911A are arranged in the memory cell array area Aid and alignment mark area A2dat predetermined pitches by the steps described above. The cell capacitor80and the alignment mark AMd are laid out in a hexagonal lattice in the memory cell array area A1dand the alignment mark area A2d. FIG.24is a schematic sectional view showing one step of the method for manufacturing the DRAM of the second embodiment. As shown inFIG.24, a plurality of cell transistors81are formed above the alumina layer61in the Z direction by the known technique. The cell transistors81are formed above their respective capacitors80in the Z direction. After that, an interconnect (e.g., a bit line)85and bonding pads73are formed. Lithography (e.g., photolithography) is performed for patterning of each of the components81,85and73of the memory cell array100A. In the second embodiment, a mask for the lithography is aligned with the substrate40(wafer9) using the alignment mark AMd formed by anodic oxidation. FIG.25is a schematic sectional view showing one step of the method for manufacturing the DRAM of the second embodiment. As shown inFIG.25, a second silicon substrate40is bonded to a first silicon substrate41such that the bonding pad73of the first silicon substrate40is opposed to the bonding pad38of the second silicon substrate41by substantially the same step as that ofFIG.13described above. When wafers are bonded to each other, the first and second silicon substrates40and41are aligned with each other using the alignment mark991of the second silicon substrate41and the alignment mark Amd (990d) of the first silicon substrate40. After that, silicon is removed, by a process such as backgrinding, from a second surface (surface opposed to the bonding surface) of the substrate (wafer) on which a memory cell array is formed, by substantially the same step as those shown inFIGS.14and15described above. An unreacted aluminum layer is also removed. Accordingly, the exposed alumina barrier layer is removed. Thus, the capacitor electrode801in the alumina hole911is exposed. As shown inFIG.20, an interconnect (plate electrode)89is formed on the capacitor electrode801and the alumina layer61. An interlayer insulating layer79is formed on the interconnect89and alumina layer61. A pad78is formed in the interlayer insulating layer79. When the interconnect89and the pad78are formed, the alignment mark AMd of the memory cell array chip400A may be used to align a wafer and a mask for lithographic are aligned with each other. Thus, the DRAM1A of the second embodiment is formed with the memory control circuit chip (wafer)41as a support substrate. After that, the DRAM1A of the second embodiment is chipped by dicing the wafer9. At this time, part or all of the alignment marks990d(AMd) in the dicing area A2dmay be cut or removed from the chip of the DRAM1A. The DRAM of the second embodiment described above is thus completed. The memory device (and the method for manufacturing the memory device) of the second embodiment can bring about substantially the same advantages as those of the first embodiment. (3) Modification A modification to the memory devices of the above embodiments will be described with reference toFIGS.26through28. FIG.26is a schematic top view illustrating a modification to the memory devices of the embodiments. As shown inFIG.26, in a memory device (e.g., a domain wall memory) of the modification, a plurality of alumina holes910Z may be arranged regularly at predetermined pitches Dp3in an area A3Z between the memory cell array area A1and the alignment mark area A2. For example, in the area A3Z, the alumina holes910Z are arranged in a layout different from that of the alumina holes910and910A in the areas A1and A2. In this case, the pitches Dp3of the alumina holes910Z may differ from the pitches Dp1and Dp2of the alumina holes910and910A in the areas A1and A2. The dimensions Dz of the alumina holes910Z in a direction parallel to the surface of the substrate may differ from the dimensions Da and Db of the alumina holes910and910A in the areas A1and A2. In the area A2, alumina holes910C (and members51C and62C in the holes910C) other than the alumina holes910A used for the alignment mark AM may be arranged at predetermined pitches (e.g., pitches Dp2). In this case, the alignment mark AM can be distinguished from the members51C and62C in the alumina holes910C according to the presence or absence of the conductive layer55. FIG.27is a schematic sectional view illustrating a modification to the memory devices of the embodiments. As shown inFIG.27, a layer for clarifying a boundary between adjacent areas A2and A3need not be provided in the alignment mark area A2. In this case, a mark portion990Z has substantially the same configuration as that of members51and62in each of the alumina holes910in the memory cell array area A1. FIG.28is a schematic sectional view illustrating a modification to the memory device manufacturing methods of the embodiments. Two silicon substrates40and41may be aligned with each other using at least one of an alignment mark AMX formed using a mark AM and an alignment mark991X formed using a mark991, as may be the substrates40and41and various masks. For example, the mark AMX aligned with the mark AM is located at a position (level) different from that of the mark AM in the Z direction. The mark AMX is formed in the insulating layer68covering the upper surface (bonding surface) of the alumina layer61, using the mark AM for lithography alignment during the formation of components (e.g., interconnects) on the wafer40. For example, the mark AMX is used to perform lithography alignment for formation of pads and interconnects on the wafer40or alignment of the wafers40and41. FIG.28shows an example in which the mark AMX is provided in the vicinity of a region vertically aligned with the mark AM in the Z direction. If, however, the mark AMX is a pattern formed by a manufacturing process using the mark AM for lithography alignment, the mark AMX need not be provided in the vicinity of the mark AM. The mark AMX may be provided to overlap the alignment mark AM in the Z direction. In addition, the mark AMX may be formed on the side opposed to the bonding surface of the memory cell array chip400(silicon wafer40). For example, the mark991X aligned with the mark991is located at a position (level) different from that of the mark991in the Z direction. The mark991X is formed in the insulating layer39covering the upper surface (bonding surface) of the wafer41, using the mark991for lithography alignment during the formation of components (e.g., interconnects) on the wafer41. For example, the mark991X is used to perform lithography alignment for formation of pads and interconnects on the wafer41or alignment of the wafers40and41. FIG.28shows an example in which the mark991X is provided in the vicinity of a region vertically aligned with the mark991in the Z direction. If, however, the mark991X is a pattern formed by a manufacturing process using the mark991for lithography alignment, the mark991X need not be provided in the vicinity of the mark AM. The mark991X may be provided to overlap the alignment mark991 Note that any one of the reading element10, switching element20and write interconnect WRL may be provided on the side opposite to the bonding surface of the memory cell array chip400(silicon wafer40). In this case, the reading element10, switching element20and write interconnect WRL are formed after the wafers40and41are bonded to each other. The modifications shown inFIGS.26through28may be applied to the DRAM of the second embodiment. The modifications shown inFIGS.26through28can bring about substantially the same advantages as those of the above-described embodiments. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 97,156 |
11942467 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the deviation normally found in the respective testing measurements. Also, as used herein, the terms “about,” “substantial” or “substantially” generally mean within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the terms “about,” “substantial” or “substantially” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “about,” “substantial” or “substantially.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “standard cell” or “cell” used throughout the present disclosure refers to a group of circuit patterns in a design layout to implement specific functionalities of a circuit. A standard cell is comprised of one or more layers, and each layer includes various patterns expressed as unions of polygons. A design layout may be initially constructed by a combination of identical or different standard cells. The cells are interconnected using a routing structure. The geometries of the patterns in the cells may be adjusted at different stages of layout design in order to compensate for design and process effects. A standard cell may cover circuits corresponding to a portion or an entirety of a die to be manufactured. The standard cells may be accessible from cell libraries provided by semiconductor manufacturers or designers. In some embodiments, the standard cells are included in a standard cell library, which may be stored in a non-transitory computer-readable storage medium and accessed by a processor in various circuit design stages. Embodiments of the present disclosure discuss semiconductor structures including both one or more MIM capacitors and one or more MOM capacitors and manufacturing methods of the semiconductor structures for the combined capacitor structure to serve as a decoupling capacitor for stabilizing the power signal and reducing noise. With the arrangement of a dielectric layer interposed between the MOM capacitor(s) and the MIM capacitor, the overall capacitance density can be increased due to the parasitic capacitance generated, which is advantageous to increasing the operation voltage. In addition, the combination of the MIM capacitor and the MOM capacitor can provide an increased capacitance value without significantly increasing the complexity as well as costs of the manufacturing process of the semiconductor structure. FIG.1is a cross-sectional view of a semiconductor structure1in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor structure1can be included in an electronic device which is not limited by the present disclosure. Referring toFIG.1, in some embodiments, the semiconductor structure1includes one or more MOM capacitors (e.g., MOM capacitors11-14), one or more MIM capacitors (e.g., a MIM capacitor20), dielectric layers30and40, an inter-level dielectric (ILD)50, conductive interconnections60aand60b, and a metal layer70. The MOM capacitors11-14may be disposed over a substrate (not shown inFIG.1). In some embodiments, the substrate (also referred to as a die substrate) may include a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In other embodiments, the substrate may include semiconductor materials that include group group IV, and/or group V elements. For example, the substrate may include germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), or the like. The substrate may be a p-type semiconductor substrate (acceptor type) or an n-type semiconductor substrate (donor type). In some embodiments a periphery region and a cell region can be defined over the substrate. Various electrical components may be formed over the substrate. In some embodiments, active devices, i.e., transistors can be formed over the substrate in the periphery region, while the capacitors (e.g., the MOM capacitors11-14and the MIM capacitor20) can be formed over the substrate in the cell region, as illustrated inFIG.1. Referring toFIG.1, the MOM capacitors11-14are stacked over the substrate. For example, the MOM capacitor11(also referred to as “the metal-dielectric-metal layer”) is stacked with the MOM capacitor12(also referred to as “the metal-dielectric-metal layer”). In some embodiments, the MOM capacitor14(also referred to as “the metal-dielectric-metal layer”) may be the bottommost MOM capacitor within the stack of the MOM capacitors11-14, and the MOM capacitor11may be the topmost MOM capacitor within the stack of the MOM capacitors11-14. In some embodiments, the MOM capacitor11is interposed between the dielectric layer30and the MOM capacitor12. Referring toFIG.1, the MOM capacitor11may include a plurality of fingers11a(also referred to as “conductive fingers”), a plurality of fingers11b(also referred to as “conductive fingers”), and a dielectric material11c. The fingers11aand the fingers11bmay be arranged in parallel and staggeredly. The dielectric material11cmay be between the fingers11aand the fingers11b. The fingers11aand the fingers11bmay respectively electrically connect to two electrodes of the MOM capacitor11. In some embodiments, the MOM capacitor12includes a plurality of fingers12a, a plurality of fingers12b, and a dielectric material12c. The fingers12aand the fingers12bmay be arranged in parallel and staggeredly. The dielectric material12cmay be between the fingers12aand the fingers12b. The fingers11a,11b,12aand12bmay be in parallel. In some embodiments, the MOM capacitor13(also referred to as “the metal-dielectric-metal layer”) includes a plurality of fingers13a, a plurality of fingers13b, and a dielectric material13c. The fingers13aand the fingers13bmay be arranged in parallel and staggeredly. The dielectric material13cmay be between the fingers13aand the fingers13b. The fingers11a,11b,12a,12b,13a, and13bmay be in parallel. In some embodiments, the MOM capacitor14includes a plurality of fingers14a, a plurality of fingers14b, and a dielectric material14c. The fingers14aand the fingers14bmay be arranged in parallel and staggeredly. The dielectric material14cmay be between the fingers14aand the fingers14b. The fingers11a,11b,12a,12b,13a,13b,14a, and14bmay be in parallel. The fingers11a,11b,12a,12b,13a,13b,14a, and14bof the MOM capacitors11-14may include various conductive materials, such as copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), an alloy thereof, a combination therefore, or the like, but the present disclosure is not limited thereto. In some embodiments, at least one of the fingers may include a barrier layer (not shown inFIG.1) adhering and spacing between the conductive material of the finger and the sidewall defined by the dielectric material. In some embodiments, the barrier layer may include Ta, TaN, TiN, a combination thereof, or the like. In some embodiments, the conductive material of the fingers may include Cu, W, Co, Al, an alloy thereof, a combination thereof, or the like. The dielectric materials11c,12c,13c, and14cmay include various insulating materials or dielectric materials, such as silicon oxide, silicon oxynitride, silicon oxycarbide, a combination thereof, or the like, but the present disclosure is not limited thereto. In some embodiments, the dielectric materials11c,12c,13c, and14cmay include one or more low-k dielectric materials having k values lower than or equal to about 3.9. In some embodiments, the k value of the low-k dielectric material may be lower than or equal to about 3. In some embodiments, the k value of the low-k dielectric material may range from about 2.5 to about 3. In some embodiments, the cross-section of each of the fingers11a,11b,12a,12b,13a,13b,14a, and14bmay have a rectangular shape or a trapezoid shape tapering from a top surface toward a bottom surface. In some embodiments, a cross-sectional width of the top surface of each of the fingers ranges from about 50 nm to about 200 nm. In some embodiments, a cross-sectional width of the bottom surface of each of the fingers ranges from about 30 nm to about 200 nm. In some embodiments, a distance between the top surfaces of adjacent fingers ranges from about 70 nm to about 350 nm. In some embodiments, a distance between the bottom surfaces of adjacent fingers ranges from about 70 nm to about 400 nm. Referring toFIG.1, the semiconductor structure1may further include an ILD layer81, etch stop layers82, and liners83. In some embodiments, the MOM capacitors11-14are over the ILD layer81, and the etch stop layers82are over the ILD layer81and each of the dielectric materials12c-14c. Each of the liner layers83may be conformally disposed over each of the etch stop layers82. The ILD layer81may include, but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCBN, or any combinations thereof. The etch stop layer82may include SiC, SiNx, or the like. The liner83may include tetraethyl orthosilicate (TEOS) or the like. The MIM capacitor20may be over the MOM capacitor11. In some embodiments, the MIM capacitor20may include conductive layers20A,20B, and a dielectric layer20C. The conductive layers20A and20B may serve as or electrically connect to electrodes of the MIM capacitor20. In some embodiments, the conductive layer20B is over the dielectric layer30, the conductive layer20A is over the conductive layer20B, and the dielectric layer20C is between the conductive layer20A and the conductive layer20B. In some embodiments, the conductive layer20B includes sub-layers21,22and23. In some embodiments, the sub-layer23is proximal to the dielectric layer30, the sub-layer21is distal from the dielectric layer30, and the sub-layer22is between the sub-layer21and the sub-layer23. In some embodiments, a material of the sub-layer22may be different from materials of the sub-layers21and23. The sub-layer23may taper toward the sub-layer22. The sub-layer22may taper toward the sub-layer21. The sub-layer21may taper toward the dielectric layer20C. The dielectric layer20C may include a stepped structure. In some embodiments, the dielectric layer20C includes a portion20C1proximal to the conductive layer20A and a portion20C2proximal to the conductive layer20B, and a width of the portion20C1is less than a width of the portion20C2. In some embodiments, a lateral surface of the portion20C1, a portion of a top surface of the portion20C2, and a lateral surface of the portion20C2form a stepped profile of the dielectric layer20C. The portion20C2may taper toward the portion20C1, and the portion20C1may taper toward the conductive layer20A. A lateral surface of the conductive layer20B and a lateral surface of the portion20C2of the dielectric layer20C form a continuous surface. In some embodiments, a thickness of the conductive layer20B is about 2000 Å. In some embodiments, the conductive layer20A is over the dielectric layer20C. In some embodiments, the conductive layer20A is over the portion20C1of the dielectric layer20C. The conductive layer20A may be spaced apart from the portion20C2of the dielectric layer20C by the portion20C1of the dielectric layer20C. The conductive layer20A may taper away from the dielectric layer20C. In some embodiments, a thickness of the conductive layer20A is about 800 Å. In some embodiments, a thickness of the dielectric layer20C ranges from about 300 Å to about 700 Å. The conductive layer20A and the sub-layers21-23of the conductive layer20B may include various conductive materials, such as Cu, W, Co, Al, Ta, TaN, Ti, TiN, an alloy thereof, a combination therefore, or the like, but the present disclosure is not limited thereto. In some embodiments, the conductive layers20A and the sub-layer22include AlCu, and the sub-layers21and23include TaN. The dielectric layer20C may include a high-k dielectric material. In some embodiments, the dielectric layer20C may include aluminum oxide (Al2O3), zirconium oxide (ZrO2), silicon nitride (Si3N4), tantalum nitride (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), hafnium oxide (HfO2), a multi-layer structure of the combination thereof, or the like. In some embodiments, the semiconductor structure1may further include a cap layer84and a mask layer85. The mask layer85is between the MIM capacitor20and the cap layer84. The mask layer85may be formed directly on the conductive layer20A of the MIM capacitor20. Lateral surfaces of the mask layer85may substantially align to lateral surfaces of the conductive layer20A of the MIM capacitor20. The mask layer85may taper toward the cap layer84. The mask layer85may include nitride or oxynitride, such as silicon nitride (SiNx), silicon oxynitride (SiON), or the like. In some embodiments, a thickness of the mask layer85ranges from about 200 Å to about 400 Å. The cap layer84may be formed over the conductive layer20A of the MIM capacitor20. In some embodiments, the cap layer84may contact the dielectric layer20C. In some embodiments, the cap layer84may contact the lateral surfaces of the conductive layer20A. In some embodiments, the cap layer84has a greater mechanical strength than that of the stack of the capacitors, so as to alleviate the affection of external force applied on the stack of the capacitors. The cap layer84may include nitride, oxide, or a combination thereof, such as plasma enhanced deposited silicon nitride, silicon oxide, or the like. Referring toFIG.1, the dielectric layer30is between the MIM capacitor20and the MOM capacitor11. In some embodiments, the dielectric layer30is over the MOM capacitor11(or the metal-dielectric-metal layer). The dielectric layer30may include a stepped structure. In some embodiments, the dielectric layer30includes a portion301proximal to the conductive layer20B and a portion302proximal to the MOM capacitor11, and a width of the portion301is less than a width of the portion302. The portion301may taper toward the conductive layer20B. A distance between a top surface302aof the portion302and a top surface301aof the portion301is about 360 Å. In some embodiments, a thickness of the dielectric layer30ranges from about 900 Å to about 4000 Å. In some embodiments, a thickness of the dielectric layer30ranges from about 900 Å to about 1900 Å. In some embodiments, the dielectric layer30includes silicon carbide (SiC), silicon nitride (SiNx), or a combination thereof. The dielectric layer40(also referred to as “the passivation layer”) may be between the dielectric layer30and the MOM capacitor11. The dielectric layer40may include un-doped silicate glass (USG), oxide, such as plasma enhanced deposited silicon oxide, or the like. The metal layer70(also referred to as “the patterned metal layer”) may be between the dielectric layer30and the MOM capacitor11(or the metal-dielectric-metal layer). In some embodiments, the metal layer70is within the dielectric layer40. In some embodiments, the metal layer70may include a plurality of metal lines in parallel to the fingers11aand11bof the MOM capacitor11. In some embodiments, the metal layer70may include dummy metal patterns or layers. In some other embodiments, the metal layer70may be electrically connected to the MOM capacitors11-14and/or the MIM capacitor20. The ILD50(also referred to as “the passivation layer”) is above the cap layer84. The ILD50may cover the MIM capacitor20, the dielectric layer30, and the cap layer85. The ILD50may include un-doped silicate glass (USG), plasma enhanced deposited oxide (PEOX), or the like. The conductive interconnections60aand60b(also referred to as “the conductive vias”) may be electrically connected to the MIM capacitor20. In some embodiments, the conductive interconnections60apenetrates through the ILD50, the cap layer84, and the mask layer85to electrically connect to the conductive layer20A (or the electrode) of the MIM capacitor20. In some embodiments, the conductive interconnections60bpenetrates through the ILD50, the cap layer84, and the portion20C2of the dielectric layer20C to electrically connect to the conductive layer20B (or the electrode) of the MIM capacitor20. According to some embodiments of the present disclosure, with the arrangement of a dielectric layer interposed between the MOM capacitor(s) and the MIM capacitor, the overall capacitance density can be increased due to the parasitic capacitance generated, which is advantageous to increasing the operation voltage, for example, up to about 6V to about 10 V or higher. Moreover, while the formation of MOM capacitors can be integrated into the current processes for metal line layers (e.g., the back-end-of-line (BEOL) processes), the MOM capacitors normally exhibit relatively low capacitance values; on the other hand, a MIM capacitor may have a relatively large capacitance value, yet the formation thereof requires additional manufacturing processes between the current processes for metal line layers (e.g., between the metal line M5process and the metal line M6process). According to some embodiments of the present disclosure, the combination of the MIM capacitor and the MOM capacitor can provide an increased capacitance value without significantly increasing the complexity as well as costs of the manufacturing process of the semiconductor structure. For example, an in-die or in-chip decoupling capacitor having a capacitance density value of greater than about 2 nF/mm2for high voltage devices (e.g., about 7V or 8V) can be obtained. The numbers of the MOM capacitors, the MIM capacitor, and the fingers in each of the MOM capacitors shown inFIG.1are for illustrative purposes only. Numbers and configurations of the MOM capacitors, the MIM capacitor, and the fingers in each of the MOM capacitors other than those shown inFIG.1are within the contemplated scope of the present disclosure. FIG.1Ais a top view of a portion of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.1Aas an example, but the present disclosure is not limited thereto. Referring toFIG.1A, the fingers11aand the fingers11bmay be arranged in parallel and staggeredly. In some embodiments, referring toFIGS.1and1A, the fingers12aand the fingers12bof the MOM capacitor12may be arranged in parallel and staggeredly in a fashion similar to that of the fingers11aand11bof the MOM capacitor11. In some embodiments, referring toFIGS.1and1A, the fingers11aand the fingers12amay be arranged in parallel. In some embodiments, the MOM capacitor11and the MIM capacitor20overlap from a top view perspective. In some embodiments, the conductive layer20A of the MIM capacitor20overlaps with the MOM capacitor11(or the metal-dielectric-metal layer) from a top view perspective. In some embodiments, a projection of the MOM capacitor11is within the conductive layer20A of the MIM capacitor20. FIG.1Bis a top view of a portion of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.1Bas an example, but the present disclosure is not limited thereto. In some embodiments, a projection of the MIM capacitor20is within the MOM capacitor11. In some embodiments, projections of a plurality of the MIM capacitors20are within the MOM capacitor11. In some embodiments, one or more MIM capacitors20overlap with the MOM capacitor11(or the metal-dielectric-metal layer) from a top view perspective. In some embodiments, one or more projections of the conductive layers20A are within the MOM capacitor11(or the metal-dielectric-metal layer). In some embodiments, one or more projections of the conductive layers20A overlap with the MOM capacitor11(or the metal-dielectric-metal layer) from a top view perspective. FIG.1Cis a top view of a portion of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.1Cas an example, but the present disclosure is not limited thereto. In some embodiments, a plurality of the MOM capacitors11are substantially coplanar and overlap with the MIM capacitor20from a top view perspective. In some embodiments, a plurality of the MOM capacitors11are at substantially the same elevation and overlap with the MIM capacitor20from a top view perspective. In some embodiments, projections of one or more MOM capacitors11are within the MIM capacitor20. FIG.1Dis a top view of a portion of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.1Das an example, but the present disclosure is not limited thereto. In some embodiments, a plurality of the MOM capacitors11are at substantially the same elevation and overlap with the MIM capacitor20from a top view perspective. In some embodiments, the MOM capacitors11overlap a portion of the MIM capacitor20from a top view perspective. According to some embodiments of the present disclosure, an increase in an overlapping area between the MIM capacitor and the MOM capacitor can result in an increase of the parasitic capacitance, thereby increasing the overall capacitance of the stack of the capacitors. Therefore, the overall capacitance density value may be adjusted according to actual applications by simply varying the overlapping area without increasing or decreasing the numbers of capacitors or capacitor structures to be formed. Therefore, the applicable range of the frequency of the noise to be decoupled may be increased without forming more or less numbers of capacitors and/or undesirably increasing the complexity of the manufacturing process of the semiconductor structure. FIG.2Ais a diagram illustrating the electrical connection between a MOM capacitor and a MIM capacitor of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.2Aas an example, but the present disclosure is not limited thereto. In some embodiments, a cross-sectional structure of the MIM capacitor along the cross-sectional line2A-2A′ may be shown inFIG.1. Referring toFIG.2A, in some embodiments, the fingers11aare electrically connected to a voltage V1, and the fingers11bare electrically connected to a voltage V2which is different from the voltage V1. In some embodiments, the conductive layer20B is connected to the voltage V1, and the conductive layer20A is connected to the voltage V2. In some embodiments, the MIM capacitor20and the MOM capacitor11are electrically connected in parallel. In some embodiments, the MIM capacitor20and the stack of the MOM capacitors11-14may be electrically connected in parallel. In some embodiments, the voltage V1is higher than the voltage V2. In some embodiments, the voltage V1is a positive voltage, and the voltage V2is ground. In some embodiments, the capacitors that are electrically connected (e.g., the MOM capacitor11and the MIM capacitor20) may serve as an in-die decoupling capacitor for one or more circuits corresponding to a portion or an entirety of a die formed from the semiconductor structure. In some embodiments, the MIM capacitor20and the MOM capacitor11electrically connected in parallel may have a capacitance density value from about 2 nF/mm2to about 3 nF/mm2under an operation voltage from about 6 V to about 10 V. In some embodiments, the fingers12amay be electrically connected to the voltage V1, and the fingers12bmay be electrically connected to the voltage V2. In some embodiments, the fingers13amay be electrically connected to the voltage V1, and the fingers13bmay be electrically connected to the voltage V2. In some embodiments, the fingers14amay be electrically connected to the voltage V1, and the fingers14bmay be electrically connected to the voltage V2. FIG.2Bis a diagram illustrating the electrical connection between a MOM capacitor and a MIM capacitor of a semiconductor structure in accordance with some embodiments of the present disclosure. In some embodiments, the MOM capacitor11and the MIM capacitor20included in the semiconductor structure1are shown inFIG.2Aas an example, but the present disclosure is not limited thereto. In some embodiments, a cross-sectional structure of the MIM capacitor along the cross-sectional line2B-2B′ may be shown inFIG.1. In some embodiments, the MIM capacitor20is electrically connected in series with the MOM capacitor11. In some embodiments, the MIM capacitor20may be electrically connected in series with the stack of the MOM capacitors11-14. In some embodiments, the conductive layer20B is electrically connected to the fingers11bof the MOM capacitor11(or the metal-dielectric-metal layer), and the conductive layer20A is connected to a voltage V3different from the voltage V1. In some embodiments, the voltage V1is higher than the voltage V3. In some embodiments, the voltage V1is a positive voltage, and the voltage V3is ground. In some embodiments, the MIM capacitor20and the MOM capacitor11electrically connected in series may have a capacitance density value from about 1 nF/mm2to about 1.5 nF/mm2under an operation voltage from about 12 V to about 20 V. According to some embodiments of the present disclosure, the overall capacitance may be adjusted by varying the number of each type of the capacitors as well as selecting to electrically connect the MIM capacitor and the MOM capacitor in parallel or in series, so as to achieve a desired capacitance value for decoupling signals having a predetermined frequency value or range from a voltage supply. Therefore, the power signal can be stabilized, and the noise can be reduced. FIG.3is a cross-sectional view of a semiconductor structure3in accordance with some embodiments of the present disclosure. The semiconductor structure3is similar to the semiconductor structure1in many aspects, and thus descriptions of these aspects are not repeated for brevity. Referring toFIG.3, the semiconductor structure3differs from the semiconductor structure1in, for example, the configurations of the MIM capacitor20. In some embodiments, the dielectric layer30includes sub-layers310and320. In some embodiments, the sub-layer320of the dielectric layer30is on the MOM capacitor11(or the metal-dielectric-metal layer). In some embodiments, the sub-layer310of the dielectric layer30is between the sub-layer320of the dielectric layer30and the conductive layer20B. In some embodiments, the sub-layer310of the dielectric layer30is proximal to the MIM capacitor20, and the sub-layer320of the dielectric layer30is proximal to the MOM capacitor11. In some embodiments, the sub-layer310of the dielectric layer30includes an oxide layer, and the sub-layer320of the dielectric layer30includes silicon carbide, silicon nitride, or a combination thereof. In some embodiments, a thickness of the dielectric layer30ranges from about 900 Å to about 1900 Å. In some embodiments, a thickness of the sub-layer310of the dielectric layer30ranges from about 500 Å to about 2000 Å. In some embodiments, a thickness of the sub-layer310of the dielectric layer30is about 1000 Å. In some embodiments, a thickness of the sub-layer320of the dielectric layer30is about 900 Å. In some embodiments, a thickness of the sub-layer320of the dielectric layer30ranges from about 500 Å to about 2000 Å. In some embodiments, the cap layer84includes sub-layers841and842. The sub-layer841and the sub-layer842may include different materials. In some embodiments, the sub-layer841includes silicon nitride, and the sub-layer842includes silicon oxide. In some embodiments, the sub-layer841and the ILD50include different materials. FIG.4is a cross-sectional view of a semiconductor structure4in accordance with some embodiments of the present disclosure. The semiconductor structure4is similar to the semiconductor structure1in many aspects, and thus descriptions of these aspects are not repeated for brevity. Referring toFIG.4, the semiconductor structure4differs from the semiconductor structure1in, for example, the configurations of the MIM capacitor20. In some embodiments, the MIM capacitor20includes conductive layers20A,20B and20D, and the dielectric layer20C is between the conductive layers20A,20B and20D. In some embodiments, the dielectric layer20C separates the conductive layer20B (also referred to as “the bottom terminal”) from the conductive layer20D (also referred to as “the middle terminal”), and separates the conductive layer20D from the conductive layer20A (also referred to as “the top terminal”). In some embodiments, the dielectric layer20C provides a separation spacing between each of the conductive layers. The conductive layers20A,20B and20D may include conductive materials, such as TiN, Ti, Al, TaN, Ta, Cu, W, indium tin oxide (ITO), tungsten nitride (WN), rhenium trioxide (ReO3), rhenium oxide (ReO2), iridium oxide (IrO2), ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), molybdenum nitride (MoN), molybdenum (Mo), a conductive metal, the combination thereof, or the like. In some embodiments, the conductive interconnections60cand60dpenetrate through the ILD50and taper toward the metal layer70. In some embodiments, the conductive interconnection60cis electrically connected to the conductive layer20D, and the conductive interconnection60dis connected to the conductive layers20A and20B, thereby different voltages can be applied separately to the conductive layer20D and the conductive layers20A and20B, respectively. In some embodiments, the semiconductor structure4may further include a barrier layers61adhering and spacing between the sidewall of the conductive interconnection60cand the ILD50as well as the sidewall of the conductive interconnection60dand the ILD50. The barrier layer61may include Ta, TaN, TiN, a combination thereof, or the like. FIG.5is a cross-sectional view of a semiconductor structure5in accordance with some embodiments of the present disclosure. The semiconductor structure5is similar to the semiconductor structure4in many aspects, and thus descriptions of these aspects are not repeated for brevity. Referring toFIG.5, the semiconductor structure5differs from the semiconductor structure4in, for example, the MIM capacitor20may be a deep trench capacitor (DTC). In some embodiments, the dielectric layer30defines a trench, and portions of the conductive layers20A and20B and the dielectric layer20C are filled in the trench. In some embodiments, the conductive interconnection60penetrates through the ILD50, the cap layer84, and the mask layer85to electrically connect to the conductive layer20A (or the electrode). In some embodiments, the conductive layer20B (or the electrode) electrically connects to the metal layer70. In some embodiments, the dielectric layer20C may include molding compounds, pre-impregnated composite fibers (e.g., pre-preg) BPSG, silicon oxide, silicon nitride, silicon oxynitride, USG, any combination thereof, or the like. Examples of molding compounds may include, but are not limited to, an epoxy resin having fillers dispersed therein. Examples of a pre-preg may include, but are not limited to, a multi-layer structure formed by stacking or laminating a number of pre-impregnated materials/sheets. FIGS.6A to6Iare cross-sectional views of intermediate stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.6A, an etch stop layer82is formed over an ILD81, a dielectric material14cis formed over the etch stop layer82, and a patterned metal layer including the fingers14aand14bare formed in the dielectric layer14c. In some embodiments, the fingers14aare spaced apart from and in parallel to the fingers14b. In some embodiments, the dielectric material14cis between the fingers14aand the fingers14b. The dielectric layer14cmay be formed by spin coating, deposition, plasma enhanced deposition, or the like. The fingers14aand14bmay be formed by a variety of techniques, e.g., single and/or dual damascene processes, electroplating, electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. A planarization operation, such as chemical mechanical planarization (CMP) operation, may be performed on the top surfaces of the fingers14a, the fingers14b, and the dielectric layer14c. As such, a MOM capacitor14(or a metal-dielectric-metal layer) is formed. Referring toFIG.6B, an etch stop layer82is formed on the fingers14a, the fingers14b, and the dielectric layer14c, and a liner83is formed on the etch stop layer82. The liner83may be formed by spin coating, deposition, plasma enhanced deposition, or the like. Referring toFIG.6C, operations similar to those illustrated inFIGS.6A-6Bare performed to form dielectric materials11c-13c, patterned metal layers each including two sets of fingers, etch stop layers82, and liners83, and thus the MOM capacitors11-14are formed as stack illustrated inFIG.6C. Referring toFIG.6D, a dielectric layer40is formed on the fingers11aand11band the dielectric material11c, and a metal layer70including a plurality of metal lines is formed within the dielectric layer40. The dielectric layer40may be composed of glass, such as un-doped silicate glass (USG), or the like. In some other embodiments, the dielectric layer40may be composed of oxide layer, such as plasma enhanced deposited oxide, or the like. In some embodiments, the dielectric layer40may be formed by spin coating, deposition, plasma enhanced deposition, or the like. The metal layer70may be formed by operations similar to those for forming the fingers11aand11b. Referring toFIG.6E, a dielectric layer30′ is formed over the metal layer70, conductive layers23′,22′, and21′ are formed over the dielectric layer30′, a dielectric layer20C′ is formed over the conductive layer21′, a conductive layer20A′ is formed over the dielectric layer20C′, and a mask layer85′ is formed over the conductive layer20A′. The aforesaid layers may be formed by one or more suitable deposition operations, for example, spin coating, deposition, or plasma enhanced deposition for dielectric layers, and electroplating, electroless plating, high-density IMP deposition, high-density ICP deposition, sputtering, PVD, CVD, LPCVD, or PECVD for conductive layers. Referring toFIG.6F, the mask layer85′ is patterned to form a mask layer85, and a patterning operation is performed on the conductive layer20A′ and the dielectric layer20C′ according to the mask layer85to form a conductive layer20A and a dielectric layer20C. The patterning operation on the mask layer85′ may be performed by photolithography and etching. A portion of the dielectric layer20C′ may be removed by etching so as to form the dielectric layer20C having a stepped structure including portions20C1and20C2. Referring toFIG.6G, a cap layer84′ is formed over the mask layer85, the conductive layer20A, and the dielectric layer20C. The cap layer84′ may be formed by spin coating, deposition, plasma enhanced deposition, or the like. Referring toFIG.6G, the cap layer84′, the dielectric layer20C, the conductive layers21′,22′, and23′, and the dielectric layer30′ are patterned to form the cap layer84, the dielectric layer20C, the conductive layers21,22, and23, and the dielectric layer30, an ILD50is formed over the cap layer84, the dielectric layer20C, the conductive layers21,22, and23, and the dielectric layer30, and via trenches60a′ and60b′ are formed within the ILD50to expose a portion of the conductive layer20A and a portion of the conductive layer20B. The patterning operation may be performed by the following steps. A photomask (not shown) may be disposed over the cap layer84′, and portions of the cap layer84′, the dielectric layer20C, the conductive layers21′,22′, and23′, and the dielectric layer30′ exposed from the photomask are removed to form the cap layer84, the dielectric layer20C, the conductive layers21,22, and23, and the dielectric layer30, then the photomask is removed. Referring toFIG.6I, a conductive material is formed in the via trenches60a′ and60b′ to form conductive interconnections60aand60b. The conductive material can formed by a variety of techniques, e.g., deposition, electro plating, electro-less plating, sputtering, PVD, atomic layer deposition (ALD), or the like. In some embodiments, the conductive material is or includes AlCu. In some embodiments, a planarization operation is performed to remove the excessive conductive material above a top surface of ILD50. FIGS.7A to7Eare cross-sectional views of intermediate stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.7A, operations similar to those illustrated inFIGS.6A-6Dare performed to form a stack of MOM capacitors11-14, a dielectric layer40, and a metal layer70including a plurality of metal lines within the dielectric layer40. Referring toFIG.7B, operations similar to those illustrated inFIG.6Eare performed to form a dielectric layer30′ over the metal layer70, a conductive layer20B′ over the dielectric layer30′, a dielectric layer20C′ over the conductive layer20B′, a conductive layer20A′ over the dielectric layer20C′, and a mask layer85′ over the conductive layer20A′. In some embodiments, forming the dielectric layer30including forming a sub-layer320over the fingers11aand11band the dielectric material11c; and forming a sub-layer310on the sub-layer320. The sub-layers310and320may be formed by one or more suitable deposition operations, for example, spin coating, deposition, or plasma enhanced deposition. Referring toFIG.7C, operations similar to those illustrated inFIGS.6F-6Gare performed to form a patterned mask layer85, a conductive layer20A, and a cap layer84′ over the mask layer85and the conductive layer20A. In some embodiments, the cap layer84′ is formed by forming a sub-layer842′ over the mask layer85, the conductive layer20A, and the dielectric layer20C, and forming a sub-layer841′ on the sub-layer841′. The sub-layers841′ and842′ may be formed by one or more suitable deposition operations, for example, spin coating, deposition, or plasma enhanced deposition. Referring toFIG.7D, operations similar to those illustrated inFIG.6Hare performed to form the cap layer84including sub-layers841and842, the dielectric layer20C, and the conductive layer20B, an ILD50is formed over the cap layer84, the dielectric layer20C, the conductive layer20B, and the dielectric layer30, and via trenches60a′ and60b′ are formed within the ILD50to expose a portion of the conductive layer20A and a portion of the conductive layer20B. Referring toFIG.7E, operations similar to those illustrated inFIG.6Iare performed to form conductive interconnections60aand60b. FIGS.8A to8Eare cross-sectional views of intermediate stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.8A, operations similar to those illustrated inFIGS.6A-6Dare performed to form a stack of MOM capacitors11-14, a dielectric layer40, and a metal layer70including a plurality of metal lines within the dielectric layer40. Referring toFIG.8B, a dielectric sub-layer320is formed over the fingers11aand11band the dielectric material11c, and a dielectric sub-layer310is formed on the sub-layer320. The sub-layers310and320may be formed by one or more suitable deposition operations, for example, spin coating, deposition, or plasma enhanced deposition. Still referring toFIG.8B, conductive layers20A′,20B and20D and a dielectric layer20C are formed on the dielectric layer30. In some embodiments, the conductive layer20B is disposed above the dielectric layer30, herein the conductive layer20B covers at least a portion of a region of a top surface of the dielectric layer30, as at least another portion of the top surface of the dielectric layer30is exposed from the conductive layer20B. The top surface of the dielectric layer30exposing from the conductive layer20B is covered by the dielectric layer20C. In some embodiments, the forming of the dielectric layer30may include laminating ZrO2—Al2O3—ZrO2tri-layer. The conductive layer20D has a portion overlapping the conductive layer20B and a portion directly on the dielectric layer30, herein the dielectric layer30is formed above the conductive layer20B, spacing between the conductive layer20D and the conductive layer20B. The dielectric layer30is further formed above and covering the conductive layer20D. The conductive layer20A′ is further formed above the dielectric layer30over the conductive layers20B and20D. Referring toFIG.8C, at least a portion of the conductive layer20A′ is removed to form a conductive layer20A. The remained portions of the conductive layers20A,20B and20D together with the dielectric layer20C form a MIM capacitor structure. Referring toFIG.8D, an ILD50is formed above the conductive layers20A,20B and20D and the dielectric layer20C. The ILD50may be formed by a variety of techniques, e.g., spin-on coating, deposition, plasma enhanced deposition, or the like. Still referring toFIG.8D, via trenches60c′ and60d′ are formed above the metal lines of the metal layer70by, for example, dry etching operation. The via trench60c′ penetrates the ILD50, the conductive layer20A, the dielectric layer20C, the conductive layer20D, and the dielectric layer30including sub-layers310and320. The via trench60d′ penetrates the ILD50, the conductive layer20A, the dielectric layer20C, the conductive layer20B, and the dielectric layer30including sub-layers310and320. Referring toFIG.8E, barrier layers61are conformably formed at least on the sidewalk of the via trenches60c′ and60d′, and a conductive material is formed inside the via trenches60c′ and60d′ to form conductive interconnections60cand60d. The conductive material can formed by a variety of techniques, e.g., deposition, electro plating, electro-less plating, sputtering, PVD, ALD, or the like. In some embodiments, the conductive material is AlCu. In some embodiments, a planarization operation is performed to remove the excessive conductive material above a top surface of the ILD50. FIGS.9A to9Eare cross-sectional views of intermediate stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. Referring toFIG.9A, operations similar to those illustrated inFIGS.6A-6Dare performed to form a stack of MOM capacitors11-14, a dielectric layer40, and a metal layer70including a plurality of metal lines within the dielectric layer40. Next, a dielectric layer30is formed over the metal layer70, and a trench30′ is formed from a top surface of the dielectric layer30into the dielectric layer30. The trench30′ can be formed by using, for example, drilling, laser drilling, etching or other suitable operations. Referring toFIG.9B, a conductive layer20B′ is formed on a bottom surface and sidewall surfaces of the trench30′ and on a top surface of the dielectric layer30. In some embodiments, the conductive layer20B′ is conformally formed on the bottom surface and sidewall surfaces of the trench30′ and the top surface of the dielectric layer30. Next, a dielectric layer20C′ is conformally formed on the conductive layer20B′. In some embodiments, a portion of the dielectric layer20C′ is formed within the trench30′. Next, a conductive layer20A′ is conformally formed on the dielectric layer20C′. In some embodiments, a portion of the conductive layer20A′ is formed within the trench30′. Next, a mask layer85′ is formed over the conductive layer20A′. Referring toFIG.9C, operations similar to those illustrated inFIGS.6F-6Gare performed to form a patterned mask layer85, a conductive layer20A, and a cap layer84′ over the mask layer85and the conductive layer20A. In some embodiments, the cap layer84′ is formed by forming a sub-layer842′ over the mask layer85, the conductive layer20A, and the dielectric layer20C, and forming a sub-layer841′ on the sub-layer841′. The sub-layers841′ and842′ may be formed by one or more suitable deposition operations, for example, spin coating, deposition, or plasma enhanced deposition. Referring toFIG.9D, operations similar to those illustrated inFIG.6Hare performed to form the cap layer84including sub-layers841and842, the dielectric layer20C, and the conductive layer20B, an ILD50is formed over the cap layer84, the dielectric layer20C, the conductive layer20B, and the dielectric layer30, and a via trench60′ is formed within the ILD50to expose a portion of the conductive layer20A. Referring toFIG.9E, a conductive material is formed in the via trench60′ to form a conductive interconnection60. FIG.10Aillustrates a schematic view of a circuit10A in accordance with some embodiments of the present disclosure. The circuit10A includes a decoupling capacitor100, transistors300and400, and a diode200. The decoupling capacitor100may be an in-die decoupling capacitor. The decoupling capacitor100may include one or more MOM capacitors and one or more MIM capacitors in accordance with some embodiments of the present disclosure, and the numbers of the MOM capacitors and the MIM capacitors may vary according to actual applications. For example, the decoupling capacitor100may include the structures of the MOM capacitor11and the MIM capacitor20as shown inFIG.1,FIG.1A,FIG.1B,FIG.1C,FIG.1D,FIG.2A,FIG.2B,FIG.3,FIG.4, orFIG.5. The decoupling capacitor100has terminals110and120, and the terminal110is electrically connected to the transistor300and the diode200(through the terminal A). The terminal120of the decoupling capacitor100is electrically connected to ground or a low voltage side. The terminal120of the decoupling capacitor100is configured to receive a voltage lower than a voltage at the terminal110. In some embodiments, a voltage difference between the terminal110and the terminal120is equal to or greater than 6V. In some embodiments, referring toFIGS.2A and2B, the terminal110may be connected to the voltage V1. In some embodiments, referring toFIGS.2A and2B, the terminal120may be connected to the voltage V2or the voltage V3. In some embodiments, referring toFIGS.2A and2B, the terminal110may be connected to the fingers11aof the MOM capacitor11, and the terminal120may be connected to the fingers11bof the MOM capacitor11or the conductive layer20A of the MIM capacitor20. The transistor300may be or include a high voltage (HV) pMOS transistor, e.g., a lateral diffused MOS (LDMOS) transistor, a bipolar-CMOS-DMOS (BCD) transistor, or a diode. In some embodiments, the HV pMOS transistor may include a planar MOS structure or a FinFet structure. In some embodiments, the transistor300may be or include an I/O component or a logic device. The source (e.g., the terminal D) of the transistor300may be configured to receive a supply voltage (e.g., VDD) or other circuits. The gate of the transistor300may be configured to receive a control signal to turn on or turn off the transistor300. The drain of the transistor300may be connected to the decoupling capacitor100and the diode200. The diode200includes an anode (e.g., the terminal A) and a cathode (e.g., the terminal B). The terminal A of the diode200may function as an input of the diode200. The terminal B of the diode200may function as an output of the diode200. The terminal A of the diode200is electrically connected to the drain of the transistor300and the terminal110of the decoupling capacitor100. The terminal B of the diode200is electrically connected to the transistor400. The diode200may be or include a laser diode, a CMOS image sensor (CIS) pixel unit, an OLED pixel unit, or a combination thereof. In some embodiments, the transistor400may be or include a HV nMOS transistor, e.g., a LDMOS transistor, a BCD transistor, or a diode. The transistor400has a drain connected to the terminal B of the diode200. The transistor400has a gate configured to receive a control signal to turn on or turn off the transistor400. The transistor400include a source (e.g., the terminal E) connected to a voltage source (e.g., ground or VSS) or other circuits. FIG.10Billustrates a schematic view of a circuit11B in accordance with some embodiments of the present disclosure. In some embodiments, the circuit10B may be a CIS pixel unit. The CIS pixel unit may be a CIS four-transistor (4T) pixel. In some embodiments, the diode200illustrated inFIG.10Amay be replaced by the CIS 4T pixel shown inFIG.10B. The CIS 4T pixel includes a transfer transistor TG coupled to a transfer voltage Vtx, a reset transistor RST coupled to a reset signal Vtx, a source follower SF monitoring a potential Vfdof a floating diffusion (FD) which receives a signal charge Vpdcollected by a photodiode PD, and a select transistor SE connected to a current source Ibiasand an output voltage Vout. The voltage source Vddof the CIS 4T pixel shown inFIG.11Bmay be connected to the terminal A illustrated inFIG.10A, and the ground which is connected to the photodiode PD may be connected to the terminal B illustrated inFIG.10A. According to an embodiment, a semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer. According to an embodiment, an electronic device includes a decoupling capacitor. The decoupling capacitor has a first terminal electrically connected to a diode and a second terminal configured to receive a first voltage. The decoupling capacitor includes a first MOM capacitor, a MIM capacitor, and a dielectric layer. The first MOM capacitor includes a first finger and a second finger arranged in parallel. The MIM capacitor is over the first MOM capacitor. The MIM capacitor includes a conductive layer. The first terminal is connected to the first finger of the first MOM capacitor, and the second terminal is connected to the second finger of the first MOM capacitor or the conductive layer of the MIM capacitor. The dielectric layer is between the MIM capacitor and the first MOM capacitor. According to an embodiment, a method of manufacturing a semiconductor structure includes: forming a patterned metal layer comprising a plurality of first fingers and a plurality of second fingers spaced apart from and in parallel to the first fingers; forming a dielectric material between the first fingers and the second fingers; forming a first dielectric layer over the first fingers, the second fingers, and the dielectric material; forming a first conductive layer over the first dielectric layer; forming a second dielectric layer over the first conductive layer; and forming a second conductive layer over the second dielectric layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 55,529 |
11942468 | DETAILED DESCRIPTION FIG.1is a perspective view of a top-side of a packaged semiconductor die with circuitry arranged symmetrically around an axis of the die according to some embodiments of the disclosure. A packaged die100may include a package terminal array104for coupling circuitry within the packaged die100to other electrical components and/or devices, such as through electrical paths of a printed circuit board (PCB). The packaged die100may include circuitry, such as a first high-voltage circuit110, a second high-voltage circuit120, and a low-voltage circuit130. The circuits110and120may be located in the packaged die100in a symmetric arrangement around an axis102. The circuit130may also be located in the packaged die100in a symmetric arrangement around axis102. High-voltage circuits may refer to circuits that may generate voltages that are higher than those generated by the low-voltage circuits, voltages that are at least twice those generated by the low-voltage circuits, or voltages that are at least triple those generated by the low-voltage circuits. High-voltage circuits may refer to circuits that generate voltages that are higher than a supply voltage for the circuit, circuits that generate voltages that are at least double the supply voltage for the circuit, or circuits that generate voltages that are at least triple the supply voltage for the circuit. In different embodiments, high-voltage circuits may refer to circuits that generate voltages higher than 1.8 volts (such as between 1.8-10 volts, between 1.8-15 volts, or between 1.8-20 volts), higher than 3.3 volts (such as between 3.3-10 volts, between 3.3-15 volts, or between 3.3-20 volts), higher than 5 volts (such as between 5-15 volts, between 5-20 volts, between 5-25 volts), higher than 10 volts (such as between 10-20 volts, between 10-30 volts, or between 10-50 volts), higher than 15 volts (such as between 15-30 volts, between 15-50 volts, or between 15-100 volts), higher than 20 volts (such as between 20-50 volts, between 20-100 volts, or between 20-150 volts), or higher than 25 volts (such as between 25-50 volts, between 25-75 volts, or between 25-150 volts). The circuits110,120, and130are coupled to terminals of the terminal package array104to input and output signals to other devices. One arrangement of a terminal package array is shown inFIG.2.FIG.2is a perspective view of a bottom side of a packaged semiconductor die with circuits arranged symmetrically around an axis of the die according to some embodiments of the disclosure. A package terminal array104of a packaged die100may include edge terminals104A and interior terminals104B. The terminals104A-B may be coupled to the circuits110,120, and/or130through vertical conductors122, sometimes referred to as vias, and/or horizontal conductors124. Edge terminals104A are located in the array104such that at least one side of the edge terminals104A has no neighboring terminal. That is, the edge terminals104A are the outermost terminals of the array. The interior terminals104B each have neighboring terminals in the array and are spaced apart from neighboring terminals by a pitch, which may be less than 0.5 mm. Some of the terminals104A and104B may be dummy terminals without affecting whether the terminals are edge or interior terminals. A printed circuit board (PCB) includes electrical traces that function as electrical paths for coupling inputs and outputs to the packaged die100through the package terminal array. Traces to the interior terminals104B are routed through the spacing between the edge terminals104A. Traces to the edge terminals104A are not subject to such spacing constraints. The spacing constraints for reaching interior terminals104B restrict the widths of the traces that may reach the interior terminals104B and the spacing possible between those traces. Circuits of the embedded die100are organized according to embodiments of this disclosure to locate high-voltage circuits110and120symmetrically around the axis102such that high-voltage outputs of the high-voltage circuits110and120may be coupled to edge terminals104A to avoid the spacing constraints for traces reaching the interior terminals104B. Symmetry about the axis for the circuits110,120, and130may be arranged by organizing components of the circuits into columns. Each column may be defined, in part, by a positive and negative voltage supply rail passing through each column such that all circuits in the column are coupled to the same portion of the supply rail. One column organization for low-voltage circuitry is shown inFIG.3, although similar columns may be organized in the high-voltage circuits.FIG.3is a block diagram illustrating a columnar layout for circuitry according to some embodiments of the disclosure. Low-voltage circuit130may be organized into column310and column320. Each of the columns310and320may be coupled to different portions of a positive voltage supply rail302. Each of the columns310and320may be coupled to different portions of a negative voltage supply rail304. The columns310and320may be organized around an axis of symmetry102and between the high-voltage circuits110and120. A width of the columns310and320may be defined by a spacing of terminals of the packaging terminal array104. As shown inFIG.3, the columns310and320are defined as a ratio of 1:1 to the pitch of the package terminal array104. However, other ratios may be used such that multiple columns fit between terminals of the array104. For example, a ratio of 2:1 results in a column width approximately half the pitch of the array104, and a ratio of 4:1 results in a column width approximately one quarter the pitch of the array104. The ratios may be fractions being defined as ratios of positive integer numbers not exceeding 12. Circuits within columns310and320may be organized into blocks330A-330F, in which each of the blocks330A-330F includes components configured to provide separate functions. The circuit layout may be used to construct an audio amplifier for driving a load that reproduces sounds. Driving a transducer for reproduced sounds may involve driving the load with a voltage that is higher than an available supply voltage. For example, a piezoelectric transducer may be driven, at times, by an audio amplifier with a drive signal that is above 15V. One circuit layout for an audio amplifier that is organized in a symmetric manner around an axis is shown inFIG.4.FIG.4is a block diagram illustrating a circuit layout for an audio amplifier with symmetry around an axis of a semiconductor die according to some embodiments of the disclosure. An amplifier400may include differential output stages410and420organized symmetrically around the axis102of the circuitry on a semiconductor die. The splitting of the two output stages to physically separate locations may create a feedback loop that creates electromagnetic noise, but the symmetry creates in-phase changes that cancel out such that the physical separation does not reduce the fidelity of output from the separated output stages. Low-voltage circuits may be located between the output stages410and420. The low-voltage circuit430may be circuitry configured to operate at voltages lower than the high-voltage circuit of output stages410and420. Low-voltage circuitry430may include small-signal analog and digital circuitry. Small-signal circuitry refers to circuitry configured to operate at and output signals with voltage levels lower than 5 Volts. Circuit430may include digital pads432for receiving a digital input signal, such as a digital audio signal. Circuit430may also include digital circuits434, which process the digital signals received at the pads432. The digital circuits434may include circuitry for performing operations such as decoding the digital signals, volume leveling, application of equalizer settings, high-definition enhancements, and/or echo or room effects. The digital circuits434may be configured to perform particular functions by one-time programmable (OTP) memory436. For example, the digital circuits434may be a digital signal processor (DSP) configured at startup based on firmware in the OTP436. The output of the digital circuits434is routed in routing circuitry440to a modulator442. The modulator442modulates the digital signal from digital circuits434to an analog signal for amplification by the output stages410and420. The modulator442is coupled to analog circuitry444and gate drivers446A-446B for driving amplifier gain stages in the output stages410and420. The analog circuitry444may be coupled to analog pads and accompanying routing circuitry448. Circuit430may also include level shifter (LS) circuits438located symmetrically around the axis102corresponding to the output stages410and420. Output stages410and420may be high-voltage circuits that are particular examples of the high-voltage circuits110and120shown inFIG.1. A packaging terminal array configuration for a packaged die may have high-voltage terminals at an edge of the packaging terminal array as shown in the example configuration ofFIG.5.FIG.5is a block diagram illustrating a package terminal array with high-voltage outputs at an edge of the array according to some embodiments of the disclosure. A packaged die500may include several terminals including a first terminal511, a second terminal512, a third terminal513, and a fourth terminal514. The terminals511-514may be configured for inputting and/or outputting high-voltage signals by being coupled to appropriate circuitry within high-voltage circuitry within the packaged die500. For example, terminals511and512may output amplified signals for driving a load502, such as a piezoelectric transducer. Terminals513and514may receive feedback signals from the load502that may be used to determine, for example, a voltage across the load and thus may also be high-voltage signals because the signal from terminals511-512driving the load502may be high-voltage signals. In some embodiments, edge terminals may be used to couple the high-voltage circuits to capacitors that are used to generate voltages to a high voltage that is above the supply voltage level. Other signals coupled to edge terminals may include Vbst_bridge, Gnda_bridge, Vcap1_top, Vcap1_bot, vdda, vssa, Vcap2_bot, Vcap2_top, vddd, and asp_blk, although not all of these signals necessarily may be high-voltage signals. Signals coupled to interior terminals may include clock, supply, control, and information signals, such as i2c_sda, i2c_scl, init_b, reset_b, i2c_addr, vddio, vssd, asp_fsync, mclk, mute_b, asp_dm, asp_dout, gpio, Ana_vis1, and Ana_vis2. The packaging terminal arrays may be formed on the packaged dies at the wafer-level as described in the example manufacturing process ofFIG.6.FIG.6is a flow chart illustrating a method of wafer-level packaging for packaging semiconductor dies with circuitry arranged symmetrically around axes of the dies according to some embodiments of the disclosure. A method600begins at block602with forming high-voltage circuitry in symmetrical regions around axes of individual chips on a wafer. The forming of circuitry may include steps including preparing a substrate, implanting dopant to the substrate, depositing metal and insulating layers on the substrate to form transistor structures, resistor structures, and/or capacitor structures. For example, a transistor with source, drain, and gate regions may be formed, with a gate electrode structure above the gate region and various contacts to the source, drain, and gate of the transistors. Metal layers over the transistor and other structures may be formed to interconnect the structures to obtain an output stage of a differential amplifier. The forming of block602may form the structures in a layout with symmetrical high-voltage circuits organized around an axis, such as described above with reference toFIG.1,FIG.2,FIG.3, orFIG.4. At block604, low-voltage circuitry is formed between symmetric regions of high-voltage circuitry on individual chips on the wafer. The forming at block604may include steps similar to those described for forming the high-voltage circuitry but used to form different circuitry with different interconnects to obtain low-voltage circuitry, such as digital processing circuitry. The forming of block604may form the structures in a layout with low-voltage circuits organized in columns between the high-voltage circuits, such as described above with reference toFIG.1,FIG.2,FIG.3, orFIG.4. The forming of the low-voltage circuits at block604and the high-voltage circuits at block602may be performed in a different order or interchangeable to obtain a wafer with a plurality of dies. The steps of blocks602and604are used to form a plurality of dies on a semiconductor wafer. Each of the dies may be further processed on the wafer, and later separated into separate chips for use in products, such as mobile phones, headphones, tablet computing devices, or other computing or audio devices. At block606, the individual chips are packaged on the wafer by forming a package and a package terminal array for each individual chip and accompanying vertical and horizontal conductors to couple terminals of the array to the high-voltage and low-voltage circuitry. The package terminal array may be coupled to circuitry on the die with high-voltage outputs and inputs coupled to edge terminals of the array, such as described above with reference toFIG.2orFIG.5. At block608, the individual chips are separated to form separate packaged dies by dicing the wafer. An audio amplifier is one example of high-voltage circuitry that may be organized on a die as described above. Such an audio amplifier may be used for producing audio output in a variety of electronic devices, such as portable media players, cell phones, laptop computers, stereo systems, and other devices that convert stored audio data into an audio output. One advantageous embodiment for such an audio amplifier with symmetric high-voltage output stages coupled to edge terminals of a package terminal array is a mobile device for playing back music, high-fidelity music, and/or speech from telephone calls.FIG.7is an illustration showing an example mobile device for audio playback including such an audio amplifier according to one embodiment of the disclosure. A mobile device700may include a display702for allowing a user to provide user input to the mobile device700. One or more physical buttons704may also allow a user to provide user input to the mobile device700. The mobile device700may also include a printed circuit board (PCB)710interconnecting components that provide the functionality of mobile device700. For example, application processor (AP)732, memory734, and audio amplifier736components may be attached to the PCB710. Communications between the components may be provided through conductors on or in the PCB710. Communication bridge chips720and722coupled to endpoints of the conductors may include processing and memory circuitry that provide interfaces for transmitting and receiving data between components732,734, and736. The audio amplifier736may provide an audio output signal to a headphone jack740, for driving a transducer, such as headphones742. The audio component736may also be coupled to an internal speaker744, such as a piezoelectric transducer. Conductors in or on the PCB710may route a signal from a high-voltage output at an edge terminal of a package terminal array of the audio amplifier736to the speaker744. Such a routing of the PCB may reduce spacing issues with routing conductors carrying high-voltage signals between other terminals in the array to reach an interior terminal. The audio amplifier736may provide signal processing, digital-to-analog conversion (DAC), filtering, and/or amplification, using circuitry described such as with reference toFIG.4, to audio files received from memory734for output to a user. Although the data received at the audio amplifier736is described as received from memory734, the audio data may also be received from other sources, such as an universal serial bus (USB) connection, a device connected through Wi-Fi to the mobile device700, a cellular radio, an Internet-based server, another wireless radio, and/or another wired connection. The schematic flow chart diagram ofFIG.6is generally set forth as a logical flow chart diagram. As such, the depicted order and labeled steps are indicative of aspects of the disclosed method. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more steps, or portions thereof, of the illustrated method. Additionally, the format and symbols employed are provided to explain the logical steps of the method and are understood not to limit the scope of the method. Although various arrow types and line types may be employed in the flow chart diagram, they are understood not to limit the scope of the corresponding method. Indeed, some arrows or other connectors may be used to indicate only the logical flow of the method. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted method. Additionally, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown. The operations described above as performed by high-voltage or low-voltage circuits may be performed by any circuit configured to perform the described operations. Such a circuit may include logic circuitry, such as transistors configured as logic gates, and memory circuitry, such as transistors and capacitors configured as dynamic random access memory (DRAM), electronically programmable read-only memory (EPROM), or other memory devices. The logic circuitry may be configured through hard-wire connections or through programming by instructions contained in firmware. Further, the logic circuity may be configured as a general-purpose processor capable of executing instructions contained in software and/or firmware. If implemented in firmware and/or software, functions described above may be stored as one or more instructions or code on a computer-readable medium. Examples include non-transitory computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise random access memory (RAM), read-only memory (ROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc includes compact discs (CD), laser discs, optical discs, digital versatile discs (DVD), floppy disks and Blu-ray discs. Generally, disks reproduce data magnetically, and discs reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media. Although the present disclosure and certain representative advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. For example, although audio amplifiers are described in portions of the detailed description, aspects of the invention may be applied to the design of or implemented on different kinds of circuitry, including processors such as graphics processing units (GPUs), central processing units (CPUs), and digital signal processors (DSPs). As another example, although processing of certain kinds of data, such as audio data, may be described in example embodiments, other kinds or types of data may be processed through the methods and devices described above. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. | 20,902 |
11942469 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In some embodiments, an integrated circuit includes gate-conductors and terminal-conductors at the front side of a substrate. The integrated circuit also includes backside horizontal conducting lines in a backside first conducting layer and backside vertical conducting lines in a backside second conducting layer at the backside of the substrate. A backside vertical conducting line of interest is aligned with a first vertical boundary of a circuit cell and is connected to a backside horizontal conducting line of interest through a pin-connector. In some embodiments, the backside horizontal conducting line of interest is an extended conducting line that extends across the first vertical boundary of the circuit cell. In some embodiments, the backside vertical conducting line of interest is a local two-dimensional conducting line which has a first portion with a first width and has a second portion with a second width that is different from the first width. In some embodiments, because of the extended conducting line and/or the local two-dimensional conducting line, more flexibility is provided for the positioning of the pin-connector without generating design rule violations. FIGS.1A-1Bare layout diagrams of a NOR gate circuit100, in accordance with some embodiments. The layout diagrams ofFIGS.1A-1Binclude the layout patterns for specifying a p-type active-region structure80pand an n-type active-region structure80nboth extending in the X-direction, gate-conductors (152and158) extending in the Y-direction, terminal-conductors (132p,132n,135p,135n, and138) extending in the Y-direction, and dummy gate-conductors (151and159) extending in the Y-direction. The NOR gate circuit100is in a cell that is bounded by cell boundaries110, and the cell width along the X-direction is bounded by two vertical cell boundaries111and119extending in the Y-direction. The layout diagram ofFIG.1Aalso includes the layout patterns for specifying the power rails (40and20) extending in the X-direction, the front-side first-layer conducting lines (122,124, and126) extending in the X-direction, and various via-connectors. The layout diagram ofFIG.1Balso includes the layout patterns for specifying the backside horizontal conducting lines (181,182,184, and186) extending in the X-direction, the backside vertical conducting lines (172,175, and178) extending in the Y-direction, and various via-connectors. In the X-Y coordinate, the X-direction and the Y-direction are perpendicular to each other. In the NOR gate circuit100as specified by the layout diagrams ofFIGS.1A-1B, two adjacent gate-conductors (such as the gate-conductors152and158) are separated by a pitch distance equal to a contacted poly pitch (CPP). In the NOR gate circuit100, a distance between the vertical cell boundary111and the vertical cell boundary119along in the X-direction is three CPPs. FIG.1Cis an equivalent circuit of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1B, in accordance with some embodiments.FIGS.2A-2EandFIGS.3A-3Care cross-sectional views of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1B, in accordance with some embodiments. In the NOR gate circuit100as specified by the layout diagrams ofFIGS.1A-1Band as shown in the equivalent circuit ofFIG.1C, the gate-conductor152intersects the p-type active-region structure80pat the channel region of a p-type transistor pA1, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA1. The gate-conductor158intersects the p-type active-region structure80pat the channel region of a p-type transistor pA2, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA2. The terminal-conductors132pand135pintersect the p-type active-region structure80pat various source/drain regions of the p-type transistor pA2and pA1. The terminal-conductors132nand135nintersect the n-type active-region structure80nat various source/drain regions of the n-type transistor nA2and nA1. The terminal-conductor138intersect the p-type active-region structure80pand the n-type active-region structure80ncorrespondingly at the drain region of the p-type transistor pA1and at the drain region of the n-type transistor nA1. Non-limiting examples of the p-type transistors (pA1and pA2) and the n-type transistors (nA1and nA2) include FinFETs, nano-sheet transistors, and nano-wire transistors. The layout patterns for the dummy gate-conductors151and159inFIGS.1A-1Bspecify that the active regions (such as, source regions, drain regions, and channel regions) in the NOR gate circuit100are isolated from the active regions in adjacent cells. In the NOR gate circuit100as specified by the layout diagrams ofFIGS.1A-1Band as shown in the equivalent circuit ofFIG.1C, the front-side first-layer conducting lines (122,124, and126) and the power rails (40and20) are positioned in a first connection layer above the substrate. In some embodiments, the first connection layer is the first metal layer M0above the top insulation layer fabricated in the front-end-of-line (FEOL) process. In the NOR gate circuit100, the terminal-conductor132pis conductively connected to the power rail40through the via-connector1VDdd, and the power rail40is configured for providing a first supply voltage VDD. The terminal-conductor135nis conductively connected to the power rail20through the via-connector1VDss, and the power rail20is configured for providing a second supply voltage VSS. The front-side first-layer conducting line126is conductively connected to the terminal-conductor132nthrough the via-connector1VD1and conductively connected to the terminal-conductor138through the via-connector1VD2. In the NOR gate circuit100, the terminal-conductor138(inFIG.1A) is also conductively connected to the backside horizontal conducting line182(inFIG.1B) through the via-connector1BVD1that passes through the substrate. Additionally, the gate-conductor152(inFIG.1A) is conductively connected to the backside horizontal conducting line184(inFIG.1B) through the via-connector1BVG1, and the gate-conductor158(inFIG.1A) is conductively connected to the backside horizontal conducting line186(inFIG.1B) through the via-connector1BVG2. In the NOR gate circuit100, the backside horizontal conducting line182is conductively connected to the backside vertical conducting line178through the via-connector1BV0A. The backside horizontal conducting line184is conductively connected to the backside vertical conducting line172through the via-connector1BV0B. The backside horizontal conducting line186is conductively connected to the backside vertical conducting line175through the via-connector1BV0C. In the NOR gate circuit100, the backside horizontal conducting lines181,182,184, and186are in a backside first conducting layer below the substrate. The backside vertical conducting lines172,175, and178are in a backside second conducting layer that is below the backside first conducting layer. In some embodiments, the backside first conducting layer is the first backside metal layer BM0fabricated at the backside of the substrate, and the backside second conducting layer is the second backside metal layer BM1fabricated at the backside of the substrate. The first backside metal layer BM0is sandwiched between the substrate and the second backside metal layer BM1. Each of the via-connectors1BV0A,1BV0B, and1BV0C is a via-connector BVO that passes through the interlayer dielectric (ILD) materials separating the second backside metal layer BM1and the first backside metal layer BM0. In the NOR gate circuit100, the backside vertical conducting line172, the via-connector1BV0B, and the backside horizontal conducting line184are conductively connected together to carry an input signal “A1” of the NOR gate circuit100. The backside vertical conducting line175, the via-connector1BV0C, and the backside horizontal conducting line186are conductively connected together to carry an input signal “A2” of the NOR gate circuit100. The backside vertical conducting line178, the via-connector1BV0A, and the backside horizontal conducting line182are conductively connected together to carry an output signal “ZN” of the NOR gate circuit100. In the NOR gate circuit100, the via-connector1BV0A (as shown inFIG.1C) functions as a pin-connector extending in the Z-direction for connecting the backside vertical conducting line178to the backside horizontal conducting line182that carries the output signal “ZN” of the NOR gate circuit100. In some embodiments, as shown inFIG.1B, when the backside horizontal conducting line182extends across the vertical cell boundary119, more flexibility is provided for the positioning of the pin-connector (i.e., the via-connector1BV0A) without generating design rule violations. InFIG.1B, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” extending in the X-direction. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one eighth of the CPP. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one fourth of the CPP. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one half of the CPP. In some embodiments, the distance “Δ” is selected to be sufficiently large to mitigate the design rule violations associated with the pin-connector connection between the backside vertical conducting line178and the backside horizontal conducting line182. In some embodiments, the distance “Δ” is selected to be less than one CPP so that the horizontal gap distance from the vertical cell boundary119to the vertical cell boundary of the adjacent cell is reduced to a minimal distance for mitigating the design rule violations associated with the pin-connector connection. InFIG.1B, the backside vertical conducting line178has a width “W” extending in the X-direction. In some embodiments, the width “W” is selected to reduce the IR drops in the backside vertical conducting line178. In some embodiments, the width “W” of the backside vertical conducting line178is larger than one half of the CPP. In some embodiments, the width “W” of the backside vertical conducting line178is larger than three fourths of the CPP. Generally, the larger the width “W”, the smaller the IR drops in the backside vertical conducting line178. The spacing requirements between adjacent backside vertical conducting lines, however, limit the maximum value of the width “W”, if the number of the tracks for the backside vertical conducting lines in a cell is fixed. Decreasing the number of the tracks may increase the maximum value of the width “W”, but routing flexibility for the cell design is reduced at the same time. In some embodiments, the compromise between the routing flexibility and the IR drop requirements determines the maximum value of the width “W”. FIG.2Ais a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane A-A′, in accordance with some embodiments. As shown inFIG.2A, the p-type active-region structure80pis on the substrate50. Each of the terminal-conductors132p,135p, and138intersects the p-type active-region structure80p. Each of the gate-conductors152and158also intersects the p-type active-region structure80p. In some embodiments, the active regions (such as, the source region, the channel region, or the drain region) in the p-type active-region structure80pare isolated from the active regions in the adjacent cells, by the boundary isolation region151iunder the dummy gate-conductor151and the boundary isolation region159iunder the dummy gate-conductor159. The front-side first-layer conducting line122overlies the insulation layer52which covers the gate-conductors (152and158) and the terminal-conductors (132p,135p, and138). The backside vertical conducting lines172,175, and178are positioned on the backside interlayer dielectric56which overlies the backside interlayer dielectric54at the backside of the substrate50. FIG.2Bis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane B-B′, in accordance with some embodiments. As shown inFIG.2B, the n-type active-region structure80nis on the substrate50. Each of the terminal-conductors132n,135n, and138intersects the n-type active-region structure80n. Each of the gate-conductors152and158also intersects the n-type active-region structure80n. In some embodiments, the active regions (such as, the source region, the channel region, or the drain region) in the n-type active-region structure80nare isolated from the active regions in the adjacent cells, by the boundary isolation region151iunder the dummy gate-conductor151and the boundary isolation region159iunder the dummy gate-conductor159. The front-side first-layer conducting line126overlies the insulation layer52which covers the gate-conductors (152and158) and the terminal-conductors (132n,135n, and138). The backside vertical conducting lines172,175, and178are positioned on the backside interlayer dielectric56which overlies the backside interlayer dielectric54at the backside of the substrate50. FIG.2Cis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane C-C′, in accordance with some embodiments. As shown inFIG.2C, the insulation layer52covers the gate-conductors (152and158), the terminal-conductors (132p,135p, and138), and the dummy gate-conductors (151and159). The backside horizontal conducting lines181and182are positioned at the backside of the substrate50. Portions of the backside interlayer dielectric54separate the backside horizontal conducting line181from the backside horizontal conducting line182. The backside vertical conducting lines172,175, and178are positioned on the backside interlayer dielectric56which covers the backside interlayer dielectric54and the backside horizontal conducting lines181and182. The via-connector1BVD1passes through the substrate50and conductively connects the terminal-conductor138with the backside horizontal conducting line182. The via-connector1BV0A passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line182with the backside vertical conducting line178. FIG.2Dis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane D-D′, in accordance with some embodiments. As shown inFIG.2D, the insulation layer52covers the gate-conductors (152and158), the terminal-conductor138, and the dummy gate-conductors (151and159). The backside horizontal conducting line184is positioned at the backside of the substrate50. The backside vertical conducting lines172,175, and178are positioned on the backside interlayer dielectric56which covers the backside interlayer dielectric54and the backside horizontal conducting line184. InFIG.2D, the via-connector1BVG1passes through the substrate50and conductively connects the gate-conductor152with the backside horizontal conducting line184. The via-connector1BV0B passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line184with the backside vertical conducting line172. FIG.2Eis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane E-E′, in accordance with some embodiments. As shown inFIG.2E, the insulation layer52covers the gate-conductors (152and158), the terminal-conductors (132n,135n, and138), and the dummy gate-conductors (151and159). The backside horizontal conducting line186is positioned at the backside of the substrate50. The backside vertical conducting lines172,175, and178are positioned on the backside interlayer dielectric56which covers the backside interlayer dielectric54and the backside horizontal conducting line186. The via-connector1BVG2passes through the substrate50and conductively connects the gate-conductor158with the backside horizontal conducting line186. The via-connector1BV0C passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line186with the backside vertical conducting line175. FIG.3Ais a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane P-P′, in accordance with some embodiments. As shown inFIG.3A, the terminal-conductor132nintersects the n-type active-region structure80non the substrate50, and the terminal-conductor132pintersects the p-type active-region structure80pon the substrate50. The insulation layer52covers the terminal-conductors132nand132p. The power rails (40and20) and the front-side first-layer conducting lines122and126are in the first connection layer overlying the insulation layer52. The via-connector1VDdd passes through the insulation layer52and conductively connects the terminal-conductor132pwith the power rail40. The backside horizontal conducting lines181,184, and186are positioned at the backside of the substrate50. The backside interlayer dielectric54and the backside horizontal conducting lines181,184, and186are covered by the backside interlayer dielectric56. The backside vertical conducting line172overlies the backside interlayer dielectric56. The via-connector1BV0B passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line184with the backside vertical conducting line172. FIG.3Bis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane Q-Q′, in accordance with some embodiments. As shown inFIG.3B, the terminal-conductor135nintersects the n-type active-region structure80non the substrate50, and the terminal-conductor135pintersects the p-type active-region structure80pon the substrate50. The insulation layer52covers the terminal-conductors135nand135p. The power rails (20and40) and the front-side first-layer conducting lines122,124, and126are in the first connection layer overlying the insulation layer52. The via-connector1VDss passes through the insulation layer52and conductively connects the terminal-conductor135nwith the power rail20. The backside horizontal conducting lines184and186are positioned at the backside of the substrate50. The backside interlayer dielectric54and the backside horizontal conducting lines184and186are covered by the backside interlayer dielectric56. The backside vertical conducting line175overlies the backside interlayer dielectric56. The via-connector1BV0C passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line186with the backside vertical conducting line175. FIG.3Cis a cross-sectional view of the NOR gate circuit100as specified by the layout diagrams inFIGS.1A-1Bin a cutting plane R-R′, in accordance with some embodiments. As shown inFIG.3C, the terminal-conductor138intersects the n-type active-region structure80nand the p-type active-region structure80pon the substrate50. The insulation layer52covers the terminal-conductor138. The power rails (20and40) and the front-side first-layer conducting lines124and126are in the first connection layer overlying the insulation layer52. The backside horizontal conducting lines182,184, and186are positioned at the backside of the substrate50. The via-connector1BVD1passes through the substrate50and conductively connects the terminal-conductor138with the backside horizontal conducting line182. The backside interlayer dielectric54and the backside horizontal conducting lines182,184and186are covered by the backside interlayer dielectric56. The backside vertical conducting line178overlies the backside interlayer dielectric56. The via-connector1BV0A passes through the backside interlayer dielectric56and conductively connects the backside horizontal conducting line182with the backside vertical conducting line178. In the NOR gate circuit100as specified by the layout diagrams ofFIGS.1A-1B, the backside vertical conducting line178has a uniform width “W” at the backside of the substrate50. In some alternative embodiments, at least one backside vertical conducting line includes a first portion having a first width and a second portion having a second width, and the first width of the first portion is larger than the second width of the second portion. As examples, in the NOR gate circuits as specified by the layout diagrams ofFIGS.4A-4E(which are described in more detail in the following), the first portion of the of the backside vertical conducting line178has a first width “Wa” and the second portion of the of the backside vertical conducting line178has a second width “Wb,” where the first width “Wa” is larger than the second width “Wb.” FIGS.4A-4Eare layout diagrams of an NOR gate circuit400, in accordance with some embodiments. Each of the layout diagrams inFIGS.4A-4Einclude the layout patterns for specifying the backside horizontal conducting lines (181,182,184, and186) and the backside vertical conducting lines (172,175, and178). The layout of the elements in the NOR gate circuit400at the backside of the substrate (as shown inFIGS.4A-4E) is different from the layout of the elements in the NOR gate circuit100at the backside of the substrate (as shown inFIG.1B). The layout of the elements in the NOR gate circuit400at the front-side of the substrate, however, is the same as the layout of the elements in the NOR gate circuit100at the front-side of the substrate (as shown inFIG.1A). Consequently, for the NOR gate circuit400, only the layout of the elements at the backside of the substrate are described in detail with reference to the layout diagrams ofFIGS.4A-4E, and the layout of the elements at the front-side are not described again with reference to front-side layout diagrams. As specified by the layout diagrams inFIGS.4A-4E, the NOR gate circuit400includes backside horizontal conducting lines181,182,184, and186in a backside first conducting layer below the substrate. The NOR gate circuit400also includes backside vertical conducting lines172,175, and178in a backside second conducting layer that is below the backside first conducting layer. The gate-conductor152is conductively connected to the backside horizontal conducting line184through the via-connector1BVG1, and the backside horizontal conducting line184is conductively connected to the backside vertical conducting line172through the via-connector1BV0B. The gate-conductor158is conductively connected to the backside horizontal conducting line186through the via-connector1BVG2, and the backside horizontal conducting line186is conductively connected to the backside vertical conducting line175through the via-connector1BV0C. The terminal-conductor138(inFIG.1A) is conductively connected to the backside horizontal conducting line182through the via-connector1BVD1, and the backside horizontal conducting line182is conductively connected to the backside vertical conducting line178through the via-connector1BV0A. As specified by the layout diagrams ofFIGS.4A-4E, in the NOR gate circuit400, the backside vertical conducting line178includes a first portion178A and a second portion178B. The first portion178A covers an overlap region between the backside horizontal conducting line182and the backside vertical conducting line178, while the second portion178B is outside the overlap region. The first portion178A has a first width “Wa” and the second portion has a second width “Wb.” The first width “Wa” is larger than the second width “Wb.” In some embodiments, the first width “Wa” is larger than the second width “Wb” by an amount that is more than one eighth of one CPP. In some embodiments, the first width “Wa” is larger than the second width “Wb” by an amount that is more than one fourth of one CPP. In some embodiments, the first width “Wa” is sufficiently larger than the second width “Wb” to allow the positioning of the pin-connector1BV0A without generating design rule violations. In some embodiments, the flexibility of positioning pin-connectors for circuit cells having cell widths less than or equal to three CPPs improves the layout area coverages in integrated circuit designs. In some embodiments, such as in the NOR gate circuit400ofFIG.4A, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” extending in the X-direction. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one eighth of the CPP. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one fourth of the CPP. In some embodiments, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP but more than one half of the CPP. In some embodiments, the distance “Δ” is selected to be sufficiently large to mitigate the design rule violations associated with the pin-connector connection between the backside vertical conducting line178and the backside horizontal conducting line182. In some embodiments, the distance “Δ” is selected to be less than one CPP so that the horizontal gap distance from the vertical cell boundary119to the vertical cell boundary of the adjacent cell is reduced to a minimal distance for mitigating the design rule violations associated with the pin-connector connection. In some embodiments, such as in the NOR gate circuit400ofFIG.4B, the backside horizontal conducting line182extends across the vertical cell boundary119. In some embodiments, such as in the NOR gate circuit400ofFIG.4C, the first portion178A of the backside vertical conducting line178extends across the vertical cell boundary119, while the second portion178B of the backside vertical conducting line178does not extend across the vertical cell boundary119. In some embodiments, such as in the NOR gate circuit400ofFIG.4D, both the first portion178A and the second portion178B of the backside vertical conducting line178extend across the vertical cell boundary119. In some embodiments, such as in the NOR gate circuit400ofFIG.4E, while the backside vertical conducting line178does not extend across the vertical cell boundary119, the first width “Wa” of the first portion178A is increased, to provide more flexibility for the positioning of the pin-connector (i.e., the via-connector1BV0A) onto the backside horizontal conducting line182. In addition, the backside vertical conducting line175(which is adjacent to the backside vertical conducting line178) is also modified, to avoid design rule violations. FIGS.5A-5Bare layout diagrams of a NAND gate circuit500, in accordance with some embodiments. The layout diagrams ofFIGS.5A-5Binclude the layout patterns for specifying a p-type active-region structure80pand an n-type active-region structure80n, gate-conductors (552and558), terminal-conductors (532p,532n,535p,535n, and538), and dummy gate-conductors (151and159). The NAND gate circuit500is in a cell that is bounded by cell boundaries110, and the cell width is bounded by two vertical cell boundaries111and119. The layout diagram ofFIG.5Aalso includes the layout patterns for specifying the power rails (40and20), the front-side first-layer conducting lines (522,524, and526), and various via-connectors. The layout diagram ofFIG.5Balso includes the layout patterns for specifying the backside horizontal conducting lines (581,582,584, and586), the backside vertical conducting lines (572,575, and578), and various via-connectors. In the NAND gate circuit500as specified by the layout diagrams ofFIGS.5A-5B, the gate-conductor552intersects the p-type active-region structure80pat the channel region of a p-type transistor pA1, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA1. The gate-conductor558intersects the p-type active-region structure80pat the channel region of a p-type transistor pA2, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA2. The terminal-conductors532pand535pintersect the p-type active-region structure80pat various source/drain regions of the p-type transistor pA2and pA1. The terminal-conductors532nand535nintersect the n-type active-region structure80nat various source/drain regions of the n-type transistor nA2and nA1. The terminal-conductor538intersect the p-type active-region structure80pand the n-type active-region structure80ncorrespondingly at the drain region of the p-type transistor pA1and at the drain region of the n-type transistor nA1. In the NAND gate circuit500as specified by the layout diagrams ofFIGS.5A-5B, the front-side first-layer conducting lines (522,524, and526) and the power rails (40and20) are positioned in a first connection layer above the substrate. In the NAND gate circuit500, the terminal-conductor535pis conductively connected to the power rail40through the via-connector5VDdd, and the power rail40is configured for providing a first supply voltage VDD. The terminal-conductor532nis conductively connected to the power rail20through the via-connector5VDss, and the power rail20is configured for providing a second supply voltage VSS. The front-side first-layer conducting line522is conductively connected to the terminal-conductor532pthrough the via-connector5VD1and conductively connected to the terminal-conductor538through the via-connector5VD2. In the NAND gate circuit500, the terminal-conductor538(inFIG.5A) is also conductively connected to the backside horizontal conducting line582(inFIG.5B) through the via-connector5BVD1that passes through the substrate. Additionally, the gate-conductor552(inFIG.5A) is conductively connected to the backside horizontal conducting line584(inFIG.5B) through the via-connector5BVG1, and the gate-conductor558(inFIG.5A) is conductively connected to the backside horizontal conducting line586(inFIG.5B) through the via-connector5BVG2. In the NAND gate circuit500, the backside horizontal conducting line582is conductively connected to the backside vertical conducting line578through the via-connector5BV0A. The backside horizontal conducting line584is conductively connected to the backside vertical conducting line572through the via-connector5BV0B. The backside horizontal conducting line586is conductively connected to the backside vertical conducting line575through the via-connector5BV0C. In the NAND gate circuit500, the backside horizontal conducting lines581,582,584, and586are in a backside first conducting layer below the substrate. The backside vertical conducting lines572,575, and578are in a backside second conducting layer below the backside first conducting layer and the substrate50. In the NAND gate circuit500, the backside vertical conducting line572, the via-connector5BV0B, and the backside horizontal conducting line584are conductively connected together to carry an input signal “A1” of the NAND gate circuit500. The backside vertical conducting line575, the via-connector5BV0C, and the backside horizontal conducting line586are conductively connected together to carry an input signal “A2” of the NAND gate circuit500. The backside vertical conducting line578, the via-connector5BV0A, and the backside horizontal conducting line582are conductively connected together to carry an output signal “ZN” of the NAND gate circuit500. In the NAND gate circuit500, the via-connector5BVOA functions as a pin-connector extending in the Z-direction for connecting the backside vertical conducting line578to the backside horizontal conducting line582that carries the output signal “ZN” of the NAND gate circuit500. In some embodiments, when the backside horizontal conducting line582extends across the vertical cell boundary119, more flexibility is provided for the positioning of the pin-connector (i.e., the via-connector5BVOA) without generating design rule violations. InFIG.5B, the backside horizontal conducting line582extends across the vertical cell boundary119by a distance “Δ” along the X-direction. In some embodiments, the backside horizontal conducting line582extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP. In some embodiments, the backside horizontal conducting line582extends across the vertical cell boundary119by a distance “Δ” that is more than one eighth of the CPP, one fourth of the CPP, or one half of the CPP. . In some embodiments, the distance “Δ” is selected to be sufficiently large to mitigate the design rule violations associated with the pin-connector connection between the backside vertical conducting line578and the backside horizontal conducting line582. In some embodiments, the distance “Δ” is selected to be less than one CPP so that the horizontal gap distance from the vertical cell boundary119to the vertical cell boundary of the adjacent cell is reduced to a minimal distance for mitigating the design rule violations associated with the pin-connector connection. FIGS.6A-6Bare layout diagrams of an inverter circuit600, in accordance with some embodiments. The layout diagrams ofFIGS.6A-6Binclude the layout patterns for specifying a p-type active-region structure80pand an n-type active-region structure80n, gate-conductors (652and658), terminal-conductors (632,635p,635n, and638), and dummy gate-conductors (151and159). The inverter circuit600is in a cell that is bounded by cell boundaries110, and the cell width is bounded by two vertical cell boundaries111and119. The layout diagram ofFIG.6Aalso includes the layout patterns for specifying the power rails (40and20), the front-side first-layer conducting lines (622,624, and626), and various via-connectors. The layout diagram ofFIG.6Balso includes the layout patterns for specifying the backside horizontal conducting lines (681,682,684, and686), the backside vertical conducting lines (672,675, and678), and various via-connectors. In the inverter circuit600as specified by the layout diagrams ofFIGS.6A-6B, the gate-conductor652intersects the p-type active-region structure80pat the channel region of a p-type transistor pA1, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA1. The gate-conductor658intersects the p-type active-region structure80pat the channel region of a p-type transistor pA2, and intersects the n-type active-region structure80nat the channel region of an n-type transistor nA2. The terminal-conductor635pintersects the p-type active-region structure80pat the source regions of the p-type transistor pA2and pA1. The terminal-conductor635nintersects the n-type active-region structure80nat the source regions of the n-type transistor nA2and nA1. The terminal-conductors632intersects the p-type active-region structure80pand the n-type active-region structure80ncorrespondingly at the drain region of the p-type transistor pA1and at the drain region of the n-type transistor nA1. The terminal-conductor638intersects the p-type active-region structure80pand the n-type active-region structure80ncorrespondingly at the drain region of the p-type transistor pA2and at the drain region of the n-type transistor nA2. In the inverter circuit600as specified by the layout diagrams ofFIGS.6A-6B, the front-side first-layer conducting lines (622,624, and626) and the power rails (40and20) are positioned in a first connection layer above the substrate. In the inverter circuit600, the terminal-conductor635pis conductively connected to the power rail40through the via-connector6VDdd, and the power rail40is configured for providing a first supply voltage VDD. The terminal-conductor635nis conductively connected to the power rail20through the via-connector6VDss, and the power rail20is configured for providing a second supply voltage VSS. The front-side first-layer conducting line626is conductively connected to the terminal-conductor632through the via-connector6VD1and conductively connected to the terminal-conductor638through the via-connector6VD2. In the inverter circuit600, the terminal-conductor638(inFIG.6A) is also conductively connected to the backside horizontal conducting line682(inFIG.6B) through the via-connector6BVD1that passes through the substrate. Additionally, the backside horizontal conducting line684(inFIG.6B) is conductively connected to the gate-conductor652through the via-connector6BVG1, and conductively connected to the gate-conductor658through the via-connector6BVG2. In the inverter circuit600, the backside horizontal conducting line682is conductively connected to the backside vertical conducting line678through the via-connector6BV0A. The backside horizontal conducting line684is conductively connected to the backside vertical conducting line672through the via-connector6BV0B. In the inverter circuit600, the backside horizontal conducting lines681,682,684, and686are in a backside first conducting layer below the substrate. The backside vertical conducting lines672,675, and678are in a backside second conducting layer below the backside first conducting layer. In the inverter circuit600, the backside vertical conducting line672functions as an input node “IN” for the inverter circuit600. The backside vertical conducting line678functions as an output node “ZN” for the inverter circuit600. In the inverter circuit600, the via-connector6BV0A functions as a pin-connector extending in the Z-direction for connecting the backside vertical conducting line678to the backside horizontal conducting line682that carries the output signal “ZN” of the inverter circuit600. In some embodiments, when the backside horizontal conducting line682extends across the vertical cell boundary119, more flexibility is provided for the positioning of the pin-connector (i.e., the via-connector6BV0A) without generating design rule violations. InFIG.6B, the backside horizontal conducting line682extends across the vertical cell boundary119by a distance “Δ” extending in the X-direction. In some embodiments, the backside horizontal conducting line682extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP. In some embodiments, the backside horizontal conducting line682extends across the vertical cell boundary119by a distance “Δ” that is more than one eighth of the CPP, one fourth of the CPP, or one half of the CPP. In some embodiments, the distance “Δ” is selected to be sufficiently large to mitigate the design rule violations associated with the pin-connector connection between the backside vertical conducting line678and the backside horizontal conducting line682. In some embodiments, the distance “Δ” is selected to be less than one CPP so that the horizontal gap distance from the vertical cell boundary119to the vertical cell boundary of the adjacent cell is reduced to a minimal distance for mitigating the design rule violations associated with the pin-connector connection. FIGS.7A-7Bare layout diagrams of an inverter circuit700, in accordance with some embodiments. The layout diagrams ofFIGS.7A-7Binclude the layout patterns for specifying a p-type active-region structure80pand an n-type active-region structure80n, gate-conductor758, terminal-conductors (735p,735n, and738), and dummy gate-conductors (151and159). The inverter circuit700is in a cell that is bounded by cell boundaries110, and the cell width is bounded by two vertical cell boundaries111and119. The layout diagram ofFIG.7Aalso includes the layout patterns for specifying the power rails (40and20), the front-side first-layer conducting lines (722,724, and726), and various via-connectors. The layout diagram ofFIG.7Balso includes the layout patterns for specifying the backside horizontal conducting lines (782,784, and786), the backside vertical conducting lines (775, and778), and various via-connectors. In the inverter circuit700as specified by the layout diagrams ofFIGS.7A-7B, the gate-conductor758intersects the p-type active-region structure80pat the channel region of a p-type transistor Tp, and intersects the n-type active-region structure80nat the channel region of an n-type transistor Tn. The terminal-conductor735pintersects the p-type active-region structure80pat the source region of the p-type transistor Tp. The terminal-conductor735nintersects the n-type active-region structure80nat the source region of the n-type transistor Tn. The terminal-conductor738intersects the p-type active-region structure80pand the n-type active-region structure80ncorrespondingly at the drain region of the p-type transistor Tp and at the drain region of the n-type transistor Tn. In the inverter circuit700as specified by the layout diagrams ofFIGS.7A-7B, the front-side first-layer conducting lines (722,724, and726) and the power rails (40and20) are positioned in a first connection layer above the substrate. In the inverter circuit700, the terminal-conductor735pis conductively connected to the power rail40through the via-connector7VDdd, and the power rail40is configured for supplying a first supply voltage VDD. The terminal-conductor735nis conductively connected to the power rail20through the via-connector7VDss, and the power rail20is configured for supplying a second supply voltage VSS. In the inverter circuit700, the terminal-conductor738(inFIG.7A) is also conductively connected to the backside horizontal conducting line782(inFIG.7B) through the via-connector7BVD1that passes through the substrate. Additionally, the gate-conductor758is conductively connected to the backside horizontal conducting line784through the via-connector7BVG1. In the inverter circuit700, the backside horizontal conducting line782is conductively connected to the backside vertical conducting line778through the via-connector7BV0A. The backside horizontal conducting line784is conductively connected to the backside vertical conducting line775through the via-connector7BV0B. In the inverter circuit700, the backside horizontal conducting lines782,784, and786are in a backside first conducting layer below the substrate. The backside vertical conducting lines772,775, and778are in a backside second conducting layer that is below the backside first conducting layer. In the inverter circuit700, the backside vertical conducting line775functions as an input node “IN” for the inverter circuit700. The backside vertical conducting line778functions as an output node “ZN” for the inverter circuit700. In the inverter circuit700, the via-connector7BV0A functions as a pin-connector extending in the Z-direction for connecting the backside vertical conducting line778to the backside horizontal conducting line782that carries the output signal “ZN” of the inverter circuit700. In some embodiments, when the backside horizontal conducting line782extends across the vertical cell boundary119, more flexibility is provided for the positioning of the pin-connector (i.e., the via-connector7BV0A) without generating design rule violations. In some embodiments, the flexibility of positioning pin-connectors for circuit cells having cell widths less than or equal to two CPPs improve the layout area coverages in integrated circuit designs. InFIG.7B, the backside horizontal conducting line782extends across the vertical cell boundary119by a distance “Δ” extending in the X-direction. In some embodiments, the backside horizontal conducting line782extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP. In some embodiments, the backside horizontal conducting line782extends across the vertical cell boundary119by a distance “Δ” that is more than one eighth of the CPP, one fourth of the CPP, or one half of the CPP. In some embodiments, the distance “Δ” is selected to be sufficiently large to mitigate the design rule violations associated with the pin-connector connection between the backside vertical conducting line778and the backside horizontal conducting line782. In some embodiments, the distance “Δ” is selected to be less than one CPP so that the horizontal gap distance from the vertical cell boundary119to the vertical cell boundary of the adjacent cell is reduced to a minimal distance for mitigating the design rule violations associated with the pin-connector connection. FIG.8is a flow chart of a process800of designing an integrated circuit, in accordance with some embodiments. The process800inFIG.8is explained with reference to the layout diagrams inFIGS.9A-9Cas examples.FIGS.9A-9Care layout diagrams of a cell900, in accordance with some embodiments. As shown inFIGS.9A-9C, the cell900includes backside horizontal conducting lines (981,982,984, and986) in the first backside metal layer BMO and backside vertical conducting lines (972,975, and978) in the second backside metal layer BM1. The via-connector9BVOA (which functions as a pin-connector) connects the backside vertical conducting line978to the backside horizontal conducting line982. InFIG.8, the process800start with the first part805of the design flow. The first part805includes the design operations before the placement and routing of backside conducting lines. Example operations in the first part805of the design flow include floor planning, partitioning, power planning, and placement and routing of various elements at the front side of the substrate. After the process800finishes the first part805of the design flow, the process800proceeds to operation810which conducts auto placement and routing (APR) for various backside conducting lines. Then, after operation810, the process800proceeds to operation820which conducts a design rule check (DRC) for the layout designs of the backside conducting lines. A design rule for layout designs is a geometric constraint imposed on the layout designs to ensure the corresponding circuits based on the layout designs function properly and reliably and the corresponding circuits can also be produced with acceptable yield. The design rule check is conducted to ensure that the layout designs do not violate design rules. If the layout designs of the backside conducting lines pass the design rule check, the process800proceeds to the remaining part895of the design flow. On the other hand, if the layout designs of the backside conducting lines fail to pass the design rule check, the process800proceeds to operation832. One example DRC failure is when the separation spacing between two backside conducting lines becomes too small. Another example DRC failure is when a pin-connector is positioned too close to an edge of a backside conducting line. In operation832, the layout areas near the cell900(which is found to have at least one design rule violation at operation820) are analyzed to determine whether the positon of the cell900can be shifted. If the positon of the cell900can be shifted, then the process800proceeds to operation838to fix design rule violations, and the positon of the cell900is shifted from an original position to an alternative position in a modified layout design. For example, in the modified layout design as shown inFIG.9A, the cell900is shifted from the original position902to the alternative position908. On the other hand, in operation832, if the position of the cell900cannot be shifted, the process800proceeds to operation834. In operation834, the layout areas near the cell900(which are found to have at least one design rule violation at operation820) are analyzed to determine whether the backside horizontal conducting line for supporting pin access can be extended. If the backside horizontal conducting line can be extended, then the process800proceeds to operation838to fix design rule violations, and the backside horizontal conducting line is redesigned as an extended conducting line that is extended across a vertical cell boundary in a modified layout design. For example, in the modified layout design as shown inFIG.9B, the backside horizontal conducting line982(as an extended conducting line) extends across the vertical cell boundary119by a distance “Δ.” On the other hand, in operation834, if the backside horizontal conducting line for supporting pin access cannot be extended, the process800proceeds to operation836. In operation836, the backside vertical conducting line for accessing a circuit node through a pin-connector is redesigned as a local two-dimensional conducting line in a modified layout design, and the process800proceeds to operation838. The local two- dimensional conducting line has a first portion with a first width and has a second portion with a second width that is different from the first width. For example, in the modified layout design as shown inFIG.9C, the backside vertical conducting line978has a first portion978A and a second portion978B. The first portion978A has a first width “Wa,” and the second portion978B has a second width “Wb” which is smaller than the first width “Wa.” Additionally, in the modified layout design as shown inFIG.9C, the backside vertical conducting line975is also modified. In some embodiments, the backside vertical conducting line975is modified to avoid design rule violations caused by the increased first width “Wa” of the first portion978A. In some alternative embodiments, the backside vertical conducting line975is not modified, while the first portion978A is designed with an increased first width “Wa.” In operation836, when the backside vertical conducting line (such as978inFIG.9C) for accessing a circuit node is redesigned as a local two-dimensional conducting line, there is the possibility that the local two-dimensional conducting line may cause design rule violations and the adjacent backside vertical conducting line (such as975inFIG.9C) may need to be modified to mitigate the design rule violations. For example, when the backside vertical conducting line978is changed to a local two-dimensional conducting line inFIG.9C, the backside vertical conducting line975inFIG.9Cis shortened from the backside vertical conducting line975inFIG.9A. In the example flow chart ofFIG.8, because of the possibility of modifying an adjacent backside vertical conducting line, operation836is positioned in the process flow after operations832and834. InFIG.8, after the process800finishes operation838, the process800returns to operation810, and auto placement and routing (APR) are conducted for various backside conducting lines. Then, the process800proceeds to operation820, and the modified layout designs are checked again for design rule violations. The iteration including operations838,810, and820is repeated until the layout design passes the design rule check, then, the process800proceeds to the remaining part895of the design flow. Example operations in the remaining part895of the design flow include clock tree synthesis, RC extraction, timing analysis, signal integrity analysis, verifications, and the like. FIG.10is a flowchart of a method1000of manufacturing an integrated circuit, in accordance with some embodiments. The sequence in which the operations of method1000are depicted inFIG.10is for illustration only; the operations of method1000are capable of being executed in sequences that differ from that depicted inFIG.10. It is understood that additional operations may be performed before, during, and/or after the method1000depicted inFIG.10, and that some other processes may only be briefly described herein. In operation1010of method1000, a first-type active-region structure and a second-type active-region structure are fabricated. In some embodiments, the first-type active-region structure is a p-type active-region structure, and the second-type active-region structure an n-type active-region structure. In some embodiments, the first-type active-region structure is an n-type active-region structure, and the second-type active-region structure a p-type active-region structure. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the p-type active-region structure80pand the n-type active-region structure80nare fabricated atop the substrate50. Examples of the active-region structures fabricated in operation1010include fin structures, nano-sheet structures, and nano-wire structures. In operation1022and operation1024of method1000, gate-conductors and terminal-conductors are fabricated. Each of the gate-conductor and the terminal-conductors intersects the first-type active-region structure and/or the second-type active-region structure above the substrate. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the gate-conductors fabricated in operation1022include the gate-conductors152and158intersecting the p-type active-region structure80pand the n-type active-region structure80n. In the example embodiment, the terminal-conductors fabricated in operation1022include the terminal-conductors132p,135p, and138intersecting the p-type active-region structure80pand the terminal-conductors132n,135n, and138intersecting the n-type active-region structure80n. After operation1022and operation1024, the process flow proceeds to operation1030. In operation1030of method1000, front-side first-layer conducting lines are fabricated. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, after a top insulation layer is fabricated in the front-end-of-line (FEOL) process, the front-side first-layer conducting lines122,124, and126in a first connection layer (such as the first metal layer M0) overlying the top insulation layer are fabricated in operation1030. After operations1010,1022,1024, and1030, the wafer containing the substrate is flipped in operation1040. Then, the process flow proceeds to1050. In operation1050of method1000, via-connectors that pass through the substrate are fabricated. One example of the via-connectors fabricated in operation1050is the via-connector for connecting a gate-conductor at the front side of the substrate to a conducting line at the backside of the substrate. Another example of the via-connectors fabricated in operation1050is the via-connector for connecting a terminal-conductor at the front side of the substrate to a conducting line at the backside of the substrate. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the via-connectors1BVG1,1BVG2, and1BVD1that pass through the substrate50are fabricated in operation1050. After operation1050, the process flow proceeds to operation1060. In operation1060of method1000, backside horizontal conducting lines are fabricated at the backside of the substrate. In some embodiments, one of the backside horizontal conducting lines is fabricated as an extended conducting line that extends across a vertical boundary of a circuit cell by a distance that is less than one CPP. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the backside horizontal conducting lines181,182,184, and186are fabricated in a backside first conducting layer (such as in the first backside metal layer BM0) at the backside of the substrate50. In the example embodiment, the backside horizontal conducting line182extends across the vertical cell boundary119by a distance “Δ” that is less than one CPP. After operation1060, the process flow proceeds to operation1070. In operation1070of method1000, via-connectors are fabricated. One example of the via-connectors fabricated in operation1070is the via-connector for connecting a backside horizontal conducting line with a backside vertical conducting line. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the via-connectors1BV0A,1BV0B, and1BV0C which pass through the backside interlayer dielectric56are fabricated in operation1070. After operation1070, the process flow proceeds to operation1080. In operation1080of method1000, backside vertical conducting lines are fabricated. In some embodiments, one of the backside vertical conducting lines is aligned with a vertical boundary of a circuit cell and is directly connected to one of the backside horizontal conducting lines with a pin-connector. In some embodiments, the backside vertical conducting lines that is aligned with the vertical boundary of the circuit cell is a local two-dimensional conducting line which has a first portion with a first width and has a second portion with a second width that is different from the first width. In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the backside vertical conducting lines172,175, and178are fabricated in a backside first conducting layer (such as in the first backside metal layer BM0). In the example embodiment, the backside vertical conducting line178is aligned with the vertical cell boundary119. The backside vertical conducting line178is conductively connected to the backside horizontal conducting line182through the via-connector1BV0A (which functions as a pin-connector). In the example embodiment as shown inFIGS.4A-4E, the backside vertical conducting line178includes a first portion178A that has a first width “Wa” and a second portion178B that has a second width “Wb.” In the example embodiment as shown inFIGS.2A-2EandFIGS.3A-3C, the gear ratio between the backside vertical conducting lines (in the second backside metal layer BM1) and the contacted poly pitch (CPP) of the gate-conductors is one to one (i.e.,1:1). In some alternative embodiments, the gear ratio between the backside vertical conducting lines (in the second backside metal layer BM1) and the CPP of the gate-conductors is two to three (i.e., 2:3). In still some alternative embodiments, the gear ratio between the backside vertical conducting lines (in the second backside metal layer BM1) and the CPP of the gate-conductors is one to two (i.e., 1:2). Other selections of the gear ratios are also within the contemplated scope of the present disclosure. FIG.11is a block diagram of an electronic design automation (EDA) system1100in accordance with some embodiments. In some embodiments, EDA system1100includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system1100, in accordance with some embodiments. In some embodiments, EDA system1100is a general purpose computing device including a hardware processor1102and a non-transitory, computer-readable storage medium1104. Storage medium1104, amongst other things, is encoded with, i.e., stores, computer program code1106, i.e., a set of executable instructions. Execution of instructions1106by hardware processor1102represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Processor1102is electrically coupled to computer-readable storage medium1104via a bus1108. Processor1102is also electrically coupled to an I/O interface1110by bus1108. A network interface1112is also electrically connected to processor1102via bus1108. Network interface1112is connected to a network1114, so that processor1102and computer-readable storage medium1104are capable of connecting to external elements via network1114. Processor1102is configured to execute computer program code1106encoded in computer-readable storage medium1104in order to cause system1100to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1102is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium1104is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium1104includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium1104includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium1104stores computer program code1106configured to cause system1100(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1104also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium1104stores library1107of standard cells including such standard cells as disclosed herein. In one or more embodiments, storage medium1104stores one or more layout diagrams1109corresponding to one or more layouts disclosed herein. EDA system1100includes I/O interface1110. I/O interface1110is coupled to external circuitry. In one or more embodiments, I/O interface1110includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor1102. EDA system1100also includes network interface1112coupled to processor1102. Network interface1112allows system1100to communicate with network1114, to which one or more other computer systems are connected. Network interface1112includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems1100. System1100is configured to receive information through I/O interface1110. The information received through I/O interface1110includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor1102. The information is transferred to processor1102via bus1108. EDA system1100is configured to receive information related to a UI through I/O interface1110. The information is stored in computer-readable medium1104as user interface (UI)1142. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system1100. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.12is a block diagram of an integrated circuit (IC) manufacturing system1200, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system1200. InFIG.12, IC manufacturing system1200includes entities, such as a design house1220, a mask house1230, and an IC manufacturer/fabricator (“fab”)1250, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1260. The entities in system1200are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1220, mask house1230, and IC fab1250is owned by a single larger company. In some embodiments, two or more of design house1220, mask house1230, and IC fab1250coexist in a common facility and use common resources. Design house (or design team)1220generates an IC design layout diagram1222. IC design layout diagram1222includes various geometrical patterns designed for an IC device1260. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1260to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram1222includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1220implements a proper design procedure to form IC design layout diagram1222. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1222is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1222can be expressed in a GDSII file format or DFII file format. Mask house1230includes data preparation1232and mask fabrication1244. Mask house1230uses IC design layout diagram1222to manufacture one or more masks1245to be used for fabricating the various layers of IC device1260according to IC design layout diagram1222. Mask house1230performs mask data preparation1232, where IC design layout diagram1222is translated into a representative data file (“RDF”). Mask data preparation1232provides the RDF to mask fabrication1244. Mask fabrication1244includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)1245or a semiconductor wafer1253. The design layout diagram1222is manipulated by mask data preparation1232to comply with particular characteristics of the mask writer and/or requirements of IC fab1250. InFIG.12, mask data preparation1232and mask fabrication1244are illustrated as separate elements. In some embodiments, mask data preparation1232and mask fabrication1244can be collectively referred to as mask data preparation. In some embodiments, mask data preparation1232includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1222. In some embodiments, mask data preparation1232includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, mask data preparation1232includes a mask rule checker (MRC) that checks the IC design layout diagram1222that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1222to compensate for limitations during mask fabrication1244, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, mask data preparation1232includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1250to fabricate IC device1260. LPC simulates this processing based on IC design layout diagram1222to create a simulated manufactured device, such as IC device1260. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1222. It should be understood that the above description of mask data preparation1232has been simplified for the purposes of clarity. In some embodiments, data preparation1232includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1222according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1222during data preparation1232may be executed in a variety of different orders. After mask data preparation1232and during mask fabrication1244, a mask1245or a group of masks1245are fabricated based on the modified IC design layout diagram1222. In some embodiments, mask fabrication1244includes performing one or more lithographic exposures based on IC design layout diagram1222. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)1245based on the modified IC design layout diagram1222. Mask1245can be formed in various technologies. In some embodiments, mask1245is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask1245includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask1245is formed using a phase shift technology. In a phase shift mask (PSM) version of mask1245, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1244is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1253, in an etching process to form various etching regions in semiconductor wafer1253, and/or in other suitable processes. IC fab1250is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1250is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. IC fab1250includes fabrication tools1252configured to execute various manufacturing operations on semiconductor wafer1253such that IC device1260is fabricated in accordance with the mask(s), e.g., mask1245. In various embodiments, fabrication tools1252include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein. IC fab1250uses mask(s)1245fabricated by mask house1230to fabricate IC device1260. Thus, IC fab1250at least indirectly uses IC design layout diagram1222to fabricate IC device1260. In some embodiments, semiconductor wafer1253is fabricated by IC fab1250using mask(s)1245to form IC device1260. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1222. Semiconductor wafer1253includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1253further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Details regarding an integrated circuit (IC) manufacturing system (e.g., system1200ofFIG.12), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference. An aspects of the present disclosure relates to an integrated circuit. The integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate, a front-side first-layer conducting line in a first connection layer above the substrate, and a plurality of gate-conductors extending in a second direction below the first connection layer. Two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”). The integrated circuit also includes a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction. Each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region, and a distance between the first vertical boundary and the second vertical boundary along the first direction is less than or equal to three CPPs. The integrated circuit also includes a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, and a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across the first vertical boundary of the circuit cell. The backside vertical conducting line is aligned with the first vertical boundary. Another aspect of the present disclosure relates an integrated circuit. The integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate, a front-side first-layer conducting line in a first connection layer above the substrate, and a plurality of gate-conductors extending in a second direction below the first connection layer. Two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”). The integrated circuit also includes a circuit cell having a first vertical boundary and a second vertical boundary extending in the second direction perpendicular to the first direction. Each of the first vertical boundary and the second vertical boundary crosses at least one boundary isolation region. The integrated circuit also includes a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, and a pin-connector for the circuit cell directly connected between the backside horizontal conducting line and the backside vertical conducting line at an overlap region between the backside horizontal conducting line and the backside vertical conducting line. The backside vertical conducting line has a first portion covering the overlap region and a second portion outside the overlap region. A first width of the first portion along the first direction is larger than a second width of the second portion along the first direction. Still another aspect of the present disclosure relates to a method. The method includes fabricating a first-type active-region structure and a second-type active-region structure extending in a first direction on a substrate, and fabricating a plurality of gate-conductors extending in a second direction perpendicular to the first direction. Each gate-conductor intersects the first-type active-region structure and/or the second-type active-region structure above the substrate. Two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (CPP). The method also includes fabricating a backside horizontal conducting line extending in the first direction in a backside first conducting layer below the substrate, fabricating a pin-connector that is connected to the backside horizontal conducting line, and fabricating a backside vertical conducting line extending in the second direction in a backside second conducting layer below the backside first conducting layer, The backside vertical conducting line is aligned with a first vertical boundary of a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line at an overlap region between the backside horizontal conducting line and the backside vertical conducting line. In the method, fabricating the backside horizontal conducting line includes fabricating the backside horizontal conducting line as an extended conducting line that extends across the first vertical boundary of the circuit cell by a distance that is less than one CPP. It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof. | 81,788 |
11942470 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification. Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Reference throughout the specification to “one embodiment,” “an embodiment,” or “some embodiments” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” or “in some embodiments” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments. In this document, the term “coupled” may also be termed as “electrically coupled”, and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. Furthermore, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used throughout the description for ease of understanding to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around”, “about”, “approximately” or “substantially” shall generally refer to any approximate value of a given value or range, in which it is varied depending on various arts in which it pertains, and the scope of which should be accorded with the broadest interpretation understood by the person skilled in the art to which it pertains, so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “approximately” or “substantially” can be inferred if not expressly stated, or meaning other approximate values. FIG.1is a schematic layout diagram100of an integrated circuit (IC), in accordance with some embodiments of the present disclosure. The layout diagram100is arranged in rows including several rows R[0], R[1], R[2], . . . , and R[n]. The rows R[0], R[1], R[2], . . . , and R[n] extend in an X direction, and stack in a Y direction sequentially. Cells (which are shown inFIG.2) are disposed in various rows R[0], R[1], R[2], . . . , and R[n] for designing corresponding circuits of the IC, in some embodiments. Relative to the Y direction, various cells in the rows R[0], R[1], R[2], . . . , and R[n] have respective heights. For example, as illustrated inFIG.1, one cell in the row R[0] has a height H0, which is only one height labeled inFIG.1for simplicity of illustration. In some embodiments, the heights are referred to as cell heights, which are also equal to heights of the corresponding rows. In some other embodiments, at least one of the height of the rows R[0], R[1], R[2], . . . , and R[n] is different from the others. In some alternative embodiments, at least two of the heights of the rows R[0], R[1], R[2], . . . , and R[n] are the same. In some embodiments, the layout diagram100represents an initial layout diagram according to one or more methods of generating a layout diagram. In some other embodiments, the IC including the semiconductor device is fabricated based on a larger layout diagram which includes the layout diagram100. Reference is now made toFIG.2.FIG.2is a schematic layout diagram200of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagram200is a zoomed-in view of an area120in the layout diagram100shown inFIG.1. The layout diagram200with respect to the embodiments ofFIG.1, like elements inFIG.2are designated with the same reference numbers for ease of understanding. For simplicity of illustration, only few rows R[0] and R[1] and few cells C11, C12and C21are shown in the layout diagram200. For illustration inFIG.2, the cells C11and C12are arranged in the row R[1], and are arranged next to each other with respect to the X direction. The cell C21is arranged in the row R[2], and abuts the cell C11with respect to the Y direction. Various cells C11, C12and C21in the layout diagram200are utilized for the design of corresponding circuits, with a consideration of circuit performance, circuit power and a manufacturing process. In some embodiments, the cells C11, C12and C21are utilized from a standard cell library (which is a standard cell library2062discussed with reference toFIG.20). The cells C11, C12and C21have the same cell heights that are equal to the heights of the rows R[1]-R[2]. In some other embodiments, the cells C11, C12and C21are utilized from respective cell libraries, and have respective cell heights that are equal to the corresponding heights of the rows R[1]-R[2]. With reference toFIG.2, the layout diagram200further includes several patterns which are patterned as “LFZ”. These patterns LFZ are arranged along boundaries of the rows R[1]-R[2] in the X direction. Specifically, the patterns LFZ are arranged at each boundaries CB1, CB2and CBn of the rows R[1]-R[2], and are arranged alternatively and separated from each other. Alternatively stated, the patterns LFZ are arranged around a top boundary CBn and a bottom boundary CB1of the cell C21, and also arranged around top boundaries CB1and bottom boundaries CB2of the cells C11and C12. In some embodiments, the patterns LFZ are utilized to design an arrangement of via patterns. For example, with reference toFIG.2, vias211and212in the cell C11are separated from each other by one pattern LFZ, and the via211in the cell C11is spaced apart from a via221in the cell C21by at least one pattern LFZ. In some embodiments, the via patterns are utilized to form vias in the semiconductor device. The vias include gate vias and conductive vias, as discussed in more detail in the following embodiments. By following at least one guideline, the via patterns are forbad to be placed in the patterns LFZ. As such, in the corresponding semiconductor device, no vias are formed at the regions where the patterns LFZ are disposed. In various embodiments, some guidelines are provided in following paragraphs of the present disclosure for demonstrating when and/or where to arrange or form the vias in the semiconductor device. Reference is now made toFIGS.3A-3B.FIGS.3A-3Bare schematic layout diagrams of a semiconductor device300, in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device300is fabricated based on the layout diagram200. The semiconductor device300with respect to the embodiments ofFIG.2, like elements inFIGS.3A-3Bare designated with the same reference numbers for ease of understanding. For simplicity of illustration, only a portion of the semiconductor device300is shown inFIGS.3A-3B, and only few elements are labeled inFIGS.3A-3B. For example,FIG.3Aillustrates the cell C11corresponding to the cell C11inFIG.2and a part of a cell C01.FIG.3Billustrates the cell C11. The cell C01abuts the cell C11and is arranged in another row (which is R[0] shown inFIG.1). As illustrated inFIG.3A, a front side of the semiconductor device300is illustrated. The semiconductor device300includes gates311,312and313patterned as “POLY”, conductive segments321,322and323patterned as “MD”, gate via341patterned as “VG”, contact via331patterned as “VD”, and signal rails351,352,353and354patterned as “M0”. The gates311-313are formed across active areas (not labeled inFIG.3A) which is patterned as “AA”. The gates311-313extend along the Y direction. The conductive segments321-323are formed above the active areas and extend along the Y direction. The conductive segments are referred to as MD segments hereinafter. In some embodiments, the gates311-313correspond to gate terminals of respective transistors. The MD segments321-323correspond to source/drain terminals of respective transistors. In some other embodiments, the gate311and the adjacent MD segments321and323correspond to a same transistor. The active areas are symbol layers where a main part of the semiconductor device300disposed, rather than physical layers, in some embodiments. In some embodiments, the active areas are polysilicon. In some embodiments, the active areas are made of p-type doped material. In some other embodiments, the active areas are made of n-type doped material. In various embodiments, the active areas are configured to form channels of transistors. In some other embodiments, the active areas are fin-shaped active regions and are configured to form fin structures for forming fin field-effect transistors (FinFET). The gate via341is disposed above the active areas and is coupled between the gate311and the signal rail352that is disposed in a metal-zero (M0) layer above the active areas. In some embodiments, the gate via341and other gate vias discussed with the following embodiments of the present disclosure correspond to vias that are coupled between the corresponding gate terminals and metal rails formed in the M0 layer. The contact via331is disposed above the active areas and is coupled between the MD segment322and the signal rail353that is disposed in the M0 layer. In some embodiments, the contact via331and contact gate vias discussed with the following embodiments of the present disclosure correspond to vias that are coupled between the corresponding source/drain terminals and metal rails formed in the M0 layer. The signal rails351,352,353and354are disposed in the M0 layer. The signal rails351-354extend along the X direction. In some other embodiments, the signal rails351-354are configured to couple data signals to the corresponding transistors. As illustrated inFIG.3B, a back side of the semiconductor device300is illustrated. The back side is opposite to the front side. The semiconductor device300further includes backside vias361patterned as “VB”, and backside power rails371and372patterned as “BM0”. The backside via361is disposed above the back side of the semiconductor device300, which is also below the front side of the semiconductor device300including, for example, the active areas and the M0 layer. The backside via361is coupled between the MD segment321and the backside power rail371that is disposed in a backside metal-0 (BM0) layer. With reference toFIG.3B, the BM0 layer is above the backside via361. The backside power rails371and372are disposed in the BM0 layer. The backside power rails371and372extend along the X direction. In some other embodiments, the backside power rails371and372are configured to transmit power signals. For example, with reference toFIG.3B, the backside power rail371is coupled to a first reference voltage VSS, and is configured to receive the voltage signal VSS and couple the voltage signal VSS to the corresponding transistors. The backside power rail372is coupled to a second reference voltage VDD, and is configured to receive the voltage signal VDD and couple the voltage signal VDD to the corresponding transistors. In some embodiments, with reference toFIGS.3A-3B, with respect to the direction Y, widths of the signal rails351-354are the same, and widths of the backside power rails371-372are the same. The widths of the signal rails351-354are smaller than the widths of the backside power rails371-372. In some approaches, a semiconductor device including backside power rails have cells. These cells abut to each other without overlapping with a power rail in a front side of a layout view. As such, at least two vias disposed on two adjacent signal rails of these two abutting cells are arranged adjacent and close to each other. In such case, these two vias are hard to be fabricated with limited manufacturing techniques. Even these two vias are fabricated by chance, the corresponding data signals transmitted therebetween are interfered to each other. Compared to the above approaches, in the embodiments of the present disclosure, for example with reference toFIGS.2-3B, the backside power rails371-372are included in the semiconductor device300that includes the cells C11and C21. In a layout view, by arranging the forbidden regions patterned as LFZ inFIG.2, the contact vias211-212of the cell C11and the contact vias221-222of the cell C21disposed in two adjacent signal rails are separated from each other by at least a distance D1, D2or D3. Thereby, the contact vias are not too close to each other, and are easy to be fabricated. Reference is now made toFIGS.4A-4B.FIGS.4A-4Bare cross sectional view of the semiconductor device300shown inFIGS.3A-3B, in accordance with some embodiments of the present disclosure.FIG.4Ais a cross-sectional view along a line A-A′ ofFIG.3A.FIG.4Bis a cross-sectional view along a line C-C′ ofFIG.3A. For ease of understanding, the embodiments with respect toFIG.4Aare discussed with reference toFIG.4B, and only illustrates some structures that are associated with the corresponding structures shown inFIGS.3A-3Bas an exemplary embodiment. The semiconductor device300with respect to the embodiments ofFIGS.3A-3B, like elements inFIGS.4A-4Bare designated with the same reference numbers for ease of understanding. As illustrated inFIG.4A, the MD segments321and322are respectively disposed on epitaxy structures421and422, and silicide layers411and412are respectively disposed over therebetween. The MD segment321, the silicide layer411and the epitaxy structure421are spaced apart from the MD segment322, the silicide layer412and the epitaxy structure422by an isolation structure431. A dielectric structure441is filled between the MD segments321and322, the epitaxy structures421and422and the isolation structure431. In some embodiments, the epitaxy structures421and422correspond to the active areas illustrated inFIG.3A. In some other embodiments, the epitaxy structures421and422include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. In some embodiments, the silicide layers411and412cover tops of the epitaxy structures421and422, respectively. In some other embodiments, the silicide layers411and412are embedded in the epitaxy structures421and422, respectively. In various embodiments, the epitaxy structures421and422include CoSi2, TiSi2, WSi2, NiSi2, MoSi2, TaSi2, PtSi, or the like. In some embodiments, the isolation structure431is a shallow trench isolation (STI) structure, suitable isolation structure, combinations thereof or the like. In some other embodiments, the isolation structure431is made of oxide (e.g., silicon oxide) or nitride (e.g., silicon nitride). In some embodiments, the dielectric structure441is made of high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials. With reference toFIG.4A, an interlayer dielectric (ILD) layer451is disposed above the MD segments321and322and the dielectric structure441. A dielectric structure461is filled between the signal rails351,352,353and354, and is also indicated as the M0 layer in some embodiments. The contact via331is disposed in the ILD layer451, and contacts both of the MD segment322and the signal rail353. In some embodiments, the ILD layer451includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. With reference toFIG.4A, a backside ILD layer471is disposed below the epitaxy structures421and422, the isolation structure431and the dielectric structure441. The backside power rail371is disposed below the backside ILD layer471and the backside via361. A dielectric structure (not shown) is filled around the backside power rail371, and is also indicated as the BM0 layer in some embodiments. The backside via361is disposed in the backside ILD layer471, and contacts both of the MD segment321and the backside power rail371. In some embodiments, the backside ILD layer471and the ILD layer451include the same materials. Compared toFIG.4A, in the cross sectional view of the semiconductor device300shown inFIG.4B, a spacer481is disposed on opposite sidewalls of the gate311, and between the MD segment321and the MD segment323which are disposed above the epitaxy structures421and423respectively. The dielectric structure441is filled between the gates311-313, the MD segments321and323, the epitaxy structures421and423, and the spacer481. The gate via341is disposed in the ILD layer451, and contacts both of the gate311and the signal rail352. In some embodiments, the spacer481includes SiO2, Si3N4, SiOxNy, SiC, SiCN films, SiOC, SiOCN films, and/or combinations thereof. Reference is now made toFIG.5.FIG.5is a schematic layout diagram500of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagram500is a zoomed-in view of the cell C11in the layout diagram200shown inFIG.2. In some embodiments, the layout diagram500is utilized to fabricate the semiconductor device300inFIGS.3A-4B. In various embodiments, the layout diagram500is utilized to fabricate the semiconductor device1700inFIGS.17-18C. The correspondence between a given layout diagram feature formed based on the given layout diagram feature, a same reference designator is used in each of the layout diagram and structure depictions, as discussed below. For simplicity of illustration, the MD segments are not shown inFIG.5. The layout diagram500with respect to the embodiments ofFIGS.2-4B, like elements inFIG.5are designated with the same reference numbers for ease of understanding. As illustrated inFIG.5, the cell C11is arranged in the row R[1] that is arranged between the rows R[0] and R[2]. In the cell C11, multiple gates311,312,314,315and316are disposed, and multiple signal rails351,352,355and356are disposed. The layout diagram500further includes several forbidden regions patterned as DLFZ and GLFZ, which are discussed in detailed with reference toFIGS.6A-6B. These forbidden regions are arranged along the boundaries of the rows R[0]-R[1]. Alternatively stated, the forbidden regions are arranged along cell boundaries including a top cell boundary CB1and a bottom cell boundary CB2. In some embodiments, the forbidden regions inside the cell C11are some separated regions that are included in the active areas of the cell C11as discussed with reference toFIGS.3A-4B. In some other embodiments, the forbidden regions outside the cell C11are some other separated regions of active areas that are included in other cells (not shown). These other cells abut the cell C11, and are arranged in the corresponding row R[0] and R[2]. These other cells include, for example, the cell C21in the row R[2] shown inFIG.2, and the cell C01in the row R[0] shown inFIG.3A. To implement the semiconductor device300discussed with referenceFIGS.3A-4B, whether to arrange the vias, including the gate vias and the contact vias, is determined. Specifically, where to arrange the vias in specific regions in the corresponding cell is determined, based on the forbidden regions patterned as DLFZ and GLFZ. In some embodiments, a first guideline is provided to determine whether to arrange the contact vias. For illustration inFIG.5, when the first guideline is followed, the contact vias are not arranged in the forbidden regions patterned as DLFZ. The first guideline is discussed below with reference to embodiments ofFIG.6A. In some embodiments, a second guideline is provided to determine whether to arrange the gate vias. For illustration inFIG.5, when the second guideline is followed, the gate vias are not arranged in the forbidden regions patterned as GLFZ. The second guideline is discussed below with reference to embodiments ofFIG.6B. Reference is now made toFIGS.6A-6B.FIGS.6A-6Bare schematic layout diagrams600A-600B of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagrams600A and600B are alternative embodiments of the layout diagram500shown inFIG.5. The layout diagram600A or600B has configurations similar to that of the layout diagram500as illustrated inFIG.5, and similar detailed description is therefore omitted. The layout diagrams600A and600B with respect to the embodiments ofFIG.5, like elements inFIGS.6A-6Bare designated with the same reference numbers for ease of understanding. Compared toFIG.5, in the layout diagram600A shown inFIG.6A, the forbidden regions patterned as GLFZ are not illustrated. In the layout diagram600A, the forbidden regions patterned as DLFZ are disposed along the cell boundaries CB1-CB2, and are separated from each other. Alternatively stated, these forbidden regions are castle-like shaped and arranged regularly along the cell boundaries CB1-CB2. For example, with reference toFIG.6A, the forbidden regions611,612,613,614and615are disposed abutting the cell boundary CB1, and some others without labeling are disposed abutting the cell boundary CB2. With respect to the cell boundary CB1, the forbidden regions611and612are disposed diagonally, and the forbidden regions613and614are also disposed diagonally, and so on. As illustrated inFIG.6A, the forbidden regions611,613and615are disposed outside the cell C11, and bottom sides thereof are located at the cell boundary CB1. The forbidden regions612and614are disposed inside the cell C11, and top sides thereof are located at the cell boundary CB1. Furthermore, with respect to the Y direction, the forbidden region612abuts a region621. The region621is included in the active area in the abutted cell (not shown), and spaces the forbidden regions611and613apart. Similarly, the forbidden region614abuts a region622. The region622is included in the active area in the abutted cell, and spaces the forbidden regions613and615apart. Regarding the first guideline, there are some conditions to be followed in the first guideline. When these conditions are satisfied, the contact vias are allowed to be formed with a high density in at least two abutting cells. One condition of the first guideline is that there is a cell abutting a target cell, for generating another circuit that is other than the circuit generated based on the target cell. For illustration ofFIG.6A, the cell C11is the target cell, and another cell (not shown) abuts the cell C11. Another condition of the first guideline is that at least one contact via is arranged in at least one region that abuts the active region in the target cell. For illustration ofFIG.6A, a contact via (not shown) is arranged in the region621that abuts a region in the cell C11, which is indicated as the forbidden region612. Similarly, a contact via (not shown) is arranged in the region622that abuts a region in the cell C11, which is indicated as the forbidden region614. When the above conditions are satisfied, at least one contact via is allowed to be arranged in the active region in the target cell, excluding the region that abuts the region in the abutted cell arranged with the contact via. For illustration ofFIG.6A, when the contact vias are arranged in the regions621and622, the contact vias531,532,533and534in the cell C11are arranged outside the forbidden regions612and614that abut the regions621and622. Accordingly, no contact vias are arranged in the forbidden regions612and614. Aforementioned configurations of the contact vias in the abutted cells and the forbidden regions patterned as DLFZ are regarded as the first guideline, in some embodiments. When the first guideline is followed, the contact vias531-533are disposed in the cell C11as illustrated inFIG.6A. When the abutted cell is substituted with the cell C11as the target cell, in some embodiments, the first guideline is also provided, to determine where to arrange the contact vias in such abutted cell. For example, with reference toFIG.6A, when the contact via532is disposed in a region that abuts the forbidden region611, no contact vias are allowed to be disposed in the forbidden region611. Similarly, when the contact vias533and534are respectively disposed in regions that abut the forbidden regions613and615, the contact vias are forbade being disposed in the forbidden regions613and615. Compared toFIG.5, in the layout diagram600B shown inFIG.6B, the forbidden regions patterned as DLFZ are not illustrated. Compared toFIG.6A, in the layout diagram600B shown inFIG.6B, the forbidden regions patterned as GLFZ are illustrated, substituted with the forbidden regions patterned as DLFZ. The forbidden regions in FIG.6B have configurations similar to that of the forbidden regions inFIG.6A, and similar detailed description is therefore omitted. As illustrated inFIG.6B, the forbidden regions631,633and635are disposed outside the cell C11, and top sides thereof are located at the cell boundary CB2. The forbidden regions632and634are disposed inside the cell C11, and bottom sides thereof are located at the cell boundary CB2. Furthermore, the regions641and642are included in the active area in another abutted cell (not shown), and respectively space the forbidden regions631and633apart, and the forbidden regions633and635apart. Regarding the second guideline, there are some conditions to be followed in the second guideline. When these conditions are satisfied, the gate vias are allowed to be formed with a high density in at least two abutting cells. Similar to the conditions followed by the first guideline, the conditions of the second guideline include that there are at least two abutting cells for generating respective circuits, and that at least one gate via is arranged in at least one region of one cell that abuts the active region of the other one cell. For illustration ofFIG.6B, a cell (not shown) and the cell C11abut to each other. In addition, a gate via (not shown) is arranged in the region641that abuts a region in the cell C11, which is indicated as the forbidden region632. Similarly, a gate via (not shown) is arranged in the region642that abuts a region in the cell C11, which is indicated as the forbidden region634. When the above conditions are satisfied, at least one gate via is allowed to be arranged in the active region in one of the abutting cells, excluding the region that abuts the region in the other one arranged with that gate via. For illustration ofFIG.6B, when the gate vias are arranged in the regions641and642, the gate via341in the cell C11is arranged outside the forbidden regions631and632that abut the regions641and642. Accordingly, gate contact vias are not arranged in the forbidden regions631and632. Aforementioned configurations of the gate vias in the abutted cells and the forbidden regions patterned as GLFZ are regarded as the second guideline, in some embodiments. When the second guideline is followed, the gate via341is disposed in the cell C11as illustrated inFIG.6B. When the arrangement of the gate vias in the cell C11is determined, in some embodiments, the second guideline is also provided to determine where to arrange the gate vias in the abutted cells. For example, with reference toFIG.6B, when the gate via341is disposed in a region that abuts the forbidden region635, no gate vias are allowed to be disposed in the forbidden region635. Compared to the above approaches that vias are arranged adjacent and close to each other in two abutting cells, in the embodiments of the present disclosure, for example with reference toFIGS.5-6B, in a layout view of the layout diagrams500-600B, by arranging the forbidden regions patterned as DLFZ and/or GLFZ, it avoids that the gate vias or the contact vias in these abutting cells are placed too close to each other, and it further eases the difficulty of the manufacturing. In some embodiments, the configurations of the forbidden regions patterned as DLFZ and GLFZ inFIGS.5-6Bare defined by, for illustration inFIGS.7A-7D, the cell geometry. The cell geometry includes, for example, a cell height, amounts of the gates and signal rails, and intervals between two adjacent gates and between two adjacent signal rails. Reference is now made toFIGS.7A-7D.FIGS.7A-7Dare schematic layout diagrams700A-700D of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagrams700A-700D are alternative embodiments of the layout diagram500shown inFIG.5or the layout diagrams600A-600B shown inFIGS.6A-6B. For simplicity of illustration, only few elements are shown inFIGS.7A-7D. As illustrated inFIG.7A, a cell (not labeled) is included in the layout diagram700A. With respect to the Y direction, the cell has a cell height H1that is substantially equal to a height of a corresponding row where such cell is disposed. The height H1is also referred to as a cell height H1. In the cell, multiple gates711-712are disposed, and are separated from each other by a gate pitch P1, with respect to the X direction. In the cell, also disposed multiple signal rails (not labeled) having the same width, with respect to the Y direction. These signal rails are separated from each other by a signal rail pitch P2, with respect to the Y direction. The signal rail pitch P2is indicated as a M0 pitch hereinafter. In some embodiments, the cell height H1is substantially equal to four times to fifth times of the M0 pitch P2. As such, about four signal rails are disposed in one cell. In some embodiments, the forbidden regions patterned as DLFZ have sizes that are the same. In some other embodiments, with reference toFIG.7A, with respect to the X direction, a length L1of one forbidden region731is substantially equal to one gate pitch P1(i.e., L1=1*P1). With respect to the Y direction, a width W1of the forbidden region731is substantially in a range one M0 pitch P2to two times of the M0 pitch P2(i.e., W1=1*P2˜2*P2). Therefore, with such configurations, when the forbidden region731or732is arranged along a top or a bottom boundary of the cell, such forbidden region731or732is partially overlapped with one signal rail in a layout view. Regarding the first guideline, arrangement and distribution of the forbidden regions with the above configurations are defined, in some embodiments. Such arrangement and distribution of the forbidden regions discussed with reference toFIGS.7A-7Bare indicated as a first constraint. For example, with reference toFIG.7A, in one cell, at least two forbidden regions731and732are arranged between two adjacent gates711and712. Meanwhile, no other forbidden regions are arranged between other two adjacent gates including one of the gates711and712. In another example, with reference toFIG.7B, at least two forbidden regions731,732and733are arranged between the gates711and712, and the forbidden regions731and733are stacked with respect to the Y direction. Therefore, with the above arrangement and distribution, two adjacent gates711-712are arranged with at least two forbidden regions731-733therebetween. Compared toFIG.7A, in the layout diagram700C shown inFIG.7C, the forbidden regions patterned as DLFZ have different arrangement and distribution. As discussed above, when the first guideline is followed, the contact vias has a distribution with a high density in at least two abutting cells. For example, with reference back toFIG.2, in the cells C11and C21, especially at an area (not labeled) that is across the cell boundary CB1thereof, the contact vias211-212and221-222have a high density configuration. In such region, a distance D1between the contact vias211and221is substantially equal to two times of the gate pitch P1(i.e., D1=2*P1). These two contact vias211and221are separated from each other by one forbidden region patterned as LFZ, with respect to the Y direction. A distance D2between the contact vias211and212is substantially equal to two times of the M0 pitch P2(i.e., D2=2*P2). These two contact vias211and212are separated from each other by another forbidden region, with respect to the X direction. A distance D3between the contact vias211and222is substantially equal to a square root of a sum of the gate pitch P1squared and the M0 pitch P2squared (i.e., D3=√{square root over (P12+P22)}). These two contact vias are separated from each other and arranged diagonally. In some embodiments, the vias212and222is spaced apart by the distance D3. Regarding the first guideline, another arrangement and distribution of the forbidden regions are defined, in some embodiments. Such arrangement and distribution of the forbidden regions discussed with reference toFIGS.7C-7Dare indicated as a second constraint. For example, with reference toFIG.7C, in one cell, at least one forbidden region752is arranged between two adjacent gates711and712. Meanwhile, at least one forbidden region751or753is also arranged between other two adjacent gates including one of the gates711and712. In another example, with reference toFIG.7D, at least one forbidden regions751,752,753and754are arranged between every two gates711and712, and the forbidden regions753and754are stacked with respect to the Y direction. Therefore, with the above arrangement and distribution, every two adjacent gates711-712are arranged with at least one forbidden regions751-754therebetween. In some embodiments, the forbidden regions patterned as GLFZ shown inFIGS.5and6Band the forbidden regions patterned as DLFZ have similar configurations as discussed above with reference toFIGS.7A-7D. In some embodiments, the forbidden regions patterned as GLFZ shown inFIGS.5and6B, regarding the second guideline, have similar arrangement and distribution as the forbidden regions patterned as DLFZ. Alternatively stated, the second guideline includes similar constraints, including the first and the second constraints, in the first guideline, as discussed above with reference toFIGS.7A-7BandFIGS.7C-7Drespectively. The difference between the forbidden regions patterned as GLFZ and that patterned as DLFZ is a relative placement between the forbidden regions and the gates. For example, with reference toFIG.6B, in the cell C11, the forbidden regions632and634are overlapped with the gates315and312. A middle of each of the forbidden regions632and634are substantially aligned with the gates315and312, with respect to the Y direction. On the other hand, with reference toFIG.6A, in the cell C11, the forbidden regions612and614are arranged between the adjacent gates314-315and between the adjacent gates311-312. Reference is now made toFIG.8.FIG.8is a schematic layout diagram800of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagram800is an alternative embodiment of the layout diagrams200or500shown inFIG.2or5. In various embodiments, the layout diagram800is utilized to fabricate the semiconductor device300inFIGS.3A-4Bor the semiconductor device1700inFIGS.17-18C. The correspondence between a given layout diagram feature formed based on the given layout diagram feature, a same reference designator is used in each of the layout diagram and structure depictions, as discussed below. For simplicity of illustration, only few elements are labeled inFIG.8. The layout diagram800with respect to the embodiments ofFIGS.2-5, like elements inFIG.8are designated with the same reference numbers for ease of understanding. As illustrated inFIG.8, two single height cells C11and C01are included in the layout diagram800. The cell C11is defined between the cell boundaries including CB1and CB2. In the cell C11, active areas A1and A2are arranged and include various doped materials. In some embodiments, regarding the single height cell C11, the cell boundary CB1is defined corresponding to the active area A1, and another boundary CB2is defined corresponding to the active area A2. Similarly, the cell C01is defined between the cell boundaries including CB2and CB3. In the cell C01, active areas A3and A4are arranged and include various doped materials. In some embodiments, regarding the single height cell C01, the cell boundary CB2is defined corresponding to the active area A3, and another boundary CB3is defined corresponding to the active area A. In some embodiments, the active area A1is made of n-type doped material, and a cell boundary CB1of the cell C11is located adjacent to the active area A1. In some embodiments, the active area A2is made of p-type doped material, and a cell boundary CB2of the cell C11is located adjacent to the active area A2. Furthermore, the cell boundary CB2of the cell C01is also located adjacent to the active area A3that is made of p-type doped material. In some embodiments, the active area A4is made of n-type doped material, and a cell boundary CB3of the cell C01is located adjacent to the active area A4. In some embodiments, with reference toFIG.8, with respect to the Y direction, the cell C11has a cell height H2, and the cell C01has a cell height H3. In some embodiments, cell C11corresponds to the cell C11illustrated in at leastFIGS.5-7B. In some other embodiments, the cell height H2is equal to the cell height H1. In various embodiments, the cell heights H1-H3are the same. In some embodiments, at least one of the cell heights H1-H3is different from the others. To implement various semiconductor devices included in an IC, the layout diagrams as discussed above with reference toFIGS.1,2,5,6A-6B,7A-7D and8are used or modified to be used, as illustrated by the non-limiting examples discussed below with respect toFIGS.9A-14B. These semiconductor devices correspond to the semiconductor device300discussed with referenceFIGS.3A-4Bor the semiconductor devices1700discussed with referenceFIGS.17-18C. In the various embodiments discussed below, the semiconductor device or the IC of the present disclosure is implemented through the use of layout diagrams, including the single height cell, depicted inFIGS.9B-9D,10B-10D,11B-11D,12B-12D,13B-13D and14Bthat correspond to circuit diagrams depicted inFIGS.9A,10A,11A,12A,13A and14A, as indicated. It is noted that these layout diagrams merely illustrate a front side of the corresponding semiconductor device, and are provided when the guidelines with various constraints are followed as discussed above with reference toFIGS.5-7D. Reference is now made toFIG.9A.FIG.9Ais a circuit diagram of an IC900A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC900A is used as one unit cell/circuit for implementing an inverter. For illustration of the IC900A, a gate terminal of a PMOS transistor P1is coupled to a gate terminal of a NMOS transistor N1as indicated by connection I. In some embodiments, the connection I is indicated as an input terminal, for providing a control signal to both of the PMOS transistor P1and the NMOS transistor N1. A source/drain terminal of the PMOS transistor P1is coupled to a node A1. A source/drain terminal of the PMOS transistor P1is coupled to a node A2. A source/drain terminal of the NMOS transistor N1is coupled to a node B1. A source/drain terminal of the NMOS transistor N2is coupled to a node B2. The node A1is further coupled to a power rail referenced as VDD. The nodes B1is further coupled to another power rail referenced as VSS. The node A2is further coupled to the node B2as indicated by a connection ZN. To implement the IC900A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIGS.9B-9D. For clarification of demonstrating various forbidden regions patterned as DLFZ and GLFZ, the following layout diagrams900B-900D inFIGS.9B-9Dhave separate diagrams A and B for illustrating the patterns DLFZ and GLFZ, respectively. In addition, for simplicity of illustration, similar elements are not repeatedly labeled in the layout diagrams900B-900D, and similar detailed description is therefore omitted. FIG.9Bis a layout diagram900B of the IC900A inFIG.9A, in accordance with some embodiments of the present disclosure. The layout diagram900B is provided in diagram A ofFIG.9Bby following the first guideline with the first constraint. The layout diagram900B is also provided in diagram B ofFIG.9Bby following the second guideline with the first constraint. As illustrated in diagram A ofFIG.9B, a gate911is arranged as the gate terminals of PMOS transistor P1and NMOS transistor N1inFIG.9A. MD segments921,922and923are arranged as sources/drains of PMOS transistor P1or NMOS transistor N1inFIG.9A. The gate911and the MD segments921and922together correspond to the PMOS transistor P1. The gate911and the MD segments923and922together correspond to the NMOS transistor N1. In such embodiments, the PMOS transistor P1share the MD segment922, which corresponds to the PMOS transistor P1being coupled at the nodes A2and B2together illustrated inFIG.9A. It also corresponds to the nodes A2and B2being coupled between the connection ZN illustrated inFIG.9A. A contact via931is arranged. Signal rails951and952are arranged. The contact via931couples the MD segment922to the signal rail952. A gate via941is arranged. The gate via941couples the gate911to the signal rail951, which corresponds to the gate of the PMOS transistor P1or NMOS transistor N1being coupled between the connection I as discussed above with respect toFIG.9A. Backside vias (not shown) are arranged at a back side of the same cell illustrated in the layout diagram900B. One of the backside vias couples the MD segment921to a backside power rail (not shown), which corresponds to the node A1being coupled to the power rail VDD as discussed above with respect toFIG.9A. The other one of the backside vias (not shown) couples the MD segment923to a backside power rail (not shown), which corresponds to the node B1being coupled to the power rail VSS as discussed above with respect toFIG.9A. The forbidden regions961,962,963and964are arranged. The forbidden regions961-964correspond to the forbidden regions611-615as discussed above with reference toFIGS.5-6A. The arrangement and distribution of the forbidden regions961-964further correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no contact vias are formed in the forbidden regions961-964. Compared to diagram A ofFIG.9B, in the layout diagram900B shown in diagram B ofFIG.9B, the forbidden regions971,972,973,974,975and976are arranged. The forbidden regions971-976correspond to the forbidden regions631-636as discussed above with reference toFIGS.5and6B. The arrangement and distribution of the forbidden regions971-976correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no gate vias are formed in the forbidden regions971-976. FIG.9Cis a layout diagram900C of the IC900A inFIG.9A, in accordance with some embodiments of the present disclosure. The layout diagram900C is provided in diagram A ofFIG.9Cby following the first guideline with the second constraint. The layout diagram900C is also provided in diagram B ofFIG.9Bby following the second guideline with the second constraint. Compared to diagram A ofFIG.9B, in the layout diagram900C shown in diagram A ofFIG.9C, the forbidden regions961-964are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions961-964correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no contact vias are formed in the forbidden regions961-964. Compared to diagram B ofFIG.9B, in the layout diagram900C shown in diagram B ofFIG.9C, the forbidden regions971-976are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions971-976correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no gate vias are formed in the forbidden regions971-976. FIG.9Dis a layout diagram900D of the IC900A inFIG.9A, in accordance with some embodiments of the present disclosure. The layout diagram900D is provided in diagram A ofFIG.9Dby following the first guideline with the first constraint. The layout diagram900D is also provided in diagram B ofFIG.9Dby following the second guideline with the second constraint. The layout diagram900D in diagram A ofFIG.9Dand the layout diagram900B in diagram A ofFIG.9Bare the same, followed by the first guideline with the first constraint. The layout diagram900D in diagram B ofFIG.9Dand the layout diagram900C in diagram B ofFIG.9Care the same, followed by the second guideline with the second constraint. As such, no detailed discussion herein. Reference is now made toFIG.10A.FIG.10Ais a circuit diagram of an IC1000A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1000A is used as one unit cell/circuit for implementing an NAND gate. For illustration of the IC1000A, a gate terminal of a PMOS transistor P1is coupled to a gate terminal of a NMOS transistor N1as indicated by a connection I1. A gate terminal of a PMOS transistor P2is coupled to a gate terminal of a NMOS transistor N2as indicated by a connection I2. In some embodiments, the connections I1and I2are indicated as input terminals, for providing corresponding control signals to both of the PMOS transistor P1and the NMOS transistor N1, and both of the PMOS transistor P2and the NMOS transistor N2, respectively. A source/drain terminal of the PMOS transistor P1is coupled to a node A1; a source/drain terminal of the PMOS transistor P1is coupled to a source/drain terminal of the PMOS transistor P2at a node A2; and a source/drain terminal of the PMOS transistor P2is coupled at a node A3. The node A1is further coupled to the node A3. The node A2is further coupled to a power rail referenced as VDD. A source/drain terminal of the NMOS transistor N1is coupled to a node B1; a source/drain terminal of the NMOS transistor N1is coupled to a source/drain terminal of the NMOS transistor N2; and a source/drain terminal of the NMOS transistor N2is coupled at a node B2. The node B1is further coupled to a power rail referenced as VSS. The node B2is further coupled to the node A3as indicated by a connection ZN. To implement the IC1000A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIGS.10B-10D. For clarification of demonstrating various forbidden regions patterned as DLFZ and GLFZ, the following layout diagrams1000B-1000D inFIGS.10B-10Dhave separate diagrams A and B for illustrating the patterns DLFZ and GLFZ, respectively. In addition, for simplicity of illustration, similar elements are not repeatedly labeled in the layout diagrams1000B-1000D, and similar detailed description is therefore omitted. FIG.10Bis a layout diagram1000B of the IC1000A inFIG.10A, in accordance with some embodiments of the present disclosure. The layout diagram1000B is provided in diagram A ofFIG.10Bby following the first guideline with the first constraint. The layout diagram1000B is also provided in diagram B ofFIG.10Bby following the second guideline with the first constraint. As illustrated in diagram A ofFIG.10B, gates1011and1012are arranged as gate terminals of PMOS transistors P1-P2or NMOS transistors N1-N2inFIG.10A. MD segments1021,1022,1023,1024and1025are arranged as source/drain terminals of PMOS transistors P1-P2or NMOS transistors N1-N2inFIG.10A. The gate1011and the MD segments1021and1022together correspond to the PMOS transistor P1. The gate1012and the MD segments1022and1023together correspond to the PMOS transistor P2. In such configurations, the PMOS transistors P1and P2share the MD segment1022, which corresponds to the PMOS transistors P1and P2being coupled at the node A2illustrated inFIG.10A. The gate1011and the MD segments1024and1025together correspond to the NMOS transistor N1. The gate1012and the MD segments1025and1023together correspond to the NMOS transistor N2. In such configurations, the PMOS transistor P2and the NMOS transistor N2share the MD segment1023, which corresponds to the PMOS transistor P2and the NMOS transistor N2being coupled together illustrated inFIG.10A. It also corresponds to the nodes A3and B2being coupled between the connection ZN illustrated inFIG.10A. Contact vias1031and1032are arranged. Signal rails1051,1052,1053and1054are arranged. The contact via1031couples the MD segment1021to the signal rail1051. The contact via1032couples the MD segment1023to the signal rail1051. With such configurations, the MD segments1021and1023are coupled together, which corresponds to the nodes A1and A3being coupled together as discussed above with respect toFIG.10A. Gate vias1041and1042are arranged. The gate via1041couples the gate1011to the signal rail1052, which corresponds to the gate of the PMOS transistor P1or NMOS transistor N1being coupled between the connection I1as discussed above with respect toFIG.10A. The gate via1042couples the gate1012to the signal rail1053, which corresponds to the gate of the PMOS transistor P2or NMOS transistor N2being coupled between the connection I2as discussed above with respect toFIG.10A. Backside vias (not shown) are arranged at a back side of the same cell illustrated in the layout diagram1000B. One of the backside vias couples the MD segment1022to a backside power rail (not shown), which corresponds to the node A2being coupled to the power rail VDD as discussed above with respect toFIG.10A. The other one of the backside vias (not shown) couples the MD segment1024to a backside power rail (not shown), which corresponds to the node B1being coupled to the power rail VSS as discussed above with respect toFIG.10A. The forbidden regions1061,1062,1063,1064,1065and1066are arranged. The forbidden regions1061-1066correspond to the forbidden regions611-615as discussed above with reference toFIGS.5-6A. The arrangement and distribution of the forbidden regions1061-1066further correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no contact vias are formed in the forbidden regions1061-1066. Compared to diagram A ofFIG.10B, in the layout diagram1000B shown in diagram B ofFIG.10B, the forbidden regions1071,1072,1073,1074,1075,1076,1077and1078are arranged. The forbidden regions1071-1078correspond to the forbidden regions631-636as discussed above with reference toFIGS.5and6B. The arrangement and distribution of the forbidden regions1071-1078correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no gate vias are formed in the forbidden regions1071-1078. FIG.10Cis a layout diagram1000C of the IC1000A inFIG.10A, in accordance with some embodiments of the present disclosure. The layout diagram1000C is provided in diagram A ofFIG.10Cby following the first guideline with the second constraint. The layout diagram1000C is also provided in diagram B ofFIG.10Bby following the second guideline with the second constraint. Compared to diagram A ofFIG.10B, in the layout diagram1000C shown in diagram A ofFIG.10C, the forbidden regions1061-1066are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions1061-1066correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no contact vias are formed in the forbidden regions1061-1066. Compared to diagram B ofFIG.10B, in the layout diagram1000C shown in diagram B ofFIG.10C, the forbidden regions1071-1078are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions1071-1078correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no gate vias are formed in the forbidden regions1071-1078. FIG.10Dis a layout diagram1000D of the IC1000A inFIG.10A, in accordance with some embodiments of the present disclosure. The layout diagram1000D is provided in diagram A ofFIG.10Dby following the first guideline with the first constraint. The layout diagram1000D is also provided in diagram B ofFIG.10Dby following the second guideline with the second constraint. The layout diagram1000D in diagram A ofFIG.10Dand the layout diagram1000B in diagram A ofFIG.10Bare the same, followed by the first guideline with the first constraint. The layout diagram1000D in diagram B ofFIG.10Dand the layout diagram1000C in diagram B ofFIG.10Care the same, followed by the second guideline with the second constraint. As such, no detailed discussion herein. Reference is now made toFIG.11A.FIG.11Ais a circuit diagram of an IC1100A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1100A is an alternative embodiments of the IC1000A shown inFIG.10A. The circuit diagram of the IC1100A has configurations similar to that of the IC1000A as illustrated inFIG.10A, and similar detailed description is therefore omitted. Compared toFIG.10A, in the circuit diagram shown inFIG.11A, the nodes A1and A3are respectively coupled to a power rail referenced as VDD. The node A2is coupled to the node B2as indicated by connection ZN shown inFIG.11A. To implement the IC1100A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIGS.11B-11D. For clarification of demonstrating various forbidden regions patterned as DLFZ and GLFZ, the following layout diagrams1100B-1100D inFIGS.11B-11Dhave separate diagrams A and B for illustrating the patterns DLFZ and GLFZ, respectively. In addition, for simplicity of illustration, similar elements are not repeatedly labeled in the layout diagrams1100B-1100D, and similar detailed description is therefore omitted. FIG.11Bis a layout diagram1100B of the IC1100A inFIG.11A, in accordance with some embodiments of the present disclosure. The layout diagram1100B is provided in diagram A ofFIG.11Bby following the first guideline with the first constraint. The layout diagram1100B is also provided in diagram B ofFIG.11Bby following the second guideline with the first constraint. As illustrated in diagram A ofFIG.11B, gates1111and1112are arranged as gate terminals of PMOS transistors P1-P2or NMOS transistors N1-N2inFIG.11A. MD segments1121,1122,1123,1124,1125and1126are arranged as source/drain terminals of PMOS transistors P1-P2or NMOS transistors N1-N2inFIG.11A. The gate1111and the MD segments1121and1122together correspond to the PMOS transistor P1. The gate1112and the MD segments1122and1123together correspond to the PMOS transistor P2. In such embodiments, the PMOS transistors P1and P2share the MD segment1122, which corresponds to the PMOS transistors P1and P2being coupled at the node A2illustrated inFIG.11A. The gate1111and the MD segments1124and1125together correspond to the NMOS transistor N1. The gate1112and the MD segments1125and1126together correspond to the NMOS transistor N2. Contact vias1131and1132are arranged. Signal rails1151,1152,1153and1154are arranged. The contact via1131couples the MD segment1122to the signal rail1151. The contact via1132couples the MD segment1126to the signal rail1153. With such configurations, the MD segments1122and1126are coupled together, which corresponds to the nodes A2and B2being coupled together as discussed above with respect toFIG.11A. It also corresponds to the nodes A2and B2being coupled between the connection ZN illustrated inFIG.11A. Gate vias1141and1142are arranged. The gate via1141couples the gate1111to the signal rail1152, which corresponds to the gate of the PMOS transistor P1or NMOS transistor N1being coupled between the connection I1as discussed above with respect toFIG.11A. The gate via1142couples the gate1112to the signal rail1154, which corresponds to the gate of the PMOS transistor P2or NMOS transistor N2being coupled between the connection I2as discussed above with respect toFIG.11A. Backside vias (not shown) are arranged at a back side of the same cell illustrated in the layout diagram1100B. The backside vias couple the MD segments1121and1123to a backside power rail (not shown), which respectively corresponds to the nodes A1and A3being coupled to the power rail VDD as discussed above with respect toFIG.11A. The other one of the backside vias (not shown) couples the MD segment1124to a backside power rail (not shown), which corresponds to the node B1being coupled to the power rail VSS as discussed above with respect toFIG.11A. The forbidden regions1161,1162,1163,1164,1165and1166are arranged. The forbidden regions1161-1166correspond to the forbidden regions1061-1066shown inFIG.10B, which is not detailed herein. Compared to diagram A ofFIG.11B, in the layout diagram1100B shown in diagram B ofFIG.11B, the forbidden regions1171,1172,1173,1174,1175,1176,1177and1178are arranged. The forbidden regions1071-1078correspond to the forbidden regions1071-1078shown inFIG.10B, which is not detailed herein. FIG.11Cis a layout diagram1100C of the IC1100A inFIG.11A, in accordance with some embodiments of the present disclosure. The layout diagram1100C is provided in diagram A ofFIG.11Cby following the first guideline with the second constraint. The layout diagram1100C is also provided in diagram B ofFIG.11Bby following the second guideline with the second constraint. In some embodiments, the forbidden regions1161-1166correspond to the forbidden regions1061-1066shown inFIG.10C, which is not detailed herein. In some embodiments, the forbidden regions1171-1178correspond to the forbidden regions1071-1078shown inFIG.10C, which is not detailed herein. FIG.11Dis a layout diagram1100D of the IC1100A inFIG.11A, in accordance with some embodiments of the present disclosure. The layout diagram1100D is provided in diagram A ofFIG.11Dby following the first guideline with the first constraint. The layout diagram1100D is also provided in diagram B ofFIG.11Dby following the second guideline with the second constraint. In some embodiments, the forbidden regions1161-1166correspond to the forbidden regions1061-1066shown inFIG.10Dwhich is not detailed herein. In some embodiments, the forbidden regions1171-1178correspond to the forbidden regions1071-1078shown inFIG.10D, which is not detailed herein. Reference is now made toFIG.12A.FIG.12Ais a circuit diagram of an IC1200A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1200A is used as one unit cell/circuit for implementing two different logic functions including, for example, a AND gate which is a combination of an NAND gate function and an inverse function. For illustration of the IC1200A, a gate terminal of a PMOS transistor P1is coupled to a gate terminal of a NMOS transistor N1at a node E1; a gate terminal of a PMOS transistor P2is coupled to a gate terminal of a NMOS transistor N2as indicated by connection I2; and a gate terminal of a PMOS transistor P3is coupled to a gate terminal of a NMOS transistor N3as indicated by a connection I1. In some embodiments, the connections I1and I2are indicated as input terminals, for providing corresponding control signals to both of the PMOS transistor P3and the NMOS transistor N3, and both of the PMOS transistor P2and the NMOS transistor N2, respectively. A source/drain terminal of the PMOS transistor P1is coupled to a node A1; a source/drain terminal of the PMOS transistor P1is coupled to a source/drain terminal of a PMOS transistor P2at a node A2; a source/drain terminal of the PMOS transistor P2is coupled to a source/drain terminal of a PMOS transistor P3at a node A3; a source/drain terminal of the PMOS transistor P3is coupled to a node A4. A source/drain terminal of the NMOS transistor N1is coupled to a node B1; a source/drain terminal of the NMOS transistor N1is coupled to a source/drain terminal of a NMOS transistor N2at a node B2; a source/drain terminal of the NMOS transistor N2is coupled to a source/drain terminal of a NMOS transistor N3; and a source/drain terminal of the NMOS transistor N3is coupled to a node B3. The node A1is further coupled to the node B1as indicated by a connection Z. The nodes A2and A4are further coupled to a power rail referenced as VDD. The node A3is further coupled to the node E1at a node E2, and the node E1is also further coupled to the node B3as indicated by connection ZN. The nodes B2is further coupled to another power rail referenced as VSS. To implement the IC12A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIGS.12B-12D. For clarification of demonstrating various forbidden regions patterned as DLFZ and GLFZ, the following layout diagrams1200B-1200D inFIGS.12B-12Dhave separate diagrams A and B for illustrating the patterns DLFZ and GLFZ, respectively. In addition, for simplicity of illustration, similar elements are not repeatedly labeled in the layout diagrams1200B-1200D, and similar detailed description is therefore omitted. FIG.12Bis a layout diagram1200B of the IC1200A inFIG.12A, in accordance with some embodiments of the present disclosure. The layout diagram1200B is provided in diagram A ofFIG.10Bby following the first guideline with the first constraint. The layout diagram1200B is also provided in diagram B ofFIG.12Bby following the second guideline with the first constraint. As illustrated in diagram A ofFIG.12B, gates1211,1212and1213are arranged as gate terminals of PMOS transistors P1-P3or NMOS transistors N1-N3inFIG.10A. MD segments1221,1222,1223,1224,1225,1226and1227are arranged as source/drain terminals of PMOS transistors P1-P3or NMOS transistors N1-N3inFIG.12A. The gate1211and the MD segments1221and1222together correspond to the PMOS transistor P1. The gate1212and the MD segments1222and1223together correspond to the PMOS transistor P2. The gate1213and the MD segments1223and1224together correspond to the PMOS transistor P3. In such configurations, the PMOS transistors P1and P2share the MD segment1222, which corresponds to the PMOS transistors P1and P2being coupled at the node A2illustrated inFIG.12A. The PMOS transistors P2and P3share the MD segment1223, which corresponds to the PMOS transistors P2and P3being coupled at the node A3illustrated inFIG.12A. Furthermore, the gate1211and the MD segments1221and1225together correspond to the NMOS transistor N1. The gate1212and the MD segments1225and1226together correspond to the NMOS transistor N2. The gate1213and the MD segments1226and1227together correspond to the NMOS transistor N3. In such configurations, the PMOS transistor P1and the NMOS transistor N1share the MD segment1221, which corresponds to the PMOS transistor P1and the NMOS transistor N1coupled at the nodes A1and B1together. It also corresponds to the nodes A1and B1being coupled between the connection Z illustrated inFIG.12A. Also, the NMOS transistors N1and N2share the MD segment1225, which corresponds to the NMOS transistors N1and N2being coupled at the node B2illustrated inFIG.12A. Contact vias1231,1232and1233are arranged. Signal rails1251,1252,1253,1254and1255are arranged. The contact via1231couples the MD segment1221to the signal rail1251, for transmitting a first data signal (not shown) that is also transmitted within the connection Z. The contact via1232couples the MD segment1223to the signal rail1252, for transmitting a second data signal (not shown). The contact via1233couples the MD segment1227to the signal rail1254, for transmitting the second data signal. In such configurations, the MD segments1223and1227receive the same data signal, which corresponds to the nodes A3and B3being coupled together as discussed above with respect toFIG.12A. Gate vias1241,1242and1243are arranged. The gate via1241couples the gate1211to the signal rail1254, which corresponds to the gate of the PMOS transistor P1or NMOS transistor N1being coupled together at the node E1as discussed above with respect toFIG.12A, for transmitting the second data signal. In such configurations, the MD segments1223and1227and the gate1211receive the same data signal, which further corresponds to the nodes E1, E2and B3being coupled between the connection ZN as discussed above with respect toFIG.12A. The Gate via1242couples the gate1212to the signal rail1253, which corresponds to the gate of the PMOS transistor P2or NMOS transistor N2being coupled between the connection I2as discussed above with respect toFIG.12A. The Gate via1243couples the gate1213to the signal rail1255, which corresponds to the gate of the PMOS transistor P3or NMOS transistor N3being coupled between the connection I1as discussed above with respect toFIG.12A. Backside vias (not shown) are arranged at a back side of the same cell illustrated in the layout diagram1200B. The backside vias couple the MD segments1222and1224to a backside power rail (not shown), which respectively corresponds to the nodes A2and A4being coupled to the power rail VDD as discussed above with respect toFIG.12A. The other one of the backside vias (not shown) couples the MD segment1225to a backside power rail (not shown), which corresponds to the node B2being coupled to the power rail VSS as discussed above with respect toFIG.12A. The forbidden regions1261,1262,1263,1264,1265,1266,1267and1268are arranged. The forbidden regions1261-1268correspond to the forbidden regions611-615as discussed above with reference toFIGS.5-6A. The arrangement and distribution of the forbidden regions1261-1268further correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no contact vias are formed in the forbidden regions1261-1268. Compared to diagram A ofFIG.12B, in the layout diagram1200B shown in diagram B ofFIG.12B, the forbidden regions1270,1271,1272,1273,1274,1275,1276,1277,1278and1279are arranged. The forbidden regions1270-1279correspond to the forbidden regions631-636as discussed above with reference toFIGS.5and6B. The arrangement and distribution of the forbidden regions1270-1279correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no gate vias are formed in the forbidden regions1270-1279. FIG.12Cis a layout diagram1200C of the IC1200A inFIG.12A, in accordance with some embodiments of the present disclosure. The layout diagram1200C is provided in diagram A ofFIG.12Cby following the first guideline with the second constraint. The layout diagram1200C is also provided in diagram B ofFIG.12Bby following the second guideline with the second constraint. Compared to diagram A ofFIG.12B, in the layout diagram1200C shown in diagram A ofFIG.12C, the forbidden regions1261-1268are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions1261-1268correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no contact vias are formed in the forbidden regions1261-1268. Compared to diagram B ofFIG.12B, in the layout diagram1200C shown in diagram B ofFIG.12C, the forbidden regions1270-1279are arranged at different locations, with consideration of the second constraint. The arrangement and distribution of the forbidden regions1270-1279correspond to that is discussed above with reference toFIGS.7C-7D. Therefore, with such configurations, no gate vias are formed in the forbidden regions1270-1279. FIG.12Dis a layout diagram1200D of the IC1200A inFIG.12A, in accordance with some embodiments of the present disclosure. The layout diagram1200D is provided in diagram A ofFIG.12Dby following the first guideline with the first constraint. The layout diagram1200D is also provided in diagram B ofFIG.12Dby following the second guideline with the second constraint. The layout diagram1200D in diagram A ofFIG.12Dand the layout diagram1200B in diagram A ofFIG.12Bare the same, followed by the first guideline with the first constraint. The layout diagram1200D in diagram B ofFIG.12Dand the layout diagram1200C in diagram B ofFIG.12Care the same, followed by the second guideline with the second constraint. As such, no detailed discussion herein. Reference is now made toFIG.13A.FIG.13Ais a circuit diagram of an IC1300A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1300A is used as one unit cell/circuit for implementing various logic functions including, for example, a AND gate function, an OR gate function and an inverse function. For illustration of the IC1300A, a gate terminal of a PMOS transistor P1is coupled to a gate terminal of a NMOS transistor N1as indicated by connection I4; a gate terminal of a PMOS transistor P2is coupled to a gate terminal of a NMOS transistor N2as indicated by connection I3; a gate terminal of a PMOS transistor P3is coupled to a gate terminal of a NMOS transistor N3as indicated by a connection I1; and a gate terminal of a PMOS transistor P4is coupled to a gate terminal of a NMOS transistor N4as indicated by a connection I2. In some embodiments, the connections I1-I4are indicated as input terminals, for providing corresponding control signals to the corresponding PMOS transistors P1-P4and the NMOS transistors N1-N4. A source/drain terminal of the PMOS transistor P1is coupled to a node A1; a source/drain terminal of the PMOS transistor P1is coupled to a source/drain terminal of a PMOS transistor P2at a node A2; a source/drain terminal of the PMOS transistor P2is coupled to a source/drain terminal of a PMOS transistor P3at a node A3; a source/drain terminal of the PMOS transistor P3is coupled to a source/drain terminal of a PMOS transistor P4at a node A4; and a source/drain terminal of the PMOS transistor P4is coupled a node A5. A source/drain terminal of the NMOS transistor N1is coupled to a node B1; a source/drain terminal of the NMOS transistor N1is coupled to a source/drain terminal of a NMOS transistor N2; a source/drain terminal of the NMOS transistor N2is coupled to a source/drain terminal of a NMOS transistor N3at a node B2; a source/drain terminal of the NMOS transistor N3is coupled to a source/drain terminal of a NMOS transistor N4; and a source/drain terminal of the NMOS transistor N4is coupled to a node B3. The node A1is further coupled to the nodes A3and A5. The node A2is further coupled to a power rail referenced as VDD. The node A4is further coupled to the node B2as indicated by a connection ZN. The nodes B1and B3are further coupled to a power rail referenced as VSS. To implement the IC13A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIGS.13B-13D. For clarification of demonstrating various forbidden regions patterned as DLFZ and GLFZ, the following layout diagrams1300B-1300D inFIGS.13B-13Dhave separate diagrams A and B for illustrating the patterns DLFZ and GLFZ, respectively. In addition, for simplicity of illustration, similar elements are not repeatedly labeled in the layout diagrams1300B-1300D, and similar detailed description is therefore omitted. FIG.13Bis a layout diagram1300B of the IC1300A inFIG.13A, in accordance with some embodiments of the present disclosure. The layout diagram1300B is provided in diagram A ofFIG.13Bby following the first guideline with the first constraint. The layout diagram1300B is also provided in diagram B ofFIG.13Bby following the second guideline with the first constraint. As illustrated in diagram A ofFIG.13B, gates1311,1312,1313and1314are arranged as gate terminals of PMOS transistors P1-P4or NMOS transistors N1-N4inFIG.10A. MD segments1320,1321,1322,1323,1324,1325,1326,1327,1328and1329are arranged as source/drain terminals of PMOS transistors P1-P4or NMOS transistors N1-N4inFIG.13A. The gate1311and the MD segments1321and1322together correspond to the PMOS transistor P1. The gate1312and the MD segments1322and1323together correspond to the PMOS transistor P2. The gate1313and the MD segments1323and1324together correspond to the PMOS transistor P3. The gate1314and the MD segments1324and1325together correspond to the PMOS transistor P4. In such configurations, the PMOS transistors P1and P2share the MD segment1322, which corresponds to the PMOS transistors P1and P2being coupled at the node A2illustrated inFIG.13A. The PMOS transistors P2and P3share the MD segment1323, which corresponds to the PMOS transistors P2and P3being coupled at the node A3illustrated inFIG.13A. The PMOS transistors P3and P4share the MD segment1324, which corresponds to the PMOS transistors P3and P4being coupled at the node A4illustrated inFIG.13A. Furthermore, the gate1311and the MD segments1326and1327together correspond to the NMOS transistor N1. The gate1312and the MD segments1327and1328together correspond to the NMOS transistor N2. The gate1313and the MD segments1328and1329together correspond to the NMOS transistor N3. The gate1314and the MD segments1329and1320together correspond to the NMOS transistor N4. In such configurations, the NMOS transistors N2and N3share the MD segment1228, which corresponds to the NMOS transistors N2and N3being coupled at the node B2illustrated inFIG.13A. Contact vias1331,1332,1333,1334and1335are arranged. Signal rails1351,1352,1353,1354,1355,1356and1357are arranged. The contact via1331couples the MD segment1321to the signal rail1351. The contact via1332couples the MD segment1323to the signal rail1351. The contact via1334couples the MD segment1325to the signal rail1351. In such configurations, the MD segments1321,1323and1325couple to the same signal rail1351, which corresponds to the nodes A1, A3and A5being coupled together illustrated inFIG.13A. The contact via1333couples the MD segment1324to the signal rail1355, for transmitting a first data signal (not shown). The contact via1335couples the MD segment1328to the signal rail1354, for transmitting the first data signal. In such configurations, the MD segments1324and1328receive the same data signal, which corresponds to the nodes A4and B2being coupled together, which is also indicated as the connection ZN, illustrated inFIG.13A. Gate vias1341,1342,1343and1344are arranged. The gate via1341couples the gate1311to the signal rail1352, which corresponds to the gate of the PMOS transistor P1or NMOS transistor N1being coupled between the connection I4as discussed above with respect toFIG.13A. The gate via1342couples the gate1312to the signal rail1353, which corresponds to the gate of the PMOS transistor P2or NMOS transistor N2being coupled between the connection I3as discussed above with respect toFIG.13A. The gate via1343couples the gate1313to the signal rail1356, which corresponds to the gate of the PMOS transistor P3or NMOS transistor N3being coupled between the connection I1as discussed above with respect toFIG.13A. The gate via1344couples the gate1314to the signal rail1357, which corresponds to the gate of the PMOS transistor P4or NMOS transistor N4being coupled between the connection I2as discussed above with respect toFIG.13A. Backside vias (not shown) are arranged at a back side of the same cell illustrated in the layout diagram1300B. One of the backside vias couples the MD segment1322to a backside power rail (not shown), which respectively corresponds to the node A2being coupled to the power rail VDD as discussed above with respect toFIG.13A. Some other backside vias (not shown) couples the MD segments1326and1320to a backside power rail (not shown), which corresponds to the nodes B1and B3being coupled to the power rail VSS as discussed above with respect toFIG.13A. The forbidden regions1361,1362,1363,1364,1365,1366,1367,1368,1369, and1360are arranged. The forbidden regions1360-1369correspond to the forbidden regions611-615as discussed above with reference toFIGS.5-6A. The arrangement and distribution of the forbidden regions1360-1369further correspond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no contact vias are formed in the forbidden regions1360-1369. Compared to diagram A ofFIG.13B, in the layout diagram1300B shown in diagram B ofFIG.13B, the forbidden regions1371,1372,1373,1374,1375,1376,1377,1378,1379,1370,137aand137bare arranged. The forbidden regions1370-1379and137a-137bcorrespond to the forbidden regions631-636as discussed above with reference toFIGS.5and6B. The arrangement and distribution of the forbidden regions1370-1379and137a-137bcorrespond to that is discussed above with reference toFIGS.7A-7B. Therefore, with such configurations, no gate vias are formed in the forbidden regions1370-1379and137a-137b. FIG.13Cis a layout diagram1300C of the IC1300A inFIG.13A, in accordance with some embodiments of the present disclosure. The layout diagram1300C is provided in diagram A ofFIG.13Cby following the first guideline with the second constraint. The layout diagram1300C is also provided in diagram B ofFIG.13Bby following the second guideline with the second constraint. Compared to diagram A ofFIG.13B, in the layout diagram1300C shown in diagram A ofFIG.13C, several patterns are altered, including, for example, some of the MD segments1320-1329have different sizes. For example, with reference to diagram A ofFIG.13B, sizes of the MD segments1323,1324and1325are altered, compared to that shown in diagram A ofFIG.13B. In addition, some of the contact vias1331-1335are placed at different locations, and some of the signal rails1351-1357have alternative patterns. For example, with reference to diagram A ofFIG.13C, in a layout view, the contact vias1331,1332and1334are arranged to overlap with the signal rail1353. In such configurations, similar to that is discussed with reference to diagram A ofFIG.13B, the MD segments1321,1323and1325couple together to the same signal rail1353, which corresponds to the nodes A1, A3and A5being coupled together illustrated inFIG.13A. In a layout view, the contact via1333is arranged to overlap with the signal rail1352, for transmitting the first data signal. In such case, the contact via1335couples the MD segment1328to the signal rail1356, for transmitting the first data signal. With such configurations, similar to that is discussed with reference to diagram A ofFIG.13B, the MD segments1324and1328receive the same data signal, which corresponds to the connection ZN illustrated inFIG.13A. Furthermore, some of the gate vias1341-1344are placed at different locations. For example, with reference to diagram A ofFIG.13C, in a layout view, the gate via1341is arranged at a location that is close to the cell boundary, and arranged to overlap with the signal rail1351. In some embodiments, the cell boundary corresponds to the cell boundary CB1at least shown inFIG.8. In such case, the gate via1341couples the gate1311to the signal rail1351, which also corresponds to the connection I4as discussed above with respect toFIGS.13A-13B. With the comparison of the layout diagram1300B, the above alternations in the layout diagram1300C are generated based on various forbidden regions1360-1369,1370-1379and137a-137b. Specifically, in the layout diagram1300B shown in diagram A ofFIG.13B, the forbidden regions1360-1369are arranged at different at different locations, by following the first guideline with consideration of the second constraint. The second constraint is discussed above with reference toFIGS.7C-7D. In the layout diagram1300B shown in diagram B ofFIG.13B, the forbidden regions1370-1379and137a-137bare arranged at different at different locations, by following the second guideline with consideration of the second constraint. Therefore, with such configurations, no contact vias are formed in the forbidden regions1360-1369, and no gate vias are formed in the forbidden regions1370-1379and137a-137b. Reference is now made toFIG.14A.FIG.14Ais a circuit diagram of an IC1400A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1400A is an alternative embodiments of the IC1300A shown inFIG.13A. The circuit diagram of the IC1400A has configurations similar to that of the IC1300A as illustrated inFIG.13A, and similar detailed description is therefore omitted. For illustration of the IC1400A, a dashed circle labeled with “CX” is a part of the IC1400A, and is identical to the IC1300A shown inFIG.13A. The other part of the IC1400A includes a PMOS transistor P5and a NMOS transistor N5, that has no function in the IC1400A. Gate terminals of the PMOS transistor P1and the NMOS transistor N5are not coupled to other metal rails. The PMOS transistor P5and the NMOS transistor N5are indicated as dummy transistors, in some embodiments. A source/drain terminal of the PMOS transistor P5is coupled to a node A6; a source/drain terminal of the PMOS transistor P5is coupled to a source/drain terminal of the PMOS transistor P1at the node A1. A source/drain terminal of the NMOS transistor N5is coupled to a node B4; a source/drain terminal of the NMOS transistor N5is coupled to a source/drain terminal of the PMOS transistor N1at the node B1. The node A6is further coupled to a power rail referenced as VDD. The node B4is further coupled to a power rail referenced as VSS. To implement the IC14A, embodiments of layout designs and/or structures are provided and discussed below as illustrated with reference toFIG.14B. FIG.14Bis a layout diagram1400B of the IC1400A inFIG.14A, in accordance with some embodiments of the present disclosure. The layout diagram1400B is provided inFIG.14Bby following the first guideline with the first constraint. The layout diagram1400B is provided inFIG.14Bby following the second guideline with the first constraint. For simplicity of illustration, forbidden regions patterned as DLFZ are shown and forbidden regions patterned as GLFZ are omitted. In some embodiments, the layout diagram1400B is an alternative embodiments of the layout diagram1300B shown inFIG.13B. The layout diagram1400B has configurations similar to that of the layout diagram1300B as illustrated inFIG.13B, and similar detailed description is therefore omitted. For illustration of the layout diagram1400B, a dashed circle labeled with “CX′” is a part of the layout diagram1400B, and is identical to the layout diagram1300B shown in diagram A inFIG.13B. Compared to diagram A ofFIG.14B, in the layout diagram1400B shown inFIG.14B, further arranged is a gate1411as gate a terminal of PMOS transistor P5or NMOS transistor N5inFIG.14A. Also arranged are MD segments1421and1423are arranged as source/drain terminals of PMOS transistor P5or NMOS transistor N5inFIG.14A. The gate1411and the MD segments1421and1322together correspond to the PMOS transistor P5. The gate1411and the MD segments1422and1327together correspond to the NMOS transistor N5. Signal rails1351-1354in the layout diagram1400B are elongated, compared to the layout diagram1300B. Specifically, since the gate1411is arranged, each of the signal rails1351-1354gets longer by substantially one gate pitch P1, with respect to the X direction. With such configurations, when a situation comes to that another cell (not shown) abuts the current cell with respect to the X direction, at least one of the contact vias, for example, the contact via1331, is separated from other vias in the abutted cell by more distances. Reference is now made toFIG.15.FIG.15is a schematic layout diagram1500of a semiconductor device, in accordance with some embodiments of the present disclosure. In some embodiments, the layout diagram1500is an alternative embodiment of the layout diagram200shown inFIG.2. In some other embodiments, the layout diagram1500is an alternative embodiment of the layout diagram800shown inFIG.8. In various embodiments, the layout diagram1500is utilized to fabricate the semiconductor device300inFIGS.3A-4Bor the semiconductor device1700inFIGS.17-18C. The correspondence between a given layout diagram feature formed based on the given layout diagram feature, a same reference designator is used in each of the layout diagram and structure depictions, as discussed below. For simplicity of illustration, only few elements are labeled inFIG.15. The layout diagram1500with respect to the embodiments ofFIG.8, like elements inFIG.15are designated with the same reference numbers for ease of understanding. Compared toFIG.8, in the layout diagram1500inFIG.15, one double height cell C21is included. The cell C21is defined between the cell boundaries including CB4and CB5, and has a cell height H4. In the cell C21, active areas A1, A2, A3and A4are arranged separately with respect to Y direction, and a metal segment151is arranged in a metal-1 (M1) layer. The metal segment151extends from the active area A1to the active area A4, and extends across a boundary CB′, with respect to Y direction. At least one via, for example, the vias1521,1522and1523, is arranged inside the metal segment151, to form a metal via contacting between the signal rail (not labeled) in the M0 layer and the metal segment151. This via is patterned as “V0” in the layout diagram1500B, and indicates as a via coupled between the M0 and M1 layers. The M1 layer is above the M0 layer, in some embodiments. In some embodiments, the active areas A1-A4correspond to the active areas A1-A4illustrated inFIG.8. In some other embodiments, the cell boundaries CB4-CB5correspond to the cell boundaries CB1-CB2or CB2-CB3illustrated inFIG.8, respectively. In some embodiments, regarding the double height cell C21, the cell boundaries CB4-CB5are defined corresponding to the active areas A1and A4, when at least one condition is satisfied. In some other embodiments, a first condition indicates that the metal segment in the M1 layer is arranged across the active areas A2-A3which defining the boundary CB′ therebetween. In some alternative embodiments, a second condition indicates that a length of the metal segment is less than a sum of heights H2and H3, which is also referred to as the cell height H4. In various embodiments, a third condition indicates that at least two vias arranged inside the metal segment are configured to couple between at least one metal rail in the M0 layer and the metal segment in the M1 layer. To implement various semiconductor devices included in an IC, the layout diagrams as discussed above with reference toFIGS.1,2,5,6A-6B,7A-7D and15are used or modified to be used, as illustrated by the non-limiting examples discussed below with respect toFIGS.16A-16C. These semiconductor devices correspond to the semiconductor device300discussed with referenceFIGS.3A-4Bor the semiconductor devices1700discussed with referenceFIGS.17-18C. In the various embodiments discussed below, the semiconductor device or the IC of the present disclosure is implemented through the use of layout diagrams, including the double height cell, depicted inFIGS.16B-16Cthat correspond to a circuit diagram depicted inFIG.16A, as indicated. It is noted that these layout diagrams merely illustrate a front side of the corresponding semiconductor device, and are provided when the guidelines with various constraints are followed are followed as discussed above with reference toFIGS.5-7D. Reference is now made toFIG.16A.FIG.16Ais a circuit diagram of an IC1600A, in accordance with some embodiments of the present disclosure. In some embodiments, the IC1600A is used as one unit cell/circuit for implementing a flip-flop. For illustration of the IC1600A, it is provided multiple PMOS transistors, including the PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9and P10, multiple NMOS transistors, including the NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10and N11, and invertors, including the invertors INV1, INV2, INV3, INV4, INV5and INV6. The PMOS transistor P1is configured to receive a data signal SI as a control signal; the PMOS transistor P2is configured to receive a data signal SEB as a control signal; the PMOS transistor P3is configured to receive a data signal SE as a control signal; the PMOS transistor P4is configured to receive a data signal D as a control signal. Similarly, the PMOS transistor P5is configured to receive a data signal CLKBB, and the NMOS transistor N5is configured to receive a data signal SEB. The NMOS transistor N1is configured to receive the data signal SI; the NMOS transistor N6is configured to receive the data signal SE; the NMOS transistor N3is configured to receive the data signal D; and the NMOS transistor N2is configured to receive the data signal SEB. The invertor INV1is configured to receive the data signal SE as an input signal, and to output the data signal SEB; the invertor INV2is configured to receive a data signal CP as an input signal, and to output the data signal CLKB; and the invertor INV3is configured to receive the data signal CLKB as an input signal, and to output the data signal CLKBB. The invertor INV4is configured to receive a data signal m1_axas an input signal, which is transmitted from the PMOS transistor P5and the NMOS transistor N5, and to output a data signal m1_b. The PMOS transistor P7is configured to receive the data signal m1_b; the PMOS transistor P6is configured to receive the data signal CLKB; the NMOS transistor N11is configured to receive the data signal CLKBB; and the NMOS transistor N7is configured to receive the data signal m1_b. The PMOS transistor P8is configured to receive the data signal CLKB, and the NMOS transistor N8is configured to receive the data signal CLKBB. The invertor INV5is configured to receive a data signal s1_aas an input signal, which is transmitted from the PMOS transistor P8and the NMOS transistor N8, and to output a data signal s1_bx; and the invertor INV6is configured to receive the data signal s1_bxas an input signal, and to output a data signal Q, which is also indicated as an output signal of the flip-flop. The PMOS transistor P9is configured to receive the data signal s1_bx; the PMOS transistor P10is configured to receive the data signal CLKBB; the NMOS transistor N9is configured to receive the data signal CLKB; and the NMOS transistor N10is configured to receive the data signal s1_bx. FIGS.16B-16Care layout diagrams1600B and1600C of the IC1600A inFIG.16A, in accordance with some embodiments of the present disclosure. The layout diagrams1600B and1600C are provided by following the first guideline with the second constraint and the second guideline with the first constraint. In some other embodiments, the diagrams1600B and1600C are provided to fabricate the IC1600A by following the first guideline with the first or second constraint and the second guideline with the first or second constraint. As illustrated inFIG.16B, the patterns below the M1 layer are illustrated. For simplicity of illustration, only few elements are labeled inFIG.16B. In addition, the PMOS transistors P1-P10, the NMOS transistors N1-N11and the invertors INV1-INV4are noted with the corresponding gates1610-1619and161a-161g. The data signals SEB, SI, D, mx1, mx2, CP, CLKB, CLKBB, m1_ax, m1_b, s1_bxand Q are noted with the corresponding signal rails inFIG.16C. These signal rails are patterned as M0 and are configured to transmit the aforesaid data signals. The gate1611is arranged as the gate terminals of PMOS transistor P1and NMOS transistor N1; the gate1612is arranged as the gate terminals of PMOS transistor P2and NMOS transistor N2; the gate1613is arranged as the gate terminals of PMOS transistor P4and NMOS transistor N3; the gate1614is arranged as the gate terminals of PMOS transistor P3and NMOS transistor N6and as the input terminal of invertor INV1; the gate1615is arranged as the gate terminal of NMOS transistor N11; the gate1616is arranged as the gate terminal of NMOS transistor N6; the gate1617is arranged as the gate terminals of PMOS transistor P7and NMOS transistor N7; and the gate1618is arranged as the input terminal of invertor INV3. Furthermore, the gate1619is arranged as the input terminal of invertor INV6; the gate1610is arranged as the input terminal of invertor INV5; the gate161ais arranged as the gate terminals of PMOS transistor P9and NMOS transistor N10; the gate161bis arranged as the gate terminal of PMOS transistor P10; the gate161cis arranged as the gate terminal of NMOS transistor N9; the gate161dis arranged as the gate terminal of PMOS transistor P6; the gate161eis arranged as the gate terminal of NMOS transistor N8; the gate161fis arranged as the input terminal of invertor INV4; and the gate161gis arranged as the input terminal of invertor INV2. Gate vias1640-1649and164a-164gare arranged, and to couple the gates1610-1619and161a-161gto the corresponding signal rails (not labeled). Contact vias1631,1632and others without labelling are arranged. The contact via1631couples one MD segment (not labeld) to one signal rail (not labeld), for transmitting the data signal Q (shown inFIG.16C), which corresponds to the invertor INV6being outputting the data signal Q as discussed above with respect toFIG.16A. The contact via1632couples one MD segment (not labeld) to one signal rail1655, for transmitting the data signal CLKBB (shown inFIG.16C), which corresponds to the invertor INV3being outputting the data signal CLKBB as discussed above with respect toFIG.16A. The forbidden regions patterned as DLFZ and GLFZ are arranged. Specifically, the forbidden regions patterned as DLFZ are arranged without the contact vias, and correspond to the forbidden regions discussed above with reference toFIGS.7C-7D. The forbidden regions patterned as GLFZ are arranged without the gate vias, and correspond to the forbidden regions discussed above with reference toFIGS.7A-7B. As illustrated inFIG.16C, the patterns disposed in the M0-M1 layers are illustrated. For simplicity of illustration, only few elements are labeled inFIG.16C. For ease of understanding, the gates1610-1619and161a-161gare also illustrated in the layout diagram1600C. Metal segments1691,1692,1693,1694,1695,1696,1697,1698,1699,1690and169aare arranged in the M1 layer. Vias1681,1682,1683,1684,1685and1686and others without labelling are arranged and patterned as “V0’. The vias couples the signal rails in the M0 layer to the corresponding metal segments1690-1691and169ain the M1 layer. For example, with reference toFIG.16C, the via1681couples the signal rail1652to the metal segments1691, and the via1682couples the signal rail1651to the metal segments1691, which corresponds to the signal rails1651-1652transmitted with the data signal SEB. The via1683couples the signal rail1653to the metal segments1696, and the via1684couples the signal rail1654to the metal segments1696, which corresponds to the signal rails1653-1654transmitted with the data signal CLKB. The via1685couples the signal rail1655to the metal segments1698, and the via1686couples the signal rail1656to the metal segments1698, which corresponds to the signal rails1655-1656transmitted with the data signal CLKBB. Reference is now made toFIG.17.FIG.17is a schematic layout diagram of a semiconductor device1700, in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device1700corresponds to the semiconductor device300depicted inFIGS.3A-3B. The semiconductor device1700with respect to the embodiments ofFIGS.3A-3B, like elements inFIG.17are designated with the same reference numbers for ease of understanding, and similar detailed description is therefore omitted. For simplicity of illustration, only few elements are labeled inFIG.17. For illustration inFIG.17, a cell C11is arranged. In some embodiments, the cell C11is an alternative embodiment of the cell C11depicted inFIGS.3A-3B. Compared to embodiments depicted inFIGS.3A-3B, in the cell C11, no backside power rails or backside vias are arranged. A front side of the semiconductor device1700is illustrated. The semiconductor device1700includes gates1711and1712, MD segments1721,1722,1723and1724, contact vias1731,1732and1733, gate vias1741and1742, and metal rails1751,1752,1753,1754,1755,1756,1757and1758. Some forbidden regions patterned as DLFZ are also shown for the following illustration, and some forbidden regions patterned as GLFZ are not shown for simplifying illustration. The metal rails1751-1758have widths that are the same, with respect to the Y direction. In some embodiments, the metal rails1751-1758include power rails1751and1757, and signal rails1752-1756and1758. In some other embodiments, the power rails1751and1757are configured to transmit power signals. For example, with reference toFIG.17, the power rail1751is configured to receive a power voltage signal VDD and couple the power voltage signal VDD to the corresponding transistors. The power rail1757is configured to receive a reference voltage signal VSS and couple the reference voltage signal VSS to the corresponding transistors. In some alternative embodiments, the signal rails1752-1756and1758are configured to transmit data signals, and are configured to couple the data signals to the corresponding transistors. Reference is now made toFIGS.18A-18C.FIGS.18A-18Care cross sectional view of the semiconductor device1700shown inFIG.17, in accordance with some embodiments of the present disclosure.FIG.18Ais a cross-sectional view along a line A-A′ ofFIG.17.FIG.18Bis a cross-sectional view along a line B-B′ ofFIG.17.FIG.18Cis a cross-sectional view along a line C-C′ ofFIG.17. For ease of understanding, the embodiments with respect toFIG.18Aare discussed with reference toFIGS.18B-18C, and only illustrates some structures that are associated with the corresponding structures shown inFIG.17as an exemplary embodiment. The semiconductor device1700with respect to the embodiments ofFIG.17, like elements inFIGS.18A-18Care designated with the same reference numbers for ease of understanding. As illustrated inFIG.18A, the MD segments1721and1723are respectively disposed on epitaxy structures1821and1822, and silicide layers1811and1812are respectively disposed over therebetween. An isolation structure1831is formed between the MD segments1721and1723, between the epitaxy structures1821and1822, and between the silicide layers1811and1812, and a dielectric structure1841is filled therebetween. An interlayer dielectric (ILD) layer1851is disposed above the MD segments1721and1723and the dielectric structure1841. A dielectric structure1861is filled between the power rails1751and1757and signal rails1752-1756, and is also indicated as the M0 layer in some embodiments. The contact via1731is disposed in the ILD layer1851, and contacts both of the MD segment1721and the power rail1751. A backside ILD layer1871is disposed below the epitaxy structures1821and1822, the isolation structure1831and the dielectric structure1841. As illustrated inFIG.18B, the MD segments1722and1724are respectively disposed on epitaxy structures1823and1824, and silicide layers1813and1814are respectively disposed over therebetween. An isolation structure1832is formed between the MD segments1722and1724, between the epitaxy structures1823and1824, and between the silicide layers1813and1814, and the dielectric structure1841is filled therebetween. The ILD layer1851is disposed above the MD segments1722and1724and the dielectric structure1841. The dielectric structure1861is filled between the power rails1751and1757and signal rails1752-1753and1755. The contact via1732is disposed in the ILD layer1851, and contacts both of the MD segment1722and the signal rail1752. The contact via1733is disposed in the ILD layer1851, and contacts both of the MD segment1724and the signal rail1755. The backside ILD layer1871is disposed below the epitaxy structures1823and1824, the isolation structure1832and the dielectric structure1841. As illustrated inFIG.18C, spacers1881and1882are disposed on opposite sidewalls of the gate1711and1712respectively. The dielectric structure1841is filled between the gates1711-1712and the spacers1881-1882. The gate vias1741-1742are disposed in the ILD layer1851, and contacts both of the gate1711and the signal rail1754and both of the gate1712and the signal rail1758, respectively. In some embodiments, the silicide layers1811-1814correspond to the silicide layers411-412shown inFIG.4A. In some embodiments, the epitaxy structures1821-1824correspond to the epitaxy structures421-422shown inFIGS.4A-4B. In some embodiments, the isolation structures1831-1832correspond to the isolation structure431shown inFIG.4A. In some embodiments, the dielectric structure1841corresponds to the dielectric structure441shown inFIGS.4A-4B. In some embodiments, the ILD layer1851corresponds to the ILD layer451shown inFIGS.4A-4B. In some embodiments, the dielectric structure1861corresponds to the dielectric structure461shown inFIG.4A. In some embodiments, the backside ILD layer1871corresponds to the backside ILD layer471shown inFIGS.4A-4B. In some embodiments, the spacers1881-1882correspond to the spacer481shown inFIG.4B. Reference is now made toFIG.19.FIG.19is a flow chart of a method1900for fabricating an IC, in accordance with some embodiments of the present disclosure. In some embodiments, the IC includes at least one semiconductor device including, for example, the semiconductor device300or1700. In some other embodiments, the IC is manufactured based on at least one layout diagram including, for example, layout diagrams200,500,600A-600B,700A-700D,800,900B-900D,1000B-1000D,1100B-1200D,1300B-1300D,1400B,1500, or1600B-1600C, discussed above with respect toFIGS.2-16C. Following illustrations of the method1900inFIG.19with reference to the semiconductor device300shown inFIGS.3A-4Bor the layout diagrams600A-600B inFIGS.6A-6Bthereof include exemplary operations. However, the operations inFIG.19are not necessarily performed in the order shown. Alternatively stated, operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure. At operation1910, gates and conductive segments are formed across or above a first active area and a second active area. The first active area is included in a first cell that corresponds to a first circuit. The second active area is included in a second cell that corresponds to a second circuit and abuts with the first cell. For illustration, as shown inFIG.3A, the gates311-313are formed across the active areas patterned as AA in the cells C11and C01, and the MD segments321and323are formed above these active areas. The cell C11corresponds to one circuit, and the cell C01that abuts the cell C11corresponds to another circuit. At operation1920, a first conductive via is formed in the first cell, within a first region that abuts a first forbidden region in the second active area, in a layout view. For illustration, as shown inFIG.6A, the contact via532is disposed in the cell C11within a region that abuts the forbidden region611in the active area (not shown) of another cell (not shown) that abuts the cell C11. The cell abutting the cell C11is indicated as an abutted cell hereinafter. In another example, with reference toFIG.6B, the gate via341is disposed in the cell C11within a region that abuts the forbidden region635in the active area of another abutted cell. At operation1930, a second conductive via is formed in the second cell, within a second region that abuts a second forbidden region in the first active area, in a layout view. For illustration, as shown inFIG.6A, a contact via (not shown) is disposed in the abutted cell within the region621that abuts the forbidden region612in the active area of cell C11. In another example, with reference toFIG.6B, a gate via (not shown) is disposed in another abutted cell within the region642that abuts the forbidden region634in the active area of cell C11. At operation1940, signal rails are formed above the first active area and the second active area. For illustration, as shown inFIG.3A, the signal rails351-352are formed in the M0 layer that is disposed above the active areas. Also for illustration as shown inFIGS.6A-6B, the signal rails351-352are disposed. In some embodiments, the first conductive via formed in the operation1920couples one of the signal rails to one of the gates or the conductive segments formed in the operation1910. For illustration, as shown inFIG.6A, the contact via532couples the signal rail355to one MD segment (which is not labeled and shown inFIG.3A). In another example, with reference toFIG.6B, the gate via341couples the signal rail352to the gate311. In some embodiments, the second conductive via formed in the operation1920couples one of the signal rails to one of the gates or the conductive segments formed in the operation1910. For illustration, as shown inFIG.3A, in the abutted cell C01, the contact via331couples the signal rail353to the MD segment322. In some embodiments, the first forbidden region is configured where no conductive via is disposed, and the second forbidden region is configured where no conductive via is disposed. For illustration, as shown inFIG.6A, the forbidden region611, when the contact via532is disposed as the illustration, has no contact vias disposed in. The forbidden region612, when the contact via is disposed in the region621, has no contact vias disposed in. For another illustration, as shown inFIG.6B, the forbidden region635, when the gate via341is disposed as the illustration, has no gate vias disposed in. The forbidden region634, when the gate via is disposed in the region642, has no gate vias disposed in. Reference is now made toFIG.20.FIG.20is a block diagram of an electronic design automation (EDA) system2000for designing the integrated circuit layout design, in accordance with some embodiments of the present disclosure. EDA system2000is configured to implement one or more operations of the method1900disclosed inFIG.19, and further explained in conjunction withFIGS.3A-7D. In some embodiments, EDA system2000includes an APR system. In some embodiments, EDA system2000is a general purpose computing device including a hardware processor2020and a non-transitory, computer-readable storage medium2060. Storage medium2060, amongst other things, is encoded with, i.e., stores, computer program code (instructions)2061, i.e., a set of executable instructions. Execution of instructions2061by hardware processor2020represents (at least in part) an EDA tool which implements a portion or all of, e.g., the method1900. The processor2020is electrically coupled to computer-readable storage medium2060via a bus2050. The processor2020is also electrically coupled to an I/O interface2010and a fabrication tool2070by bus2050. A network interface2030is also electrically connected to processor2020via bus2050. Network interface2030is connected to a network2040, so that processor2020and computer-readable storage medium2060are capable of connecting to external elements via network2040. The processor2020is configured to execute computer program code2061encoded in computer-readable storage medium2060in order to cause EDA system2000to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor2020is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit. In one or more embodiments, computer-readable storage medium2060is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium2060includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium2060includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD). In one or more embodiments, storage medium2060stores computer program code2061configured to cause EDA system2000(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium2060also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, storage medium2060stores library2062of standard cells including such standard cells as disclosed herein, for example, cells C01, C11, C12and C21discussed above with respect toFIGS.2-8and15. EDA system2000includes I/O interface2010. I/O interface2010is coupled to external circuitry. In one or more embodiments, I/O interface2010includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor2020. EDA system2000also includes network interface2030coupled to processor2020. Network interface2030allows EDA system2000to communicate with network2040, to which one or more other computer systems are connected. Network interface2030includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more systems2000. EDA system2000also includes the fabrication tool2070coupled to the processor2020. The fabrication tool2070is configured to fabricate semiconductor devices, including, for example, the semiconductor device300inFIGS.3A-4Band the semiconductor device1700inFIGS.17-18C, and integrated circuits that include the semiconductor devices based on the design files processed by the processor2020and/or the IC layout designs as discussed above. EDA system2000is configured to receive information through I/O interface2010. The information received through I/O interface2010includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor2020. The information is transferred to processor2020via bus2050. EDA system2000is configured to receive information related to a UI through I/O interface2010. The information is stored in computer-readable medium2060as user interface (UI)2063. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system2000. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool. In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, for example, one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. FIG.21is a block diagram of IC manufacturing system2100, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using IC manufacturing system2100. InFIG.21, IC manufacturing system2100includes entities, such as a design house2110, a mask house2120, and an IC manufacturer/fabricator (“fab”)2130, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device2140. The entities in IC manufacturing system2100are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house2110, mask house2120, and IC fab2130is owned by a single larger company. In some embodiments, two or more of design house2110, mask house2120, and IC fab2130coexist in a common facility and use common resources. Design house (or design team)2110generates an IC design layout diagram2111. IC design layout diagram2111includes various geometrical patterns, for example, an IC layout design depicted inFIG.2,FIG.5,FIGS.6A-6B,FIGS.7A-7D,FIG.8,FIGS.9B-9D,FIGS.10B-10D,FIGS.11B-11D,FIGS.12B-12D,FIGS.13B-13D,FIG.14B,FIG.15, and/orFIGS.16B-16C, designed for an IC device2140, for example, semiconductor devices300and1700, discussed above with respect toFIGS.3A-4Band/orFIGS.17-18C. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device2140to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram2111includes various IC features, such as an active area, gate electrode, source and drain, conductive segments or vias of an interlayer interconnection, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house2110implements a proper design procedure to form IC design layout diagram2111. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram2111is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram2111can be expressed in a GDSII file format or DFII file format. Mask house2120includes data preparation2121and mask fabrication2121. Mask house2120uses IC design layout diagram2111to manufacture one or more masks2123to be used for fabricating the various layers of IC device2140according to IC design layout diagram2111. Mask house2120performs mask data preparation2121, where IC design layout diagram2111is translated into a representative data file (“RDF”). Mask data preparation2121provides the RDF to mask fabrication2122. Mask fabrication2122includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)2123or a semiconductor wafer2133. The IC design layout diagram2111is manipulated by mask data preparation2121to comply with particular characteristics of the mask writer and/or requirements of IC fab2130. InFIG.21, data preparation2121and mask fabrication2122are illustrated as separate elements. In some embodiments, data preparation2121and mask fabrication2122can be collectively referred to as mask data preparation. In some embodiments, data preparation2121includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram2111. In some embodiments, data preparation2121includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem. In some embodiments, data preparation2121includes a mask rule checker (MRC) that checks the IC design layout diagram2111that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram2111to compensate for limitations during mask fabrication2122, which may undo part of the modifications performed by OPC in order to meet mask creation rules. In some embodiments, data preparation2121includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab2130to fabricate IC device2140. LPC simulates this processing based on IC design layout diagram2111to create a simulated manufactured device, such as IC device2140. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram2111. It should be understood that the above description of data preparation2121has been simplified for the purposes of clarity. In some embodiments, data preparation2121includes additional features such as a logic operation (LOP) to modify the IC design layout diagram2111according to manufacturing rules. Additionally, the processes applied to IC design layout diagram2111during data preparation2121may be executed in a variety of different orders. After data preparation2121and during mask fabrication2122, a mask2123or a group of masks2123are fabricated based on the modified IC design layout diagram2111. In some embodiments, mask fabrication2122includes performing one or more lithographic exposures based on IC design layout diagram2111. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)2123based on the modified IC design layout diagram2111. Mask2123can be formed in various technologies. In some embodiments, mask2123is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (for example, photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask2123includes a transparent substrate (for example, fused quartz) and an opaque material (for example, chromium) coated in the opaque regions of the binary mask. In another example, mask2123is formed using a phase shift technology. In a phase shift mask (PSM) version of mask2123, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication2122is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer2133, in an etching process to form various etching regions in semiconductor wafer2133, and/or in other suitable processes. IC fab2130includes wafer fabrication2132. IC fab2130is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab2130is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business. IC fab2130uses mask(s)2123fabricated by mask house2120to fabricate IC device2140. Thus, IC fab2130at least indirectly uses IC design layout diagram2111to fabricate IC device2140. In some embodiments, semiconductor wafer2133is fabricated by IC fab2130using mask(s)2123to form IC device2140. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram2111. Semiconductor wafer2133includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer2133further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps). Moreover, various circuits or devices to implement the transistors in the aforementioned embodiments are within the contemplated scope of the present disclosure. In some embodiments of this document, at least one of the transistors is implemented with at least one MOS transistor, at least one bipolar junction transistor (BJT), etc., or the combination thereof. Various circuits or devices to implement the transistors in the aforementioned embodiments are within the contemplated scope of the present disclosure. In some embodiments, a semiconductor device is disclosed and includes a first cell. The first cell is surrounded by a castle-shaped forbidden region. The first cell includes a first active region, a second active region, and at least one via. The first active region and the second active region extend along a first direction and are separated from each other along a second direction traverse to the first direction. The first active region partially overlaps an upper region of the castle-shaped forbidden region, and the second active region partially overlaps a lower region of the castle-shaped forbidden region. The at least one via is arranged outside the castle-shaped forbidden region. In some embodiments, a portion of the first active region overlaps the upper region. A portion of the second active region overlaps the lower region. The portion of the first active region and the portion of the second active region align with each other along the second direction. In some embodiments, the semiconductor device further includes a second cell abutting the first cell along the second direction. A boundary between the first cell and the second cell is arranged between first portions of the upper region and second portions of the upper region. The first portions of the upper region overlap the first cell and the second portions of the upper region overlap the second cell. In some embodiments, the first and second portions of the upper region are arranged in a staggered manner along the first direction. In some embodiments, the first portions of the upper region and first portions of the lower region are aligned with each other along the second direction. The second portions of the upper region and second portions of the lower region are aligned with each other along the second direction. In some embodiments, the first cell further includes multiple strip structures. The strip structures extend along the second direction and are separated from each other along the first direction. The strip structures partially abut or overlap the castle-shaped forbidden region. In some embodiments, the first cell further includes multiple conductive structures. The conductive structures extend along the first direction. The at least one via is coupled to one of the conductive structures. Each of the strip structures partially abuts the upper region and the lower region. In some embodiments, the at least one via is coupled to one of the strip structures. Odd-number strip structures of the strip structures partially overlap with the upper region and the lower region. In some embodiments, a method is disclosed and includes: forming multiple strip structures within a first cell, wherein the strip structures extend along a first direction and are separated from each other along a second direction different from the first direction, and odd-number strip structures of the strip structures partially overlap with a first serpentine forbidden portion abutting a first boundary between the first cell and a second cell; forming a first via within a first region of the second cell, wherein three sides of the first region abut the first serpentine forbidden portion; and forming a second via that is within the first cell and outside the first serpentine forbidden portion. In some embodiments, the odd-number strip structures of the strip structures partially overlap with a second serpentine forbidden portion abutting a second boundary between the first cell and a third cell. In some embodiments, even-number strip structures of the strip structures are arranged outside the first serpentine forbidden portion and the second serpentine forbidden portion. In some embodiments, the first serpentine forbidden portion and the second serpentine forbidden portion are symmetrical with respect to a line between the first boundary and the second boundary. In some embodiments, the method further includes: forming a first active region and a second active region that extend along the second direction and are separated from each other along the first direction. The first active region partially overlaps the first serpentine forbidden portion, and the second active region partially overlaps the second serpentine forbidden portion. In some embodiments, a portion of the first active region overlaps the first serpentine forbidden portion. A portion of the second active region overlaps the second serpentine forbidden portion. The portion of the first active region and the portion of the second active region align with each other along the first direction. In some embodiments, a portion of the first cell overlaps the first serpentine forbidden portion. A portion of the second cell overlaps the first serpentine forbidden portion. The portion of the first cell and the portion of the second cell are arranged in a staggered manner along the second direction on the first boundary. In some embodiments, a method is disclosed and includes: forming at least one first via in a first region abutting multiple forbidden regions; forming at least one second via in a second region that is different from the first region and abuts the forbidden regions; and forming multiple conductive structures, wherein one of the conductive structures is coupled to the at least one second via. The forbidden regions are arranged on two sides of a cell boundary. In some embodiments, three sides of the first region abut the forbidden regions. Three sides of the second region abut the forbidden regions. In some embodiments, the first region and the second region are arranged on the two sides of the cell boundary and are arranged in a diagonal manner. In some embodiments, the conductive structures extend along a first direction and are separated from each other along a second direction traverse to the first direction. Each of the conductive structures partially abuts the forbidden regions. In some embodiments, odd-number conductive structures of the conductive structures partially overlap with the forbidden regions. Even-number conductive structures are arranged outside the forbidden regions. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 132,084 |
11942471 | DETAILED DESCRIPTION In the following embodiments, when required for convenience, the description will be made by dividing into a plurality of sections or embodiments, but except when specifically stated, they are not independent of each other, and one is related to the modified example, detail, supplementary description, or the like of part or all of the other. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to the specific number, but may be not less than or equal to the specific number, except for cases where the number is specifically indicated and is clearly limited to the specific number in principle. Furthermore, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are specifically specified and the case where they are considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of components and the like, it is assumed that the shapes and the like are substantially approximate to or similar to the shapes and the like, except for the case in which they are specifically specified and the case in which they are considered to be obvious in principle, and the like. The same applies to the above numerical values and ranges. Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same functions are denoted by the same reference numerals, and repetitive descriptions thereof are omitted. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle except when particularly necessary. First Embodiment Configuration of Semiconductor Device FIG.1Ais a plan view showing an example of a schematic configuration of a main part of a semiconductor device according to a first embodiment of the present disclosure.FIG.1Bis a diagram showing an example of an equivalent circuit of the semiconductor device inFIG.1A. The semiconductor device1shown inFIG.1Aincludes one semiconductor chip10in which a power device is formed. The power device may be an IGBT or a MOSFET. In the specification, as shown inFIG.1B, the case where the power device PWD is an IGBT is mainly taken as an example. The semiconductor chip10shown inFIG.1A, in the main surface, includes an intermediate electrode (third electrode) ME, in addition to a gate electrode (first electrode) GE, a gate wiring GL extending from the gate electrode GE, and an emitter electrode (second electrode) EE. Further, the semiconductor chip10, on the back surface facing the main surface, includes a collector electrode CE. Each electrode is made of, for example, a metal material typified by aluminum or the like. The gate electrode GE, the emitter electrode EE and the collector electrode CE are connected to the gate, emitter and collector of the power device PWD, respectively, as shown inFIG.1B. Further, the semiconductor chip10shown inFIG.1Aincludes a protection element forming region15. As shown inFIG.1B, a gate protection element DD is formed in the protection element forming region15. The gate protection element DD is, in this example, a cathode common type bidirectional Zener diode provided between two nodes N1and N2. The bidirectional Zener diode includes a plurality of stages of p-n junctions formed between the two nodes N1and N2. The gate protection element DD may not necessarily be limited to a bidirectional Zener diode, and may include a plurality of stages of p-n junctions. Further, the bidirectional diode may be an anode common type instead of the cathode common type. The node N1of the gate protection element DD is connected to the intermediate electrode ME through a contact hole40, as shown inFIGS.1A and1B. On the other hand, when one of the gate electrode GE and the emitter electrode EE is a target electrode and the other is a non-target electrode, the node N2of the gate protection element DD is connected to the target electrode through the contact hole40. In the example ofFIGS.1A and1B, the target electrode is the gate electrode GE, and the non-target electrode is the emitter electrode EE. Thus, by providing the intermediate electrode ME, the gate protection element DD, in the semiconductor chip10, is not connected between the gate electrode GE and the emitter electrode EE. As shown inFIG.1A, for example, a plurality of unit cells CU arranged in a matrix in the X-axis direction and Y-axis direction is formed in the lower layer region of the emitter electrode EE in the semiconductor chip10. As shown inFIG.1B, each of the plurality of unit cells CU is the IGBT. Then, the plurality of IGBTs constitute one power device PWD as a whole by connecting each of the terminals of the IGBTs in parallel within the semiconductor chip10. Incidentally, when the power device PWD is a MOSFET, the emitter electrode EE and the collector electrode CE, respectively, a source electrode connected to the source of the MOSFET, and a drain electrode connected to the drain of the MOSFET. Details of Unit Cell and Gate Protection Element FIG.2is a cross-sectional view showing an example of a configuration between A-A′ inFIG.1A.FIG.2shows an example of a configuration of the unit cell CU inFIGS.1A and1B. InFIG.2, the collector electrode CE is formed on the back surface of the semiconductor chip10. The emitter electrode EE is formed on the main surface of the semiconductor chip10. Further, on the main surface side of the semiconductor chip10, two trench gate layers31are formed side by side in the X-axis direction. The gate insulating film32is formed on the surfaces of the two trench gate layers31. The trench gate layer31is connected to the gate wiring GL shown inFIG.1A. The unit cell CU in the semiconductor chip10is divided into an active region20and an inactive region21. The active region20, in the X-axis direction, is a region sandwiched between the two trench gate layers31, and the region where an emitter current flows. On the other hand, the inactive regions21, in the X-axis direction, are regions provided on both sides of the active region20. As shown inFIG.1, by arranging such a unit cell CU side by side in the X-axis direction, the active region20, in the X-axis direction, will be disposed at a certain interval. In the active region20, an N+ type emitter layer23n, a P type body layer25p, an N type hall barrier layer27n, an N− type drift layer28n, an N type field stop layer29n, and a P+ type collector layer30pare formed in this order from the emitter electrode EE to the collector electrode CE. On the other hand, in the inactive region21, an interlayer insulating film24, the body layer25p, a P type floating layer26p, the N− type drift layer28n, the N type field stop layer29n, and the P+ type collector layer30pare formed in this order from the emitter electrode EE to the collector electrode CE. A contact hole22is formed in the interlayer insulating film24, the emitter layer23nis formed in the contact hole22, and further, the emitter electrode EE is laminated. The structure as shown inFIG.2is called, for example, an Injection Enhancement (IE) type trench gate IGBT or the like. That is, by providing the inactive regions21on both sides of the active region20, IE effect that carriers are accumulated on the emitter side in the drift layer28noccurs. As a result, it is possible, for example, to reduce an on-voltage between the emitter and the collector. In the Y-axis direction ofFIG.1A, in a region between the neighboring unit cells CU, instead of the N+ type emitter layer23ninFIG.2, a P type body contact layer that connects the P type body layer25pto the emitter electrodes EE is provided. FIG.3is a cross-sectional view showing an example of a configuration between B-B′ inFIG.1A.FIG.3shows an example of a configuration of the gate protection element DD ofFIG.1Bformed in the protection element forming region15ofFIG.1A. InFIG.3, a field insulating film44is formed in the main surface side of the semiconductor chip10. The gate protection element DD is formed on the field insulating film44. The gate protection element DD includes the two nodes N1and N2, P+ type semiconductor layers42pand N+ type semiconductor layer43nwhich are alternately arranged in the X-axis direction between the two nodes N1and N2. Thus, the gate protection element DD is, in this example, a bidirectional Zener diode including a plurality of stages of p-n junctions formed between the two nodes N1and N2. The number of stages of the p-n junctions is an even number, and accordingly, the two nodes N1and N2are configured by semiconductor layers of the same conductive type. In the example ofFIG.3, the number of stages of the p-n junction is six, and the two nodes N1and N2are the P+ type semiconductor layers42p. An interlayer insulating film41is formed on the gate protection element DD. The two contact holes40are formed in the interlayer insulating film41so as to reach the two nodes N1and N2of the gate protection element DD. Further, the intermediate electrode ME is formed on the upper layer of the node N1, and the gate electrode GE is formed on the upper layer of the node N2. As a result, the node N1of the gate protection element DD is connected to the intermediate electrode ME through the contact hole40, and the node N2of the gate protection element DD is connected to the gate electrode GE through the contact hole40. The configuration of the back surface side of the semiconductor chip10inFIG.3is the same as the example of the configuration ofFIG.2. Incidentally, when the anode common type rather than the cathode common type is used as the bidirectional Zener diode constituting the gate protection element DD, the conductive types of the semiconductor layers42pand43ninFIG.3may be replaced with each other. Also, when the MOSFET rather than the IGBT is used as the unit cell CU, the emitter electrode EE, the emitter layer23nand the collector electrode CE ofFIG.2, respectively, are replaced with the source electrode, the source layer and the drain electrode. Further, in this case, for example, the inactive region21, the collector layer30p, and the hole barrier layer27nare not necessary, and the field stop layer29nis configured to be an N+ type drain layer. Manufacturing Method of Semiconductor Device FIG.4is a flowchart showing an example of main processes in a manufacturing method of the semiconductor device according to the first embodiment of the present disclosure. InFIG.4, at first, a predetermined semiconductor manufacturing apparatus performs a wafer process in a step S11. The wafer process in the step S11includes a process of forming the power device PWD (step S111), a process of forming each electrode (step S112), and a process of forming the gate protection element DD (step S113). In the step S111, for example, a plurality of semiconductor chips10including the unit cell CU in which the emitter electrode EE is removed fromFIG.2is formed on a semiconductor wafer. In the step S112, the gate electrode GE, the intermediate electrode ME, the emitter electrode EE, and the like as shown inFIGS.2and3are formed. In the step S113, the gate protection element DD as shown inFIG.3is formed. Incidentally, strictly, after the gate protection element DD is formed in the step S113, the gate electrode GE and the intermediate electrode ME is formed in step S112, so as to connect to the gate protection element DD through the contact hole40. Subsequently, in a step S12, a probe inspection apparatus performs a probe test for the semiconductor wafer on which the wafer process of the step S11has been performed. Next, in a step S13, the probe inspection apparatus or the like determines a quality for each semiconductor chip10in the semiconductor wafer based on the result of the probe test. Then, in a step S14, a predetermined assembly apparatus performs assembly to a package for the semiconductor chip10which is determined to be a non-defective in the step S13. After that, a test or the like for the assembled semiconductor device is performed. Details of Probe Test Process FIG.5Ais a diagram explaining an example of a probe test process inFIG.4, andFIG.5Bis a supplementary diagram ofFIG.5A. InFIG.5A, an example of a configuration in which the periphery of the protection element forming area15inFIG.1Ais extracted is shown. InFIG.5B, an example of an equivalent circuit at the time of testing inFIG.5Ais shown. In the step S12ofFIG.4, as shown inFIGS.5AandFIG.5B, a state in which a probe50gis in contact with the gate electrode GE and a probe50eis in contact with the emitter electrode EE is constructed. Then, the probe inspection apparatus applies a voltage between the gate electrode GE and the emitter electrode EE through the probes50gand50eand measures a current. Here, in the semiconductor device serving as a comparative example as shown in Patent Document 1, the intermediate electrode ME, for example, inFIGS.1A and1B, is not provided, and the gate protection element DD between the gate electrode GE and the emitter electrode EE is configured to be connected. In this case, when a voltage is applied between the gate electrode GE and the emitter electrode EE, a reverse current flows to the p-n junction included in the gate protection element DD. The probe inspection apparatus measures the combined current of the reverse current and the leakage current between the gate and the emitter caused by the abnormality of the gate insulating film32ofFIG.2. Consequently, in the semiconductor device as the comparative example, there is a possibility that the abnormality of the gate insulating film32cannot be detected with high accuracy. For example, under normal conditions, the reverse current may be in the order of μA, and the leakage current of the gate insulating film32may be in the order of pA-nA. In this case, for example, even if the leakage current of the gate insulating film32is slightly increased due to a slight abnormality, the leakage current may be buried in the reverse current, and the increase in the leakage current may not be detected. Incidentally, examples of the abnormality of the gate insulating film32include contamination of foreign matter and local thinness of the film thickness. On the other hand, in the semiconductor device1according to the first embodiment, by providing the intermediate electrode ME, the gate protection element DD is not connected between the gate electrode GE and the emitter electrode EE. As a result, it becomes possible to detect the abnormality of the gate insulating film32with high accuracy. For example, it is possible to detect a slight abnormality occurring in the gate insulating film32. Also, in the probe test, an accelerated test may be performed, such as measuring the leakage current between the gate and the emitter after applying a voltage for acceleration test between the gate and the emitter for a certain period of time. When the semiconductor device1according to the first embodiment is used, for example, it becomes possible to detect an abnormality of the gate insulating film32that may cause a detection omission in this acceleration test. FIG.6is a diagram explaining an example of another probe test process inFIG.4. InFIG.6, a state in which the probe50gis in contact with the gate electrode GE which is the target electrode, and a probe50mis in contact with the intermediate electrode ME is constructed. The probe inspection apparatus applies a voltage between the gate electrode GE which is the target electrode and the intermediate electrode ME through the probes50gand50mand measures a current. Thus, for example, an abnormality of the gate protection element DD typified by an open defect or the like in the contact hole40ofFIG.3is detectable. Details of Assembly Process FIG.7is a diagram explaining an example of an assembly process inFIG.4. InFIG.7, an example of a configuration of the semiconductor device1after the semiconductor chip10is assembled into a package is shown. The semiconductor device1shown inFIG.7includes a die pad60which is a part of the package for sealing the semiconductor chip10, three external terminals PNg, PNc, and PNe which are external terminals of the package, and metallic wiring members62g,62m, and62e, in addition to the semiconductor chip10. The wiring members62g,62m, and62eare typically bonding wires, plate members, or the like. The external terminal (first external terminal) PNg is a lead for the gate, and the external terminal (second external terminal) PNe is a lead for the emitter. The external terminal PNc is a lead for the collector, and has a configuration connected to the die pad60. A region surrounded by, for example, a V-shaped groove61is formed in the die pad60, the semiconductor chip10is mounted in this region via a metal paste material. The wiring member (first wiring member)62gconnects the gate electrode GE and the external terminal PNg. The wiring member (second wiring member)62econnects the emitter electrode EE and the external terminal PNe. The wiring member (third wiring member)62mconnects the intermediate electrode ME and the emitter electrode EE which is the non-target electrode. In the assembled semiconductor device1, the gate protection element DD is, by the wiring member62m, connected between the external terminal PNg which is the lead for the gate and the external terminal PNe which is the lead for the emitter. In the assembly process (step S14) ofFIG.4, the predetermined assembly apparatus assembles the semiconductor chip10into, for example, a package as shown inFIG.7. Modification of Assembly InFIG.7, the wiring member62mfor connecting the intermediate electrode ME and the emitter electrode EE is provided, but the semiconductor device1ofFIG.7may be configured so that the wiring member62mis not provided. In this case, the intermediate electrode ME is electrically open to the emitter electrode EE which is the non-target electrode. For example, the gate protection element DD may not be required depending on what kind of circuit the power device PWD is incorporated into. Or, without using the gate protection element DD incorporated in the semiconductor chip10, a gate protection element may be separately provided as an external component of the assembled semiconductor device1. In such a case, a configuration in which the wiring member62mis not provided may be used. That is, by using the same semiconductor chip10and selecting whether to provide the wiring member62m, substantially, it becomes possible to realize the semiconductor device1incorporating the gate protection element DD and the semiconductor device1not incorporating the gate protection element DD. Thus, by realizing the two types of the semiconductor device1on sharing the semiconductor chip10, for example, it is possible to reduce the cost. Main Effects of First Embodiment As described above, by using the method of the first embodiment, typically, an abnormality of the gate insulating film32can be detected with high accuracy. Consequently, the reliability of the semiconductor device1is enhanced. Further, for example, in order to be able to detect the abnormality of the gate insulating film32with high accuracy, it is also conceivable to use a semiconductor device that does not incorporate the gate protection element DD. In this case, in order to ensure an ESD breakdown voltage to some extent, for example, it may be necessary to take measures such as increasing the size of the semiconductor chip. On the other hand, by using the method of the first embodiment, since the abnormality of the gate insulating film32can be detected with high accuracy while incorporating the gate protection element DD, it is possible to contribute to miniaturization of the semiconductor chip. Second Embodiment Configuration of Semiconductor Device FIG.8Ais a plan view showing an example of a schematic configuration of a main part of a semiconductor device according to a second embodiment of the present disclosure.FIG.8Bis a diagram showing an example of an equivalent circuit of the semiconductor device inFIG.8A. The semiconductor device1shown inFIG.8Aincludes a semiconductor chip10athat differs fromFIG.1A. Arrangement of a protection element forming region15aof the semiconductor chip10ais different from the arrangement of the protection element forming region15in the example of the configuration ofFIG.1A. As shown inFIG.8B, the same gate protection element DD as in the case ofFIG.1Bis formed in the protection element forming region15a. Further, as in the case ofFIGS.1A and1B, the node N1of the gate protection element DD is connected to the intermediate electrode ME through the contact hole40, and the node N2of the gate protection element DD is connected to the target electrode through the contact hole40. However, inFIGS.8A and8B, contrary to the case ofFIGS.1A and1B, the target electrode is the emitter electrode EE and the non-target electrode is the gate electrode GE. When assembling such a semiconductor chip10a, for example, the wiring member (third wiring member)62minFIG.7connects the intermediate electrode ME and the gate electrode GE which is the non-target electrode. In addition, as described above, when using a configuration that does not provide the wiring member62m, the intermediate electrode ME is electrically open to the gate electrode GE which is the non-target electrode. Further, with respect to the probe test process (step S12) ofFIG.4, inFIG.6, a voltage is applied between the intermediate electrode ME and the emitter electrode EE which is the target electrode. Main Effects of Second Embodiment As described above, even by using the method of the second embodiment, the same effects as the various effects described in the first embodiment can be obtained. It may be determined whether any method of the first embodiment or the second embodiment is used based on, for example, the ease of layout of the semiconductor chip, the ease of securing the area required for the protection element forming region, the ease of wiring using the wiring member62mas shown inFIG.7, or the like. Third Embodiment Configuration of Semiconductor Device FIG.9is a plan view showing an example of a schematic configuration of a main portion of a semiconductor device according to a third embodiment of the present disclosure.FIG.10is a plan view showing an example of a schematic configuration of a main part of a semiconductor device that differs fromFIG.9. The arrangement of the intermediate electrode ME is not limited to the arrangement shown inFIG.1A or8A, and can be appropriately changed as shown inFIG.9or10. For example, in the arrangement example ofFIG.1A or8A, it is necessary to secure a space for arranging the intermediate electrode ME between the gate electrode GE and the emitter electrode EE in the X-axis direction. On the other hand, in arrangement examples ofFIGS.9and10, utilizing an empty area where the gate electrode GE and the emitter electrode EE are not arranged, the intermediate electrode ME is arranged in the empty region. In an example of a semiconductor chip10bofFIG.9, the intermediate electrode ME is arranged in an empty region around the gate electrode GE, and a protection element forming region15bis provided between the gate electrode GE and the intermediate electrode ME. In an example of a semiconductor chip10cofFIG.10, the intermediate electrode ME is arranged in an empty area around the emitter electrode EE, and a protection element forming region15cis provided between the emitter electrode EE and the intermediate electrode ME. Thus, when there is an empty area in the semiconductor chip10aor10b, by arranging the intermediate electrode ME in the empty area, it is possible to increase the layout efficiency and contribute to miniaturization of the semiconductor chip10. It should be noted that the same empty area as inFIG.9and the like exists inFIG.1Aand the like. However, when the arrangement example such as the shownFIG.1Aor the like is used, for example, the emitter electrode EE may be extended to the empty region, and the unit cell CU may be arranged in the lower layer of the emitter electrode EE. Although the invention made by the present inventors has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof. | 24,734 |
11942472 | DETAILED DESCRIPTION The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. More specifically, in exemplary embodiments, the high-voltage ESD device(s) comprises a vertical silicon-controlled rectifier (SCR) combined with a vertical NPN device. In embodiments, the SCR and NPN each includes an n+ buried layer (NBL), which is split by a p+ isolation region. Advantageously, the high-voltage ESD device provides high current performance for high-voltage applications, with relatively high holding voltage for high-voltage applications while keeping high current performance. In addition, the high-voltage ESD devices described herein save significant chip area compared to a structure with an equivalent performance. In embodiments, the ESD device may be a combination of a vertical SCR and vertical NPN (or PNP) to provide a high voltage and high current performance ESD device. The SCR and NPN may be connected through a buried n+ layer (NBL) split by a p+ isolation region. In embodiments, the NBL and p+ isolation region will form a lateral NPN device. Also, the addition of the p+ isolation region will enable a high holding voltage due to an increase in resistance. In embodiments, the vertical NPN comprises a collector (n+ region), a base (p-type well) and an emitter (n+ diffusion) at the cathode region; whereas the SCR may include a p-field junction at a bottom of a n-type high voltage double diffusion drain (HVNDDD) for a high voltage device at the anode region. A base resistor can also be provided on the cathode side of the device, tapping to the p-well and which provides for fast triggering. The ESD devices of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the ESD devices of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the ESD devices uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. FIGS.1A-1Fshow intermediate structures and a final structure of a high-voltage ESD device and respective fabrication processes in accordance with aspects of the present disclosure. In particular,FIG.1Ashows a structure10comprising a substrate12. In embodiments, the substrate12may be a p+ substrate composed of any suitable semiconductor material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. The substrate12includes n+ regions14, e.g., discontinuous n+ regions. In embodiments, the n+ regions14may be formed by introducing a dopant by, for example, using an ion implantation process as shown representatively by arrows22. In embodiments, the n+ regions14may be a discontinuous layer of n+ doped material (separated or split by isolation regions as discussed with respect toFIG.1B). In the ion implantation process, the n+ regions14may be formed by introducing a concentration of a dopant of n+ dopant type in the substrate12using a patterned implantation mask20to define selected areas exposed for the implantation. The n-type dopants used in the n+ regions14may include, e.g., Arsenic (As), Phosphorus (P) and Sb, among other suitable examples, at a dopant dose concentration of approximately 1E18 cm−3to 5E20 cm−3. The implantation mask20may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask20has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. InFIG.1B, the implantation mask20is stripped and another implantation mask20amay be deposited and patterned to define selected areas exposed for the implantation of p+ dopants for isolation region16. In embodiments, the isolation region16will split or separate adjacent n+ regions14. The isolation region16may be doped with p-type dopants, e.g., Boron (B), among other suitable examples, as shown representatively at arrows22a. The dopant dose concentration may be approximately 1E18 cm−3to 5E20 cm−3. In embodiments, the isolation region16provides an isolation region between the adjacent n+ regions14, which can be used to effectively increase the resistance of the device. InFIG.1C, an epitaxial semiconductor material17may be grown on the substrate12and, more specifically, over the n+ regions14and the isolation region16. In embodiments, the epitaxial semiconductor material17may be an n+ type semiconductor material which buries the n+ regions12and isolation region16within the substrate material, e.g., semiconductor material12,17. In alternative embodiments, the substrate12may be thicker so that the upper portion may undergo an ion implantation process with an n+ type dopant, e.g., at a concentration of approximately 1E15 cm−3to 5E17 cm−3. In either scenario, the semiconductor material17may be used for n-well and p-well structures as described in more detail herein. A p-well18may be formed within the semiconductor material17, which is in electrical contact with the n+ region14(hereinafter referred to as an n+ buried layer (NBL)). In embodiments, the p-well18is a high-voltage p-well formed using p-type dopants, e.g., Boron (B). As with any of the well regions described herein, the high-voltage p-well18may be formed by deposition of an implantation mask20c(similar to the mask described above), followed by a patterning process to form an opening and, thereafter, an ion implantation process of certain dopant type, e.g., p-type dopant for the p-wells, shown representatively by arrows24, e.g., at a concentration of approximately 4E16 cm−3to 2E18 cm−3. Referring toFIG.1D, a p-well26may be formed in the p-well18. In embodiments, the p-well26may be a p-type high-voltage double diffusion drain (HVPDDD), formed using an ion implantation process with an appropriate implantation mask as already described herein such that no further explanation is required for a complete understanding of the present disclosure. In embodiments, the p-well18may have a dopant dose concentration of, e.g., approximately 1E16 cm−3to 4E18 cm−3. An n-well28may be formed in the substrate17, remote from the p-wells18,26. In other words, the n-well28may be separated from the p-wells18,26by the substrate17. In embodiments, the n-well28may be an n-type high-voltage double diffusion drain (HVNDDD) formed by using an ion implantation process with an appropriate implantation mask as already described herein. In embodiments, the n-well28may have lower dopant dose concentration to control breakdown voltage, e.g., of approximately 5E15 cm−3to 4E18 cm−3. A p-buried layer30may be formed below the n-well28. In embodiments, the p-buried layer30makes contact (e.g., electrical contact) to both the NBL14and the n-well28. The p-buried layer30may be formed using an ion implantation process with a dopant dose concentration of, e.g., approximately 1E16 cm−3to 1E19 cm−3. FIG.1Dshows shallow trench isolation structures32formed in the wells26,28and spanning between the wells26,28. The shallow trench isolation structures32can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over the substrate17is exposed to energy (light) to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to form one or more trenches in the substrate17through the openings of the resist. Following the resist removal by a conventional oxygen ashing process or other known stripants, insulator material, e.g., oxide, can be deposited in the trenches by any conventional deposition processes, e.g., chemical vapor deposition (CVD) process, to form the shallow trench isolation structures32. Any residual insulator material on the surface of the substrate17can be removed by conventional chemical mechanical polishing (CMP) processes. In embodiments, the lateral dimension of the shallow trench isolation region spanning between the wells34,36may be adjusted to provide a high DC breakdown voltage and prevention of a lateral SCR. Also, in embodiments, the shallow trench isolation structures32can be replaced by LOCOS (LOCal Oxidation of Silicon). InFIG.1E, a p-well34and an n-well36may be formed in the substrate17. More specifically, the p-well34may be formed in the p-well26and the n-well36may formed in the n-well28. Again, the wells34,36may be formed by conventional ion implantation processes with appropriate dopant types at a dopant dose concentration of, e.g., approximately 1E17 cm−3to 1E19 cm−3. In addition, p+ doped region38and n+ doped region40may be formed in the p-well34; whereas p+ doped regions38aandn+ doped region40amay be formed in the n-well36using respective p-type dopants and n-type dopants. In embodiments, the doped region40may be an emitter region. Also, the combination of the p-well34, p-well26and p-well18may be a p-type base region. The p+ doped region38and n+ doped region40may be doped at a higher dopant concentration, e.g., 5E19 cm−3to 5E21 cm−3. The structure may undergo a thermal process (e.g., rapid thermal process) for dopant activation and diffusion. In embodiments, the shallow trench isolation structures32located in the n-well36may be provided between the well regions38aand40a. As should be understood by those of skill in the art, the shallow trench isolation structures32may reduce current voltage, which result in a faster turn on of the device. In addition, shallow trench isolation structure (or LOCOS)32ais provided between and separates the different wells34,36. It should be recognized that the combination of regions40,34,26,14,18form a vertical NPN device42. Also, the combination of regions38a,40a,36,28,30and14form a vertical PNPN silicon-controlled rectifier (SCR) device44. In embodiments, the NPN device42and the PNPN SCR device44are separated by the shallow trench isolation region (or LOCOS)32a. In embodiments, the space between the isolation region32amay be large, e.g., approximately 4 to 10 μm or larger, to provide a high DC breakdown voltage and prevention of a lateral SCR. In embodiments, the lateral SCR can lead to high density of current flow due to a narrow current path. Also, the NPN region42may be on a cathode side of the device; whereas the PNPN SCR44may be on the anode side of the device. Moreover, both of these devices42,44will be electrically connected together through the NBL14and isolation region16, e.g., collector. And, by using the p-buried layer30, the PNPN SCR44can have a current performance of approximately 80 mA/um, which is a relatively high current to provide improved performance and high holding voltage (Vh) compared to a conventional high voltage NPN SCR. In addition, by increasing the distance between the wells34,36, it is also possible to control voltage breakdown. As further shown inFIG.1F, a cathode48connects to the NPN device42and an anode50connects to the PNPN SCR device44. Prior to forming contacts of the cathode48and anode50, a silicide block layer46may be formed over portions of the structure including, e.g., completely blocking the p+ doped region38bof the NPN device42. A silicide process may then be performed to form silicide on the remaining active regions38,38a,40and40a. The contacts of the cathode48and anode50are composed of metal contacts. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over fully formed and patterned devices (e.g., doped or ion implanted regions38,38a,40,40a). After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active regions of the device (e.g., doped or ion implanted regions38,38a,40,40a) forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. The non-silicided p+ doped region38bwill be a floating p-type region between the cathode48and the shallow trench isolation region32a, adjacent to the anode50. The dimensions (e.g., width) of the floating p-type region can be adjusted for preventing a lateral SCR making current flow in a vertical direction through the PNPN and NPN. In embodiments, the mask to prevent the p+ doped region38bfrom being silicide will prevent the formation of a lateral SCR for high voltage (Vh) control. Also, by adjusting the width of the p+ doped region38b, it is possible to prevent lateral SCR action, make current flow in the vertical direction through the PNPN and NPN portions of the device, and hence increase holding voltage. Following the silicide process, an insulator material47may be formed over the structure using a conventional deposition process of oxide material, e.g., chemical vapor deposition (CVD) processes. The insulator material47undergoes a conventional etching (RIE) process to form openings exposing the silicide of the regions38,40,38a,40a. Thereafter, contact metal(s), e.g., aluminum, tungsten, etc., may be deposited within openings of the insulator material47to form the contacts for the cathode48and the anode50. In embodiments, the contacts of the cathode48are in direct contact with the doped regions38,40and the contacts of the anode50are in direct contact with doped regions38a,40a. FIG.2shows an ESD device in accordance with additional aspects of the present disclosure. In particular, the ESD device10aofFIG.2includes a resistor52on the contact of the cathode48. For example, the resistor52may be provided on the contact plug for the p+ region38. In embodiments, the resistor52may be a base resistor with a resistance of, e.g., 10 kohm, which enables fast triggering. FIG.3representatively shows electrical current flows through the device ofFIG.2. In particular, the electric current flow is representative shown by the dashed arrows, as it passes from the anode side of the device to the cathode side of the device. In embodiments, the current flow labeled100is a major current path. The current flow will be through both the PNPN SCR device44and NPN device42, by having the current passing through the NBL14and isolation region16. It should be recognized by those of ordinary skill in the art that the current flow will be similar in any of the devices described herein, e.g., from the anode of the side of the PNPN SCR device through the NBL14and isolation region16, to the cathode on the side of the NPN device. It should also be understood by those of skill in the art that the isolation region16will provide an increased resistance of the device to effectively enable a high holding voltage. FIG.4shows an ESD device in accordance with further aspects of the present disclosure. In the ESD device10bofFIG.4, the p+ region38ais provided between the n+ regions40awithin the well region36on the side of the anode50. In this way, the p+ region38ais in the middle of two n+ regions40a. The shallow isolation structures in the well36(e.g., between the p+ region38aand the n+ regions40a) can also be removed in this configuration. The remaining features are the same as with respect toFIG.1E or2. FIG.5shows an ESD device in accordance with further aspects of the present disclosure. In the ESD device10cofFIG.5, resistors52are provided on contacts for the anode side of the device. In embodiments, the resistors52may be base resistors with a resistance of, e.g., 1 kohm, for providing fast triggering and keeping the DC breakdown voltage high. The remaining features are the same as with respect toFIG.4. FIG.6shows yet another ESD device in accordance with aspects of the present disclosure. In the ESD device10dofFIG.6, a single p+ region38cmay be provided within the n-well region36. The single p+ region38cmay be connected to the anode50. Also, as should be recognized by one of ordinary skill in the art, the single p+ region38cwill undergo a silicide process in the area of the connection to the anode50; otherwise, the silicide block layer46will remain over the remaining portions thereof. The remaining features are the same as with respect toFIG.4. FIG.7shows another ESD device in accordance with aspects of the present disclosure. In the ESD device10eofFIG.7, a vertical resistor54formed in the substrate, e.g., semiconductor material12,17, may be provided on a cathode side of the device. In this embodiment, the vertical resistor54may comprise an n-well28aformed in the substrate17, adjacent to the p-wells18,26, in addition to an n-well36aformed in the n-well28a. In embodiments, the wells28a,36amay directly contact at least the well34. It should be understood by those of ordinary skill in the art that the n-wells28a,36amay be formed in the same processes (e.g., using the same blocking masks and ion implantation processes) as the wells28,36. An n+ doped region40cmay be formed in the n-well36a. In this way, the vertical resistor54comprises the n+ doped region40c, wells28a,36aand the NBL14. The remaining features are the same as with respect toFIG.4, including the SCR44, the NPN device42and the lateral NPN, e.g., comprising regions14,16. The ESD devices can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multi-chip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things. The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. | 20,231 |
11942473 | DETAILED DESCRIPTION OF EMBODIMENTS The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. In this description, reference is made to the drawings in which like reference numerals may indicate identical or functionally similar elements. It will be understood that elements illustrated in the figures are not necessarily drawn to scale. Moreover, it will be understood that certain embodiments can include more elements than illustrated in a drawing and/or a subset of the elements illustrated in a drawing. Further, some embodiments can incorporate any suitable combination of features from two or more drawings. Terms such as above, below, over and so on as used herein refer to a device orientated as shown in the figures and should be construed accordingly. It should also be appreciated that because regions within a semiconductor device (such as a transistor) are defined by doping different parts of a semiconductor material with differing impurities or differing concentrations of impurities, discrete physical boundaries between different regions may not actually exist in the completed device but instead regions may transition from one to another. Some boundaries as shown in the accompanying figures are of this type and are illustrated as abrupt structures merely for the assistance of the reader. In the embodiments described below, p-type regions can include a p-type semiconductor material, such as boron, as a dopant. Further, n-type regions can include an n-type semiconductor material, such as phosphorous, as a dopant. A skilled artisan will appreciate various concentrations of dopants in regions described below. To help assure that an electronic system is reliable, manufacturers can test the electronic system under defined stress conditions, which can be described by standards set by various organizations, such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), the Automotive Engineering Council (AEC), and the International Organization for Standardization (ISO). The standards can cover a wide multitude of electrical overstress events as discussed above, including electrostatic discharge (ESD) events and/or electromagnetic interference (EMI) events. Monolithic bi-directional protection devices are provided herein. In certain embodiments, a protection device includes a forward-biased diode and a silicon-controlled rectifier (SCR) that are implemented in a common semiconductor tub to provide protection to one or more pins or pads of an IC interface. For example, the protection device can be used to protect transceiver interface inputs and/or outputs, signal amplifier inputs and/or outputs, and/or data converters inputs and/or outputs. The protection device operates with a small amount of total parasitic capacitance that behaves linearly over the operating voltage range of the IC interface. For example, the forward-biased diode (which can correspond to a base-emitter junction of a bipolar transistor) provides a diffusion capacitance while the SCR provides a depletion capacitance. Although each of these individual capacitances behave non-linearly, collectively the diffusion capacitance of the forward-biased diode and the depletion capacitance of the SCR behave linearly. Accordingly, the protection device is well suited for protecting signal pins of an IC interface for high speed applications sensitive to capacitive loading. For example, the protection device can be used in a variety of applications, including local interconnect network (LIN) interfaces, controller area network (CAN) interfaces, FlexRay interfaces, RS-232 interfaces, RS-485 interfaces, single edge nibble transmission (SENT) interfaces, and/or Automotive Audio Bus (ATB) interfaces, such as A2B devices. In certain implementations, the protection device includes one or more features to achieve low capacitance, for instance, using a diode in series with SCR (which can correspond to a base-to-emitter junction of a bipolar transistor, in some implementations) and/or using a floating n-type well (NW) for the SCR to reduce depletion capacitance between anode and cathode. The SCR itself also incorporated fast turn on features implemented using poly gates to isolate n-type and p-type diffusion regions rather than shallow trench isolation (STI) regions. The protection device operates bi-directionally, thereby providing protection against both positive polarity and negative polarity overstress. In certain implementations, deep n-type well (DNW) forming the semiconductor tub includes DNW isolated diodes used to provide reverse (negative polarity) protection. Furthermore, the DNW isolate diodes can provide additional parallel SCR action that aids in not only making overstress protection more robust, but also in addressing fault conditions arising when the transceiver interface is powered up (for instance, using a 3.3 V or 5 V power supply). Certain protection schemes for transceiver interfaces include a combination of off-chip and on-chip components, which increase component count and capacitance. In contrast, the protection devices herein can be implemented on a single semiconductor IC or chip while still providing robust performance, such as protection against 8000V system level overstress. Accordingly, the benefits of both compact integration and robust performance can be achieved. FIG.1shows a circuit diagram of one example of a transceiver interface20, which can include one or more monolithic bi-directional protection devices described herein. The transceiver interface20includes a first pin1, a second pin2, a transmitter circuit3, a first monolithic bi-directional protection device7a, a second monolithic bi-directional protection device7b, a first n-type metal oxide semiconductor (NMOS) transistor8a, a second NMOS transistor8b, a p-type metal oxide semiconductor (PMOS) transistor9a, a second PMOS transistor9b, a first resistor10a, a second resistor10b, a third resistor10c, a fourth resistor10d, a first diode structure11a, and a second diode structure11b. As used herein and as persons having ordinary skill in the art will appreciate, MOS transistors can have gates made out of materials that are not metals, such as poly silicon, and can have dielectric regions implemented not just with silicon oxide, but with other dielectrics, such as high-k dielectrics. The transceiver interface20can be, for example, an interface IC in which the first and second pins1,2are directly exposed to a user, for instance, connected to car cables or an industrial machinery hardness, in a normal operational environment. The transceiver interface20can be used to communicate data over the interface, such as by using low voltage differential signaling. For clarity of the figures, details related to receiving signals over the first and second pins1,2have been omitted fromFIG.1. The NMOS transistors8a,8band PMOS transistors9a,9bcan be used for electrically transmitting signals over the first and second pins1,2. For example, the transmitter circuit3can be used to control the gate voltages of the NMOS transistors8a,8band PMOS transistors9a,9bto control a differential voltage between the first and second pins1,2. The voltage can have positive or negative polarity. As shown inFIG.1, the transceiver interface20can receive power from a power high supply voltage V2and a power low supply voltage V1. Certain components of the transceiver interface20, such as the NMOS transistors8a,8b, PMOS transistors9a,9b, diode structures11a,11b, and monolithic bi-directional protection devices7a,7bcan be fabricated in a substrate that is biased using a substrate voltage VSUB. Various parasitic substrate devices can be present in the transceiver interface20. The parasitic substrate devices can include terminals electrically connected to the substrate voltage VSUBAbsent protection, the parasitic substrate devices may be damaged during ESD and/or EMI conditions. In the illustrated configuration, the NMOS transistors8a,8binclude parasitic substrate bipolar transistors17a,17b, respectively. Additionally, the PMOS transistors9a,9binclude parasitic substrate diodes18a-18d. Furthermore, the diode structures11a,11binclude parasitic substrate diodes18e,18f, respectively. Although a certain parasitic substrate devices are shown inFIG.1, other configurations of parasitic substrate devices are possible. In some embodiments, the diode structures11a,11b, and parasitic substrate diodes18a-18dmay not be included in the transceiver interface20. For example, in certain implementations, the sources of the PMOS transistors9a,9bmay be directed connected to the power high supply voltage V2and the sources of the NMOS transistors8a,8bmay be directed connected to the power low supply voltage V1. In some embodiments, the backgate of each of the PMOS transistors9a,9bthe NMOS transistors8a,8bmay be connected to their respective sources or driven by a floating well drive. The first monolithic bi-directional protection device7aincludes an anode terminal (A) electrically connected to the first pin1, a cathode terminal (C) electrically connected to the power low voltage V1, and a substrate terminal (SUBST) electrically connected to the substrate voltage VSUB. Additionally, the second monolithic bi-directional protection device7bincludes an anode terminal electrically connected to the second pin2, a cathode terminal electrically connected to the power low voltage V1, and a substrate terminal electrically connected to the substrate voltage VSUB. The first and second monolithic bi-directional protection devices7a,7bcan be used to protect the transceiver interface20from ESD and/or EMI events. The monolithic bi-directional protection devices7a,7bcan protect components of the transceiver interface20including, for example, parasitic substrate devices associated with the components. The transceiver interface20ofFIG.1illustrates one example of a transceiver interface that can be implemented using the monolithic bi-directional protection devices described herein. However, the transceiver interfaces can be implemented in other ways to meet communication protocol constraints. Additionally, although the monolithic bi-directional protection devices have been illustrated in the context of transceiver interfaces, the clamp devices described herein can be used in a wide range of ICs and other electronics, including, for example, industrial control systems, interface systems, power management systems, microelectromechanical system (MEMS) sensor systems, automotive systems, wireless infrastructure systems, and/or digital signal processing (DSP) systems. Additionally, although the transceiver interface20has been illustrated as including two signal pins and two monolithic bi-directional protection devices, more or fewer monolithic bi-directional protection devices and pins can be included to meet system specifications. Furthermore, the monolithic bi-directional protection devices can be connected in other ways. For example, the terminals of the clamp devices can be connected in other ways, such as to other nodes and/or voltages. FIG.2is a graph30showing a relationship between current and voltage of a clamp device according to one embodiment. As described above, a clamp device can include an anode terminal, a cathode terminal, and a substrate terminal. The graph30includes a first plot21corresponding to one example of a clamp device current versus voltage (I-V) relationship when the voltage of the first terminal is varied while the voltages of the second terminal and the substrate terminal are independent and held constant. Additionally, the graph30includes a second plot22corresponding to one example of a monolithic bi-directional protection device response when the voltage of the substrate terminal is varied while the voltage of the first terminal and the second terminal are held constant. As shown inFIG.2, the monolithic bi-directional protection device can transition from a high-impedance state +ZHto a low-impedance state +ZLwhen the voltage difference between the first terminal and the second terminal reaches a positive trigger voltage +VTR. Thereafter, the clamp device can shunt a large amount of current and remain in the low-impedance state +ZLas long as the voltage difference between the first terminal and the second terminal remains above a positive holding voltage +VHOLD. By configuring the monolithic bi-directional protection device to have both a trigger voltage and a holding voltage, the monolithic bi-directional protection device can exhibit enhanced stability against unintended activation. The monolithic bi-directional protection device can also transition from a high-impedance state −ZHto a low-impedance state −ZLwhen the voltage difference between the first terminal and the second terminal reaches a negative trigger voltage −VTR. The monolithic bi-directional protection device can remain in the low-impedance state −ZLas long as the voltage difference between the first terminal and the second terminal remains below the negative holding voltage −VHOLD. Bi-directional operation of the monolithic bi-directional protection device can permit a reduction in layout area relative to a design that uses separate structures (for example, a combination of on-chip and off-chip components) for protection against positive and negative electrical overstress events, thereby enabling a more scalable design solution. As shown inFIG.2, the monolithic bi-directional protection device can be configured to transition to a low-impedance state before the voltage difference between the first terminal and the second terminal reaches either a positive failure voltage +VFor a negative failure voltage −VFthat can otherwise cause damage to the IC. When normal operating voltages are applied to the terminals of the monolithic bi-directional protection device, the monolithic bi-directional protection device should conduct a relatively small leakage current, thereby reducing or minimizing static power dissipation and enhancing the energy efficiency of the IC. Thus, the monolithic bi-directional protection device can be configured to be very low leakage at normal operating voltages and to trigger during electrical overstress events before internal or core devices reach overvoltage conditions. The monolithic bi-directional protection device can also operate with a linear parasitic capacitance, as described herein. As shown by the second plot22, the monolithic bi-directional protection device can be highly isolated from voltage changes to the substrate terminal. For example, in the illustrated example, a positive substrate breakdown voltage +BV to the substrate terminal can be greater than the positive trigger voltage +VTR, and a negative substrate breakdown voltage −BV to the substrate terminal can be beyond the negative trigger voltage −VTR. In certain implementations described herein, a clamp device is implemented to have a forward trigger voltage +VTRin the range of 3 V to 80 V, a forward holding voltage +VHOLDin the range of 2 V to 60 V, a reverse trigger voltage −VTRin the range of −3 V to −80 V, a reverse holding voltage −VHOLDin the range of −2 V to −60 V, a forward substrate breakdown voltage +BV in the range of 15 V to 100 V, and a revere substrate breakdown voltage −BV in the range of −3 V to −80 V. However, other implementations are possible. InFIG.2, voltage is expressed along a horizontal axis, and current is expressed along a vertical axis. In the illustrated embodiment, the clamp device has I-V characteristics that are symmetrical. In other implementations, the clamp devices described herein can have asymmetrical I-V characteristics. For example, clamp devices can have different trigger voltages, holding voltages, and/or failure voltages with different I-V curves in the positive and negative regions of the graph. Electrostatic Discharge Protection Devices for High Speed Transceiver Interfaces Electrical overstress events such as electrostatic discharge (ESD) can damage or destroy integrated circuits (ICs) by generating overvoltage conditions and high levels of power dissipation in relatively small areas of the ICs. Silicon-controlled-rectifier (SCR) device topologies are often considered for ESD protection applications to achieve a higher level of robustness. Aspects of this disclosure relate to ESD protection devices which can be used to protect ICs that meet new high data rates requirements. For example, A2B is a standard for a high data-rate communications, control, and power distribution bus. Successive generations of A2B devices are designed to support increased data rates, which previous ESD protection schemes may not be able to meet. The next generation of A2B devices provide higher data rates, which previous ESD protection device may not be able to meet. In order to meet the data rate and robustness requirements to protect devices implementing certain standards such as A2B, a protection device may include one or more of the following characteristics: +/−8,000 V robustness or higher (e.g., +/−10,000 V), fault tolerance to about 1 A/5 V, about 3 pF linear capacitance or less, and manufactured using a deep submicron CMOS technology. In some implementations, deep submicron may refer to sub 90 nm or sub 65 nm process technologies. In the context of the next generation A2B family of interface products, there is a desired to solve the following technical problems: minimize the number of board-level components by providing for 8,000 V IEC protection on-chip and implement the on-chip 8,000 V protection element to with a low linear capacitance in order to meet the data-rate requirements for the next generation A2B products. In particular, the capacitance of a protection device is related to the amount available bandwidth with lower capacitances increasing the bandwidth. Thus, it is desirable to reduce the capacitance of the protection device in order to meet data-rate (e.g. bandwidth) requirements. It can be difficult to simply use prior larger geometry designs (e.g., 180 nm) scaled for deep submicron processes. Specifically, the scaling of larger geometry designs leads to large capacitance in deep submicron designs. This scaling typically results in capacitance, which is outside of the bandwidth requirements for protection devices. In some embodiments, ESD protection devices for A2B used a combination of off-chip and on-chip protection. However, it is desirable to provide solutions for 8,000 V IEC protection on-chip, reducing the need for off-self components. In addition, in order to meet requirements for increasing data-rates, there is a need for the on-chip 8,000 V protection element to have low linear capacitance. In view of the above technical goals, aspects of this disclosure relate to protection device which includes a monolithic, bi-directional SCR that can address at least some of these problems. In particular, this disclosure relates to an improved monolithic bi-directional SCR that provides +/−8000 V protection using deep submicron design technology. SCRs of such requirement are traditionally manufactured using comparatively larger geometry technology. FIG.3provides an illustration of a symbol which represents the protection device200in accordance with aspects of this disclosure. With reference toFIG.3, the protection device200includes three pins, an anode A, a cathode C, and a substrate pin SUB ST. FIG.4is a cross-section of an embodiment of the protection device200ofFIG.3in accordance with aspects of this disclosure. With reference toFIG.4, the protection device200is fabricated in a p-type substrate (P-SUB)202, and includes a first deep n-type well (DNW)204a, a second DNW204b, a third DNW204c, a fourth DNW204d, and a fifth DNW204e. The protection device200also includes one or more first n-type wells (n-well or NW)206aand206a′, a second n-well206b, a third n-well206c, a fourth n-well206d, a fifth n-well206e, a sixth n-well206f, a seventh n-well206g, an eighth n-well206h, a ninth n-well206i, and a tenth n-well206j. The protection device200further includes a first p-type well (p-well or PW)208a, a second p-well208b, a third p-well208c, a fourth p-well208d, a fifth p-well208e, a sixth p-well208f, and a seventh p-well208g. AlthoughFIG.4illustrates a cross-section of the protection device200, the cross section may not be taken along a straight line. For example, in some implementations the regions formed in the DNW204amay be formed in one area of the protection device layout200with the remainder of the regions formed in a separate area. In the illustrated embodiment, the protection device200is implemented in an multi-finger configuration about an axis205for SCR section inside DNW204a. In particular, a plurality of n-well fingers206a,206a′ are formed in the DNW204awith the p-well208asurrounding each of the n-well fingers206aand206a′. Thus, when viewed from above, the first n-wells206aand206a′ are implemented as fingers surrounded by the first p-well208a. Additionally, the second p-well208bis implemented as a ring surrounding the first n-well206a. Likewise, the other wells of the protection device200are implemented in a multi-finger configuration of when viewed from above. However, other configurations, such as annular arrangements, are possible. The protection device200also includes a first p-type active (P+) region210a(also referred to a p-type diffusion region), a second P+ region210b, a third P+ region210c, a fourth P+ region210d, a fifth P+ region210e, a sixth P+ region210f, a seventh P+ region210g, an eighth P+ region210h, a ninth P+ region210i, a tenth P+ region210j, and an eleventh P+ region210k. The SCR further includes a first n-type active (N+) region212a(also referred to as an n-type diffusion region), a second N+ region212b, a third N+ region212c, a fourth N+ region212d, a fifth N+ region212e, a sixth N+ region212f, a seventh N+ region212g, an eighth N+ region212h, a ninth N+ region212i, and a tenth N+ region212j. The P+ and N+ regions can also be implemented as concentric rings in an annular configuration. Various poly gates214are also depicted over the structure. As described earlier, using poly gates214to isolate adjacent N+ and P+ regions provides faster turn on speed relative to a configuration in which isolation is provided by STI regions. As shown inFIG.4, a resistance RPW associated with resistances between opposing portions of the first p-well208asurrounding the first n-well206ahas been annotated. The protection device200undergoes back end processing to form contacts and metallization. For clarity, electrical connections associated with back end processing are depicted schematically using circuit lines over the cross section. As shown inFIG.4, the anode A is connected to the seventh P+ region210g(which is formed in p-well208c) and the seventh N+ region212g(which is formed p-well208d). The cathode C is connected to the second N+ region212b(which is formed in p-well208a), the fifth P+ region210e(which is formed in p-well208a), and the tenth P+ region210j(which is formed in p-well2080. The substrate pin SUB ST is connected to the sixth P+ region210f(which is formed in p-well208b) and the eleventh P+ region210k(which is formed in p-well208g). In addition, the fourth P+ region210d(which is formed in n-well206a), the fourth N+ region212d(which is formed in n-well206a), and the sixth N+ region212f(which is formed in p-well208c) are electrically connected together using a first conductor (formed in back end metallization); the eighth P+ region210h(formed in p-well208d) and the eighth N+ region212h(formed in p-well208e) are electrically connected together using a second conductor (formed in back end metallization); and the ninth P+ region210i(formed in p-well208e) and the ninth N+ region212i(formed in p-well2080are electrically connected together using a third conductor (formed in back end metallization). FIG.5shows a circuit diagram of the protection device200ofFIG.4in accordance with aspects of this disclosure. The circuit diagram represents a circuit representation of the circuit components present in the cross section of the protection device200ofFIG.4. Correspondence between the circuit diagram and various portions of the cross section are depicted inFIG.5. The circuit diagram of the protection device200includes an anode terminal A, a cathode terminal C, a substrate terminal SUBST, an auxiliary protection diode222, a first reverse parasitic DNW diode224, a second reverse parasitic DNW diode226, and a third reverse parasitic DNW diode228, a positive protection NPN bipolar transistor230, a first reverse protection NPN bipolar transistor232, a second reverse protection NPN bipolar transistor234, a third reverse protection NPN bipolar transistor236, a first positive protection PNP bipolar transistor238, an SCR PNP bipolar transistor240, an SCR NPN bipolar transistor242, and a second positive parasitic protection PNP bipolar transistor244. The SCR PNP bipolar transistor240and the SCR NPN bipolar transistor242include collectors and bases that are cross-coupled to form an SCR246. As shown inFIG.5, the resistor RPW is across the base-to emitter junction of the SCR NPN bipolar transistor242. The protection device200provides three different paths of current conduction during ESD transient events. In response to a positive polarity ESD event, a first path250is formed from the anode A to the cathode C through the positive protection NPN bipolar transistor230(by way of the base-emitter junction) and the SCR246. Also in response to the positive polarity ESD event, a second path252is formed from the anode A to the cathode C through the positive protection NPN bipolar transistor230(by way of the base-emitter junction), the first positive protection PNP bipolar transistor238(from emitter to collector), the P-SUB202, and the second positive protection PNP bipolar transistor244(from emitter to collector). In response to a negative polarity ESD event, a third path254is formed from the cathode C to the anode A through the third reverse protection NPN bipolar transistor236(through the base-emitter junction), the second reverse protection NPN bipolar transistor234(through the base-emitter junction), and the first reverse protection NPN bipolar transistor232(through the base-emitter junction). The first and second paths250and252provide current conduction during positive ESD transients (e.g., when the voltage of the anode A is greater than the voltage of the cathode C), while the third path254provides current conduction during negative ESD transients (e.g., when the voltage of the anode A is less than the voltage of the cathode C). By providing the two separate paths250and252to handle positive ESD transients in the embodiment of the protection device200, the protection device200is able to provide both comparatively high fault tolerance and comparatively high current handling. In addition, the first and second paths250and252are further able to ensure the initial SCR can be designed to have a high holding current and a high holding voltage. This enables the protection element to be substantially immune to any fault condition that may occur on the 5V transmitter interface power up either using a 3.3V or 5V supply. The protection device200is designed using a combination of an SCR having P+ trigger variation with a diode network (e.g., including the diodes224,226, and228) to achieve 8,000 V IEC compliance with decreased capacitance. The protection device200can protect I/O with up to 5 V+ blocking voltage and 3 V+ holding voltage requirements. By constructing a protection device200in accordance with the embodiment illustrated inFIGS.4and5, the resulting protection device200can provide any combination of the following characteristics: +/−8,000 V robustness, fault tolerance to about 1 A/5 V which is achieved by having a tunable holding voltage, 3 pF linear capacitance (which may represent the best in class for 8,000 V compliant device). The above characteristics of the protection device200can also be achieved using a 40 nm CMOS technology using standard process offerings that does not add any additional mask or cost to the product. One advantageous feature of the protection device200is a linearization technique where the integrated layout combines a forward-biased diode (diffusion capacitance) and an SCR246(depletion capacitance) in a single tub such that the capacitance of the whole protection device200network is substantially linear over the operating voltage range. Another advantageous feature is the use of the poly gates214(shown inFIG.5B) to isolate the P+ and N+ regions210and212rather than shallow trench isolation, thereby increasing the speed of the SCR246. The capacitance of the SCR246can also be reduced by floating the second n-well206b. This eliminates a relatively large depletion capacitance present between the anode and the cathode of the SCR246. Yet another advantageous feature is the isolated diode stack224/226/228formed with the DNWs204c-204e, which provide reverse negative direction protection. In addition, the diode222, together with the transistors230and244(which have bases and collectors cross-coupled to form an SCR), provide additional SCR action in parallel to the SCR246. For example, because the diode222is connected between the transistor230and the P-SUB202, the second path252is provided between the anode A and the cathode C. In some embodiments, the additional SCR path252has a 7 V/1 A trigger, and once triggered the holding voltage collapses to 4 V and the power handling drastically reduces. This enables the protection device200to have a smaller lower capacitance while being able to handle 30 A of current. The introduction of the additional SCR path252also allows the initial SCR246to be designed with a higher holding current (1 A)/voltage (6 V). In some embodiments, the additional SCR path252makes the protection device200virtually immune to any fault condition that can occur on a 5 V transceiver interface powered up either using a 3.3 V or a 5 V power supply. Advantageously, since the protection device200provides a monolithic design, the protection device200is able to address the above problems without the use of external protection elements, which reduces the manufacturing costs for the system. The protection device200also has a lower capacitance and takes up a smaller area compared to alternative designs such as a monolithic bipolar protection device, which has a higher capacitance and larger footprint. FIG.6Ais a graph600showing a relationship between current and positive voltage of the protection device200according to one embodiment.FIG.6Bis a graph610showing a relationship between current and negative voltage of the protection device200according to one embodiment. The graphs600and610were generated using 100 ns transmission line pulse (TLP) testing with a 600 pS rise time. FIG.7Ais a graph700showing the DC characterization (anode A to cathode C) of the protection device200according to one embodiment. The DC characterization is shown for each of a plurality of example temperatures (25° C., 85° C., and 125° C.).FIG.7Bis a graph710showing the CV characterization (anode A to cathode C) of the protection device200according to one embodiment. Applications Devices employing the above described schemes can be implemented into various electronic devices. Examples of electronic devices include, but are not limited to, RF communication systems, consumer electronic products, electronic test equipment, communication infrastructure, etc. For instance, RF switches with fast switching can be used in a wide range of RF communication systems, including, but not limited to, base stations, mobile devices (for instance, smartphones or handsets), laptop computers, tablets, Internet of Things (IoT) devices, and/or wearable electronics. The teachings herein are applicable to RF communication systems operating over a wide range of frequencies and bands, including those using time division duplexing (TDD) and/or frequency division duplexing (FDD). CONCLUSION The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected). Although this invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in the context of one embodiment can be incorporated into other embodiments as well. Accordingly, the scope of the present invention is defined only by reference to the appended claims. | 33,691 |
11942474 | Throughout the drawings, the same or like reference numerals represent the same or like elements. DETAILED DESCRIPTION Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are exemplary only and not intended to limit the scope of the present disclosure. In addition, in the following descriptions, descriptions of known structures and techniques might be omitted, so as not to unnecessarily obscure the concepts of the present disclosure. Various structures according to embodiments of the present disclosure are schematically shown in the drawings. These drawings are not drawn to scale, and some details may be enlarged while some details may be omitted for the purpose of clarity. Shapes and relative sizes and positions of various regions and layers shown in the drawings are only illustrative, and there may be deviations due to manufacture tolerances or technical limitations in practice. Those skilled in the art can also devise regions/layers with different shapes, sizes, and relative positions as desired. In the context of the present disclosure, when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intervening layer/element interposed therebetween. In addition, if a layer/element is “on” another layer/element in an orientation, then the layer/element may be “below” the other layer/element when the orientation is turned. A vertical semiconductor device according to embodiments of the present disclosure may comprise a plurality of vertical semiconductor devices stacked on each other on a substrate. The so called “vertical” device means that the device has its active region extending in a vertical direction (for example, in a direction substantially perpendicular to a surface of the substrate). According to embodiments of the present disclosure, the vertical active region of the semiconductor device may comprise a first source/drain layer, a channel layer and a second source/drain layer sequentially stacked. The first source/drain layer and the second source/drain layer may have source/drain regions of the device formed therein, and the channel layer may have a channel region of the device formed therein. An electrically conductive channel may be formed by the channel region between the source/drain regions on opposite ends of the channel region. According to embodiments of the present disclosure, the semiconductor device may be a conventional field effect transistor (FET). In the case of FET, the first source/drain layer and the second source/drain layer (or, the source/drain regions on the opposite ends of the channel layer) may be doped with the same conductivity type (for example, n-type or p-type). An electrically conductive channel may be formed by the channel region between the source/drain regions on the opposite ends of the channel region. Alternatively, the semiconductor device may be a tunneling FET. In the case of the tunneling FET, the first source/drain layer and the second source/drain layer (or, the source/drain regions on the opposite ends of the channel layer) may be doped with different or opposite conductivity types (for example, respectively n-type and p-type). In such a case, charged particles such as electrons can tunnel from the source region through the channel region to the drain region, thus forming a conductive path between the source region and the drain region. Although the conventional FET and the tunneling FET have different conductive mechanisms, both of them present an electrical characteristic that whether to be conductive or not between the source/drain regions can be controlled by a gate. Therefore, for both the conventional FET and the tunneling FET, the terms “source/drain layer (source/drain region)” and “channel layer (channel region)” are used collectively in the descriptions, although there is no general “channel” in the tunneling FET. According to embodiments of the present disclosure, in the case of the tunneling FET, the source/drain layers between the neighboring semiconductor devices may have opposite doping types, thus forming a pn junction. Such a pn junction may be short-circuited by an electrically conductive material such as metal or metal silicide formed on surfaces of the source/drain layers. A gate stack may be formed around at least part of an outer periphery of the channel layer. According to embodiments of the present disclosure, the gate stack may be self-aligned to the channel layer. For example, the gate stack may be substantially coplanar with the channel layer. Especially, a volume occupied by the gate stack may be defined by interfaces between the channel layer and the first and second source/drain layers. In such a case, the gate stack may have an upper surface substantially coplanar with an upper surface of the channel layer, and a lower surface substantially coplanar with a lower surface of the channel layer. The channel layer may be composed of a single crystal semiconductor material to improve device performances. Certainly, the source/drain layers may also be composed of a single crystal semiconductor material. In such a case, the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layers may be eutectic. According to embodiments of the present disclosure, the channel layer may have an etch selectivity with respect to the source/drain layers by, for example, including different semiconductor materials. This is advantageous to respectively processing the channel layer and the source/drain layer by, for example, selectively etching. In addition, the first source/drain layer and the second source/drain layer may have an etch selectivity with respect to each other, so as to be processed respectively. According to embodiments of the present disclosure, a leakage limiting layer or an ON-current enhancement layer may be disposed between the first source/drain layer and the channel layer and/or between the channel layer and the second source/drain layer (in the case of the tunneling FET, especially between the two layers forming a tunneling junction). The leakage limiting layer may have a band gap greater than that of at least one of an overlying layer or an underlying layer adjacent thereto. The ON-current enhancement layer may have a band gap smaller than that of at least one of an overlying layer or an underlying layer adjacent thereto. Due to the difference in band gap, it is possible to suppress the leakage or enhance the ON-current. In a parallel connection, the respective semiconductor devices may be electrically connected between a first electrically conductive channel and a second electrically conductive channel. More specifically, the semiconductor devices each may have one of their respective source/drains electrically connected to the first electrically conductive channel in common, and also the other of their respective source/drains electrically connected to the second electrically conductive channel in common. Additionally, the respective semiconductor devices may have their gates electrically connected to each other. Therefore, in the parallel connection, three common electrically conductive channels may be provided, that is, the first electrically conductive channel and the second electrically conductive channel to which the source/drain layers are connected, and a third electrically conductive channel to which the gate stacks (especially, gate conductor layers therein) are connected. The first to the third electrically conductive channels may be disposed on the outer periphery of the active region. In this way, the source/drain layers and the gate stacks may form the desired electrical connection by extending laterally to corresponding ones of the electrically conductive channels. The electrically conductive channels each may have an extent in the vertical direction to cover the semiconductor devices stacked on each other, so that the source/drain layers and the gate stacks of the respective semiconductor devices can be connected to the corresponding ones of the electrically conductive channels simply by extending laterally. For the convenience of manufacture, the respective electrically conductive channels may extend in the vertical direction (for example, in a direction substantially perpendicular to the surface of the substrate). In addition, in order to avoid mutual interference with each other, the electrically conductive channels may be in different ranges in a circumferential direction of the active region. For example, the electrically conductive channels may be disposed on different sides of the active region, for example, to face each other. For each of the semiconductor devices, the first source/drain layer thereof should be electrically connected to one of the first electrically conductive channel and the second electrically conductive channel, while the second source/drain layer thereof should be electrically connected to the other of the first electrically conductive channel and the second electrically conductive channel. In addition, according to embodiments of the present disclosure, the source/drain layer between two adjacent semiconductor devices may be shared by the two semiconductor devices. That is, for two adjacent semiconductor devices, the second source/drain layer of the lower semiconductor device and the first source/drain layer of the upper semiconductor device may be the same layer (or may be electrically connected to each other), and may be electrically connected to one of the first electrically conductive channel and the second electrically conductive channel. In addition, the first source/drain layer of the lower semiconductor device and the second source/drain layer of the upper semiconductor device may be electrically connected to the other of the first electrically conductive channel and the second electrically conductive channel. As a result, the parallel connection is achieved. Assume that the semiconductor devices are numbered from bottom to top and that the first semiconductor device (namely, the lowermost semiconductor device) has its first source/drain layer connected to the first electrically conductive channel. Then, the first semiconductor device may have its second source/drain layer (also, the first source/drain layer of the second semiconductor device) connected to the second electrically conductive channel, the second semiconductor device may have its second source/drain layer (also, the first source/drain layer of the third semiconductor device) connected to the first electrically conductive channel, the third semiconductor device may have its second source/drain layer (also, the first source/drain layer of the fourth semiconductor device) connected to the second electrically conductive channel, and so on. Therefore, the first source/drain layer of the first semiconductor device, the second source/drain layer of the second semiconductor device (also, the first source/drain layer of the third semiconductor device) . . . may extend laterally towards the first electrically conductive channel. The second source/drain layer of the first semiconductor device (also, the first source/drain layer of the second semiconductor device), the second source/drain layer of the third semiconductor device (also, the first source/drain layer of the fourth semiconductor device) . . . may extend laterally towards the second electrically conductive channel. The source/drain layers extending towards the same electrically conductive channel may be processed in a like way, and thus may have the same material; while the source/drain layers extending towards different electrically conductive channels need to be processed in different ways, and thus may have an etch selectivity with respect to each other. According to embodiments of the present disclosure, at least one of a first contact to the first electrically conductive channel, a second contact to the second electrically conductive channel, or a third contact to the gate stack may be disposed on the top of the active region, and thus at least partially overlaps a main body of the active region (and also the gate stack formed around the channel layer) so as to save a footprint. For example, at least one of the first contact, the second contact, or the third contact may be located inside, at least partially, an area defined by outer peripheries of at least one layer in the active region and the gate stacks formed around the channel layers. The contacts may be connected to the respective electrically conductive channel through bridging parts. Such bridging parts may be formed by an electrically conductive layer disposed on the top surface of the active region, and different bridging parts may be substantially coplanar with each other. According to embodiments of the present disclosure, an isolation layer may be formed on an outer sidewall of the active region and the gate stacks, in order to avoid undesirable electrical connection between the layers in the active region and the gate stacks and the electrically conductive channels. Any layer which needs not to be electrically connected to the electrically conductive channels may have its outer sidewall recessed inwards with respect to a surface of the isolation layer and thus be covered by the isolation layer, and therefore being prevented from contacting the electrically conductive channels so as not to form electrical connection therebetween. On the other hand, any layer which needs to be electrically connected to any of the electrically conductive channels may be exposed at least in a certain region by passing through the isolation layer (especially the sidewall thereof), and thus contact the electrically conductive channel to form electrical connection therebetween. For example, this may be achieved by protruding the layer with respect to the remaining layers at least in the certain region, in which case the isolation layer may expose the layer while covering the remaining layers. Similarly, a dielectric layer may be formed on top of the active region to avoid undesirable electrical connection between the contacts formed on the top of the active region and the uppermost source/drain layer. Such a dielectric layer may be provided by, for example, a hard mask layer to be described later. For example, at least one of the first contact, the second contact, or the third contact may be formed on the dielectric layer. Such a semiconductor device may be manufactured as follows, for example. According to embodiments of the present disclosure, a semiconductor stack including a plurality of source/drain layers disposed sequentially in a vertical direction and two or more channel layers respectively disposed between respective pairs of adjacent ones of the source/drain layers may be disposed on a substrate. For example, this may be achieved by alternately stacking the source/drain layers and channel layers. For example, these layers may be formed by epitaxy. At least one pair of adjacent ones of the layers, which are epitaxially grown respectively, may have a clear crystal interface therebetween. In addition, the layers may be doped respectively, so that at least one pair of adjacent ones of the layers may have a doping concentration interface therebetween. In addition, as described above, the source/drain layer between the channel layers may be doped into the same type as a whole, and thus can be shared by the channel layers overlying and underlying it; or alternatively, the source/drain layer may include sub-layers, for example, two sub-layers, and at least some of the sub-layers may be doped into different types. For one same channel layer, the source/drain layers or the sub-layers overlying and underlying it may be doped into the same conductivity type (the conventional FET) or opposite conductivity types (the tunneling FET). An active region may be defined in the above described semiconductor stack. For example, the respective layers of the stack may be selectively etched into desired shapes in sequence. Generally, the active region may be in a columnar shape, and the respective layers may be relatively recessed or protruded so as to form desired electrical contact with subsequently formed electrically conductive channels, as described above. Then, gate stacks may be formed around at least part of outer peripheries of the respective channel layers. An isolation layer may be formed on outer peripheries of the stack and the gate stacks, so as to encapsulate sidewalls for which electrical connection is unnecessary and to expose sidewalls for which electrical connection is desired. Then, electrically conductive channels contacting the sidewalls exposed at the isolation layer may be formed on a sidewall of the isolation layer, and contacts contacting the electrically conductive channels may be formed on the top of the stack. Since the respective layers in the stack and the gate stacks may need to be relatively recessed or protruded, a hard mask layer may be provided on top of the stack in order to facilitate patterning. The hard mask layer may define a main body of the active region. A specific one of the layers may be relatively recessed by being selectively etched (and thus the remaining layers are relatively protruded with respect to this layer). In the subsequent process, with an outer peripheral sidewall of the hard mask layer as a reference, those layers that do not need to be relatively protruded may have their respective outer peripheral sidewalls recessed inwards with respect to the outer peripheral sidewall of the hard mask layer, while those layers that need to be relatively protruded may have their respective outer peripheral sidewalls be substantially coplanar with the outer peripheral sidewall of the hard mask. In forming the isolation layer, the hard mask layer may also be used as a mask. In this way, the outer peripheral sidewall of the isolation layer may also be substantially coplanar with the outer peripheral sidewall of the hard mask layer, and thus expose the outer peripheral sidewalls of the relatively protruding layers. For example, the hard mask layer may be used as a mask to pattern the stack. Then, the channel layers may be selectively etched, such that outer peripheries thereof may be recessed inwards with respect to the outer periphery of the hard mask layer. Sacrificial gates may be formed in recesses of the respective channel layers with respect to the outer periphery of the hard mask layer. In a first range in the circumferential direction of the active region in which a first electrically conductive channel is to be formed, the source/drain layers to be connected to the first electrically conductive channel may be relatively protruded (and also may be relatively recessed in the remaining range in the circumferential direction of the active region to avoid unnecessary electrical connection). To do this, for example, a first shielding layer may be formed in the first range to shield the sidewalls of those source/drain layers in the first range. With presence of the first shielding layer, those source/drain layers may be etched selectively, such that the outer peripheries thereof may be recessed inwards with respect to the outer periphery of the hard mask layer. In such a recess, a first partial isolation layer may be formed therein. Similarly, in a second range in the circumferential direction of the active region in which a second electrically conductive channel is to be formed, the source/drain layers to be connected to the second electrically conductive channel may be relatively protruded (and also may be relatively recessed in the remaining range in the circumferential direction of the active region to avoid unnecessary electrical connection). To do this, for example, a second shielding layer may be formed in the second range to shield the sidewalls of those source/drain layers in the second range. With presence of the second shielding layer, those source/drain layers may be etched selectively, such that the outer peripheries thereof may be recessed inwards with respect to the outer periphery of the hard mask layer. In such a recess, a second partial isolation layer may be formed therein. Then, a replacement gate process may be performed to replace the sacrificial gate with gate stacks. Similarly, in a third range in the circumferential direction of the active region in which a third electrically conductive channel is to be formed, the gate stacks to be connected to the third electrically conductive channel may be relatively protruded (and also may be relatively recessed in the remaining range in the circumferential direction of the active region to avoid unnecessary electrical connection). To do this, for example, a third shielding layer may be formed in the third range to shield the sidewalls of those gate stacks in the third range. With presence of the third shielding layer, those gate stacks may be etched selectively, such that the outer peripheries thereof may be recessed inwards with respect to the outer periphery of the hard mask layer. In such a recess, a third partial isolation layer may be formed therein. In this way, the isolation layer (the first partial isolation layer+the second partial isolation layer+the third partial isolation layer) encapsulates the stack and the gate stacks, while exposing the sidewalls of the source/drain layers to be connected to the first electrically conductive channel at the first range, the sidewalls of the source/drain layers to be connected to the second electrically conductive channel at the second range, and the sidewalls of the gate stacks to be connected to the third electrically conductive channel at the third range. The first range to the third range each may include several discrete sub-ranges, whose sizes may be different. The present disclosure may be implemented in various forms, some examples of which will be described below. FIGS.1to20(b) are schematic diagrams illustrating a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown inFIG.1, a substrate1001is provided. The substrate1001may be a substrate in various forms, including but not limited to a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, or the like. In the following description, a bulk Si substrate is described by way of example for convenience. A well region1001wmay be formed in the substrate1001. If a p-type device is to be formed, the well region1001wmay be an n-type well; or alternatively, if an n-type device is to be formed, the well region1001wmay be a p-type well. The well region1001wmay be formed by, for example, injecting a corresponding conductivity type of dopants (p-type dopants such as B or In, or n-type dopants such as As or P) into the substrate1001followed by thermal annealing, with a doping concentration of about 1E17-2E19 cm−3. There are various ways in the art to provide such a well region, and thus detailed descriptions thereof are omitted here. As shown inFIG.2, on the substrate1001, a stack of alternating source/drain layers1003-1,1007-1,1003-2,1007-2and channel layers1005-1,1005-2,1005-3may be formed by, for example, epitaxy. These are all layers of semiconductor materials. As described above, the channel layers may have an etch selectivity with respect to the source/drain layers, and the source/drain layers overlying and underlying one same channel layer may have an etch selectivity with respect to each other. For example, the channel layers1005-1,1005-2,1005-3may comprise the same material such as SiGe (with an atomic percentage of Ge of about 10-40%), and have a thickness of about 10-100 nm. The source/drain layers1003-1and1003-2may comprise the same material such as SiGe (with an atomic percentage of Ge of about 10-40% and different from, for example less than, the atomic percentage of Ge in the channel layers, so as to provide the etch selectivity), and have a thickness of about 10-50 nm. The source/drain layers1007-1and1007-2may comprise the same materials such as Si, and have a thickness of about 10-50 nm. In growing the source/drain layers and the channel layers, they may be doped in-situ to the desired conductivity type and doping concentration. For example, in the case of forming an n-type FET, n-type impurities such as As or P may be used to dope the source/drain layers1003-1,1007-1,1003-2,1007-2to the n-type, at a doping concentration of about 1E18-1E21 cm−3; in the case of forming a p-type FET, p-type impurities such as B or In may be used to dope the source/drain layers1003-1,1007-1,1003-2,1007-2to the p-type, at a doping concentration of about 1E18-2E20 cm−3. The channel layers1005-1,1005-2,1005-3may be not intentionally doped, or be lightly doped to adjust a threshold voltage (Vt) of the device. In addition, the difference in the doping concentration may provide the etch selectivity. In the case of forming a tunneling FET, the source/drain layers overlying and underlying one same channel layer may be doped to opposite conductivity types. Certainly, the way of doping is not limited to in-situ doping, and may be performed in other ways such as ion implantation or the like. In this example, there are three channel layers1005-1,1005-2,1005-3, which will result in three semiconductor devices stacked on each other accordingly. However, the present disclosure is not limited thereto, and more (for example, four or more) or less (for example, one or two) semiconductor devices may be formed. A hard mask layer may be formed on the stack. The hard mask layer may comprise a stack of, for example, an etching stop layer1009, a first mask sub-layer1011and a second mask sub-layer1015. Here, for the convenience of forming electrically conductive channels later, an electrically conductive material layer1013may be interposed between the first mask sub-layer1011and the second mask sub-layer1015. Here, the first mask sub-layer1011(and the etching stop layer1009) each comprise a dielectric material, such as a low k dielectric material, and can be used thereafter for electrical isolation between overlying interconnect components, such as contacts and the electrically conductive channels, and the underlying device. For example, the etching stop layer1009may comprise oxide (for example, silicon oxide), with a thickness of about 2-5 nm, and may be formed by deposition or thermal oxidation; the first mask sub-layer1011may comprise nitride (for example, silicon nitride) or a low k dielectric material (for example, silicon carbide based materials), with a thickness of about 10-100 nm, and may be formed by deposition; the electrically conductive material layer1013may comprise an electrically conductive material such as metal silicide (for example, silicide containing Co, Ni, or Ti), with a thickness of about 5-20 nm, and may be formed by silicidation; and the second mask sub-layer1015may comprise nitride, with a thickness of about 10-100 nm, and may be formed by deposition. Next, an active region of the device may be defined. For example, this may be achieved as follows. As shown inFIGS.3(a) and3(b), photoresist1017may be formed on the hard mask layer. The photoresist1017may be patterned into a desired shape (in this example, substantially a rectangle) by photolithography (exposure and development). As shown in the top view ofFIG.3(a), the pattern defined by the photoresist1017is within the range of the well region1001w. Certainly, the pattern of the photoresist1017is not limited to the rectangle, and may be various other suitable shapes, such as round, oval, square, or the like. The pattern of the photoresist1017may be subsequently transferred into the hard mask layer and then into the underlying semiconductor layers. Specifically, as shown inFIG.4, with the patterned photoresist as a mask, the hard mask layer, the source/drain layer1007-2, the channel layer1005-3, the source/drain layer1003-2, the channel layer1005-2, the source/drain layer1007-1, the channel layer1005-1, the source/drain layer1003-1may be selectively etched sequentially by, for example, reactive ion etching (RIE). In this example, the etching is performed into the substrate1001(but not to the bottom surface of the well region1001w), so as to form a trench in the substrate1001, in which shallow trench isolation (STI) may be formed subsequently. The source/drain layers and the channel layers after being etched form a pillar (in this example, a hexahedral pillar with a rectangular cross section), defining the active region. The RIE may be performed for example in the direction generally perpendicular to the substrate surface, and thus the pillar is also generally perpendicular to the substrate surface. Then, the photoresist1017may be removed. So far, the respective layers in the active region may have their outer peripheral sidewalls substantially coplanar with an outer peripheral sidewall of the hard mask layer. In the subsequent process, the layers in the active region may have their respective shapes adjusted as desired (by, for example, recessing the sidewalls thereof). In the trench formed in the substrate1001, a dielectric material may be filled to form the STI. For example, as shown inFIGS.5(a) and5(b), oxide may be deposited on the structure shown inFIG.4, planarized by, for example, chemical mechanical polishing (CMP) (with the hard mask layer, for example, the second mask sub-layer1015, as a stop layer), and then etched-back (by, for example, wet etching, vapor etching, vapor HF, or the like) to form the STI1019. The STI1019is formed around the active region, to achieve electrical isolation among active regions. Here, the STI1019, after being etched back, may have a top surface lower than that of substrate1001, and thus the STI1019may expose a part of the well region1001W. Then, as shown inFIGS.6(a) and6(b), the outer peripheral sidewalls of the channel layers may be recessed with respect to the outer peripheral sidewall of the hard mask layer (in this example, in a lateral direction generally parallel to the substrate surface), so that gate stacks may be formed subsequently within the range defined by the hard mask layer. This is advantageous, because the outer peripheral sidewall of the hard mask layer may be used as a reference to define relative recess and protrusion of the respective layers in the active region and gate stacks. In one example, this may be realized by further selectively etching the channel layers1005-1,1005-2,1005-3with respect to the respective source/drain layers. As described above, due to the etch selectivity between the channel layers and the source/drain layers, such selective etching can be achieved. The selective etching can be performed in a precise and controllable way by use of atomic layer etch (ALE) or digital etch. Such recesses of the outer peripheries of the respective channel layers with respect to the outer peripheries of the source/drain layers facilitate the subsequent formation of the gate stacks. However, the present disclosure is not limited thereto. The outer peripheral sidewalls of the channel layers may be recessed with respect to the outer peripheral sidewall of the hard mask layer (so that the hard mask layer may be used as a reference), but not recessed with respect to the outer peripheral sidewalls of the source/drain layers (by, for example, etching the source/drain layers and channel layers to the generally same extent). In such a case, the gate stacks may be formed also around the outer periphery of the channel layers. There are various ways in the art to form the gate stacks for the vertical type device, and detailed descriptions thereof will be omitted here. In this example, it is assumed, without considering anisotropy, that the selective etching of the channel layers1005-1,1005-2,1005-3is performed substantially identically in each direction. Therefore, the channel layers1005-1,1005-2,1005-3after being etched are still substantially rectangular in shape. For example, the rectangle has a short side with a length of w1, and a long side with a length of w2. It is possible to control electrostatic characteristics of the device such as short channel effects by w1, and to define a width of the device or an amount of current that can be conducted by w2. In the recesses of the respective channel layers with respect to the outer peripheries of the source/drain layers, the gate stacks are to be formed subsequently. In order to prevent the subsequent process from impacting the channel layers or leaving unnecessary material(s) in the recesses so as not to affect the subsequent formation of the gate stacks, a material layer may be filled in the recesses to occupy the space for the gate stacks (therefore, the material layer may be called a “sacrificial gate”). For example, oxynitride (for example, silicon oxynitride) or silicon carbide (different from the material of the hard mask layer so that selectively etching can be conducted subsequently) may be deposited on the structure shown inFIGS.6(a) and6(b), and then the deposited oxynitride or silicon carbide may be etched back by, for example, RIE. The RIE may be performed in a direction generally perpendicular to the substrate surface, and thus the oxynitride or silicon carbide may be left only in the recesses to form sacrificial gates1021, as shown inFIGS.7(a) and7(b). In such a case, the sacrificial gates1021may substantially fill up the respective recesses. Then, the source/drain layers may have their shapes adjusted to achieve the required relative recess/protrusion. In order to achieve the parallel connection, the source/drain layers on an upper side and a lower side of one same channel layer need to be connected to different electrically conductive channels, and thus need to be protruded at different regions. To do this, as shown inFIGS.8(a) and8(b), a first shielding layer1023amay be formed at the region where the source/drain layers1003-1and1003-2need to be relatively protruded (referred to as “a first region”), so as to shield the sidewalls of the source/drain layers1003-1and1003-2. For example, in the structure shown inFIGS.7(a) and7(b), a spacer may be formed on the STI1019around sidewalls of those protruding elements with respect to the STI1019(specifically, the portion of the substrate protruding above STI1019, the sacrificial gates1021, and the respective source/drain layers) by a spacer formation process (for example, conformal deposition followed by RIE in the vertical direction). For example, the spacer may comprise Si. Then, photoresist may be formed to shield a portion of the spacer at the first region but to expose the remaining portion of the spacer. The exposed portion of the spacer may be removed by selective etching such as RIE, and thus the portion of the spacer at the first region may be left to form the first shielding layer1023a. After that, the photoresist may be removed. In this example, the first shielding layer1023ais formed only at a lower edge in the top view shown inFIG.3(a)(or, accordingly a left edge inFIG.8(b)), so that subsequently the source/drain layers1003-1and1003-2may protrude relatively at this location. However, the present disclosure is not limited thereto. The first shielding layer1023amay shield more of the sidewalls of the source/drain layers1003-1and1003-2. For example, the first region may include a plurality of separated sub-regions. This can improve the device performances, for example, RC delay. Then, as shown inFIGS.9(a) and9(b), the outer peripheral sidewalls of the source/drain layers1003-1and1003-2may be recessed with respect to the outer peripheral sidewall of the hard mask layer. This may be achieved by selectively etching the source/drain layers1003-1and1003-2. Due to the presence of the first shielding layer1023a, the sidewalls of the source/drain layers1003-1and1003-2are not recessed at the first region, and thus are relatively protruded. In the figures, it is illustrated that the outer peripheral sidewalls of the source/drain layers1003-1and1003-2after being etched are still relatively protruded with respect to the outer peripheral sidewalls of the channel layers. However, the present disclosure is not limited thereto. For example, the outer peripheral sidewalls of the source/drain layers1003-1and1003-2after being etched may be substantially aligned with or even relatively recessed with respect to the outer peripheral sidewalls of the channel layers. In order to avoid damaging the channel layers, an etching recipe for the source/drain layers1003-1and1003-2may be selected to have substantially no effects on the channel layers. Subsequently, the first shielding layer1023amay be removed by selective etching such as RIE. For the source/drain layers1003-1and1003-2, an isolation layer1025may be formed around them. For example, as shown inFIGS.10(a) and10(b), the isolation layer1025may be formed by depositing a dielectric layer, especially a low k dielectric layer such as low k silicon carbide, on the structure shown inFIGS.9(a) and9(b)(with the first shielding layer1023aremoved) followed by etching-back. The etching-back may be performed by RIE in the vertical direction, and thus the isolation layer1025may be left below the hard mask layer, while having its outer peripheral sidewall substantially coplanar with the outer peripheral sidewall of the hard mask layer. Therefore, the other portions of the sidewalls of the source/drain layers1003-1and1003-2than that exposed at the first region are covered by the isolation layer1025. Such the isolation layer1025may be self-aligned to the source/drain layers1003-1and1003-2. Next, the remaining source/drain layers1007-1and1007-2may be processed similarly. For example, as shown inFIGS.11(a) and11(b), a second shielding layer1023bmay be formed at the region where the source/drain layers1007-1and1007-2need to be relatively protruded (referred to as “a second region”), so as to shield the sidewalls of the source/drain layers1007-1and1007-2. For example, in the structure shown inFIGS.10(a) and10(b), a spacer may be formed on the STI1019around the sidewalls of those protruding elements with respect to the STI1019(specifically, the portion of the substrate protruding above STI1019, the sacrificial gates1021, the isolation layer1025, and the respective source/drain layers) by a spacer formation process (for example, conformal deposition followed by RIE in the vertical direction). For example, the spacer may comprise SiGe. Then, photoresist may be formed to shield a portion of the spacer at the second region but to expose the remaining portion of the spacer. The exposed portion of the spacer may be removed by selective etching such as RIE, and thus the portion of the spacer at the second region may be left to form the second shielding layer1023b. After that, the photoresist may be removed. In this example, the second shielding layer1023bis formed only at an upper edge in the top view shown inFIG.3(a)(or, accordingly a right edge inFIG.11(b)), so that subsequently the source/drain layers1007-1and1007-2may protrude relatively at this location. However, the present disclosure is not limited thereto. The second shielding layer1023bmay shield more of the sidewalls of the source/drain layers1007-1and1007-2. For example, the second region may include a plurality of separated sub-regions. This can improve the device performances, for example, RC delay. Here, the first region and the second region are disposed opposite to each other, in order to avoid as much as possible the mutual interference between the electrically conductive channels to be formed subsequently and respectively in these two regions. Then, as shown inFIGS.12(a) and12(b), the outer peripheral sidewalls of the source/drain layers1007-1and1007-2may be recessed with respect to the outer peripheral sidewall of the hard mask layer. This may be achieved by selectively etching the source/drain layers1007-1and1007-2(by, for example, wet etching with TMAH solution). Due to the presence of the second shielding layer1023b, the sidewalls of the source/drain layers1007-1and1007-2are not recessed at the second region, and thus are relatively protruded. In the figures, it is illustrated that the outer peripheral sidewalls of the source/drain layers1007-1and1007-2after being etched are still relatively protruded with respect to the outer peripheral sidewalls of the channel layers. However, the present disclosure is not limited thereto. For example, the outer peripheral sidewalls of the source/drain layers1007-1and1007-2after being etched may be substantially aligned with or even relatively recessed with respect to the outer peripheral sidewalls of the channel layers. In order to avoid damaging the channel layers, an etching recipe for the source/drain layers1007-1and1007-2may be selected to have substantially no effects on the channel layers. Subsequently, the second shielding layer1023bmay be removed by selective etching such as RIE. In addition, in this example, because the substrate1001comprises the same material (Si) as the source/drain layers1007-1and1007-2, the substrate1001may be also etched. Here, the etching is stopped before the bottom of the well region1001w. For the source/drain layers1007-1and1007-2, an isolation layer may be formed around them. For example, as shown inFIGS.13(a) and13(b), the isolation layer may be formed by depositing a dielectric layer, especially a low k dielectric layer such as low k silicon carbide, on the structure shown inFIGS.12(a) and12(b)(with the second shielding layer1023bremoved) followed by etching-back. The isolation layer formed hereby and the isolation layer1025previously formed may comprise the same material, and thus are collectively shown as1025′. The etching back may be performed by RIE in the vertical direction, and thus the isolation layer1025′ may be left below the hard mask layer, while having tis outer peripheral sidewall substantially coplanar with the outer peripheral sidewall of the hard mask layer. Therefore, the other portions of the sidewalls of the source/drain layers1007-1and1007-2than that exposed at the second region are covered by the isolation layer1025′. Such the isolation layer may be self-aligned to the source/drain layers1007-1and1007-2. According to other embodiments, in order to improve electrical contact characteristics, metal silicide may be formed on the surfaces of the source/drain layers. For example, the isolation layer1025′ may not be formed, and instead the isolation layer1025may be removed. Therefore, the sidewalls of the respective source/drain layers1003-1,1003-2,1007-1, and1007-2may be exposed. Then, a metal layer such as Ni or NiPt may be formed by deposition, for example, chemical vapor deposition (CVD), atomic layer epitaxy (ALE), physical vapor deposition (PVD), or the like, and then subjected to annealing for silicidation, resulting in metal silicide such as NiPtSi. Then, the metal layer unreacted may be removed. After that, the isolation layer1025′ described above may be formed. After adjusting the shapes of the source/drain layers, a replacement gate process may be performed. For example, as shown inFIGS.14(a) and14(b), the sacrificial gates1021may be removed by selective etching, so as to release the space in the recesses, and the gate stacks may be formed in the released space. Specifically, a gate dielectric layer1027and a gate conductor layer1029may be subsequently deposited on the structure shown inFIGS.13(a) and13(b)(with the sacrificial gate1021removed), and the deposited gate conductor layer1029(and optionally the gate dielectric layer1027) may be etched back. The etching-back may be performed by RIE in the vertical direction, and thus the gate stacks may be left below the hard mask layer, while having their respective outer peripheral sidewalls substantially coplanar with the outer peripheral sidewall of the hard mask layer. For example, the gate dielectric layer1027may comprise high-k gate dielectric such as HfO2, and the gate conductor layer1029may comprise a metal gate conductor. In addition, a work function adjustment layer may be formed between the gate dielectric layer1027and the gate conductor layer1029. Before forming the gate dielectric layer1027, an interface layer of, for example, oxide may be formed. Because the sidewalls of the source/drain layers1003-1,1003-2and the sidewalls of the gate stacks, especially those of the gate conductor layer1029, are now substantially coplanar in the first region (see the left sidewalls inFIG.14(b)), a first electrically conductive channel to the source/drain layers1003-1,1003-2, if formed, will also contact the gate conductor layer1029. In order to avoid such a case, the sidewalls of the gate stacks, especially those of the gate conductor layer1029, may be relatively recessed at least in the first region. In addition, because the sidewalls of the source/drain layers1007-1,1007-2and the sidewalls of the gate stacks, especially those of the gate conductor layer1029, are now substantially coplanar in the second region (see the right sidewalls inFIG.14(b)), a second electrically conductive channel to the source/drain layers1007-1,1007-2, if formed, will also contact the gate conductor layer1029. In order to avoid such a case, the sidewalls of the gate stacks, especially those of the gate conductor layer1029, may be relatively recessed at least in the second region. In addition, in order to form a third electrically conductive channel to the gate conductor layer1029, the gate conductor layer1029may be relatively protruded at a third region different from the first region and the second region. To do this, as shown inFIGS.15(a) and15(b), a third shielding layer1031may be formed. The third shielding layer1031may be formed at a third region different from the first region and the second region, to expose the sidewalls of the gate stack at least at the first region and the second region. For example, in the structure shown inFIGS.14(a)14(b), a spacer may be formed on the STI1019around sidewalls of those protruding elements with respect to the STI1019(specifically, the portion of the substrate protruding above STI1019, the isolation layer, the gate stacks, and the hard mask layer) by a spacer formation process. For example, the spacer may comprise oxide. In this example, the third shielding layer1031is formed at edges on the left and right sides in the top view illustrated inFIG.3(a)(or, accordingly edges on the left and right sides inFIG.15(a)), so as to avoid mutual interference between the third electrically conductive channels to be formed at the third region and the first electrically conductive channel and the second electrically conductive channel to be formed respectively at the first region and the second region. However, the present disclosure is not limited thereto. The third shielding layer1031may shield more of the sidewall of the gate stacks. For example, the third region may include a plurality of separated sub-regions. This can improve the device performances, for example, RC delay. Then, the outer peripheral sidewalls of the gate stacks may be recessed with respect to the outer peripheral sidewall of the hard mask layer. This may be achieved by etching back the gate dielectric layer1027and the gate conductor layer1029. Then, the third shielding layer1031may be removed. Due to the third shielding layer1031, the sidewalls of the gate stacks are recessed at least at the first region and the second region (see dotted circles inFIG.15(b)), such that the source/drain layers1003-1and1003-2are protruded with respect to the gate stacks and the source/drain layers1007-1and1007-2at the first region and that the source/drain layers1007-1and1007-2are protruded with respect to the gate stacks and the source/drain layers1003-1and1003-2at the second region. In addition, at the third region, due to the presence of the third shielding layer1031, the gate stacks are not recessed and thus protruded with respect to the source/drain layers1003-1and1003-2and the source/drain layers1007-1and1007-2, so as to subsequently contact the third electrically conductive channel to the gate stack. After etching back the gate stacks, a dielectric material may be further filled in the space produced by the etching-back (see the dotted circles inFIG.15(b)). The dielectric material may be same as that in the isolation layer1025′, and thus they are not distinguished from each other in the drawings. In addition, as shown inFIG.15(b), the top surface of the STI1019may be lower than the top surface of the substrate1001, and thus some part of the substrate may be exposed. In this example, the substrate1001is exposed at the second region. Further, the substrate1001and the source/drain layer1003-1contact each other. Therefore, when the second electrically conductive channel to the source/drain layers1007-1and1007-2is formed subsequently at the second region, the second electrically conductive channel may form a short-circuit with the source/drain layer1003-1through the exposed part of the substrate, which is undesirable. To do this, as shown inFIGS.16(a) and16(b), another isolation layer1033may be formed on the STI1019, so as to cover the exposed surface of the substrate1001. For example, the isolation layer1033may be formed by depositing SiC, planarizing the deposited SiC by, for example, CMP (which may be stopped at the hard mask layer), and then etching back SiC. The isolation layer1033may, on one hand, need to expose the sidewalls of the source/drain layers1007-1,1007-2(implying that a top surface thereof may not be higher than the bottom surface of the lower source/drain layer1007-1), and, on the other hand, be capable of shielding possible paths to the source/drain layer1003-1(implying that the top surface thereof may not be lower than the top surface of the source/drain layer1003-1). Here, the isolation layer1033may comprise a material different from the third shielding layer1031, so as to prevent the etching back thereof from removing the third shielding layer1031. However, the isolation layer1033formed in such a way also covers the sidewall of the source/drain layer1003-1in the first region. The sidewall of the source/drain layer1003-1needs to be exposed at the first region, to enable contact between it and the first electrically conductive channel to be formed at the first region. For example, as shown inFIGS.17(a),17(b) and17(c), a shielding layer1035, for example, photoresist, may be formed to at least cover the isolation layer1033in the second region and to at least expose the isolation layer1033in the first region. Subsequently, the isolation layer1033may be selectively etched by, for example, RIE. The RIE may stop at the STI1019. Therefore, the sidewall of the source/drain layer1003-1is exposed at the first region. Then, the shielding layer1035and the third shielding layer1031may be removed. Due to the above processes, a protruding structure defined by the hard mask layer is formed above the STI1019. The protruding structure has most of its outer periphery covered by the isolation layer1025′ (and the isolation layer1033). The electrically conductive channels may be formed subsequently on the surface of the isolation layer1025′. At the first region, the source/drain layers1003-1,1003-2are protruded with respect to the source/drain layers1007-1,1007-2and gate stacks; at the second region, the source/drain layers1007-1,1007-2are protruded with respect to the source/drain layers1003-1,1003-2and gate stacks; and at the third region, the gate stacks are protruded with respect to the source/drain layers1003-1,1003-2and the source/drain layers1007-1,1007-2. The sidewalls of these protruded parts are substantially coplanar to the sidewall of the hard mask layer, and exposed at the surface of the isolation layer1025′. Therefore, the electrically conductive channels to be formed subsequently on the surface of the isolation layer1025′ may contact the sidewalls of these protruded parts. As shown inFIGS.18(a),18(b) and18(c), the first electrically conductive channel1037-1, the second electrically conductive channel1037-2, and the third electrically conductive channel1037-3may be formed on the surface of the isolation layer through an electrically conductive material such as metal (for example, at least one of W, Co, or Ru) or metal silicide (for example, at least one of NiSi, NiPtSi, PtSi, CoSi, CoSi2, TiSi, or TiSi2) by, for example, a spacer formation process in combination with photolithography. The first electrically conductive channel1037-1, the second electrically conductive channel1037-2, and the third electrically conductive channel1037-3may be formed respectively at the first region, the second region, and the third region, to contact the source/drain layers1003-1,1003-2exposed at the first region, the source/drain layers1007-1,1007-2exposed at the second region, and the gate stacks exposed at the third region, respectively. Here, the electrically conductive channels may be formed on respective sides (e.g., four sides) of the hard mask layer (e.g., rectangle), as shown in the top view of theFIG.18(c). The electrically conductive channels may contact the sidewalls of the source/drain layers and the gate stacks (especially the gate conductor layer1029therein), respectively. In addition, the electrically conductive channels contact the sidewall of the electrically conductive material layer1013. In the case where at least one of the first region, the second region, or the third region includes separated sub-regions, the electrically conductive channels may be formed respectively in the sub-regions. In addition, the sizes of the electrically conductive channels may not necessarily be the same. According to other embodiments, if silicide is not formed on the surfaces of the source/drain layers in the foregoing process, the source/drain layers may be silicided. For example, the gate stacks may be etched back and a shielding layer (having a material different from that of the isolation layer1025′) may be filled in the gap due to the etching-back. Then, the isolation layer1025′ may be removed, and the thus exposed surfaces of the source/drain layers may be silicided. Then, an isolation layer may be filled in the gap (some part thereof may be occupied by the silicide) due to the removal of the isolation layer1025′. Then, the shielding layer may be removed from, for example, the third region, to expose the sidewalls of the gate stacks. Then, in forming the electrically conductive channels, the electrically conductive material may enter the gap due to the removal of the shielding layer to contact the sidewalls of the gate stacks. According to other embodiments, the electrically conductive channels may have stress used to adjust the device performances. For example, for the n-type device, the electrically conductive channels may have compressive stress to create tensile stress in the channel layers; or alternatively, for the p-type device, the electrically conductive channels may have tensile stress to create compressive stress in the channel layers. Then, the electrically conductive material layer1013may be patterned to achieve required electric isolation. For example, as shown inFIGS.19(a) and19(b), the electrically conductive material layer1013may be cut off along line AA′, to be divided into three parts corresponding to the first electrically conductive channel1037-1, the second electrically conductive channel1037-2, and the third electrically conductive channel1037-3, respectively. This may be achieved by selectively etching (with a cutting mask) the second mask sub-layer1015and the electrically conductive material layer1013sequentially by, for example, RIE. Then, as shown inFIGS.20(a) and20(b), an interlayer dielectric layer1039may be formed on the structure shown inFIGS.19(a) and19(b)(inFIG.20(a), the interlayer dielectric layer1039is not shown for clarity). For example, the interlayer dielectric layer1039may be formed by depositing oxide and then planarizing it by, for example, CMP. In the interlayer dielectric layer1039, contacts1041,1042, and1043may be formed. These contacts may be formed by etching holes and filling an electrically conductive material such as metal therein. The contact1041is electrically connected to the source/drain layers1003-1,1003-2through the electrically conductive material layer1013and the first electrically conductive channel1037-1; the contact1042is electrically connected to the source/drain layers1007-1,1007-2through the electrically conductive material layer1013and the second electrically conductive channel1037-2; and the contact1043is electrically connected to the gate conductor layer1029through the electrically conductive material layer1013and the third electrically conductive channel1037-3. In this example, the contacts1041,1042, and1043are arranged in a row generally along the longitudinal direction of the active region (the long side direction of the rectangular active region), so as to overlap with the main body of the active region as much as possible to save the footprint more while ensuring their spacing. In this example, the contacts1041,1042, and1043are formed on the top of the active region. However, the present disclosure is not limited thereto. For example, only one or two of the contacts1041,1042, and1043may be formed on the top of the active region, while the other contact(s) may be offset in a lateral direction as in the conventional technology. The semiconductor device according to embodiments of the present disclosure are applicable to various electronic devices. For example, by integrating a plurality of such semiconductor devices and also other devices (for example, other forms of transistors, etc.), an integrated circuit (IC) may be formed, and an electronic device may be manufactured thereby. Therefore, the present disclosure also provides an electronic device comprising the above described semiconductor device. The electronic device may also comprise components, such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such an electronic device may comprise, for example, a smart-phone, a computer, a tablet computer, a wearable smart device, a mobile power, or the like. According to embodiments of the present disclosure, there is also provided a method of manufacturing a system on chip (SoC). The method may comprise the above described method of manufacturing the semiconductor device. Specifically, a plurality of types of devices may be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure. In the above description, technical details such as patterning and etching of each layer have not been described in detail. However, those skilled in the art should understand that layers, regions or the like in desired shapes can be formed in various ways. In addition, in order to form one same structure, those skilled in the art can also devise a method, which is not completely the same as the method described above. In addition, although the embodiments are respectively described above, this does not mean that measures in the respective embodiments can not be used in combination to advantage. The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure. | 60,449 |
11942475 | DETAILED DESCRIPTION The following disclosure provides different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features, such that the first and second features are not in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The term “nominal” as used herein refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values is typically due to slight variations in manufacturing processes or tolerances. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). The term “vertical,” as used herein, means nominally perpendicular to the surface of a substrate. Integrated circuits (IC) can include combinations of semiconductor structures like input/output (I/O) field effect transistors (FETs) and non-I/O FETs. The I/O FETs can be part, for example, of a circuit formed in a peripheral region of the IC referred to as “I/O region” or “high voltage region,” while the non-I/O devices can be part of a “core” circuit referred to as logic circuit or memory circuit formed in a “core” region of the IC. The I/O devices can be configured to receive input/output voltages or current of the IC and tolerate a higher voltage or current than the non-I/O devices. For example, the I/O devices can be configured to handle input voltages from an external power supply, such as a lithium ion battery, outputting about 5 V. Further, the I/O devices can be part of a transformer circuit that outputs a distribution voltage of about 1 V which can be subsequently distributed to the non-I/O FETs. On the other hand, the non-I/O devices are not configured to handle the input/output voltages/current directly and are referred to as core devices, logic devices, and/or memory devices. For example, the non-I/O devices can include FETs forming logic gates, such as NAND, NOR, inverters, or a combination thereof. Additionally, the non-I/O devices can include memory devices, such as static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, other types of memory devices, or combinations thereof. For fabrication efficiency, it is desirable that I/O and non-I/O FETs are formed concurrently on the same substrate. Metal gate materials and high-dielectric constant (high-k) dielectric materials (e.g., with a k-value greater than about 3.9) have been implemented in the gate stack fabrication of the non-I/O FETs for several technology nodes to improve the device characteristics and promote device scaling. To simplify, harmonize, and streamline the fabrication process between I/O and non-I/O FETs, metal gate and high-k dielectric materials have also been implemented for the gate stacks of I/O FETs. Because the I/O and non-I/O FETs are configured to operate at different voltages (e.g., at about 5 V and about 1 V respectively), their structures can vary with regard to their physical dimensions. For example, the gate stack of the I/O FETs can have a larger surface area (e.g., greater than about 1 μm2) and include a thicker gate oxide compared to the gate stack of the non-I/O FETs which are smaller in size. Due to the larger size of I/O FETs, chemical mechanical planarization (CMP) for these devices can be challenging if the gate electrode material is a metal or a metallic stack. For example, planarization of such large features can cause erosion or “dishing” of the gate electrode for the I/O FET. Consequently, the thickness of the gate electrode of the I/O FET may be non-uniform across the device, which can degrade the performance and reliability of the I/O FET. Embodiments of the present disclosure are directed to a method for forming I/O FETs with polysilicon gate electrodes and silicon oxide gate dielectrics concurrently with non-I/O FETs having metal gate electrodes and high-k gate dielectrics. In some embodiments, the polysilicon gate electrode provides resilience to CMP dishing and therefore allows for a process to form larger I/O FETs (e.g., equal to or greater than about 10 μm2). In some embodiments, the method described herein can be applied to planar and non-planar transistors (e.g., finFETs). According to some embodiments,FIG.1is an isometric view of a polysilicon I/O FET structure100. Polysilicon I/O FET structure100is formed on a semiconductor substrate105between substrate isolation regions110. In some embodiments, each substrate isolation region110can be a shallow trench isolation region (e.g., an STI region) that includes a dielectric material such as silicon dioxide (SiO2) or a low-k dielectric material (e.g., with a k-value lower than about 3.9). Substrate isolation regions110are formed in semiconductor substrate105to provide electrical isolation between doped regions of semiconductor substrate105. The doped regions of semiconductor substrate105are not shown inFIG.1for simplicity. According to some embodiments, semiconductor substrate105can include (i) silicon, (ii) a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide(InP), indium arsenide (InAs), and/or indium antimonide (InSb), (iii) an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or (iv) combinations thereof. For example purposes, semiconductor substrate105will be described in the context of crystalline silicon. Based on the disclosure herein, other materials, as discussed above, can be used. These materials are within the spirit and scope of this disclosure. Polysilicon I/O FET structure100is laterally isolated from neighboring devices or structures (not shown inFIG.1) through dielectric layer115. In some embodiments, dielectric layer115can be an interlayer dielectric such as SiO2, doped SiO2, or any other suitable dielectric material with a dielectric constant equal to or less than about 3.9 (e.g., about 3.6, about 3.3, etc.). By way of example and not limitation, dielectric layer115surrounds the side surfaces of polysilicon I/O FET structure100as shown inFIG.1. In some embodiments, polysilicon I/O FET structure100includes a gate stack having a gate dielectric layer120formed on semiconductor substrate105and a polysilicon gate electrode layer125disposed on gate dielectric layer120. By way of example and not limitation, gate dielectric layer120can include silicon oxide (SiO2), which can be thermally grown on (e.g., in contact with) semiconductor substrate105. By way of example and not limitation, gate dielectric layer120can have a thickness between about 20 Å and about 500 Å and can be substantially thicker than a gate dielectric layer of a non-I/O FET (e.g., from about 2 to about 20 times thicker). Gate dielectric layer120allows polysilicon I/O FET structure100to operate with high gate voltages (e.g., about 5 V). In some embodiments, polysilicon gate electrode layer125has a thickness125Tthat ranges from about 10 nm to about 300 nm, a width125Wthat ranges from about 0.1 μm to about 100 μm, and a length125Lthat ranges from about 0.05 μm to about 50 μm. According to some embodiments, the surface area (e.g.,125W×125L) of polysilicon gate electrode layer125is greater than about 1 μm2. In some embodiments, the surface area of polysilicon gate electrode layer125is between about 1 μm2and about 10 μm2. In some embodiments, the surface area of polysilicon gate electrode layer125is greater than about 10 μm2, for example about 20 μm2. In some embodiments, polysilicon gate electrode layer125of polysilicon I/O FET structure100offers resilience to dishing caused by a gate electrode CMP process even when the surface area of the gate electrode is greater than about 10 μm In other words, thickness125Tof polysilicon I/O FET structure100can be substantially uniform across length125Land width125Wafter a gate CMP process. According to some embodiments, thickness125Tvariation across length125Land width125Wafter a gate CMP process can be about 10% or less. For a thickness125Tof about 10 nm, the thickness variation can be about 1 nm. In referring toFIG.11, the center to edge thickness ratio (C/E) for a polished polysilicon gate electrode layer125of polysilicon I/O FET structure100(e.g., post CMP) is between about 0.9 and about 1, according to some embodiments. That is, the center thickness (C) of a polished polysilicon gate electrode layer125of polysilicon I/O FET structure100is between about 90% and about 100% of the edge (E) thickness along the x-y plane. Further, polysilicon I/O FET structure100shown inFIG.1includes spacer structures130on sidewalls along width125Wof polysilicon gate electrode layer125. By way of example and not limitation, spacer structures130can include a nitride, such as silicon nitride, and can further include one or more layers to form a spacer stack. In some embodiments, polysilicon gate electrode layer125includes a silicided portion where contact structures (not shown inFIG.1) can be formed thereon. In some embodiments, the silicided portion of polysilicon gate electrode layer125is a cladding silicide layer135that includes titanium silicide, nickel silicide, cobalt silicide, or any suitable silicide material that can be formed or grown on polysilicon gate electrode layer125. In some embodiments, polysilicon gate electrode layer125is doped so that it becomes conductive. By way of example and not limitation, the dopant concentration of polysilicon gate electrode layer125can be between about 1013atoms/cm3and about 1019atoms/cm3and the dopant species can be either n-type (e.g., phosphorous, arsenic, antimony) or p-type (e.g., boron, indium, and gallium). Additionally, polysilicon I/O FET structure100can include source/drain regions140and silicide layer145. In some embodiments, an etch stop layer150is disposed over substrate isolation regions110, semiconductor substrate105, silicide layer145, sidewall surfaces of gate dielectric layer120, and spacer structures130as shown inFIG.1. By way of example and not limitation, polysilicon I/O FET structure100shown inFIG.1is a planar FET structure. However, this is not limiting, and polysilicon I/O FET structures, according to the embodiments described herein, can be formed on one or more semiconductor fins to form one or more non-planar polysilicon I/O FET structures, such as polysilicon I/O finFET structures. For example,FIG.2is an isometric view of two polysilicon I/O finFET structures200each formed on a semiconductor fin205. Polysilicon I/O FET structure100and polysilicon I/O finFET structures200shown respectively inFIGS.1and2share similar structural elements, such as gate dielectric layer120, polysilicon gate electrode layer125, spacer structures130, silicide layer135, and etch stop layer150. Further, the surface area of polysilicon gate electrode layers125in polysilicon I/O FET structure100and polysilicon I/O finFET structures200can be substantially equal—e.g., greater than about 1 μm2, between about 1 μm2and about 10 μm2, or greater than about 10 μm2(e.g., about 20 μm2). In some embodiments, the thickness of gate dielectric layer120is substantially thicker than respective gate dielectric layers in non-I/O FETs and non-I/O finFETs. In some embodiments, polysilicon I/O FET structure100shown inFIG.1can be formed concurrently with non-I/O FET structures on the same semiconductor substrate. Likewise, polysilicon I/O finFET structures200shown inFIG.2can be formed concurrently with non-I/O finFET structures on the same semiconductor substrate. FIG.3is a flow chart of a method300that describes the process for forming planar and non-planar polysilicon I/O FET structures with polysilicon gate electrodes and silicon oxide gate dielectrics concurrently with non-I/O FET structures having metal gate electrodes and high-k gate dielectrics. Other fabrication operations may be performed between the various operations of method300and may be omitted merely for clarity. For example purposes, the polysilicon I/O FET structure formed using method300will be described in the context of a planar structure, such as polysilicon I/O FET structure100. Based on the disclosure herein, non-planar I/O polysilicon FET structures, like I/O polysilicon finFET structures200, which share similar structural elements and surface area, as discussed above, can be formed using method300. These non-planar I/O polysilicon FET structures (e.g., I/O polysilicon finFET structures) are within the spirit and scope of this disclosure. Method300will be described in reference toFIGS.4-9. In referring toFIGS.3and4, method300begins with operation305and the process for forming a gate dielectric layer in a first region of a semiconductor substrate and a high-k gate dielectric layer in a second region of the semiconductor substrate. In some embodiments, the first region of the semiconductor substrate corresponds to an area of an IC where I/O devices are formed—e.g., an I/O region of the semiconductor substrate. The second region of the semiconductor substrate corresponds to an area of the IC where non-I/O devices are formed—e.g., a non-I/O region of the semiconductor substrate. By way of example and not limitation, referring toFIG.4, gate dielectric layer120corresponds to the gate dielectric layer of operation305formed in an I/O substrate region400, and high-k gate dielectric layer410corresponds to the high-k gate dielectric layer of operation305formed in a non-I/O substrate region405of semiconductor substrate105. Since gate dielectric layer120is used for I/O FETs (and not for non-I/O FETs), gate dielectric layer120is selectively formed in an I/O substrate region400of semiconductor substrate105, as shown inFIG.4. In some embodiments, I/O substrate region400ofFIG.4is a cross-sectional view of semiconductor substrate105across cut-line AB shown inFIG.1. According to some embodiments, substrate region400corresponds to an I/O area of the IC and substrate region405corresponds to a non-I/O region (e.g., core or logic region) of the IC. In some embodiments, I/O substrate region400and non-I/O substrate region405are not neighboring regions—for example, I/O substrate region400and non-I/O substrate region405are spaced apart. A selective process for forming dielectric layer120in I/O substrate region400can include first forming gate dielectric layer120on both I/O and non-I/O substrate regions and then patterning gate dielectric layer120to remove gate dielectric layer120from non-I/O substrate region405. By way of example and not limitation, gate dielectric layer120can be thermally grown or deposited at a thickness range between about 20 Å and about 500 Å. Byway of example and not limitation, high-k gate dielectric layer410has a dielectric constant (k-value) greater than about 3.9 (e.g., about 4.0, about 10, about 20, about 30, etc.). In some embodiments, high-k gate dielectric layer410is a metal oxide layer that is blanket deposited on both I/O and non-I/O substrate regions and then patterned so that it is removed from I/O substrate region400as shown inFIG.4. In some embodiments, the thickness of high-k gate dielectric layer410ranges from about 5 Å to about 20 Å. In some embodiments, an interfacial gate dielectric layer, not shown inFIG.4, is formed between high-k dielectric layer410and semiconductor substrate105in non-I/O substrate region405. This interfacial gate dielectric layer can include, for example, silicon oxide or silicon oxynitride. In some embodiments, high-k gate dielectric layer410and the interfacial gate dielectric layer form a gate dielectric stack in non-I/O substrate region405. In referring toFIG.3, method300continues with operation310and the process for depositing and patterning a polysilicon gate electrode layer on gate dielectric layer120and high-k gate dielectric layer410to form respective polysilicon gate electrode structures for I/O and non I/O FETs. In referring toFIG.5, polysilicon gate electrode layer125can be blanket deposited at a thickness between about 100 Å and about 3000 Å on semiconductor substrate105and subsequently patterned to concurrently form I/O FET gate electrode structure500in I/O substrate region400and non-I/O FET gate electrode structure505in non-I/O substrate region405. In some embodiments, I/O FET gate electrode structure500and non-I/O FET gate electrode structure505are formed using a single patterning operation. In some embodiments, during operation310, patterning of polysilicon gate electrode layer125can be accomplished with the help of a hard mask stack that includes a bottom oxide layer515(e.g., a silicon oxide layer) and a top nitride layer520(e.g., a silicon nitride layer). Oxide layer515and nitride layer520can protect polysilicon gate electrode layer125during the etching operation of the aforementioned patterning process. In some embodiments, I/O FET gate electrode structure500formed in I/O substrate region400is configured to have a length greater than non-I/O FET gate electrode structure505formed in non-I/O substrate region405. For example, I/O FET gate electrode structure500has a length500L(e.g., a gate length) that ranges from about 0.05 μm to about 50 μm, while non-I/O FET gate electrode structure505has a length (e.g., a gate length) between about 5 nm and about 50 nm. In some embodiments, I/O FET gate electrode structures500having a length500Lsmaller than about 50 nm can adversely impact the performance of the I/O FET. For example, I/O FETs with I/O FET gate electrode structures500having a length smaller than about 0.05 μm may exhibit high levels of current densities but unacceptable amounts of leakage current. On the other hand, I/O FET gate electrode structures500having a length500Llarger than about 50 μm have a footprint (e.g., surface area) that may reduce the available space for other IC components. In other words, there is a tradeoff between the size of I/O FET gate electrode structures500and the available space for other IC components. In some embodiments, after patterning, I/O FET gate electrode structure500and non-I/O FET gate electrode structure505may have substantially equal widths along the y-axis (not shown inFIG.5) and respective heights500Hand505Halong the z-axis. However, in subsequent global planarization operations500Hwill become shorter than505Hdue to the thickness difference between gate dielectric layer120and high-k dielectric layer410. In some embodiments, during the aforementioned patterning process of polysilicon gate electrode layer125, gate dielectric layer120in I/O substrate region400remains on semiconductor substrate105and is not removed. On the other hand, high-k gate dielectric layer410is patterned together with polysilicon gate electrode layer125. Consequently, length500Lof I/O FET gate electrode structure500is shorter than the length of gate dielectric layer120while the length of non-I/O FET gate electrode structure505is substantially equal to the length of high-k gate dielectric layer410as shown inFIG.5 According to some embodiments, the surface area or footprint of I/O FET gate electrode structure500is greater than about 1 μm2, between about 1 μm2and about 10 μm2, or greater than about 10 μm2(e.g., about 20 μm2). According to some embodiments, dishing during CMP and space availability are factors (among others) for defining the lateral dimensions (e.g., length and width) for I/O FET gate electrode structure500shown inFIG.5. In some embodiments, non-I/O FET gate electrode structure505is a sacrificial gate electrode structure that will be replaced with a metal gate electrode stack in a subsequent operation. In referring toFIG.3, method300continues with operation315and the process for forming spacer structures on sidewall surfaces of the polysilicon gate electrode structures, such as I/O FET gate electrode structure500and non-I/O FET gate electrode structure505. By way of example and not limitation,FIG.6shows formed spacer structures130on the sidewalls of I/O FET gate electrode structure500and non-I/O FET gate electrode structure505. By way of example and not limitation, spacer structures260can be formed by a blanket deposition of a spacer material (e.g., silicon nitride) followed by an anisotropic etching process that selectively removes the spacer material from all horizontal surfaces (e.g., the y-x plane) of the structures shown inFIG.6. In some embodiments, once spacer structures130have been formed on sidewall surfaces of I/O FET gate electrode structure500, a second etching process removes portions of gate dielectric layer120not masked (e.g., covered) by spacer structures130in I/O substrate region400. In other words, spacer structures130and I/O FET gate electrode structure500are used as an etching mask to define the length of gate dielectric layer120for the I/O FETs in I/O substrate region400. Therefore, spacer structures130do not cover sidewall surfaces of gate dielectric layer120in I/O FETs as shown inFIG.6. In contrast, for non-I/O FETs, spacer structures130extend over the sidewall surfaces of high-k dielectric layer410. In some embodiments, prior to forming spacer structures130in operation315, lightly doped regions600are formed by an ion implant process in semiconductor substrate105using I/O FET gate electrode structure500and non-I/O FET gate electrode structure505as implant masks. Later, after forming spacer structures130, a second ion implant process forms heavily doped regions610in I/O substrate region400and non-I/O substrate region405respectively. During the second ion implant process, spacer structures130are used as implant masks. As a result, lightly doped regions600are substantially aligned to I/O FET gate electrode structure500and non-I/O FET gate electrode structure505and heavily doped regions610are substantially aligned to spacer structures130. In some embodiments, lightly doped regions600and heavily doped regions610combined form source/drain regions of the I/O and non-I/O FETs. In some embodiments, after forming spacer structures130, a top surface of heavily doped regions610is silicided to form a self-aligned silicide (“salicide”) layer145over the source/drain regions of I/O and non-I/O FETs. By way of example and not limitation, silicide layer145can be formed as follows. A metal layer can be blanket deposited over semiconductor substrate105. During a subsequent annealing process, a silicide is formed in sites where the deposited metal is in direct contact with the exposed silicon, such as heavily doped regions610of semiconductor substrate105. During the silicidation process, top surfaces of I/O FET gate electrode structure500and non-I/O FET gate electrode structure505are not silicided because both structures are capped (e.g., not exposed) with oxide layer515and nitride layer520. After the silicidation process, the unreacted metal is removed with, for example, a wet etching process. In some embodiments, a second annealing process is performed after the removal of the unreacted metal to complete the silicidation process. By way of example and not limitation, silicide layer145can include nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, or any other suitable metal silicide. In referring toFIG.3, method300continues with operation320and the process for forming an etch stop layer on spacer structures130, I/O FET gate electrode structure500, and non-I/O FET gate electrode structure505. In some embodiments, the etch stop layer can be blanket deposited to cover (e.g., conformally) all the features disposed on or in semiconductor substrate105. For example, as shown inFIG.7, etch stop layer150is deposited I/O FET gate electrode structure500, non-I/O FET gate electrode structure505, spacer structures130, isolation regions110and silicide layer145. By way of example and not limitation, etch stop layer150can be a nitride layer, such as a silicon nitride layer. In referring toFIGS.3and8, method300continues with operation325and the process for forming a dielectric layer115around sidewall surfaces of I/O FET gate electrode structure500and non-I/O FET gate electrode structure505. By way of example and not limitation, a dielectric layer115can be blanket deposited over semiconductor substrate105so that I/O FET gate electrode structure500and non-I/O FET gate electrode structure505become embedded in dielectric layer115. A subsequent CMP process removes excess dielectric material from top surfaces of I/O FET gate electrode structure500and non-I/O FET gate electrode structure505. In some embodiments, the CMP process removes a portion of etch stop layer150, nitride layer520, and oxide layer515so that a top surface of polysilicon gate electrode layer125is exposed in both I/O FET gate electrode structure500and non-I/O FET gate electrode structure505as shown inFIG.8. In some embodiments, as a result of the aforementioned CMP process, the top surface of polysilicon gate electrode layer125in both I/O FET gate electrode structure500and non-I/O FET gate electrode structure505become substantially coplanar with the top surface of dielectric layer115. In some embodiments, after the CMP process, the top surface of I/O FET gate electrode structure500remains substantially flat with no dishing. Additionally, after the CMP process, I/O FET gate electrode structure500becomes shorter than non-I/O FET gate electrode structure505(e.g.,500H<505H) due to the thickness difference between gate dielectric layer120and high-k dielectric layer410. Referring toFIG.3, method300continues with operation330and the process for replacing gate electrode layer125from non-I/O FET gate electrode structure505with a metal gate electrode structure. By way of example and not limitation, referring toFIG.9, metal gate electrode layer125is selectively removed and replaced with metal gate electrode905to form non-I/O FET910. In some embodiments, metal gate electrode905includes one or more metal or metallic layers. By way of example and not limitation, selective removal of polysilicon gate electrode layer125from non-I/O FET gate electrode structure505can be achieved by masking I/O substrate region400with a hard mask (e.g., a nitride layer) while removing polysilicon gate electrode layer125from non-I/O FET gate electrode structure505with a wet etching process, a dry etching process, or combinations thereof. In some embodiments, high-k dielectric layer410is not removed by the etching process used to remove polysilicon gate electrode layer125from non-I/O FET gate electrode structure505. Once polysilicon gate electrode layer125has been selectively removed from non-I/O FET gate electrode structure505, metal gate electrode905can be subsequently deposited. In some embodiments, material from metal gate electrode905is blanket deposited in I/O and non-I/O substrate regions400and405, respectively. A CMP process subsequently removes excess metal gate electrode material from the top surfaces of dielectric layer115to form non-I/O FET910. During the CMP process of the metal gate electrode material, the hard mask (not shown inFIG.9) on I/O substrate region400is removed and polysilicon gate electrode layer125from I/O FET gate electrode structure500is exposed as shown inFIG.9. According to some embodiments, after the metal gate electrode CMP process, the top surface of I/O FET gate electrode structure500remains substantially flat with no dishing. In some embodiments, polysilicon gate electrode layer125from I/O FET gate electrode structure500is resilient to dishing during the aforementioned metal gate electrode material CMP process. In referring toFIG.3, method300concludes with operation335and the process for forming a silicide on the top surface of I/O FET gate electrode structure500to form polysilicon I/O FET915shown inFIG.9. In some embodiments, the silicidation process can be similar to the silicidation process described for the process for forming silicide layer145above. In some embodiments, non-I/O substrate region405can be masked during the silicidation process with a hard mask (e.g., a nitride layer). Referring toFIG.10, a metal layer (not shown inFIG.10) can be blanket deposited on dielectric layer115over I/O and non-I/O substrate regions400and405respectively. During a subsequent annealing process, a silicide is formed on the exposed top surface of I/O FET gate electrode structure500. After the silicidation process, the unreacted metal is removed with, for example, a wet etching process. In some embodiments, a second annealing process is performed after the removal of the unreacted metal to complete the silicidation process. As a result, silicide layer135is formed in the top surface of polysilicon gate electrode layer125and polysilicon I/O FET915is formed. By way of example and not limitation, silicide layer135can include nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, or any other suitable metal silicide. According to some embodiments, the process for forming silicide layer135on polysilicon gate electrode layer125can be combined with a process for forming a silicide layer in other areas of the IC. In some embodiments, method300can be used to form non-planar I/O FET structures with polysilicon gate electrodes and silicon oxide gate dielectrics, like I/O finFET structure200shown inFIG.2. Embodiments of the present disclosure are directed to a method for forming I/O FETs featuring polysilicon gate electrodes/silicon oxide gate dielectrics integrated with non-/O FETs featuring metal gate electrodes/high-k gate dielectrics. In some embodiments, the polysilicon gate electrode of the I/O FETs provides resilience to CMP dishing during the metal gate electrode CMP process of the non-I/O FETs, and therefore allows a process to form I/O FETs with a larger footprint—e.g., greater than about 1 μm2, between about 1 μm2and about 10 μm2, or greater than about 10 μm2(e.g., about 20 μm2). In some embodiments, the method described herein is compatible with planar and non-planar transistor structures (e.g., finFETs). In some embodiments, a structure includes a first transistor formed on a first region of a semiconductor substrate, where the first transistor includes a gate dielectric; a polysilicon gate electrode disposed on the gate dielectric with the gate dielectric being wider than the gate electrode; and a first spacer structure abutting a sidewall of the polysilicon gate electrode so that a sidewall of the spacer structure is aligned to a sidewall of the gate dielectric. The structure further includes a second transistor formed on a second region of the semiconductor substrate, where the second transistor is narrower than the first transistor and includes a high-k gate dielectric; a metal gate electrode disposed on and aligned with the high-k gate dielectric so that a sidewall of the metal gate electrode is aligned to a sidewall of the high-k gate dielectric; and a second spacer structure abutting the sidewalls of the metal gate electrode and high-k gate dielectric. In some embodiments, a method includes depositing a silicon oxide layer on a first region of a semiconductor substrate; depositing a high-k dielectric layer, thinner than the silicon oxide layer, on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide layer and high-k dielectric layer; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes forming a first spacer on sidewalls of the first polysilicon gate electrode structure so that outer sidewalls of the first spacer are aligned to sidewalls of the silicon oxide layer; forming a second spacer on sidewalls of the second polysilicon gate electrode structure and the high-k dielectric layer; and replacing the second polysilicon gate electrode structure with a metal gate electrode structure. In some embodiments, a structure includes a first transistor formed on a first region of a semiconductor substrate, where the first transistor includes a silicon oxide gate dielectric; a polysilicon gate electrode disposed on the silicon oxide gate dielectric and having sidewall edges not aligned to sidewall edges of the silicon oxide gate dielectric; and a first spacer structure with inner sidewalls abutting the sidewall edges of the polysilicon gate electrode. The structure further includes a second transistor formed on a second region of the semiconductor substrate, where the second transistor is narrower than the first transistor and includes a high-k gate dielectric; a metal gate electrode disposed on the high-k gate dielectric so that sidewall edges of the metal gate electrode are aligned to sidewall edges of the high-k gate dielectric; and a second spacer structure abutting the sidewall edges of the metal gate electrode and the high-k gate dielectric. It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way. The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 35,579 |
11942476 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. The present disclosure will be described with respect to embodiments for semiconductors formed of fin field effect transistors (FinFETs). The embodiments of the disclosure may also be applied, however, to a variety of integrated circuits. Various embodiments will be explained in detail with reference to the accompanying drawings. FIGS.1A to15Aare perspective views of a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.FIGS.1B to15Bare side views ofFIGS.1A to15A, respectively.FIG.15Cis a cross-sectional view taken along the metal gate direction MG ofFIG.15A. Reference is made toFIGS.1A and1B. The semiconductor device10includes a substrate with plural patterned fins stood upright and device features can be formed on, above or over the plural patterned fins. The substrate100may be a bulk silicon substrate. Alternatively, the substrate100may include an elementary semiconductor, such as silicon (Si) or germanium (Ge) in a crystalline structure; a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); or combinations thereof. Possible substrates100also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate100, in a P-well structure, in an N-well structure, in a dual-well structure, and/or using a raised structure. The substrate100may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device. Semiconductor fins110are formed over the substrate100within different functional regions, e.g., a LOGIC region and/or a memory region. In some embodiments, the semiconductor fins110may be of the same type or of different types. For example, some of the fins110are n-type semiconductor fins, and the others of the fins110are p-type semiconductor fins, and the present disclosure is not limited in this respect. In some embodiments, a pad layer122and a mask layer123are disposed on the semiconductor fins110. In some embodiments, the pad layer122may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad layer122may act as an adhesion layer between the semiconductor fins110and the mask layer123. In some embodiments, the mask layer123is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer123is used as a hard mask during following processes, such as photolithography. The semiconductor fins110may be formed by suitable method. For example, a pad layer and a mask layer may be blanketed over the substrate100. A patterned photo-sensitive layer is formed over the substrate100. Then, the pad layer, the mask layer, and the substrate100may be patterned using one or more photolithography processes with the patterned photo-sensitive layer, including double-patterning or multi-patterning processes, to form the pad layer122, the mask layer123, and the semiconductor fins110. Reference is made toFIGS.2A and2B. A liner or spacer layer120is formed over the substrate100. In some embodiments, the liner or spacer layer120is formed to conformally cover the semiconductor fins110by suitable deposition process, such as atomic layer deposition (ALD). Thus, plural trenches125are formed in the liner or spacer layer120and between the semiconductor fins110and210. For example, some trenches125are formed between relatively close fins110, and some other trenches125are formed between relatively distant fins110. In some embodiments, a thickness of the liner or spacer layer120is about 12 nm to about 19 nm, and the present disclosure is not limited in this respect. In certain embodiments, the term “about” used in this context means greater or less than the stated value or the stated range of values by a percentage such as 5%, 10%, 15%, etc. of the stated values. However, in some embodiments, if two adjacent fins are too close, the liner or spacer layer120may be filled in the space between the fins. For example, since the semiconductor fins110at the left side inFIG.3Bare close enough, the liner or spacer layer120is filled in the space between the semiconductor fins110, and no trench is formed therebetween. Reference is made toFIGS.3A and3B. One or more etching process(es) are performed to remove parts of the semiconductor fins110and the liner or spacer layer120to form a recess135and cut each of the fins110into two portions such that end surfaces of two separate portions of each fin110are exposed from the recess135. As a result, the recess135and the larger trench125between the patterned fins110collectively form a cross-shaped concave area (i.e., from a top view) exposing parts of the substrate100. Some mask layer may be used and patterned to define the cross-shaped area before the etching process(es). In some embodiments, the etching process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Reference is made toFIGS.4A and4B. A dielectric layer140is formed over the substrate100and filling the trenches125and the recess135. In some embodiments, the portions of the dielectric layer140filled in the trenches125may be referred to as dielectric fin or dummy fins145. The dummy fins145are formed between some of the semiconductor fins110. For example, a dummy fin145is formed between immediate-adjacent two of the semiconductor fins110. The dummy fin145may be spaced from the adjacent semiconductor fins110by the liner or spacer layer120, and a bottom of the dummy fin145may also be spaced from the substrate100by the liner or spacer layer120. The dielectric layers140and the dummy fin145may also be collectively referred as a dielectric dummy fin layer. In some embodiments, the dielectric layer140is in contact with end surfaces of the semiconductor fins110. In some embodiments, the relative large trench125and the recess135covered by the dielectric layer140collectively form a cross-shaped concave recess135a. The dielectric layer140surrounding the recess135amay be spaced from the adjacent semiconductor fins110by the liner or spacer layer120, and a bottom of the dielectric layer140may also be spaced from the substrate100by the liner or spacer layer120. In some embodiments, the dielectric layer140may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, SiO2, Si3N4, SiOCN, or metal oxides, such as HfO2, ZrO2, HfAlOx, HfSiOxand the like and may be formed by methods utilized to form such a layer, such as CVD, plasma enhanced CVD, sputter, and other methods known in the art. Reference is made toFIGS.5A and5B. A silicon oxide148is deposited in the cross-shaped concave recess135a. In some embodiments, the silicon oxide148may be deposited by first depositing a flowable oxide and converting the flowable oxide to silicon oxide. The flowable oxide may be deposited using a spin on glass (SOG) or flowable chemical vapor deposition (FCVD) process. Unlike the HDPCVD process, the SOG process and the FCVD process do not damage the semiconductor substrate100(the sidewall and bottom of the trench). Thus, the current leakage caused by the HDPCVD process can be avoided. After being deposited in the recess135a, the flowable oxide may be cured at a temperature ranging from about 600 degrees C. to about 1000 degrees C., to convert the flowable oxide to silicon oxide. From a top view, a cross-shaped area, i.e., the silicon oxide148, is formed between separate and adjacent dielectric layers140. Reference is made toFIGS.6A and6B. One or more etching process(es) are performed to remove at least part of the dielectric layer140and top portions of the silicon oxide148until a top surface of the remaining silicon oxide148ais below a top portion110aof the semiconductor fin110. In some embodiments, the top surface of the remaining silicon oxide148amay be at least below an interface between the pad layer122and the semiconductor fin110. After etching the silicon oxide148, the oxide-filled recess135ais a concave recess with the dielectric layer140as surrounding sidewalls and the remaining silicon oxide148aas a bottom. In some embodiments, the etching process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Reference is made toFIGS.7A and7B. A dielectric layer144is formed conformally over the dielectric layer140and the recesses135a. The recess135aafter being covered by the dielectric layer144still forms a concave top surface. Another oxide layer150is formed over the dielectric layer144and filled into the concave top surface of the dielectric layer144such that a substantially flat top surface may be formed. The oxide layer150may be formed by the same process as the oxide layer148, eg., flowable chemical vapor deposition (FCVD) process or different process. Reference is made toFIGS.8A and8B. Then, a chemical-mechanical planarization (CMP) process is performed to remove the excessive oxide layer150and dielectric layers140,144until the semiconductor fins110are exposed. After the CMP process, a substantially flat top surface is formed over the semiconductor fins110, the dummy fins145, the dielectric layers140and144a, and the remained oxide layer150a. That is, top surfaces of the semiconductor fins110and top surfaces of the dielectric layers140and144aare substantially coplanar, and top surfaces of the semiconductor fins110and a top surface of the dummy fin145are substantially coplanar. In some embodiments, a dual helmet structure152including the remained oxide layer150a, the remained dielectric layer144aand a top portion of the dielectric layer140may be used as a CMP stop feature. Compared with using merely the dielectric layers144aand140as the CMP stop feature, the dual helmet structure152with an oxide scheme, i.e., the remained oxide layer150a, is a CMP favored feature due to less CMP process end point curve noise (e.g., CMP end point signal noise). That is, a clear CMP end point signal is obtained due to the dual helmet structure152with a large oxide surface, e.g., a by-product generated by the fin110top materials, low k dielectric materials (e.g.140and144), the remained oxide layer150aand a CMP slurry may serve as the CMP stop favored feature. After the CMP process, the semiconductor fins110are exposed with the pad layers122and the mask layers123removed, and all top surfaces of the semiconductor fins110may be substantially coplanar. Reference is made toFIGS.9A and9B. One or more etching process(es) are performed to remove the remained oxide layer150aand at least part of the liner or spacer layers120between adjacent semiconductor fins110and/or between the semiconductor fin110and the dummy fin145. An enough height of each semiconductor fin110is exposed after performing the etching process(es). In some embodiments, the etching process(es) may be performed until top surfaces of the remained liner or spacer layers120may be below a top surface of the remaining silicon oxide148a. In some embodiments, the liner or spacer layers120may be referred as a isolation structure. After performing the etching process(es), a second dielectric stage160with a dielectric concave top portion is formed within an isolation area and between the semiconductor fins110. In some embodiments, the dielectric stage160may have a cross-shaped concave top portion. In other embodiments, the dielectric stage160may include an oxide dielectric core (e.g., the silicon oxide148a) and a non-oxide dielectric layer (e.g.,140and144a) entirely wrapping the oxide dielectric core. In other embodiments, the oxide dielectric core may be made from a flowable oxide. In other embodiments, the dielectric layer140surrounding the dielectric stage160and the dummy fin145may be made from the same materials by the same deposition process. In other embodiments, the dielectric layer144aon top of the silicon oxide148amay be made from materials different from the dielectric layer140. The dielectric layer144amay be referred as a helmet layer for the dielectric stage160. In other embodiments, the dielectric layer144aon top of the silicon oxide148amay include, for example, a high-k dielectric material such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or combinations thereof. In some embodiments, the etching process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO3/CH3COOH solution, or other suitable solution. The dry and wet etching processes have etching parameters that can be tuned, such as etchants used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. For example, a wet etching solution may include NH4OH, KOH (potassium hydroxide), HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof. Dry etching processes include a biased plasma etching process that uses a chlorine-based chemistry. Other dry etchant gasses include CF4, NF3, SF6, and He. Dry etching may also be performed anisotropically using such mechanisms as DRIE (deep reactive-ion etching). Reference is made toFIGS.10A and10B. A thin oxide layer155is formed over a top surface of the dielectric stage160, outer surfaces of the semiconductor fins110and an outer surface of the dummy fin145. The oxide layer155may act as gate dielectric in later process. Reference is made toFIGS.11A and11B. Plural dummy gates180are formed over the oxide layer155, in which the dummy gates180across the semiconductor fins110, the dummy fin145and the dielectric stage160, and the dummy gates180bcross the dielectric stage160. The dielectric stage160anchors the dummy gates180on the isolation area to avoid the risk of dummy gate collapse due to a high aspect ratio. Without the dielectric stage160, the dummy gates180bmay be patterned with a high aspect ratio and have a relatively high risk of collapse. In some embodiments, the dummy gates180bmay stand within a concave area of the dielectric layer144a(part of the dielectric stage160). In some embodiments, the dummy gates180bmay have its bottom at least partially in contact with the concave area of the dielectric layer144a(part of the dielectric stage160). Since the dielectric stage160has its top portion that is substantially level with top portions of the semiconductor fins110and the dummy fins145around, at least the dummy gates180bare formed with a relatively small aspect ratio compared with that of the dummy gates formed on the substrate without the isolation structure (not shown in the drawings). In some embodiments, mask layers182and184are formed over the dummy gates180. The mask layers182and184acts as a hard mask during the patterning process of the dummy gates180and may act as a hard mask during the following processes, such as etching. In some embodiments, the mask layers182and184may include silicon oxide, silicon nitride and/or silicon oxynitride. In some embodiments, the dummy gates180may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gates may be doped poly-silicon with uniform or non-uniform doping. In some embodiments, the dummy gates180may be formed by, for example, forming a dummy gate material layer over the oxide layer155. Patterned masks, such as mask layers182and184, are formed over the dummy gate material layer. Then, the dummy gate material layer may be patterned using one or more etching processes, such as one or more dry plasma etching processes or one or more wet etching processes. During the etching process, the patterned mask may act as an etching mask. At least one parameter, such as etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate, of the patterning (or etching) recipe can be tuned. For example, dry etching process, such as plasma etching, may be used to etch the dummy gate material layer and the oxide layer155until the semiconductor fins110and the dummy fin145are exposed. Reference is made toFIGS.12A and12B. Gate spacer structures including plural gate spacers190on opposite sidewalls of the dummy gates180are formed. In some embodiments, at least one of the gate spacers190includes single or multiple layers. The gate spacers190can be formed by blanket depositing one or more dielectric layer(s) on the previously formed structure. The dielectric layer(s) may include silicon nitride (SiN), oxynitride, silicon carbon (SiC), silicon oxynitride (SiON), oxide, and the like. The gate spacers190may be formed by methods such as CVD, plasma enhanced CVD, sputter, or the like. The gate spacers190may then be patterned, such as by one or more etch processes to remove horizontal portions of the gate spacers190from the horizontal surfaces of the structure. The oxide layer155exposed from the dummy gates180and the gate spacers190are removed by suitable process, such as etching. The remained portions of the oxide layer155are disposed under the dummy gates180and the gate spacers190. Thus, the remained portions of the oxide layer155may be referred to as gate dielectric. Also, the dummy gate180and the remained oxide layer155may collectively be referred to as a dummy gate stack. Portions of the semiconductor fins110and the dummy fins145are exposed after the oxide layer155are partially removed. Then, plural source/drain features200are respectively formed over the exposed semiconductor fins110of the substrate100. In some embodiments, the adjacent source/drain features200are spaced by and in contact with the dummy fin145such that the formation of the source/drain features200are easily to be controlled. In some embodiments, the source/drain features200may be epitaxy structures, and may also be referred to as epitaxy features200. The source/drain features200may be formed using one or more epitaxy or epitaxial (epi) processes, such that Si features, SiGe features, and/or other suitable features can be formed in a crystalline state on the semiconductor fins110. In some embodiments, the source/drain features200may be cladding over the semiconductor fins110. In some embodiments, lattice constants of the source/drain features200are different from lattice constants of the semiconductor fins110, such that channels in the semiconductor fins110are strained or stressed to enable carrier mobility of the semiconductor device and enhance the device performance. In some embodiments, the source/drain features200may include semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), silicon carbide (SiC), or gallium arsenide phosphide (GaAsP). The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins110(e.g., silicon). The source/drain features200may be in-situ doped. The doping species include P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain features200are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the source/drain features200. One or more annealing processes may be performed to activate the source/drain features200. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes. In some embodiments, the source/drain features200over the semiconductor fins100may include the same doping-type, and the source/drain feature200over one of the semiconductor fins100may include doping-type different from that of the source/drain features200over the other of the semiconductor fins100. For example, some source/drain features200may be n-type, and the other source/drain features200may be p-type, and vise versa. Reference is made toFIGS.13A and13B. An etching stop layer215and interlayer dielectric220is formed over the dielectric stage160, the substrate100and covers the source/drain features200. Then, a CMP process is performed to remove the excessive interlayer dielectric220, and the mask layers182and184(referring toFIGS.11A and11B) until the dummy gates180are exposed. In some embodiments, the interlayer dielectric220may include silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, silicon germanium, or combinations thereof. The interlayer dielectric220may be formed by a suitable technique, such as CVD, ALD and spin-on coating. In some embodiments, air gaps may be created in the interlayer dielectric220. Then, a replacement gate (RPG) process scheme is employed. The dummy gate stacks185are replaced with gate stacks230. For example, the dummy gate stacks185are removed to from a plurality of gate trenches. The dummy gate stacks185are removed by a selective etch process, including a selective wet etch or a selective dry etch, and carries a substantially vertical profile of the gate spacers190. The gate trenches expose portions of the semiconductor fins110and210of the substrate100. Then, the gate stacks230are formed respectively in the gate trenches and cover the semiconductor fins110and210of the substrate100. The gate stacks230may be also referred as the gate structures. The gate stacks230include an interfacial layer (not shown), gate dielectrics232formed over the interfacial layer, and gate metals234formed over the gate dielectrics232. The gate dielectrics232, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The gate metals234may include a metal, metal alloy, and/or metal silicide. In some embodiments, the gate metals234included in the gate stacks230may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a work function to enhance the device performance (work function metal layer), liner layer, wetting layer, adhesion layer and a conductive layer of metal, metal alloy or metal silicide. For example, the gate metals234may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include a plurality of layers. The work function layer(s) may be deposited by CVD, PVD, electro-plating and/or other suitable process. In some embodiments, the interfacial layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, and/or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable method. The gate dielectrics232may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric212may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The gate dielectrics232may be formed by ALD, PVD, CVD, oxidation, and/or other suitable methods. Reference is made toFIGS.14A and14B. An etching process is performed to remove portions of the gate stacks230. During the etching process, plural openings235are formed in the gate stacks230. In some embodiments, the openings235may expose at least portions of the dummy fin145and the dielectric layer144a(part of the dielectric stage160), as shown inFIG.15C. Then, plural isolation features240are formed in the openings235. In some embodiments, the isolation features240may be formed by depositing a dielectric layer blanketing the substrate100. Then, a CMP process is performed to remove the excessive dielectric layer until the gate stacks230are exposed. Some of the isolation features240are in contact with the dielectric layer144aand the dummy fin145. The gate stack230with the isolation features240may be divided into separate parts, as shown inFIG.15C. The isolation features may also be referred as gate isolation structures. Reference is made toFIGS.15A and15B. An etching process is performed to remove portions of the interlayer dielectric220. Thus, plural openings245are formed in the interlayer dielectric220and the etching stop layer215to expose the source/drain features200and the dummy fins145. Then, plural contacts250are formed in the openings245. The contacts250may be formed by depositing a conductive material layer over the substrate100and following with a CMP process until the gate stacks230are exposed. In some embodiments, the contacts250are in contact with the source/drain features200and the dummy fins145. For example, inFIG.15B, the contact250is in contact with the source/drain features200over the semiconductor fins110, and is in contact with the dummy fins145between the semiconductor fins110. The dummy fin145can support the contact250, such that the contact250does not extend further into a space between the source/drain features200. In some embodiments, at least one of the contacts250includes a barrier layer251and conductive layer252. In some embodiments, the source/drain features200have their sidewalls in contact with the dielectric layer40and the dummy fin145. In some embodiments, the conductive layer252may include suitable metal, such as TiN, WN, TaN, or Ru, which performs in a p-type FinFET. In some alternative embodiments, the metal layer may include suitable metal, such as Ti, Ag, Al, TiAl, TiAlN, TiAlC, TiAlCN, TaC, TaCN, TaSiN, Mn, or Zr, which performs in an n-type FinFET. In some other embodiments, the contacts250may be multi-layer including, work function layers, liner layers, interface layers, seed layers, adhesion layers, barrier layers and so on. Reference is made toFIG.15C, which is a cross-sectional view taken along the metal gate direction MG ofFIG.15A. In some embodiments, one isolation feature240is in contact with the dummy fin145while another isolation feature240is in contact with a top surface of the dielectric stage160, e.g., a top surface of the dielectric layer144asuch that the gate stack230may be divided into separate parts. In some embodiments, the dielectric stage160has a helmet layer (i.e.,144a) with a thinner portion and two thicker portions with the helmet depth (D), and the thinner portion is coupled between the two thicker portions with the helmet depth (D). A thickness difference between the thinner portion and the thicker portion is referred as the concave depth (d). In some embodiments, a top surface of the helmet layer (i.e.,144a) is higher than a top surface of the liner or spacer layer120(i.e., an isolation structure). In some embodiments, the dielectric concave top portion of the dielectric stage160may be equipped with a total helmet depth (D) ranging from about 15 nm to about 80 nm in order to cover the oxide148aunderneath and anchor the dummy gates on its top surface. When the total helmet depth (D) is smaller than 15 nm, it may be easily etched and the oxide148aunderneath is thus exposed. In some embodiments, the dielectric concave top portion of the dielectric stage160may be equipped with a concave depth (d) ranging from about 3 nm to about 40 nm, and this depth (d) range may be easily formed on the helmet layer (i.e.,144a) along with the total helmet depth (D) ranging from about 15 nm to about 80 nm. In some embodiments, the dielectric layer140wrapping around the dielectric stage160may be equipped with a helmet width (W) greater than about 60 nm along the metal gate direction MG, i.e., a longitudinal direction of the gate stack. The helmet width (W) greater than about 60 nm is enough to allow a concave helmet layer (i.e.,144a) formed thereon with an oxide-filled that is favored for CMP semiconductor fins stop feature due. In some embodiments, a top surface of the dielectric layer140is substantially coplanar with a top surface of the helmet layer (i.e.,144a). In some embodiments, a top surface of the dielectric layer140is substantially coplanar with top surfaces of the fins110. According to aforementioned embodiments, a semiconductor device includes a dielectric stage located over a substrate and between the semiconductor fins of the substrate. The dielectric stage has a concave shape helmet that is substantially coplanar with top surfaces of the semiconductor fins and allows dummy gates to be formed thereon. The dielectric stage may include an oxide dielectric core and a non-oxide dielectric layer wrapping the oxide dielectric core, and the oxide dielectric core may be a flowable oxide. With such configurations, the dielectric stage anchors the dummy gates on its top surface to avoid the risk of dummy gate collapse due to a high aspect ratio. Also, the concave helmet with an oxide-filled within the concave part is CMP favored due to less CMP end point curve noise, and the oxide surface is favored for CMP semiconductor fins stop feature. An embodiment of the present disclosure is a semiconductor device having a substrate and first, second fins, an isolation structure between the first and second fins, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure. An embodiment of the present disclosure is that the helmet layer has a first portion, a second portion, and a third portion, the first portion connects the second portion and the third portion, and each of the second portion and the third portion is thicker than the first portion. An embodiment of the present disclosure is that a thickness of the second portion of the helmet layer is in a range from about 15 nm to about 80 nm. An embodiment of the present disclosure is that a thickness difference between the first portion and the second portion of the helmet layer is in a range from about 3 nm to about 40 nm. An embodiment of the present disclosure is the semiconductor device further including a dielectric dummy fin layer wrapping around the dielectric stage. An embodiment of the present disclosure is that a top surface of the dielectric dummy fin layer is substantially coplanar with the top surface of the helmet layer. An embodiment of the present disclosure is that a top surface of the dielectric dummy fin layer is substantially coplanar with a top surface of the first fin. An embodiment of the present disclosure is the semiconductor device further including a gate structure over the first fin, the helmet layer, and the dielectric dummy fin layer. An embodiment of the present disclosure is that a width of the dielectric dummy fin layer along a longitudinal direction of the gate structure is greater than about 60 nm. An embodiment of the present disclosure is the semiconductor device further including a first epitaxy structure adjoining the first fin and in contact with the dielectric dummy fin layer. An embodiment of the present disclosure is the semiconductor device further including a second epitaxy structure adjoining the second fin and in contact with the dielectric dummy fin layer. An embodiment of the present disclosure is the semiconductor device further including a gate structure over the first fin and the helmet layer, and a gate isolation structure in the gate structure and landing on the helmet layer. An embodiment of the present disclosure is a semiconductor device having first fin and second fins, a dielectric stage between an end surface of the first fin and an end surface of the second fin, a dielectric dummy fin layer wrapping around the dielectric stage, and a helmet layer over the dielectric stage. An embodiment of the present disclosure is that a top surface of the dielectric dummy fin layer is substantially coplanar with a top surface of the first fin. An embodiment of the present disclosure is that the dielectric dummy fin layer is in contact with the end surface of the first fin. An embodiment of the present disclosure is that the dielectric dummy fin layer is in contact with the end surface of the second fin. An embodiment of the present disclosure is a method for depositing a first dielectric layer over a first fin and a second fin; depositing a dielectric dummy fin layer over the first dielectric layer, wherein the dielectric dummy fin layer has a first portion over top surfaces of the first fin and the second fin; depositing a second dielectric layer over the dielectric dummy fin layer; removing a first portion of the second dielectric layer over a top surface of the first portion of the dielectric dummy fin layer, wherein a second portion of the second dielectric layer remains between the first fin and the second fin; recessing the second portion of the second dielectric layer; removing the first portion of the dielectric dummy fin layer, wherein a second portion of the dielectric dummy fin layer remains between the first fin and the second fin; depositing a helmet layer over the recessed second portion of the second dielectric layer and the second portion of the dielectric dummy fin layer; depositing a third dielectric layer over the helmet layer; and removing the third dielectric layer, the helmet layer, the dielectric dummy fin layer, and the first dielectric layer over the top surfaces of the first fin and the second fin. An embodiment of the present disclosure is the method further including depositing the helmet layer over the recessed second portion of the second dielectric layer and the second portion of the dielectric dummy fin layer is performed such that the helmet layer defines a recess over the recessed second portion of the second dielectric layer, and a bottom of the recess is lower than the top surfaces of the first fin and the second fin. An embodiment of the present disclosure is the method further including etching the first dielectric layer, the first fin and the second fin to expose end surfaces of the first fin and the second fin prior to depositing the dielectric dummy fin layer. An embodiment of the present disclosure is the method further including depositing the dielectric dummy fin layer is performed such that the dielectric dummy fin layer is in contact with the end surfaces of the first fin and the second fin. In some embodiments, a method for forming a semiconductor device includes: forming a semiconductor fin extending upwardly from a substrate; breaking the semiconductor fin into two separate fin structures; conformally forming a first dielectric layer over the fin structures; after conformally forming the first dielectric layer, filling a recess between the fin structures with a flowable oxide; etching back the flowable oxide to lower a top surface of the flowable oxide to a level below top surfaces of the fin structures; conformally forming a second dielectric layer over the first dielectric layer and the etched back flowable oxide, such that a laterally portion of the second dielectric layer in the recess is lower than the top surfaces of the fin structures; and planarizing the first and second dielectric layers to expose the fin structures, while leaving the laterally portion of the second dielectric layer covering the flowable oxide. In some embodiments, further includes: curing the flowable oxide is performed prior to etching back the flowable oxide. In some embodiments, the flowable oxide is formed of a material different than the first and second dielectric layers. In some embodiments, planarizing the first and second dielectric layers is performed such that top surface of first and second dielectric layers are coplanar with the top surfaces of the fin structures. In some embodiments, the method further includes forming a second flowable oxide layer over the second dielectric layer to fill into the recess, wherein planarizing the first and second dielectric layers is performed on the second flowable oxide, such that top surfaces of the first and second dielectric layers in the recess are coplanar with a top surface of the second flowable oxide in the recess. In some embodiments, the planarized second flowable oxide layer in the recess has a thickness in a range from about 3 nm to about 40 nm after planarizing the first and second dielectric layers is complete. In some embodiments, the method further includes removing the planarized second flowable oxide layer after planarizing the first and second dielectric layers. In some embodiments, the second dielectric layer has a material the same as the first dielectric layer. In some embodiments, the second dielectric layer is formed of metal oxide. In some embodiments, the second dielectric layer is formed of a carbon-containing material. In some embodiments, a method for forming a semiconductor device includes: forming first and second semiconductor fins extending upwardly from a substrate; conformally forming a spacer layer over the first and second semiconductor fins; conformally forming a first dielectric layer over the spacer layer; after conformally forming the first dielectric layer, forming a flowable oxide layer laterally between the first and second semiconductor fins; conformally forming a second dielectric layer over the first dielectric layer and the flowable oxide layer, wherein the second dielectric layer has a portion laterally between the first and second semiconductor fins; performing a chemical-mechanical planarization (CMP) process on the first and second dielectric layers and the spacer layer, such that the first and second semiconductor fins are exposed; after performing the CMP process, thinning down the spacer layer; and after thinning down the spacer layer, forming a gate structure extending across the first and second semiconductor fins. In some embodiments, thinning down the spacer layer is performed such that a topmost surface of the spacer layer is lower than a top surface of the flowable oxide layer. In some embodiments, thinning down the spacer layer is performed such that a topmost surface of the spacer layer is higher than a lateral portion of the first dielectric layer. In some embodiments, thinning down the spacer layer is performed such that a vertical portion of the first dielectric layer above a topmost surface of the spacer layer has a width narrower than below the topmost surface of the spacer layer. In some embodiments, the second dielectric layer has a material the same as the first dielectric layer. In some embodiments, the second dielectric layer is formed of a silicon-containing material. In some embodiments, a method for forming a semiconductor device includes: depositing a first dielectric layer over a first fin and a second fin; depositing a dielectric dummy fin layer over the first dielectric layer, wherein the dielectric dummy fin layer has a first portion over top surfaces of the first fin and the second fin; depositing a second dielectric layer over the dielectric dummy fin layer; removing a first portion of the second dielectric layer over a top surface of the first portion of the dielectric dummy fin layer, wherein a second portion of the second dielectric layer remains between the first fin and the second fin; recessing the second portion of the second dielectric layer; removing the first portion of the dielectric dummy fin layer, wherein a second portion of the dielectric dummy fin layer remains between the first fin and the second fin; depositing a helmet layer over the recessed second portion of the second dielectric layer and the second portion of the dielectric dummy fin layer; depositing a third dielectric layer over the helmet layer; and removing the third dielectric layer, the helmet layer, the dielectric dummy fin layer, and the first dielectric layer over the top surfaces of the first fin and the second fin. In some embodiments, depositing the helmet layer over the recessed second portion of the second dielectric layer and the second portion of the dielectric dummy fin layer is performed such that the helmet layer defines a recess over the recessed second portion of the second dielectric layer, and a bottom of the recess is lower than the top surfaces of the first fin and the second fin. In some embodiments, further includes: etching the first dielectric layer, the first fin and the second fin to expose end surfaces of the first fin and the second fin prior to depositing the dielectric dummy fin layer. In some embodiments, depositing the dielectric dummy fin layer is performed such that the dielectric dummy fin layer is in contact with the end surfaces of the first fin and the second fin. In some embodiments, a method includes forming a semiconductor fin on a substrate; conformally forming a dielectric layer over the semiconductor fin; depositing an oxide layer over the dielectric layer; etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin; conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer; planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin; forming a gate structure extending across the semiconductor fin; forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure. In some embodiments, after planarizing the metal oxide layer and the dielectric layer, the dielectric layer has an U-shaped cross-sectional profile taken along a lengthwise direction of the gate structure and cupping an underside of the metal oxide layer. In some embodiments, the dielectric layer has a lateral portion greater than about 60 nm. In some embodiments, after planarizing the metal oxide layer and the dielectric layer, the metal oxide layer comprises edge regions contacting the dielectric layer and a central region laterally between the edge regions and having a top surface in a lower position than edge regions. In some embodiments, the top surface of the central region is in a lower position than a top surface of the semiconductor fin. In some embodiments, the edge regions of the metal oxide layer have top surfaces in a position level with a top surface of the dielectric layer. In some embodiments, the metal oxide layer comprises HfO2, ZrO2, HfAlOx, or HfSiOx. In some embodiments, the dielectric layer is made of a same material as the metal oxide layer. In some embodiments, the dielectric layer is made of a different material than the metal oxide layer. In some embodiments, depositing the oxide layer is performed by a flowable chemical vapor deposition process. In some embodiments, a method includes forming first and second nanostructured pedestals on a substrate; conformally forming a first dielectric layer over the first and second nanostructured pedestals; forming an oxide material on the first dielectric layer, the first dielectric layer cupping an underside of the oxide material; conformally forming a second dielectric layer over the first dielectric layer and the oxide material; planarizing the first and second dielectric layers to expose the first and second nanostructured pedestals, while leaving a remainder of the second dielectric layer covering the oxide material; forming a first metal layer wrapping around the first nanostructured pedestal and a second metal layer wrapping around the second nanostructured pedestal; growing first epitaxial structures on opposite sides of the first metal layer and second epitaxial structures on opposite sides of the second metal layer. In some embodiments, the remainder of the second dielectric layer comprises edge regions contacting the first dielectric layer and a central region laterally between the edge regions, the central region having a thinner thickness than the edge regions from a cross-sectional view. In some embodiments, the oxide material has a top surface in a lower position than top surfaces of the first and second nanostructured pedestals. In some embodiments, the first dielectric layer is made of a metal oxide. In some embodiments, the first dielectric layer comprises SiCN, SiN, or SiOCN. In some embodiments, a semiconductor device includes a first semiconductive channel pattern, a second semiconductive channel pattern, first source/drain patterns, second source/drain patterns, an oxide material, a metal oxide layer, a dielectric layer, and a gate pattern. The first source/drain patterns are on the first channel pattern. The second source/drain patterns are on the second channel pattern. The oxide material is laterally between the first and second semiconductive channel patterns from a cross-sectional view. The metal oxide layer is over the oxide material. The dielectric layer cups an underside of the oxide material and the metal oxide layer. The metal oxide layer includes edge regions contacting the dielectric layer and a central region laterally between the end portions. The central region has a thinner thickness than the edge regions from the cross-sectional view. The gate pattern extends across the first and second semiconductive channel patterns and the dielectric layer. In some embodiments, the thickness of central region of the metal oxide layer is thinner than thicknesses of the edge regions of the metal oxide layer from about 3 nm to about 40 nm. In some embodiments, the edge regions of the metal oxide layer have a thickness in a range from about 15 nm to about 80 nm. In some embodiments, the central region of the metal oxide layer has a top surface in a lower position than a top surface of the dielectric layer. In some embodiments, the semiconductor device further includes a spacer layer underlying the dielectric layer and further extending to laterally surround a lower portion of the dielectric layer and lower portions of the first and second semiconductive channel patterns. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 52,401 |
11942477 | DETAILED DESCRIPTION First, an exemplary example of a semiconductor device according to an embodiment will be described with reference toFIG.1.FIG.1illustrates a perspective view of a semiconductor device according to an embodiment. Referring toFIG.1, a semiconductor device1according to an exemplary embodiment may include a first circuit region C1. The semiconductor device1, according to the exemplary embodiment, may include a semiconductor chip, a semiconductor package formed using a single semiconductor chip, a semiconductor package formed using two or more semiconductor chips, or an electronic device formed using such semiconductor packages. In an implementation, the semiconductor device1may include a first circuit region C1in which transistors and the like are formed. Next, an exemplary example of the semiconductor device1including the first circuit region C1will be described with reference toFIGS.2to4B. InFIGS.2to4,FIG.2illustrates a plan view of the first circuit region C1of the semiconductor device1described above,FIG.3illustrates a cross-sectional view of a region taken along line I-I′ inFIG.2,FIG.4Aillustrates a cross-sectional view of a region taken along line IIa-IIa′ inFIG.2, andFIG.4Billustrates a cross-sectional view of a region taken along line IIb-IIb′ inFIG.2. Referring toFIGS.2,3,4A and4B, a semiconductor substrate3may be provided. The semiconductor substrate3may be formed of a semiconductor material such as silicon. Active regions9aand9band an isolation region6may be on the semiconductor substrate3. The active regions9aand9bmay include a first active region9aand a second active region9b. The first active region9amay include a first lower active region9a_1, and first upper active regions9a_2on the first lower active region9a_1. The second active region9bmay include a second lower active region9b_1, and second upper active regions9b_2on the second lower active region9b_1. The first and second lower active regions9a_1and9b_1may protrude from the semiconductor substrate3in a vertical direction Z perpendicular to the semiconductor substrate3(e.g., perpendicular to a planar surface of the semiconductor substrate3). The first upper active regions9a_2may protrude from the first lower active region9a_1in the vertical direction Z, and may be spaced apart from each other. The second upper active regions9b_2may protrude from the second lower active region9b_1in the vertical direction Z, and may be spaced apart from each other. The isolation region6may include a second isolation region6bsurrounding side surfaces of the first and second lower active regions9a_1and9b_1, and defining the first and second lower active regions9a_1and9b_1; and a first isolation region6aoverlapping the first and second lower active regions9a_1and9b_1, and covering the side surfaces of the first and second upper active regions9b_2and9b_2on the first and second lower active regions9a_1and9b_1. The isolation region6may include silicon oxide. The first and second upper active regions9a_2and9b_2may protrude from the first and second lower active regions9a_1and9b_1in the vertical direction Z, and may extend through the first isolation region6a. For example, the first and second upper active regions9a_2and9b_2may have upper surfaces located on a level higher than that of an upper surface of the first isolation region6a(e.g., the upper surfaces of the first and second upper active regions9a_2and9b_2may be farther from the semiconductor substrate3than the upper surface of the first isolation region6a). Gate line structures63aand63bmay be on the first and second active regions9aand9band the isolation region6, respectively. The gate line structures63aand63bmay include one or more of first gate line structures63aoverlapping the first active region9aand extending onto the isolation region6, and one or more of second gate line structures63boverlapping the second active region9band extending onto the isolation region6. Referring to the plan or top view, the first and second upper active regions9a_2and9b_2may be in the form of a line shape extending in a first direction X, and the gate line structures63aand63bmay be in the form of a line shape extending in a second direction Y, perpendicular to the first direction X. The first and second directions X, Y may be in directions parallel to a horizontal portion of (e.g., the planar surface of) the semiconductor substrate3. As seen from the plan or top view, the first and second upper active regions9a_2and9b_2may intersect the gate line structures63aand63b. In the one or more of first gate line structures63a, when a plurality of first gate line structures63aare provided, a portion of the plurality of first gate line structures63amay be a first dummy line structure63d1partially overlapping the active region9a, and remaining portion thereof may overlap the first active region9aand traverse the first active region9a. In the one or more of second gate line structures63b, when a plurality of second gate line structures63bare provided, a portion of the plurality of second gate line structures63bmay be a second dummy line structure63d2partially overlapping the active region9b, and remaining portion thereof may overlap the second active region9band traverse the second active region9b. Each of the one or more of first gate line structures63amay include a first gate electrode line69a, and a first gate dielectric66acovering a lower surface of the first gate electrode line69aand covering side surfaces of the first gate electrode line69a. In an implementation, each of the one or more of first gate line structures63amay include a first capping line72aon the first gate electrode line69a. The first capping line72amay cover an upper surface of the first gate electrode line69aand upper end portions of the first gate dielectric66a. The upper end portions of the first gate dielectric66amay be under (e.g., closer to the semiconductor substrate3than) the first capping line72a. Each of the one or more of second gate line structures63bmay include a second gate electrode line69b, and a second gate dielectric66bcovering a lower surface of the second gate electrode line69band covering side surfaces of the second gate electrode line69b. In an implementation, each of the one or more of second gate line structures63bmay include a second capping line72bon the second gate electrode line69b. The second capping line72bmay cover an upper surface of the second gate electrode line69band upper end portions of the second gate dielectric66b. The first and second gate dielectrics66aand66bmay include silicon oxide, and/or a high-k dielectric having a dielectric constant higher than that of the silicon oxide. The first and second gate electrode lines69aand69bmay be formed of any one of dopant polysilicon, a metal nitride (e.g., TiN, TaN, WN, or the like) and a metal (e.g., Ti, Ta, W, or the like), or a combination thereof. Depending on characteristics or types of transistors that may be formed on the first and second active regions9aand9b, the first and second gate dielectrics66aand66bmay be formed of the same material as each other, in different thicknesses from each other, or of different materials from each other, and the first and second gate electrode lines69aand69bmay be formed of a conductive material having the same work function as each other, or may be formed of a conductive material having different work functions from each other. In an implementation, the first and second capping lines72aand72bmay be formed of the same material as each other. In an implementation, the first and second capping lines72aand72bmay be formed of a silicon nitride or silicon nitride-based insulating material. In an implementation, the first and second capping lines72aand72bmay be formed of a metal material such as tungsten having electrical conductivity higher than that of a metal nitride to improve electrical characteristics of the semiconductor device. For convenience or for a better understanding of the following, one first gate line structure63atraversing the first active region9aamong the one or more of first gate line structures63a, and one second gate line structure63btraversing the second active region9bamong the one or more of second gate line structures63bwill mainly be described. In an implementation, a semiconductor device may include a plurality of first gate line structures63atraversing the first active region9aamong the one or more of first gate line structures63a, and a plurality of second gate line structures63btraversing the second active region9bamong the one or more of second gate line structures63b. First source/drain regions24amay be on the first active region9a, and second source/drain regions24bmay be on the second active region9b. The first source/drain regions24amay include a portion filling first recess regions21ain the first upper active region9a_2of the first active region9a. The second source/drain regions24bmay include a portion filling second recess regions21bin the second upper active region9b_2of the second active region9b. For example, each of the first source/drain regions24amay be in the form of a bar shape on the first lower active region9a_1and traversing the first upper active regions9a_2. Each of the second source/drain regions24bmay be in the form of a bar shape on the second lower active region9b_1and traversing the second upper active regions9b_2. A first channel region CH1may be formed in the first upper active region9a_2located between the first source/drain regions24a, and a second channel region CH2may be formed in the second upper active region9b_1located between the second source/drain regions24b. The first gate line structure63atraversing the first active region9amay include a portion on the first channel region CH1, and the second gate line structure63btraversing the second active region9bmay include a portion on the second channel region CH2. In a case that the first gate line structure63atraversing the first active region9ais provided in plural, the first channel region CH1may be provided in plural to correspond to the plurality of first gate line structures63a. In a case that the second gate line structure63btraversing the second active region9bis provided in plural, the second channel region CH2may be provided in plural to correspond to the plurality of first gate line structures63a. In an implementation, the first source/drain regions24a, the first channel region CH1in the first upper active region9a_2, between the first source/drain regions24a, the first gate dielectric66aand the first gate electrode line69a, on the first channel region CH1, may constitute a first transistor TR1. The second source/drain regions24b, the second channel region CH2in the second upper active region9b_2, between the second source/drain regions24b, the second gate dielectric66band the second gate electrode line69b, on the second channel region CH2, may constitute a second transistor TR2. In an implementation, the first and second transistors TR1and TR2may be an NMOS transistor or a PMOS transistor. In an implementation, the first transistor TR1may be an NMOS transistor, and the second transistor TR2may be a PMOS transistor. In an implementation, when the first and second transistors TR1and TR2are NMOS transistors, the first and second source/drain regions24aand24bmay have N-type conductivity, and may be formed of a silicon epitaxial layer capable of imparting tensile stress to the first and second channel regions CH1and CH2. In an implementation, when the first and second transistors TR1and TR2are PMOS transistors, the first and second source/drain regions24aand24bmay have P-type conductivity, and may be formed of a silicon-germanium SiGe epitaxial layer capable of imparting compressive stress to the first and second channel regions CH1and CH2. In an implementation, when the first transistor TR1may be an NMOS transistor, the first and source/drain regions24amay be formed of a silicon epitaxial layer capable of imparting tensile stress to the first channel region CH1. When the second transistor TR2is a PMOS transistor, the second source/drain regions24bmay be formed of a silicon-germanium SiGe epitaxial layer capable of imparting compressive stress to the second channel region CH2. As described above, the first gate line structure63amay overlap the first active region9a, and may extend onto the isolation region6, and the second gate line structure63bmay overlap the second active region9b, and may extend onto the isolation region6. The first gate line structure63aand the second gate line structure63bmay have end portions facing each other on the isolation region6between the first and second active regions9aand9b. For example, a first end portion63e1of the first gate line structure63amay face a second end portion63e2of the second gate line structure63b, on the isolation region6between the first and second active regions9aand9b. A gate separation region40may be on the isolation region6between the first and second active regions9aand9b. In an implementation, the gate separation region40may be provided in plural, when the first gate line structure63ais provided in plural and the second gate line structure63bis provided in plural. In an implementation, the gate separation region40may have an upper surface that is coplanar with upper surfaces of the first and second gate line structures63aand63b. For example, the gate separation region40may have an upper surface coplanar with the upper surfaces of the first and second capping lines72aand72bof the first and second gate line structures63aand63b. In an implementation, the gate separation region40may impart tensile stress to the first channel region CH1and the second channel region CH2to help improve the performance of the first and second transistors TR1and TR2. Spacers18may be on the side surfaces of the first and second gate line structures63aand63b, and may extend onto side surfaces of the gate separation region40. Therefore, the first and second gate line structures63aand63band the gate separation region40may be between adjacent spacers18. Referring to the plan or top view, the spacers18may be in the form of a line shape extending in the second direction Y. The spacers18may be formed of an insulating material. For example, the spacers18may be formed of an insulating material such as SiN, SiCN, SiOCN, or the like. The spacers18may include a first spacer portion18acovering the side surfaces of the first and second gate line structures63aand63b, and a second spacer portion18bcovering the side surfaces of the gate separation region40. In an implementation, the first spacer portion18amay have a width that is wider than that of the second spacer portion18b. For example, the second spacer portion18bmay be narrower than the first spacer portion18a. The first gate dielectric66amay cover the lower surface of the first gate electrode line69a, may extend between the first gate electrode line69aand the spacers18, and may extend between the first gate electrode line69aand the gate separation region40. The second gate dielectric66bmay cover the lower surface of the second gate electrode line69b, may extend between the second gate electrode line69band the spacers18, and may extend between the second gate electrode line69band the gate separation region40 An interlayer insulating layer27may be on the second isolation region6bof the isolation region6. On the second isolation region6b, the spacers18may be formed between the gate line structures63aand63band the interlayer insulating layer27, and between the gate separation region40and the interlayer insulating layer27. The interlayer insulating layer27may be formed as a single layer which may be formed of silicon oxide, or may be formed as a laminated structure including silicon oxide and silicon nitride, stacked in sequence. First contact structures78amay be on the first source/drain regions24a, and second contact structures78bmay be on the second source/drain regions24b. The first and second capping lines72aand72b, the spacers18and the gap fill layer52of the gate separation region40may act as an etch mask in an etching process for forming the first and second contact structures78aand78b. Thus, the first and second contact structures78aand78bmay be formed by a self-aligned contact process. An exemplary example of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.5.FIG.5illustrates cross-sectional views of regions taken along line IIIa-IIIa′ and line IVa-IVa′ inFIG.2, respectively. Referring toFIG.5together withFIGS.2to4B, the gate separation region40may be a gate separation region40aincluding a gap fill layer52and a buffer structure. The buffer structure may include a buffer liner46covering bottom and side surfaces of the gap fill layer52. In the first direction X, i.e., in the width direction X of the first and second gate line structures63aand63b, a width of each of the first and second gate line structures63aand63bmay be narrower than a width of the gate separation region40. The buffer liner46of the buffer structure may be between the gap fill layer52and the isolation region6, between the gap fill layer52and the second spacer portions18bof the spacers18, between the gap fill layer52and the first end portion63e1of the first gate line structure63a, and between the gap fill layer52and the second end portion63e2of the second gate line structure63b. In an implementation, the gate separation region40amay further include a lower insulation layer12abetween the buffer liner46and the isolation region6. The buffer liner46may be formed of an insulating material having a dielectric constant higher than that of silicon oxide and a dielectric constant lower than that of silicon nitride. In a case that the isolation region6includes silicon oxide, the buffer liner46may have a dielectric constant higher than that of the silicon oxide of the isolation region6. The buffer liner46may have a dielectric constant higher than that of the lower insulation layer12a. The gap fill layer52may be formed of an insulating material having a dielectric constant higher than that of the insulating material of the buffer liner46. The buffer liner46may be formed of an insulating material having a dielectric constant of between about 4 and about 5. The gap fill layer52may be formed of an insulating material having a dielectric constant higher than the dielectric constant of the buffer liner46, e.g., an insulating material having a dielectric constant of about 5 or more. For example, the buffer liner46may be formed of an insulating material such as SiOCN, SiON, or the like, and the gap fill layer52may be formed of an insulating material such as SiN or the like. A modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.6.FIG.6illustrates a cross-sectional view of a region indicated by line IIIa-IIIa′ inFIG.2. In a modified embodiment, and referring toFIG.6together withFIGS.2to4B, between the second spacer portions18bof the spacers18, the gate separation region40may be a gate separation region40bwhich may be between the second spacer portions18b, and may extend into the isolation region6. The gate separation region40bmay include a gap fill layer52, and a buffer structure having a buffer liner46covering bottom and side surfaces of the gap fill layer52. A lower surface of the gate separation region40bmay be present below a lower surface of the spacers18. Another modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.7.FIG.7illustrates a cross-sectional view of a region indicated by line IIIa-IIIa′ inFIG.2. In another modified embodiment, and referring toFIG.7together withFIGS.2to4B, between the second spacer portions18bof the spacers18, the gate separation region40may be a gate separation region40cwhich may be between the second spacer portions18b,may extend into the isolation region6, and may have a lower portion having a width that is greater than that of an upper portion. The gate separation region40cmay include a gap fill layer52, and a buffer structure having a buffer liner46covering bottom and side surfaces of the gap fill layer52. A lower surface of the gate separation region40cmay be present below a lower surface of the spacers18. Another modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.8.FIG.8illustrates a cross-sectional view of a region indicated by line IVa-IVa′ inFIG.2. In another modified embodiment, and referring toFIG.8together withFIGS.2to4B, between first and second end portions63e1and63e2facing each other in the first and second gate line structures63aand63b, the gate separation region40may be a gate separation region40dwhich may be between the first and second end portions63e1and63e2and may extend into the isolation region6. The gate separation region40dmay include a gap fill layer52, and a buffer structure having a buffer liner46covering bottom and side surfaces of the gap fill layer52. A lower surface of the gate separation region40dmay be present below lower surfaces of the first and second gate line structures63aand63b. Another modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.9.FIG.9illustrates a cross-sectional view of a region indicated by line IVa-IVa′ inFIG.2. In another modified embodiment, and referring toFIG.9together withFIGS.2to4B, between first and second end portions63e1and63e2facing each other in the first and second gate line structures63aand63b, the gate separation region40may be a gate separation region40ewhich may be between the first and second end portions63e1and63e2, may extend into the isolation region6, and may have a lower portion having a width that is greater than a width of an upper portion. The gate separation region40emay include a gap fill layer52, and a buffer structure having a buffer liner46covering bottom and side surfaces of the gap fill layer52. The buffer liner46and the gap fill layer52described with the same reference numerals inFIGS.6to9may be formed of the same material as the buffer liner46and the gap fill layer52described inFIG.5. In an implementation, the following components, referred to by the same reference numerals as the components described above, may be formed of the same materials as those described above. Therefore, with reference to the components described with the same reference numerals, descriptions of the components repeatedly referred to, subsequent to the description of the first-mentioned components, may be understood from the first-mentioned components, and thus may be omitted. Another modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.10.FIG.10illustrates a cross-sectional view of regions indicated by lines IIIa-IIIa′ and IVa-Iva′ inFIG.2, respectively. In another modified embodiment, and referring toFIG.10together withFIGS.2to4B, the gate separation region40may be a gate separation region40fincluding a buffer structure, and a gap fill layer152on the buffer structure. The buffer structure may include a lower buffer layer150. In an implementation, the gate separation region40fmay further include a lower insulation layer12abetween the lower buffer layer150and the isolation region6. The lower buffer layer150may be formed of an insulating material having better gap fill properties and a dielectric constant lower than that of the gap fill layer152. For example, the gap fill layer152may be formed of an insulating material such as silicon nitride or the like, and the lower buffer layer150may be formed of an insulating material such as silicon oxide or the like. The lower insulation layer12amay be formed using a flowable oxide. Another modified embodiment of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIG.11.FIG.11illustrates a cross-sectional view of regions indicated by lines IIIa-IIIa′ and IVa-IVa′ inFIG.2, respectively. In another modified embodiment, and referring toFIG.11together withFIGS.2to4B, the gate separation region40may be a gate separation region40gincluding a buffer structure having a lower buffer layer150and a buffer liner146, and a gap fill layer152. The lower buffer layer150and the gap fill layer152may be sequentially stacked. The buffer liner146may be between the lower buffer layer150and the isolation region6, between the side surfaces of the lower buffer layer150and the interlayer insulating layer27, between the side surfaces of the lower buffer layer150and the first and second end portions63e1and63e2of the first and second gate line structures63aand63b, between the side surfaces of the gap fill layer152and the interlayer insulating layer27, and between the side surfaces of the gap fill layer152and the first and second end portions63e1and63e2of the first and second gate line structures63aand63b. The buffer liner146may be formed of an insulating material having a dielectric constant lower than that of the gap fill layer152, and a dielectric constant higher than that of the lower buffer layer150. For example, the lower buffer layer150may be formed of a silicon oxide or silicon oxide-based insulating material, the gap fill layer152may be formed of silicon nitride, and the buffer liner146may be formed of an insulating material having a dielectric constant of about 4 to about 5, e.g., an insulating material such as SiOCN, SiON, or the like. In an implementation, the gate separation region40gmay further include a lower insulation layer12abetween the lower buffer layer150and the isolation region6. Another modified embodiment of the gate separation region40, described above with reference toFIGS.2to4B, will be described with reference toFIG.12.FIG.12illustrates a cross-sectional view of a region indicated by lines IIIa-IIIa′ and IVa-IVa′ inFIG.2, respectively. In another modified embodiment, and referring toFIG.12together withFIGS.2to4B, the gate separation region40may be a gate separation region40hincluding a lower buffer layer150, a gap fill layer152on the lower buffer layer150, and a buffer liner146′ between the buffer layer150and the gap fill layer152and between side surfaces of the gap fill layer152and the second spacer portions18b. The lower buffer layer150and the buffer liner146′ may constitute a buffer structure. In an implementation, the gate separation region40hmay further include a lower insulation layer12abetween the lower buffer layer150and the isolation region6. Various modified examples of the gate separation region40described above with reference toFIGS.2to4Bwill be described with reference toFIGS.13,14and15, respectively.FIGS.13,14and15illustrate cross-sectional views of regions indicated by lines inFIG.2, respectively. In another modified embodiment, and referring toFIGS.13,14and15, respectively, together withFIGS.2to4B, between the second spacer portions18bof the spacers18, the gate separation region40may be a gate separation region (40iinFIG.13,40jinFIG.14,40kinFIG.15) which may be between the second spacer portions18b, may extend into the isolation region6, and may have a lower portion having a width that is greater than a width of an upper portion. In another modified embodiment, referring toFIG.13, the gate separation region40imay include a lower buffer layer150and a gap fill layer152that are stacked in sequence. The lower buffer layer150may constitute a buffer structure. The gate separation region40imay include a lower region, and an upper region on the lower region. The lower region may have a width that is greater than a width of the upper region. The buffer structure, i.e., the lower buffer layer150, may be on the upper surface of the gate separation region40i. The gap fill layer152may be in the upper region of the gate separation region40i. The lower buffer layer150may be formed of a material having a good gap fill property, e.g., a flowable oxide, and the gate separation region40imay be formed without a defect such as a seam or the like. In another modified embodiment, referring toFIG.14, the gate separation region40jmay include the lower buffer layer150and the gap fill layer152, stacked in sequence, and a buffer liner146′ covering bottom and side surfaces of the lower buffer layer150and covering side surface of the gap fill layer152. The lower buffer layer150and the buffer liner146′ may constitute a buffer structure. In another modified embodiment, referring toFIG.15, the gate separation region40kmay include a lower buffer layer150and a gap fill layer152, stacked in sequence, and a buffer liner146′ covering side surfaces of the gap fill layer152and between the gap fill layer152and the lower buffer layer150. The lower buffer layer150and the buffer liner146′ may constitute a buffer structure. Various modified examples of the gate separation region40, described above with reference toFIGS.2to4B, will be described with reference toFIGS.16,17and18, respectively.FIGS.16,17and18illustrate cross-sectional views of regions indicated by line IVa-IVa′ inFIG.2, respectively. In another modified embodiment, and referring toFIGS.16,17and18, respectively, together withFIGS.2to4B, between the first and second end portions63e1and63e2facing each other in the first and second gate line structures63aand63b, the gate separation region40may be a gate separation region (401inFIG.16,40minFIG.17,40ninFIG.18) which may be between the first and second end portions63e1and63e2, may extend into the isolation region6, and may have a lower portion having a width that is greater than a width of an upper portion. In another modified embodiment, referring toFIG.16, the gate separation region401may include a buffer structure including a lower buffer layer150, and a gap fill layer152stacked on the buffer structure. In another modified embodiment, referring toFIG.17, the gate separation region40mmay include the lower buffer layer150and the gap fill layer152, stacked in sequence, and a buffer liner146covering bottom and side surfaces of the lower buffer layer150and covering side surface of the gap fill layer152. The lower buffer layer150and the buffer liner146may constitute a buffer structure. In another modified embodiment, referring toFIG.18, the gate separation region40nmay include the lower buffer layer150and the gap fill layer152, stacked in sequence, and a buffer liner146′ between the gap fill layer152and the lower buffer layer150and covering side surface of the gap fill layer152. The lower buffer layer150and the buffer liner146′ may constitute a buffer structure. Next, a modified embodiment of the gate separation region40and the spacers18described above will be described with reference toFIG.19.FIG.19illustrates a plan view of an example of a first circuit region C1of a semiconductor device (1inFIG.1) according to an embodiment including another modified embodiment of the gate separation region40described above. Modified examples of the above-described gate separation region40and the above-described spacers18will be mainly described. Components other than the gate separation region40and the spacers18will be substantially the same as those described with reference toFIGS.2to4B. Therefore, some components may be omitted from the following description, and some components will be directly quoted. Referring toFIG.19, active regions9aand9band first and second gate line structures63aand63b, the same as those described with reference toFIGS.2to4B, may be provided. Gate separation regions240may be between the first and second gate line structures63aand63b. Spacers18′ may also cover portions of side surfaces of each of the gate separation regions240, and may cover side surfaces of the first and second gate line structures63aand63b. Extension portions253may extend in a first direction X from at least a portion of the gate separation regions240. The first direction X may be a longitudinal direction of first and second upper active regions9a_2and9b_2, and a width direction of the first and second gate line structures63aand63b, as described with reference toFIGS.2to4B. Various examples of the gate separation regions240and the spacers18′ will be described with reference toFIGS.20A and20B.FIG.20Aillustrates a cross-sectional view of regions taken along line IIIb-IIIb′ and line IVb-IVb′ inFIG.19, andFIG.20Billustrates a cross-sectional view of a region taken along line IV-IV′ inFIG.19. Referring to20A and20B together withFIG.19, the gate separation regions240may be gate separation regions240abetween first end portions63e1of the first gate line structures63aand second end portions63e2of the second gate line structures63b, and including extension portions253connected to each other. Each of the gate separation regions240amay include a gap fill layer252, a buffer liner246covering bottom and side surfaces of the gap fill layer252and extending onto a lower surface of the extension portions253, and a lower insulation layer12abetween the buffer liner246and the isolation region6. The extension portions253may extend from an upper region of the gap fill layers252in a first direction X, e.g., in a width direction of the first and second gate line structures63aand63bto form the gap fill layers252integrally. The buffer liner246may be a buffer structure. The spacers18′ may include first spacer portions18a′covering side surfaces of the first and second gate line structures63aand63b, and second spacer portions18b′extending from the first spacer portions18a′, connecting to the first spacer portions18a′. Each of the second spacer portions18b′may have a thickness that is less than that of each of the first spacer portions18a′. The upper surfaces of the second spacer portions18b′may be located on a level lower than (e.g., closer to the semiconductor substrate3than) that of the upper surfaces of the first spacer portions18a′. Interlayer insulating layers27may be on a second isolation region6bof an isolation region6. On the second isolation region6b, the spacers18may be between the gate line structures63aand63band the interlayer insulating layers27, and between the gate separation regions240and the interlayer insulating layers27. The extension portions253may extend from the upper region of the gap fill layers252in the first direction X, and may cover the second spacer portions18band the interlayer insulating layers27. Thus, the extension portions253may overlap the second spacer portions18b′and the interlayer insulating layers27. Various modified examples of the gate separation regions240will be described with reference toFIGS.21,22, and23, respectively.FIGS.21,22and23illustrate cross-sectional views of regions taken along line IIIb-IIIb′ and line IVb-IVb′ inFIG.19. Referring to each ofFIGS.21,22and23together withFIG.19, the gate separation regions240may be gate separation regions (240binFIG.21,240cinFIG.22,240dinFIG.23) which may include a lower buffer layer250and a gap fill layer252′, stacked in sequence, and extension portions253connected to an upper region of the gap fill layer252′ and extending in the first direction X. In a modified embodiment, referring toFIG.21, each of the gate separation regions240bmay further include a lower insulation layer12abetween the lower buffer layer250and the isolation region6. The lower buffer layer250may be a buffer structure. In a modified embodiment, referring toFIG.22, each of the gate separation regions240cmay further include a buffer liner246covering lower and side surfaces of the lower buffer layer250, covering side surfaces of the gap fill layer252′ and extending to lower surfaces of the extension portions253. Each of the gate separation regions240cmay further include a lower insulation layer12abetween the buffer liner246and the isolation region6. The buffer liner246and the lower buffer layer250may constitute a buffer structure. In a modified embodiment, referring toFIG.23, each of the gate separation regions240dmay further include a buffer liner246between a lower surface of the gap fill layer252′ and the lower buffer layer250, covering side surfaces of the gap fill layer252′, and extending onto lower surfaces of the extension portions253. The lower buffer layer250and the buffer liner246may constitute a buffer structure. Each of the gate separation regions240dmay further include a lower insulation layer12abetween the lower buffer layer250and the isolation region6. Various modified examples of the gate separation regions240will be described with reference toFIGS.24,25,26, and27, respectively.FIGS.24,25,26, and27illustrate cross-sectional views of a region taken along line IIIb-IIIb′ inFIG.19, respectively. Referring toFIGS.24,25,26and27, respectively, together withFIG.19, between the second spacer portions18bof the spacers18, the gate separation regions240may be gate separation regions (240ein FIG.,240finFIG.25,240ginFIG.26,240hinFIG.27) which may be between the second spacer portions18b, may extend into the isolation region6, and may have a lower portion having a width broader than a width of an upper portion. In a modified embodiment, referring toFIG.24, each of the gate separation regions240emay include a gap fill layer252, extension portions253connected to an upper region of the gap fill layer252, and a buffer liner246covering bottom and side surfaces of the gap fill layer252and extending between the extension portions253and interlayer insulating layers27. The buffer liner246may be a buffer structure. In a modified embodiment, referring toFIG.25, each of the gate separation regions240fmay include a lower buffer layer250and a gap fill layer252′, stacked in sequence, and extension portions253connected to an upper region of the gap fill layer252′ and extending in the first direction X. The lower buffer layer250may be a buffer structure. In a modified embodiment, referring toFIG.26, each of the gate separation regions240gmay include a lower buffer layer250and a gap fill layer252′, stacked in sequence, and a buffer liner246covering lower and side surfaces of the lower buffer layer250, covering side surfaces of the gap fill layer252′ and extending onto lower surfaces of extension portions253. The lower buffer layer250and the buffer liner246may constitute a buffer structure. In a modified embodiment, referring toFIG.27, each of the gate separation regions240hmay include a lower buffer layer250and a gap fill layer252′, stacked in sequence, and a buffer liner246′ between a lower surface of the gap fill layer252′ and the lower buffer layers250, covering side surfaces of the gap fill layer252′ and extending onto lower surfaces of extension portions253. The lower buffer layer250and the buffer liner246′ may constitute a buffer structure. Among the components described with reference toFIGS.1to27, the ‘buffer liner’ referred to by the same reference numeral or various reference numerals may be formed of the same material as each other. The ‘gap fill layer’ referred to by the same reference numeral or various reference numerals may be formed of the same material as each other. The ‘lower buffer layer’ referred to by the same reference numeral or various reference numerals may be formed of the same material as each other. For example, the buffer liner46described with reference toFIG.5, the buffer liner146described with reference toFIG.11, the buffer liner146′ described with reference toFIG.12, the buffer liner246described with reference toFIG.20A, and the buffer liner246described with reference toFIG.20Bmay be formed of the same material. The gap fill layer52described with reference toFIG.5, the gap fill layer152described with reference toFIG.11, and the gap fill layer252described with reference toFIG.20Amay be formed of the same material as each other. Next, a modified embodiment of the active regions9aand9bdescribed above with reference toFIG.2toFIG.27will be described with reference toFIG.28. In a modified embodiment, referring toFIG.28, the gate separation regions40and240may be provided between the first and second gate line structures63aand63b, and between the end portions63e1and63e2facing each other in the first and second gate line structures63aand63b, the same as described above with reference toFIGS.2to27. The first active region9a′may include a first lower active region9a_1, first upper active regions9a_2protruding in the vertical direction Z from the first lower active region9a_1, and first floating active regions9a_3on an upper portion of the first upper active regions9a_2and spaced apart from the first upper active regions9a_2. The second active region9b′may include a second lower active region9b_1, second upper active regions9b_2protruding in the vertical direction Z from the second lower active region9b_1, and second floating active regions9b_3on an upper portion of the active regions9b_2and spaced apart from the second upper active regions9b_2. The first floating active regions9a_3may be surrounded by the first gate line structure63a, and the second floating active regions9b_3may be surrounded by the second gate line structure63b. Next, referring toFIG.29, modified examples of the first and second gate line structures63aand63bwill be described with reference toFIGS.2to27. In a modified embodiment, referring toFIG.29, each of the first gate line structures63a′may include a first gate electrode line69a, and a first gate dielectric66acovering a lower surface of the first gate electrode line69aand covering side surfaces of the first gate electrode line69a. Each of the second gate line structures63b′may include a second gate electrode line69b, and a second gate dielectric66bcovering a lower surface of the second gate electrode line69band covering side surfaces of the second gate electrode line69b. Thus, in a modified embodiment, the upper surfaces of the first and second gate electrode lines69aand69bmay be coplanar with the upper surfaces of the gate separation regions40and240described above with reference toFIGS.1to27. As described above with reference toFIGS.1to29, the semiconductor device1according to an embodiment may include the first circuit region C1described above. In an implementation, the semiconductor device1may include other circuit regions together with the first circuit region C1described above. An exemplary example of the semiconductor device1including a second circuit region C2together with the first circuit region C1described above, with reference toFIGS.30and31, and an exemplary example of the semiconductor device1including a third circuit region C3together with the first circuit region C1described above, with reference toFIGS.32and33, will now be described. Hereinafter, the semiconductor device1, an exemplary example to be described with reference toFIGS.30and31, andFIGS.32and33, may include the second circuit region (C2inFIG.30) or the third circuit region (C3inFIG.32) together with the first circuit region C1described above with reference toFIGS.1to29. In this case, the description of the first circuit region C1, e.g., components constituting the first circuit region C1, and various modified examples thereof, described with reference toFIGS.1to29, may be omitted. Among the components constituting the first circuit region C1described with reference toFIGS.1to29, the components to be applied to the second circuit region (C2inFIG.30) or the third circuit region (C3inFIG.32) in the same manner may be omitted, or these components may be directly quoted, but the detailed description of the components may be omitted. First, referring toFIGS.30and31, an exemplary example of the semiconductor device1including the second circuit region C2together with the first circuit region C1described above with reference toFIGS.1to29will be described.FIG.30illustrates a perspective view of a semiconductor device1according to an embodiment, and a plan view of an enlarged portion of the perspective view.FIG.31illustrates a cross-sectional view of regions taken along line VI-VI′ and line VII-VII′ inFIG.30, respectively. Referring toFIGS.30and31together withFIGS.1to29, the semiconductor device1according to an embodiment may include the second circuit region C2together with the first circuit region C1described with reference toFIGS.1to29. The second circuit region C2may include third active regions109corresponding to the first and second active regions9aand9bof the first circuit region C1. Therefore, among the third active regions109adjacent to each other, one of the third active regions109may have the same structure as the first active region9a, and the other one of the third active regions109may have the same structure as the second active region9b. For example, each of the third active regions109may include a third lower active region109_1having the same structure as the first lower active region9a_1, and third upper active regions109_2having the same structure as the first upper active regions9a_2. In an implementation, the third active regions109may be defined by the isolation region6including the first and second isolation regions6aand6b, in the same manner as the first and second active regions9aand9b. The second circuit region C2may include third source/drain regions124that may correspond to the first and second source/drain regions24aand24bof the first circuit region C1. The second circuit region C2may include third gate line structures163that may correspond to the first and second gate line structures63aand63bof the first circuit region C1. For example, each of the third gate line structures163may include a third gate dielectric166covering the third gate electrode line169and a lower surface of the third gate electrode line169and covering side surfaces of the third gate electrode line169. In an implementation, each of the third gate line structures163may include a third capping line172covering an upper surface of the third gate electrode line169and an upper end portion of the third gate dielectric166. The third capping line172may be formed of the same material as the first and second capping lines72aand72b. The second circuit region C2may include a gate separation region340between end portions163efacing each other in the third gate line structures163on the second isolation region6b. To clearly distinguish between the components, the gate separation regions40and240in the first circuit region C1will be referred to as first gate separation regions40and240, and the gate separation region340in the second circuit region C2will be referred to as a second gate separation region340. The second circuit region C2may include spacers18corresponding to the spacers18of the first circuit region C1. Thus, the spacers18may include first spacer portions18acovering side surfaces of the third gate line structures163, and second spacer portions18bcovering side surfaces of the second gate separation region340, in the same manner as in the first circuit region C1. The second gate separation region340may have a different structure from the first gate separation regions40and240. For example, the second gate separation region340may be formed of a gap fill layer352filling between the end portions163efacing each other in the third gate line structures163, and between the second spacer portions18b. The second gate separation region340may further include a lower insulation layer12abetween the gap fill layer352and the second isolation region6b. The gap fill layer352may be formed of silicon nitride, and the lower insulation layer12amay be formed of silicon oxide. In an implementation, when the transistors formed in the first circuit region C1are PMOS transistors and the transistors formed in the second circuit region C2are NMOS transistors, the first gate separation regions40and240and the second gate separation region340may commonly include a gap fill layer formed of an insulating material having a dielectric constant of about 5 or greater, and the first gate separation regions40and240may further include a buffer structure, for example, the buffer liner46described prior to that of the second gate separation region340. The buffer liner46may be formed of an insulating material having a dielectric constant of about 4 to 5, as described above. Next, referring toFIGS.32and33, an exemplary example of the semiconductor device1including the third circuit region C3, together with the first circuit region C1described above with reference toFIGS.1to29, may be described.FIG.32illustrates a plan view and a portion of a perspective view of the semiconductor device1according to an embodiment.FIG.33illustrates a cross-sectional view of regions taken along line VIII-VIII′ and line IX-IX′ inFIG.32, respectively. Referring toFIGS.32and33together withFIGS.1to29, a semiconductor device1according to an embodiment may include a third circuit region C3together with the first circuit region C1described above with reference toFIGS.1to29. In this case, the description in which an exemplary example of the first circuit region C1is described with reference toFIGS.6and8will be directly quoted and described. The third circuit region C3may include fourth active regions209. Each of the fourth active regions209may include a fourth lower active region209_1, and fourth upper active regions209_2protruding in an upward direction Z from the fourth lower active region209_1. The fourth active regions209may be defined by the isolation region6in the same manner as the first and second active regions9aand9bof the first circuit region C1. The second isolation region6bof the isolation region6may be between the fourth lower active regions209_1, and the first isolation region6aof the isolation region6may be on the fourth lower active regions209_1. In this case, the fourth upper active regions209_2may extend in the upward direction Z from the first lower active regions209_1, and may pass through the first isolation region6a. The third circuit region C3may include fourth source/drain regions424that may correspond to the first and second source/drain regions24aand24bof the first circuit region C1. The third circuit region C3may include a fourth gate line structures463having end portions463efacing each other on the second isolation region6bof the isolation region6between the fourth active regions209. Each of the fourth gate line structures463may include a fourth gate electrode line469, and a fourth gate dielectric466covering a lower surface of the fourth gate electrode line469and covering side surfaces of the fourth gate electrode line469. In an implementation, each of the fourth gate line structures463may include a fourth capping line472covering the upper surface of the fourth gate electrode line469and the upper end portions of the fourth gate dielectric466. The fourth capping line472may be formed of the same material as the first and second capping lines72aand72b. The third circuit region C3may include a gate separation region440between end portions463efacing each other in the fourth gate line structures463on the second isolation region6b. The gate separation regions40and240in the first circuit region C1will be referred to as first gate separation regions40and240, and the gate separation region440in the third circuit region C3will be referred to as a third gate separation region440. The third circuit region C3may include spacers18corresponding to the spacers18and18′ of the first circuit region C1. Thus, the spacers18may include first spacer portions18acovering the side surfaces of the fourth gate line structures463, and second spacer portions18bcovering the side surfaces of the second gate separation region340, as in the first circuit region C1. The third gate separation region440may be substantially the same as the first gate separation regions40and240, except for the size. For example, the third gate separation region440may have a lower surface located on a level lower than the lower surface of the first gate separation regions40and240. The third gate separation region440may have a width that is greater or a planar size (e.g., area) that is larger than the first gate separation regions40and240. For example, among the various examples of the first gate separation regions40and240of the first circuit region C1described with reference toFIGS.1to29, in a case that the first gate separation regions40and240are the first gate separation region (40binFIG.6and/or40dinFIG.8) described with reference toFIGS.6and8, the third gate separation region440may include a buffer liner446that may correspond to the buffer liner46in the first gate separation region (40binFIG.6and/or40dinFIG.8), and a gap fill layer452that may correspond to the gap fill layer52in the first gate separation region (40binFIG.6and/or40dinFIG.8). A thickness of the buffer liner446portion of the third gate separation region440between the gap fill layer452and the isolation region6in the third circuit region C3may be thicker than a thickness of a portion of the buffer liner46of the first gate separation region (40binFIG.6and/or40dinFIG.8) between the gap fill layer52and the isolation region6of the first gate separation region (40binFIG.6and/or40dinFIG.8) in the first circuit region C1. Throughout the specification, terms such as “first,” “second,” “third,” and “fourth,” and the like may be used to describe various components. The terms may be used only for the purpose of distinguishing one component from another component(s). For example, a “third component” may be referred to as a “second component,” and a “second component” may be referred to as a “third component” without departing from the scope of the present inventive concept. For example, the third circuit region C3may be referred to as a second circuit region C2, and the second circuit region C2may be referred to as a third circuit region C3. Next, an exemplary example of a method of forming a semiconductor device according to an embodiment will be described. Hereinafter, various examples of a method of forming a semiconductor device according to an embodiment will be described with reference toFIGS.2and34to37B.FIG.34illustrates a process flow chart of an exemplary method of forming a semiconductor device according to an embodiment, andFIGS.35A to37Billustrate cross-sectional views of stages in a method of forming a semiconductor device according to an embodiment. InFIGS.35A to37B,FIGS.35A,36A and37Aare cross-sectional views illustrating a region taken along line I-I′ inFIG.2, andFIGS.35B,36B and37Bare cross-sectional views illustrating a region taken along line IIIa-IIIa′ inFIG.2. Referring toFIGS.2,34,35A and35B, active regions9aand9band an isolation region6may be formed (S10). The active regions9aand9band the isolation region6may be formed on the semiconductor substrate3. The formation of the isolation region6may include, e.g., forming a first isolation region6adefining active lines having a line shape on the semiconductor substrate3; forming a second isolation region6bpassing through the first isolation region6aand the active lines and extending into the semiconductor substrate3; and partially etching the first and second isolation regions6aand6bto expose upper regions of remaining active lines. By forming the second isolation region6b, a first lower active region9a_1and a second lower active region9b_1below the remaining active lines may be formed. Active lines remaining on the first lower active region9a_1may be defined as first upper active regions9a_2, and active lines remaining on the second lower active region9b_1may be defined as second upper active regions9b_2. The first lower active region9a_1and the first upper active regions9a_2may constitute a first active region9a, and the second lower active region9b_1and the second upper active region9b_2may constitute a second active region9b. Therefore, the active regions9aand9bmay include the first and second active regions9aand9b. Preliminary gate lines15may be formed on the active regions9aand9band the isolation region6(S20). Before forming the preliminary gate lines15, a lower base layer12may be formed. The formation of the lower base layer12and the preliminary gate lines15may include forming an insulation layer and a preliminary gate on a semiconductor substrate3on which the active regions9aand9band the isolation region6are formed, and patterning the insulation layer and the preliminary gate layer in the form of a line shape. Thus, the insulation layer may be patterned to be formed as the lower base layer12, and the preliminary gate layer may be patterned to be formed as the preliminary gate lines15. Spacers18may be formed on the side surfaces of the preliminary gate lines15(S30). The spacers18may be formed of any one of SiN, SiON, and SiCN, or a combination thereof. Source/drain regions (24ainFIG.4A and24binFIG.4B) may be formed on the active regions9aand9b. For example, the formation of the source/drain regions (24ainFIG.4A and24binFIG.4B) may include performing an etching process using the preliminary gate lines15and the spacers18as an etch mask, etching the active regions9aand9bto form recess regions (21ainFIG.4A and21binFIG.4B), and performing an epitaxial process to form epitaxial layers filling the recess regions (21ainFIG.4A and21binFIG.4B). Referring toFIGS.2,34,36A and36B, interlayer insulating layers27filling between the preliminary gate lines15may be formed. The interlayer insulating layers27may be formed of silicon oxide. A mask pattern30may be formed on the preliminary gate lines15and the interlayer insulating layers27, and an etching process using the mask pattern30as an etch mask may be performed to form an opening33for separating the preliminary gate lines15on the isolation region6. When the preliminary gate lines15to be separated are present in plural, the opening33may be formed in plural. In an implementation, the opening33may expose the lower insulation layer12. In an implementation, the openings33may pass through the lower insulation layer12and extend into the second isolation region6bof the isolation region6. Referring toFIGS.2,34,37A and37B, in an exemplary example, while the opening33is formed, a thickness of the spacers18adjacent to the opening33may be reduced. A gate separation region40for separating the preliminary gate lines15on the isolation region6may be formed (S50). For example, the preliminary gate lines15may be etched by a patterning process to form the opening (33inFIGS.36A and36B) between the preliminary gate lines15, and a buffer liner46covering an inner wall of the opening (33inFIGS.36A and36B) may be formed, and a gap fill layer52filling the opening (33inFIGS.36A and36B) may be formed. In an implementation, the gate separation region40may include a lower insulation layer12aremaining below the buffer liner46, together with the gap fill layer52and the buffer liner46. The exemplary method of forming the gate separation region40described above may be applied to a method of forming the gate separation regions240,340, and440of various shapes or structures described above. Referring again toFIGS.4A,4B and5, together withFIGS.2and34, the preliminary gate lines (15inFIGS.37A and37B) may be substituted with gate line structures63aand63b(S60). For example, substituting the preliminary gate lines (15inFIGS.37A and37B) with the gate line structures63aand63bmay include removing the preliminary gate lines (15ofFIGS.37A and37B) to form gate trenches, forming a gate dielectric covering an inner wall of the gate trenches, forming gate electrode lines for filling the gate trenches on the gate dielectric, partially etching the gate electrode lines and the gate dielectric, and forming a capping line for filling remaining portions of the gate trenches. Thus, the gate line structures63aand63bas illustrated inFIGS.4A and4Bmay be formed. The gate line structures63aand63bmay include first and second gate line structures63aand63bhaving end portions63e1and63e2facing each other. Then, contact structures78aand78bmay be formed (S70). For example, the contact structures78aand78bmay be formed on the first and second source/drain regions24aand24b. The contact structures78aand78bmay be formed of any one of doped silicon, metal-silicide, metal nitride, and metal, or combination thereof. In an implementation, the gate separation regions40,240,340, and440described above may apply tensile stress to the channel region of the transistor in the longitudinal direction of the gate line structure. For example, the performance of the transistor adjacent to the gate separation regions40,240,340, and440described above may be improved. In an implementation, the gate separation regions40,240,340, and440described above may be formed without defects such as seams or the like. For example, the defects may be reduced, and the productivity of the semiconductor device may be improved. According to embodiments, a semiconductor device including a gate separation region formed between gate line structures may be provided. The gate separation region may include a buffer structure including a material having a dielectric constant higher than that of silicon oxide and lower than that of silicon nitride. In an implementation, such a gate separation region may provide tensile stress on a channel region of a transistor in a longitudinal direction of the gate line structure, thereby improving performance of the transistor. For example, a semiconductor device including a transistor with improved performance may be provided. The embodiments may provide a semiconductor device including a gate separation region separating gate line structures. The embodiments may provide a semiconductor device including a gate separation region, in which performance of a transistor may be improved. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 62,945 |
11942478 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments of the present disclosure relate to gate all around (GAA) transistors, such as nanostructure FETs, which has a stack of semiconductor layers including first and second semiconductor layers alternatingly formed over a substrate. The first semiconductor layers form nanostructure channel(s) of the transistors. Portions of the second semiconductor layers are removed so that the nanostructure channels (e.g., first semiconductor layers) are wrapped around by a gate electrode. According to embodiments of the present disclosure, one or more nanostructure channels are attached to two opposing sides of a dielectric feature to form a fork-like nanostructure transistor, such as a forksheet transistor. A portion of a high-k dielectric layer disposed around the dielectric feature located in the source/drain regions are removed and replaced with a dielectric material having different etch selectivity compared to the high-k dielectric layer. As a result, gate to source/drain bridging is avoided. Furthermore, the high-k dielectric layer is replaced with a dielectric material having a lower k value, thus, device capacitance may be reduced. While the embodiments of this disclosure are discussed with respect to nanostructure channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In cases where gate all around (GAA) transistor structures are adapted, the GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. FIGS.1-22Bshow exemplary sequential processes for manufacturing a semiconductor device structure100, in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-22B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. As shown inFIG.1, a stack of semiconductor layers104is formed over a substrate101. The substrate101may be a semiconductor substrate. As shown inFIG.1, a semiconductor device structure100includes the stack of semiconductor layers104formed over a front side of the substrate101. The substrate101may include a single crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In this embodiment, the substrate101is made of Si. In some embodiments, the substrate101is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide. The substrate101may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurity). Depending on circuit design, the dopants may be, for example boron for a p-type field effect transistor (FET) and phosphorus for an n-type FET. The stack of semiconductor layers104includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate device, such as nanosheet channel FETs or forksheet FETs. In some embodiments, the stack of semiconductor layers104includes first semiconductor layers106(106a,106b) and second semiconductor layers108(108a,108b). In some embodiments, the stack of semiconductor layers104includes alternating first and second semiconductor layers106,108. The first semiconductor layers106are aligned with the second semiconductor layers108. The first semiconductor layers106and the second semiconductor layers108are made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layers106may be made of Si and the second semiconductor layers108may be made of SiGe. In some examples, the first semiconductor layers106may be made of SiGe and the second semiconductor layers108may be made of Si. In some cases, the SiGe in the first or second semiconductor layers106,108can have a germanium composition percentage between about 10% and about 80%. Alternatively, in some embodiments, either of the semiconductor layers106,108may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combinations thereof. The first semiconductor layers106or portions thereof may form nanostructure channel(s) of the semiconductor device structure100in later fabrication stages. The term nanostructure is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having any suitable shape, such as an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including, for example, a cylindrical in shape or substantially rectangular cross-section. The nanostructure channel(s) of the semiconductor device structure100may be surrounded by a gate electrode. For example, at least three surfaces of the nanostructure channel(s) may be surrounded by the gate electrode, and the transistor is a forksheet transistor. The nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, forksheet transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode surrounding the channels. It is noted that while two layers of the first semiconductor layers106and two layers of the second semiconductor layers108are alternately arranged as illustrated inFIG.1, it is for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of first and second semiconductor layers106,108can be formed in the stack of semiconductor layers104; the number of layers depending on the predetermined number of channels for the semiconductor device structure100. In some embodiments, the number of first semiconductor layers106, which is the number of channels, is between 3 and 8. The first and second semiconductor layers106,108are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layers104may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. The substrate101may include a sacrificial layer107on the stack of semiconductor layers104. The sacrificial layer107protects the stack of semiconductor layers104during the subsequent processes and is removed along with a portion of a cladding layer (FIG.11) prior to the formation of the sacrificial gate stack (FIG.12A). In cases where the first semiconductor layer106of the stack of semiconductor layers104is Si, the sacrificial layer107includes SiGe epitaxially grown on the first semiconductor layer106. A mask structure110is formed over the sacrificial layer107. The mask structure110may be a multilayer structure. In some embodiments, the mask structure110includes an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer may be a pad oxide layer, such as a SiO2layer. The nitrogen-containing layer may be a pad nitride layer, such as Si3N4. The mask structure110may be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process. FIG.2is a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.2, fins112(112a-112c) are formed from the stack of semiconductor layers104and the substrate101. Each fin112has an upper portion including the stack of semiconductor layers104and a substrate portion116formed from the substrate101. The fins112may be fabricated using multi-patterning operations including photo-lithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. The photo-lithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing post-exposure bake processes, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches114(e.g.,114a,114b) in unprotected regions through the mask structure110, through the stack of semiconductor layers104, and into the substrate101, thereby leaving the plurality of extending fins112(e.g.,112a,112b,112c). As shown inFIG.2, the trenches114aand114bare formed with different widths between the fins112a,112b,112c. The trench114ais formed between the fin112aand the fin112band has a width WO1. The trench114bis formed between the fin112band the fin112cand has a width W02. The width W02may be equal, less, or greater than the width WO1. In the embodiment shown inFIG.2, the width WO1 is greater than the width W02. As described above, the first semiconductor layers106may serve as channels in a forksheet transistor device, and the channels formed from the fins112b,112cmay extend from a dielectric feature formed in the trench114b. FIG.3is a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.3, after the fins112are formed, an insulating material118is formed on the substrate101. The insulating material118fills the trenches114(FIG.2) between neighboring fins112until the fins112are embedded in the insulating material118. Then, a planarization process, such as a chemical mechanical polishing (CMP) process and/or an etch-back process, is performed such that the top of the fins112is exposed. The insulating material118may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material118may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD). FIG.4is a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments. As shown inFIG.4, the insulating material118is recessed to form an isolation region120. The recess of the insulating material118exposes portions of the fins112, such as the stack of semiconductor layers104. A top surface of the insulating material118may be level with or slightly below a surface of the second semiconductor layer108bin contact with the substrate portion116. Thereafter, the mask structures110is removed by any suitable process, such as an etch process. FIGS.5-11are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along cross-section A-A ofFIG.4, in accordance with some embodiments. As shown inFIG.5, the semiconductor device structure100has three fins112a,112b, and112cformed along the Y direction. As discussed above, the distances between adjacent fins112a,112b, and112cmay vary. With the smaller width W02of the trench114b(i.e., reduced fin-to-fin spacing) between the fins112band112c, layers of a first dielectric feature130(FIG.7) subsequently formed my fill the trench114b(FIG.6). The first dielectric feature130allows the nanostructure channels to extend from opposite sides of the first dielectric feature130and to form a forksheet transistor at a later stage. The reduced fin-to-fin spacing and fork-like nanostructure transistors enable greater device density (even with greater channel width) and superior area and performance scalability. As shown inFIG.6, a first dielectric layer126is formed on the exposed surfaces of the semiconductor device structure100and in the trenches114a,114b(FIG.5),114c,114d. The first dielectric layer126may include a high-k material having a k value greater than that of silicon dioxide. In some embodiments, the high-k material has a k value greater than 7. Exemplary materials may include, but are not limited to, metal oxides, such as HfO2, ZrO2, TiO2, Al2O3, La2O3, Y2O3, ScO2, or alloy metal oxide, such as HfAlOx, HfSiOx, HfZrOx, ZrAlOx, ZrSiOx, where x may be integers or non-integers. The first dielectric layer126may be formed by a conformal process, such as an ALD process. The first dielectric layer126may be formed on the exposed surface of the insulating material118at the bottom of the trenches114a,114b,114c,114dand on the exposed portions of the fins112a,112b,112c(e.g., first and second semiconductor layers106,108and the sacrificial layer107). The first dielectric layer126may have substantially the same thickness ranging from about 2 nm to about 7 nm. Next, a second dielectric layer128is formed on the first dielectric layer126in the trench114a,114b(FIG.5),114c,114d, and over the fins112a,112b,112c. The second dielectric layer128fills the trench114bdue to the small width W02but not the trench114a. The second dielectric layer128may include a low-k dielectric material (e.g., a material having a k value lower than that of silicon dioxide), such as SiOCH or porous SiO2. In some embodiments, the second dielectric layer128is a silicon-containing dielectric material having a k vale less than 7, such as SiO2, SiCN, SiOC, or SiOCN. The second dielectric layer128may be formed by a conformal process, such as an ALD process. The second dielectric layer128may have a thickness ranging from about 5 nm to about 30 nm. If the thickness of the second dielectric layer128is less than about 5 nm, the trench114bmay not be filled. On the other hand, if the thickness of the second dielectric layer128is greater than about 30 nm, the manufacturing cost is increased without significant advantage. Next, as shown inFIG.7, the first dielectric layer126and the second dielectric layer128are recessed. The recess of the first dielectric layer126and the second dielectric layer128may be performed by any suitable removal process, such as dry etch, wet, etch, or a combination thereof. The removal process may be selective etch processes that remove the first dielectric layer126and the second dielectric layer128but not the sacrificial layers107, the first semiconductor layers106, the second semiconductor layers108, and the insulating material118. Because the trenches114a,114c,114dare not completely filled and have a larger dimension (i.e., width W01) in the Y direction compared to that of the trench114b(FIG.5), the etchant removes more of the first dielectric layer126and the second dielectric layer128in the trenches114a,114c,114dthan the first dielectric layer126and the second dielectric layer128in the trench114b(FIG.5). As a result, the first dielectric layer126and the second dielectric layer128in the trenches114a,114c,114dare etched at a faster rate than the etch rate of the first dielectric layer126and the second dielectric layer128in the trench114b. In cases where the first dielectric layer126and the second dielectric layer128include different materials, a first etch process may be performed to recess the second dielectric layer128followed by a second etch process to recess the first dielectric layer126. The removal process is performed until the first dielectric layer126and the second dielectric layer128in the trenches114a,114c,114dare completely etched away. The removal process also removes the first dielectric layer126and the second dielectric layer128on exposed surfaces of the fins112a,112b,112cand the insulating material118. As a result of the removal process, the first dielectric layer126and the second dielectric layer128on exposed surfaces of the semiconductor device structure100are removed except for the first dielectric layer126and the second dielectric layer128filled in the trench114b(FIG.5). The first dielectric layer126and the second dielectric layer128in the trench114bmay be referred to herein as a first dielectric feature130. The sidewalls127(127a,127b) and the bottom129of the second dielectric layer128are in contact with the first dielectric layer126. The sidewall127ais opposite of the sidewall127b, and the bottom129connects the sidewall127ato sidewall127b. The first dielectric layer126is formed with a first thickness T1corresponding to the thickness of the first dielectric layer126discussed above, and the second dielectric layer128is formed with a second thickness T2greater than the first thickness T1. Next, as shown inFIG.8, a cladding layer132is formed on the exposed surfaces of the stack of semiconductor layers104, the dielectric feature130(e.g., top surfaces of the first dielectric layer126and a top surface of the second dielectric layer128), and the insulating material118. The cladding layer132may be formed by a conformal process, such as an ALD process. The cladding layer132may have substantially the same thickness ranging from about 1 nm to about 10 nm. The thickness of the cladding layer132formed on the sidewalls of the fins112a,112b,112cmay define the space for a second dielectric feature134(FIG.10) and a gate electrode layer182(FIG.22A) to be formed after subsequent removal of the cladding layers132. Thus, if the thickness of the cladding layer132is more than about 10 nm, the trenches114a,114c,114dmay be filled, resulting in the second dielectric feature134not able to form in the trenches114a,114c,114d. In some embodiments, the cladding layer132includes a semiconductor material. In some embodiments, the cladding layer132and the second semiconductor layers108are made of the same material having the same etch selectivity. For example, the cladding layer132and the second semiconductor layers108include SiGe. The cladding layer132and the second semiconductor layer108may be removed subsequently to create space for the gate electrode layer. Next, as shown inFIG.9, portions of the cladding layer132are removed. The removal of the cladding layer132may be performed by any suitable removal process, such as dry etch, wet, etch, or a combination thereof. The removal process may be an anisotropic etch process to remove the cladding layer132formed on horizontal surfaces of the fins112a,112b,112c(e.g., top surfaces of the sacrificial layer107, the first dielectric layer126and the second dielectric layer128) and on the insulating material118. The removal process does not remove the cladding layer132formed on vertical surfaces of the fins112a,112b,112c. Next, as shown inFIG.10, a second dielectric feature134is formed in the trenches114a,114c,114d(FIG.9). The second dielectric feature134includes a third dielectric layer136and a fourth dielectric layer138formed on the third dielectric layer136. The third dielectric layer136may include a high-k dielectric material. In some embodiments, the third dielectric layer136includes the same material as the first dielectric layer126. The fourth dielectric layer138may include a low-k dielectric material. In some embodiments, the fourth dielectric layer138is a silicon-containing dielectric material having a k value less than about 7, such as SiCN, SiOC, or SiOCN. In some embodiments, the fourth dielectric layer138includes the same material as the second dielectric layer128. The second dielectric feature134may be formed in a similar fashion as the first dielectric feature130. For example, the third dielectric layer136may be formed on the cladding layer132and on the exposed surface of the insulating material118at the bottom of the trenches114a,114c,114dand on the exposed portions of the first dielectric feature (e.g., top surfaces of the first and second dielectric layers126,128), using a conformal process, such as an ALD process. The third dielectric layer136may have substantially the same thickness ranging from about 1 nm to about 30 nm. The fourth dielectric layer138is then formed in the trenches114a,114c,114dand over the fins112a,112b,112cand the first dielectric feature130. The fourth dielectric layer138may be formed by a flowable process, such as an FCVD process. The fourth dielectric layer138may have a thickness ranging from about 2 nm to about 15 nm. The fourth dielectric material138fills the trenches114a,114c,114d. Thus, if the thickness of the fourth dielectric layer138is less than about 2 nm, the trenches114a,114c,114dmay not be filled. Next, a planarization process is performed so that the top surfaces of the third dielectric layer136, the cladding layer132, the sacrificial layer107, the fourth dielectric layer138, the first dielectric layer126, and the second dielectric layer128are substantially co-planar, as shown inFIG.10. The planarization process may be any suitable process, such as a CMP process. The second dielectric feature134is formed in the trenches114a,114c,114d(FIG.9). The sidewalls133(133a,133b) and the bottom135of the fourth dielectric layer138are in contact with the third dielectric layer136. The sidewall133ais opposite the sidewall133b, and the bottom135connects the sidewall133ato sidewall133b. The third dielectric layer136is formed with a third thickness T3corresponding to the thickness of the third dielectric layer136discussed above, and the fourth dielectric layer138is formed with a fourth thickness T4greater than the third thickness T3. The third thickness T3of the third dielectric layer136may be greater, equal, or less than the first thickness T1of the first dielectric layer126. In some embodiments, the third thickness T3is substantially identical to the first thickness T1, which is about 1 nm to about 10 nm. In some embodiments, the third thickness T3is less than the first thickness T1. In some embodiments, the third thickness T3is greater than the first thickness T1. Likewise, the fourth thickness T4of the fourth dielectric layer138may be greater, equal, or less than the second thickness T2of the second dielectric layer128. In one embodiment, the fourth thickness T4is equal to the second thickness T2, which is about 5 nm to about 40 nm. In some embodiments, the fourth thickness T4is less than to the second thickness T2. In some embodiments, the fourth thickness T4is greater than to the second thickness T2. InFIG.11, the cladding layers132are recessed, and the sacrificial layers107are removed. The recess of the cladding layers132may be performed by any suitable etch process, such as dry etch, wet etch, or a combination thereof. The etch process may be controlled so that the remaining cladding layers132are substantially at the same level as the top surface140of the topmost first semiconductor layer106in the stack of semiconductor layers104. In cases where the cladding layers132and the sacrificial layers107are made of SiGe, the etch process may be a selective etch process that removes the cladding layers132and the sacrificial layers107but does not remove the layers of the first and second dielectric features130,134and the first semiconductor layers106. FIG.12Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.12B and12Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments. Cross-section B-B is in the X-Y plane extending across the first semiconductor layers106, and cross-section C-C is in the X-Y plane extending across the second semiconductor layers108. As shown inFIG.12A, one or more sacrificial gate stacks142are formed on the semiconductor device structure100. The sacrificial gate stacks142may each include a sacrificial gate dielectric layer144, a sacrificial gate electrode layer146, and a mask structure148. The sacrificial gate dielectric layer144may include one or more layers of dielectric material, such as SiO2, SiN, a high-k dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer144may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer146may include polycrystalline silicon (polysilicon). The mask structure148may include an oxygen-containing layer150and a nitrogen-containing layer152. The sacrificial gate electrode layer146and the mask structure148may be formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. The sacrificial gate stacks142may be formed by first depositing blanket layers of the sacrificial gate dielectric layer144, the sacrificial gate electrode layer146, and the mask structure148, followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stack142, the stacks of semiconductor layers104of the fins112a,112b,112care partially exposed on opposite sides of the sacrificial gate stack142. While one sacrificial gate stack142is shown, the number of the sacrificial gate stacks142is not limited to one. More than one sacrificial gate stacks142may be arranged along the X direction in some embodiments. FIG.13Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.13B and13Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments.FIG.13Dis a cross-sectional side view of the semiconductor device structure100taken along cross-section D-D ofFIG.12A. Cross-section D-D is in the X-Z plane extending across the fin112a. As shown inFIGS.13A-13D, a spacer154is formed on the sidewalls of the sacrificial gate stacks142. The spacer154may be formed by first depositing a conformal layer that is subsequently etched back to form sidewall spacers154. For example, a spacer material layer can be disposed conformally on the exposed surfaces of the semiconductor device structure100. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etch process, most of the spacer material layer is removed from horizontal surfaces, such as the tops of the fins112a,112b,112c, the cladding layers132, the third dielectric layers136, and the fourth dielectric layers138, leaving the spacers154on the vertical surfaces, such as the sidewalls of sacrificial gate stacks142. The spacer154may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. As shown inFIGS.13A-13D, exposed portions of the fins112a,112b,112c(FIG.12A), exposed portions of the cladding layers132, exposed portions of the first and second dielectric layers126,128, and exposed portions of the third and fourth dielectric layers136,138not covered by the sacrificial gate stacks142and the spacers154are selectively recessed or removed by using one or more suitable etch processes, such as dry etch, wet etch, or a combination thereof. In some embodiments, exposed portions of the stacks of semiconductor layers104of the fins112a,112b,112cand exposed portions of the cladding layers132are removed, exposing portions of the substrate portions116of the substrate101. In some embodiments, the etch process may reduce the height of the exposed portions of the first and second dielectric layers126,128(i.e., dielectric feature130) and exposed portions of the third and fourth dielectric layers136,138(i.e., dielectric feature134), as shown inFIG.13A. Thus, the third dielectric layer136under the sacrificial gate stack142and the spacers154has the height H1, while the third dielectric layer136located between source/drain (S/D) epitaxial features160(FIG.17A) has the height H2less than the height H1. The height H1may range from about 10 nm to 30 nm. Portions of the dielectric feature134having the height H1are used to cut off the gate electrode layers, while portions of the dielectric feature134having the height H2is in the S/D region are used to separate the source and the drain region. Thus, if the height H1is less than about 10 nm, the gate electrode layers may not be sufficiently cut-off. On the other hand, if the height H1is greater than about 30 nm, the manufacturing cost is increased without significant advantage. Likewise, the height of the first dielectric layer126between S/D epitaxial features160(FIG.17A) will have a height less than the height of the first dielectric layer126under the sacrificial gate stack142and the spacers154. At this stage, end portions of the stacks of semiconductor layers104under the sacrificial gate stacks142and the spacers154have substantially flat surfaces which may be flush with corresponding spacers154, as shown inFIG.13D. In some embodiments, the end portions of the stacks of semiconductor layers104under the sacrificial gate stacks142and spacers154are slightly horizontally etched. FIG.14Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.14B and14Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments.FIG.14Dis a cross-sectional side view of the semiconductor device structure100taken along cross-section D-D ofFIG.12A. As shown inFIGS.14A-14D, the edge portions of each second semiconductor layer108and the edge portions of the cladding layers132are removed to form a gap, and dielectric spacers158are formed in the gap. In some embodiments, the portions of the semiconductor layers108and the cladding layers132are removed by a selective wet etching process that does not remove the first semiconductor layers106. For example, in cases where the second semiconductor layers108and the cladding layers132are made of SiGe, and the first semiconductor layers106are made of silicon, a selective wet etching including an ammonia and hydrogen peroxide mixtures (APM) may be used. In some embodiments, the dielectric spacers158may be made of a low-k dielectric material, such as SiOCH or porous SiO2. In some embodiments, the dielectric spacers158includes a material having a k value less than 7, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric spacers158may be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers158. The dielectric spacers158may be protected by the first semiconductor layers106during the anisotropic etching process. As shown inFIG.14D, the dielectric spacers158may be flush with the corresponding spacers154. FIG.15Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.15B and15Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments.FIG.15Dis a cross-sectional side view of the semiconductor device structure100taken along cross-section D-D ofFIG.15C.FIG.15Eis a cross-sectional side view of the semiconductor device structure100taken along cross-section E-E ofFIG.15C. Cross-section D-D is in the X-Z plane extending across the second dielectric layer128, and cross-section C-C is in the X-Z plane extending across the third dielectric layer136. As shown inFIGS.15A-15E, portions of the first dielectric layer126and the third dielectric layer136are removed. In some embodiments, the first and third dielectric layers126,136are made of a high-k dielectric material, which may protect the second and fourth dielectric layers128,138during the removal of the exposed portions of the fins112a,112b,112cand the cladding layers132as described inFIGS.13A-13D. Without the first and third dielectric layers126,136, the second and fourth dielectric layers128,138may be substantially affected by the removal processes. However, after the removal of the exposed portions of the fins112a,112b,112cand the cladding layers132, the first and third dielectric layers126,136may be removed from the S/D regions in order to reduce the capacitance of the devices. The removal of the portions of the first and third dielectric layers126,136may be performed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, a halogen-based dry etch, such as a chlorine-based dry etch, is used, and the etchant may include a halogen, such as BCl3, SiCl4, Cl2, or other halogen-containing etchant. The halogen-based dry etch may be a selective etch process that does not substantially affect the second and fourth dielectric layers128,138, the dielectric spacers158, the spacer154, the insulating material118, and the first semiconductor layers106. The removed portions of the first and third dielectric layers126,136not only include the exposed portions of the first and third dielectric layers126,136, but also include the portions of the first and third dielectric layers126,136located under the spacer154and the second and fourth dielectric layers128,138. As shown inFIGS.15A,15D,15E, the first and third dielectric layers126,136may be lateral etched along the X direction, and the remaining first and third dielectric layers126,136may be recessed from planes P defined by the outer surfaces155of the spacers154disposed on opposite sidewalls of the sacrificial gate electrode layer146. FIG.16Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.16B and16Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments.FIG.16Dis a cross-sectional side view of the semiconductor device structure100taken along cross-section D-D ofFIG.15C.FIG.16Eis a cross-sectional side view of the semiconductor device structure100taken along cross-section E-E ofFIG.15C. As shown inFIGS.16A-16E, a dielectric spacer157is formed under the spacer154and the second and fourth dielectric layers128,138. The dielectric spacer157may include a material having a lower k value than that of the first and third dielectric layers126,136. The material of the dielectric spacer157may also have a different etch selectivity compared to the materials of the first and third dielectric layers126,136and the materials of the second and fourth dielectric layers128,138. For example, the dielectric spacer157may include a low-k dielectric material or a dielectric material having a k value less than 7. In some embodiments, the dielectric spacer157includes a material different from the materials of the first, second, third, and fourth dielectric layers126,128,136,138. In some embodiments, the dielectric spacer157includes the same material as the dielectric spacer158. In some embodiments, the materials of the dielectric spacers157,158are different. In some embodiments, the dielectric spacers157may be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacers157. The dielectric spacers157may be protected by the spacer154, the second dielectric layer128, and the fourth dielectric layer138during the anisotropic etching process. As shown inFIG.16E, a portion of the dielectric spacers157may be flush with the corresponding spacers154. For example, the portion of the dielectric spacers157disposed under and in contact with the spacer154includes an outer surface159, which is substantially co-planar with the outer surface155of the spacer154. As shown inFIG.16D, the portion of the dielectric spacers157disposed under and in contact with the fourth dielectric layer138(or the second dielectric layer128) may be disposed adjacent and in contact the third dielectric layer136(or the first dielectric layer126). In some embodiments, the outer surface155of the spacer154, the outer surface159of the portion of the dielectric spacer157disposed under and in contact with the spacer154, an outer surface161of the dielectric spacer158, an outer surface165of a portion of the second dielectric layer128disposed under and in contact with the spacer154, and an outer surface167of a portion of the fourth dielectric layer138disposed under and in contact with the spacer154may be substantially co-planar, as shown inFIG.16A. In some embodiments, an outer surface163of the first semiconductor layer106may be also substantially co-planar with the outer surfaces155,159,161,165,167. FIG.17Ais a perspective view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.17B and17Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments. As shown inFIGS.17A,17B,17C, S/D epitaxial features160are formed on the substrate portions116of the fins112a,112b,112c. The S/D epitaxial feature160may include one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. The S/D epitaxial features160may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate101. The S/D epitaxial features160are formed by an epitaxial growth method using CVD, ALD or MBE. The S/D epitaxial features160are in contact with the first semiconductor layers106, the dielectric spacers158, and the second and fourth dielectric layers128,138, as shown inFIGS.17B,17C. The S/D epitaxial features160may be the S/D regions. For example, one of a pair of S/D epitaxial features160located on one side of the first semiconductor layers106can be a source region, and the other of the pair of S/D epitaxial features160located on the other side of the first semiconductor layers106can be a drain region. A pair of S/D epitaxial features160includes a source epitaxial feature160and a drain epitaxial feature160connected by the channels (i.e., the first semiconductor layers106). In this disclosure, a source and a drain are interchangeably used, and the structures thereof are substantially the same. As described above, the portions of the first and the third dielectric layers126,136are removed from the S/D regions in order to decrease the device capacitance. FIGS.18A and18Bare cross-sectional views of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIG.18Ais a cross-sectional view of the semiconductor device structure100taken along cross-section A-A ofFIG.4, andFIG.18Bis a cross-sectional view of the semiconductor device structure100taken along cross-section D-D ofFIG.12A. After the formation of the S/D epitaxial features160, a contact etch stop layer (CESL)162may be formed on the S/D epitaxial features160, the first dielectric features130, and the second dielectric features134. The CESL162may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof. The CESL162may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL162is a conformal layer formed by the ALD process. Next, an interlayer dielectric (ILD) layer164is formed on the CESL162, as shown inFIGS.18A,18B. The materials for the ILD layer164may include an oxide formed by tetraethylorthosilicate (TEOS), un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer164may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer164, the semiconductor device structure100may be subject to a thermal process to anneal the ILD layer164. FIGS.19A and19Bare cross-sectional views of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIG.19Ais a cross-sectional view of the semiconductor device structure100taken along cross-section A-A ofFIG.17A, andFIG.19Bis a cross-sectional view of the semiconductor device structure100taken along cross-section D-D ofFIG.12A. As shown inFIGS.19A and19B, the sacrificial gate electrode layer146(FIG.17A) and the sacrificial gate dielectric layer144(FIG.17A) are removed, exposing the top surfaces of the cladding layers132and the stacks of semiconductor layers104. The sacrificial gate electrode layer146may be first removed by any suitable process, such as dry etch, wet etch, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer144, which may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer146but not the spacers154, the first dielectric features130, the second dielectric features134, and the CESL162. FIGS.20A and20Bare cross-sectional views of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.20C and20Dare top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments. As shown inFIGS.20A-20D, the cladding layers132and the second semiconductor layers108are removed. The removal process exposes the dielectric spacers158and the first semiconductor layers106. The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The removal process may be a selective etch process that removes the cladding layers132and the second semiconductor layers108but not the first semiconductor layers106, the spacers154, the first dielectric features130, the second dielectric features134, the CESL162, and the ILD layer164. In cases where the cladding layers132and the second semiconductor layers108are made of SiGe, and the first semiconductor layers106are made of silicon, a selective wet etching including an ammonia and hydrogen peroxide mixtures (APM) may be used. As a result of the etch process, openings166are formed, leaving the first semiconductor layers106(e.g., first semiconductor layers106a,106b) protruding from a first side121and a second side123(opposing the first side121) of the first dielectric feature130. Specifically, each of the first semiconductor layers106a,106bhas a first end in contact with the first dielectric layer126and a second end extending away from the first end, as shown inFIG.20A. The portion of the first semiconductor layers106not covered by the dielectric spacers158may be exposed in the openings166. Each first semiconductor layer106serves as a nanostructure channel of the nanostructure transistor or forksheet transistor. FIG.21Ais a cross-sectional view of one of various stages of manufacturing the semiconductor device structure100, in accordance with some embodiments.FIGS.21B and21Care top views of the semiconductor device structure100taken along cross-section B-B and cross-section C-C ofFIG.12A, respectively, in accordance with some embodiments. As shown inFIGS.21A,21B,21C, after the removal of the cladding layers132and the second semiconductor layers108, the first dielectric layer126and the third dielectric layer136are recessed by a removal process. The removal process is a controlled isotropic process so that exposed portions of the first dielectric layer126disposed on the second dielectric layer128are removed, while portions of the first dielectric layer126disposed between the second dielectric layer128and the first semiconductor layers106aand between the second dielectric layer128and the first semiconductor layers106bremain substantially intact. The remaining portions of the first dielectric layer126disposed under the second dielectric layer128may be in contact with the dielectric spacer157(FIG.17A). In some embodiments, exposed portions of the third dielectric layer136are simultaneously removed during the recess of the first dielectric layer126. In some embodiments, exposed portions of the third dielectric layer136are entirely removed as a result of the removal process. The portion of the third dielectric layer136disposed between the insulating material118and the fourth dielectric layer138may remain substantially intact. The remaining portions of the third dielectric layer136disposed under the fourth dielectric layer138may be in contact with the dielectric spacer157(FIG.16D). The removal process may be selective, so the materials other than the first and third dielectric layers126,136are not substantially affected. In either case, the lateral recess or removal of the first dielectric layer126increases the surface coverage of the gate electrode layer182(FIG.22) around the first semiconductor layer106b. Particularly, the gate electrode layer182extends towards the second dielectric layer128and over a plane defined by the interface between the first dielectric layer126and the first semiconductor layers106a. For example, the thickness of a gate dielectric layer180(FIG.22A) may be less than the thickness of the remaining portion of the first dielectric layer126disposed between the first semiconductor layers106and the second dielectric layer128. Thus, the gate electrode layer182may extend over the plane defined by the interface. Since the gate electrode layer182provides greater surface coverage around the first semiconductor layers106, a better electrical control over the nanostructure channels (e.g., first semiconductor layers106a,106b) is achieved and thus leakage in the off state is reduced. Furthermore, the recess or removal of the first and third dielectric layers126,136, which may include a dielectric material having a k value greater than 7, may reduce the device capacitance. As shown inFIGS.21B,21C, the portion of the first and third dielectric layers126,136exposed in the opening166are removed. Because the dielectric spacers157include a material different from the material of the first and third dielectric layers126,136, the dielectric spacers157are not substantially affected by the etchant used to remove the portions of the first and third dielectric layers126,136. Without the dielectric spacers157, the subsequently formed gate electrode layer182(FIG.22) may be formed too close to the S/D epitaxial features160, leading to gate to source/drain bridging. Thus, with the dielectric spacers157, gate to source/drain bridging may be reduced or eliminated. FIG.22Ais a cross-sectional view of the semiconductor device structure100taken along cross-section A-A ofFIG.17A, in accordance with some embodiments.FIG.22Bis a cross-sectional side view of the semiconductor device structure100taken along cross-section D-D ofFIG.12A, in accordance with some embodiments. As shown inFIGS.22A,22B, an interfacial layer (IL)178is formed to surround at least three surfaces (except for the surfaces being in contact with the first dielectric layer126and the S/D epitaxial features160) of the first semiconductor layers106(e.g., first semiconductor layers106a,106b). In some embodiments, the IL178may form on the first semiconductor layers106but not the first dielectric layer126. In some embodiments, the IL178may also form on the exposed surfaces of the substrate portion116of the substrate101. The IL178may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, hafnium silicate, etc. The IL178may be formed by CVD, ALD or any suitable conformal deposition technique. In one embodiment, the IL178is formed using ALD. The thickness of the IL178is chosen based on device performance considerations. In some embodiments, the IL178has a thickness ranging from about 0.5 nm to about 2 nm. Next, a gate dielectric layer180is formed on the exposed surfaces of the semiconductor device structure100. In some embodiments, the gate dielectric layer180is formed on the IL178, the insulating material118, and on the exposed surfaces of the first and second dielectric features130,134(e.g., the first dielectric layers126and the third dielectric layers136), as shown inFIG.22. The gate dielectric layer180may include or made of hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HMO), hafnium titanium oxide (HMO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k materials. In some embodiments, the gate dielectric layer180may include or made of the same material as the sacrificial gate dielectric layer144. The gate dielectric layer180may be a conformal layer formed by a conformal process, such as an ALD process or a CVD process. The gate dielectric layer180may have a thickness of about 0.5 nm to about 3 nm, which may vary depending on the application. The gate dielectric layer180may be in contact with the first, second, third, and fourth dielectric layers126,128,136,138, as shown inFIG.22A. As shown inFIGS.22A,22B, after the formation of the IL178and the gate dielectric layer180, the gate electrode layer182is formed in the opening166(FIG.21A). The gate electrode layer182is formed on the gate dielectric layer180to surround a portion of each first semiconductor layer106a,106b. The gate electrode layer182may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layer182may be formed by PVD, CVD, ALD, electro-plating, or other suitable method. The gate electrode layer182may be also deposited over the first and second dielectric features130,134. It is understood that the semiconductor device structure100may undergo further complementary metal oxide semiconductor (CMOS), middle-of-line (MOL), and/or back-end-of-line (BEOL) processes to form various features such as transistors, contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure100may also include backside contacts (not shown) on the backside of the substrate101by flipping over the semiconductor device structure100, removing the substrate101, and selectively connecting the S/D epitaxial features160to a backside power rail (e.g., positive voltage VDD or negative voltage VSS) through the backside contacts. The present disclosure provides a semiconductor device structure100including forksheet transistors with improved gate control over the nanostructure channels and reduced gate to source/drain bridging. By replacing a portion of the first and third dielectric layers126,136disposed under the spacer154with the dielectric spacers157, the dielectric spacers157are not substantially affected during the removal of the portion of the first and third dielectric layers126,136disposed in the channel regions. As a result, gate to source/drain bridging is reduced or eliminated. An embodiment is a semiconductor device structure. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials. Another embodiment is a semiconductor device structure. The structure includes a first semiconductor layer having a first surface, a first dielectric spacer in contact with the first semiconductor layer, a second dielectric spacer in contact with the first dielectric spacer, a spacer in contact with the second dielectric spacer, a first source/drain epitaxial feature in contact with the first surface of the first semiconductor layer, and a first dielectric layer in contact with the second dielectric spacer and the first source/drain epitaxial feature. The first dielectric spacer has a second surface, the second dielectric spacer has a third surface, the spacer has a fourth surface, and the first, second, third, and fourth surfaces and substantially co-planar. A further embodiment is a method. The method includes forming first, second and third fins from a substrate, the first fin including a first plurality of semiconductor layers, the second fin including a second plurality of semiconductor layers, the third fin including a third plurality of semiconductor layers, and each of the first, second, and third plurality of semiconductor layers includes first semiconductor layers and second semiconductor layers. The method further includes forming a first dielectric feature between the first fin and the second fin, and the first dielectric feature has a first dielectric layer and a second dielectric layer in contact with sidewalls and a bottom of the first dielectric layer. The method further includes forming a second dielectric feature between the second fin and the third fin, and the second dielectric feature has a third dielectric layer and a fourth dielectric layer in contact with sidewalls and a bottom of the third dielectric layer. The method further includes forming a sacrificial gate stack on a portion of the first, second, third fins, the first dielectric feature, and the second dielectric feature, and a portion of the first, second, third fins, first dielectric feature, and second dielectric feature are exposed. The method further includes removing a portion of the exposed portions of the first, second, and third fins not covered by the sacrificial gate stack, removing the exposed portion of the second and fourth dielectric layers, lateral recessing the second and fourth dielectric layers, forming a dielectric spacer under the first and third dielectric layers and in space created by the lateral recessing of the second and fourth dielectric layers, and removing the sacrificial gate stack to expose portions of the first, second, and third fins. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 59,796 |
11942479 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. One of ordinary skill in the art will appreciate that the dimensions may be varied according to different technology nodes. One of ordinary skill in the art will recognize that the dimensions depend upon the specific device type, technology generation, minimum feature size, and the like. It is intended, therefore, that the term be interpreted in light of the technology being evaluated. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. The present disclosure is related to semiconductor devices and methods of forming the same. More particularly, some embodiments of the present disclosure are related to semiconductor devices including a backside gate via under a gate structure for implementing a small-sized device. FIGS.1-20Fillustrate a method for manufacturing a semiconductor device (or an integrated circuit structure)100at various stages in accordance with some embodiments of the present disclosure. In addition to the semiconductor device100,FIGS.1-7A,12A,13A,14,15A,16A,17A,18A,19A, and20Adepict X-axis, Y-axis, and Z-axis directions. In some embodiments, the semiconductor device shown inFIGS.1-20Fmay be intermediate devices fabricated during processing of an integrated circuit (IC), or a portion thereof, that may include static random access memory (SRAM), logic circuits, passive components, such as resistors, capacitors, and inductors, and/or active components, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. FIGS.1-7A,12A,13A,14,15A,16A,17A,18A,19A, and20Aare perspective views of some embodiments of the semiconductor device100at intermediate stages during fabrication.FIGS.7B,8-11,12B,13B,15B,16B,17B,18B,19B, and20Bare cross-sectional views of some embodiments of the semiconductor device100at intermediate stages during fabrication along a first cut (e.g., cut I-I), which is along a lengthwise direction of the channel (semiconductor fin).FIGS.15C,17C,18C, and20Care cross-sectional views of some embodiments of the semiconductor device100at intermediate stages during fabrication along a second cut (e.g., cut which is along a lengthwise direction of another channel (another semiconductor fin).FIGS.15D,17D,18D, and20Dcross-sectional views of some embodiments of the semiconductor device100at intermediate stages during fabrication along a third cut (e.g., cut which is in one of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.15E,17E,18E, and20E are cross-sectional views of some embodiments of the semiconductor device100at intermediate stages during fabrication along a fourth cut (e.g., cut IV-IV), which is in another of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.15F,17F,18F, and20Fare cross-sectional views of some embodiments of the semiconductor device100at intermediate stages during fabrication along a fifth cut (e.g., cut V-V), which is in the isolation region and is parallel to the lengthwise direction of the channel. Reference is made toFIG.1. A substrate110is provided. In some embodiments, the substrate110is made of a suitable elemental semiconductor, such as silicon, diamond or germanium; a suitable alloy or compound semiconductor, such as Group-IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenic phosphide, or gallium indium phosphide), or the like. Further, the substrate110may include an epitaxial layer (epi-layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure. One or more semiconductor fins112are formed on the substrate110. The semiconductor fins112may be N-type or P-type. For example, one or some of the semiconductor fins112are N-type, and one or some of the semiconductor fins112are P-type. The semiconductor fins112may be formed using, for example, a patterning process to form trenches such that trenches are formed between adjacent semiconductor fins112. As discussed in greater detail below, the semiconductor fins112will be used to form FinFETs. It is understood that two semiconductor fins112are illustrated for purposes of illustration, but other embodiments may include any number of semiconductor fins. In some embodiments, one or more dummy semiconductor fins are formed adjacent to the semiconductor fins112. The semiconductor fins112may be formed by performing an etching process to the substrate110. Specifically, a patterned hard mask structure390is formed over the substrate110. In some embodiments, the patterned hard mask structure390is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon-nitride, or the like. For example, the patterned hard mask structure390includes an oxide pad layer392and a nitride mask layer394over the oxide pad layer392. The patterned hard mask structure390covers a portion of the substrate110while leaves another portion of the substrate110uncovered. The substrate110is then patterned using the patterned hard mask structure390as a mask to form trenches102. Accordingly, the semiconductor fins112are formed. Reference is made toFIG.2. Isolation structures120, such as shallow trench isolations (STI), are disposed in trenches102(seeFIG.1) and over the substrate110. The isolation structures120can be equivalently referred to as an isolation insulating layer in some embodiments. The isolation structures120may be made of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the isolation structures120are formed through a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the isolation structures120extending over the top surfaces of the semiconductor fins112, are removed using, for example, an etching back process, chemical mechanical polishing (CMP), or the like. The isolation structures120are then recessed to expose an upper portion of the semiconductor fin112as illustrated inFIG.2. In some embodiments, the isolation structures120are recessed using a single etch processes, or multiple etch processes. In some embodiments in which the isolation structures120is made of silicon oxide, the etch process may be, for example, a dry etch, a chemical etch, or a wet cleaning process. For example, the chemical etch may employ fluorine-containing chemical such as dilute hydrofluoric (dHF) acid. Reference is made toFIG.3. After the semiconductor fins112are formed, dummy gate structures130are formed over the substrate110and at least partially disposed over the semiconductor fins112. The portions of the semiconductor fins112underlying the dummy gate structures130may be referred to as the channel regions, and the semiconductor fins112may be referred to as channel layers. The dummy gate structures130may also define source/drain (S/D) regions of the semiconductor fins112, for example, the regions of the semiconductor fins112adjacent and on opposing sides of the channel regions. Dummy gate formation operation first forms a dummy gate dielectric layer over the semiconductor fins112. Subsequently, a dummy gate electrode layer and a hard mask which may include multiple layers (e.g., an oxide layer and a nitride layer) are formed over the dummy gate dielectric layer. The hard mask is then patterned to be nitride mask layers138and oxide mask layers136, followed by patterning the dummy gate electrode layer to be dummy gate electrodes134by using the mask layers138and pad layers136as etch masks. In some embodiments, after patterning the dummy gate electrode layer, the dummy gate dielectric layer is removed from the S/D regions of the semiconductor fins112and to be dummy gate dielectric layers132. The etch process may include a wet etch, a dry etch, and/or combinations thereof. The etch process is chosen to selectively etch the dummy gate dielectric layer without substantially etching the semiconductor fins112, the dummy gate electrode layers134, the oxide mask layers136and the nitride mask layers138. After formation of the dummy gate structures130is completed, gate spacers140are formed on sidewalls of the dummy gate structures130. In some embodiments of the gate spacer formation operations, a spacer material layer is deposited on the substrate110. The spacer material layer may be a conformal layer that is subsequently etched back to form gate spacers140. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer142(seeFIG.7B) and a second spacer layer144(seeFIG.7B) formed over the first spacer layer142. The first and second spacer layers142and144each are made of a suitable material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. By way of example and not limitation, the first and second spacer layers142and144may be formed by depositing in sequence two different dielectric materials over the dummy gate structures130using processes such as, an ALD process, a PEALD (plasma enhanced ALD) process, a PECVD process, a subatmospheric CVD (SACVD) process, or other suitable process. An anisotropic etching process is then performed on the deposited spacer layers142and144to expose portions of the semiconductor fins112not covered by the dummy gate structures130(e.g., in the source/drain regions of the semiconductor fins112). Portions of the spacer layers142and144directly above the dummy gate structures130may be removed by this anisotropic etching process. Portions of the spacer layer142and144on sidewalls of the dummy gate structures130may remain, forming gate sidewall spacers, which are denoted as the gate spacers140, for the sake of simplicity. In some embodiments, the first spacer layer142is formed of silicon oxide that has a lower dielectric constant than silicon nitride, and the second spacer layer144is formed of silicon nitride that has a higher etch resistance against subsequent etching processing (e.g., etching source/drain recesses in the semiconductor fins112) than silicon oxide. In some embodiments, the gate spacers140may be used to offset subsequently formed doped regions, such as source/drain regions. The gate spacers140may further be used for designing or modifying the source/drain region profile. Reference is made toFIG.4. After the formation of the gate spacers140is completed, source/drain epitaxial structures150are formed on source/drain regions of the semiconductor fins112that are not covered by the dummy gate structures130and the gate spacers140. In some embodiments, formation of the source/drain epitaxial structures150includes recessing source/drain regions of the semiconductor fins112, followed by epitaxially growing semiconductor materials in the recessed source/drain regions of the semiconductor fins112. The source/drain regions of the semiconductor fins112can be recessed using suitable selective etching processing that attacks the semiconductor fins112, but barely attacks the gate spacers140and the mask layers138of the dummy gate structures130. For example, recessing the semiconductor fins112may be performed by a dry chemical etch with a plasma source and an etchant gas. The plasma source may be inductively coupled plasma (ICP) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, reactive ion etch (RIE), or the like and the etchant gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the semiconductor fins112at a faster etch rate than it etches the gate spacers140and the mask layers138of the dummy gate structures130. In some other embodiments, recessing the semiconductor fin112may be performed by a wet chemical etch, such as ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the semiconductor fins112at a faster etch rate than it etches the gate spacers140and the mask layers138of the dummy gate structures130. In some other embodiments, recessing the semiconductor fins112may be performed by a combination of a dry chemical etch and a wet chemical etch. Once recesses are created in the source/drain regions of the semiconductor fins112, the source/drain epitaxial structures150are formed in the source/drain recesses in the semiconductor fins112by using one or more epitaxy or epitaxial (epi) processes that provides one or more epitaxial materials on the semiconductor fins112. During the epitaxial growth process, the gate spacers140limit the one or more epitaxial materials to source/drain regions in the semiconductor fins112. In some embodiments, the lattice constants of the source/drain epitaxial structures150are different from the lattice constant of the semiconductor fins112, so that the channel region in the semiconductor fins112and between the source/drain epitaxial structures150can be strained or stressed by the source/drain epitaxial structures150to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fins112. In some embodiments, the source/drain epitaxial structures150include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures150may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures150are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures150. In some exemplary embodiments, the source/drain epitaxial structures150in an n-type transistor include SiP, while those in a p-type include GeSnB and/or SiGeSnB. In embodiments with different device types, a mask, such as a photoresist, may be formed over n-type device regions, while exposing p-type device regions, and p-type epitaxial structures may be formed on the exposed semiconductor fins112in the p-type device regions. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type device region while exposing the n-type device regions, and n-type epitaxial structures may be formed on the exposed semiconductor fins112in the n-type device region. The mask may then be removed. Once the source/drain epitaxial structures150are formed, an annealing process can be performed to activate the p-type dopants or n-type dopants in the source/drain epitaxial structures150. The annealing process may be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal annealing (MSA) process or the like. Reference is made toFIG.5. A first interlayer dielectric (ILD) layer165is formed on the substrate110. In some embodiments, a contact etch stop layer (CESL)160is also formed prior to forming the first ILD layer165. In some embodiments, the CESL160includes a silicon nitride layer, a silicon oxynitride layer, and/or other suitable materials having a different etch selectivity than the first ILD layer165. The CESL160may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the first ILD layer165includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials having a different etch selectivity than the CESL160. The first ILD layer165may be deposited by a subatmospheric CVD (SACVD) process, a flowable CVD process, or other suitable deposition technique. In some embodiments, after formation of the first ILD layer165, the wafer may be subject to a high thermal budget process to anneal the first ILD layer165. In some examples, after forming the first ILD layer165, a planarization process may be performed to remove excessive materials of the first ILD layer165. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the first ILD layer165(and the CESL160, if present) overlying the dummy gate structures130. In some embodiments, the CMP process also removes the oxide mask layers136and the nitride mask layers138(as shown inFIG.4) and exposes the dummy gate electrodes134. Reference is made toFIG.6. The dummy gate electrodes134and the dummy gate dielectric layers132(seeFIG.5) are removed, resulting in gate trenches between corresponding gate spacers140. The dummy gate electrodes134and the dummy gate dielectric layers132are removed using a selective etching process (e.g., selective dry etching, selective wet etching, or combinations thereof) that etches materials in the dummy gate electrodes134and the dummy gate dielectric layers132at a faster etch rate than it etches other materials (e.g., the gate spacers140, the CESL160, and/or the first ILD layer165). Thereafter, replacement gate structures170are respectively formed in the gate trenches. The gate structures170may be the final gates of FinFETs. The final gate structures each may be a high-k/metal gate stack, however other compositions are possible. In some embodiments, each of the gate structures170forms the gate associated with the three-sides of the channel region provided by the semiconductor fins112. Stated another way, each of the gate structures170wraps around the semiconductor fins112on three sides. In various embodiments, the (high-k/metal) gate structure170includes a gate dielectric layer172lining the gate trench and a gate electrode over the gate dielectric layer172. The gate electrode may include a work function metal layer174formed over the gate dielectric layer172and a fill metal176formed over the work function metal layer174and filling a remainder of gate trenches. The gate dielectric layer172includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer174and/or fill metal176used within high-k/metal gate structures170may include a metal, metal alloy, or metal silicide. Formation of the high-k/metal gate structures170may include multiple deposition processes to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials. In some embodiments, the interfacial layer of the gate dielectric layer172may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer172may include hafnium oxide (HfD2). Alternatively, the gate dielectric layer172may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof. The work function metal layer174may include work function metals to provide a suitable work function for the high-k/metal gate structures170. For an n-type FinFET, the work function metal layer174may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AIC)), aluminides, and/or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer174may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal176may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. Reference is then made toFIGS.7A and7B, whereFIG.7Bis a cross-sectional view taken along line I-I ofFIG.7A. An etching back process is performed to etch back the replacement gate structures170and the gate spacers140, resulting in recesses R1over the etched-back gate structures170and the etched-back gate spacers140. In some embodiments, because the materials of the replacement gate structures170have a different etch selectivity than the gate spacers140, a first selective etching process may be initially performed to etch back the replacement gate structures170to lower the replacement gate structures170. Subsequently, a second selective etching process is performed to lower the gate spacers140. As a result, the top surfaces of the replacement gate structures170may be at a different level than the top surfaces of the gate spacers140. Subsequently, dielectric caps180are respectively formed in the recesses R1. For example, a dielectric cap layer is deposited over the substrate110until the recesses R1are overfilled. The dielectric cap layer includes SiN, SiC, SiCN, SiON, SiCON, combinations thereof or the like, and is formed by a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), combinations thereof or the like. A CMP process is then performed to remove the cap layer outside the recesses R1, leaving portions of the dielectric cap layer in the recesses R1to serve as the dielectric caps180. Source/drain contacts195are formed extending through the first ILD layer165. Formation of the source/drain contacts195includes, by way of example and not limitation, performing one or more etching processes to form contact openings extending though the first ILD layer165to expose the source/drain epitaxial structures150, depositing one or more metal materials overfilling the contact openings, and then performing a CMP process to remove excessive metal materials outside the contact openings. In some embodiments, the one or more etching processes are selective etching that etches the first ILD layer165at a faster etch rate than etching the dielectric caps180and the CESL160. As a result, the selective etching is performed using the dielectric caps180and the CESL160as an etch mask, such that the contact openings and hence source/drain contacts195are formed self-aligned to the source/drain epitaxial structures150without using an additional photolithography process. In that case, the dielectric caps180allowing for forming the source/drain contacts195in a self-aligned manner can be called self-aligned-contact (SAC) caps180. In some embodiments, metal alloy layers190are respectively formed above the source/drain epitaxial structures150prior to forming the source/drain contacts195. The front-side metal alloy layers190, which may be silicide layers, are respectively formed in the trenches and over the exposed source/drain epitaxial structures150by a self-aligned silicide (salicide) process. The silicide process converts the surface portions of the source/drain epitaxial structures150into the silicide contacts. Silicide processing involves deposition of a metal that undergoes a silicidation reaction with silicon (Si). In order to form silicide contacts on the source/drain epitaxial structures150, a metal material is blanket deposited on the source/drain epitaxial structures150. After heating the wafer to a temperature at which the metal reacts with the silicon of the source/drain epitaxial structures150to form contacts, unreacted metal is removed. The silicide contacts remain over the source/drain epitaxial structures150, while unreacted metal is removed from other areas. The silicide layer may include a material selected from titanium silicide, cobalt silicide, nickel silicide, platinum silicide, nickel platinum silicide, erbium silicide, palladium silicide, combinations thereof, or other suitable materials. In some embodiments, the metal alloy layer190may include germanium. Reference is made toFIG.8. A second ILD layer210is formed over the substrate110. In some embodiments, the second ILD layer210includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The second ILD layer210may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the second ILD layer210, the wafer may be subject to a high thermal budget process to anneal the second ILD layer210. Subsequently, the second ILD layer210is patterned to form at least one gate contact opening O1extending downward through the second ILD layer210and the dielectric cap180to the gate structure170. The second ILD layer210can be patterned by using suitable photolithography and etching techniques. Reference is made toFIG.9. A patterned mask layer M1is formed over the substrate110to fill the gate contact opening O1. The patterned mask layer M1has openings O2vertically above some of the source/drain contacts210. In some embodiments, the patterned mask layer M1may be a photoresist mask formed by suitable photolithography process. For example, the photolithography process may include spin-on coating a photoresist layer over the structure as illustrated inFIG.8, performing post-exposure bake processes, and developing the photoresist layer to form the patterned mask layer M1. In some embodiments, patterning the resist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process. Subsequently, with the patterned mask layer M1in place, a via etching process is performed to form via openings O3extending through the second ILD layer210. As a result of the etching process, the source/drain contacts195get exposed at bottoms of the via openings O3. Reference is made toFIG.10. The patterned mask layer M1(referring toFIG.9) is removed from the gate contact opening O1by ashing and/or wet stripping, and then a front-side butted contact (or butted via)220is formed to fill the gate contact opening O1and one of the via openings O3and a source/drain via225is formed to fill another via opening O3. The butted via220and the source/drain via225are formed using, by way of example and not limitation, depositing one or more metal materials overfilling the openings O1and O3, followed by a CMP process to remove excessive metal material(s) outside the openings O1and O3. As a result of the CMP process, the butted via220and the source/drain via225have top surfaces substantially coplanar with the second ILD layer210. The butted via220and the source/drain via225may include metal materials such as copper, aluminum, tungsten, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like. In some embodiments, the butted via220and the source/drain via225may further include one or more barrier/adhesion layers (not shown) to protect the second ILD layer210from metal diffusion (e.g., copper diffusion). The one or more barrier/adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using PVD, CVD, ALD, or the like. Reference is made toFIG.11. A front-side multilayer interconnection (MLI) structure230is formed over the substrate110. The front-side MLI structure230may include a plurality of front-side metallization layers232. The number of front-side metallization layers232may vary according to design specifications of the semiconductor device. Only three front-side metallization layers232are illustrated inFIG.11for the sake of simplicity. Except the bottommost front-side metallization layers232, the other front-side metallization layers232each includes a first front-side inter-metal dielectric (IMD) layer233and a second front-side IMD layer234. The second front-side IMD layers234are formed over the corresponding first front-side IMD layers233. The front-side metallization layers232include one or more horizontal interconnects, such as front-side metal lines235, respectively extending horizontally or laterally in the second front-side IMD layers234and vertical interconnects, such as front-side conductive vias236, respectively extending vertically in the first front-side IMD layers233. The front-side metal lines235and front-side conductive vias236can be formed using, for example, a single damascene process, a dual damascene process, the like, or combinations thereof. In some embodiments, the front-side IMD layers233-234may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the front-side IMD layers may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon oxide, silicon oxynitride, combinations thereof, or the like, formed by any suitable method, such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like. The front-side metal lines and vias235and236may include metal materials such as copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the front-side metal lines and vias235and236may further include one or more barrier/adhesion layers (not shown) to protect the respective front-side IMD layers233-234from metal diffusion (e.g., copper diffusion) and metallic poisoning. The one or more barrier/adhesion layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using physical vapor deposition (PVD), CVD, ALD, or the like. Reference is made toFIGS.12A and12B, whereFIG.12Bis a cross-sectional view taken along line I-I ofFIG.12A. A carrier substrate240is bonded to the front-side MLI structure230in accordance with some embodiments of the present disclosure. For clarity, the front-side metallization layers232are shown inFIG.12Band are omitted inFIG.12A. The carrier substrate240may be silicon, doped or undoped, or may include other semiconductor materials, such as germanium; a compound semiconductor; or combinations thereof. The carrier substrate240may provide a structural support during subsequent processing on backside of the semiconductor device and may remain in the final product in some embodiments. In some other embodiments, the carrier substrate240may be removed after the subsequent processing on backside of semiconductor device is complete. In some embodiments, the carrier substrate240is bonded to a topmost dielectric layer of the front-side MLI structure230by, for example, fusion bonding. Afterwards, the semiconductor device is flipped upside down, such that a backside surface of the substrate110faces upwards, as illustrated inFIGS.13A and13B. Reference is made toFIG.14. The substrate110is thinned down to expose the bottom surface124of the isolation structure120. In some embodiments, thinning is accomplished by a CMP process, a grinding process, or the like. Reference is made toFIGS.15A-15F, whereFIG.15Bis a cross-sectional view taken along line I-I ofFIG.15A,FIG.15Cis a cross-sectional view taken along line II-II ofFIG.15A,FIG.15Dis a cross-sectional view taken along line III-Ill ofFIG.15A,FIG.15Eis a cross-sectional view taken along line IV-IV ofFIG.15A, andFIG.15Fis a cross-sectional view taken along line V-V ofFIG.15A. As shown inFIG.15A, a third ILD layer310is formed to cover the semiconductor fins112and the isolation structures120. In some embodiments, the third ILD layer310includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The third ILD layer310may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the third ILD layer310, the wafer may be subject to a high thermal budget process to anneal the third ILD layer310. Subsequently, gate via openings O4aand O4bare formed in the third ILD layer310and extend to the gate electrode (e.g., the work function metal layer174or the fill metal176) of the gate structures170. For example, one of the gate via openings O4apasses through one of the semiconductor fins112as shown inFIGS.15B and15D, and another one of the gate via openings O4apasses through another one of the semiconductor fins112as shown inFIGS.15C and15E. Further, the gate via opening O4bpasses through one of the isolation structures120as shown inFIGS.15F and15E. In some embodiments, at least one source/drain via opening O5is formed in the third ILD layer310and extends to one of the source/drain epitaxial structures150. For example, the source/drain via opening O5passes through one of the semiconductor fins112as shown inFIG.15C. The gate via openings O4aand O4band the source/drain via opening O5may be formed by using a single or multiple etching process(es). Reference is made toFIGS.16A and16B, whereFIG.16Bis a cross-sectional view taken along line II-II ofFIG.16A. A portion of the third ILD layer310is removed, such that the source/drain via opening O5is connected to the adjacent gate via opening O4athrough a recess R2. For example, a mask layer is formed over the third ILD layer310and exposes the portion of the third ILD layer310. The portion of the third ILD layer310is then removed by using the mask layer as an etch mask. The mask layer is then removed after the formation of the recess R2. In some embodiments, the recess R2exposes the semiconductor fin112as shown inFIG.16B. In some other embodiments, the depth of the recess R2is shallower than a thickness of the third ILD layer310, such that the recess R2does not expose the semiconductor fin112. Reference is made toFIGS.17A-17F, whereFIG.17Bis a cross-sectional view taken along line I-I ofFIG.17A,FIG.17Cis a cross-sectional view taken along line II-II ofFIG.17A,FIG.17Dis a cross-sectional view taken along line III-III ofFIG.17A,FIG.17Eis a cross-sectional view taken along line IV-IV ofFIG.17A, andFIG.17Fis a cross-sectional view taken along line V-V ofFIG.17A. Spacer structures320are formed on inner sidewalls of the gate via openings O4aand O4band the source/drain via opening O5. The formation of the spacer structures320may include blanket forming spacer layers and then performing etching operations to remove the horizontal portions of the spacer layers. The remaining vertical portions of the spacer layers form the spacer structures320. The spacer structures320include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiCxOyNz, high-k dielectric materials, or combinations thereof. The spacer structures320can be formed using a deposition method, such as plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or the like. Reference is made toFIGS.18A-18F, whereFIG.18Bis a cross-sectional view taken along line I-I ofFIG.18A,FIG.18Cis a cross-sectional view taken along line II-II ofFIG.18A,FIG.18Dis a cross-sectional view taken along line III-III ofFIG.18A,FIG.18Eis a cross-sectional view taken along line IV-IV ofFIG.18A, andFIG.18Fis a cross-sectional view taken along line V-V ofFIG.18A. Gate via contacts335a,335band a backside butted contact (or butted via)330are formed in the openings O4a, O4b, and O5(seeFIG.17A). Formation of the gate via contacts335a,335band the backside butted contact330includes depositing one or more metal materials overfilling the openings O4a, O4b, and O5and the recess R2, and then performing a CMP process to remove excessive metal materials outside the openings O4a, O4b, and O5. As shown inFIGS.18B and18D, the spacer structure320isolates the gate via contact335afrom the semiconductor fin112. Reference is made toFIGS.19A-19B, whereFIG.19Bis a cross-sectional view taken along line I-I ofFIG.19A. A backside MLI structure340is formed over the third ILD layer310. The backside MLI structure340may include a plurality of backside metallization layers342. For clarity, the backside metallization layers342are shown inFIG.19Band are omitted inFIG.19A. The number of backside metallization layers342may vary according to design specifications of the semiconductor device. Only three backside metallization layers342are illustrated inFIG.19Bfor the sake of simplicity. Except the bottommost backside metallization layers342, the other backside metallization layers342each includes a first backside inter-metal dielectric (IMD) layer343and a second backside IMD layer344. The second backside IMD layers344are formed over the corresponding first backside IMD layers343. The backside metallization layers342include one or more horizontal interconnects, such as backside metal lines345, respectively extending horizontally or laterally in the second backside IMD layers344and vertical interconnects, such as backside conductive vias346, respectively extending vertically in the first backside IMD layers343. The backside metal lines345and backside conductive vias346can be formed using, for example, a single damascene process, a dual damascene process, the like, or combinations thereof. In some embodiments, the backside IMD layers343-344may include low-k dielectric materials having k values, for example, lower than about 4.0 or even 2.0 disposed between such conductive features. In some embodiments, the backside IMD layers may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon oxide, silicon oxynitride, combinations thereof, or the like, formed by any suitable method, such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like. The backside metal lines and vias345and346may include metal materials such as copper, aluminum, tungsten, combinations thereof, or the like. In some embodiments, the backside metal lines and vias345and346may further include one or more barrier/adhesion layers (not shown) to protect the respective backside IMD layers343-344from metal diffusion (e.g., copper diffusion) and metallic poisoning. The one or more barrier/adhesion layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed using physical vapor deposition (PVD), CVD, ALD, or the like. Reference is made toFIGS.20A-20F, whereFIG.20Bis a cross-sectional view taken along line I-I ofFIG.20A,FIG.20Cis a cross-sectional view taken along line II-II ofFIG.20A,FIG.20Dis a cross-sectional view taken along line III-III ofFIG.20A,FIG.20Eis a cross-sectional view taken along line IV-IV ofFIG.20A, andFIG.20Fis a cross-sectional view taken along line V-V ofFIG.20A. Optionally, the carrier substrate240(seeFIGS.19A and19B) is removed, and the semiconductor device inFIGS.19A and19Bis flipped upside down, such that the front-side MLI structure230faces upwards, as illustrated inFIGS.20A-20F. As shown inFIGS.20A and20B, the semiconductor device100includes the semiconductor fins112, the gate structures170across the semiconductor fins112, the source/drain epitaxial structures150on the semiconductor fins112and on opposite sides of the gate structures170, and backside vias under the gate structures170. For example, the semiconductor device100further includes a gate via contact335aunder the gate structure170. As shown inFIGS.20B and20D, the gate via contact335apasses through the semiconductor fin112and the gate dielectric layer172to the work function metal layer174(or to the fill metal176in some embodiments). As such, the gate via contact335ais electrically connected to one of the gate structures170. In some embodiments, the gate via contact335ais in contact with a bottom surface175of the work function metal layer174. As mentioned above, since the gate via contact335ais formed from a backside of the semiconductor device100, the gate via contact335atapers upward. The semiconductor device100further includes the spacer structures320. One of the spacer structures320laterally surrounds the gate via contact335ato electrically isolate the gate via contact335afrom the semiconductor fin112. Stated another way, the spacer structure320is in contact with the gate via contact335aand the semiconductor fin112. Further, the spacer structure320is in contact with the gate dielectric layer172. For example, the semiconductor device100further includes a gate via contact335bunder the gate structure170. As shown inFIGS.20E and20F, the gate via contact335bpasses through (or is embedded in) the isolation structure120and the gate dielectric layer172to the work function metal layer174(or to the fill metal176in some embodiments). As such, the gate via contact335bis electrically connected to one of the gate structures170. In some embodiments, the gate via contact335bis in contact with the bottom surface175of the work function metal layer174. As mentioned above, since the gate via contact335bis formed from a backside of the semiconductor device100, the gate via contact335btapers upward. Another one of the spacer structures320laterally surrounds the gate via contact335b. Stated another way, the spacer structure320is in contact with the gate via contact335band isolation structure120. Further, the spacer structure320is in contact with the gate dielectric layer172. For example, the semiconductor device100further includes a backside butted contact330under the gate structure170and the source/drain epitaxial structure150. As shown inFIGS.20C and20E, the backside butted contact330passes through the semiconductor fin112and the gate dielectric layer172to the work function metal layer174(or to the fill metal176in some embodiments). As such, the backside butted contact330is electrically connected to one of the gate structures170. In some embodiments, the backside butted contact330is in contact with a bottom surface175of the work function metal layer174. As mentioned above, since the backside butted contact330is formed from a backside of the semiconductor device100, the backside butted contact330tapers upward. Some of the spacer structures320laterally surround the backside butted contact330. Stated another way, the spacer structures320are in contact with the backside butted contact330and semiconductor fin112. Further, the spacer structures320are in contact with the gate dielectric layer172and the source/drain epitaxial structure150. The semiconductor device100includes at least one of the gate via contacts335a,335band the backside butted contact330. In some embodiments, the semiconductor device100further includes front-side vias, such as the front-side butted contact220and/or the source/drain via225as shown inFIG.20B. Further, the semiconductor device100may include front-side gate via contacts formed in the second ILD layer210and connected to the gate structure170. In some embodiments, each of the gate via contact335a,335band the backside butted contact330has a width or length in a range of about 8 nm to about 30 nm, and has a height in a range of about 10 nm to about 50 nm. The gate structure170is between the backside vias (e.g., the gate via contact335a,335band the backside butted contact330) and the dielectric cap180. In some embodiments, a top surface167of the first ILD layer165is higher than a top surface339of the backside vias (e.g., the gate via contact335a,335band the backside butted contact330), and a top surface122of the isolation structure120is lower than the top surface339of the backside vias (e.g., the gate via contact335a,335band the backside butted contact330). The backside vias (e.g., the gate via contact335a,335band the backside butted contact330) are electrically isolated from the front-side MLI structure230. FIG.21is a cross-sectional view of a semiconductor device (or an integrated circuit structure)100ain accordance with some embodiments of the present disclosure. The difference between the semiconductor device100ainFIG.21and the semiconductor device100inFIG.20Fis the present of the spacer structure. InFIG.21, the spacer structure320(seeFIG.20F) is omitted. That is, the gate via contact335bis in contact with the isolation structure120and the third ILD layer310. Other relevant structural details of the semiconductor device100ainFIG.21are the same as or similar to the semiconductor device100inFIG.20F, and, therefore, a description in this regard will not be repeated hereinafter. FIG.22is a cross-sectional view of a semiconductor device (or an integrated circuit structure)100bin accordance with some embodiments of the present disclosure. The difference between the semiconductor device100binFIG.22and the semiconductor device100inFIG.20Cis the present of an etch stop layer. InFIG.22, an etch stop layer350is formed to cover the semiconductor fins112and the isolation structures120prior to the formation of the third ILD layer310. As such, the etch stop layer350is between the third ILD layer310and the semiconductor fins112and/or between the third ILD layer310and the isolation structures120. The etch stop layer350can be an etch stop layer for etching the recess R2(seeFIG.16B). The etch stop layer350is made of a material different from the third ILD layer310, such that the etching process for forming the recess R2has an etching selectivity between the etch stop layer350and the third ILD layer310. For example, the etch stop layer350is a nitride layer (e.g., silicon nitride) and the third ILD layer310is an oxide layer (e.g., silicon dioxide). Other relevant structural details of the semiconductor device100binFIG.22are the same as or similar to the semiconductor device100inFIG.20C, and, therefore, a description in this regard will not be repeated hereinafter. FIGS.23A-34Fillustrate a method for manufacturing a semiconductor device (or an integrated circuit structure)200at various stages in accordance with some embodiments of the present disclosure. In addition to the semiconductor device200,FIGS.23A,24A,25A,26A,27A,28-3IA,32A,33, and34A depict X-axis, Y-axis, and Z-axis directions. In some embodiments, the semiconductor device shown inFIGS.23A-34Fmay be intermediate devices fabricated during processing of an integrated circuit (IC), or a portion thereof, that may include static random access memory (SRAM), logic circuits, passive components, such as resistors, capacitors, and inductors, and/or active components, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. FIGS.23A,24A,25A,26A,27A,28-31A,32A,33, and34Aare perspective views of some embodiments of the semiconductor device200at intermediate stages during fabrication.FIGS.23B,24B,25B,26B,27B,31B,32B, and34Bare cross-sectional views of some embodiments of the semiconductor device200at intermediate stages during fabrication along a first cut (e.g., cut I-I), which is along a lengthwise direction of the channel (semiconductor fin).FIGS.25C,26C,27C,31C,32C, and34Care cross-sectional views of some embodiments of the semiconductor device200at intermediate stages during fabrication along a second cut (e.g., cut II-II), which is along a lengthwise direction of another channel (another semiconductor fin).FIGS.25D,26D,27D,31D,32D, and34Dcross-sectional views of some embodiments of the semiconductor device200at intermediate stages during fabrication along a third cut (e.g., cut III-III), which is in one of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.25E,26E,27E,31E,32E, and34Ecross-sectional views of some embodiments of the semiconductor device200at intermediate stages during fabrication along a fourth cut (e.g., cut IV-IV), which is in another of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.25F,26F,27F,31F,32F, and34Fcross-sectional views of some embodiments of the semiconductor device200at intermediate stages during fabrication along a fifth cut (e.g., cut V-V), which is in the isolation region and is parallel to the lengthwise direction of the channel. Reference is made toFIGS.23A-23B, whereFIG.23Bis a cross-sectional view taken along line I-I ofFIG.23A. A carrier substrate540is provided. The carrier substrate540may be silicon, doped or undoped, or may include other semiconductor materials, such as germanium; a compound semiconductor; or combinations thereof. The carrier substrate540may provide a structural support during subsequent processing on backside of the semiconductor device and may remain in the final product in some embodiments. In some other embodiments, the carrier substrate540may be removed after the subsequent processing on front-side of semiconductor device is complete. Subsequently, a backside MLI structure640is formed over the carrier substrate540. The backside MLI structure640may include a plurality of backside metallization layers642. For clarity, the backside metallization layers642are shown inFIG.23Band are omitted inFIG.23A. The number of backside metallization layers642may vary according to design specifications of the integrated circuit structure. Only three backside metallization layers642are illustrated inFIG.23Bfor the sake of simplicity. Except the topmost backside metallization layers642, the other backside metallization layers642each includes a first backside inter-metal dielectric (IMD) layer643and a second backside IMD layer644. The first backside IMD layers643are formed over the corresponding second backside IMD layers644. The backside metallization layers642include one or more horizontal interconnects, such as backside metal lines645, respectively extending horizontally or laterally in the second backside IMD layers644and vertical interconnects, such as backside conductive vias646, respectively extending vertically in the first backside IMD layers643. For example, a dielectric layer is formed over the carrier substrate540, and openings are formed in the dielectric layer. Conductive materials are filled in the openings to form the backside metal lines645. Another dielectric layer is then formed over the dielectric layer and the backside metal lines645, and openings are formed in the dielectric layer. Another conductive material is then filled in the openings to form the backside conductive vias646. These operations are performed cyclically, and the backside MLI structure640is formed. In some embodiments, since the backside metallization layers642are formed from bottom to top, the backside metal lines645and the backside conductive vias646are tapered downward as shown inFIG.23B. Reference is made toFIGS.24A-24C, whereFIG.24Bis a cross-sectional view taken along line I-I ofFIG.24A, andFIG.24Cis a cross-sectional view taken along line II-II ofFIG.24A. As shown inFIG.24A, a third ILD layer610is formed to cover the backside MLI structure640. Materials, configurations, dimensions, processes and/or operations regarding the third ILD layer610are similar to or the same as the third ILD layer310ofFIG.20A. A conductive structure632is then formed in the third ILD layer610as shown inFIG.24C. For example, at least one opening612is formed in the third ILD layer610, and conductive materials are filled in the opening612to form the conductive structure632. The conductive structure632is connected to one of the backside metal lines645. Subsequently, a substrate410is formed over the third ILD layer610. For example, a semiconductor material (such as a wafer) is bonded to the third ILD layer610, and the semiconductor material is thin down to a predetermined thickness. Alternatively, the semiconductor material is epitaxially grown or CVD grown over the third ILD layer610. Materials, configurations, and/or dimensions regarding the substrate410are similar to or the same as the substrate110ofFIG.1. Reference is made toFIGS.25A-25F, whereFIG.25Bis a cross-sectional view taken along line I-I ofFIG.25A,FIG.25Cis a cross-sectional view taken along line II-II ofFIG.25A,FIG.25Dis a cross-sectional view taken along line III-III ofFIG.25A,FIG.25Eis a cross-sectional view taken along line IV-IV ofFIG.25A, andFIG.25Fis a cross-sectional view taken along line V-V ofFIG.25A. After the formation of the substrate410, the carrier substrate540(seeFIG.24A) is removed in some embodiments. The carrier substrate540can be removed after the formation of the front-side MLI structure530(seeFIG.34A) in some other embodiments. Gate via openings O6aand O6bare then formed in the substrate410and extend to the backside metal lines645or the conductive structure632. For example, the gate via opening O6band one of the gate via openings O6apass through the third ILD layer610as shown inFIGS.25B,25D,25E, and25F, and at least one source/drain via opening O7and another one of the gate via openings O6aexpose the conductive structure632as shown inFIGS.25C and25E. The gate via openings O6aand O6band the source/drain via opening O7may be formed by using a single or multiple etching process(es). Reference is made toFIGS.26A-26F, whereFIG.26Bis a cross-sectional view taken along line I-I ofFIG.26A,FIG.26Cis a cross-sectional view taken along line II-II ofFIG.26A,FIG.26Dis a cross-sectional view taken along line III-III ofFIG.26A,FIG.26Eis a cross-sectional view taken along line IV-IV ofFIG.26A, andFIG.26Fis a cross-sectional view taken along line V-V ofFIG.26A. Spacer structures620are formed on inner sidewalls of the gate via openings O6aand O6band the source/drain via opening O7. Materials, configurations, dimensions, processes and/or operations regarding the spacer structures620are similar to or the same as the spacer structures320ofFIGS.17A-17F. Reference is made toFIGS.27A-27F, whereFIG.27Bis a cross-sectional view taken along line I-I ofFIG.27A,FIG.27Cis a cross-sectional view taken along line II-II ofFIG.27A,FIG.27Dis a cross-sectional view taken along line III-III ofFIG.27A,FIG.27Eis a cross-sectional view taken along line IV-IV ofFIG.27A, andFIG.27Fis a cross-sectional view taken along line V-V ofFIG.27A. Gate via contacts635a,635band backside butted contacts (or butted via)633,634are formed in the openings O6a, O6b, and O7(seeFIG.26A). Formation of the gate via contacts635a,635band backside butted contact633,634includes depositing one or more metal materials overfilling the openings O6a, O6b, and O7, and then performing a CMP process to remove excessive metal materials outside the openings O6a, O6b, and O7. Reference is made toFIG.28. The substrate410(seeFIG.27A) is patterned to be one or more semiconductor fins (may be referred to as channel layers)412. Materials, configurations, dimensions, processes and/or operations regarding the semiconductor fins412are similar to or the same as the semiconductor fins112ofFIG.1. As shown inFIG.28, the backside butted contacts633,634and the gate via contact635aare embedded in the semiconductor fins412. That is, the semiconductor fins412wraps the backside butted contacts633,634and the gate via contact635a. Isolation structures420, such as shallow trench isolations (STI), are disposed in trenches402and over the third ILD layer610. The isolation structures420can be equivalently referred to as an isolation insulating layer in some embodiments. Materials, configurations, dimensions, processes and/or operations regarding the isolation structures420are similar to or the same as the isolation structures120ofFIG.2. As shown inFIG.28, the gate via contact635bis partially embedded in the isolation structures420, and a top portion of the gate via contact635bprotrudes from the isolation structures420. Reference is made toFIG.29. The structure ofFIG.28undergoes the processes similar to the processes shown inFIGS.3and4. That is, dummy gate structures430including dummy gate dielectric layers432, dummy gate electrodes434, oxide mask layers436, and nitride mask layers438are at least partially disposed over the semiconductor fins412. Materials, configurations, dimensions, processes and/or operations regarding the dummy gate structures430are similar to or the same as the dummy gate structures130ofFIG.3. Gate spacers440including first spacer layers442and second spacer layers444(seeFIG.31B) are formed on sidewalls of the dummy gate structures430. Materials, configurations, dimensions, processes and/or operations regarding the gate spacers440are similar to or the same as the gate spacers140ofFIG.3. After the formation of the gate spacers440is completed, source/drain epitaxial structures450are formed on source/drain regions of the semiconductor fins412that are not covered by the dummy gate structures430and the gate spacers440. Materials, configurations, dimensions, processes and/or operations regarding the source/drain epitaxial structures450are similar to or the same as the source/drain epitaxial structures150ofFIG.3. Reference is made toFIG.30. A first interlayer dielectric (ILD) layer465is formed on the semiconductor fins412and the isolation structures410. In some embodiments, a contact etch stop layer (CESL)460is also formed prior to forming the first ILD layer465. In some examples, after forming the first ILD layer465, a planarization process may be performed to remove excessive materials of the first ILD layer465. In some embodiments, the CMP process also removes the oxide mask layers436and the nitride mask layers438(as shown inFIG.29) and exposes the dummy gate electrodes434. Materials, configurations, dimensions, processes and/or operations regarding the first ILD layer465are similar to or the same as the first ILD layer165ofFIG.5. Materials, configurations, dimensions, processes and/or operations regarding the CESL460are similar to or the same as the CESL160ofFIG.5. Reference is made toFIGS.31A-31F, whereFIG.31Bis a cross-sectional view taken along line I-I ofFIG.31A,FIG.31Cis a cross-sectional view taken along line II-II ofFIG.31A,FIG.31Dis a cross-sectional view taken along line III-III ofFIG.31A,FIG.31Eis a cross-sectional view taken along line IV-IV ofFIG.31A, andFIG.31Fis a cross-sectional view taken along line V-V ofFIG.31A. The dummy gate electrodes434and the dummy gate dielectric layers432(seeFIG.30) are removed, resulting in gate trenches GT1between corresponding gate spacers440. Thereafter, a gate dielectric layer472is formed to lining the gate trenches GT1. The gate dielectric layer472covers the gate via contacts635a,635band the backside butted contact633,634. Materials, configurations, dimensions, processes and/or operations regarding the gate dielectric layer472are similar to or the same as the gate dielectric layer172ofFIG.6. Reference is made toFIGS.32A-32F, whereFIG.32Bis a cross-sectional view taken along line I-I ofFIG.32A,FIG.32Cis a cross-sectional view taken along line II-II ofFIG.32A,FIG.32Dis a cross-sectional view taken along line III-III ofFIG.32A,FIG.32Eis a cross-sectional view taken along line IV-IV ofFIG.32A, andFIG.32Fis a cross-sectional view taken along line V-V ofFIG.32A. A patterning process is performed to the structure ofFIG.31A, such that portions of the gate dielectric layer472covering the top surfaces of the gate via contacts635a,635band the backside butted contact633,634are removed as shown inFIGS.32B-32F. For example, a patterned mask layer can be formed over the structure ofFIG.31A. The patterned mask layer exposes the portions of the gate dielectric layer472covering the top surfaces of the gate via contacts635a,635band the backside butted contact633,634. Subsequently, an etching process is performed to remove these portions of the gate dielectric layer472, such that the top surfaces of the gate via contacts635a,635band the backside butted contact633,634are exposed. The patterned mask layer is removed after the etching process. In some embodiments, the gate dielectric layer472shown inFIGS.32A-32Fcan be formed by using a selectively deposition process. That is, a deposition rate of the gate dielectric layer472on a metal material (e.g., the gate via contacts635a,635band the backside butted contact633,634) is faster than a deposition rate of the gate dielectric layer472on a dielectric material (e.g., the spacer structures320, the gate spacers440, the first ILD layer465, and the CESL460. As such, the deposited gate dielectric layer472exposes the top surfaces of the gate via contacts635a,635band the backside butted contact633,634. Reference is made toFIG.33. The structure ofFIG.32Aundergoes the processes similar to the processes shown inFIGS.6and7A. That is, gate structures470including the gate dielectric layers472and a gate electrode (including work function metal layers474and fill metals476) are formed in the gate trenches GT1. Materials, configurations, dimensions, processes and/or operations regarding the gate structures470are similar to or the same as the gate structures170ofFIG.6. Subsequently, an etching back process is performed to etch back the replacement gate structures470and the gate spacers440, and dielectric caps480are formed over the etched gate structures470. Materials, configurations, dimensions, processes and/or operations regarding the dielectric caps480are similar to or the same as the dielectric caps180ofFIG.7A. After the formation of the dielectric caps480is completed, source/drain contacts495are formed extending through the first ILD layer465. In some embodiments, metal alloy layers490are respectively formed above the source/drain epitaxial structures450prior to forming the source/drain contacts495. Materials, configurations, dimensions, processes and/or operations regarding the source/drain contacts495are similar to or the same as the source/drain contacts195ofFIG.7A. Materials, configurations, dimensions, processes and/or operations regarding the metal alloy layers490are similar to or the same as the metal alloy layers190ofFIG.7A. Reference is made toFIGS.34A-34F, whereFIG.34Bis a cross-sectional view taken along line I-I ofFIG.34A,FIG.34Cis a cross-sectional view taken along line II-II ofFIG.34A,FIG.34Dis a cross-sectional view taken along line III-III ofFIG.34A,FIG.34Eis a cross-sectional view taken along line IV-IV ofFIG.34A, andFIG.34Fis a cross-sectional view taken along line V-V ofFIG.34A. The structure ofFIG.33undergoes the processes similar to the processes shown inFIGS.8-11. That is, a second ILD layer510is formed over the semiconductor fins412and the isolation structures420. At least one front-side butted contact (or butted via)520and at least one source/drain via525are formed in the second ILD layer510. Materials, configurations, dimensions, processes and/or operations regarding the second ILD layer510are similar to or the same as the second ILD layer210ofFIG.8. Materials, configurations, dimensions, processes and/or operations regarding the front-side butted contact520and the source/drain via525are similar to or the same as the front-side butted contact220and the source/drain via225ofFIG.10. Subsequently, a front-side MLI structure530is formed over the second ILD layer510. The front-side MLI structure530may include a plurality of front-side metallization layers532. The number of front-side metallization layers532may vary according to design specifications of the integrated circuit structure. Only three front-side metallization layers532are illustrated inFIGS.34B-34Ffor the sake of simplicity. Except the bottommost front-side metallization layers532, the other front-side metallization layers532each includes a first front-side inter-metal dielectric (IMD) layer533and a second front-side IMD layer534. The second front-side IMD layers534are formed over the corresponding first front-side IMD layers533. The front-side metallization layers532include one or more horizontal interconnects, such as front-side metal lines535, respectively extending horizontally or laterally in the second front-side IMD layers534and vertical interconnects, such as front-side conductive vias536, respectively extending vertically in the first front-side IMD layers533. Materials, configurations, dimensions, processes and/or operations regarding the front-side MLI structure530are similar to or the same as the front-side MLI structure230ofFIG.11. As shown inFIGS.34A and34B, the semiconductor device200includes the semiconductor fins412, the gate structures470across the semiconductor fins412, the source/drain epitaxial structures450on the semiconductor fins412and on opposite sides of the gate structures470, and backside vias under the gate structures470. For example, the semiconductor device200further includes a gate via contact635aunder the gate structure470. As shown inFIGS.34B and34D, the gate via contact635apasses through the semiconductor fin412to the work function metal layer474. As such, the gate via contact635ais electrically connected to one of the gate structures670. In some embodiments, the gate via contact635ais in contact with a bottom surface475of the work function metal layer474. As mentioned above, since the gate via contact635ais formed from a front-side of the semiconductor device200, the gate via contact635atapers downward. Further, as shown inFIG.34B, a portion of the work function metal layer474passes through the gate dielectric layer472to the gate via contact635a. The semiconductor device200further includes the spacer structures620. One of the spacer structures620laterally surrounds the gate via contact635ato electrically isolate the gate via contact635afrom the semiconductor fin412. Stated another way, the spacer structure620is in contact with the gate via contact635aand the semiconductor fin412. Further, the spacer structure620is in contact with the gate dielectric layer472. For example, the semiconductor device200further includes a gate via contact635bunder the gate structure470. As shown inFIGS.34E and34F, the gate via contact635bpasses through (or is embedded in) the isolation structure420to the work function metal layer474. That is, as shown inFIG.34E, the gate structure470surrounds a top portion of the gate via contact635b. As such, the gate via contact635bis electrically connected to one of the gate structures470. In some embodiments, the gate via contact635bis in contact with the bottom surface475of the work function metal layer474. As mentioned above, since the gate via contact635bis formed from a front-side of the semiconductor device200, the gate via contact635btapers downward. Another one of the spacer structures620laterally surrounds the gate via contact635b. Stated another way, the spacer structure620is in contact with the gate via contact635band isolation structure420. Further, the spacer structure620is in contact with the gate dielectric layer472. For example, the semiconductor device200further includes the backside butted contacts633and634under the gate structure470and the source/drain epitaxial structure450. As shown inFIGS.34C and34E, the backside butted contacts633and634pass through the semiconductor fin412to the work function metal layer474. As such, the backside butted contacts633and634are electrically connected to one of the gate structures470. In some embodiments, the backside butted contacts633and634are in contact with a bottom surface475of the work function metal layer474. As mentioned above, since the backside butted contacts633and634are formed from a backside of the semiconductor device200, the backside butted contacts633and634are tapered upward. Some of the spacer structures620laterally surround the backside butted contacts633and634. Stated another way, the spacer structures620are in contact with the backside butted contacts633and634and semiconductor fin412. Further, the spacer structures620are in contact with the gate dielectric layer472and the source/drain epitaxial structure450. The semiconductor device200includes at least one of the gate via contact635a,635band the backside butted contacts633and634. In some embodiments, the semiconductor device200further includes front-side vias, such as the front-side butted contact520and/or the source/drain via525as shown inFIG.34B. Further, the semiconductor device200may include front-side gate via contacts formed in the second ILD layer510and connected to the gate structure470. In some embodiments, each of the gate via contact635a,635band the backside butted contacts633,634has a width or length in a range of about 8 nm to about 30 nm, and has a height in a range of about 10 nm to about 50 nm. The gate structure470is between the backside vias (e.g., the gate via contact635a,635band the backside butted contacts633,634) and the dielectric cap480. In some embodiments, a top surface467of the first ILD layer465is higher than a top surface639of the backside vias (e.g., the gate via contact635a,635band the backside butted contacts633,634), and a top surface422of the isolation structure420is lower than the top surface639of the backside vias (e.g., the gate via contact635a,635band the backside butted contacts633,634). The backside vias (e.g., the gate via contact635a,635band the backside butted contacts633,634) are electrically isolated from the front-side MLI structure530. FIGS.35-49Fillustrate a method for manufacturing a semiconductor device (or an integrated circuit structure)300at various stages in accordance with some embodiments of the present disclosure. In addition to the semiconductor device300,FIGS.35-43A,44A,45A,46A,47A,48A, and49Adepict X-axis, Y-axis, and Z-axis directions. In some embodiments, the semiconductor device shown inFIGS.35-49Fmay be intermediate devices fabricated during processing of an integrated circuit (IC), or a portion thereof, that may include static random access memory (SRAM), logic circuits, passive components, such as resistors, capacitors, and inductors, and/or active components, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. FIGS.35-42,43A,44A,45A,46A,47A,48A, and49Aare perspective views of some embodiments of the semiconductor device300at intermediate stages during fabrication.FIGS.43B,44B,45B,46B,47B,48B, and49Bare cross-sectional views of some embodiments of the semiconductor device300at intermediate stages during fabrication along a first cut (e.g., cut I-I), which is along a lengthwise direction of the channel (semiconductor fin).FIGS.46C,47C, and49Care cross-sectional views of some embodiments of the semiconductor device300at intermediate stages during fabrication along a second cut (e.g., cut II-II), which is along a lengthwise direction of another channel (another semiconductor fin).FIGS.46D,47D, and49Dcross-sectional views of some embodiments of the semiconductor device300at intermediate stages during fabrication along a third cut (e.g., cut III-III), which is in one of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.46E,47E, and49Ecross-sectional views of some embodiments of the semiconductor device300at intermediate stages during fabrication along a fourth cut (e.g., cut IV-IV), which is in another of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.46F,47F, and49Fcross-sectional views of some embodiments of the semiconductor device300at intermediate stages during fabrication along a fifth cut (e.g., cut V-V), which is in the isolation region and is parallel to the lengthwise direction of the channel. Reference is made toFIG.35. A substrate710, which may be a part of a wafer, is provided. Materials, configurations, dimensions, processes and/or operations regarding the substrate710are similar to or the same as the substrate110ofFIG.1. A stacked structure960is formed on the substrate710through epitaxy, such that the stacked structure960forms crystalline layers. The stacked structure960includes first semiconductor layers962and second semiconductor layers964stacked alternately. The first semiconductor layers962and the second semiconductor layers964are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers962and the second semiconductor layers964are made of Si, a Si compound, SiGe, Ge or a Ge compound. InFIG.35, two layers of the first semiconductor layer962and three layers of the second semiconductor layer964are disposed. However, the number of the layers are not limited to five, and may be as small as 1 (each layer) and in some embodiments, 3-10 layers of each of the first and second semiconductor layers are formed. By adjusting the numbers of the stacked layers, a driving current of the GAA FET device can be adjusted. In some embodiments, the first semiconductor layers962can be SiGe layers having a germanium atomic percentage greater than zero. In some embodiments, the germanium percentage of the first semiconductor layers962is in the range between about 10 percent and about 50 percent. In some embodiments, the second semiconductor layers964may be pure silicon layers that are free from germanium. The second semiconductor layers964may also be substantially pure silicon layers, for example, with a germanium atomic percentage lower than about 1 percent. Furthermore, the second semiconductor layers964may be intrinsic, which are not doped with p-type and n-type impurities. In some embodiments, the first semiconductor layers962are referred to as sacrificial layers, and the second semiconductor layers964are referred to as channel layers. Subsequently, a patterned mask layer990is formed above the stacked structure960. In some embodiments, the patterned mask layer990includes a first mask layer992and a second mask layer994. The first mask layer992may be a pad oxide layer made of a silicon oxide, which can be formed by a thermal oxidation. The second mask layer994may be made of a silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), plasma enhanced atomic layer deposition (PEALD), atomic layer deposition (ALD), or other suitable process. Reference is made toFIG.36. The stacked structure960(seeFIG.35) is patterned by using the patterned mask layer990as an etch mask, such that the stacked structure960is patterned into fin structures905and trenches702extending in the X direction. InFIG.36, two fin structures905are arranged in the Y direction. But the number of the fin structures is not limited to, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures905to improve pattern fidelity in the patterning operations. The trenches702extend into the substrate710, and have lengthwise directions substantially parallel to each other. The trenches702form base portions712in the substrate710, where the base portions712protrude from the substrate710, and the fin structures905are respectively formed above the base portions712of the substrate710. The remaining portions of the stacked structure960are accordingly referred to as the fin structures905alternatively. Reference is made toFIG.37. After the fin structures905are formed, isolation structures720are formed above the structure inFIG.36so that the fin structures905are exposed. Materials, configurations, dimensions, processes and/or operations regarding the isolation structures720are similar to or the same as the isolation structures120ofFIG.2. Reference is made toFIG.38. The structure ofFIG.37undergoes the processes similar to the processes shown inFIGS.3and4. That is, dummy gate structures730including dummy gate dielectric layers732, dummy gate electrodes734, oxide mask layers736, and nitride mask layers738are at least partially disposed over the fin structures905. Materials, configurations, dimensions, processes and/or operations regarding the dummy gate structures730are similar to or the same as the dummy gate structures130ofFIG.3. Gate spacers740including first spacer layers742and second spacer layers744(seeFIG.43B) are formed on sidewalls of the dummy gate structures730. Materials, configurations, dimensions, processes and/or operations regarding the gate spacers740are similar to or the same as the gate spacers140ofFIG.3. Reference is made toFIG.39. After the formation of the gate spacers740is completed, the exposed portions of the fin structures905are removed by using a strained source/drain (SSD) etching process. The SSD etching process may be performed in a variety of ways. In some embodiments, the SSD etching process may be performed by a dry chemical etch with a plasma source and a reaction gas. The plasma source may be an inductively coupled plasma (ICP) etch, a transformer coupled plasma (TCP) etch, an electron cyclotron resonance (ECR) etch, a reactive ion etch (RIE), or the like and the reaction gas may be a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), chloride (Cl2), hydrogen bromide (HBr), oxygen (O2), the like, or combinations thereof. In some other embodiments, the SSD etching process may be performed by a wet chemical etch, such as ammonium peroxide mixture (APM), NH4OH, TMAH, combinations thereof, or the like. In yet some other embodiments, the SSD etch step may be performed by a combination of a dry chemical etch and a wet chemical etch. During the SSD etching process, portions of the base portions712are removed as well. Reference is made toFIG.40. Subsequently, the first semiconductor layers962are horizontally recessed (etched) to for recesses R3so that the second semiconductor layers964laterally extend past opposite end surfaces of the first semiconductor layers962. In some embodiments, end surfaces of the first semiconductor layers962may be substantially vertically aligned with the sidewalls of the dummy gate electrodes734and/or the sidewalls of the gate spacers740. Reference is made toFIG.41. Inner spacers970are respectively formed on sidewalls of the semiconductor layers962(seeFIG.40). For example, a dielectric material layer is formed over the structure ofFIG.40, and one or more etching operations are performed to form the inner spacers970. In some embodiments, the inner spacers970includes a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof and is different from the material of the gate spacers940. In some embodiments, the inner spacers970are silicon nitride. The inner spacers970may fully fill the recesses R3as shown inFIG.41. The dielectric material layer can be formed using CVD, including PECVD, PEALD, ALD, or other suitable processes. The etching operations include one or more wet and/or dry etching operations. In some embodiments, the etching is an isotropic etching. Reference is made toFIG.42. After the formation of the inner spacers970is completed, source/drain epitaxial structures750are formed on the base portions712that are not covered by the dummy gate structures730and the gate spacers740. Materials, configurations, dimensions, processes and/or operations regarding the source/drain epitaxial structures750are similar to or the same as the source/drain epitaxial structures150ofFIG.3. A first interlayer dielectric (ILD) layer765is formed on the source/drain epitaxial structures750and the isolation structures720. In some embodiments, a contact etch stop layer (CESL)760is also formed prior to forming the first ILD layer765. In some examples, after forming the first ILD layer765, a planarization process may be performed to remove excessive materials of the first ILD layer765. In some embodiments, the CMP process also removes the oxide mask layers736and the nitride mask layers738(as shown inFIG.41) and exposes the dummy gate electrodes734. Materials, configurations, dimensions, processes and/or operations regarding the first ILD layer765are similar to or the same as the first ILD layer165ofFIG.5. Materials, configurations, dimensions, processes and/or operations regarding the CESL760are similar to or the same as the CESL160ofFIG.5. Reference is made toFIGS.43A-43B, whereFIG.43Bis a cross-sectional view taken along line I-I ofFIG.43A. The structure ofFIG.42undergoes the processes similar to the processes shown inFIGS.6and7A. That is, the dummy gate electrodes734, the dummy gate dielectric layers732(seeFIG.42), and the first semiconductor layers962(seeFIG.40) are removed, resulting in gate trenches between corresponding gate spacers740. Thereafter, gate structures770including gate dielectric layers772and gate electrodes (including work function metal layers774and fill metals776) are formed in the gate trenches. Materials, configurations, dimensions, processes and/or operations regarding the gate structures770are similar to or the same as the gate structures170ofFIG.6. Reference is made toFIGS.44A-44B, whereFIG.44Bis a cross-sectional view taken along line I-I ofFIG.44A. The structure ofFIG.43Aundergoes the processes similar to the processes shown inFIGS.7A-12B. That is, an etching back process is performed to etch back the replacement gate structures770and the gate spacers740, and dielectric caps780are formed over the etched gate structures770. Materials, configurations, dimensions, processes and/or operations regarding the dielectric caps780are similar to or the same as the dielectric caps180ofFIG.7A. After the formation of the dielectric caps780is completed, source/drain contacts795are formed extending through the first ILD layer765. In some embodiments, metal alloy layers790are respectively formed above the source/drain epitaxial structures750prior to forming the source/drain contacts795. Materials, configurations, dimensions, processes and/or operations regarding the source/drain contacts795are similar to or the same as the source/drain contacts195ofFIG.7A. Materials, configurations, dimensions, processes and/or operations regarding the metal alloy layers790are similar to or the same as the metal alloy layers190ofFIG.7A. A second ILD layer810is formed over the source/drain epitaxial structures750and the isolation structures720. At least one front-side butted contact (or butted via)820and at least one source/drain via825are formed in the second ILD layer810. Materials, configurations, dimensions, processes and/or operations regarding the second ILD layer810are similar to or the same as the second ILD layer210ofFIG.8. Materials, configurations, dimensions, processes and/or operations regarding the front-side butted contact820and the source/drain via825are similar to or the same as the front-side butted contact220and the source/drain via225ofFIG.10. Subsequently, a front-side MLI structure830is formed over the second ILD layer810. The front-side MLI structure830may include a plurality of front-side metallization layers832. The number of front-side metallization layers832may vary according to design specifications of the integrated circuit structure. Only three front-side metallization layers832are illustrated inFIG.44Bfor the sake of simplicity. Except the bottommost front-side metallization layers832, the other front-side metallization layers832each includes a first front-side inter-metal dielectric (IMD) layer833and a second front-side IMD layer834. The second front-side IMD layers834are formed over the corresponding first front-side IMD layers833. The front-side metallization layers832include one or more horizontal interconnects, such as front-side metal lines835, respectively extending horizontally or laterally in the second front-side IMD layers834and vertical interconnects, such as front-side conductive vias836, respectively extending vertically in the first front-side IMD layers833. Materials, configurations, dimensions, processes and/or operations regarding the front-side MLI structure830are similar to or the same as the front-side MLI structure230ofFIG.11. A carrier substrate840is bonded to the front-side MLI structure830in accordance with some embodiments of the present disclosure. Materials, configurations, dimensions, processes and/or operations regarding the carrier substrate840are similar to or the same as the carrier substrate240ofFIG.12A. Afterwards, the semiconductor device is flipped upside down, such that a backside surface of the substrate710faces upwards, as illustrated inFIGS.45A and45B. Reference is made toFIGS.46A-46F, whereFIG.46Bis a cross-sectional view taken along line I-I ofFIG.46A,FIG.46Cis a cross-sectional view taken along line II-II ofFIG.46A,FIG.46Dis a cross-sectional view taken along line III-III ofFIG.46A,FIG.46Eis a cross-sectional view taken along line IV-IV ofFIG.46A, andFIG.46Fis a cross-sectional view taken along line V-V ofFIG.46A. The structure ofFIG.45Aundergoes the processes similar to the processes shown inFIGS.14-16F. That is, the substrate710inFIG.45Ais thinned down to expose the bottom surface724of the isolation structure720, and a third ILD layer910is formed to cover the base portions712and the isolation structures720. Materials, configurations, dimensions, processes and/or operations regarding the third ILD layer910are similar to or the same as the third ILD layer310ofFIG.15A. Subsequently, gate via openings O8aand O8bare formed in the third ILD layer910and extend to the gate electrode (e.g., the work function metal layer774or the fill metal776) of the gate structures770. For example, one of the gate via openings O8apasses through one of the base portions712as shown inFIGS.46B and46D, and another one of the gate via openings O8apasses through another one of the base portions712as shown inFIGS.46C and46E. Further, the gate via opening O8bpasses through one of the isolation structures720as shown inFIGS.46F and46E. In some embodiments, at least one source/drain via opening O9is formed in the third ILD layer910and extends to one of the source/drain epitaxial structures750. For example, the source/drain via opening O9passes through one of the base portion712as shown inFIG.46C. The gate via openings O8aand O8band the source/drain via opening O9may be formed by using a single or multiple etching process(es). A portion of the third ILD layer910is then removed, such that the source/drain via opening O9is connected to the adjacent gate via opening O8athrough a recess R4. Reference is made toFIGS.47A-47F, whereFIG.47Bis a cross-sectional view taken along line I-I ofFIG.47A,FIG.47Cis a cross-sectional view taken along line II-II ofFIG.47A,FIG.47Dis a cross-sectional view taken along line III-III ofFIG.47A,FIG.47Eis a cross-sectional view taken along line IV-IV ofFIG.47A, andFIG.47Fis a cross-sectional view taken along line V-V ofFIG.47A. The structure ofFIG.46Aundergoes the processes similar to the processes shown inFIGS.17A-18F. That is, spacer structures920are formed on inner sidewalls of the gate via openings O8aand O8band the source/drain via opening O9(seeFIG.46A). Gate via contacts935a,935band backside butted contact (or butted via)930are then formed in the openings O8a, O8b, and O9. Materials, configurations, dimensions, processes and/or operations regarding the spacer structures920are similar to or the same as the spacer structures320ofFIG.17A. Materials, configurations, dimensions, processes and/or operations regarding the gate via contacts935a,935band backside butted contact930are similar to or the same as the gate via contacts335a,335band backside butted contact330ofFIG.18A. Reference is made toFIGS.48A-48B, whereFIG.48Bis a cross-sectional view taken along line I-I ofFIG.48A. A backside MLI structure940is formed over the third ILD layer910. The backside MLI structure940may include a plurality of backside metallization layers942. For clarity, the backside metallization layers942are shown inFIG.48Band are omitted inFIG.48A. The number of backside metallization layers942may vary according to design specifications of the integrated circuit structure. Only three backside metallization layers942are illustrated inFIG.48Bfor the sake of simplicity. Except the bottommost backside metallization layers942, the other backside metallization layers942each includes a first backside inter-metal dielectric (IMD) layer943and a second backside IMD layer944. The second backside IMD layers944are formed over the corresponding first backside IMD layers943. The backside metallization layers942include one or more horizontal interconnects, such as backside metal lines945, respectively extending horizontally or laterally in the second backside IMD layers944and vertical interconnects, such as backside conductive vias946, respectively extending vertically in the first backside IMD layers943. Materials, configurations, dimensions, processes and/or operations regarding the backside MLI structure940are similar to or the same as the backside MLI structure340ofFIG.19B. Reference is made toFIGS.49A-49F, whereFIG.49Bis a cross-sectional view taken along line I-I ofFIG.49A,FIG.49Cis a cross-sectional view taken along line II-II ofFIG.49A,FIG.49Dis a cross-sectional view taken along line III-III ofFIG.49A,FIG.49Eis a cross-sectional view taken along line IV-IV ofFIG.49A, andFIG.49Fis a cross-sectional view taken along line V-V ofFIG.49A. Optionally, the carrier substrate840(seeFIGS.48A and48B) is removed, and the semiconductor device inFIGS.48A and48Bis flipped upside down, such that the front-side MLI structure830faces upwards, as illustrated inFIGS.49A-49F. As shown inFIGS.49A and49B, the semiconductor device300includes the second semiconductor layers964, the gate structures770wrapping around the second semiconductor layers964, the source/drain epitaxial structures750electrically connected to the second semiconductor layers964and on opposite sides of the gate structures770, and backside vias under the gate structures770. For example, the semiconductor device300further includes a gate via contact935aunder the gate structure770. As shown inFIGS.49B and49D, the gate via contact935apasses through the base portion712and the gate dielectric layer772to the work function metal layer774(or to the fill metal776in some embodiments). As such, the gate via contact935ais electrically connected to one of the gate structures770. In some embodiments, the gate via contact935ais in contact with a bottom surface775of the work function metal layer774. As mentioned above, since the gate via contact935ais formed from a backside of the semiconductor device300, the gate via contact935atapers upward. The semiconductor device300further includes the spacer structures920. One of the spacer structures920laterally surrounds the gate via contact935ato electrically isolate the gate via contact935afrom the base portion712. Stated another way, the spacer structure920is in contact with the gate via contact935aand the base portion712. Further, the spacer structure920is in contact with the gate dielectric layer772. For example, the semiconductor device300further includes a gate via contact935bunder the gate structure770. As shown inFIGS.49E and49F, the gate via contact935bpasses through (or is embedded in) the isolation structure720and the gate dielectric layer772to the work function metal layer774(or to the fill metal776in some embodiments). As such, the gate via contact935bis electrically connected to one of the gate structures770. In some embodiments, the gate via contact335bis in contact with the bottom surface775of the work function metal layer774. As mentioned above, since the gate via contact935bis formed from a backside of the semiconductor device300, the gate via contact935btapers upward. Another one of the spacer structures920laterally surrounds the gate via contact935b. Stated another way, the spacer structure920is in contact with the gate via contact935band isolation structure720. Further, the spacer structure920is in contact with the gate dielectric layer772. For example, the semiconductor device300further includes a backside butted contact930under the gate structure770and the source/drain epitaxial structure750. As shown inFIGS.49C and49E, the backside butted contact930passes through the base portion712and the gate dielectric layer772to the work function metal layer774(or to the fill metal776in some embodiments). As such, the backside butted contact930is electrically connected to one of the gate structures770. In some embodiments, the backside butted contact930is in contact with the bottom surface775of the work function metal layer774. As mentioned above, since the backside butted contact930is formed from a backside of the semiconductor device300, the backside butted contact930tapers upward. Some of the spacer structures920laterally surround the backside butted contact930. Stated another way, the spacer structures920are in contact with the backside butted contact930and base portion712. Further, the spacer structures920are in contact with the gate dielectric layer772and the source/drain epitaxial structure750. The semiconductor device300includes at least one of the gate via contact935a,935band the backside butted contact930. In some embodiments, the semiconductor device300further includes front-side vias, such as the front-side butted contact820and/or the source/drain via825as shown inFIG.49B. Further, the semiconductor device300may include front-side gate via contacts formed in the second ILD layer810and connected to the gate structure770. In some embodiments, each of the gate via contact935a,935band the backside butted contact930has a width or length in a range of about 8 nm to about 30 nm, and has a height in a range of about 10 nm to about 50 nm. The gate structure770is between the backside vias (e.g., the gate via contact935a,935band the backside butted contact930) and the dielectric cap780. In some embodiments, a top surface767of the first ILD layer765is higher than a top surface939of the backside vias (e.g., the gate via contact935a,935band the backside butted contact930), and a top surface722of the isolation structure720is lower than the top surface939of the backside vias (e.g., the gate via contact935a,935band the backside butted contact930). The backside vias (e.g., the gate via contact935a,935band the backside butted contact930) are electrically isolated from the front-side MLI structure830. FIG.50is a cross-sectional view of a semiconductor device (or an integrated circuit structure)300ain accordance with some embodiments of the present disclosure. The difference between the semiconductor device300ainFIG.50and the semiconductor device300inFIG.49Fis the present of the spacer structure. InFIG.50, the spacer structure920(seeFIG.49F) is omitted. That is, the gate via contact935bis in contact with the isolation structure720and the third ILD layer910. Other relevant structural details of the semiconductor device300ainFIG.50are the same as or similar to the semiconductor device300inFIG.49F, and, therefore, a description in this regard will not be repeated hereinafter. FIG.51is a cross-sectional view of a semiconductor device (or an integrated circuit structure)300bin accordance with some embodiments of the present disclosure. The difference between the semiconductor device300binFIG.51and the semiconductor device300inFIG.49Cis the present of an etch stop layer. InFIG.51, an etch stop layer950is formed to cover the base portions712and the isolation structures720prior to the formation of the third ILD layer910. As such, the etch stop layer950is between the third ILD layer910and the base portions712and/or between the third ILD layer910and the isolation structures720. The etch stop layer950can be an etch stop layer for etching the recess R4(seeFIG.46C). The etch stop layer950is made of a material different from the third ILD layer910, such that the etching process for forming the recess R4has an etching selectivity between the etch stop layer950and the third ILD layer910. For example, the etch stop layer950is a nitride layer (e.g., silicon nitride) and the third ILD layer910is an oxide layer (e.g., silicon dioxide). Other relevant structural details of the semiconductor device300binFIG.51are the same as or similar to the semiconductor device300inFIG.49C, and, therefore, a description in this regard will not be repeated hereinafter. FIGS.52A-59Fillustrate a method for manufacturing a semiconductor device (or an integrated circuit structure)400at various stages in accordance with some embodiments of the present disclosure. In addition to the semiconductor device400,FIGS.52A,53A,54-58A, and59Adepict X-axis, Y-axis, and Z-axis directions. In some embodiments, the semiconductor device shown inFIGS.52A-59Fmay be intermediate devices fabricated during processing of an integrated circuit (IC), or a portion thereof, that may include static random access memory (SRAM), logic circuits, passive components, such as resistors, capacitors, and inductors, and/or active components, such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. FIGS.52A,53A,54-57,58A, and59Aare perspective views of some embodiments of the semiconductor device400at intermediate stages during fabrication.FIGS.52B,53B,58B, and59Bare cross-sectional views of some embodiments of the semiconductor device400at intermediate stages during fabrication along a first cut (e.g., cut I-I), which is along a lengthwise direction of the channel (semiconductor fin).FIGS.52C,53C,58C, and59Care cross-sectional views of some embodiments of the semiconductor device400at intermediate stages during fabrication along a second cut (e.g., cut II-II), which is along a lengthwise direction of another channel (another semiconductor fin).FIGS.53D,58D, and59Dcross-sectional views of some embodiments of the semiconductor device400at intermediate stages during fabrication along a third cut (e.g., cut III-III), which is in one of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.53E,58E, and59Ecross-sectional views of some embodiments of the semiconductor device400at intermediate stages during fabrication along a fourth cut (e.g., cut IV-IV), which is in another of the gate regions and perpendicular to the lengthwise direction of the channel.FIGS.53F,58F, and59F cross-sectional views of some embodiments of the semiconductor device400at intermediate stages during fabrication along a fifth cut (e.g., cut V-V), which is in the isolation region and is parallel to the lengthwise direction of the channel. Reference is made toFIGS.52A-52C, whereFIG.52Bis a cross-sectional view taken along line I-I ofFIG.52A, andFIG.52Cis a cross-sectional view taken along line II-II ofFIG.52A. A carrier substrate1140is provided. Materials, configurations, dimensions, processes and/or operations regarding the carrier substrate1140are similar to or the same as the carrier substrate540ofFIG.23B. Subsequently, a backside MLI structure.1240is formed over the carrier substrate1140. The backside MLI structure1240may include a plurality of backside metallization layers1242. For clarity, the backside metallization layers1242are shown inFIGS.52B-52Cand are omitted inFIG.52A. The number of backside metallization layers1242may vary according to design specifications of the integrated circuit structure. Only three backside metallization layers1242are illustrated inFIGS.52B-52Cfor the sake of simplicity. Except the topmost backside metallization layers1242, the other backside metallization layers1242each includes a first backside inter-metal dielectric (IMD) layer1243and a second backside IMD layer1244. The first backside IMD layers1243are formed over the corresponding second backside IMD layers1244. The backside metallization layers1242include one or more horizontal interconnects, such as backside metal lines1245, respectively extending horizontally or laterally in the second backside IMD layers1244and vertical interconnects, such as backside conductive vias1246, respectively extending vertically in the first backside IMD layers1243. Materials, configurations, dimensions, processes and/or operations regarding the backside MLI structure1240are similar to or the same as the backside MLI structure640ofFIG.23B. Subsequently, a third ILD layer1210is formed to cover the backside MLI structure1240. Materials, configurations, dimensions, processes and/or operations regarding the third ILD layer1210are similar to or the same as the third ILD layer310ofFIG.20A. A conductive structure1232is then formed in the third ILD layer1210as shown inFIG.52C. For example, at least one opening is formed in the third ILD layer1210, and conductive materials are filled in the opening to form the conductive structure1232. The conductive structure1232is connected to one of the backside metal lines1245. Subsequently, a substrate1010is formed over the third ILD layer1210. Materials, configurations, dimensions, processes and/or operations regarding the substrate1010are similar to or the same as the substrate410ofFIG.24A. Reference is made toFIGS.53A-53F, whereFIG.53Bis a cross-sectional view taken along line I-I ofFIG.53A,FIG.53Cis a cross-sectional view taken along line II-II ofFIG.53A,FIG.53Dis a cross-sectional view taken along line III-III ofFIG.53A,FIG.53Eis a cross-sectional view taken along line IV-IV ofFIG.53A, andFIG.53Fis a cross-sectional view taken along line V-V ofFIG.53A. The structure ofFIG.52Aundergoes the processes similar to the processes shown inFIGS.25A-27F. That is, the carrier substrate1140(seeFIG.52A) is removed in some embodiments. The carrier substrate1140can be removed after the formation of the front-side MLI structure1130(seeFIG.59A) in some other embodiments. Gate via openings and source/drain via openings are then formed in the substrate1010and extend to the backside metal lines1245or the conductive structure1232. Spacer structures1220are formed on inner sidewalls of the gate via openings and the source/drain via opening. Materials, configurations, dimensions, processes and/or operations regarding the spacer structures1220are similar to or the same as the spacer structures320ofFIGS.17A-17F. Gate via contacts1235a,1235band backside butted contacts (or butted via)1233,1234are formed in the gate via openings and the source/drain via opening. Materials, configurations, dimensions, processes and/or operations regarding the gate via contacts1235a,1235band the backside butted contacts1233,1234are similar to or the same as the gate via contacts335a,335band the backside butted contacts330ofFIG.18A. Reference is made toFIG.54. A stacked structure1260is formed on the substrate1010through epitaxy, such that the stacked structure1260forms crystalline layers. The stacked structure1260includes first semiconductor layers1262and second semiconductor layers1264stacked alternately. In some embodiments, the first semiconductor layers1262are referred to as sacrificial layers, and the second semiconductor layers1264are referred to as channel layers. Materials, configurations, dimensions, processes and/or operations regarding the stacked structure1260are similar to or the same as the stacked structure960ofFIG.35. Subsequently, a patterned mask layer1290is formed above the stacked structure1260. In some embodiments, the patterned mask layer1290includes a first mask layer1292and a second mask layer1294. Materials, configurations, dimensions, processes and/or operations regarding the patterned mask layer1290are similar to or the same as the patterned mask layer990ofFIG.35. The structure ofFIG.54undergoes the processes similar to the processes shown inFIGS.36-44B. That is, as shown inFIG.55, the stacked structure1260(seeFIG.54) is patterned by using the patterned mask layer1290as an etch mask, such that the stacked structure1260is patterned into fin structures1205and trenches1202extending in the X direction. After the fin structures1205are formed, isolation structures1020are formed above in the trenches1202so that the fin structures1205are exposed. Materials, configurations, dimensions, processes and/or operations regarding the isolation structures1020are similar to or the same as the isolation structures120ofFIG.2. As shown inFIG.56, dummy gate structures1030including dummy gate dielectric layers1032, dummy gate electrodes1034, oxide mask layers1036, and nitride mask layers1038are at least partially disposed over the fin structures1205. Materials, configurations, dimensions, processes and/or operations regarding the dummy gate structures1030are similar to or the same as the dummy gate structures130ofFIG.3. Gate spacers1040including first spacer layers1042and second spacer layers1044(seeFIG.58B) are formed on sidewalls of the dummy gate structures1030. Materials, configurations, dimensions, processes and/or operations regarding the gate spacers1040are similar to or the same as the gate spacers140ofFIG.3. After the formation of the gate spacers1040is completed, the exposed portions of the fin structures1205are removed by using a strained source/drain (SSD) etching process. Subsequently, the first semiconductor layers1262are horizontally recessed (etched) to for recesses so that the second semiconductor layers1264laterally extend past opposite end surfaces of the first semiconductor layers1262. Inner spacers1270are respectively formed on sidewalls of the semiconductor layers1262. Materials, configurations, dimensions, processes and/or operations regarding the inner spacers1270are similar to or the same as the inner spacers970ofFIG.41. As shown inFIG.57, after the formation of the inner spacers1270is completed, source/drain epitaxial structures1050are formed on the base portions1012that are not covered by the dummy gate structures1030and the gate spacers1040. Materials, configurations, dimensions, processes and/or operations regarding the source/drain epitaxial structures1050are similar to or the same as the source/drain epitaxial structures150ofFIG.3. A first interlayer dielectric (ILD) layer1065is formed on the source/drain epitaxial structures1050and the isolation structures1020. In some embodiments, a contact etch stop layer (CESL)1060is also formed prior to forming the first ILD layer1065. In some examples, after forming the first ILD layer1065, a planarization process may be performed to remove excessive materials of the first ILD layer1065. In some embodiments, the CMP process also removes the oxide mask layers1036and the nitride mask layers1038(as shown inFIG.56) and exposes the dummy gate electrodes1034. Materials, configurations, dimensions, processes and/or operations regarding the first ILD layer1065are similar to or the same as the first ILD layer165ofFIG.5. Materials, configurations, dimensions, processes and/or operations regarding the CESL1060are similar to or the same as the CESL160ofFIG.5. Reference is made toFIGS.58A-58F, whereFIG.58Bis a cross-sectional view taken along line I-I ofFIG.58A,FIG.58Cis a cross-sectional view taken along line II-II ofFIG.58A,FIG.58Dis a cross-sectional view taken along line III-III ofFIG.58A,FIG.58Eis a cross-sectional view taken along line IV-IV ofFIG.58A, andFIG.58Fis a cross-sectional view taken along line V-V ofFIG.58A. The dummy gate electrodes1034and the dummy gate dielectric layers1032(seeFIG.57) and the first semiconductor layers1262(seeFIG.55) are removed, resulting in gate trenches GT2between corresponding gate spacers1040. Thereafter, a gate dielectric layer1072is selectively formed in the gate trenches GT2and exposes the gate via contacts1235a,1235band the backside butted contact1233,1234. Materials, configurations, dimensions, processes and/or operations regarding the gate dielectric layer1072are similar to or the same as the gate dielectric layer172ofFIG.6. Reference is made toFIGS.59A-59F, whereFIG.59Bis a cross-sectional view taken along line I-I ofFIG.59A,FIG.59Cis a cross-sectional view taken along line II-II ofFIG.59A,FIG.59Dis a cross-sectional view taken along line III-III ofFIG.59A,FIG.59Eis a cross-sectional view taken along line IV-IV ofFIG.59A, andFIG.59Fis a cross-sectional view taken along line V-V ofFIG.59A. The structure ofFIG.58Aundergoes the processes similar to the processes shown inFIGS.43A-44B. That is, gate structures1070including the gate dielectric layers1072and gate electrodes (including work function metal layers1074and fill metals1076) are formed in the gate trenches GT2. Materials, configurations, dimensions, processes and/or operations regarding the gate structures1070are similar to or the same as the gate structures170ofFIG.6. Subsequently, an etching back process is performed to etch back the replacement gate structures1070and the gate spacers1040, and dielectric caps1080are formed over the etched gate structures1070. Materials, configurations, dimensions, processes and/or operations regarding the dielectric caps1080are similar to or the same as the dielectric caps180ofFIG.7A. After the formation of the dielectric caps1080is completed, source/drain contacts1095are formed extending through the first ILD layer1065. In some embodiments, metal alloy layers1090are respectively formed above the source/drain epitaxial structures1050prior to forming the source/drain contacts1095. Materials, configurations, dimensions, processes and/or operations regarding the source/drain contacts1095are similar to or the same as the source/drain contacts195ofFIG.7A. Materials, configurations, dimensions, processes and/or operations regarding the metal alloy layers1090are similar to or the same as the metal alloy layers190ofFIG.7A. A second ILD layer1110is formed over the base portions1012and the isolation structures1020. At least one front-side butted contact (or butted via)1120and at least one source/drain via1125are formed in the second ILD layer1110. Materials, configurations, dimensions, processes and/or operations regarding the second ILD layer1110are similar to or the same as the second ILD layer210ofFIG.8. Materials, configurations, dimensions, processes and/or operations regarding the front-side butted contact1120and the source/drain via1125are similar to or the same as the front-side butted contact220and the source/drain via225ofFIG.10. Subsequently, a front-side MLI structure1130is formed over the second ILD layer1110. The front-side MLI structure1130may include a plurality of front-side metallization layers1132. The number of front-side metallization layers1132may vary according to design specifications of the integrated circuit structure. Only three front-side metallization layers1132are illustrated inFIGS.59B-59Ffor the sake of simplicity. Except the bottommost front-side metallization layers1132, the other front-side metallization layers1132each includes a first front-side inter-metal dielectric (IMD) layer1133and a second front-side IMD layer1134. The second front-side IMD layers1134are formed over the corresponding first front-side IMD layers1133. The front-side metallization layers1132include one or more horizontal interconnects, such as front-side metal lines1135, respectively extending horizontally or laterally in the second front-side IMD layers1134and vertical interconnects, such as front-side conductive vias1136, respectively extending vertically in the first front-side IMD layers1133. Materials, configurations, dimensions, processes and/or operations regarding the front-side MLI structure1130are similar to or the same as the front-side MLI structure230ofFIG.11. As shown inFIGS.59A and59B, the semiconductor device400includes the second semiconductor layers1264, the gate structures1070wrapping around the second semiconductor layers1264, the source/drain epitaxial structures1050electrically connected to the second semiconductor layers1264and on opposite sides of the gate structures1070, and backside vias under the gate structures1070. For example, the semiconductor device400further includes a gate via contact1235aunder the gate structure1070. As shown inFIGS.59B and59D, the gate via contact1235apasses through the base portions1012to the work function metal layer1074. As such, the gate via contact1235ais electrically connected to one of the gate structures1270. In some embodiments, the gate via contact1235ais in contact with a bottom surface1075of the work function metal layer1074. As mentioned above, since the gate via contact1235ais formed from a front-side of the semiconductor device400, the gate via contact1235atapers downward. Further, as shown inFIG.59B, a portion of the work function metal layer1074passes through the gate dielectric layer1072to the gate via contact1235a. The semiconductor device400further includes the spacer structures1220. One of the spacer structures1220laterally surrounds the gate via contact1235ato electrically isolate the gate via contact1235afrom the base portion1012. Stated another way, the spacer structure1220is in contact with the gate via contact1235aand the base portion1012. Further, the spacer structure1220is in contact with the gate dielectric layer1072. For example, the semiconductor device400further includes a gate via contact1235bunder the gate structure1070. As shown inFIGS.59E and59F, the gate via contact1235bpasses through (or is embedded in) the isolation structure1020to the work function metal layer1074. As such, the gate via contact1235bis electrically connected to one of the gate structures1070. In some embodiments, the gate via contact1235bis in contact with the bottom surface1075of the work function metal layer1074. As mentioned above, since the gate via contact1235bis formed from a front-side of the semiconductor device400, the gate via contact1235btapers downward. Another one of the spacer structures1220laterally surrounds the gate via contact1235b. Stated another way, the spacer structure1220is in contact with the gate via contact1235band isolation structure1020. Further, the spacer structure1220is in contact with the gate dielectric layer1072. For example, the semiconductor device400further includes backside butted contacts1233and1234under the gate structure1070and the source/drain epitaxial structure1050. As shown inFIGS.59C and59E, the backside butted contacts1233and1234pass through the base portion1012to the work function metal layer1074. As such, the backside butted contacts1233and1234are electrically connected to one of the gate structures1070. In some embodiments, the backside butted contacts1233and1234are in contact with the bottom surface1075of the work function metal layer1074. As mentioned above, since the backside butted contacts1233and1234are formed from a backside of the semiconductor device400, the backside butted contacts1233and1234are tapered upward. Some of the spacer structures1220laterally surround the backside butted contacts1233and1234. Stated another way, the spacer structures1220are in contact with the backside butted contacts1233and1234and base portion1012. Further, the spacer structures1220are in contact with the gate dielectric layer1072and the source/drain epitaxial structure1050. The semiconductor device400includes at least one of the gate via contact1235a,1235band the backside butted contacts1233and1234. In some embodiments, the semiconductor device400further includes front-side vias, such as the front-side butted contact1120and/or the source/drain via1125as shown inFIG.59B. Further, the semiconductor device400may include front-side gate via contacts formed in the second ILD layer1110and connected to the gate structure1070. In some embodiments, each of the gate via contact1235a,1235band the backside butted contacts1233,1234has a width or length in a range of about 8 nm to about 30 nm, and has a height in a range of about 10 nm to about 50 nm. The gate structure1070is between the backside vias (e.g., the gate via contact1235a,1235band the backside butted contacts1233,1234) and the dielectric cap1080. In some embodiments, a top surface1067of the first ILD layer1065is higher than a top surface1239of the backside vias (e.g., the gate via contact1235a,1235band the backside butted contacts1233,1234), and a top surface1022of the isolation structure1020is lower than the top surface1239of the backside vias (e.g., the gate via contact1235a,1235band the backside butted contacts1233,1234). The backside vias (e.g., the gate via contact1235a,1235band the backside butted contacts1233,1234) are electrically isolated from the front-side MLI structure1130. FIG.60Ais a perspective view of a semiconductor device (or an integrated circuit structure)100cin accordance with some embodiments of the present disclosure,FIG.60Bis a cross-sectional view taken along line I-I ofFIG.60A,FIG.60Cis a cross-sectional view taken along line II-II ofFIG.60A,FIG.60Dis a cross-sectional view taken along line III-III ofFIG.60A,FIG.60Eis a cross-sectional view taken along line IV-IV ofFIG.60A, andFIG.60Fis a cross-sectional view taken along line V-V ofFIG.60A. Reference is made toFIGS.60A-60F. The difference between the semiconductor device100cinFIGS.60A-60Fand the semiconductor device100inFIGS.20A-20Fis the depths of the backside butted contact330and the gate via contacts335a,335b. InFIGS.60B-60F, the backside butted contact330and the gate via contacts335a,335bpass through the work function metal layer174and are in contact with the fill metal176. Further, the spacer structures320also pass through the work function metal layer174and are in contact with the fill metal176. Other relevant structural details of the semiconductor device100cinFIGS.60A-60Fare the same as or similar to the semiconductor device100inFIGS.20A-20F, and, therefore, a description in this regard will not be repeated hereinafter. FIG.61is a cross-sectional view of a semiconductor device (or an integrated circuit structure)100din accordance with some embodiments of the present disclosure. The difference between the semiconductor device100dinFIG.61and the semiconductor device100cinFIG.60Fis the present of the spacer structure. InFIG.61, the spacer structure320(seeFIG.60F) is omitted. That is, the gate via contact335bis in contact with the isolation structure120and the third ILD layer310. Other relevant structural details of the semiconductor device100dinFIG.61are the same as or similar to the semiconductor device100cinFIG.60F, and, therefore, a description in this regard will not be repeated hereinafter. FIG.62is a cross-sectional view of a semiconductor device (or an integrated circuit structure)100ein accordance with some embodiments of the present disclosure. The difference between the semiconductor device100einFIG.62and the semiconductor device100cinFIG.60Cis the present of an etch stop layer. InFIG.62, an etch stop layer350is formed to cover the semiconductor fins112and the isolation structures120prior to the formation of the third ILD layer310. As such, the etch stop layer350is between the third ILD layer310and the semiconductor fins112and/or between the third ILD layer310and the isolation structures120. The etch stop layer350can be an etch stop layer for etching the recess R2(seeFIG.16B). The etch stop layer350is made of a material different from the third ILD layer310, such that the etching process for forming the recess R2has an etching selectivity between the etch stop layer350and the third ILD layer310. For example, the etch stop layer350is a nitride layer (e.g., silicon nitride) and the third ILD layer310is an oxide layer (e.g., silicon dioxide). Other relevant structural details of the semiconductor device100einFIG.62are the same as or similar to the semiconductor device100cinFIG.60C, and, therefore, a description in this regard will not be repeated hereinafter. Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the cell size of the semiconductor device can be shrinkage due to the gate vias and/or backside butt vias formed at the backside of the semiconductor device. Another advantage is that the size of the gate vias and/or backside butt vias can be enlarged due to the large space at the backside of the semiconductor device. With such configuration, the electrical performance of small-scaled semiconductor device can be improved. According to some embodiments, a device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. The gate structure wraps around the channel layer. The gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. The gate via is under the gate structure and is in contact with a bottom surface of the gate electrode. According to some embodiments, a method includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. An isolation structure is deposited over the substrate. A dummy gate structure is formed over the fin structure. A portion of the fin structure uncovered by the dummy gate structure is removed. A source/drain epitaxial structure is grown on a side of remaining portions of the second semiconductor layers. The dummy gate structure and the first semiconductor layers are replaced with a metal gate structure. The substrate is removed to expose a bottom surface of the isolation structure. An opening is formed in the isolation structure and exposes a gate electrode of the gate structure. A gate via is formed in the opening such that the gate via is connected to the metal gate structure and embedded in the isolation structure. According to some embodiments, a method includes forming a backside multilayer interconnection structure over a carrier substrate. A semiconductor layer is deposited over the backside multilayer interconnection structure. A first via is formed in the semiconductor layer and is electrically connected to the backside multilayer interconnection structure. The semiconductor layer is patterned to form a semiconductor fin over the backside multilayer interconnection structure. A gate structure is formed across the semiconductor fin and being electrically connected to the first via. A source/drain epitaxial structure is grown over the semiconductor fin. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 128,858 |
11942480 | DETAILED DESCRIPTION OF THE EMBODIMENTS All of the embodiments described herein are example embodiments, and thus, the inventive concept is not limited thereto and may be realized in various other forms. It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. FIG.1is a conceptual plan view for explaining a semiconductor device, according to some embodiments.FIG.2is a cross-sectional view taken along A-A ofFIG.1. Referring toFIGS.1and2, the semiconductor device according to some embodiments may include a substrate100, a first buried insulation layer110, a first well120, a second well220, a second buried insulation layer130, a third buried insulation layer230, a first semiconductor film140, a second semiconductor film240, a first element separation film160, a second element separation film150, a third element separation film250, a first gate structure180, a second gate structure280, and contacts191,193,195,197,291,293,295and297. The substrate100may include, but is not limited to, a base substrate and an epitaxial layer that is grown on the base substrate. The substrate100may include only the base substrate without an epitaxial layer. The substrate100may include a silicon substrate, a silicon germanium substrate, and the like, and the silicon substrate will be described here as an example. The first buried insulation layer110may be placed on the substrate100. Although the first buried insulation layer110may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a combination thereof, the disclosure is not limited thereto. The first element separation film160may be placed on the first buried insulation layer110. The first element separation film160may extend in a first direction DR1to come into contact with the first buried insulation layer110. The first direction DR1may be a direction from the substrate100toward the first buried insulation layer110. As shown, although a lower surface160S2of the first element separation film160may be in contact with an upper surface of the first buried insulation layer110, the disclosure is not limited thereto. Unlike the example shown in the drawings, the lower surface160S2of the first element separation film160may be placed inside the first buried insulation layer110, and may also be placed substantially on the same plane as the lower surface of the first buried insulation layer110. The first element separation film160may define an active region on the first buried insulation layer110. The first element separation film160may include a first element separation region161, a second element separation region162, and a third element separation region163. The first element separation region161, the second element separation region162, and the third element separation region163may be spaced apart from each other in a second direction DR2. The second direction DR2may be a direction that intersects the first direction DR1. The first element separation region161and the second element separation region162may define a first active region, and the second element separation region162and the third element separation region163may define a second active region. The first well120and the second well220may be placed on the first buried insulation layer110. The first well120may be placed in the first active region defined by the first element separation region161and the second element separation region162. The second well220may be placed in the second active region defined by the second element separation region162and the third element separation region163. The first well120and the second well220may be completely separated by the second element separation region162. The first well120and the second well220may not be in contact with each other. That is, the first well120and the second well220may be electrically insulated. The first well120may include a first portion121extending along the upper surface of the first buried insulation layer110, and a second portion122extending in the first direction DR1at a side of the first portion121. The second portion122may extend along one side wall of the first element separation region161. Alternatively, the first well120may include the first portion121having a first thickness and the second portion122having a second thickness on the first buried insulation layer110. The first thickness and the second thickness may be based on the first direction DR1. The second thickness may be thicker than the first thickness. A top surface of the first well120may be placed substantially on the same plane as an upper surface160S1of the first element separation film160and/or an upper surface250S1of the third element separation film250. The upper surface122S of the second portion122of the first well120may be placed substantially on the same plane as the upper surface160S1of the first element separation film160and/or the upper surface150S1of the second element separation film150. The second well220may include a third portion221extending along the upper surface of the first buried insulation layer110, and a fourth portion222extending in the first direction DR1at a side of the third portion221. The fourth portion222may extend along one side wall of the third element separation region163. Alternatively, the second well220may include the third portion221having a third thickness and the fourth portion222having a fourth thickness on the first buried insulation layer110. The fourth thickness may be thicker than the third thickness. A top surface of the second well220may be placed substantially on the same plane as the upper surface160S1of the first element separation film160and/or the upper surface250S1of the third element separation film250. An upper surface222S of the fourth portion222of the second well220may be placed substantially on the same plane as the upper surface160S1of the first element separation film160and/or the upper surface250S1of the third element separation film250. The first well120and the second well220may have different conductive types from each other. The first well120may have a first conductive type and the second well220may have a second conductive type. The first well120may be, for example, an N type, and the second well220may be a P type. The first well120may function as a body region of a first transistor, and the second well220may function as a body region of a second transistor. A first well contact191may be placed on the upper surface122S of the second portion122of the first well120. A lower surface of the first well contact191may be in contact with the upper surface122S of the second portion122of the first well120. The first well contact191may be electrically connected to the first well120. A body bias voltage may be applied to the first well120through the first well contact191. A second well contact291may be placed on the upper surface222S of the fourth portion222of the second well220. A lower surface of the second well contact291may be in contact with the upper surface222S of the fourth portion222of the second well220. The second well contact291may be electrically connected to the second well220. A body bias voltage may be applied to the second well220through the second well contact291. Therefore, a threshold voltage, a saturation current, and a leakage current of the semiconductor device according to some embodiments may be controlled. The first well contact191and the second well contact291may include a conductive substance. Although the conductive substance may include, for example, at least one of polycrystalline silicon, a metal silicide compound, a conductive metal nitride, and a metal, the disclosure is not limited thereto. Unlike the shown example, a silicide film may be formed between the lower surface of the first well contact191and the upper surface122S of the second portion122of the first well120and/or between the lower surface of the second well contact291and the upper surface222S of the fourth portion222of the second well220. Accordingly, the resistance between the first well contact191and the first well120and/or between the second well contact291and the second well220may be reduced. In the semiconductor device according to some embodiments, because the first well120and the second well220are completely separated by the first element separation film160, no PN junction is formed between the first well120and the second well220. Therefore, not only a forward body bias (FBB) voltage but also a reverse body bias (RBB) voltage may be applied to the first well120through the first well contact191. The forward body bias voltage as well as the reverse body bias voltage may be applied to the second well290through the second well contact192. That is, the body bias voltage applied to the first well120is not limited by the body bias voltage applied to the second well220. The first well120and the second well220are not limited by one of the forward body bias voltage and the reverse body bias voltage, respectively. The body bias voltage applied to the first well120and the second well220may be applied freely within a range that does not cause an HCI (Hot Carrier Injection) phenomenon on the second element separation region162or does not become equal to or higher than a breakdown voltage. Accordingly, the semiconductor device according to some embodiments may have various threshold voltages depending on the body bias voltage, and the scaling of the semiconductor device may become easier. The second buried insulation layer130may be placed on the first portion121of the first well120. The first well120may be insulated from the first semiconductor film140by the second buried insulation layer130. The third buried insulation layer230may be placed on the third portion221of the second well220. The second well220may be insulated from the second semiconductor film240by the third buried insulation layer230. The second buried insulation layer130and the third buried insulation layer230may be separated by the second element separation region162. That is, the substrate100may be a silicon substrate including two insulation layers. Although the second buried insulation layer130and the third buried insulation layer230may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a combination thereof, the disclosure is not limited thereto The first semiconductor film140may be placed on the second buried insulation layer130. The first semiconductor film140may include a first source region141, a first drain region142, and a first channel region143. The first source region141and the first drain region142may function as a source and a drain of the first gate structure180, respectively. The second semiconductor film240may be placed on the third buried insulation layer230. The second semiconductor film240may include a second source region241, a second drain region242, and a second channel region243. The second source region241and the second drain region242may function as a source and a drain of the second gate structure280, respectively. The first semiconductor film140and the second semiconductor film240may be separated by the second element separation region162. Unlike the example shown in the drawings, at least a part of the first source region141and the first drain region142may have a structure that protrudes from the upper surface of the first semiconductor film140, and at least a part of the second source region241and the second drain region242may have a structure that protrudes from the upper surface of the second semiconductor film240. The first semiconductor film140and the second semiconductor film240may have different conductive types from each other. The first semiconductor film140may have the same conductive type as the first well120, and the second semiconductor film240may have the same conductive type as the second well220. The first semiconductor film140may have a first conductive type, and the second semiconductor film240may have a second conductive type. The first semiconductor film140may be, for example, an N type, and the second semiconductor film240may be a P type. A first source contact193and a second source contact293may be formed on the first source region141and the second source region241, respectively. A source voltage may be applied to each of the first source region141and the second source region241through the first source contact193and the second source contact293. A first drain contact197and a second drain contact297may be formed on the first drain region142and the second drain region242, respectively. A drain voltage may be applied to the first drain region142and the second drain region292through the first drain contact197and the second drain contact297, respectively. The first source contact193, the second source contact293, the first drain contact197, and the second drain contact297may include a conductive substance. For example, although such a conductive substance may include at least one of polycrystalline silicon, metal silicide compound, conductive metal nitride, and metal, the disclosure is not limited thereto. The second element separation film150may be placed between the first element separation region161and the second element separation region162. The second element separation film150may be placed on the first well120. The second element separation film150may extend in the first direction DR1and come into contact with the second buried insulation layer130. A lower surface150S2of the second element separation film150may be placed substantially on the same plane as the lower surface of the second buried insulation layer130. The second element separation film150may separate the second portion122of the first well120and the second buried insulation layer130, and the second portion122of the first well120and the first semiconductor film140. That is, the second portion122of the first well120may extend along one side wall of the second element separation film150. The second portion122of the first well120may fill between the first element separation region161and the second element separation film150. Therefore, in the semiconductor device according to some embodiments, the first well120may be insulated. The first well120may be in contact with the first buried insulation layer110, the first element separation region161, the first element separation film150, the second buried insulation layer130, and the second element separation region162. The first well120may be insulated by the first buried insulation layer110, the first element separation region161, the first element separation film150, the second buried insulation layer130, and the second element separation region162. The third element separation film250may be placed between the second element separation region162and the third element separation region163. The third element separation film250may be placed on the second well220. The third element separation film250may extend in the first direction DR1and come into contact with the third buried insulation layer230. A lower surface250S2of the third element separation film250may be placed substantially on the same plane as the lower surface of the third buried insulation layer230. The third element separation film250may separate the fourth portion222of the second well220and the third buried insulation layer230, and the fourth portion222of the second well220and the second semiconductor film240. That is, the fourth portion222of the second well220may extend along one side wall of the third element separation film250. The fourth portion222of the second well220may fill between the third element separation film250and the third element separation region163. Therefore, in the semiconductor device according to some embodiments, the second well220may be insulated. The second well220may be in contact with the first buried insulation layer110, the second element separation region162, the third buried insulation layer230, the third element separation film250, and the third element separation region163. The second well220may be insulated by the first buried insulation layer110, the second element separation region162, the third buried insulation layer230, the third element separation film250, and the third element separation region163. Unlike the shown example, the lower surface150S2of the second element separation film150and the lower surface250S2of the third element separation film250may be placed substantially on the same plane as the upper surface of the second buried insulation layer130and the upper surface of the third buried insulation layer230, or may be placed inside the second buried insulation layer130and the third buried insulation layer230, respectively. The lower surface150S2of the second element separation film150and the lower surface250S2of the third element separation film250may be placed above a level of the lower surface160S2of the first element separation film160. The first gate structure180may be placed on the first semiconductor film140. The first gate structure180may include a first gate electrode181, a first gate insulation layer182and a first gate spacer183. The second gate structure280may be placed on the second semiconductor film240. The second gate structure280may include a second gate electrode281, a second gate insulation layer282, and a second gate spacer283. The first gate structure180and the first semiconductor film140may form the first transistor, and the second gate structure280and the second semiconductor film240may form the second transistor. The first gate electrode181may be formed to fill a gate trench defined by the first gate spacer183and the first gate insulation layer182. The second gate electrode281may be formed to fill a gate trench defined by the second gate spacer283and the second gate insulation layer282. The first gate electrode181and the second gate electrode281may include a conductive substance. For example, the first gate electrode181and the second gate electrode281may include at least one of polysilicon (poly Si), amorphous silicon (a-Si), tantalum (Ti), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum (Ta), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W) and combinations thereof. The first gate electrode181may be formed through, but is not limited to, for example, a replacement process (or a gate last process). The first gate electrode181may also be formed through a gate first process. A first gate contact195may be formed on the first gate electrode181. A gate voltage may be applied to the first gate electrode181through the first gate contact195. The second gate contact295may be formed on the second gate electrode281. A gate voltage may be applied to the second gate electrode281through the second gate contact295. The first gate contact195and the second gate contact295may include a conductive substance. For example, although the conductive substance may include at least one of polycrystalline silicon, metal silicide compound, conductive metal nitride, and metal, the disclosure is not limited thereto. The first gate insulation layer182may be formed between the first gate electrode181and the first semiconductor film140. The first gate insulation layer182may be formed on the first channel region143of the first semiconductor film140. The second gate insulation layer282may be formed between the second gate electrode281and the second semiconductor film240. The second gate insulation layer282may be formed on the second channel region243of the second semiconductor film240. That is, since the semiconductor device according to some embodiments has an FD-SOI (Fully Depleted Silicon On Insulator) structure, the first channel region143and the second channel region243may be completely depleted, and a parasitic capacitance and a leakage current may be reduced accordingly. The first gate insulation layer182and the second gate insulation layer282may include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and a high dielectric constant (high-k) material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, but is not limited to, for example, one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate. The first gate spacer183may be formed on the side walls of the first gate electrode181. The second gate spacer283may be formed on the side walls of the second gate electrode281. The first gate spacer183and the second gate spacer283may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), and combinations thereof. Also, unlike the shown example, an interface film may be interposed between the first gate insulation layer182and the first channel region143and/or between the second gate insulation layer282and the second channel region243. The interlayer insulation layer170may cover the first element separation film160, the second element separation film150, the third element separation film250, the first gate structure180, the second gate structure280, the first semiconductor film140, and the second semiconductor film240. The contacts191,193,195,197,291,293,295and297may be formed inside the interlayer insulation layer170. Although the interlayer insulation layer170may include, for example, an oxide film, the disclosure is not limited thereto. FIGS.3to8are cross-sectional views for explaining a semiconductor device according to some embodiments. For reference,FIGS.3to8may be cross-sectional views taken along A-A ofFIG.1. For convenience of explanation, points different fromFIG.2will be mainly described. Referring toFIG.3, in the semiconductor device according to some embodiments, the first semiconductor film140may have a conductive type different from the first well120, and the second semiconductor film240may have a conductive type different from the second well220. The first well120may have a second conductive type and the second well220may have a first conductive type. The first well120may be, for example, a P type, and the second well220may be, for example, an N type. Referring toFIG.4, in the semiconductor device according to some embodiments, a top surface120S of the first well120may be placed below a level of the upper surface160S1of the first element separation film160and a level of the upper surface150S1of the second element separation film150. The top surface120S of the first well120may be exposed by the first element separation region161and the second element separation film150. That is, the first well120may not include the second portion122ofFIG.2. A top surface220S of the second well220may be placed below a level of the upper surface250S1of the third element separation film250and a level of the upper surface160S1of the first element separation film160. The top surface220S of the second well220may be exposed by the third element separation film250and the third element separation region163. That is, the second well220may not include the fourth portion222ofFIG.2. Referring toFIG.5, the first element separation film160may penetrate the first buried insulation layer110. The first element separation film160may extend into the substrate100. The lower surface160S2of the first element separation film160may be placed inside the substrate100. Referring toFIG.6, the second element separation film150may penetrate the second buried insulation layer130. The second element separation film150may extend into the first well120. The lower surface150S2of the second element separation film150may be placed inside the first portion121of the first well120. The third element separation film250may penetrate the third buried insulation layer230. The third element separation film250may extend into the second well220. The lower surface250S2of the third element separation film250may be placed inside the fourth portion222of the second well220. Referring toFIG.7, the second portion122of the first well120may penetrate the second buried insulation layer130. At least a part of the side wall of the second portion122of the first well120may be in contact with the second buried insulation layer130. The fourth portion222of the second well220may penetrate the third buried insulation layer230. At least a part of the side wall of the fourth portion222of the second well220may be in contact with the third buried insulation layer230. This may be attributed to a position at which the first element separation film160, the second element separation film150and the third element separation film250are formed and/or a position at which the second portion122of the first well and the fourth portion222of the second well220are formed. Referring toFIG.8, in some embodiments, the second portion122of the first well120may penetrate the second buried insulation layer130and the first semiconductor film140. At least a part of the side wall of the second portion122of the first well120may be in contact with the second buried insulation layer130and the first semiconductor film140. The fourth portion222of the second well220may penetrate the third buried insulation layer230and the second semiconductor film240. At least a part of the side wall of the fourth portion222of the second well220may be in contact with the third buried insulation layer230and the second semiconductor film240. This may be attributed to a position at which the first element separation film160, the second element separation film150and the third element separation film250are formed and/or a position at which the second portion122of the first well and the fourth portion222of the second well220are formed. FIG.9is a conceptual plan view for explaining a semiconductor device, according to some embodiments. For convenience of explanation, points different from those ofFIG.1will be mainly described. For reference,FIGS.2to8are cross-sectional views taken along A-A ofFIG.9. Referring toFIG.9, a semiconductor device according to some embodiments may include a plurality of gate structures180,280,380,480,580and680. The first, third and fifth gate structures180,380and580may be placed on the first well120, and the second, fourth and sixth gate structures280,480and680may be placed on the second well220. The first element separation film160may define the first well120and the second well220. The first well120and the second well220may be separated by the first element separation film160. The first well120and the second well220may extend in the third direction DR3. The second element separation film150may be placed on the first portion121of the first well120. The second element separation film150may define the first, third and fifth gate structures180,380and580. The first, third and fifth gate structures180,380and580may be placed on the first portion121of the first well120. The first, third and fifth gate structures180,380and580may be separated by the second element separation film150. The first, third and fifth gate structures180,380and580may share the first well120and the first well contact191. The first, third and fifth gate structures180,380and580may share the first well120as a common body region. When a body bias voltage is applied to the first well120through the first well contact191, the first, third and fifth gate structures180,380and580have may have a common body bias. That is, the first, third and fifth transistors configured by the first, third and fifth gate structures180,380and580may have the same threshold voltage. The third element separation film250may be placed on the third portion221of the second well220. The third element separation film250may define the second, fourth and sixth gate structures280,480and680. The second, fourth and sixth gate structures280,480and680may be placed on the third portion221of the second well220. The second, fourth and sixth gate structures280,480and680may be separated by the third element separation film250. The second, fourth and sixth gate structures280,480and680may share the second well220and the second well contact291. The second, fourth and sixth gate structures280,480and680may share the second well220as a common body region. When a body bias voltage is applied to the second well220through the second well contact291, the second, fourth and sixth gate structures280,480and680may have a common body bias. That is, the second, fourth and sixth transistors configured by the second, fourth and sixth gate structures280,480and680may have the same threshold voltage. Therefore, in the semiconductor device according to some embodiments, transistors having the same threshold voltage may be placed on the single well to share the well as a common body region, and the body bias voltage may be applied to the transistors through the single well contact. Therefore, the area of the semiconductor device according to some embodiments may decrease compared to the semiconductor device in which a well contact is formed for each transistor. FIG.10is a conceptual plan view for explaining a semiconductor device, according to some embodiments.FIG.11is a cross-sectional view taken along the line B-B ofFIG.10. For convenience of explanation, points different from those ofFIGS.1and2will be mainly described. Referring toFIGS.10and11, the semiconductor device according to some embodiments may include a substrate100, a first buried insulation layer710, a first well720, a third buried insulation layer730, a first semiconductor film740, a first element separation film760, a second element separation film750, a first gate structure780, a second buried insulation layer810, a second well820, a second semiconductor film840, a second gate structure880, and contacts791,793,795,797,893,895and897. The first buried insulation layer710, the first well720, the third buried insulation layer730, the first semiconductor film740, the first element separation film760, the second element separation film750, the interlayer insulation layer770, the first gate structure780, the first well contact791, the first source contact793, the first gate contact795, and the first drain contact797may be substantially the same as each of the first buried insulation layer110, the first well120, the second buried insulation layer130, the first semiconductor film140, the first element separation film160, the second element separation film150, the interlayer insulation film170, the first gate structure180, the first well contact191, the first source contact193, the first gate contact195and the first drain contact197shown inFIGS.1and2. The second buried insulation layer810and the second semiconductor film840may be sequentially placed on the substrate100. The second buried insulation layer810and the second semiconductor film840are placed in the second active region defined by the second element separation region762and the third element separation region763. The second buried insulation layer810and the second semiconductor film840may be separated from the first buried insulation layer710, the first well720, the third buried insulation layer730and the first semiconductor film740, by the second element separation region762. The first element separation film760may be in contact with the substrate100. A bottom surface760S2of the first element separation film760may be placed substantially on the same plane as an upper surface of the substrate100. Unlike the shown example, the bottom surface760S2of the first element separation film760may also be placed inside the substrate100. A lower surface750S2of the second element separation film750may be placed substantially on the same plane as the top surface of the third buried insulation layer730, and may also be placed inside the third buried insulation layer730. The lower surface750S2of the second element separation film750may be placed above a level of the lower surface760S2of the first element separation film760. The second semiconductor film840may include a second source region841, a second drain region842and a second channel region843. The second source region841and the second drain region842may function as a source and a drain of the second gate structure880, respectively. A source voltage may be applied to the second source region841through the second source contact893. A drain voltage may be applied to the second drain region842through the second drain contact897. Bottom surfaces of the second source region841and the second drain region842may be, for example, placed below a level of the bottom surfaces of the first source region141and the first drain region142. The second gate structure880may be placed on the second semiconductor film840. The second gate structure880may include a second gate electrode881, a second gate insulation layer882and a second gate spacer883. The second gate structure880may form a second transistor. The second gate electrode881may be formed to fill a gate trench defined by the second gate spacer883and the second gate insulation layer882. The second gate electrode881and the second gate contact895may include a conductive substance. A gate voltage may be applied to the second gate electrode881through the second gate contact895. The second gate insulation layer882may be formed between the second gate electrode881and the second semiconductor film840. The second gate insulation layer882may be formed on the second channel region843of the second semiconductor film840. The second gate spacer883may be formed on the side wall of the second gate electrode281. An interface film is interposed between the first gate insulation layer782and the first channel region743and/or between the second gate insulation layer882and the second channel region843. The first gate structure780and the first semiconductor film740may form the first transistor, and the second gate structure880and the second semiconductor film840may form the second transistor. That is, the semiconductor device according to some embodiments may include a first transistor having an FD-SOI (Fully Depleted Silicon On Insulator) structure, and a second transistor having a PD-SOI (Partially Depleted Silicon On Insulator) structure. The first transistor and the second transistor are electrically insulated by the first element separation film760and may operate independently of each other. According to an embodiment, the semiconductor device shown inFIG.10may be extended to the third direction DR3to take a form similar to the semiconductor device shown inFIG.9, thereby including two additional first semiconductor films740and two additional first gate structures780in the third direction DR3, and two additional second semiconductor films840and two additional second gate structures880in the third direction DR3. In this embodiment, the bottom surfaces of the second source region841and the second drain region842in any of the second semiconductor film840may be disposed below a level of the bottom surfaces of the first source region741and the first drain region742in any of the first semiconductor film740. FIGS.12to17are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device in reference toFIGS.1and2, according to some embodiments. For reference,FIGS.12to17are cross-sectional views taken along A-A ofFIG.17. The reference numbers used inFIGS.1and2apply to the description of the method shown inFIGS.12to17. Referring toFIG.12, the substrate100on which the first buried insulation layer110, the first well120, the second well220, the second buried insulation layer130, the first semiconductor film140and the second semiconductor film240are each formed may be provided. Each of the first well120and the second well220may be a first portion121of the first well120and a third portion221of the second well220, which will be described later. The first well120, the second well220, the first semiconductor film140, and the second semiconductor film240may be formed by doping the substrate100with impurities, respectively. For example, the substrate100may be doped with a substance of the first conductive type and a substance of the second conductive type to form each of the first well120and the second well220. Further, the substrate100may be doped with the substance of the first conductive type and the substance of the second conductive type to form each of the first semiconductor film140and the second semiconductor film240. Referring toFIG.13, a first trench t1may be formed. The first trench t1may penetrate the first semiconductor film140, the second buried insulation layer130and the first well120. The first trench t1may penetrate the second semiconductor film240, the second buried insulation layer130and the second well220. An upper surface of the first buried insulation layer110may be exposed by the first trench t1. Alternatively, the first trench t1may etch the first semiconductor film140and the second buried insulation layer130, and the second semiconductor film240and the third buried insulation layer230to expose the upper surface of the well120and the upper surface of the second well220. Alternatively, the first trench t1may be formed such that a bottom surface is placed inside the first well120and the second well220. Referring toFIG.14, the second portion122may fill the first trench t1that penetrates the first semiconductor film140, the second buried insulation layer130, and the first portion121. Accordingly, the first well120which includes the first portion121extending along the upper surface of the first buried insulation layer110and the second portion122for filling the first trench t1may be formed. The fourth portion222may fill the first trench t1that penetrates the second semiconductor film240, the second buried insulation layer130and the third portion221. Accordingly, the second well220which includes the third portion221extending along the upper surface of the second buried insulation layer130and the fourth portion222for filling the first trench t1may be formed. The second portion122of the first well120and the fourth portion222of the second well220may be formed by doping the substrate with impurities, respectively. For example, the substrate100may be doped with the substance of the first conductive type and the substance of the second conductive type to form each of the second portion122and the fourth portion222. Referring toFIG.15, a second trench t2may be formed. The second trench t2may be formed between the first semiconductor film140and the second semiconductor film240. Further, the second trench t2may be formed, for example, on both sides of the second portion122and both sides of the fourth portion222. The second trench t2may be formed by etching up to the second buried insulation layer130and the third buried insulation layer230. The second trench t2may expose the upper surface of the first portion121of the first well120and the upper surface of the third portion221of the second well220. Accordingly, the second buried insulation layer130and the third buried insulation layer230may be separated, and the first semiconductor film140and the second semiconductor film240may be separated. Further, the first semiconductor film140and the second buried insulation layer130may be separated from the second portion122of the first well120, and the second semiconductor film240and the third buried insulation layer230may be separated from the fourth portion222of the second well220. Alternatively, the second trench t2may be formed such that a bottom surface is placed on the upper surface of the second buried insulation layer130and the upper surface of the third buried insulation layer230. Alternatively, the second trench t2may be formed such that the bottom surface is placed inside the second buried insulation layer130and the third buried insulation layer230. Referring toFIG.16, a third trench t3may be formed by further etching the first portion121of the first well120and the fourth portion222of the second well220on a part of the second trench t2. The third trench t3may expose the upper surface of the first buried insulation layer110. Accordingly, the first portion121of the first well120may be separated from the third portion221of the second well220, and the second portion122of the first well120and the fourth portion222of the second well220may be defined. Alternatively, the third trench t3may be formed such that the bottom surface is placed inside the first buried insulation layer110. Alternatively, the third trench t3may expose the upper surface of the substrate100by etching the first buried insulation layer110, and the bottom surface may be placed inside the substrate100by etching a part of the substrate100. Referring toFIG.17, the first element separation film160may fill the third trench t3. The second element separation film150may fill the second trench t2on the first well120. The third element separation film250may fill the second trench t2on the second well220. Accordingly, the upper surface160S1of the first element separation film160, the upper surface150S1of the third element separation film250, and the upper surface250S1of the third element separation film250may be placed substantially on the same plane as the upper surface122S of the second portion122of the first well120and the upper surface222S of the fourth portion222of the second well220. Further, the lower surface160S2of the first element separation film160may be placed below the lower surface150S2of the second element separation film150and the lower surface250S2of the third element separation film250. This may be due to the formation of the second trench t2and the third trench t3. Referring toFIG.2, the first source region141and the first drain region142may be formed inside the first semiconductor film140, and the second source region241and the second drain region242may be formed inside the second semiconductor film240. The first source region141, the first drain region142, the second source region241and the second drain region242may be formed by doping each of the first semiconductor film140and the second semiconductor film240with impurities or by an epitaxial growth. The first gate structure180may be formed on the first semiconductor film140, and the second gate structure280may be formed on the second semiconductor film240. By forming an insulation layer and a conductive film on the first semiconductor film140and the second semiconductor film240, and patterning them, the first and second gate insulation layers182and282and the first and second gate electrodes181and281may be formed. The first and second gate spacers183and183may be formed on the side walls of the first and second gate electrodes181and281. Although the first and second gate structures180and280have been described as being formed by the gate first method, the disclosure is not limited thereto, and the first and second gate structures180and280may also be formed by the gate last method. The interlayer insulation layer170may be formed, and the interlayer insulation layer170may be etched to form a contact hole. The contact hole may be filled with conductive substance to form contacts191,193,195,197,293,295and297. FIGS.18to21are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device in reference toFIGS.1,2and12-17, according to some embodiments. For reference,FIGS.18to23are cross-sectional views taken along A-A of FIG.1. The reference numbers used inFIGS.1,2and12-17apply to the description of the method shown inFIGS.18to21. Referring toFIG.18, a first substrate10and a second substrate20may be provided. The first substrate10may include the substrate100, and a first insulation layer102placed on the substrate100. The second substrate20may include a first additional substrate125, and a second insulation layer104placed on the first additional substrate125. The first substrate10and the second substrate20may be an SOI (Silicon on Insulator) substrate in which an insulation layer is formed on a silicon substrate. The second substrate20may be attached onto the first substrate10such that the second insulation layer104faces the first insulation layer102. Referring toFIG.19, the first insulation layer102and the second insulation layer104may be attached to form the first buried insulation layer110. The substrate100and the first additional substrate125may be spaced apart from each other by the first buried insulation layer110. Referring toFIG.20, a third substrate30may be provided. The third substrate30may include a second additional substrate145, and the second buried insulation layer130placed on the second additional substrate145. The third substrate30may be an SOI (Silicon on Insulator) substrate in which an insulation layer is formed on a silicon substrate. The third substrate30may be attached onto the first additional substrate125such that the second buried insulation layer130faces the first additional substrate125. Referring toFIG.21, the first additional substrate125and the second buried insulation layer130may be attached. The first additional substrate125and the second additional substrate145may be spaced apart from each other by the second buried insulation layer130. Therefore, the substrate100may include two buried insulation layers110and130. Referring back toFIG.12, the first additional substrate125may be doped with impurities to form the first well120and the second well220, and the second additional substrate145may be doped with impurities form the first semiconductor film140and the second semiconductor film240. FIGS.22and23are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device in reference toFIGS.1,2and12-21, according to some embodiments. For reference,FIGS.22and23are cross-sectional views taken along A-A ofFIG.1. The reference numbers used inFIGS.1,2and12-21apply to the description of the method shown inFIGS.22and23. Referring toFIG.22, the substrate100spaced apart from the second additional substrate145by the second buried insulation layer130may be provided. The substrate100may be an SOI substrate in which an insulation layer is formed on a silicon substrate. An oxygen implant process may be performed on the second additional substrate145. Referring toFIG.23, oxygen may be doped into the substrate100by the oxygen ion implanting process to form a pre-insulating layer115. The first additional substrate125may be separated from the substrate100by the pre-insulating layer115. An annealing (heat) process may be performed on the second additional substrate145. Although any one of low temperature soak annealing, flash lamp annealing, laser annealing and spike annealing may be used as the annealing process, the disclosure is not limited thereto. Referring back toFIG.12, oxygen in the pre-insulating layer115is diffused by the annealing process, and the first buried insulation layer110may be formed. The first additional substrate125may be doped with impurities to form the first well120and the second well220, and the second additional substrate145may be doped with impurities to form the first semiconductor film140and the second semiconductor film240. FIGS.24to28are intermediate stage diagrams for explaining the method of manufacturing the semiconductor device in reference toFIGS.10and11, according to some embodiments. For reference,FIGS.24to28are cross-sectional views taken along B-B ofFIG.10. The reference numbers used inFIGS.10and11apply to the description of the method shown inFIGS.24to28. Referring toFIG.24, the substrate100on which the first buried insulation layer710, the first well720, the third buried insulation layer730and the first semiconductor film740are sequentially formed may be provided. The first well720may be the first portion721of the first well720to be described below. A fourth trench t4and a fifth trench t5may be formed. The fourth trench t4and the fifth trench t5may penetrate the first semiconductor film740, the third buried insulation layer730, and the first well720. The upper surface of the first buried insulation layer710may be exposed by the fourth trench t4and the fifth trench t5. Alternatively, the fourth trench t4and/or the fifth trench t5may etch the first semiconductor film740and the third buried insulation layer730to expose the top surface of the first well720. Alternatively, the fourth trench t4and/or the fifth trench t5may be formed such that the bottom surfaces are placed inside the first well720. For example, the width of the fourth trench t4in the second direction DR2may be smaller than the width of the fifth trench t5. The region in which the fifth trench t5is formed may be a region for forming a second transistor to be described below. The first well720and the first semiconductor film740may be formed by doping the substrate100with impurities, respectively. Referring toFIG.25, the second portion722may fill the fourth trench t4. Accordingly, the first well720which includes the first portion721extending along the first buried insulation layer710and the second portion722for filling the fourth trench t4may be formed. The first semiconductor film740may fill the fifth trench t5. The first semiconductor film740may be formed by doping the substrate100with impurities. Referring toFIG.26, a sixth trench t6may be formed. The sixth trench t6may be formed between the first semiconductor film740, the third buried insulation layer730and the second semiconductor film840. Further, the sixth trench t6may be formed, for example, on both sides of the second portion722of the first well720. The sixth trench t6may be formed by etching up to the third buried insulation layer730. The sixth trench t6may expose the upper surface of the first portion721of the first well720. Accordingly, the third buried insulation layer730and the first semiconductor film740may be separated from the second semiconductor film840. Further, the first semiconductor film740and the third buried insulation layer730may be separated from the second portion722of the first well720. Alternatively, the sixth trench t6may be formed such that the bottom surface is placed on the upper surface of the third buried insulation layer730. Alternatively, the sixth trench t6may be formed such that the bottom surface is placed inside the third buried insulation layer730. Referring toFIG.27, a seventh trench t7may be formed by further etching the first portion721of the first well720on a part of the sixth trench t6. The seventh trench t7may expose the upper surface of the substrate100. Accordingly, the first portion721of the first well720may be separated from the second semiconductor film840, and the first buried insulation layer710may be separated from the second buried insulation layer810. A second portion722of the first well720may be defined. Alternatively, the seventh trench t7may be formed such that the bottom surface is placed on the upper surface of the first buried insulation layer710, and the first buried insulation layer710and the second buried insulation layer810may not be separated. Alternatively, the seventh trench t7may be formed such that the bottom surface is placed inside the first buried insulation layer710and the second buried insulation layer810. Referring toFIG.28along withFIG.11, the first element separation film760may fill the seventh trench t7. The second element separation film750may fill the sixth trench t6. Accordingly, the upper surface760S1of the first element separation film760and the upper surface750S1of the second element separation film750may be placed substantially on the same plane as an upper surface722S of the second portion722of the first well720. Further, the lower surface760S2of the first element separation film760may be placed below a level of the lower surface750S2of the second element separation film750. This may be due to the formation of the sixth trench t6and the seventh trench t7. Referring back toFIG.11, the first source region741and the first drain region742may be formed inside the first semiconductor film740, and the second source region841and the second drain region842may be formed inside the second semiconductor film840. The first source region741, the first drain region742, the second source region841and the second drain region842may be formed by doping each of the first semiconductor film740and the second semiconductor film840with impurities or by an epitaxial growth. The first gate structure780may be formed on the first semiconductor film740, and the second gate structure880may be formed on the second semiconductor film840. By forming an insulation layer and a conductive film on the first semiconductor film740and the second semiconductor film840, and patterning them, the first and second gate insulation layers782and882, and the first and second gate electrodes781and881may be formed. The first and second gate spacers783and883may be formed on the side walls of the first and second gate electrodes781and881. Although the first and second gate structures780and880have been described as being formed by the gate first method, the disclosure is not limited thereto, and the first and second gate structures780and880may also be formed by the gate last method. The interlayer insulation layer770is formed, and the interlayer insulation layer770is etched to form a contact hole. Contact holes may be filled with conductive substance to form contacts791,793,795,797,893,895and897. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the above embodiments without substantially departing from the principles of the disclosure. Therefore, the above embodiments of the disclosure are used in a generic and descriptive sense only and not for purposes of limitation. | 54,862 |
11942481 | DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, examples of methods of manufacturing polycrystalline silicon layers, thin film transistor substrates and methods of manufacturing the thin film transistor substrates, and display devices and methods of manufacturing the display devices will be explained in detail with reference to the accompanying drawings. Specific examples are illustrated in the drawings and described in detail in the specification. However, the disclosed systems and devices can be modified in various manners and take various forms different from the detailed drawings but consistent with this disclosure. Thus, it should be understood that this disclosure is not intended to be limited to the disclosed particular forms. Further, it should be understood that the disclosure is intended to cover all modifications, equivalents, and substitutions within the spirit and technical range of the disclosure. It should further be understood that in the this application, the terms “include”, “have”, or the like are used to specify that there is a feature, a number, a step, an operation, an element, a part, or a combination thereof described in the specification, but do not exclude a possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof in advance. When a layer, film, region, substrate, or area, is referred to as being “on” another layer, film, region, substrate, or area, it may be directly on the other film, region, substrate, or area, or intervening films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly on” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further when a layer, film, region, substrate, or area, is referred to as being “below” another layer, film, region, substrate, or area, it may be directly below the other layer, film, region, substrate, or area, or intervening layers, films, regions, substrates, or areas, may be present therebetween. Conversely, when a layer, film, region, substrate, or area, is referred to as being “directly below” another layer, film, region, substrate, or area, intervening layers, films, regions, substrates, or areas, may be absent therebetween. Further, “over” or “on” may include positioning on or below an object and does not necessarily imply a direction based upon gravity. Still further, the spatially relative terms “below,” “beneath,” “lower,” “above,” “upper,” or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, further to the orientation depicted in the drawings. In varying examples, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations. Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to another element, or “electrically connected” to another element with one or more intervening elements interposed therebetween. It will be further understood that when the terms “comprises,” “comprising,” “includes” and/or “including” are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof. It is further to be understood that, although the terms “first,” “second,” “third,” or the like may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used to distinguish one element from another element or for the convenience of description and explanation thereof. In varying examples, when “a first element” is discussed in the description, it may be termed “a second element” or “a third element,” and “a second element” and “a third element” may be termed in a similar manner without departing from the teachings herein. In varying examples, a first color filter may be any one of a red, green, or blue color filter. A second color filter may be any one of a red, green, or blue color filter. A third color filter may be any one of a red, green, or blue color filter. First and second with respect to the light blocking members may be used interchangeably in the specification. Further, the terms “about” or “approximately” as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). In varying examples, “about” may mean within one or more standard deviations, or within ±5%, 10%, 20%, 30%, or 80% of a stated value. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification. Further, the phrase “in a plan view” refers to when an object portion is viewed from above, and the phrase “in a cross-sectional view” refers to when a cross-section taken by vertically cutting an object portion is viewed from the side. It is to be appreciated to those skilled in the art in light of this disclosure that, while the various processes/operations of various methods discussed below may be shown according to one or more particular orders for ease of explanation, that certain processes/operations may be performed in different orders or performed in a parallel fashion in varying method examples. It is to be further appreciated that certain processes/operations may be omitted in various examples of disclosed methods. Accordingly, a particular order of processes/operations should be determined by the language of the claims rather than inferred by the specification. Turning to the drawings,FIG.1is a flowchart to explain an embodiment of a method of manufacturing a polycrystalline silicon layer.FIGS.2,3,4, and5are schematic diagrams to explain an embodiment of a method of manufacturing a polycrystalline silicon layer. Referring toFIGS.1and2, an amorphous silicon layer132may be formed on a substrate110(S110). The substrate110may be an insulating substrate including glass, quartz, ceramic, etc. The substrate110may be an insulating flexible substrate including plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polycarbonate (PC), polyarylate, polyether sulfone (PES), polyimide (PI), etc. A buffer layer120may be formed on the substrate110. The buffer layer120may provide a planar or planarized surface above the substrate110. The buffer layer120may prevent impurities from permeating through the substrate110. For example, the buffer layer120may be formed of silicon oxide, silicon nitride, etc., or a combination thereof. The amorphous silicon layer132may be formed on the buffer layer120. The amorphous silicon layer132may be formed by methods such as low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, etc., or a combination thereof. A thickness of the amorphous silicon layer132may be in a range of about 370 Å to about 500 Å. If the thickness of the amorphous silicon layer132is less than about 370 Å, the hysteresis characteristic of a thin film transistor including a polycrystalline silicon layer that is formed by crystallizing the amorphous silicon layer132may decrease. A natural oxide layer NOL may be formed on the amorphous silicon layer132. The natural oxide layer NOL may be formed when an upper portion of the amorphous silicon layer132is exposed to air. When the natural oxide layer NOL remains on the amorphous silicon layer132, a protrusion that has a relatively large thickness may be formed on a surface of the polycrystalline silicon layer by the natural oxide layer NOL in a subsequent process for crystallizing the amorphous silicon layer132to form the polycrystalline silicon layer. Referring toFIGS.1and3, the amorphous silicon layer132may be cleaned (S120). The amorphous silicon layer132may be cleaned, for example, using hydrofluoric acid210. The hydrofluoric acid210may be an aqueous solution in which a hydrogen fluoride (HF) dissolves. For instance, the hydrofluoric acid210may include the hydrogen fluoride in an amount of about 0.5%. The amorphous silicon layer132may be cleaned by the hydrofluoric acid210to remove the natural oxide layer NOL formed on the amorphous silicon layer132. The amorphous silicon layer132may be cleaned for about 60 seconds to about 120 seconds. If the amorphous silicon layer132is cleaned for less than about 60 seconds, the natural oxide layer NOL formed on the amorphous silicon layer132may not be sufficiently or appropriately removed, and grains of the subsequently formed polycrystalline silicon layer may not grow enough. If the amorphous silicon layer132is cleaned for greater than about 120 seconds, the amorphous silicon layer132may be affected by the hydrofluoric acid210, and grains of the subsequently formed polycrystalline silicon layer may burst. Referring toFIGS.1and4, the amorphous silicon layer132may be rinsed (S130). The amorphous silicon layer132may be rinsed, for example, using hydrogenated deionized water220. A hydrogen concentration of the hydrogenated deionized water220may be about 1.0 ppm. The hydrogenated deionized water220may be supplied to the amorphous silicon layer132via a spray230. In an embodiment, the substrate110disposed under the spray230may move, and the spray230may be fixed. The hydrofluoric acid210that remains on the amorphous silicon layer132may be removed by rinsing the amorphous silicon layer132with the hydrogenated deionized water220. If the amorphous silicon layer132is rinsed with dehydrogenated deionized water, oxygen in the deionized water may remain on the amorphous silicon layer132, which may cause or result in a visible circular defect due to the oxygen after a crystallization process. However, in this and other possible examples, the amorphous silicon layer132may be rinsed with the hydrogenated deionized water220thereby preventing such circular defect. Referring toFIGS.1and5, a polycrystalline silicon layer134may be formed (S140). The polycrystalline silicon layer134may be formed by irradiating the amorphous silicon layer132with a laser beam240. A laser250may generate the laser beam240to irradiate the amorphous silicon layer132. The laser250may generate the laser beam240intermittently. The laser250may be an excimer laser for generating the laser beam240which may have a relatively short wavelength, relatively high power, and/or relatively high efficiency. The excimer laser may include, for example, an inert gas, an inert gas halide, a mercury halide, an inert gas acid compound, a polyatomic excimer, or a combination thereof. Examples of the inert gas are Ar2, Kr2, and Xe2. Examples of the inert gas halide are ArF, ArCl, KrF, KrCl, XeF, and XeCl. Examples of the mercury halide are HgCl, HgBr, and HgI. Examples of the inert gas acid compound are ArO, KrO, and XeO. Examples of the polyatomic excimer are Kr2F, and Xe2F. The amorphous silicon layer132may be crystallized into the polycrystalline silicon layer134by irradiating the amorphous silicon layer132with the laser beam240emitted from the laser250. The substrate110may move along direction D1as shown inFIG.5. In other embodiments, a laser may move along a substrate to irradiate a laser beam on an amorphous silicon layer disposed on the substrate. A wavelength of the laser beam240irradiated to the amorphous silicon layer132may be about 308 nm. The laser250may irradiate the amorphous silicon layer132with the laser beam240having an energy density in a range of about 440 mJ/cm2to about 490 mJ/cm2. If the energy density of the laser beam240is less than about 440 mJ/cm2, a grain size of the polycrystalline silicon layer134may be relatively small. If the energy density of the laser beam240is greater than about 490 mJ/cm2, the amorphous silicon layer132may be completely liquidated by the laser beam240so that crystal seeds for crystallization of silicon may not be formed. A scan pitch of the laser beam240may be about 10 μm or less. When the scan pitch of the laser beam240is about 10 μm or less, the polycrystalline silicon layer134having a relatively large grain size may be formed. As shown inFIG.5, a region in which the crystallization process is performed using the laser beam240may be converted into polycrystalline silicon from amorphous silicon so that the polycrystalline silicon layer134may be formed from the amorphous silicon layer132. FIGS.6and7are schematic diagrams illustrating a polycrystalline silicon layer according to an embodiment. The polycrystalline silicon layer134shown inFIGS.6and7may be formed by the manufacturing method, for example, described with reference toFIGS.1to5. Referring toFIGS.5,6, and7, one or more grains134amay be formed in the polycrystalline silicon layer134. When the laser beam240is irradiated on the amorphous silicon layer132in a solid state, the amorphous silicon layer132may absorb heat and change to be in a liquid state. The amorphous silicon layer132may release the heat and change to be in the solid state again. Through and by the irradiation of the laser beam240, crystal may grow from a crystal seed to form a grain134a. In instances where there is a difference in cooling rate in the amorphous silicon layer132in the course of changing from the liquid state to the solid state, since the grain134agrows from a region having a relatively higher cooling rate toward a region having a relatively slower cooling rate, a grain boundary134bmay be formed in the region having the relatively slower cooling rate. When the amorphous silicon layer132is irradiated with the laser beam240having the wavelength of about 308 nm and the energy density of about 440 mJ/cm2to about 490 mJ/cm2with the scan pitch of about 10 μm or less as described above, an average value of the grain sizes may be in a range of about 400 nm to about 800 nm. Here, a grain size of a grain134amay mean a width of the grain134ain a plan view. The grain size may be a distance between adjacent grain boundaries134b. The sizes of the grains134aof the polycrystalline silicon layer134may be determined by a wavelength, a scan pitch, an energy density, etc., or a combination thereof of the laser beam240irradiated from the laser250. For example, the larger the wavelength of the laser beam240, the smaller the scan pitch of the laser beam240, and the larger the energy density of the laser beam240, the larger the sizes of the grains134aof the polycrystalline silicon layer134. In a conventional method of manufacturing a polycrystalline silicon layer, an amorphous silicon layer may be irradiated with a laser beam having a wavelength of about 308 nm and a relatively small energy density (e.g., about 410 mJ/cm2to about 440 mJ/cm2) with a relatively large scan pitch (e.g., about 15 μm to about 25 μm), and a polycrystalline silicon layer having a relatively small grain size (e.g., an average value of the grain sizes is less than about 300 nm) may be formed. However, in this and other possible embodiments of the invention, the amorphous silicon layer132may be irradiated with the laser beam240having a wavelength of about 308 nm and a relatively large energy density (e.g., about 440 mJ/cm2to about 490 mJ/cm2) with a relatively small scan pitch (e.g., about 10 μm or less), and the polycrystalline silicon layer134having a relatively large grain size (e.g., an average value of grain sizes is in a range of about 400 nm to about 800 nm) may be formed. Each grain134aof the polycrystalline silicon layer134may include one or more crystal planes. The crystal planes of each grain134amay include crystal planes with different directions. A ratio of a (111) direction crystal plane to total crystal planes of the polycrystalline silicon layer134may be greater than a ratio of a (001) direction crystal plane to the total crystal planes of the polycrystalline silicon layer134. In a conventional method of manufacturing a polycrystalline silicon layer such that an amorphous silicon layer is irradiated with a laser beam having a relatively small energy density (e.g., about 410 mJ/cm2to about 440 mJ/cm2), a ratio of a (111) direction crystal plane to total crystal planes may be less than a ratio of a (001) direction crystal plane to the total crystal planes. However, in the method of manufacturing the polycrystalline silicon layer according to this and other possible embodiments, when the amorphous silicon layer132is irradiated with the laser beam240having a relatively large energy density (e.g., about 440 mJ/cm2to about 490 mJ/cm2), a ratio of a (111) direction crystal plane to total crystal planes may be greater than a ratio of a (001) direction crystal plane to the total crystal planes. A value obtained by dividing a sum of a ratio of a (001) direction crystal plane to the total crystal planes and a ratio of a (101) direction crystal plane to the total crystal planes by a ratio of a (111) direction crystal plane to the total crystal planes may be about 0.7 or less. Here, “(111), (001), and (101)” represent direction indices or Miller indices. A protrusion134cmay be formed at a grain boundary134bon a surface of the polycrystalline silicon layer134which is formed through the above-described crystallization process. The amorphous silicon layer132melted by the laser beam240may be re-crystallized to form the grains134aof the polycrystalline silicon layer134. The protrusions134cmay be formed at the grain boundaries134b. Sizes of the grains134aand a number of the protrusions134cformed at the grain boundaries134bmay be inversely proportional. For example, the larger the sizes of the grains134a, the smaller the number of the protrusions134c. As the sizes of the grains134aof the polycrystalline silicon layer134may be relatively larger, the number of the protrusions134cincluded in a unit area may be relatively smaller. The protrusions134cmay project upward from the surface of the polycrystalline silicon layer134, and may have a sharp-pointed tip. The protrusions134cmay each have a thickness TH corresponding to a distance from the surface of the polycrystalline silicon layer134to the tip of each protrusion134c. For example, the thickness TH of each protrusion may be a distance between the top of a sharp-pointed tip of the protrusion and a lowest level of the surface of the polycrystalline silicon layer134in a grain adjacent to the protrusion. In each grain, the lowest level of the surface of the polycrystalline silicon layer134may correspond to a surface level at or around a center of a grain. The surface of the polycrystalline silicon layer134may be rough. A root-mean-square (RMS) value of a surface roughness of the polycrystalline silicon layer134may be about 4 nm or less. An RMS value of the thicknesses of the protrusions134cformed on the surface of the polycrystalline silicon layer134may be about 4 nm or less. The cleaning process (S120) using the hydrofluoric acid210and the rinsing process (S130) using the hydrogenated deionized water220may be performed before the crystallization process (S140). The crystallization process (S140) may be performed irradiating the amorphous silicon layer132with the laser beam having a relatively large energy density with a relatively small scan pitch. Therefore, the polycrystalline silicon layer134having a relatively large grain size and a relatively small surface roughness may be formed. Hereinbefore, the cleaning process (S120), the rinsing process (S130), and the crystallization process (S140) for forming the polycrystalline silicon layer134are described. However, it is possible to add processes and/or operations for forming the polycrystalline silicon layer134in addition to the above processes and/or operations, or omit some of the above processes and/or operations. It is further possible that different processes and/or operations may be performed at different times or at a same time period, or that a same process and/or operation be performed at different or multiple times. For instance, in varying examples, the crystallizing process (S140) may be performed two or more times. Hereinafter, a thin film transistor substrate and a method of manufacturing the thin film transistor substrate will be described with reference toFIGS.8to15.FIG.8is a schematic cross-sectional view illustrating a thin film transistor substrate according to an embodiment. Referring toFIG.8, a thin film transistor substrate100may include a substrate110and a thin film transistor TR disposed on the substrate110. The thin film transistor TR may include an active pattern AP, a gate insulation layer140, a gate electrode GE, a source electrode SE, and a drain electrode DE which are sequentially stacked. The thin film transistor TR may perform a switching operation of flowing a current through the active pattern AP based on a signal applied to the gate electrode GE. The thin film transistor TR may have a top gate structure in which the gate electrode GE is positioned above the active pattern AP. However, this and other particular examples are not limited thereto, and the thin film transistor TR may have a bottom gate structure in which the gate electrode is positioned below the active pattern AP. FIGS.9,10,11,12,13,14, and15are schematic cross-sectional views to explain a method of manufacturing a thin film transistor substrate, for example, the thin film transistor substrate inFIG.8. In the below description of a method of manufacturing a thin film transistor substrate, it will be avoided to repeat the same or similar description provided above for the method of manufacturing the polycrystalline silicon layer. Referring toFIG.9, an amorphous silicon layer132may be formed on a substrate110. The substrate110may be an insulating substrate including glass, quartz, ceramic, etc., or a combination thereof. The substrate110may be an insulating flexible substrate including plastic such as PET, PEN, PEEK, PC, polyarylate, PES, PI, etc., or a combination thereof. A barrier layer that includes silicon oxide, silicon nitride, amorphous silicon, etc., or a combination thereof may be additionally formed on the substrate110. A buffer layer120may be formed on the substrate110. The buffer layer120may provide a planar or planarized surface above the substrate110. The buffer layer120may prevent impurities from permeating through the substrate110. The amorphous silicon layer132may be formed on the buffer layer120. The amorphous silicon layer132may be formed by methods such as LPCVD, APCVD, PECVD, sputtering, vacuum evaporation, etc. or a combination thereof. A natural oxide layer may be formed on the amorphous silicon layer132. The amorphous silicon layer132may be cleaned using hydrofluoric acid. The hydrofluoric acid may include a hydrogen fluoride in an amount of about 0.5%. The amorphous silicon layer132may be cleaned by the hydrofluoric acid to remove the natural oxide layer formed on the amorphous silicon layer132. The amorphous silicon layer132may be cleaned for about 60 seconds to about 120 seconds. The amorphous silicon layer132may be rinsed using hydrogenated deionized water. A hydrogen concentration of the hydrogenated deionized water may be about 1.0 ppm. The hydrofluoric acid that remains on the amorphous silicon layer132may be removed by rinsing the amorphous silicon layer132with the hydrogenated deionized water. Referring toFIG.10, the amorphous silicon layer132may be crystallized to form a polycrystalline silicon layer134. The polycrystalline silicon layer134may be formed by irradiating the amorphous silicon layer132with a laser beam. A laser may generate the laser beam to irradiate the amorphous silicon layer132. The laser may intermittently generate the laser beam. The laser may irradiate the amorphous silicon layer132with the laser beam having an energy density in a range of about 440 mJ/cm2to about 490 mJ/cm2. A wavelength of the laser beam may be about 308 nm. A scan pitch of the laser beam may be about 10 μm or less. When the laser beam is irradiated on the amorphous silicon layer132in a solid state, the amorphous silicon layer132may absorb heat and change to be in a liquid state. The amorphous silicon layer132may release the heat and change to be in the solid state again. Through and by the irradiation of the laser beam240, crystal may grow from a crystal seed to form a grain. In instances where there is a difference in cooling rate in the amorphous silicon layer132in the course of changing from the liquid state to the solid state, since the grain grows from a region having a relatively higher cooling rate toward a region having a relatively slower cooling rate, a grain boundary may be formed in the region having the relatively slower cooling rate. One or more grains may be formed in the polycrystalline silicon layer134. An average value of grain sizes may in a range of about 400 nm to about 800 nm. A protrusion may be formed at a grain boundary on a surface of the polycrystalline silicon layer134which is formed through the crystallization process. The protrusion may project upward from the surface of the polycrystalline silicon layer134, and may have a sharp-pointed tip. The protrusion may have a thickness corresponding to a distance from the surface of the polycrystalline silicon layer134to the tip of the protrusion. An RMS value of a surface roughness of the polycrystalline silicon layer134may be about 4 nm or less. An RMS value of the thicknesses of the protrusions formed on the surface of the polycrystalline silicon layer134may be about 4 nm or less. Referring toFIG.11, the polycrystalline silicon layer134may be etched to form a polycrystalline silicon pattern136. The polycrystalline silicon layer134may be etched by photolithography. A photoresist pattern may be formed on the polycrystalline silicon layer134using an exposing process and a developing process, and the polycrystalline silicon layer134may be etched using the photoresist pattern as an etch-stopper. Referring toFIG.12, a gate insulation layer140may be formed on the polycrystalline silicon pattern136. The gate insulation layer140may be disposed on the buffer layer120, and may cover the polycrystalline silicon pattern136. The gate insulation layer140may be formed of silicon oxide, silicon nitride, etc. or a combination thereof. The polycrystalline silicon pattern136in which an RMS value of a surface roughness is about 4 nm or less may be formed so that the polycrystalline silicon pattern136may have a relatively small surface roughness. Accordingly, an effect to the gate insulation layer140formed on the polycrystalline silicon pattern136by the protrusions formed on the surface of the polycrystalline silicon pattern136may be minimized, and the gate insulation layer140may be relatively thin. A thickness of the gate insulation layer140may be in a range of about 30 nm to about 200 nm. Referring toFIG.13, the gate electrode GE may be formed on the gate insulation layer140. The gate electrode GE may overlap the polycrystalline silicon pattern136. The gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or an alloy thereof, and the gate electrode GE may have a single-layer structure or a multi-layer structure including different metal layers. For example, the gate electrode GE may include a triple layer of Mo, Al and Mo, a double layer of Cu and Ti, or the like. A first metal layer and a photoresist pattern that overlaps the polycrystalline silicon pattern136may be formed on the gate insulation layer140. The first metal layer may be etched using the photoresist pattern to form the gate electrode GE. Referring toFIG.14, ions may be injected into portions of the polycrystalline silicon pattern136to form an active pattern AP. The polycrystalline silicon pattern136may be partially doped with an ion injection process so that the active pattern AP including a source region SR, a channel region CR, and a drain region DR may be formed. The ions may be n-type impurities or p-type impurities. The ions may not be doped and remain in a portion of the polycrystalline silicon pattern136which overlaps the gate electrode GE thereby forming the channel region CR. Portions of the polycrystalline silicon pattern136which are doped with ions may have increased conductivity and may have a property of conductor, so that the source region SR and the drain region DR may be formed. The channel region CR may be formed between the source region SR and the drain region DR. A low concentration doping region may be respectively formed between the channel region CR and the source region SR and between the channel region CR and the drain region DR by doping impurities with a lower concentration than that of the ion injection process. The low concentration doping region may serve as a buffer in the active pattern AP so that electrical characteristics of a thin film transistor may be improved. Referring toFIG.15, an insulation interlayer150may be formed on the gate electrode GE. The insulation interlayer150may be disposed on the gate insulation layer140, and may cover the gate electrode GE. The insulation interlayer150may include an inorganic insulation layer, an organic insulation layer, or a combination thereof. The insulation interlayer150may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. The insulation interlayer150may further include insulating metal oxide such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. or a combination thereof. When the insulation interlayer150includes the organic insulation layer, the insulation interlayer150may include polyimide, polyamide, acryl resin, phenol resin, benzo cyclobutene (BCB), etc., or a combination thereof. The insulation interlayer150and the gate insulation layer140may be partially etched to form a first contact hole CH1and a second contact hole CH2respectively exposing the source region SR and the drain region DR. Referring toFIG.8, the source electrode SE and the drain electrode DE respectively electrically connected to the source region SR and the drain region DR of the active pattern AP may be formed on the insulation interlayer150. A second metal layer may be formed on the insulation interlayer150and patterned to form the source electrode SE being in contact with the source region SR and the drain electrode DE being in contact with the drain region DR. Each of the source electrode SE and the drain electrode DE may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, or an alloy thereof. Each of the source electrode SE and the drain electrode DE may have a single-layer structure or a multi-layer structure including different metal layers. Each of the source electrode SE and the drain electrode DE may include a triple layer of Mo, Al and Mo, a double layer of Cu and Ti, or the like. A cleaning process using the hydrofluoric acid and a rinsing process using the hydrogenated deionized water may be performed before the crystallization process. The crystallization process in which the amorphous silicon layer is irradiated with the laser beam having a relatively large density with a relatively small scan pitch may be performed. The thin film transistor TR may be formed to include the active pattern AP having a relatively large grain size and a relatively small surface roughness. Because a grain size of the active pattern AP is relatively large, the number of grain boundaries per unit area may be small. Thus, an electric charge mobility of the thin film transistor TR including the active pattern AP may increase. Because the surface roughness of the active pattern AP is relatively small, an interface area between the active pattern AP and the gate insulation layer140located on the active pattern AP may be small. Thus, hysteresis characteristic of the thin film transistor TR including the active pattern AP may be improved, and the gate insulation layer140having a relatively small thickness may be formed on the active pattern AP. Table 1 below illustrates that an electric charge mobility and a threshold voltage deviation of a thin film transistor including an active pattern having a relatively small grain size and a relatively large surface roughness by being crystallized with a laser beam having a relatively small energy density according to a comparative example of the prior art, and an electric charge mobility and a threshold voltage deviation of the thin film transistor TR including the active pattern AP having a relatively large grain size and a relatively small surface roughness by being crystallized with the laser beam having a relatively large energy density (e.g., about 480 mJ/cm2) according to one or more examples of this disclosure. The threshold voltage deviation is a difference between a threshold voltage when luminance of a pixel changes from a high grayscale (e.g., a white grayscale) to a low grayscale (e.g., a black grayscale) and a threshold voltage when luminance of the pixel changes from the low grayscale to the high grayscale, and hysteresis characteristic of the thin film transistor may be decreased as the threshold voltage deviation is larger. TABLE 1ComparativeexampleExampleElectric charge mobility [cm2/V · s]89.8592Threshold voltage deviation [V]0.26620.1874 Referring to Table 1, the electric charge mobility of the thin film transistor according to the comparative example is less than 90 cm2/V·s. In contrast, the electric charge mobility of the thin film transistor TR according to an embodiment of the invention may be greater than about 90 cm2/V·s. Further, the threshold voltage deviation of the thin film transistor according to the comparative example is greater than 0.22 V. In contrast, the threshold voltage deviation of the thin film transistor TR according to an embodiment of the invention may be less than about 0.2 V. Therefore, the thin film transistor substrate100according to an embodiment of the invention may include the thin film transistor TR having a relatively large electric charge mobility and improved hysteresis characteristic. Hereinafter, a display device and a method of manufacturing the display device will be described with reference toFIGS.16to19.FIG.16is a schematic diagram illustrating an equivalent circuit of a pixel of a display device according to one or more examples. A display device according to an embodiment may include signal lines and pixels PX connected to the signal lines and arranged as a substantial matrix form. The signal lines may include gate lines GL for transmitting gate signals (or scan signals), data lines DL for transmitting data voltages, and driving voltage lines PL for transmitting driving voltages ELVDD. The gate lines GL may extend along a substantial row direction. The data lines DL and the driving voltage lines PL may cross the gate lines GL, and may extend along a substantial column direction. Referring toFIG.16, each pixel PX may include a driving transistor TR1, a switching transistor TR2, a storage capacitor CST, and an organic light emitting diode OLED. The driving transistor TR1may include a control terminal connected to the switching transistor TR2, an input terminal connected to the driving voltage line PL, and an output terminal connected to the organic light emitting diode OLED. The driving transistor TR1may transmit an output current Id whose magnitude varies depending on the voltage between the control terminal and the output terminal of the driving transistor TR1to the organic light emitting diode OLED. The switching transistor TR2may include a control terminal connected to the gate line GL, an input terminal connected to the data line DL, and an output terminal connected to the driving transistor TR1. The switching transistor TR2may transmit a data voltage applied to the data line DL in response to a gate signal applied to the gate line GL to the driving transistor TR1. The storage capacitor CST may connect the control terminal and the input terminal of the driving transistor TR1. The storage capacitor CST may store the data voltage applied to the control terminal of the driving transistor TR1, and may maintain the data voltage after the switching transistor TR2is turned off. The organic light emitting diode OLED may include an anode connected to the output terminal of the driving transistor TR1and a cathode connected to a common voltage ELVSS. The organic light emitting diode OLED may emit light having different luminance depending on the output current Id of the driving transistor TR1thereby displaying an image. In an embodiment, each pixel PX may include two thin film transistors TR1and TR2and one capacitor CST, however, the number of transistors and/or capacitor(s) and their configuration are not limited thereto. In other embodiments, each pixel PX may include three or more thin film transistors and two or more capacitors. FIG.17is a schematic cross-sectional view illustrating a display device according to an embodiment. Referring toFIG.17, a display device may include a substrate110, a thin film transistor TR1disposed on the substrate110, and a display element disposed on the thin film transistor. The display device may include an organic light emitting diode as the display element. However, in other embodiments, the display device may include, as a display element, a liquid crystal element, an electrophoresis element, an electrowetting element, etc. The thin film transistor TR1and the organic light emitting diode OLED shown inFIG.17may correspond to the driving transistor TR1and the organic light emitting diode OLED shown inFIG.16, respectively. The display device may include the thin film transistor substrate100as illustrated inFIG.8. The organic light emitting diode OLED may include a first electrode E1, an emission layer180, and a second electrode E2, which are sequentially stacked. The organic light emitting diode OLED may emit light based on a driving current receiving from the thin film transistor TR1to display an image. FIGS.18and19are schematic cross-sectional views to explain a method of manufacturing a display device according to an embodiment, for example, the display device shown inFIG.17. In the below description of a method of manufacturing a display device, it will be avoided to repeat the same or similar description provided above for the method of manufacturing the thin film transistor substrate. Referring toFIG.18, a first electrode E1may be formed on a thin film transistor TR1. A planarization layer (or a passivation layer)160may be formed on a source electrode SE and a drain electrode DE. The planarization layer160may be disposed on an insulation interlayer150, and may cover the source electrode SE and the drain electrode DE. The planarization layer160may protect the thin film transistor TR1. The planarization layer160may provide a planarized surface above the thin film transistor TR1. The planarization layer160may include an inorganic insulation layer, an organic insulation layer, or a combination thereof. In varying examples, the planarization layer160may have a single-layer structure or a multi-layer structure including silicon nitride or silicon oxide. In case that the planarization layer160includes the organic insulation layer, the planarization layer160may include polyimide, polyamide, acrylic resin, phenol resin, BCB, etc. or a combination thereof. The planarization layer160may be patterned to form a contact hole that exposes the drain electrode DE. The first electrode E1may be formed on the planarization layer160. The first electrode E1may be connected to the drain electrode DE. A third metal layer may be formed on the planarization layer160and patterned to form the first electrode E1that is in contact with the drain electrode DE. The first electrode E1may be a pixel electrode of the display device. The first electrode E1may be formed as a transmitting electrode or a reflective electrode depending on an emission type of the display device. When the first electrode E1is formed as the transmitting electrode, the first electrode E1may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc., or a combination thereof. In case that the first electrode E1is formed as the reflective electrode, the first electrode E1may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, etc., or a combination thereof. The first electrode E1may have a multi-layer structure including the materials used in the transmitting electrode. A pixel defining layer170may be formed on the planarization layer160. The pixel defining layer170may have an opening portion that exposes at least a portion of the first electrode E1. The pixel defining layer170may include an organic insulation material. Referring toFIG.19, an emission layer180may be formed on the first electrode E1. The emission layer180may be formed on an upper surface of the first electrode E1exposed by the opening portion of the pixel defining layer170. The emission layer180may be formed by methods such as screen printing, inkjet printing, evaporation, etc. The emission layer180may include a low molecular weight polymer or a high molecular weight polymer. The emission layer180may include copper phthalocyanine, N,N′-diphenylbenzidine, tris-(8-gydroxyquinoline)aluminum, etc., or a combination thereof as the low molecular weight polymer. The emission layer180may include poly(3,4-ethylenedioxythiophene), polyaniline, poly-phenylenevinylene, polyfluorene, etc., or a combination thereof as the high molecular weight polymer. The emission layer180may emit red light, green light, or blue light. In other embodiments, the emission layer180may emit white light. In that case, the emission layer180may have a multi-layer structure including a red emission layer, a green emission layer, and a blue emission layer, or a single-layer structure including a red emission material, a green emission material, and a blue emission material. A hole injection layer and/or a hole transport layer may be further formed between the first electrode E1and the emission layer180, or an electron transport layer and/or an electron injection layer may be further formed on the emission layer180. Referring toFIG.17, a second electrode E2may be formed on the emission layer180. The second electrode E2may be a common electrode of the display device. The second electrode E2may be formed as a transmitting electrode or a reflective electrode depending on an emission type of the display device. In case that the second electrode E2is formed as the transmitting electrode, the second electrode E2may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof. The display device may be a top emission type in which light is emitted toward the second electrode E2. However, the emission type is not limited thereto. The display device may also be a bottom emission type. The display devices according to the disclosed examples may be applied to a display device included in a computer, a notebook, a mobile phone, a smartphone, a smart pad, a PMP, a PDA, an MP3 player, or the like. Although the methods of manufacturing the polycrystalline silicon layers, the thin film transistor substrates and the methods of manufacturing the same, and the display devices and the methods of manufacturing the same according to the examples have been described with reference to the drawings, the illustrated examples may be modified and changed by a person having ordinary knowledge in the relevant technical field without departing from the technical spirit described in the following claims. | 45,323 |
11942482 | DETAILED DESCRIPTION OF THE EMBODIMENTS The disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the disclosure are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the disclosure. The drawings and description are to be regarded as illustrative in nature and are not restrictive. Like reference numerals designate like elements throughout the specification. In the drawings, size and thickness of each element are arbitrarily illustrated for convenience of description, and the disclosure is not necessarily limited to as illustrated in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity. In addition, in the drawings, for better understanding and ease of description, the thicknesses of some layers and regions are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or one or more intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, throughout the specification, the word “on” a target element will be understood to mean positioned above or below the target element and will not necessarily be understood to mean positioned “at an upper side” based on an opposite to gravity direction. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. Further, throughout the specification, the phrase “on a plane” means viewing a target portion from the top, and the phrase “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side. The phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and should not be interpreted in an ideal or excessively formal sense unless clearly so defined herein. Hereinafter, a display device according to an embodiment of the disclosure will be described with reference to the accompanying drawings. FIG.1illustrates a schematic cross-section of a display device according to an embodiment.FIG.1simply illustrates a part of the cross-section for better comprehension and ease of description, and the disclosure is not limited thereto. Referring toFIG.1, a substrate SUB is provided. The substrate SUB may include at least one of polystyrene, polyvinyl alcohol, poly(methyl methacrylate), polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose triacetate, and cellulose acetate propionate. The substrate SUB may be a rigid substrate, or a flexible substrate that can be bent, folded, and rolled. The substrate SUB may be single-layered or multi-layered. The substrate SUB may be formed by alternately laminating at least one base layer and at least one inorganic layer including sequentially laminated polymer resins. A light blocking layer BML is disposed on the substrate SUB. The light blocking layer BML may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu) and a metal oxide and may have a single layer or multi-layer structure including the same. A first oxygen supply layer OS1is disposed on the light blocking layer BML. The first oxygen supply layer OS1may be disposed while directly contacting the light blocking layer BML. As shown inFIG.1, the first oxygen supply layer OS1and the light blocking layer BML may have a same planar shape. However, this is only an example, and the planar shape of the first oxygen supply layer OS1may be different from that of the light blocking layer BML. The first oxygen supply layer OS1may be a metal oxide containing indium (In), zinc (Zn), gallium (Ga), or tin (Sn). For example, the oxygen supply layer OS1may be one of an indium gallium zinc oxide (IGZO), an indium tin oxide (ITO), an indium tin gallium oxide (ITGO), an indium zinc oxide (IZO), a zinc oxide (ZnO), and an indium tin gallium zinc oxide (ITGZO). The first oxygen supply layer OS1and a semiconductor layer ACT, which will be described below, may include a same material. Although it will be described in detail below, the first oxygen supply layer OS1supplies oxygen to the semiconductor layer ACT and can increase the reliability of the semiconductor layer ACT including an oxide semiconductor. A thickness of the first oxygen supply layer OS1may be about 30% to about 50% of that of the semiconductor layer ACT. This is a numerical range for adequately supplying oxygen to the semiconductor layer ACT, and in case that the thickness of the first oxygen supply layer OS1is less than about 30% of that of the semiconductor layer ACT, the first oxygen supply layer OS1may not adequately supply oxygen to the semiconductor layer ACT, and the semiconductor layer ACT may function as a conductor. In case that the thickness of the first oxygen supply layer OS1exceeds about 50% of that of the semiconductor layer ACT, an excessive amount of oxygen may be supplied, and thus a threshold voltage of a transistor including the semiconductor layer ACT may be excessively high. A buffer layer BUF is disposed on the first oxygen supply layer OS1. The buffer layer BUF may include at least one of a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxynitride (SiOxNy), and amorphous silicon (Si). The buffer layer BUF may include a first opening OP1that overlaps the first oxygen supply layer OS1and the light blocking layer BML. In the first opening OP1, a first source/drain (SD) electrode SE may be electrically connected with the first oxygen supply layer OS1or the light blocking layer BML. The semiconductor layer ACT is disposed on the buffer layer BUF. The semiconductor layer ACT may include an oxide semiconductor. The oxide semiconductor may include at least one of indium (In), tin (Sn), zinc (Zn), hafnium (Hf), and aluminum (Al). For example, the semiconductor layer ACT may include an indium gallium zinc oxide (IGZO). The semiconductor layer ACT and the first oxygen supply layer OS1may include a same material. The semiconductor layer ACT may include a channel area CA that overlaps a gate electrode GE, and a first area SA and a second area DA that are disposed at opposite sides of the channel area CA. A gate insulating layer GI is disposed on the semiconductor layer ACT. The gate insulating layer GI may include at least one of a silicon oxide (SiOx), a silicon nitride (SiNx), and a silicon oxynitride (SiOxNy) and may have a single-layered or multi-layered structure including the same. The gate insulating layer GI may be disposed while overlapping the channel area CA of the semiconductor layer ACT. A gate conductive layer GC (seeFIG.10) that includes the gate electrode GE may be disposed on the gate insulating layer GI. The gate conductive layer GC may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and a metal oxide and may have a single-layered or multi-layered structure including the same. The gate electrode GE and the gate insulating layer GI may be formed by a same process and may have a same planar shape. The gate electrode GE may be disposed while overlapping the semiconductor layer ACT in a direction that is perpendicular to a surface of the substrate SUB. An interlayer insulating layer ILD may be disposed on the semiconductor layer ACT and the gate electrode GE. The interlayer insulating layer ILD may include a silicon oxide (SiOx), a silicon nitride (SiNx), and a silicon oxynitride (SiOxNy) and may have a single-layered or multi-layered structure including the same. In case that the interlayer insulating layer ILD has a multi-layer structure including a silicon nitride and a silicon oxide, the layer containing the silicon nitride may be disposed closer to the substrate SUB than the layer including the silicon oxide. The interlayer insulating layer ILD may include a first opening OP1overlapping the first oxygen supply layer OS1and the light blocking layer BML, a second opening OP2overlapping the first area SA of the semiconductor layer ACT, and a third opening OP3overlapping the second area DA. A data conductive layer that includes the first SD electrode SE and a second SD electrode DE is disposed on the interlayer insulating layer ILD. The data conductive layer may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu) and a metal oxide and may have a single layer or multi-layer structure including the same. The first SD electrode SE may contact the first oxygen supply layer OS1in the first opening OP1and may contact the first area SA of the semiconductor layer ACT in the second opening OP2. The second SD electrode DE may contact the second area DA of the semiconductor layer ACT in the third opening OP3. An insulating layer VIA is disposed on the data conductive layer. The insulating layer VIA may include organic insulating materials such as general-purpose polymers such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), polymer derivatives with phenolic groups, acryl-based polymers, imide polymers, polyimide, and siloxane polymers. The insulating layer VIA may include a fourth opening OP4that overlaps the first SD electrode SE. A first electrode191is disposed on the insulating layer VIA. A partitioning wall350may be disposed on the insulating layer VIA and the first electrode191. The partitioning wall350may include an opening355that overlaps the first electrode191. An emission layer360may be disposed in the opening355. A second electrode270may be disposed on the partitioning wall350and the emission layer360. The first electrode191, the emission layer360, and the second electrode270may form a light emitting diode LED. As described above, the display device according to the embodiment includes the first oxygen supply layer OS1disposed below the semiconductor layer ACT. In the case of the semiconductor layer ACT including the oxide semiconductor, it may be difficult to use it as a transistor because it exhibits the same properties as a conductor due to an oxygen vacancy therein, or it may not be suitable to be used as a transistor because of its a low threshold voltage. However, in the case of the display device according to an embodiment, since the first oxygen supply layer OS1supplies oxygen to the semiconductor layer ACT, reliability of the semiconductor layer ACT including the oxide semiconductor can be secured. Specifically, excessive oxygen included in the first oxygen supply layer OS1is introduced into the buffer layer BUF due to heat treatment and the like. Excess oxygen supplied to the buffer layer BUF is delivered to the semiconductor layer ACT and is combined with the oxygen vacancy inside the semiconductor layer ACT to eliminate the oxygen vacancy. Accordingly, the oxygen deficiency in the semiconductor layer ACT can be eliminated, and reliability of the transistor including the semiconductor layer ACT can be secured. FIG.2schematically illustrates a voltage (V)-current (I) graph of a display device that does not include the first oxygen supply layer OS1. Referring toFIG.2, it can be observed than a threshold voltage appears as low as about −4.35 V. FIG.3is a voltage (V)-current (I) graph of the display device that includes the first oxygen supply layer OS1according to the embodiment. Referring toFIG.3, it can be observed that a threshold voltage is about 0.09 V in the display device including the first oxygen supply layer OS1. For example, compared to the graph ofFIG.2, it can be seen that the threshold voltage is positively shifted and the display device operates more stably. FIG.4illustrates a cross-section of a display device according to another embodiment. Referring toFIG.4, a display device according to the embodiment may be different from the embodiment ofFIG.1at least in a planar shape of a first oxygen supply layer OS1. Repetitive descriptions will be omitted. Referring toFIG.4, a planar shape of a first oxygen supply layer OS1is different from a planar shape of a light blocking layer BML. For example, a part of the light blocking layer BML may not overlap the first oxygen supply layer OS1. As shown inFIG.4, the first SD electrode SE directly overlaps the light blocking layer BML in the first opening OP1and may not contact the first oxygen supply layer OS1. The area of the first oxygen supply layer OS1may be appropriately adjusted depending on a material and a threshold voltage of a semiconductor layer ACT. FIG.5illustrates a cross-section of a display device according to another embodiment. Referring toFIG.5, a display device according to the embodiment is the same as that according to the embodiment shown inFIG.1, except that a second oxygen supply layer OS2disposed between a gate insulating layer GI and a gate electrode GE is further included. Detailed descriptions of the same elements as those ofFIG.1will be omitted. A thickness of the second oxygen supply layer OS2may be about 30% to about 50% of a thickness of the semiconductor layer ACT. This is a numerical range for adequately supplying oxygen to the semiconductor layer ACT, and in case that the thickness of the first oxygen supply layer OS1is less than about 30% of the thickness of the semiconductor layer ACT, the semiconductor layer ACT may not receive an adequate amount of oxygen, and the semiconductor layer ACT may function as a conductor. In case that the thickness of the second oxygen supply layer OS2exceeds about 50% of the thickness of the semiconductor layer ACT, an excessive amount of oxygen may be supplied, and thus a threshold voltage of a transistor including the semiconductor layer ACT may be excessively high. Referring toFIG.5, the second oxygen supply layer OS2, the gate insulating layer GI, and the gate electrode GE may be formed by a same process and may have a same planar shape. The second oxygen supply layer OS2may be a metal oxide including indium, zinc, gallium, or tin. For example, the second oxygen supply layer OS2may include at least one of an IGZO, an ITO, an ITGO, an IZO, a ZnO, and an ITGZO. The first oxygen supply layer OS1, the second oxygen supply layer OS2, and the semiconductor layer ACT may include a same material. In case that the first oxygen supply layer OS1and the second oxygen supply layer OS2are included in the display device, much more oxygen can be supplied to the semiconductor layer ACT. FIG.6illustrates a cross-section of a display device according to another embodiment. Referring toFIG.6, a display device according to the embodiment may be different from the embodiment ofFIG.5at least in a planar shape of a first oxygen supply layer OS1. Repetitive descriptions of the same elements will be omitted. Referring toFIG.6, a planar shape of a first oxygen supply layer OS1is different from a planar shape of a light blocking layer BML. For example, a part of the light blocking layer BML may not overlap the first oxygen supply layer OS1. As shown inFIG.6, a first SD electrode SE overlaps the light blocking layer BML in a first opening OP1and may not contact the first oxygen supply layer OS1. Next, a method for manufacturing the display device according to the embodiment ofFIG.1will be described with reference toFIGS.7to12.FIGS.7to12are manufacturing process diagrams of the display device according to the embodiment ofFIG.1. Referring toFIG.7, the light blocking layer BML is formed on the substrate SUB. Since materials forming the substrate SUB and the light blocking layer BML have been described above, no further description will be provided. The light blocking layer BML may be formed by dry-etching after depositing the light blocking layer BML material on the substrate SUB. Next, referring toFIG.8, the first oxygen supply layer OS1is formed on the light blocking layer BML. Since the material forming the first oxygen supply layer OS1has been described above, no further description will be provided. The first oxygen supply layer OS1may be formed through wet etching after depositing the first oxygen supply layer OS1material on the substrate SUB and the light blocking layer BML. InFIG.8, the light blocking layer BML and the first oxygen supply layer OS1have the same planar shape, but this is not restrictive. For example, as shown inFIG.4, a planar shape of the first oxygen supply layer OS1may be different from a planar shape of the light blocking layer BML. Next, referring toFIG.9, the buffer layer BUF and the semiconductor layer ACT are formed on the light blocking layer BML and the first oxygen supply layer OS1. Since the material forming the buffer layer BUF and the semiconductor layer ACT have been described above, no further description will be provided. As shown inFIG.9, the semiconductor layer ACT may be disposed while overlapping the light blocking layer BML in a direction that is perpendicular to a surface of the substrate SUB. The semiconductor layer ACT may be formed by dry-etching after depositing a semiconductor layer ACT material on the buffer layer BUF. Next, referring toFIG.10, the gate insulating layer GI and the gate conductive layer GC are formed on the semiconductor layer ACT. Since the material forming the gate insulating layer GI and the gate conductive layer GC have been described above, no further description will be provided. Next, referring toFIG.11, the gate electrode GE is formed by wet-etching the gate conductive layer GC. The gate insulating layer GI can then be dry-etched by using a photoresist700used for etching the gate electrode GE. Referring toFIG.12, the gate insulating layer GI and the gate electrode GE may have a same planar shape. The interlayer insulating layer ILD is formed. The description of the material of the interlayer insulating layer ILD is the same as described above, and thus will be omitted. The main configuration of the present the disclosure is for the first oxygen supply layer OS1, and the subsequent manufacturing process is omitted. Hereinafter, a method for manufacturing the display device according to the embodiment ofFIG.5will be described with reference toFIGS.13to18.FIGS.13to18schematically illustrate manufacturing process diagrams of the display device according to the embodiment ofFIG.5. Referring toFIG.13, the light blocking layer BML is formed on the substrate SUB. The description of the materials forming the substrate SUB and the light blocking layer BML have been provided above, and therefore repetitive descriptions will not be provided. The light blocking layer BML is formed by dry-etching after depositing the light blocking layer BML material on the substrate SUB. Next, referring toFIG.14, the first oxygen supply layer OS1is formed on the light blocking layer BML. The description of the materials forming the first oxygen supply layer OS1is the same as described above, and thus no further description will be provided. The first oxygen supply layer OS1may be formed through wet-etching after depositing the first oxygen supply layer OS1material on the substrate SUB and the light blocking layer BML. InFIG.14, the light blocking layer BML and the first oxygen supply layer OS1have a same plane shape is illustrated, but this is not restrictive. For example, as shown inFIG.6, the planar shape of the first oxygen supply layer OS1may be different from the planar shape of the light blocking layer BML. Next, referring toFIG.15, the buffer layer BUF and the semiconductor layer ACT are formed on the light blocking layer BML and the first oxygen supply layer OS1. The description of the materials forming the buffer layer BUF and semiconductor layer ACT has been provided above, and therefore repetitive descriptions will not be provided. As shown inFIG.15, the semiconductor layer ACT may overlap the light blocking layer BML in a direction that is perpendicular to a surface of the substrate SUB. The semiconductor layer ACT may be formed by dry-etching after depositing the semiconductor layer ACT material on the buffer layer BUF. Next, referring toFIG.16, the gate insulating layer GI, the second oxygen supply layer OS2, and the gate conductive layer GC are formed on the semiconductor layer ACT. The description of the materials forming the gate insulating layer GI, the second oxygen supply layer OS2, and the gate conductive layer GC has been provided above, and therefore repetitive descriptions will not be provided. Referring toFIG.17, the gate conductive layer GC and the second oxygen supply layer OS2are dry-etched such that the gate electrode GE and the second oxygen supply layer OS2are formed. The gate conductive layer GC and the second oxygen supply layer OS2can be collectively etched using a photoresist700and may have a same planar shape. Referring toFIG.18, the gate insulating layer GI may be dry-etched by using a photoresist700used to etch the gate electrode GE and the second oxygen supply layer OS2. Therefore, the gate insulating layer GI, the second oxygen supply layer OS2, and the gate electrode GE may have a same planar shape. Next, the interlayer insulating layer ILD is formed. A material forming the interlayer insulating layer ILD has been described above, and therefore repetitive descriptions will not be provided. The main configuration of the disclosure is for the first oxygen supply layer OS1and the second oxygen supply layer OS2, and the subsequent manufacturing process is omitted. In the above, the main features of the disclosure have been described, focusing on a transistor and a light emitting diode electrically connected thereto for better comprehension and ease of description. The display device according to the embodiment may include transistors and capacitors, and an example thereof will be described below. FIG.19is a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment. Referring toFIG.19, a display device according to an embodiment includes pixels, and a pixel may include transistors T1, T2, and T3, a capacitor Cst, and at least one light emitting diode LED. In the embodiment, it will be described as an example that a pixel includes a light emitting diode LED. The transistors T1, T2, and T3include a first transistor T1, a second transistor T2, and a third transistor T3. A source electrode and a drain electrode, which will be described below, are provided to distinguish between two electrodes disposed on respective sides of channels of the respective transistor T1, T2, and T3and the terms may be interchanged. A gate electrode G1of the first transistor T1is electrically connected with an end of the capacitor Cst, a first electrode S1of the first transistor T1is electrically connected with a driving voltage line that transmits a driving voltage ELVDD, and a second electrode D1of the first transistor T1is electrically connected with an anode of the light emitting diode LED and another end of the capacitor Cst. The first transistor T1may receive a data voltage DAT according to the switching operation of the second transistor T2and supply a driving current to the light emitting diode LED according to a voltage stored in the capacitor Cst. A gate electrode G2of the second transistor T2is electrically connected with a first scan line that transmits a first scan signal SC, a first electrode S2of the second transistor T2is electrically connected with a data line that can transmit the data voltage DAT or a reference voltage, and a second electrode D2of the second transistor T2is electrically connected with the end of the capacitor Cst and the gate electrode G1of the first transistor T1. The second transistor T2may be turned on according to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1of the first transistor T1and the end of the capacitor Cst. A gate electrode G3of the third transistor T3is electrically connected with a second scan line that transmits a second scan signal SS, a first electrode S3of the third transistor T3is electrically connected with the another end of the capacitor Cst, the second electrode D1of the first transistor T1, and the anode of the light emitting diode LED, and a second electrode D3of the third transistor T3is electrically connected with an initialization voltage line that transmits an initialization voltage INIT. The third transistor T3is turned on according to the second scan signal SS to transmit the initialization voltage INIT to the anode of the light emitting diode LED and the another end of the capacitor Cst to initialize a voltage of the anode of the light emitting diode LED. FIG.19illustrates that the first scan signal SC and the second scan signal SS have different configurations, but this is merely an example, and the second transistor T2and the third transistor T3may be applied with the same scan signal. The end of the capacitor Cst is electrically connected with the gate electrode G1of the first transistor T1, and the another end thereof is electrically connected with the first electrode S3of the third transistor T3and the anode of the light emitting diode LED. A cathode of the light emitting diode LED is electrically connected with a common voltage line that transmits a common voltage ELVSS. The light emitting diode LED may emit light according to a driving current generated by the first transistor T1. Each of the transistors T1, T2, and T3may be disposed while overlapping the light blocking layer BML, and the first transistor T1may be electrically connected with the light blocking layer BML. While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. In contrast, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. | 27,168 |
11942483 | DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. The present invention therefore should not be construed as being limited to the following description of the embodiments. Note that in structures described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is omitted. Note that content (or may be part of the content) described in one embodiment may be applied to, combined with, or replaced by different content (or may be part of the different content) described in the embodiment and/or content (or may be part of the content) described in one or more different embodiments. Note that the structure of a diagram (or may be part of the diagram) illustrated in one embodiment can be combined with the structure of another part of the diagram, the structure of a different diagram (or may be part of the different diagram) illustrated in the embodiment, and/or the structure of a diagram (or may be part of the diagram) illustrated in one or more different embodiments. Note that size, thickness, or regions in the drawings are exaggerated for clarity in some cases. Thus, one aspect of an embodiment of the present invention is not limited to such scales. Alternatively, the drawings are perspective views of ideal examples. Thus, one aspect of an embodiment of the present invention is not limited to shapes and the like illustrated in the drawings. For example, a variation in shape due to a manufacturing technique or dimensional deviation can be included. Note that an explicit expression “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and where X and Y are directly connected. Here, each of X and Y is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Accordingly, a connection relation other than those illustrated in drawings and texts is also included, without limitation to a predetermined connection relation, for example, the connection relation illustrated in the drawings and the texts. For example, in the case where X and Y are electrically connected, one or more elements which enable an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, and/or a diode) can be connected between X and Y. For example, in the case where X and Y are functionally connected, one or more circuits which enable a functional connection between X and Y can be connected between X and Y. Note that for example, in the case where a signal output from X is transmitted to Y even when another circuit is provided between X and Y, X and Y are functionally connected. Note that an explicit expression “X and Y are electrically connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. That is, the explicit expression “X and Y are electrically connected” is the same as an explicit simple expression “X and Y are connected”. Note that even when independent components are electrically connected to each other in a circuit diagram, there is the case where one conductive layer has functions of a plurality of components (e.g., a wiring and an electrode), such as the case where part of a wiring functions as an electrode. The expression “electrically connected” in this specification also means that one conductive layer has functions of a plurality of components. Embodiment 1 In this embodiment, one aspect of a semiconductor device or the like (e.g., a display device or a light-emitting device) in the present invention is described with reference to drawings. FIG.1Ais a cross-sectional view of a semiconductor device in one embodiment of the present invention. The semiconductor device includes a transistor100and an electrode110over an insulating surface (or an insulating substrate)200. The transistor100includes an electrode101, an insulating layer102over the electrode101, a semiconductor layer103over the insulating layer102, an insulating layer105over the semiconductor layer103, and an electrode106over the insulating layer105. The electrode101has a region overlapping with the semiconductor layer103with the insulating layer102provided therebetween. The electrode106has a region overlapping with the semiconductor layer103with the insulating layer105provided therebetween. The electrode110is provided over the insulating layer105. A region121is at least part of a region where the electrode106at least partly overlaps with at least part of the semiconductor layer103. A region122is at least part of a region where the electrode110is provided. The insulating layer105is thinner in the region121than in the region122. It can also be said that the insulating layer105includes the region121and the region122thicker than the thin region121, the region121is at least part of a region where the electrode106overlaps with part of the semiconductor layer103, and that the region122at least partly overlaps with the electrode110. Here, the electrode101and the electrode106can function as a first gate electrode and a second gate electrode (a back gate electrode) of the transistor100, respectively. The electrode110can function as a pixel electrode. The electrode106overlaps with the semiconductor layer103with the thin region of the insulating layer105(the region121) provided therebetween; thus, the electrode106can function well as a back gate electrode. The electrodes110and106may be formed by etching of one conductive film. In that case, the electrodes110and106have the same material and substantially the same thickness. Alternatively, the electrodes110and106may be formed by etching of different conductive films. In the case where one conductive film is etched, the number of processes can be reduced. Note that the transistor preferably includes both the first gate electrode and the second gate electrode (the back gate electrode). However, one aspect of an embodiment of the present invention is not limited thereto. It is possible for the transistor to have one of the first gate electrode and the second gate electrode (the back gate electrode) but not to have the other electrode. For example, as illustrated inFIG.66C, a structure where the transistor does not include the electrode106may be employed. Even in such a case, the transistor can operate correctly. InFIG.1A, the transistor100further includes electrodes104aand104b. One of the electrodes104aand104bcan be a source electrode, and the other electrode can be a drain electrode. InFIG.1A, the electrodes104aand104bare provided over the semiconductor layer103(for example, the electrodes104aand104bare provided to be in contact with an upper surface and a side surface of the semiconductor layer103). A lower surface of the semiconductor layer103is not in contact with the electrodes104aand104b. Note that the transistor preferably includes both the source electrode and the drain electrode. However, one aspect of an embodiment of the present invention is not limited thereto. It is possible for the transistor to have one of the source electrode and the drain electrode but not to have the other electrode, or to have neither of the electrodes. Even in such a case, the transistor whose channel is formed in the semiconductor layer103can operate correctly when the transistor is connected to a different element (e.g., a different transistor) through the semiconductor layer103. Note that a transistor is an element having at least three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow through the drain, the channel region, and the source. Here, since the source and the drain of the transistor change depending on the structure, the operating condition, and the like of the transistor, it is difficult to define which is a source or a drain. Thus, a region which serves as a source or a region which serves as a drain is not referred to as a source or a drain in some cases. In that case, one of the source and the drain might be referred to as a first terminal, a first electrode, or a first region, and the other of the source and the drain might be referred to as a second terminal, a second electrode, or a second region, for example. The electrode110can be electrically connected to the transistor100through an opening provided in the insulating layer105. Note that an explicit expression “Y on X” or “Y over X” does not necessarily mean that Y is on and in direct contact with X The expression also means that X and Y are not in direct contact with each other, i.e., another object is provided between X and Y. Here, each of X and Y is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Thus, for example, an explicit expression “a layer Y on (or over) a layer X” means that the layer Y is on and in direct contact with the layer X, and another layer (e.g., a layer Z) is on and in direct contact with the layer X and the layer Y is on and in direct contact with the other layer. Note that another layer (e.g., a layer Z) may be a single layer or a plurality of layers (a stack of layers). Similarly, an explicit expression “Y above X” does not necessarily mean that Y is on and in direct contact with X, and another object may be provided therebetween. Thus, for example, an expression “a layer Y above a layer X” means that the layer Y is on and in direct contact with the layer X, and another layer (e.g., a layer Z) is on and in direct contact with the layer X and the layer Y is on and in direct contact with the other layer. Note that another layer (e.g., a layer Z) may be a single layer or a plurality of layers (a stack of layers). Note that the same can be said for an expression “Y under X” or “Y below X”. Note that as illustrated inFIG.9A, a region of the semiconductor layer103that does not overlap with the electrodes104aand104bmay be made thin. For example, when etching is performed so that the electrodes104aand104bare formed, part of a surface of the semiconductor layer103positioned below a layer to be the electrodes104aand104bmay be etched. The transistor in which at least part of a region of the semiconductor layer103that serves as a channel is made thin in this manner (or the transistor in which a channel protective film is not provided between an upper portion of the channel and the electrodes104aand104b) might also be referred to as a channel etched transistor. One aspect of the semiconductor device in the present invention is not limited to the structure inFIG.1A. Different structure examples of the semiconductor device in the present invention are described below. Note that the same portions as those inFIG.1Aare denoted by the same reference numerals, and the description thereof is omitted. For example, as illustrated inFIG.1B, an insulating layer107can be provided between the semiconductor layer103and the electrodes104aand104b. The insulating layer107functions as a protective film (a channel protective film) for preventing the semiconductor layer103(especially, the region of the semiconductor layer103that serves as a channel) from being etched when etching is performed so that the electrodes104aand104bare formed. The transistor having a channel protective film might be referred to as a channel protective transistor. In that case, the semiconductor layer103can be made thin; thus, the subthreshold swing (the S value) of the transistor100can be improved (decreased). Note that in the case where the transistor is a channel protective transistor, as illustrated inFIG.65D, the insulating layer105can be removed from the region121. In that case, the electrode106and the insulating layer107are partly in direct contact with each other. Consequently, the electrode106functioning as a back gate electrode can apply a stronger electric field to the semiconductor layer103. Alternatively, for example, as illustrated inFIG.2A, the electrodes104aand104bmay be formed below the semiconductor layer103(for example, some of upper surfaces and end surfaces of the electrodes104aand104bmay be formed to be in contact with the lower surface of the semiconductor layer103). Consequently, the semiconductor layer103can be prevented from being damaged during etching for the electrodes104aand104b. Alternatively, the semiconductor layer103can be made thin, so that the subthreshold swing (the S value) can be improved (decreased). Alternatively, for example, as illustrated inFIG.3A, ends131aand131bof the semiconductor layer103can be substantially aligned with ends132aand132bof the electrodes104aand104b. The semiconductor layer103and the electrodes104aand104bcan be formed by etching of a stack of a semiconductor film and a conductive film over the semiconductor film with the use of one mask. A photomask having three or more regions with different transmittances of light used for exposure (hereinafter such a photomask is referred to as a half-tone mask, a gray-tone mask, a phase shift mask, or a multi-tone mask) can be used as the mask. With the use of the half-tone mask, a region in which the semiconductor layer103is exposed and a region from which the semiconductor layer103is removed can be formed by etching using one mask. Thus, the number of processes of forming the transistor100can be further reduced, and the cost of the semiconductor device can be further reduced. Note that in the case where the semiconductor layer103and the electrodes104aand104bare formed using the half-tone mask, the semiconductor layer103always exists below the electrodes104aand104b. The end132aand/or the end132bmight be step-like ends. Alternatively, as illustrated inFIG.3B, the insulating layer107functioning as a channel protective film can be provided in the structure illustrated inFIG.3A. In this manner, channel protective films can be additionally provided in a variety of transistors which do not have channel protective films in drawings other thanFIG.3B. Alternatively, for example, as illustrated inFIG.9A, conductive layers108aand108bcan be provided between the semiconductor layer103and the electrodes104aand104b. The conductive layers108aand108bcan be formed using, for example, a semiconductor layer to which an impurity element imparting conductivity is added. Alternatively, for example, the conductive layers108aand108bcan be formed using a conductive metal oxide. Alternatively, for example, the conductive layers108aand108bcan be formed using a conductive metal oxide to which an impurity element imparting conductivity is added. Note that inFIG.1Aor the like, an impurity element imparting conductivity may be added to part of the semiconductor layer103. Examples of an impurity element imparting conductivity include phosphorus, arsenic, boron, hydrogen, and tin. Here, inFIG.9A, a region of the semiconductor layer103that does not overlap with the electrodes104aand104band the conductive layers108aand108bis made thin. This is because part of a surface of the semiconductor layer103positioned below a layer to be the electrodes104aand104band a layer to be the conductive layers108aand108bis etched (the transistor inFIG.9Ais a channel etched transistor) when etching is performed so that the electrodes104aand104band the conductive layers108aand108bare formed. Note that a channel protective film may be provided between the semiconductor layer103and the conductive layers108aand108b(the transistor inFIG.9Amay be a channel protective transistor) so that the semiconductor layer103can be prevented from being etched. Note that although the electrodes110and106are formed using the same layer in the above structures, this embodiment is not limited thereto. The electrodes110and106may be formed using different layers. Alternatively, an insulating layer can be provided between the electrodes104aand104band the semiconductor layer103or between the electrodes104aand104band the conductive layers108aand108b. Further, an opening may be provided in the insulating layer so that the electrodes104aand104bcan be connected to the semiconductor layer103or the electrodes104aand104bcan be connected to the conductive layers108aand108b. Note that a variety of substrates can be used as a substrate having an insulating surface200, without limitation to a certain type. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, and a base material film. Note that the transistor100may be formed over a substrate, and then, transferred to a different substrate so that the transistor100can be disposed over the different substrate. As described above, the threshold voltage can be effectively controlled by the back gate electrode of the transistor100inFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like. Thus, the transistor100can be easily normally off. Alternatively, on-state current can be effectively increased by the back gate electrode. Alternatively, off-state current can be effectively decreased by the back gate electrode. Alternatively, an on/off ratio can be increased by the back gate electrode. Thus, when a display device has the above structure, the display device can display an image accurately. Alternatively, when a display device or a light-emitting device has the above structure and the insulating layer105functions as a planarization film, the aperture ratio can be increased. This embodiment is one of basic structure examples according to one embodiment of the present invention. Thus, this embodiment can be freely combined with another embodiment obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of this embodiment. Embodiment 2 In this embodiment, one aspect of a semiconductor device or the like (e.g., a display device or a light-emitting device) in the present invention is described with reference to drawings. In the structure described in Embodiment 1 with reference toFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like, the insulating layer105in the region122or part of the region122can include a stack of a plurality of layers. The insulating layer105in the region122or part of the region122includes a stack of m (m is a natural number of 2 or more) layers. The insulating layer105in the region121or part of the region121may include a stack of m or less layers or a single layer. The insulating layer105may include an organic insulating layer or a stack of an organic insulating layer and an inorganic insulating layer. For example, in the structure illustrated inFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like, the insulating layer105in the region122may include a stack of layers105aand105b, and the insulating layer105in the region121may include a single layer of the layer105a. The layer105bis formed over the layer105a.FIG.1C,FIG.1D,FIG.2B,FIG.3C,FIG.3D, andFIG.9Beach illustrate such a structure. With such a structure, when only a necessary portion is etched utilizing a difference in sensitivity to etching (etching selectivity), a stack of the layers105aand105bcan be obtained. Accordingly, the thickness of the insulating layer105in each region can be easily controlled. Alternatively, the regions can adequately have different functions (e.g., a planarization function, an impurity blocking function, and a light blocking function) depending on film quality. Alternatively, the number of processes can be reduced when part of the layer is formed using a photosensitive material. Here, the layer105amay be an inorganic insulating layer, and the layer105bmay be an organic insulating layer. In that case, since an organic material is used, the layer105bcan be thicker than the layer105a. When the layer105ais an inorganic insulating layer (preferably a silicon nitride film), for example, an impurity in the layer105bcan be prevented from entering the transistor100. Alternatively, when the layer105bis an organic insulating layer, the organic insulating layer can function as a planarization layer; thus, unevenness due to the transistor100or the like can be reduced. In this manner, a surface on which the electrode110is formed can be planarized. Thus, for example, in the case where the electrode110is used as a pixel electrode, a display defect can be reduced. Alternatively, since the thickness of the layer105bcan be increased, noise to the pixel electrode can be reduced. Alternatively, since etching selectivity changes depending on film quality, only a necessary portion is selectively etched, so that a stack of the layers105aand105bwith a predetermined shape can be obtained. Alternatively, the layer105aand/or the layer105b(or part thereof, preferably the layer105b) may be a color filter and/or a black matrix. When the layer105aand/or the layer105bis a color filter and/or a black matrix, an attachment margin for the substrate provided with the transistor100(the substrate having the insulating surface200) and another substrate (e.g., a counter substrate or the like in the display device) can be increased. Alternatively, when a black matrix is provided in the layer105aand/or the layer105b(or part thereof) near the transistor100, light cannot be easily incident on the transistor100. When light is not easily incident on the transistor100, the off-state current of the transistor100or degradation of the transistor100can be reduced. For example, as illustrated inFIG.65A, a black matrix652can be provided in part of the layer105b. Note that a plurality of color filters with different colors that overlap with each other can be used as a black matrix. Note that a color filter and/or a black matrix is preferably formed using an organic material; thus, the color filter and/or the black matrix is preferably formed in the layer105b. Note that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. Alternatively, the thickness of the layer105amay be smaller than the thickness of the layer105b. When the thickness of the layer105ais made smaller, an electric field caused by the electrode106can be adequately applied to the channel. Alternatively, when the thickness of the layer105bis made larger, unevenness due to the transistor100or the like can be adequately reduced. Alternatively, for example, in the structure illustrated inFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like, the insulating layer105in the region122may include a stack of the layer105band a layer105c, and the insulating layer105in the region121may include a single layer of the layer105c. The layer105cis formed over the layer105b.FIG.26A,FIG.26B,FIG.27A,FIG.28A,FIG.28B, andFIG.34Aeach illustrate such a structure. With such a structure, when only a necessary portion is etched utilizing a difference in sensitivity to etching (etching selectivity), a stack of the layers105band105ccan be obtained. Accordingly, the thickness of the insulating layer105in each region can be easily controlled. Alternatively, the regions can adequately have different functions (e.g., a planarization function, an impurity blocking function, and a light blocking function) depending on film quality. Alternatively, the number of processes can be reduced because part of the layer can be formed using a photosensitive material. Here, the layer105bmay be an organic insulating layer, and the layer105cmay be an inorganic insulating layer. In that case, since an organic material is used, the layer105bcan be thicker than the layer105c. When the layer105cis an inorganic insulating layer (preferably a silicon nitride film), an impurity in the layer105bcan be prevented from entering the electrode106or a layer over the electrode106(e.g., a liquid crystal layer, an alignment film, or an organic EL layer). Alternatively, when the layer105bis an organic insulating layer, the organic insulating layer can be used as a planarization layer, and unevenness due to the transistor100or the like can be reduced. In this manner, a surface on which the electrode110is formed can be planarized. Thus, for example, in the case where the electrode110is used as a pixel electrode, a display defect can be reduced. Alternatively, since the thickness of the layer105bcan be increased, noise to the pixel electrode can be reduced. Alternatively, since etching selectivity changes depending on film quality, only a necessary portion is selectively etched, so that a stack of the layers105band105cwith a predetermined shape can be obtained. Alternatively, the layer105band/or the layer105c(or part thereof, preferably the layer105b) may be a color filter and/or a black matrix. When the layer105band/or the layer105cis a color filter and/or a black matrix, an attachment margin for the substrate provided with the transistor100(the substrate having the insulating surface200) and another substrate (e.g., a counter substrate or the like in the display device) can be increased. Alternatively, when a black matrix is provided in the layer105band/or the layer105c(or part thereof) near the transistor100, light cannot be easily incident on the transistor100. When light is not easily incident on the transistor100, the off-state current of the transistor100can be reduced and/or degradation of the transistor100can be reduced. For example, as illustrated inFIG.65B, the black matrix652can be provided in part of the layer105b. Note that a plurality of color filters with different colors that overlap with each other can be used as a black matrix. Note that a color filter and/or a black matrix is preferably formed using an organic material; thus, the color filter and/or the black matrix is preferably formed in the layer105b. Note that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. Alternatively, the thickness of the layer105cmay be smaller than the thickness of the layer105b. When the thickness of the layer105cis made smaller, an electric field caused by the electrode106can be adequately applied to the channel. Alternatively, when the thickness of the layer105bis made larger, unevenness due to the transistor100or the like can be adequately reduced. Alternatively, for example, in the structure illustrated inFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like, the insulating layer105in the region122may include a stack of the layers105a,105b, and105c, and the insulating layer105in the region121may include a stack of the layers105aand105c.FIG.26C,FIG.26D,FIG.27B,FIG.28C,FIG.28D, andFIG.34Beach illustrate such a structure. With such a structure, when only a necessary portion is etched utilizing a difference in sensitivity to etching (etching selectivity), a stack of the layers105a,105b, and105ccan be obtained. Accordingly, the thickness of the insulating layer105in each region can be easily controlled. Alternatively, the regions can adequately have different functions (e.g., a planarization function, an impurity blocking function, and a shielding function) depending on film quality. Alternatively, the number of processes can be reduced because part of the layer can be formed using a photosensitive material. Here, the layer105amay be an inorganic insulating layer, the layer105bmay be an organic insulating layer, and the layer105cmay be an inorganic insulating layer. In that case, since an organic material is used, the layer105bcan be thicker than each of the layers105aand105c. When the layer105ais an inorganic insulating layer (preferably a silicon nitride film), for example, an impurity in the layer105bcan be prevented from entering the transistor100. Alternatively, when the layer105cis an inorganic insulating layer (preferably a silicon nitride film), an impurity in the layer105bcan be prevented from entering the electrode106or the layer over the electrode106. When the layer105bis an organic insulating layer, the organic insulating layer can be used as a planarization layer, and unevenness due to the transistor100or the like can be reduced. In this manner, a surface on which the electrode110is formed can be planarized. Thus, for example, in the case where the electrode110is used as a pixel electrode, a display defect can be reduced. Alternatively, since the thickness of the layer105bcan be increased, noise to the pixel electrode can be reduced. Alternatively, the layer105aand the layer105bcan have different film qualities or the layer105band the layer105ccan have different film qualities. Then, since etching selectivity changes depending on film quality, only a necessary portion is selectively etched, so that a stack of the layers105a,105b, and105cwith a predetermined shape can be obtained. Alternatively, the layer105a, the layer105b, and/or the layer105c(or part thereof, preferably the layer105b) may be a color filter and/or a black matrix. When the layer105a, the layer105b, and/or the layer105cis a color filter and/or a black matrix, an attachment margin for the substrate provided with the transistor100(the substrate having the insulating surface200) and another substrate (e.g., a counter substrate or the like in the display device) can be increased. Alternatively, when a black matrix is provided in the layer105a, the layer105b, and/or the layer105c(or part thereof) near the transistor100, light cannot be easily incident on the transistor100. When light is not easily incident on the transistor100, the off-state current of the transistor100can be reduced and/or degradation of the transistor100can be reduced. For example, as illustrated inFIG.65C, the black matrix652can be provided in part of the layer105b. Note that a plurality of color filters with different colors that overlap with each other can be used as a black matrix. Note that a color filter and/or a black matrix is preferably formed using an organic material; thus, the color filter and/or the black matrix is preferably formed in the layer105b. Note that this embodiment is not limited thereto, and a light-blocking conductive film can be used as the black matrix. Note that each of the layers105a,105b, and105cmay be a single layer or a stack of a plurality of layers. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., Embodiment 1). Embodiment 3 In this embodiment, one aspect of a semiconductor device or the like (e.g., a display device or a light-emitting device) in the present invention is described with reference to drawings. In the structure described in Embodiment 1 with reference toFIG.1A,FIG.1B,FIG.2A,FIG.3A,FIG.3B,FIG.9A, or the like, the insulating layer105is made thin in the vicinity of the channel of the transistor100. However, the range of the region (the region121) where the insulating layer105is made thin is not limited thereto. The range of the region121may be part of the vicinity of the channel. For example, the structure illustrated inFIG.1Acan be changed into a structure illustrated inFIG.66A. InFIG.66A, the range of the region121is part of the vicinity of the channel (the range of the region121inFIG.66Ais smaller than the range of the region121inFIG.1A). The structures illustrated in other thanFIG.1Acan be changed similarly. Alternatively, the range of the region121may be the vicinity of the entire transistor100or larger than the vicinity of the entire transistor100. For example, the insulating layer105may be made thin in the vicinity of the transistor100(e.g., a region where the electrode106overlaps with the electrode104aand/or the electrode104b). In the structure described in Embodiment 2 with reference toFIG.1C,FIG.1D,FIG.2B,FIG.3C,FIG.3D,FIG.9B,FIG.26A,FIG.26B,FIG.27A,FIG.28A,FIG.28B,FIG.34A,FIG.26C,FIG.26D,FIG.27B,FIG.28C,FIG.28D,FIG.34B,FIG.65A,FIG.65B,FIG.65C, or the like, the layer105bin the vicinity of the channel of the transistor100is removed and the insulating layer105is made thin. However, the region from which the layer105bis removed is not limited thereto. The region from which the layer105bis removed may be part of the vicinity of the channel. For example, the structure illustrated inFIG.1Ccan be changed into a structure illustrated inFIG.66B. InFIG.66B, the range of the region121is part of the vicinity of the channel (the range of the region121inFIG.66Bis smaller than the range of the region121inFIG.1C). The structures illustrated in other thanFIG.1Ccan be changed similarly. Alternatively, the range of the region121may be the vicinity of the entire transistor100or larger than the vicinity of the entire transistor100. For example, in the structure illustrated inFIG.1C,FIG.1D,FIG.2B,FIG.3C,FIG.3D,FIG.9B,FIG.26C,FIG.26D,FIG.27B,FIG.28C,FIG.28D, orFIG.34B, the layer105bin the vicinity of the channel of the transistor100may be removed and the insulating layer105may be made thin. For example, the layer105bmay be removed from a region where the electrode106overlaps with the electrode104aand/or the electrode104b.FIG.1E,FIG.2D,FIG.2C,FIG.3E,FIG.2E,FIG.9C,FIG.26E,FIG.27D,FIG.27C,FIG.28E,FIG.27E, andFIG.34Ceach illustrate this structure. Note that in the structures illustrated inFIG.26E,FIG.27D,FIG.27C,FIG.28E,FIG.27E, andFIG.34C, one of the layers105aand105cmay be further removed from part or all of the region from which the layer105bis removed. In the structure where the insulating layer105is made thin in the vicinity of the transistor100(e.g., the region where the electrode106overlaps with the electrode104aand/or the electrode104b), the capacitance value of parasitic capacitance generated by overlapping of the electrode106with the electrode104aand/or the electrode104bcan be increased. Thus, the parasitic capacitance can be actively used as a storage capacitor. For example, the storage capacitor can be used as a storage capacitor in a pixel. Even when the insulating layer105is made thin in the vicinity of the transistor100as described above, in the case where a fixed potential is applied to the electrode106, the potential does not influence the potential of the electrode104aand/or the potential of the electrode104b. Note that one aspect of an embodiment of the present invention is not limited thereto. In contrast, when a variation potential (e.g., a pulse potential) is applied to the electrode106(for example, a signal which is similar to a signal input to the electrode101is input to the electrode106), in order to reduce the influence of a change in potential applied to the electrode106on the potential of the electrode104aand/or the potential of the electrode104b, it is preferable that the insulating layer105be made thick between the electrode106and the electrode104aand/or the electrode104b. For example, it is preferable that the layer105bbe provided between the electrode106and the electrode104aand/or the electrode104b. In this manner, the influence of a change in potential applied to the electrode106on the potential of the electrode104aand/or the potential of the electrode104bcan be reduced and, for example, noise to a signal input to the electrode110connected to the electrode104bcan be prevented. Thus, in the case where the electrode110is used as a pixel electrode, the display quality of the display device can be improved. Note that one aspect of an embodiment of the present invention is not limited thereto. Note that the electrode106may be formed in the entire region121or at least part of the region121. In the case where the electrode106is small, the degree of overlapping of the electrode104aand/or electrode104bwith the electrode106is small. Thus, the influence of a change in potential applied to the electrode106on the potential of the electrode104aand/or the potential of the electrode104bcan be reduced. Alternatively, in the case where a driver circuit (e.g., a scan line driver circuit or a signal line driver circuit for inputting a signal to a pixel) is formed using the transistors100, the entire region over the driver circuit may be the region121. For example, the entire layer105bover the driver circuit may be removed. This is because it is not necessary to provide a display element used for displaying an image over the driver circuit and it is not necessary to perform planarization with the use of the layer105b. Alternatively, when the entire layer105bover the driver circuit is removed, a capacitor (parasitic capacitance) formed by electrodes or wirings can be increased. In this manner, a capacitor (parasitic capacitance) used for bootstrap operation or a capacitor (parasitic capacitance) for a dynamic circuit can be increased. Alternatively, when the entire layer105bover the driver circuit is removed, a margin for part of the layer105bis not necessary; thus, the layout area of the entire driver circuit can be decreased. In that case, the electrodes106of the plurality of transistors100included in the driver circuit may be electrically connected to each other. Alternatively, the electrodes106of the plurality of transistors100included in the driver circuit may or may not be isolated from each other. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1 or part or all of Embodiment 2. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., Embodiment 1 or 2). Embodiment 4 In this embodiment, one aspect of a semiconductor device or the like (e.g., a display device or a light-emitting device) in the present invention is described with reference to drawings. Structure examples of a portion where the electrode110and the electrode104bare connected to each other in the semiconductor devices and the like in Embodiments 1 to 3 are described. Structure examples of a portion where the electrodes110and104bare connected to each other in the case of the insulating layer105including a stack of the layers105aand105bare described with reference toFIGS.4A and4BandFIGS.5A and5B. FIG.4Aillustrates the structure inFIG.1Cand an enlarged view of the portion where the electrodes110and104bare connected to each other in the structure. In the enlarged view inFIG.4A, an end of an opening in the layer105aand an end of an opening in the layer105bare substantially aligned with each other. Such openings can be formed, for example, in such a manner that a stack of a film A to be the layer105aand a film B to be the layer105bis formed, and then, the film A and the film B are etched using one photomask. The shape of the portion where the electrodes110and104bare connected to each other is not limited to the shape illustrated in the enlarged view inFIG.4A. For example, a shape illustrated inFIG.4Bmay be used. InFIG.4B, the end of the opening in the layer105aand the end of the opening in the layer105bare not aligned with each other, and the diameter of the opening in the layer105bis larger than the diameter of the opening in the layer105a(the difference in diameter between the openings is indicated by Δx1inFIG.4B). Openings with such shapes can be formed, for example, in such a manner that the structure illustrated in the enlarged view inFIG.4Ais formed, and then, ashing is performed on the layer105b. In the case where ashing is performed on the layer105b, the layer105bis formed using an organic insulating layer. Note that ashing means that part of a layer is removed in such a manner that an active oxygen molecule, an ozone molecule, an oxygen atom, or the like generated by discharge or the like chemically acts on a layer which is an organic substance to ash the layer. Alternatively, openings with such shapes can be formed in such a manner that a stack of the film A to be the layer105aand the film B to be the layer105bis formed, the film A and the film B are etched using a photomask, and then, the film B which is etched is further etched using a different photomask. Alternatively, openings with such shapes can be formed in such a manner that a stack of the film A to be the layer105aand the film B to be the layer105bis formed, the film B is etched using a photomask, and then, the film A is etched using a different photomask. In the case where the film A and the film B are etched using different photomasks, for example, as illustrated inFIG.5B, the diameter of the opening in the layer105bcan be much larger than the diameter of the opening in the layer105aas compared to the structure inFIG.4B(the difference in diameter between the openings is indicated by Δx3inFIG.5B). Alternatively, in the case where the film A and the film B are etched using different photomasks, for example, as illustrated inFIG.5A, the diameter of the opening in the layer105acan be larger than the diameter of the opening in the layer105b(the difference in diameter between the openings is indicated by Δx2inFIG.5A). FIGS.4A and4BandFIGS.5A and5Beach illustrate a structure example of the portion where the electrodes110and104bare connected to each other in the case of the insulating layer105including a stack of the layers105aand105b. However, the layered structure of the insulating layer105is not limited thereto. The shape of the portion where the electrodes110and104bare connected to each other can be varied depending on the layered structure. For example,FIGS.29A and29Beach illustrate a structure example of the portion where the electrodes110and104bare connected to each other in the case of the insulating layer105including a stack of the layers105band105c.FIG.29Aillustrates the structure inFIG.26Aand an enlarged view of the portion where the electrodes110and104bare connected to each other in the structure. InFIG.29A, the end of the opening in the layer105band an end of an opening in the layer105care not aligned with each other, and the diameter of the opening in the layer105bis larger than the diameter of the opening in the layer105c. InFIG.29B, the end of the opening in the layer105band the end of the opening in the layer105care not aligned with each other, and the diameter of the opening in the layer105cis larger than the diameter of the opening in the layer105b. Openings with the shapes inFIG.29AorFIG.29Bcan be formed, for example, in such a manner that the film B to be the layer105bis formed, the film B is etched using a photomask, a film C to be the layer105cis formed, and then, the film C is etched using a different photomask. Openings with the shapes inFIG.29Bcan be formed, for example, in such a manner that a stack of the film B to be the layer105band the film C to be the layer105cis formed, the film B and the film C are etched using a photomask, and then, the film C which is etched is further etched using a different photomask. Note that although not illustrated inFIGS.29A and29B, the end of the opening in the layer105band the end of the opening in the layer105cmay be substantially aligned with each other. For example,FIGS.30A and30Beach illustrate a structure example of the portion where the electrodes110and104bare connected to each other in the case of the insulating layer105including a stack of the layers105a,105b, and105c.FIG.30Aillustrates the structure inFIG.26Cand an enlarged view of the portion where the electrodes110and104bare connected to each other in the structure. InFIG.30A, the end of the opening in the layer105aand the end of the opening in the layer105bare substantially aligned with each other. The end of the opening in the layer105aand the end of the opening in the layer105bare not aligned with each other, and the diameter of each of the openings in the layers105aand105bis larger than the diameter of the opening in the layer105c. InFIG.30B, the end of the opening in the layer105aand the end of the opening in the layer105care substantially aligned with each other. The end of the opening in the layer105aand the end of the opening in the layer105care not aligned with each other, and the diameter of the opening in the layer105bis larger than the diameter of each of the openings in the layers105aand105c. Openings with the shapes inFIG.30Acan be formed, for example, in such a manner that a stack of the film A to be the layer105aand the film B to be the layer105bis formed, the film B and the film A are etched using a photomask, the film C to be the layer105cis formed, and then, the film C is etched using a different photomask. Openings with the shapes inFIG.30Bcan be formed, for example, in such a manner that a stack of the film A to be the layer105aand the film B to be the layer105bis formed, the film B is etched using a photomask, the film C to be the layer105cis formed, and then, the film C and the film A are etched using a different photomask. Note that although not illustrated inFIGS.30A and30B, the end of the opening in the layer105a, the end of the opening in the layer105b, and the end of the opening in the layer105cmay be aligned with each other. Alternatively, a structure may be employed in which the end of the opening in the layer105a, the end of the opening in the layer105b, and the end of the opening in the layer105care not aligned with each other. In that case, an end of the layer105amay be covered with the layer105b. An end of the layer105bmay or may not be covered with the layer105c. Note that in each of the structures illustrated inFIGS.4A and4BandFIGS.5A and5B, the taper angle of the end of the opening in the layer105a(indicated by θ2inFIGS.4A and4BandFIGS.5A and5B) may be substantially the same as or different from the taper angle of the end of the opening in the layer105b(indicated by θ1inFIGS.4A and4BandFIGS.5A and5B). In the structures illustrated inFIGS.29A and29B, the taper angle of the end of the opening in the layer105b(indicated by θ1inFIGS.29A and29B) may be substantially the same as or different from the taper angle of the end of the opening in the layer105c(indicated by θ3inFIGS.29A and29B). In the structures illustrated inFIGS.30A and30B, all the taper angle of the end of the opening in the layer105a(indicated by θ2inFIGS.30A and30B), the taper angle of the end of the opening in the layer105b(indicated by θ1inFIGS.30A and30B), and the taper angle of the end of the opening in the layer105c(indicated by θ3inFIGS.30A and30B) may be substantially the same, two of the taper angles may be substantially the same, or all the taper angles may be different from each other. For example, in the case where the thickness of the layer105bis large, θ1is preferably small in order that the end of the layer105bcan be smooth as much as possible. For example, θ2is preferably larger than θ1. Further, θ3is preferably larger than θ1. Note that one aspect of an embodiment of the present invention is not limited thereto. Here, the taper angle of an end of a layer is an angle formed by a side surface of the end of the layer (a tangent at a lower end) and a bottom surface of the layer when the layer is seen from a cross-sectional direction. The taper angle of each layer can be controlled by control of the thickness and material of each layer, etching conditions for forming an opening in each layer, and the like. Note thatFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Billustrate structure examples of the portion where the electrodes110and104bare connected to each other in the structures illustrated inFIG.1C,FIG.26A, andFIG.26C. However, a similar structure can be employed in the portion where the electrodes110and104bare connected to each other in the semiconductor devices in Embodiments 1 to 3 with the other structures. Each of the structure examples of the portion where the electrodes110and104bare connected to each other inFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Bcan be employed as the structure of a portion where a given electrode provided below the insulating layer105is electrically connected to a given electrode provided over the insulating layer105through an opening formed in the insulating layer105. For example, each of the structure examples of the portion where the electrodes110and104bare connected to each other inFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Bcan also be employed as the structure of a portion where an electrode formed using the same layer as the electrode110is connected to an electrode formed using the same layer as the electrode104b. For example, each of the structure examples of the portion where the electrodes110and104bare connected to each other inFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Bcan also be employed as the structure of a portion where the electrode110or an electrode formed using the same layer as the electrode110is connected to the electrode101or an electrode formed using the same layer as the electrode101. For example, each of the structure examples of the portion where the electrodes110and104bare connected to each other inFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Bcan also be employed as the structure of a portion where the electrode106or an electrode formed using the same layer as the electrode106is connected to the electrode101or an electrode formed using the same layer as the electrode101. For example, each of the structure examples of the portion where the electrodes110and104bare connected to each other inFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30Bcan also be employed as the structure of a portion where the electrode106or an electrode formed using the same layer as the electrode106is connected to the electrode104bor an electrode formed using the same layer as the electrode104b. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, or part or all of Embodiment 3. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 3). Embodiment 5 In this embodiment, examples of an electrical connection between the electrode106of the transistor100and a different electrode or a wiring are described. Note that in drawings, the same portions as those in the drawings in any of the above embodiments are denoted by the same reference numerals, and the description thereof is omitted. For example, the electrode106can be electrically connected to the electrode101. With such a connection, the same potential as the electrode101can be supplied to the electrode106. Thus, the on-state current of the transistor100can be increased.FIGS.6A to6E,FIGS.7A to7E,FIGS.8A to8E,FIGS.9D and9E,FIGS.31A to31E,FIGS.32A to32E,FIGS.33A to33E, andFIGS.34D and34Eeach illustrate an example in which the electrode106is electrically connected to the electrode101. Note that the electrical connections between the electrodes106and101in these drawings can be similar to those in the variety of drawings in Embodiments 1 to 4. Note that in the case where the transistors100are provided in pixels and a pixel matrix constituted of a plurality of pixels is formed, an opening may be formed for each pixel so that the electrode106may be electrically connected to the electrode101. Accordingly, contact resistance or wiring resistance can be lowered. Alternatively, an opening may be formed for each plurality of pixels so that the electrode106may be electrically connected to the electrode101. Accordingly, the layout area can be reduced. Alternatively, the electrode106may be electrically connected to the electrode101in a pixel matrix region or outside the pixel matrix region. When the electrode106is electrically connected to the electrode101outside the pixel matrix region, the layout area in the pixel matrix region can be reduced. Accordingly, the aperture ratio can be increased. Note that in the case where a driver circuit is provided outside the pixel matrix region, it is preferable that the electrode106be electrically connected to the electrode101in a region between the driver circuit and the pixel matrix region. Alternatively, for example, the electrode106can be electrically connected to the electrode104aor the electrode104b. With such a connection, the same potential as the electrode104aor the electrode104bcan be supplied to the electrode106.FIGS.13A to13E,FIGS.14A to14E,FIGS.15A to15E,FIGS.38A to38E,FIGS.39A to39E, andFIGS.40A to40Eeach illustrate an example in which the electrode106is connected to the electrode104b. Note that the electrical connections between the electrode106and the electrode104aor the electrode104bin these drawings can be similar to those in the variety of drawings in Embodiments 1 to 4. Note that in the case where the transistors100are provided in pixels and a pixel matrix constituted of a plurality of pixels is formed, an opening may be formed for each pixel so that the electrode106may be electrically connected to the electrode104b. Alternatively, an opening may be formed for each plurality of pixels so that the electrode106may be electrically connected to the electrode104b. Alternatively, the electrode106may be electrically connected to the electrode104bin a pixel matrix region or outside the pixel matrix region. Thus, as in the above case, contact resistance or wiring resistance can be reduced and/or the layout area can be reduced. Alternatively, for example, the electrode106can be electrically connected to the electrodes104band110. With such a connection, the same potential as the electrodes104band110can be supplied to the electrode106.FIGS.16A to16E,FIGS.17A to17E,FIGS.18A to18E,FIGS.41A to41E,FIGS.42A to42E, and FIGS.43A to43E each illustrate an example in which the electrode106is connected to the electrodes104band110. Note that in the structures in these drawings, the electrodes110and106are formed using one conductive film, and the electrodes110and106are collectively referred to as the electrode110. Although the example in which the electrodes110and106are formed using one conductive film is described, this embodiment is not limited thereto. The electrodes110and106may be formed by etching of different conductive films. Alternatively, the electrodes110and106may be in contact with each other to be electrically connected to each other. Note that the electrical connections between the electrode106and the electrodes104band110in these drawings can be similar to those in the variety of drawings in Embodiments 1 to 4. Alternatively, for example, the electrode106can be electrically connected to an electrode101awhich is formed using the same layer as the electrode101. Here, the electrodes101and101acan be formed by etching of one conductive film with the use of one mask (reticle). That is, the electrodes101and101aare patterned concurrently. Thus, the electrodes101and101ahave substantially the same material and thickness, for example.FIGS.10A to10E,FIGS.11A to11E,FIGS.12A to12E,FIGS.35A to35E,FIGS.36A to36E, andFIGS.37A to37Eeach illustrate an example in which the electrode106is connected to the electrode101a. Note that the electrical connections between the electrode106and the electrode which is formed using the same layer as the electrode101in these drawings can be similar to those in the variety of drawings in Embodiments 1 to 4. Note that in the case where the transistors100are provided in pixels and a pixel matrix constituted of a plurality of pixels is formed, an opening may be formed for each pixel so that the electrode106may be electrically connected to the electrode101a. Alternatively, an opening may be formed for plurality of pixels so that the electrode106may be electrically connected to the electrode101a. Alternatively, the electrode106may be electrically connected to the electrode101ain a pixel matrix region or outside the pixel matrix region. For example, the electrode101acan be a capacitor line provided in the pixel matrix. The capacitor line forms capacitance such as storage capacitance by overlapping with a different wiring, an electrode, a conductive layer, or the like with an insulating layer provided therebetween. Alternatively, the electrode101acan be a gate signal line provided in a different pixel or a different gate signal line in the same pixel. Alternatively, for example, the electrode106can be electrically connected to an electrode104cwhich is formed using the same layer as the electrode104aor the electrode104b. Here, the electrodes104a,104b, and104ccan be formed by etching of one conductive film with the use of one mask (reticle). That is, the electrodes104a,104b, and104care patterned concurrently. Thus, the electrodes104a,104b, and104chave substantially the same material and thickness, for example.FIGS.23A to23E,FIGS.24A to24E,FIGS.25A to25E,FIGS.49A to49E,FIGS.50A to50E, andFIGS.51A to51Eeach illustrate an example in which the electrode106is connected to the electrode104c. Note that inFIGS.25A to25EandFIGS.51A to51E, a semiconductor layer103awhich is formed using the same layer as the semiconductor layer103is provided below the electrode104c. Note that the electrical connections between the electrode106and the electrode which is formed using the same layer as the electrode104aor the electrode104bin these drawings can be similar to those in the variety of drawings in Embodiments 1 to 4. Note that in the case where the transistors100are provided in pixels and a pixel matrix constituted of a plurality of pixels is formed, an opening may be formed for each pixel so that the electrode106may be electrically connected to the electrode104c. Alternatively, an opening may be formed for each plurality of pixels so that the electrode106may be electrically connected to the electrode104c. Alternatively, the electrode106may be electrically connected to the electrode104cin a pixel matrix region or outside the pixel matrix region. For example, the electrode104ccan be a capacitor line provided in the pixel matrix. The capacitor line forms capacitance such as storage capacitance by overlapping with a different wiring, an electrode, a conductive layer, or the like with an insulating layer provided therebetween. Alternatively, the electrode104ccan be a signal line or a power supply line provided in a different pixel or a different signal line or a different power supply line in the same pixel. Here, in the case where the electrode101aor the electrode104cis a capacitor line, the following structures can be employed. A structure may be employed in which a capacitor line is provided in each pixel row (or each pixel column) of the pixel matrix and the electrode106of the transistor100in each pixel row (or each pixel column) is electrically connected to the capacitor line provided in the pixel row (or the pixel column). Alternatively, a structure may be employed in which a capacitor line is provided in each pixel row (or each pixel column) of the pixel matrix and the electrode106of the transistor100in each pixel row (or each pixel column) is electrically connected to a capacitor line provided in a pixel row (or a pixel column) adjacent to the pixel row (or the pixel column). Note that in the case where one pixel of the pixel matrix includes a plurality of subpixels, a structure may be employed in which a capacitor line is provided in each subpixel row (or each subpixel column) and the electrode106of the transistor100in each subpixel row (or each subpixel column) is electrically connected to the capacitor line provided in the subpixel row (or the subpixel column). Alternatively, in the case where one pixel of the pixel matrix includes a plurality of subpixels, a structure may be employed in which a capacitor line is provided in each pixel row (or each pixel column) and the electrode106of the transistor100in each subpixel row (or each subpixel column) is electrically connected to the capacitor line provided in the pixel row (or the pixel column). Alternatively, in the case where one pixel of the pixel matrix includes a plurality of subpixels, a structure may be employed in which a capacitor line is provided in each subpixel row (or each subpixel column) and the electrode106of the transistor100in each subpixel row (or each subpixel column) is electrically connected to a capacitor line provided in a subpixel row (or a subpixel column) adjacent to the subpixel row (or the subpixel column). A plurality of capacitor lines can be merged into a single capacitor line. For example, a capacitor line can be used in common between adjacent pixels (or subpixels). Accordingly, the number of capacitor lines can be reduced. Note that in the case where the electrode106of the transistor100is electrically connected to a capacitor line, a fixed potential (preferably a potential equal to or lower than the lowest potential applied to the electrode101) can be applied to the capacitor line. Thus, the threshold voltage of the transistor100can be controlled so that the transistor100can be normally off. Further, noise due to capacitive coupling with the electrode101, the electrode104a, or the like can be prevented from being input to the electrode110. Note that in the case where the electrode106of the transistor100is electrically connected to the capacitor line, a pulse signal can be supplied to the capacitor line. For example, in the case where common inversion driving is performed, the potential of a counter electrode and the potential of the capacitor line are changed with the same amplitude value in some cases. Even in such a case, when a low potential at which the transistor100is turned off is supplied to the electrode106, the threshold voltage of the transistor100can be controlled so that the transistor100can be normally off. Note that in the case where the electrode106of the transistor100is electrically connected to the capacitor line, it is preferable that the semiconductor layer103be not provided between a pair of electrodes (one of which is the capacitor line) of a capacitor. Note that one aspect of an embodiment of the present invention is not limited thereto. Note that the electrode101aor the electrode104cis not limited to a capacitor line, and can be a different wiring. For example, the electrode101aor the electrode104may be a power supply line, an initialization wiring, or the like. For example, the electrode101aor the electrode104may be a wiring provided in a pixel circuit in a display device including an EL element (e.g., an organic light-emitting element). Alternatively, the electrode101aor the electrode104may be a wiring provided in a driver circuit (e.g., a scan line driver circuit or a signal line driver circuit in a display device). This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, or part or all of Embodiment 4. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 4). Embodiment 6 In this embodiment, examples of an electrical connection between the electrode101of the transistor100(or an electrode formed using the same layer as the electrode101) and the electrode104aor the electrode104bof the transistor100(or an electrode formed using the same layer as the electrode104aor the electrode104b) are described with reference toFIGS.19A to19D,FIGS.44A to44D, andFIGS.45A to45D. Note that in drawings, the same portions as those in the drawings in any of the above embodiments are denoted by the same reference numerals, and the description thereof is omitted. FIGS.19A to19Deach illustrate an example of an electrical connection between the electrode101aformed using the same layer as the electrode101of the transistor100and the electrode104cformed using the same layer as the electrode104aor the electrode104bin the case of the insulating layer105including the layers105aand105b. In the structure illustrated inFIG.19A, the electrode104cand the electrode101aare electrically connected to each other through an electrode110bin an opening191formed in the layers105aand105band an opening192formed in the insulating layer102and the layers105aand105b. In the structure illustrated inFIG.19B, the electrode104cand the electrode101aare electrically connected to each other through the electrode110bin an opening193formed in the layer105aand an opening194formed in the insulating layer102and the layer105a. That is, the layer105bis not provided in the portion g109where the electrodes104cand101aare connected to each other. Note that the layer105bis not necessarily omitted from the entire portion where the electrodes104cand101aare connected to each other. For example, as in the structure illustrated inFIG.19CorFIG.19D, the layer105bmay be provided in part of the portion109where the electrodes104cand101aare connected to each other. In the structure illustrated inFIG.19C, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening195formed in the layer105aand an opening196formed in the insulating layer102and the layers105aand105b. In the structure illustrated inFIG.19D, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening197formed in the layers105aand105band an opening198formed in the insulating layer102and the layer105a. Next,FIGS.44A to44Deach illustrate an example of an electrical connection between the electrode101aformed using the same layer as the electrode101of the transistor100and the electrode104cformed using the same layer as the electrode104aor the electrode104bin the case of the insulating layer105including the layers105band105c. In the structure illustrated inFIG.44A, the electrode104cand the electrode101aare electrically connected to each other through the electrode110bin an opening441formed in the layers105band105cand an opening442formed in the insulating layer102and the layers105band105c. In the structure illustrated inFIG.44B, the electrode104cand the electrode101aare electrically connected to each other through the electrode110bin an opening443formed in the layer105cand an opening444formed in the insulating layer102and the layer105c. That is, the layer105bis not provided in the portion109where the electrodes104cand101aare connected to each other. Note that the layer105bis not necessarily omitted from the entire portion where the electrodes104cand101aare connected to each other. For example, as in the structure illustrated inFIG.44CorFIG.44D, the layer105bmay be provided in part of the portion109where the electrodes104cand101aare connected to each other. In the structure illustrated inFIG.44C, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening445formed in the layer105cand an opening446formed in the insulating layer102and the layers105band105c. In the structure illustrated inFIG.44D, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening447formed in the layers105band105cand an opening448formed in the insulating layer102and the layer105c. Next,FIGS.45A to45Deach illustrate an example of an electrical connection between the electrode101aformed using the same layer as the electrode101of the transistor100and the electrode104cformed using the same layer as the electrode104aor the electrode104bin the case of the insulating layer105including the layers105a,105b, and105c. In the structure illustrated inFIG.45A, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening451formed in the layers105a,105b, and105cand an opening452formed in the insulating layer102and the layers105a,105b, and105c. In the structure illustrated inFIG.45B, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening453formed in the layers105aand105cand an opening454formed in the insulating layer102and the layers105aand105c. That is, the layer105bis not provided in the portion109where the electrodes104cand101aare connected to each other. Note that the layer105bis not necessarily omitted from the entire portion where the electrodes104cand101aare connected to each other. For example, as in the structure illustrated inFIG.45CorFIG.45D, the layer105bmay be provided in part of the portion109where the electrodes104cand101aare connected to each other. In the structure illustrated inFIG.45C, the electrodes104cand101aare electrically connected to each other through the electrode110bin an opening455formed in the layers105aand105cand an opening456formed in the insulating layer102and the layers105a,105b, and105c. In the structure illustrated inFIG.45D, the electrode104cand the electrode101aare electrically connected to each other through the electrode110bin an opening457formed in the layers105a,105b, and105cand an opening458formed in the insulating layer102and the layers105aand105c. Each of the connections between the electrodes104cand101ain this embodiment can be used, for example, as a connection between the electrode104band the electrode101in the case of the diode-connected transistor100. The diode-connected transistor can be used, for example, in a protection circuit, a driver circuit, or the like. Alternatively, the connection between the electrodes104cand101acan also be used when a gate electrode is connected to a source electrode or a drain electrode. For example, the connection between the electrodes104cand101ais used when a gate electrode is connected to a source electrode or a drain electrode in a pixel circuit in which one pixel includes a plurality of transistors or a driver circuit. For example, in a pixel circuit in which a pixel includes an EL element (e.g., an organic light-emitting element), a plurality of transistors are provided and a gate electrode is connected to a source electrode or a drain electrode in some cases. Alternatively, also in a circuit for driving a gate line, a plurality of transistors are provided. Further, the openings191to198inFIGS.19A to19D, the openings441to448inFIGS.44A to44D, and the openings451to458inFIGS.45A to45Dcan have shapes which are similar to the shapes of the openings described in Embodiment 4 with reference toFIGS.4A and4B,FIGS.5A and5B,FIGS.29A and29B, andFIGS.30A and30B. Note that the electrodes104cand101acan be connected to each other without the use of the electrode110b. For example, the electrodes104cand101acan be directly connected to each other in a contact hole formed in the insulating layer102. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, or part or all of Embodiment 5. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 5). Embodiment 7 In this embodiment, examples of a structure in which the parasitic capacitance of the transistor100is increased or a structure in which the capacitance value of a capacitor electrically connected to the transistor100is increased are described with reference toFIGS.20A to20D,FIGS.21A to21D,FIGS.46A to46D, andFIGS.47A to47D. Note that in drawings, the same portions as those in the drawings in any of the above embodiments are denoted by the same reference numerals, and the description thereof is omitted. Note thatFIGS.20A to20DandFIGS.21A to21Deach illustrate an example in which a stack of the layers105aand105bis used as the insulating layer105.FIGS.46A and46CandFIGS.47B and47Ceach illustrate an example in which a stack of the layers105band105cis used as the insulating layer105.FIGS.46B and46DandFIGS.47A and47Deach illustrate an example in which a stack of the layers105a,105b, and105cis used as the insulating layer105. InFIGS.20A to20D,FIGS.21A to21D,FIGS.46A to46D, andFIGS.47Ato47D, the entire layer105bover the electrode104bor most of the layer105bover the electrode104bis removed, and the capacitance value of parasitic capacitance (or the capacitance value of a capacitor including the electrode104band the electrode106) is large. InFIGS.20A to20D,FIGS.21A to21D,FIGS.46A to46D, andFIGS.47A to47D, for example, parasitic capacitance is generated and/or a capacitor is formed in a portion281surrounded by a dashed line. The capacitance value can be adjusted when the shapes of the electrodes104band106, a range where the layer105bover electrode104bis removed, and the like are determined as appropriate. Note that inFIGS.20A to20D,FIGS.21A to21D,FIGS.46A to46D, andFIGS.47A to47D, parasitic capacitance might also be generated between the electrodes104band101and/or a capacitor including the electrodes104band101might be formed. The capacitance value can be adjusted when the shapes of the electrodes104band101are determined as appropriate. In this manner, capacitance between a gate and a source of the transistor100can be increased. Alternatively, a capacitor whose capacitance value is large can be formed. For example, in the case where the transistor100is used in a circuit for performing bootstrap operation, the capacitance between the gate and the source is preferably increased. Alternatively, when a signal is held in a capacitor in a dynamic circuit, the capacitor is preferably large. Thus, the transistor100with the structure illustrated inFIGS.20A to20D,FIGS.21A to21D,FIGS.46A to46D,FIGS.47A to47D, or the like is preferably used. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, or part or all of Embodiment 6. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 6). Embodiment 8 In this embodiment, structure examples of a capacitor included in a semiconductor device or the like (e.g., a display device or a light-emitting device) are described with reference toFIGS.22A to22EandFIGS.48A to48E. Note that in drawings, the same portions as those in the drawings in any of the above embodiments are denoted by the same reference numerals, and the description thereof is omitted. Note thatFIGS.22A to22Eeach illustrate an example in which a stack of the layers105aand105bis used as the insulating layer105.FIGS.48A and48Ceach illustrate an example in which a stack of the layers105band105cis used as the insulating layer105.FIGS.48B,48D, and48Eeach illustrate an example in which a stack of the layers105a,105b, and105cis used as the insulating layer105. It is possible to form a capacitor that has the electrode101aformed using the same layer as the electrode101as one electrode and has the electrode104cformed using the same layer as the electrode104aas the other electrode.FIGS.22A and22Beach illustrate such an example. InFIGS.22A and22B, for example, a capacitor is formed in a portion282surrounded by a dashed line. Note that an electrode106ais formed using the same layer as the electrode106. AlthoughFIGS.22A and22Beach illustrate an example in which the electrode106ais electrically connected to the electrode104c, one aspect of an embodiment of the present invention is not limited thereto. The electrode106ais not necessarily electrically connected to the electrode104c. The electrode106amay be electrically connected to the electrode101aor both the electrodes101aand104c. Alternatively, the electrode106ais not necessarily provided over the portion282. It is possible to form a capacitor that has the electrode101aformed using the same layer as the electrode101as one electrode and has the electrode106aas the other electrode.FIGS.22C to22EandFIGS.48A to48Eeach illustrate such an example. InFIGS.22C to22EandFIGS.48A to48E, for example, a capacitor is formed in a portion283surrounded by a dashed line. Note thatFIG.22Dcorresponds to a structure where part of the layer105bis removed fromFIG.22C. In the structure illustrated inFIG.22D, the layer105bin a region121cis not provided. Further,FIG.22Ecorresponds to a structure where the layer105bis removed in a wider width than the width of the electrode101a(in a horizontal direction in the diagram) inFIG.22D. Furthermore,FIGS.48C and48Deach illustrate a structure in which part of the layer105bis removed fromFIG.48AorFIG.48B. In each of the structures illustrated inFIGS.48C and48D, the layer105bin the region121cis not provided.FIG.48Ecorresponds to a structure where the layer105bis removed in a wider width than the width of the electrode101a(in a horizontal direction in the diagram) inFIG.48D. Note that inFIGS.22A to22EandFIGS.48A to48E, the electrode106amay be the electrode106, the electrode110, or an electrode formed using the same layer as the electrode110. The electrode101amay be the electrode101. The electrode104cmay be the electrode104. Note that each of the capacitors illustrated inFIGS.22A to22EandFIGS.48A to48Ecan be used as the capacitor provided between the gate and the source of the transistor100. Alternatively, for example, each of the capacitors illustrated inFIGS.22A to22EandFIGS.48A to48Ecan be used as a storage capacitor provided in a pixel. Alternatively, each of the capacitors illustrated inFIGS.22A to22EandFIGS.48A to48Ecan be used as a capacitor for holding a signal in a driver circuit. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, or part or all of Embodiment 7. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 7). Embodiment 9 In this embodiment, examples of materials of the insulating layers, the electrodes, the semiconductor layers, and the like in Embodiments 1 to 8 are described. The material of the semiconductor layer103in the transistor100is described below. Note that a similar material can be used for a semiconductor layer formed using the same layer as the semiconductor layer103. The semiconductor layer103in the transistor100may include a layer containing an oxide semiconductor (an oxide semiconductor layer). For example, a quaternary metal oxide such as an In—Sn—Ga—Zn—O-based oxide semiconductor; a ternary metal oxide such as an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-based oxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxide semiconductor, a Sn—Al—Zn—O-based oxide semiconductor, or a Hf—In—Zn—O-based oxide semiconductor; a binary metal oxide such as an In—Zn—O-based oxide semiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor, a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor, or an In—Ga—O-based oxide semiconductor; or a unary metal oxide such as an In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, or a Zn—O-based oxide semiconductor can be used as the oxide semiconductor. In addition, the oxide semiconductor may contain an element other than In, Ga, Sn, and Zn, for example, SiO2. For example, an In—Sn—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), tin (Sn), and zinc (Zn), and there is no limitation on the composition ratio. For example, an In—Ga—Zn—O-based oxide semiconductor means an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), and there is no limitation on the composition ratio. An In—Ga—Zn—O-based oxide semiconductor can be referred to as IGZO. The oxide semiconductor layer can be formed using an oxide semiconductor film. In the case where an In—Sn—Zn—O-based oxide semiconductor film is formed by sputtering, a target which has a composition ratio of In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, 20:45:35, or the like in an atomic ratio is used. In the case where an In—Zn—O-based oxide semiconductor film is formed by sputtering, a target has a composition ratio of In:Zn=50:1 to 1:2 in an atomic ratio (In2O3:ZnO=25:1 to 1:4 in a molar ratio), preferably In:Zn=20:1 to 1:1 in an atomic ratio (In2O3:ZnO=10:1 to 1:2 in a molar ratio), more preferably In:Zn=1.5:1 to 15:1 in an atomic ratio (In2O3:ZnO=3:4 to 15:2 in a molar ratio). For example, when the target has an atomic ratio of In:Zn:O=X:Y:Z, Z>1.5X+Y. In the case where an In—Ga—Zn—O-based oxide semiconductor film is formed by sputtering, a target can have a composition ratio of In:Ga:Zn=1:1:0.5, 1:1:1, or 1:1:2 in an atomic ratio. When the purity of the target is set to 99.99% or higher, alkali metal, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, hydride, or the like mixed into the oxide semiconductor film can be reduced. In addition, with the use of the target, the concentration of alkali metal such as lithium, sodium, or potassium can be reduced in the oxide semiconductor film. Note that it has been pointed out that an oxide semiconductor is insensitive to impurities, there is no problem when a considerable amount of metal impurities is contained in the film, and soda-lime glass which contains a large amount of alkali metal such as sodium (Na) and is inexpensive can be used (Kamiya, Nomura, and Hosono, “Carrier Transport Properties and Electronic Structures of Amorphous Oxide Semiconductors: The present status”,KOTAI BUTSURI(SOLID STATE PHYSICS), 2009, Vol. 44, pp. 621-633). But such consideration is not appropriate. Alkali metal is not an element included in an oxide semiconductor and thus is an impurity. Alkaline earth metal is also an impurity in the case where alkaline earth metal is not included in an oxide semiconductor. Alkali metal, in particular, Na becomes Na+when an insulating film which is in contact with an oxide semiconductor layer is an oxide and Na diffuses into the insulating film. In addition, in the oxide semiconductor layer, Na cuts or enters a bond between metal and oxygen which are included in an oxide semiconductor. As a result, for example, degradation of characteristics of a transistor, such as a normally-on state of the transistor due to a shift in the threshold voltage in a negative direction, or a decrease in mobility, occurs. A variation in characteristics also occurs. Such degradation of characteristics of the transistor and a variation in characteristics due to the impurity are outstanding when the concentration of hydrogen in the oxide semiconductor layer is sufficiently low. Thus, when the concentration of hydrogen in the oxide semiconductor layer is 1×1018/cm3or lower, preferably 1×1017/cm3or lower, the concentration of the impurity is preferably lowered. Specifically, the measurement value of a Na concentration by secondary ion mass spectrometry is preferably 5×1016/cm3or less, more preferably 1×1016/cm3or less, still more preferably 1×1015/cm3or less. Similarly, the measurement value of a Li concentration is preferably 5×1015/cm3or less, more preferably 1×1015/cm3or less. Similarly, the measurement value of a K concentration is preferably 5×1015/cm3or less, more preferably 1×1015/cm3or less. Note that the oxide semiconductor layer may be either amorphous or crystalline. The oxide semiconductor layer may be either single crystal or non-single-crystal. In the case of non-single-crystal, the oxide semiconductor layer may be either amorphous or polycrystalline. Further, the oxide semiconductor may have an amorphous structure including a crystalline portion or may be non-amorphous. For the oxide semiconductor layer, it is possible to use an oxide including a crystal with c-axis alignment (also referred to as c-axis aligned crystal (CAAC)) that has a phase having triangular, hexagonal, regular triangular, or regular hexagonal atomic order when seen from the direction perpendicular to the a-b plane and in which metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis direction. CAAC is described in detail with reference toFIGS.69A to69E,FIGS.70A to70C, andFIGS.71A to71C. Note that inFIGS.69A to69E,FIGS.70A to70C, andFIGS.71A to71C, the vertical direction corresponds to the c-axis direction and a plane perpendicular to the c-axis direction corresponds to the a-b plane, unless otherwise specified. When terms “upper half” and “lower half” are simply used, they refer to an upper half above the a-b plane and a lower half below the a-b plane (an upper half and a lower half with respect to the a-b plane). Further, inFIGS.69A to69E, an O atom surrounded by a circle represents a tetracoordinate O atom and an O atom surrounded by a double circle represents a tricoordinate O atom. FIG.69Aillustrates a structure including one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereinafter referred to as tetracoordinate O atoms) close to the In atom. A structure in which one In atom and oxygen atoms close to the In atom are only illustrated is called a subunit here. The structure inFIG.69Ais actually an octahedral structure, but is illustrated as a planar structure for simplicity. Note that three tetracoordinate O atoms exist in each of an upper half and a lower half inFIG.69A. In the subunit illustrated inFIG.69A, electric charge is 0. FIG.69Billustrates a structure including one pentacoordinate Ga atom, three tricoordinate oxygen atoms (hereinafter referred to as tricoordinate O atoms) close to the Ga atom, and two tetracoordinate O atoms close to the Ga atom. All the tricoordinate O atoms exist in the a-b plane. One tetracoordinate O atom exists in each of an upper half and a lower half inFIG.69B. An In atom can have the structure illustrated inFIG.69Bbecause the In atom can have five ligands. In a subunit illustrated inFIG.69B, electric charge is 0. FIG.69Cillustrates a structure including one tetracoordinate Zn atom and four tetracoordinate O atoms close to the Zn atom. InFIG.69C, one tetracoordinate O atom exists in an upper half and three tetracoordinate O atoms exists in a lower half. Alternatively, three tetracoordinate O atoms may exist in the upper half and one tetracoordinate O atom may exist in the lower half inFIG.69C. In a subunit illustrated inFIG.69C, electric charge is 0. FIG.69Dillustrates a structure including one hexacoordinate Sn atom and six tetracoordinate O atoms close to the Sn atom. InFIG.69D, three tetracoordinate O atoms exists in each of an upper half and a lower half. In a subunit illustrated in FIG.69D, electric charge is +1. FIG.69Eillustrates a subunit including two Zn atoms. InFIG.69E, one tetracoordinate O atom exists in each of an upper half and a lower half. In the subunit illustrated inFIG.69E, electric charge is −1. Here, a group of some of the subunits are referred to as one group, and some of the groups are referred to as one unit. Here, a rule of bonding the subunits to each other is described. The three O atoms in the upper half with respect to the hexacoordinate In atom inFIG.69Aeach have three proximity In atoms in the downward direction, and the three O atoms in the lower half each have three proximity In atoms in the upward direction. The one O atom in the upper half with respect to the pentacoordinate Ga atom inFIG.69Bhas one proximity Ga atom in the downward direction, and the one O atom in the lower half has one proximity Ga atom in the upward direction. The one O atom in the upper half with respect to the tetracoordinate Zn atom inFIG.69Chas one proximity Zn atom in the downward direction, and the three O atoms in the lower half each have three proximity Zn atoms in the upward direction. In this manner, the number of the tetracoordinate O atoms above the metal atom is equal to the number of the proximity metal atoms below the tetracoordinate O atoms. Similarly, the number of the tetracoordinate O atoms below the metal atom is equal to the number of the proximity metal atoms above the tetracoordinate O atoms. Since the coordination number of the O atom is 4, the sum of the number of the proximity metal atoms below the O atom and the number of the proximity metal atoms above the O atom is 4. Accordingly, when the sum of the number of the tetracoordinate O atoms above the metal atom and the number of the tetracoordinate O atoms below another metal atom is 4, the two kinds of subunits including the metal atoms can be bonded to each other. For example, in the case where a hexacoordinate metal (In or Sn) atom is bonded through three tetracoordinate O atoms in the upper half, the hexacoordinate metal atom is bonded to a pentacoordinate metal (Ga or In) atom or a tetracoordinate metal (Zn) atom. A metal atom having the above coordination number is bonded to another metal atom through a tetracoordinate O atom in the c-axis direction. Further, subunits are bonded to each other so that the total electric charge in a layer structure is 0. Thus, one group is constituted. FIG.70Aillustrates a model of one group included in a layer structure of an In—Sn—Zn—O-based material.FIG.70Billustrates a unit including three groups. Note thatFIG.70Cillustrates atomic order in the case of the layer structure inFIG.70Bobserved from the c-axis direction. InFIG.70A, for simplicity, a tricoordinate O atom is not illustrated and a tetracoordinate O atom is illustrated by a circle; the number in the circle shows the number of tetracoordinate O atoms. For example, three tetracoordinate O atoms existing in each of an upper half and a lower half with respect to a Sn atom are denoted by circled3. Similarly, inFIG.70A, one tetracoordinate O atom existing in each of an upper half and a lower half with respect to an In atom is denoted by circled1.FIG.70Aalso illustrates a Zn atom close to one tetracoordinate O atom in a lower half and three tetracoordinate O atoms in an upper half, and a Zn atom close to one tetracoordinate O atom in an upper half and three tetracoordinate O atoms in a lower half. In the group included in the layer structure of the In—Sn—Zn—O-based material inFIG.70A, in the order starting from the top, a Sn atom close to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to an In atom close to one tetracoordinate O atom in each of an upper half and a lower half, the In atom is bonded to a Zn atom close to three tetracoordinate O atoms in an upper half, the Zn atom is bonded to an In atom close to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Zn atom, the In atom is bonded to a subunit that includes two Zn atoms and is close to one tetracoordinate O atom in an upper half, and the subunit is bonded to a Sn atom close to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the subunit. Some of the groups are bonded to each other so that one unit is constituted. Here, electric charge for one bond of a tricoordinate O atom and electric charge for one bond of a tetracoordinate O atom can be assumed to be −0.667 and −0.5, respectively. For example, electric charge of a hexacoordinate or pentacoordinate In atom, electric charge of a tetracoordinate Zn atom, and electric charge of a pentacoordinate or hexacoordinate Sn atom are +3, +2, and +4, respectively. Thus, electric charge of a subunit including a Sn atom is +1. Consequently, an electric charge of −1, which cancels an electric charge of +1, is needed to form a layer structure including a Sn atom. As a structure having an electric charge of −1, the subunit including two Zn atoms as illustrated inFIG.69Ecan be given. For example, when one subunit including two Zn atoms is provided for one subunit including a Sn atom, electric charge is canceled, so that the total electric charge in the layer structure can be 0. An In atom can have either five ligands or six ligands. Specifically, when a unit illustrated inFIG.70Bis formed, an In—Sn—Zn—O-based crystal (In2SnZn3O8) can be obtained. Note that the layer structure of the obtained In—Sn—Zn—O-based crystal can be expressed as a composition formula, In2SnZn2O7(ZnO)m(m is 0 or a natural number). The above rule also applies to the following oxides: a quaternary metal oxide such as an In—Sn—Ga—Zn—O-based oxide; a ternary metal oxide such as an In—Ga—Zn—O-based oxide (also referred to as IGZO), an In—Al—Zn—O-based oxide, a Sn—Ga—Zn—O-based oxide, an Al—Ga—Zn—O-based oxide, or a Sn—Al—Zn—O-based oxide; a binary metal oxide such as an In—Zn—O-based oxide, a Sn—Zn—O-based oxide, an Al—Zn—O-based oxide, a Zn—Mg—O-based oxide, a Sn—Mg—O-based oxide, an In—Mg—O-based oxide, or an In—Ga—O-based oxide; or a unary metal oxide such as an In—O-based oxide, a Sn—O-based oxide, or a Zn—O-based oxide. For example,FIG.71Aillustrates a model of one group included in a layer structure of an In—Ga—Zn—O-based material. In the group included in the layer structure of the In—Ga—Zn—O-based material inFIG.71A, in the order starting from the top, an In atom close to three tetracoordinate O atoms in each of an upper half and a lower half is bonded to a Zn atom close to one tetracoordinate O atom in an upper half, the Zn atom is bonded to a Ga atom close to one tetracoordinate O atom in each of an upper half and a lower half through three tetracoordinate O atoms in a lower half with respect to the Zn atom, and the Ga atom is bonded to an In atom close to three tetracoordinate O atoms in each of an upper half and a lower half through one tetracoordinate O atom in a lower half with respect to the Ga atom. Some of the groups are bonded to each other so that one unit is constituted. FIG.71Billustrates a unit including three groups. Note thatFIG.71Cillustrates atomic order in the case of the layer structure inFIG.71Bobserved from the c-axis direction. Here, since electric charge of a hexacoordinate or pentacoordinate In atom, electric charge of a tetracoordinate Zn atom, and electric charge of a pentacoordinate Ga atom are +3, +2, and +3, respectively, electric charge of a subunit including an In atom, a Zn atom, and a Ga atom is 0. Thus, the total electric charge of a layer structure having a combination of such subunits is always 0. Here, since electric charge of a hexacoordinate or pentacoordinate In atom, electric charge of a tetracoordinate Zn atom, and electric charge of a pentacoordinate Ga atom are +3, +2, and +3, respectively, electric charge of a subunit including any of an In atom, a Zn atom, and a Ga atom is 0. Thus, the total electric charge of a group having a combination of such subunits is always 0. An oxide semiconductor film including CAAC (hereinafter also referred to as a CAAC film) can be formed by sputtering. The above material can be used as a target material. In the case where the CAAC film is formed by sputtering, the proportion of an oxygen gas in an atmosphere is preferably high. In the case where sputtering is performed in a mixed gas of argon and oxygen, for example, the proportion of an oxygen gas is preferably 30% or higher, more preferably 40% or higher because supply of oxygen from the atmosphere promotes crystallization of CAAC. In the case where the CAAC film is formed by sputtering, a substrate over which the CAAC film is formed is heated preferably to 150° C. or higher, more preferably to 170° C. or higher. This is because the higher the substrate temperature becomes, the more crystallization of CAAC is promoted. After heat treatment is performed on the CAAC film in a nitrogen atmosphere or in vacuum, heat treatment is preferably performed in an oxygen atmosphere or a mixed gas of oxygen and another gas. This is because oxygen deficiency due to the former heat treatment can be corrected by supply of oxygen from the atmosphere in the latter heat treatment. A film surface on which the CAAC film is formed (a deposition surface) is preferably flat. This is because the c-axis approximately perpendicular to the deposition surface exists in the CAAC film, so that deposition surface irregularities induce generation of grain boundaries in the CAAC film. Thus, planarization treatment such as chemical mechanical polishing (CMP) is preferably performed on the deposition surface before the CAAC film is formed. The average roughness of the deposition surface is preferably 0.5 nm or less, more preferably 0.3 nm or less. Note that an oxide semiconductor film formed by sputtering or the like contains moisture or hydrogen (including a hydroxyl group) as an impurity in some cases. In one embodiment of the present invention, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film (or an oxide semiconductor layer formed using an oxide semiconductor film) (in order to perform dehydration or dehydrogenation), heat treatment is performed on the oxide semiconductor film (the oxide semiconductor layer) in a reduced-pressure atmosphere, an inert gas atmosphere of nitrogen, a rare gas, or the like, an oxygen gas atmosphere, or ultra dry air (the moisture amount is 20 ppm (−55° C. by conversion into a dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less, in the case where measurement is performed by a dew point meter in a cavity ring-down laser spectroscopy (CRDS) method). By performing heat treatment on the oxide semiconductor film (the oxide semiconductor layer), moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer) can be eliminated. Specifically, heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 750° C., preferably higher than or equal to 400° C. and lower than the strain point of the substrate. For example, heat treatment may be performed at 500° C. for 3 to 6 minutes. When RTA is used for the heat treatment, dehydration or dehydrogenation can be performed in a short time; thus, treatment can be performed even at a temperature higher than the strain point of a glass substrate. After moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer) is eliminated in this manner, oxygen is added. Thus, oxygen defects, for example, in the oxide semiconductor film (the oxide semiconductor layer) can be reduced, so that the oxide semiconductor film (the oxide semiconductor layer) can be intrinsic (i-type) or substantially intrinsic. Oxygen can be added in such a manner that, for example, an insulating film including a region where the proportion of oxygen is higher than the stoichiometric proportion is formed in contact with the oxide semiconductor film (the oxide semiconductor layer), and then heat treatment is performed. In this manner, excessive oxygen in the insulating film can be supplied to the oxide semiconductor film (the oxide semiconductor layer). Thus, the oxide semiconductor film (the oxide semiconductor layer) can contain oxygen excessively. Oxygen contained excessively exists, for example, between lattices of a crystal included in the oxide semiconductor film (the oxide semiconductor layer). Note that the insulating film including a region where the proportion of oxygen is higher than the stoichiometric proportion may be applied to either the insulating film placed on an upper side of the oxide semiconductor film (the oxide semiconductor layer) or the insulating film placed on a lower side of the oxide semiconductor film (the oxide semiconductor layer) of the insulating films which are in contact with the oxide semiconductor film (the oxide semiconductor layer); however, it is preferable to apply such an insulating film to both the insulating films which are in contact with the oxide semiconductor film (the oxide semiconductor layer). The above effect can be enhanced with a structure where the oxide semiconductor film (the oxide semiconductor layer) is provided between the insulating films each including a region where the proportion of oxygen is higher than the stoichiometric proportion, which are used as the insulating films in contact with the oxide semiconductor film (the oxide semiconductor layer) and positioned on the upper side and the lower side of the oxide semiconductor film (the oxide semiconductor layer). Here, the insulating film including a region where the proportion of oxygen is higher than the stoichiometric proportion may be a single-layer insulating film or a plurality of insulating films stacked. Note that the insulating film preferably includes impurities such as moisture or hydrogen as little as possible. When hydrogen is contained in the insulating film, hydrogen enters the oxide semiconductor film (the oxide semiconductor layer) or oxygen in the oxide semiconductor film (the oxide semiconductor layer) is extracted by hydrogen, whereby the oxide semiconductor film has lower resistance (n-type conductivity); thus, a parasitic channel might be formed. Thus, it is important that a deposition method in which hydrogen is not used be employed in order to form the insulating film containing hydrogen as little as possible. A material having a high barrier property is preferably used for the insulating film. As the insulating film having a high barrier property, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum oxide film, an aluminum nitride oxide film, or the like can be used, for example. When a plurality of insulating films stacked are used, an insulating film having a low proportion of nitrogen, such as a silicon oxide film or a silicon oxynitride film, is formed on a side which is closer to the oxide semiconductor film (the oxide semiconductor layer) than the insulating film having a high barrier property. Then, the insulating film having a high barrier property is formed to overlap with the oxide semiconductor film (the oxide semiconductor layer) with the insulating film having a low proportion of nitrogen sandwiched therebetween. When the insulating film having a high barrier property is used, impurities such as moisture or hydrogen can be prevented from entering the oxide semiconductor film (the oxide semiconductor layer) or the interface between the oxide semiconductor film (the oxide semiconductor layer) and another insulating film and the vicinity thereof. In addition, the insulating film having a low proportion of nitrogen, such as a silicon oxide film or a silicon oxynitride film, is formed to be in contact with the oxide semiconductor film (the oxide semiconductor layer), so that the insulating film having a high barrier property can be prevented from being in direct contact with the oxide semiconductor film (the oxide semiconductor layer). Alternatively, addition of oxygen after moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer) is eliminated may be performed by performing heat treatment on the oxide semiconductor film (the oxide semiconductor layer) in an oxygen atmosphere. The heat treatment is performed at, for example, higher than or equal to 100° C. and lower than 350° C., preferably higher than or equal to 150° C. and lower than 250° C. It is preferable that an oxygen gas used for the heat treatment in an oxygen atmosphere do not include water, hydrogen, or the like. Alternatively, the purity of the oxygen gas which is introduced into a heat treatment apparatus is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher (that is, the impurity concentration in oxygen is 1 ppm or lower, preferably 0.1 ppm or lower). Alternatively, addition of oxygen after moisture or hydrogen in the oxide semiconductor film (the oxide semiconductor layer) is eliminated may be performed by ion implantation, ion doping, or the like. For example, oxygen made to be plasma with a microwave of 2.45 GHz may be added to the oxide semiconductor film (the oxide semiconductor layer). The thus formed oxide semiconductor layer can be used as the semiconductor layer103of the transistor100. In this manner, the transistor100with extremely low off-state current can be obtained. The semiconductor layer103of the transistor100may include microcrystalline silicon. Microcrystalline silicon is a semiconductor having an intermediate structure between amorphous and crystalline structures (including a single crystal structure and a polycrystalline structure). In microcrystalline silicon, columnar or needle-like crystals having a grain size of 2 to 200 nm, preferably 10 to 80 nm, more preferably 20 to 50 nm, still more preferably 25 to 33 nm have grown in a direction normal to a substrate surface. Thus, grain boundaries are formed at the interface of the columnar or needle-like crystals in some cases. The Raman spectrum of microcrystalline silicon, which is a typical example, shifts to a lower wavenumber side than 520 cm−1which represents single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm−1which represents single crystal silicon and 480 cm−1which represents amorphous silicon. Further, microcrystalline silicon contains hydrogen or halogen at a concentration of at least 1 atomic % to terminate a dangling bond. Furthermore, microcrystalline silicon contains a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, so that stability is increased and favorable microcrystalline silicon can be obtained. Such microcrystalline silicon is disclosed in, for example, U.S. Pat. No. 4,409,134. The semiconductor layer103of the transistor100may include amorphous silicon. The semiconductor layer103of the transistor100may include polycrystalline silicon. Alternatively, the semiconductor layer103of the transistor100may include an organic semiconductor, a carbon nanotube, or the like. The material of the electrode110is described below. Note that a similar material can be used for an electrode formed using the same layer as the electrode110. The electrode110can be formed using a light-transmissive conductive material. As the light-transmissive conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organoindium, organotin, zinc oxide, indium zinc oxide, or the like can be used. Note that the electrode110may have both a light-transmissive region and a reflective region. Thus, a transflective display device can be obtained. Alternatively, the electrode110may be formed using a reflective conductive material. Thus, a reflective display device can be obtained. Alternatively, a top-emission light-emitting device can be obtained in which light is emitted to a side opposite to a side in which a pixel is formed. In particular, in the case where a reflective conductive material is used for the electrode110, the aperture ratio can be increased when the electrode110is provided above the transistor100to overlap with the transistor100. The material of the electrode106is described below. Note that a similar material can be used for an electrode formed using the same layer as the electrode106. The electrode106can be formed using a light-transmissive conductive material. As the light-transmissive conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organoindium, organotin, zinc oxide, indium zinc oxide, or the like can be used. The material of the insulating layer105is described below. The insulating layer105may include an organic insulating layer. The insulating layer105may include an inorganic insulating layer. The insulating layer105may include a stack of an inorganic insulating layer and an organic insulating layer. For example, the layers105aand105ccan be inorganic insulating layers. The layer105bcan be an organic insulating layer. In the case where the insulating layer105or the layer105bis a color filter, a green organic insulating layer, a blue organic insulating layer, a red organic insulating layer, or the like can be used as the insulating layer105or the layer105b. In the case where the insulating layer105or the layer105bis a black matrix, a black organic insulating layer can be used as the insulating layer105or the layer105b. An acrylic resin, polyimide, polyamide, or the like can be used for the organic insulating layer. With the use of polyimide, degradation of a light-emitting element formed over the insulating layer105or the layer105bcan be reduced. Alternatively, a photosensitive material may be used for the organic insulating layer. A film including a photosensitive material can be etched without formation of a resist mask. The organic insulating layer may be formed by a droplet discharge method such as an inkjet method. Alternatively, a layer which is formed by a droplet discharge method such as an inkjet method and is etched may be used. For example, a layer which is formed by a droplet discharge method such as an inkjet method and is etched using a resist mask may be used. A silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like can be used for the inorganic insulating layer. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, or part or all of Embodiment 8. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 8). Embodiment 10 In this embodiment, one aspect of a method for manufacturing a semiconductor device is described. FIGS.59A to59Eillustrate an example of a method for manufacturing a semiconductor device with the structure illustrated inFIG.1A. The electrode101is formed over the insulating surface200, the insulating layer102is formed over the electrode101, and the semiconductor layer103which at least partly overlaps with at least part of the electrode101with the insulating layer102provided therebetween is formed (FIG.59A). The electrodes104aand104bare formed over the semiconductor layer103. An insulating film591is formed over the electrodes104aand104b. The insulating film591is formed using a positive photosensitive material (FIG.59B). Then, the insulating film591is subjected to exposure with the use of a half-tone mask592. The half-tone mask592has regions592a,592b, and592c, and these regions have different transmittances of light used for exposure. Here, (transmittance of the region592c)>(transmittance of the region592b)>(transmittance of the region592a) (FIG.59C). When the insulating film591is subjected to exposure with the use of the half-tone mask592, it is possible to form the insulating layer105that has the regions121and122and a through hole123. The region121is thinner than the region122(FIG.59D). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the insulating layer105, and at least part of the electrode110is formed over at least part of the region122(FIG.59E). In this manner, the semiconductor device can be manufactured. Note that although the insulating film591is formed using a positive photosensitive material, this embodiment is not limited thereto. The insulating film591may be formed using a negative photosensitive material. Alternatively, the insulating layer105may be formed in such a manner that the insulating film591is formed without the use of a photosensitive material, a resist is formed over the insulating film591, the resist is subjected to exposure with the use of a half-tone mask so that a resist mask is formed, and the insulating film591is etched with the use of the resist mask. FIGS.60A to60Eillustrate an example of a method for manufacturing a semiconductor device with the structure illustrated inFIG.1C. The electrode101is formed over the insulating surface200, and the insulating layer102, the semiconductor layer103, and the electrodes104aand104bare formed. The manufacturing steps up to this stage are similar to those inFIGS.59A and59B. An insulating film601ais formed over the electrodes104aand104b, and an insulating film601bis formed over the insulating film601a(FIG.60A). Then, a resist602is formed over the insulating film601b. The resist602is a positive resist. The resist602is subjected to exposure with the use of a half-tone mask603. The half-tone mask603has regions603a,603b, and603c, and these regions have different transmittances of light used for exposure. Here, (transmittance of the region603c)>(transmittance of the region603b)>(transmittance of the region603a) (FIG.60B). When the resist602is subjected to exposure with the use of the half-tone mask603, a resist mask604having three regions with different thicknesses is formed (FIG.60C). When the insulating films601aand601bare etched using the resist mask604, it is possible to form an insulating layer (a stack of the layers105aand105b) that has the regions121and122and the through hole123. The region121is thinner than the region122(FIG.60D). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the layer105b, and at least part of the electrode110is formed over at least part of the region122(FIG.60E). In this manner, the semiconductor device can be manufactured. Note that although the resist602is a positive resist in the manufacturing steps inFIGS.60A to60E, this embodiment is not limited thereto. The resist602may be formed using a negative photosensitive material. Alternatively, the insulating layer (the stack of the layers105aand105b) may be formed in such a manner that the resist602is not used, the insulating film601bis formed using a photosensitive material, and the insulating film601bis subjected to exposure with the use of a half-tone mask. Although a half-tone mask is used in the manufacturing steps inFIGS.60A to60E, this embodiment is not limited thereto. For example, manufacturing steps as illustrated inFIGS.61A to61Dcan be employed. The manufacturing step up to the step inFIG.61Ais similar to that inFIG.60A. In the manufacturing steps inFIGS.61A to61D, the insulating film601bis etched so that the region121and an opening124are formed. In this manner, the layer105bis formed (FIG.61B). After that, the insulating film601awhich is exposed through the opening124is etched so that the through hole123is formed. In that case, part of the layer105bmay be further etched. Thus, it is possible to form an insulating layer (a stack of the layers105aand105b) that has the regions121and122and the through hole123. The region121is thinner than the region122(FIG.61C). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the layer105b, and at least part of the electrode110is formed over at least part of the region122(FIG.61D). In this manner, the semiconductor device can be manufactured. Note that although the insulating films601aand601bare stacked and then etched in the manufacturing steps inFIGS.61A to61D, this embodiment is not limited thereto. For example, manufacturing steps as illustrated inFIGS.62A to62Ecan be employed. The step up to the step of forming the insulating film601a(FIG.62A) is similar to the manufacturing step inFIG.61A. After the insulating film601ais formed, the insulating film601ais etched so that the layer105ahaving an opening125is formed (FIG.62B). Then, the insulating film601bis formed to cover the layer105a(FIG.62C). Then, the insulating film601bis etched. In that case, part of the layer105amay be further etched. Thus, it is possible to form an insulating layer (a stack of the layers105aand105b) that has the regions121and122and the through hole123. The region121is thinner than the region122(FIG.62D). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the layer105b, and at least part of the electrode110is formed over at least part of the region122(FIG.62E). In this manner, the semiconductor device can be manufactured. Note that in the manufacturing steps inFIGS.60A to60E,FIGS.61A to61D, andFIGS.62A to62E, the insulating layer105is constituted of two films (the insulating films601aand601b), and only one of the films is selectively removed so that the regions121and122are formed. However, this embodiment is not limited thereto. The insulating layer105may be constituted of m (m is a natural number) films, and only n (n is a natural number smaller than m) films among m films may be selectively removed so that the regions121and122are formed. For example,FIGS.63A to63Eillustrate steps of forming the insulating layer105using three films. The steps inFIGS.63A to63Ecorrespond to steps of manufacturing a semiconductor device with the structure illustrated inFIG.26C. The step up to the step inFIG.63Aare similar to the manufacturing step inFIG.60A After the insulating film601bis formed, the insulating film601bis etched so that the layer105bhaving openings126and127is formed (FIG.63B). Then, an insulating film601cis formed to cover the layer105b(FIG.63C). Then, the insulating films601aand601care etched so that the through hole123is formed. Thus, it is possible to form an insulating layer (a stack of the layers105a,105b, and105c) that has the regions121and122and the through hole123. The region121is thinner than the region122(FIG.63D). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the layer105c, and at least part of the electrode110is formed over at least part of the region122(FIG.63E). In this manner, the semiconductor device can be manufactured. Note thatFIGS.64A to64Eillustrate steps of forming the insulating layer105using three films. These steps are different from the steps inFIGS.63A to63E. The steps inFIGS.64A to64Ecorrespond to steps of manufacturing a semiconductor device in the case of the layer105bcovering an end of the layer105ain the structure illustrated inFIG.26C. First, an insulating film is etched so that the layer105ahaving an opening128ais formed, and then, the insulating film601bis formed (FIG.64A). The insulating film601bis etched so that the layer105bhaving the opening127and an opening128is formed (FIG.64B). Here, the opening128is formed in the opening128aand has a smaller diameter than the opening128a. Then, the insulating film601cis formed to cover the layer105b(FIG.64C). Then, the insulating film601cis etched so that the through hole123is formed. Thus, it is possible to form an insulating layer (a stack of the layers105a,105b, and105c) that has the regions121and122and the through hole123. The region121is thinner than the region122(FIG.64D). After that, the electrode106which at least partly overlaps with at least part of the semiconductor layer103with the region121provided therebetween is formed over the layer105c, and at least part of the electrode110is formed over at least part of the region122(FIG.64E). In this manner, the semiconductor device can be manufactured. Note thatFIGS.59A to59E,FIGS.60A to60E,FIGS.61A to61D,FIGS.62A to62E,FIGS.63A to63E, andFIGS.64A to64Eillustrate steps of manufacturing semiconductor devices obtained by some modifications of the semiconductor device inFIG.1A,FIG.1C, orFIG.26C; however, the semiconductor devices with the other structures in the above embodiments can be manufactured similarly. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, or part or all of Embodiment 9. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 9). Embodiment 11 In this embodiment, an example in which any of the semiconductor devices in Embodiments 1 to 10 is applied to a display device is described. Any of the semiconductor devices in Embodiments 1 to 10 can be used for a pixel in a liquid crystal display device or the like. FIGS.52A and52Bare examples of a cross-sectional view of a pixel in a liquid crystal display device.FIGS.52A and52Bare cross-sectional views in the case of the semiconductor device with the structure illustrated inFIG.1Capplied to a liquid crystal display device. Note that inFIGS.52A and52B, the same portions as those inFIGS.1A to1Eare denoted by the same reference numerals, and the description thereof is omitted. InFIGS.52A and52B, the transistor100can be provided in a pixel. The electrode110can be a pixel electrode. The layer105bcan be a color filter and/or a black matrix. InFIG.52A, a protrusion510is provided in the region122. The protrusion510can function as a spacer. Thus, a gap between a substrate over which the transistor100is formed (hereinafter referred to as a pixel substrate) and a substrate for sealing a liquid crystal layer (hereinafter referred to as a counter substrate) can be controlled with the protrusion510. Note that a black matrix may be formed using the protrusion510. Alternatively, the protrusion510can function as a rib for controlling alignment of liquid crystal molecules. With the protrusion510, a direction in which liquid crystal molecules are aligned can be controlled. Note thatFIGS.52A and52Bdo not illustrate the liquid crystal layer, an electrode (hereinafter referred to as a counter electrode) which forms a pair with the pixel electrode, and the counter substrate. The counter electrode may be provided using either the pixel substrate or the counter substrate. Although an alignment film is not illustrated, the alignment film may or may not be provided. In the structure illustrated inFIG.52A, as illustrated inFIG.52B, layers510aand510bmay be provided to fill regions where the insulating layer105is thin or the insulating layer105is not provided (for example, regions where the layer105bis removed). Thus, unevenness of portions over the pixel substrate that face the liquid crystal layer can be reduced. The layers510aand510bmay be formed using a material that is different from or the same as the material of the protrusion510. A black matrix may be formed using any one of or all of the layer510a, the layer510b, and the protrusion510. Note that inFIG.52B, one of the layers510aand510bis not necessarily provided. For example, only the layer510amay be provided. Note that inFIGS.52A and52B, the protrusion510and the layers510aand510bcan be obtained by processing of an insulating layer by photolithography. Alternatively, the protrusion510and the layers510aand510bcan be formed using a photosensitive material. Note that the protrusion510and the layers510aand510bcan be formed by a droplet discharge method such as an inkjet method. AlthoughFIGS.52A and52Beach illustrate an example in which the protrusion510is provided over the pixel substrate, this embodiment is not limited thereto. The protrusion510may be provided on the counter substrate. AlthoughFIGS.52A and52Beach illustrate an example in which the protrusion510is provided to overlap with the electrode110, this embodiment is not limited thereto. The protrusion510can be provided so as not to overlap with the electrode110. Alternatively, the protrusion510can be provided so as to overlap with the electrode110and so as not to overlap with another part of the electrode110. Further, the protrusion510may be provided for each pixel or each plurality of pixels. The protrusion510may be provided to partly overlap with a wiring of the pixel or may be provided to partly overlap with the black matrix. AlthoughFIGS.52A and52Beach illustrate an example in which the semiconductor device inFIG.1Cis applied to a liquid crystal display device, this embodiment is not limited thereto. Any of the semiconductor devices in Embodiments 1 to 10 can be applied to a liquid crystal display device. For example, any of the semiconductor devices in Embodiments 1 to 10 can be applied to a liquid crystal display device, and any of the protrusion510, the layer510a, and the layer510bcan be provided, as inFIGS.52A and52B. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, part or all of Embodiment 9, or part or all of Embodiment 10. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 10). Embodiment 12 In this embodiment, an example in which any of the semiconductor devices in Embodiments 1 to 10 is applied to a display device is described. Any of the semiconductor devices in Embodiments 1 to 10 can be used for a pixel in a liquid crystal display device or the like, for example. FIGS.55A to55Fare examples of a circuit diagram of one pixel in a pixel portion of a liquid crystal display device. The pixel includes a transistor, a capacitor, and a liquid crystal element. The pixel further includes a gate signal line551, a source signal line552, a capacitor line553, and the like. The source signal line552can also be referred to as a video signal line. Note that one pixel illustrated in each ofFIGS.55A to55Fincludes a subpixel. The transistor100in any of Embodiments 1 to 10 can be used as the transistor.FIG.55Gshows the symbols of the transistor used inFIGS.55A to55F.FIG.55Gshows the symbols of the transistor and a correspondence between the symbols of the transistor and the transistor100in any of Embodiments 1 to 10. FIG.55Hexcerpts the liquid crystal element fromFIGS.55A to55F. As illustrated inFIG.55H, the liquid crystal element includes the electrode110(corresponding to a pixel electrode) and an electrode550(corresponding to a counter electrode). A liquid crystal layer is provided between the electrode110and the electrode550. Further, the parasitic capacitance or the capacitor in Embodiment 7 or Embodiment 8 can be used as the capacitor inFIGS.55A to55F. Any of the semiconductor devices in Embodiments 1 to 10 can be used for a pixel in a display device including an EL element (e.g., an organic light-emitting element) (hereinafter referred to as an EL display device) or a light-emitting device. FIGS.56A to56Care examples of a circuit diagram of a pixel in an EL display device. The pixel inFIGS.56A to56Cincludes an EL element560, a transistor562, a transistor563, and a capacitor564. The pixel further includes the gate signal line551, the source signal line552, the capacitor line553, a power supply line561, and the like. The source signal line552is also referred to as a video signal line. The transistor562has a function of controlling whether to supply a video signal to a gate of the transistor563. The transistor563has a function of controlling current to be supplied to the EL element560. The transistor100in any of Embodiments 1 to 10 can be used as the transistor. The symbols of the transistor and a correspondence between the symbols of the transistor and the transistor100in any of Embodiments 1 to 10 are as shown inFIG.55G. Further, any of the semiconductor devices in Embodiments 1 to 10 can be used for a driver circuit in a liquid crystal display device, an EL display device, or the like. For example, any of the semiconductor devices in Embodiments 1 to 10 can be used for a driver circuit such as a scan line driver circuit or a signal line driver circuit for outputting a signal to a pixel.FIGS.57A and57Billustrate examples of part of the driver circuit. The transistor100in any of Embodiments 1 to 10 can be used as some or all of transistors (transistors701,702,703,704,705,706,707,708,709,710,711,712,713,715,801,802,803,804,805,806,807,808,809,810,811,812,813,814,815,816, and817) included in the driver circuit. Further, the parasitic capacitance or the capacitor in Embodiment 7 or Embodiment 8 can be used as a capacitor714inFIG.57A. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, part or all of Embodiment 9, part or all of Embodiment 10, or part or all of Embodiment 11. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 11). Embodiment 13 In this embodiment, an example in which any of the semiconductor devices in Embodiments 1 to 10 is applied to a display device such as a liquid crystal display device is described. FIG.53andFIGS.58A and58Billustrate one aspect of the structure of a pixel in a liquid crystal display device. A cross-sectional view taken along line A1-A2in a top view ofFIG.53corresponds toFIG.58A or58B. InFIG.53andFIGS.58A and58B, a pixel530includes the transistor100, a capacitor531, and a liquid crystal element (or a display element). Note that the pixel530may be a subpixel.FIG.53andFIGS.58A to58Dillustrate only the electrode110corresponding to a pixel electrode of the liquid crystal element (or the display element), and do not illustrate a counter electrode (a common electrode). Any of the variety of structures in Embodiments 1 to 10 can be used as the structure of the transistor100. Thus, the structure of the transistor100is similar to any of the structures in Embodiments 1 to 10. Accordingly, the same portions as those in any of the structures in Embodiments 1 to 10 are denoted by the same reference numerals, and the description thereof is omitted. Note thatFIG.58Aillustrates an example in which the transistor100with the structure inFIG.1Ais used.FIG.58Billustrates an example in which the transistor100with the structure inFIG.1Cis used. Further, the parasitic capacitance or the capacitor in Embodiment 7 or Embodiment 8 can be used as the capacitor531. Note thatFIG.58Aillustrates an example in which the capacitor531is formed in the region121cwhere the insulating layer105is made thin.FIG.58Billustrates an example in which the capacitor531is formed in the region121cfrom which the layer105bis removed. The structure of the capacitor531inFIG.58Bcorresponds to the structure of the capacitor inFIG.22D. The electrode106of the transistor100is electrically connected to the electrode101athrough an opening501a. The electrode101of the transistor100functions as both a gate electrode of the transistor and a gate line. The electrode101ais provided in parallel with the electrode101. The electrode101afunctions as both a wiring for applying a potential to the electrode106of the transistor100and a capacitor line in pixels (or subpixels) in an adjacent row. The electrode104aof the transistor100functions as both one of a source electrode and a drain electrode and a source line. The source line is provided to intersect with the gate line. The electrode104bof the transistor100functions as the other of the source electrode and the drain electrode, and is electrically connected to the electrode110through an opening501b. One of a pair of electrodes of the capacitor531is the electrode110, and the other electrode of the capacitor531is the electrode101a. Note that the electrode101acan be formed using, for example, the same layer and the same material as the electrode101. Note that the electrodes101aand101may be formed using different materials. FIG.54andFIGS.58C and58Dillustrate another aspect of the structure of a pixel in a liquid crystal display device. A cross-sectional view taken along line A1-A2in a top view ofFIG.54corresponds toFIG.58C or58D. InFIG.54andFIGS.58C and58D, the pixel530includes the transistor100, a capacitor532, and a liquid crystal element (or a display element). Note that the pixel530may be a subpixel. The structure of the transistor100is similar to any of the structures in Embodiments 1 to 10. Accordingly, the same portions as those in any of the structures in Embodiments 1 to 10 are denoted by the same reference numerals, and the description thereof is omitted. Note thatFIG.58Cillustrates an example in which the transistor100with the structure inFIG.1Ais used.FIG.58Dillustrates an example in which the transistor100with the structure inFIG.1Cis used. In this manner, any of the variety of structures in Embodiments 1 to 10 can be used as the structure of the transistor100. Further, the parasitic capacitance or the capacitor in Embodiment 7 or Embodiment 8 can be used as the capacitor532. Note thatFIG.58Cillustrates an example in which the capacitor532is formed in the region121cwhere the insulating layer105is made thin.FIG.58Dillustrates an example in which the capacitor532is formed in the region121cfrom which the layer105bis removed. The structure of the capacitor532inFIG.58Dcorresponds to the structure of the capacitor inFIG.22E. The electrode106of the transistor100is electrically connected to the electrode101athrough an opening502a. The electrode101of the transistor100functions as both a gate electrode of the transistor and a gate line. An electrode101bis provided in parallel with the electrode101. The electrode101bfunctions as a capacitor line. The electrode104aof the transistor100functions as both one of a source electrode and a drain electrode and a source line. The source line is provided to intersect with the gate line. The electrode104bof the transistor100functions as the other of the source electrode and the drain electrode, and is electrically connected to the electrode110through an opening502b. One of a pair of electrodes of the capacitor532is the electrode110, and the other electrode of the capacitor532is the electrode101b. Note that the electrode101bcan be formed using, for example, the same layer and the same material as the electrode101. Note that the electrodes101band101may be formed using different materials. Note thatFIG.54illustrates an example in which the electrode110has a plurality of openings; however, this embodiment is not limited thereto. Further, the structure illustrated inFIG.53may be a structure in which the electrode110has a plurality of openings. The electrode110can have a given shape. InFIG.53,FIG.54, andFIGS.58A to58D, the electrode110can be a light-transmissive electrode. Alternatively, the electrode110can be an electrode having both a reflective region and a light-transmissive region. When the electrode110is an electrode having both a reflective region and a light-transmissive region, the liquid crystal display device can be transflective. In the case where the electrode110is an electrode having both a reflective region and a light-transmissive region, the electrode106can be formed using the same layer and the same material as a layer provided with a reflective electrode included in the reflective region. Thus, the semiconductor layer103of the transistor100can be shielded from light. The electrode having both the reflective region and the light-transmissive region can be formed by etching of a stack of a light-transmissive film and a reflective film with the use of a half-tone mask. Note that a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ various modes and can include various elements. For example, a display medium whose contrast, luminance, reflectivity, transmittance, or the like is changed by electromagnetic action, such as an EL (electroluminescence) element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor which emits light in accordance with current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, an electrowetting element, a grating light valve (GLV), a plasma display panel (PDP), a digital micromirror device (DMD), a piezoelectric ceramic display, or a carbon nanotube, can be used as a display element, a display device, a light-emitting element, or a light-emitting device. Display devices having EL elements include an EL display and the like. Display devices having electron emitters include a field emission display (FED), an SED-type flat panel display (SED: surface-conduction electron-emitter display), and the like. Display devices having liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display) and the like. Display devices having electronic ink or electrophoretic elements include electronic paper and the like. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, part or all of Embodiment 9, part or all of Embodiment 10, part or all of Embodiment 11, or part or all of Embodiment 12. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 12). Embodiment 14 In this embodiment, an example in which a display device is applied to a display module is described. FIG.72illustrates a display module. The display module inFIG.72includes a housing901, a display device902, a backlight unit903, and a housing904. The display device902is electrically connected to a driver IC905. Power source voltage or a signal is supplied to the backlight unit903through a terminal906. Note that this embodiment is not limited to the display module inFIG.72, and a display module having a touch panel may be used. The display module may have a flexible printed circuit (FPC). InFIG.72, the driver IC905may be electrically connected to the display device902through a flexible printed circuit (FPC). Further, the display module may have an optical film such as a polarizing plate or a retardation film. This embodiment is obtained by performing change, addition, modification, removal, application, superordinate conceptualization, or subordinate conceptualization on part or all of Embodiment 1, part or all of Embodiment 2, part or all of Embodiment 3, part or all of Embodiment 4, part or all of Embodiment 5, part or all of Embodiment 6, part or all of Embodiment 7, part or all of Embodiment 8, part or all of Embodiment 9, part or all of Embodiment 10, part or all of Embodiment 11, part or all of Embodiment 12, or part or all of Embodiment 13. Thus, this embodiment can be freely combined or replaced with another embodiment (e.g., any one of Embodiments 1 to 13). Embodiment 15 In this embodiment, examples of electronic devices are described. FIGS.67A to67HandFIGS.68A to68Dillustrate electronic devices. These electronic devices can include a housing5000, a display portion5001, a speaker5003, an LED lamp5004, operation keys5005(including a power switch or an operation switch), a connection terminal5006, a sensor5007(a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, smell, or infrared ray), a microphone5008, and the like. FIG.67Aillustrates a portable computer, which can include a switch5009, an infrared port5010, and the like in addition to the above objects.FIG.67Billustrates a portable image reproducing device provided with a memory medium (e.g., a DVD reproducing device), which can include a second display portion5002, a memory medium read portion5011, and the like in addition to the above objects.FIG.67Cillustrates a goggle-type display, which can include the second display portion5002, a support5012, an earphone5013, and the like in addition to the above objects.FIG.67Dillustrates a portable game machine, which can include the memory medium read portion5011and the like in addition to the above objects.FIG.67Eillustrates a digital camera with a television reception function, which can include an antenna5014, a shutter button5015, an image reception portion5016, and the like in addition to the above objects.FIG.67Fillustrates a portable game machine, which can include the second display portion5002, the memory medium read portion5011, and the like in addition to the above objects.FIG.67Gillustrates a television receiver, which can include a tuner, an image processing portion, and the like in addition to the above objects.FIG.67Hillustrates a portable television receiver, which can include a charger5017capable of transmitting and receiving signals and the like in addition to the above objects.FIG.68Aillustrates a display, which can include a support base5018and the like in addition to the above objects.FIG.68Billustrates a camera, which can include an external connection port5019, a shutter button5015, an image reception portion5016, and the like in addition to the above objects.FIG.68Cillustrates a computer, which can include a pointing device5020, the external connection port5019, a reader/writer5021, and the like in addition to the above objects.FIG.68Dillustrates a mobile phone, which can include a transmitter, a receiver, a tuner of 1seg partial reception service for mobile phones and mobile terminals, and the like in addition to the above objects. The electronic devices illustrated inFIGS.67A to67HandFIGS.68A to68Dcan have a variety of functions, for example, a function of displaying a lot of information (e.g., a still image, a moving image, and a text image) on a display portion; a touch panel function; a function of displaying a calendar, date, time, and the like; a function of controlling processing with a lot of software (programs); a wireless communication function; a function of being connected to a variety of computer networks with a wireless communication function; a function of transmitting and receiving a lot of data with a wireless communication function; a function of reading a program or data stored in a memory medium and displaying the program or data on a display portion. Further, the electronic device including a plurality of display portions can have a function of displaying image information mainly on one display portion while displaying text information on another display portion, a function of displaying a three-dimensional image by displaying images where parallax is considered on a plurality of display portions, or the like. Furthermore, the electronic device including an image receiving portion can have a function of photographing a still image, a function of photographing a moving image, a function of automatically or manually correcting a photographed image, a function of storing a photographed image in a memory medium (an external memory medium or a memory medium incorporated in the camera), a function of displaying a photographed image on the display portion, or the like. Note that functions which can be provided for the electronic devices illustrated inFIGS.67A to67HandFIGS.68A to68Dare not limited them, and the electronic devices can have a variety of functions. The electronic devices in this embodiment each include a display portion for displaying some kind of information. Next, application examples of semiconductor devices are described. FIG.68Eillustrates an example in which a semiconductor device is incorporated in a building structure.FIG.68Eillustrates a housing5022, a display portion5023, a remote controller5024which is an operation portion, a speaker5025, and the like. The semiconductor device is incorporated in the building structure as a wall-hanging type and can be provided without requiring a large space. FIG.68Fillustrates another example in which a semiconductor device is incorporated in a building structure. A display panel5026is incorporated in a prefabricated bath unit5027, so that a bather can view the display panel5026. Note that although this embodiment describes the wall and the prefabricated bath unit as examples of the building structures, this embodiment is not limited thereto. The semiconductor devices can be provided in a variety of building structures. Next, examples in which semiconductor devices are incorporated in moving objects are described. FIG.68Gillustrates an example in which a semiconductor device is incorporated in a car. A display panel5028is incorporated in a car body5029of the car and can display information related to the operation of the car or information input from inside or outside of the car on demand. Note that the display panel5028may have a navigation function. FIG.68Hillustrates an example in which a semiconductor device is incorporated in a passenger airplane.FIG.68Hillustrates a usage pattern when a display panel5031is provided for a ceiling5030above a seat of the passenger airplane. The display panel5031is incorporated in the ceiling5030through a hinge portion5032, and a passenger can view the display panel5031by stretching of the hinge portion5032. The display panel5031has a function of displaying information by the operation of the passenger. Note that although bodies of a car and an airplane are illustrated as examples of moving objects in this embodiment, this embodiment is not limited to them. The semiconductor devices can be provided for a variety of objects such as two-wheeled vehicles, four-wheeled vehicles (including cars, buses, and the like), trains (including monorails, railroads, and the like), and vessels. Note that in this specification and the like, in a diagram or a text described in one embodiment, part of the diagram or the text is taken out, and one embodiment of the invention can be constituted. Thus, in the case where a diagram or a text related to a certain portion is described, the context taken out from part of the diagram or the text is also disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Therefore, for example, in a diagram or a text in which one or more active elements (e.g., transistors or diodes), wirings, passive elements (e.g., capacitors or resistors), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, or the like are described, part of the diagram or the text is taken out, and one embodiment of the invention can be constituted. For example, M circuit elements (e.g., transistors or capacitors) (M is an integer, where M<N) are taken out from a circuit diagram in which N circuit elements (e.g., transistors or capacitors) (N is an integer) are provided, and one embodiment of the invention can be constituted. As another example, M layers (M is an integer, where M<N) are taken out from a cross-sectional view in which N layers (N is an integer) are provided, and one embodiment of the invention can be constituted. As another example, M elements (M is an integer, where M<N) are taken out from a flow chart in which N elements (N is an integer) are provided, and one embodiment of the invention can be constituted. Note that in this specification and the like, in a diagram or a text described in one embodiment, in the case where at least one specific example is described, it will be readily appreciated by those skilled in the art that a broader concept of the specific example can be derived. Thus, in the diagram or the text described in one embodiment, in the case where at least one specific example is described, a broader concept of the specific example is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Note that in this specification and the like, a content described in at least a diagram (or may be part of the diagram) is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Thus, when a certain content is described in a diagram, the content is disclosed as one embodiment of the invention even when the content is not described with a text, and one embodiment of the invention can be constituted. Similarly, part of a diagram that is taken out from the diagram is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. This application is based on Japanese Patent Application serial no. 2011-103344 filed with Japan Patent Office on May 5, 2011, the entire contents of which are hereby incorporated by reference. | 151,244 |
11942484 | DETAILED DESCRIPTION In general, according to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film. Embodiments will be described hereinafter with reference to the accompanying drawings. Incidentally, the disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc. of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Besides, in the specification and drawings, the structural elements having functions, which are identical or similar to the functions of the structural elements described in connection with preceding drawings, are denoted by like reference numerals, and an overlapping detailed description is omitted unless necessary. Note that, in the description of the present application, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z. FIG.1is a cross-sectional view of the structure of a semiconductor device of an embodiment. The semiconductor device1depicted is a thin film transistor (TFT) substrate including a plurality of thin film transistors TR1and TR2. The semiconductor device1includes, for example, an insulating substrate10, undercoat layer UC, semiconductor layer SC1, insulating film11, gate electrode ML1, gate electrode ML2, insulating film12, insulating film13, block layer HB, semiconductor layer SC2, insulating film14, and insulating film15. Note that the insulating films11to15may be referred to as first insulating film, second insulating film, third insulating film, . . . , and/or interlayer insulating film. This includes that the insulating film11is referred to as interlayer insulating film, insulating film12is referred to as first insulating film, insulating film13is referred to as second insulating film, and fourth insulating film14is referred to as interlayer insulating film. Furthermore, the semiconductor layer SC1may be referred to as first semiconductor layer and the semiconductor layer SC2may be referred to as second semiconductor layer. The insulating substrate10is formed of, for example, a light-transmissive glass substrate or light-transmissive resin substrate. An insulating undercoat layer UC is disposed on the insulating substrate10. The undercoat layer UC may be a monolayer or a multilayer, and the multilayer includes, for example, a silicon nitride layer and a silicon oxide layer. The semiconductor layer SC1is disposed above the insulating substrate10. In the example depicted, the semiconductor layer SC1is formed on the undercoat layer UC. The semiconductor layer SC1is disposed between the insulating substrate10and the block layer HB. The semiconductor layer SC1is formed of a silicon semiconductor, and in the example depicted, is formed of a polycrystalline silicon (polysilicon). The semiconductor layer SC1includes a high resistance area SCc and low resistance areas SCa and SCb resistance of which is lower than that of the high resistance area SCc. The low resistance areas SCa and SCb are positioned at the ends of the high resistance area SCc. The low resistance areas SCa and SCb contain ionic impurities concentrated higher than that of the high resistance area SCc. The insulating film11covers the semiconductor layer SC1. In the example depicted, the insulating film11is disposed above the undercoat layer UC. For example, the insulating film11is formed of a silicon oxide. The gate electrode ML1is disposed on the insulating film11and is opposed to the semiconductor layer SC1with the insulating film11interposed therebetween. The gate electrode ML1is opposed to the high resistance area SCc of the semiconductor layer SC1. The gate electrode ML2is disposed above the insulating film11and is apart from the gate electrode ML1. The gate electrodes ML1and ML2each include a metal layer of good conductivity. In the example depicted, the gate electrodes ML1and ML2are formed on the same layer, and thus, they can be manufactured at the same time with the same material. The insulating film12is disposed between the semiconductor layer SC1and the semiconductor layer SC2. The insulating film12is disposed on the insulating film11to cover the gate electrodes ML1and ML2. The insulating film12is formed of an insulative material containing hydrogen therein. In this example, the insulating film12is formed of a silicon nitride. The insulating film13is disposed above the insulating film12. In the example depicted, the insulating film13is disposed between the insulating film12and the block layer HB, and contacts the lower surface HBa of the block layer HB which will be described later. The insulating film13is preferably formed of a material which can release oxygen in a high temperature such as a silicon oxide. The block layer HB is disposed between the insulating film12and the semiconductor layer SC2. The block layer HB includes the lower surface HBa opposed to the insulating substrate10and the upper surface HBb disposed in the opposite side of the lower surface HBa. In the example depicted, the block layer HB is disposed on the insulating film13. In the example depicted, the block layer HB continuously extends to a position opposed to the semiconductor layer SC1and a position opposed to the semiconductor layer SC2. The block layer HB exerts hydrogen diffusion lower than the insulating film12and the insulating film13. Therefore, the block layer HB can suppress diffusion of hydrogen from one surface of the block layer HB to the other surface thereof. In the example depicted, the block layer HB can suppress the hydrogen diffusion from the insulating films11,12, and13, undercoat layer UC, and semiconductor layer SC1positioned in the lower surface HBa side to the semiconductor layer SC2positioned in the upper surface HBb side. The block layer HB may have an even thickness or an uneven thickness. In the example depicted, the block layer HB has steps in the upper surface HBb in positions opposed to outer edges of electrodes ML3aand ML3bwhich will be described later, and thus, the thickness of the area opposed to the semiconductor layer SC2is greater than the thickness of the area opposed to the semiconductor layer SC1. The block layer HB is preferably formed of an insulating material in order to suppress the formation of an unnecessary capacitance with a conductive member such as gate electrode ML1or semiconductor layer SC1and to prevent a short of a channel layer when the upper surface HBb of the block layer HB and the lower surface SC2aof the semiconductor layer SC2contact. The block layer HB is formed of a metal oxide such as AlOx, TiOx, ZrOx, TaOx, or HfOx, or SiNxor SiON which contains SiF4as its base material and low hydrogen. In consideration of hydrogen blocking performance and light transmissivity, the block layer HB is preferably formed of aluminum oxide (AlOx). The semiconductor layer SC2is disposed above the semiconductor layer SC1than is the insulating substrate10. The semiconductor layer SC2has the lower surface SC2ato be opposed to the insulating substrate10. In the example depicted, the semiconductor layer SC2is disposed on the block layer HB and contacts the upper surface HBb of the block layer HB. The semiconductor layer SC2is opposed to the gate electrode ML2. The semiconductor layer SC2is formed of a semiconductor of metal oxide. In consideration of semiconductor performance, the metal oxide in the semiconductor layer SC2preferably contains at least one of indiu, gallium, zinc, and tin. One end of the semiconductor layer SC2contacts the electrode ML3aand the other end contacts the electrode ML3b. In the example depicted, the electrodes ML3aand ML3bextend to the outside of the semiconductor layer SC2to be positioned above the block layer HB. The insulating film14is disposed on the block layer HB and covers the semiconductor layer SC2and the electrodes ML3aand ML3b. The insulating film14is formed of, for example, silicon oxide and is formed thicker than the insulating films11,12, and13. The insulating film15is disposed on the insulating film14. The insulating film15is formed of, for example, silicon nitride. Note that the insulating film15preferably exerts a high vapor barrier in order to prevent moisture from entering from the above. Terminals T1a, T1b, T2a, and T2care disposed on the insulating film15. Terminals T1aand T1bare each formed to pass through the insulating films11,12,13,14, and15and block layer HB, and are electrically connected to low resistance areas SCa and SCb of the semiconductor layer SC1. Terminal T2ais formed to pass through the insulating films14and15and is electrically connected to the electrode ML3a. Terminal T2cis formed to pass through the insulating films12,13,14, and15and block layer HB and is electrically connected to the gate electrode ML2. Terminals T1a, T1b, T2a, and T2care electrically connected to lines or the like which are not depicted in the figure. In the example depicted, the thin film transistor TR1is a top gate thin film transistor in which the gate electrode ML1is disposed above the semiconductor layer SC1. Furthermore, a thin film transistor TR2is a bottom gate thin film transistor in which the gate electrode ML2is disposed below the semiconductor layer SC2. Note that the structure of each of the thin film transistors TR1and TR2is not limited to the above example, and the thin film transistor TR1may be of bottom gate type and the thin film transistor TR2may be of top gate type. As above, in the present embodiment, the semiconductor device1includes the insulating substrate10, silicon semiconductor layer SC1, metal oxide semiconductor layer SC2, silicon nitride insulating film12between the semiconductor layer SC1and the semiconductor layer SC2, and block layer HB between the insulating film12and the semiconductor layer SC2. Thus, the hydrogen diffusion from the semiconductor layer SC1and the insulating film12to the semiconductor layer SC2. That is, reduction of the semiconductor layer SC2by hydrogen can be suppressed and degradation of reliability of the thin film transistor TR2can be suppressed, too. The semiconductor layer SC1is disposed between the insulating substrate10and the block layer HB. Thus, in a manufacturing process where each member is laminated on the insulating substrate10, the formation and activation of the semiconductor layer SC1can be performed before forming the semiconductor layer SC2. Thereby, a change in components of the semiconductor layer SC2caused by heat applied in the activation process of the semiconductor layer SC1can be prevented. Thus, degradation of reliability of the thin film transistor TR2can be suppressed. The semiconductor layer SC2contacts the block layer HB and hydrogen entering the semiconductor layer SC1from the lower surface SC2aside can further be blocked. Furthermore, the block layer HB continuously extends to a position opposed to the semiconductor layer SC1and a position opposed to the semiconductor layer SC2, and thus, the hydrogen diffusion to the above structure from the insulating film12and the semiconductor layer SC1can be suppressed more effectively. The semiconductor device1further includes the gate electrodes ML1and ML2. The gate electrodes ML1and ML2are disposed on the same layer (insulating film11) and are formed of the same material. Thus, the gate electrodes ML1and ML2can be formed in the same process. That is, the semiconductor device1can be manufactured through lesser processes with lesser costs. The block layer HB is formed of, for example, an aluminum oxide, and thus, the block layer HB can be formed by using aluminum formation rate of which is higher than aluminum oxide and oxidizing the aluminum through an annealing process. Therefore, a time used for manufacturing the semiconductor device1can be reduced. Furthermore, if the block layer HB of aluminum oxide contacts the semiconductor layer SC2, aluminum is diffused from the block layer HB to the semiconductor layer SC2and carriers are supplied, and thus, the mobility of the semiconductor layer SC2can be improved. Now, variations of the present embodiment will be explained with reference toFIGS.2to4. Note that the advantages obtained in the above embodiment can be achieved in these variations. FIG.2is a cross-sectional view of a variation in which the block layer is patterned. In the variation, the block layer HB is patterned to have an island shape. In this respect, the variation differs from the example ofFIG.1. In the example depicted, the block layer HB are formed as islands in the area opposed to the entire surface of the semiconductor layer SC2and the area opposed to the electrodes ML3aand ML3b. The block layer HB is not formed in the other area, and is not opposed to the semiconductor layer SC1, for example. The block layer HB depicted can be patterned using the semiconductor layer SC2and the electrodes ML3aand ML3bas a mask. Note that, if the block layer HB is formed in an island shape, the area of the block layer HB is preferably formed larger than that of the semiconductor layer SC2in order to block hydrogen entering the semiconductor layer SC2. In this variation, the block layer HB is patterned as islands, and the number of interfaces in the areas between thin film transistors can be reduced. Thereby, the transmissivity of the areas between the thin film transistors can be improved in this variation. If the semiconductor device1of the present embodiment is applied to a transmissive display device, the areas between thin film transistors correspond to openings through which light passes, and thus, a display device of high luminosity can be achieved. FIG.3is a cross-sectional view of a variation in which the block layer is disposed in a different position. The insulating film13is disposed between the block layer HB and the semiconductor layer SC2in this variation, and in this respect, the variation differs from the example ofFIG.1. In the example depicted, the block layer HB is disposed on the insulating film12and the insulating film13is disposed on the block layer HB, and the semiconductor layer SC2is disposed on the insulating film13. That is, the insulating film13contacts the upper surface HBb of the block layer HB and the lower surface SC2aof the semiconductor layer SC2. In this variation, the hydrogen diffusion form the insulating film12to the insulating film13can be suppressed. That is, the hydrogen diffusion can be suppressed in a position closer to the hydrogen supplier. FIG.4is a cross-sectional view of a variation in which the block layer is patterned. In this variation, the block layer HB is patterned as islands, and in this respect, the variation differs from the variation ofFIG.3. The advantages obtained in the variation ofFIG.2can be achieved in this variation. FIG.5is a cross-sectional view of a variation in which the thin film transistor TR2is of top gate structure. In this variation, a gate electrode ML4is disposed to be opposed to the semiconductor layer SC2, and in this respect, this variation differs from the example ofFIG.1. The gate electrode ML4is disposed above the semiconductor layer SC2, and in the example depicted, the gate electrode ML4is disposed between the insulating film14and the insulating film15. In the example depicted, a light shielding layer SH is disposed below the semiconductor layer SC2to be opposed to the semiconductor layer SC2. The light shielding layer SH and the gate electrode ML1are disposed on the same layer (insulating film11), and can be formed through the same manufacturing process with the same material used for the gate electrode ML1. The light shielding layer SH can block the light entering into the semiconductor layer SC2if the light from the below is incident on the semiconductor device1. Furthermore, in the example depicted, the insulating film14is patterned as with the gate electrode ML4; however, it may be formed on the entire surface as with the insulating film15. In this variation, the semiconductor device1can suppress the degradation of performance of the thin film transistor TR2by light leakage current. Now, variations of the present embodiment will be explained with reference toFIGS.6to8. Note that the same advantages obtained in the above embodiment can be achieved in these variations. FIG.6is a cross-sectional view of a variation in which the block layer is patterned. In this variation, the block layer HB is patterned as islands, and in this respect, the variation differs from the variation ofFIG.5. In the variation, the block layer HB is formed as islands in the area opposed to the entire surface of the semiconductor layer SC2. The block layer HB is not formed in the other area, and is not opposed to, for example, the semiconductor layer SC1. The block layer HB depicted is patterned using the semiconductor layer SC2as a mask. Note that, if the block layer HB is formed in an island shape, the area of the block layer HB is preferably formed at least greater than the area of the semiconductor layer SC2in order to block hydrogen entering the semiconductor layer SC2. In this variation, the block layer HB is patterned as islands, and the number of interfaces in the areas between thin film transistors can be reduced. Thereby, the transmissivity of the areas between the thin film transistors can be improved in this variation. FIG.7is a cross-sectional view of a variation in which the block layer is disposed in a different position. The insulating film13is disposed between the block layer HB and the semiconductor layer SC2in this variation, and in this respect, the variation differs from the example of FIG.5. In the example depicted, the block layer HB is disposed on the insulating film12and the insulating film13is disposed on the block layer HB, and the semiconductor layer SC2is disposed on the insulating film13. That is, the insulating film13contacts the upper surface HBb of the block layer HB and the lower surface SC2aof the semiconductor layer SC2. In this variation, the hydrogen diffusion from the insulating film12to the insulating film13can be suppressed. FIG.8is a cross-sectional view of a variation in which the block layer is patterned. In this variation, the block layer HB is formed as islands, and in this respect, the variation differs from the variation ofFIG.7. In the example depicted, the block layer HB is disposed on the insulating film12and is formed as islands in the area opposed to the entire surface of the semiconductor layer SC2. The block layer HB is not formed in the other area, and is not opposed to, for example, the semiconductor layer SC1. The insulating film13is disposed on the insulating film12and is partly disposed on the block layer HB formed as islands. That is, the insulating film13partly contacts the upper surface HBb of the block layer HB and the lower surface SC2aof the semiconductor layer SC2. In this variation, the advantages obtained in the variation ofFIG.6can be achieved. Now, an example where the semiconductor device1is applied to a display device DSP will be explained. FIG.9shows the structure of the display device including the semiconductor device of the present embodiment. The display device DSP is, for example, a liquid crystal display device; however, it may be a different display device such as organic electroluminescent (EL) display device. The display panel PNL includes a semiconductor device1. The display panel PNL includes a display area DA used for image display and a non-display area NDA disposed around the display area DA. The display device DSP includes, in the non-display area NDA, a drive circuit Dr, signal line drive circuit SD, scan line drive circuit GD, and the like. The display panel PNL includes a plurality of pixels PX in the display area DA. Note that the display panel PNL includes a plurality of scan lines G (G1to Gn) and a plurality of signal lines S (S1to Sm) in the display area DA. Scan lines G are drawn to the outside of the display area DA and are connected to the scan line drive circuit GD. The scan line drive circuit GD includes complementary TFT elements CC. Signal lines S are drawn to the outside of the display area DA and are connected to the signal line drive circuit SD. The common electrode CE is shared by the pixels PX. The common electrode CE is drawn to the outside of the display area DA and is connected to the drive circuit Dr. Each of the drive circuits GD, SD, and Dr is used to control the electric signal supply to the display area DA through the scan line G, signal line S, and common electrode CE. Each pixel PX includes, for example, a switching element SW, pixel electrode pE, common electrode CE, and liquid crystal layer LQ. The switching element SW is formed of, for example, a thin film transistor. The switching element SW is electrically connected to a scan line G and a signal line S to control the luminosity of pixel PX. The pixel electrode PE is electrically connected to the switching element SW. The pixel electrode PE is opposed to the common electrode CE. A capacitance CS is formed, for example, between the common electrode CE and the pixel electrode PE. In the example depicted, the complementary TFT element CC is formed of a thin film transistor TR1and the switching element SW is formed of a thin film transistor TR2. The thin film transistor TR1is not limited to the complementary TFT element CC, and it may be used as a p-type TFT element or an n-type TFT element. The thin film transistor TR1is not limited to the scan line drive circuit GD, and it may be included in the signal line drive circuit SD or in the drive circuit Dr. Furthermore, the thin film transistor R1may form a switching element SW and the thin film transistor TR2may form a peripheral drive circuit such as drive circuit Dr, signal line drive circuit SD, and scan line drive circuit GD. As can be understood from the above, the display device DSP includes a semiconductor device1of the embodiment. A change in a threshold voltage is less in the thin film transistor TR1than is in the thin film transistor TR2, for example. On the other hand, the thin film transistor TR2has an off-current less than that of the thin film transistor TR1, for example. That is, in the display device DSP, the thin film transistor TR1of high reliability can be arranged in the peripheral circuit while the thin film transistor TR2which can suppress leakage of charge can be arranged in pixels PX. Therefore, the present embodiment can present a display device DSP of high reliability and low power consumption. Since the semiconductor device1includes thin film transistors TR1and TR2of different properties on a single substrate, the thin film transistors TR1and TR2can arbitrarily arranged to correspond to requirements of the TFTs. As explained above, the present embodiment can achieve a semiconductor device which can suppress degradation of reliability. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 24,482 |
11942485 | DETAILED DESCRIPTION The technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings. However, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained on a basis of the embodiments of the present disclosure by a person of ordinary skill in the art shall be included in the protection scope of the present disclosure. Unless the context requires otherwise, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” in the description and the claims are construed as open and inclusive, i.e., “inclusive, but not limited to”. In the description, terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments/examples in any suitable manner. The terms such as “first” and “second” are used for descriptive purposes only and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features below. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, term “a plurality of/the plurality of” means two or more unless otherwise specified. In the description of some embodiments, the term such as “connected” and its extensions may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein. It will be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, the term such as “substantially” may mean that a technical feature is produced within the technical tolerance of the method used to manufacture it. For example, “substantially” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value. In the related art, a micro light-emitting diode (Micro-LED) display panel includes a glass substrate and a Micro-LED array disposed on a surface of the glass substrate. At least one through hole is provided in the glass substrate, and metal is deposited in the at least one through hole to form at least one wire. The at least one wire may connect leads on the surface of the glass substrate to leads on an opposite surface of the glass substrate, so that a controller connected to the leads on the opposite surface may control the Micro-LED array to emit light. However, in a subsequent high-temperature process, it may be easy for the metal to expand and fall off from a through hole due to a difference in thermal expansion coefficient between the metal and the glass. In the related art, a flexible printed circuit (FPC) may also be provided to electrically connect leads on two opposite surfaces of the glass substrate. However, in a case where a plurality of Micro-LED display panels are spliced to form a spliced screen, a seam of the splicing screen may be large due to a large thickness of the FPC, thereby affecting a display effect and an overall appearance. As shown inFIGS.1A,2A and2B, some embodiments of the present disclosure provide a substrate1. The substrate1includes a driving backplane10, a plurality of first connecting lines105insulated from each other, and a plurality of second connecting lines106insulated from each other. As shown inFIG.1A, the driving backplane10has a display area A and at least one peripheral region Q located on a periphery of the display area A. For example, the display area A is in a shape of a rectangle, and the at least one peripheral region Q includes one peripheral region Q disposed on a side of the display area A. For another example, the display area A is in a shape of a rectangle, and the at least one peripheral region Q includes two peripheral regions Q disposed on two sides of the display area A, respectively. Of course, the display area A may have other shapes, such as a circular shape. The driving backplane10includes a base substrate100, at least one first lead group101and at least one second lead group102. A first lead group101and a corresponding second lead group102are disposed in a peripheral region Q. For example, each first lead group101and a corresponding second lead group102are disposed in a corresponding peripheral region Q. For example, two peripheral regions Q, two first lead groups101and two second lead groups102are provided, in which one first lead group101and one second lead group102are disposed in one peripheral region Q, and another first lead group101and another second lead group102are disposed in another peripheral region Q. Of course, the relationship between the peripheral region Q and both the first lead group101and the second lead group102may be set according to actual needs. It will be understood that the at least one first lead group101and the at least one second lead group102are defined according to their positions. That is, a first lead group101or a second lead group102is disposed in a peripheral region Q, and another first lead group101or another second lead group102is disposed in another peripheral region Q. Of course, the embodiments of the disclosure do not limit the definition mode of the at least one first lead group101and the at least one second lead group102, which may be defined according to other features. The base substrate100includes a first surface110and a second surface120that are disposed opposite to each other in a thickness direction of the base substrate100. The base substrate100may be a glass substrate or a flexible substrate. The flexible substrate may be made of, for example, polyimide or polyethylene glycol terephthalate. The at least one first lead group101is disposed on the first surface110of the base substrate100. For example, the at least one first lead group101may be directly disposed on the first surface110of the base substrate100, or may be disposed on other layer on the first surface110. A first lead group101includes a plurality of first leads1010. For example, each first lead group101includes a plurality of first leads1010. The at least one second lead group102is disposed on the second surface120of the base substrate100. For example, the at least one second lead group102may be directly disposed on the second surface120of the base substrate100, or may be disposed on other layer on the second surface120. A second lead group102includes a plurality of second leads1020. For example, each second lead group102includes a plurality of second leads1020. In some embodiments, as shown inFIG.1B, the driving backplane10further includes a driving circuit103disposed on the first surface110of the base substrate100, and the plurality of first leads1010in the first lead group101are electrically connected to the driving circuit103. The driving circuit103may include a plurality of sub-circuits, a plurality of gate lines and a plurality of data lines. The plurality of sub-circuits are in one-to-one correspondence with a plurality of Micro-LEDs in the Micro-LED array, and a sub-circuit is configured to drive a corresponding Micro-LED to emit light. It will be noted that, the driving circuit103inFIG.1Bis schematically shown, and a circuit structure of the driving circuit103is not shown. The display area A includes a plurality of sub-pixel regions, and the plurality of sub-circuits are disposed in the plurality of sub-pixel regions in one-to-one correspondence. A sub-circuit includes at least one thin film transistor. Each thin film transistor includes a gate, a portion of a gate insulating layer between the gate and an active pattern, the active pattern, a source, and a drain. In some examples, first leads1010of the at least one first lead group101may be a plurality of gate line leads. The plurality of gate line leads are in one-to-one correspondence with and electrically connected to the plurality of gate lines, and each gate line is electrically connected to gates of thin film transistors in a corresponding row of sub-pixel regions. In some other examples, the first leads1010of the at least one first lead group101may be a plurality of data line leads. The plurality of data line leads are in one-to-one correspondence with and electrically connected to the plurality of data lines, and each data line is electrically connected to sources of thin film transistors in a corresponding column of sub-pixel regions. In yet other examples, first leads1010of the at least one first lead group101may include a plurality of gate line leads and a plurality of data line leads. The plurality of gate line leads are in one-to-one correspondence with and electrically connected to the plurality of gate lines, and each gate line is electrically connected to gates of thin film transistors in a corresponding row of sub-pixel regions. The plurality of data line leads are in one-to-one correspondence with and electrically connected to the plurality of data lines, and each data line is electrically connected to sources of thin film transistors in a corresponding column of sub-pixel regions. Of course, first leads1010of the at least one first lead group101may further include signal line leads electrically connected to other signal lines, as long as the driving backplane10may drive the plurality of Micro-LEDs in the Micro-LED array to emit light. As shown inFIGS.1A,1B and2A, the plurality of first connecting lines105are disposed on at least one side face of the driving backplane10adjacent to at least one peripheral region Q where the at least one first lead group101and the at least one second lead group102are disposed. Each first connecting line105is electrically connected to at least one first lead1010. For example, each first connecting line105may be electrically connected to one first lead1010, or several first leads1010. In some examples, as shown inFIGS.1A,1B and2A, the plurality of first connecting lines105are disposed on a single side face of the driving backplane10adjacent to a peripheral region Q.FIG.2Aonly shows an example in which there are three first connecting lines105, but the embodiments of the present disclosure are not limited thereto. The number of the first connecting lines105may be set according to actual conditions. In some other examples, as shown inFIGS.3A and3B, the plurality of first connecting lines105are disposed on two opposite side faces of the driving backplane10adjacent to two opposite peripheral regions Q, respectively. That is, some first connecting lines105are disposed on one side face of the driving backplane10, and other first connecting lines105are disposed on the opposite side face of the driving backplane10. In yet other examples, the plurality of first connecting lines105may also be disposed on at least three side faces of the driving backplane10, for example, three side faces or four side faces. As shown inFIGS.1A,1B and2B, the plurality of second connecting lines106are disposed on the at least one side face of the driving backplane10adjacent to the at least one peripheral region Q where the at least one first lead group101and the at least one second lead group102are disposed. Each second connecting line106is electrically connected to at least one second lead1020. For example, each second connecting line106may be electrically connected to one second lead1020, or several second lead1020.FIG.2Bonly shows an example in which each second connecting line106is electrically connected to one second lead1020. As shown inFIGS.1A and1B, each first connecting line105is in contact with a corresponding second connecting line106. That is, the plurality of first connecting lines105are in one-to-one correspondence with the plurality of second connecting lines106, and each first connecting line105and a corresponding second connecting line106are in contact at a corresponding side face of the driving backplane10. In this way, the second leads1020and the first leads1010may be electrically connected through the first connecting lines105and the second connecting lines106, so that the signals on the second leads1020may be transmitted to the driving circuit103of the driving backplane10through the second connecting lines106, the first connecting lines105and the first leads1010. In a case where the plurality of first connecting lines105are disposed on the single side face of the driving backplane10, as shown inFIGS.1A,1B and2B, the plurality of second connecting lines106are also disposed on the single side face of the driving backplane10. In a case where the plurality of first connecting lines105are disposed on two side faces of the driving backplane10, as shown inFIGS.3A and3C, the plurality of second connecting lines106are also disposed on the two side faces of the driving backplane10. In a case where the plurality of first connecting lines105are disposed on at least three side faces of the driving backplane10, the plurality of second connecting lines106are also disposed on the at least three side faces of the driving backplane10.FIG.3Conly shows an example in which there are three second connecting lines106, but the embodiments of the present disclosure are not limited thereto, and the number of the second connecting lines106may be set according to actual conditions. In a case where the substrate1is applied to a display apparatus, as shown inFIGS.1A and1B, a controller104may also be provided on the second surface120of the base substrate100, and is connected to second leads1020in the at least one second lead group102to output signals to the second leads1020. In some examples, in a case where the first leads1010in the at least one first lead group101are the gate line leads, the controller104may include at least one gate driver chip, and the second leads1020may be electrically connected to the at least one gate driver chip. In some other examples, in a case where the first leads1010in the at least one first lead group101are the data line leads, the controller104may include at least one source driver chip, and the second leads1020may be electrically connected to the at least one source driver chip. In yet other examples, in a case where the first leads1010in the at least one first lead group101include gate line leads and data line leads, the controller104may include at least one gate driver chip and at least one source driver chip. A part of the second leads1020may be electrically connected to the at least one gate driver chip, and the remaining part of the second leads1020may be electrically connected to the at least one source driver chip. Of course, in a case where the first leads1010further include signal line leads electrically connected to other signal lines, the controller104may further include other chips or circuits. It will be noted that, the above chips or circuits may be separately arranged, or may be disposed on a single circuit board. In the substrate1provided by some embodiments of the present disclosure, the second leads1020and the first leads1010are electrically connected through the first connecting lines105and the corresponding second connecting lines106that are disposed at the at least one side face of the driving backplane10. On one hand, it may avoid forming through holes in the base substrate100, thereby avoiding problems such as a reduction in mechanical properties of the substrate1and an easy fall-off of wires in the through holes. On another hand, in a case where the substrate1is applied to a spliced display apparatus, since the FPC is not used, a seam of the spliced screen may be reduced. In some embodiments, as shown inFIGS.1A and1B, an orthographic projection of the first connecting line105on a side face where it is located and an orthographic projection of the corresponding second connecting line106on the side face do not overlap. That is, an interface between the first connecting line105and the corresponding second connecting line106is a region where an end face of the first connecting line105and an end face of the second connecting line106meet. In some embodiments, the interface between the first connecting line105and the corresponding second connecting line106is substantially located at a position at half a thickness of the base substrate100. For example, as shown inFIGS.1A and1B, the thickness of the base substrate100is H, and the interface between the first connecting line105and the corresponding second connecting line106is substantially located at the position at half of the thickness H of the base substrate100. In some embodiments, as shown inFIGS.1A,1B,2A and2B, the first connecting line105extends to the first surface110of the base substrate100and is in lap joint with the at least one first lead1010, the second connecting line106extends to the second surface120of the base substrate10and is in lap joint with the at least one second lead1020. For example, as shown inFIGS.1A,1B and2A, the first connecting line105includes a first portion1051located on a side face of the base substrate100and a second portion1052located on the surface of the at least one first lead1010facing away from the base substrate100. An orthographic projection of the second portion1052on the base substrate100overlaps with an orthographic projection of the first lead1010connected to the second portion1052on the base substrate100. In this way, a contact area between the first connecting line105and the first lead1010may be increased, and a contact resistance between the first connecting line105and the first lead1010may be further reduced. In addition, for example, as shown inFIGS.1A,1B and2B, the second connecting line106includes a third portion1061located on a side face of the base substrate100and a fourth portion1062located on a surface of the at least one second lead1020facing away from the base substrate100. An orthographic projection of the fourth portion1062on the base substrate100overlaps with an orthographic projection of the second lead1020connected to the fourth portion1062on the base substrate100. In this way, a contact area between the second connecting line106and the second lead1020may be increased, and a contact resistance between the second connecting line106and the second lead1020may be further reduced. In some embodiments, the plurality of first connecting lines105are made of a metal material, and the plurality of second connecting lines106are also made of a metal material. For example, the metal material may include or may be copper, aluminum, copper alloy, or aluminum alloy. The metal material may have a good conductivity and a low resistivity, which is advantageous for the signal transmission. In some examples, the plurality of first connecting lines105and the plurality of second connecting lines106may be made of a same material. In some other examples, the plurality of first connecting lines105and the plurality of second connecting lines106may be made of different materials. In some embodiments, as shown inFIG.4, the substrate1further includes a protective layer107disposed on the at least one side face of the driving backplane10. The protective layer107covers the plurality of first connecting lines105and the plurality of second connecting lines106. The protective layer107is used to protect the plurality of first connecting lines105and the plurality of second connecting lines106, to prevent them from being oxidized. In addition, in the case where the substrate1is applied to the spliced display apparatus, the protective layer107may also prevent abrasion of first connecting lines105and second connecting lines106on different substrates1that is caused by a relative movement between the substrates1during splicing. In some embodiments, the protective layer107may include a resin material, such as epoxy resin or acrylic resin. In some other embodiments, the protective layer107further includes a black dye (e.g., carbon black). In this way, the protective layer107may also prevent a reflection of light by the plurality of first connecting lines105or the plurality of second connecting lines106which may affect display effect. In some embodiments, as shown inFIG.1B, the substrate1further includes the plurality of Micro-LEDs200disposed on the first surface110of the base substrate100. For example, the plurality of Micro-LEDs200are disposed on other layers on the first surface110of the base substrate100, and constitute the Micro-LED array. The plurality of Micro-LEDs200are driven by the driving circuit103of driving backplane10to emit light. For example, as shown inFIG.1B, the plurality of Micro-LEDs200are disposed on the driving circuit103on the first surface110of the base substrate100. The plurality of Micro-LEDs200are electrically connected to the driving circuit103and are driven by the driving circuit103to emit light. For example, the Micro-LED array is formed by using a mass transfer method. That is, a plurality of light-emitting diode (LED) bare chips are grown on a sapphire supply substrate by using a molecular beam epitaxy method. The plurality of LED bare chips are separated from the supply substrate by using a laser lift-off technology. The plurality of LED bare chips are adsorbed by a patterned transfer substrate. The transfer substrate and the driving backplane10are aligned to transfer the plurality of LED bare chips absorbed on the transfer substrate to matching positions on the driving backplane10. Finally, the transfer substrate is removed. Some embodiments of the present disclosure provide a display panel. As shown inFIG.5, the display panel2includes the substrate1described in any one of the above embodiments. On this basis, the display panel2further includes an encapsulation layer300for encapsulating the plurality of Micro-LEDs200. The display panel2has same beneficial effects as the substrate1, which will not be repeated herein. Some embodiments of the present disclosure provide a display apparatus. As shown inFIG.6, the display apparatus includes at least one display panel2as above. In some examples, the display apparatus includes a single display panel2. In some other examples, the display apparatus includes a plurality of display panels2. In this case, as shown inFIG.6, the plurality of display panels2are spliced together, so as to form a large-sized spliced display apparatus. In a case where the plurality of display panels2are spliced together, back surfaces of the plurality of display panels2that are opposite to display surfaces are in a same plane, and the display surfaces are light exit surfaces of the display panels2. For example, the display apparatus further includes a support, and side faces of any two adjacent display panels2that face each other are aligned and bonded to the support.FIG.6shows an example in which the display apparatus includes four display panels2, but the embodiments of the present disclosure are not limited thereto. In the display apparatus provided by some embodiments of the present disclosure, in the substrate1of each display panel2, the plurality of first connecting lines105and the plurality of second connecting lines106for electrically connecting the first leads1010and the second leads1020that are respectively located on the first surface110and the second surface120of the base substrate100have a thinner thickness compared with the FPC. Therefore, in the case where the display apparatus includes the plurality of display panels2, a seam between two adjacent display panels2may be very small, and the display effect and an overall aesthetics may be further improved. Some embodiments of the present disclosure provide a method for manufacturing the substrate1. As shown inFIG.7, the method includes S101to S105. In S101, as shown inFIG.8A, at least one strip-shaped groove1011corresponding to each driving backplane to be cut11is formed in a third surface1001of a driving backplane motherboard1000which includes at least one driving backplane to be cut11. The driving backplane to be cut11has a display area A and at least one peripheral region Q located on a periphery of the display area A. Each first lead group101and a corresponding second lead group102of the driving backplane to be cut11are disposed in one peripheral region Q. Each first strip-shaped groove1011is in contact with a corresponding peripheral region Q where a first lead group and a second lead group are disposed. In a case where the driving backplane motherboard1000includes a plurality of driving backplanes to be cut11, structures of the plurality of driving backplanes to be cut11are completely the same. There is a cutting region between two adjacent driving backplanes to be cut11, and the structure of each driving backplane to be cut11is the same as a structure of the driving backplane10. After the driving backplane motherboard1000is cut, a plurality of driving backplanes10are obtained. It will be seen that, before the driving backplane motherboard1000is cut, the plurality of driving backplanes to be cut11share a single base motherboard1100. After the driving backplane motherboard1000is cut, a portion of the base motherboard1100corresponding to a driving backplane10is a base substrate100. In a case where the driving backplane motherboard1000includes a single driving backplane to be cut11, the structure of the driving backplane to be cut11is the same as the structure of the driving backplane10. After the driving backplane motherboard1000is cut, a single driving backplane10is obtained. In this case, since the at least one first strip-shaped groove1011is formed in the driving backplane motherboard1000, the base motherboard1100of the driving backplane motherboard1000includes at least one portion that will be cut away in addition to a portion corresponding to the driving backplane to be cut11. FIG.8Aonly shows an example in which the driving backplane motherboard1000includes a single driving backplane to be cut11, but the embodiments of the present disclosure are not limited thereto. In addition,FIG.8Aonly shows an example in which a single strip-shaped groove1011is provided corresponding to a single driving backplane to be cut11. In practice, the number of the at least one first strip-shaped groove1011may be selected according to positions of the plurality of first leads1010. For example, as shown inFIG.8B, two parallel first strip-shaped grooves1011corresponding to the driving backplane to be cut11that are located at two opposite edges of the driving backplane to be cut11may be formed in the third surface1001of the driving backplane motherboard1000. The base motherboard1100of the driving backplane motherboard1000may be a glass motherboard or a flexible resin motherboard (for example, the flexible resin motherboard may be made of polyimide or polyethylene glycol terephthalate). According to different materials of the base motherboard1100, the at least one first strip-shaped groove1011may be formed in the third surface1001of the driving backplane motherboard1000by using different processes. In some examples, the base motherboard1100is the glass motherboard. In this case, forming the at least one first stripe-shaped groove1011corresponding to each driving backplane to be cut11in the third surface1001of the driving backplane motherboard includes: forming the at least one first stripe-shaped groove1011corresponding to each driving backplane to be cut11in the third surface1001of the driving backplane motherboard1000by using a laser cutting method. In some other examples, the base motherboard1100is the flexible resin motherboard. In this case, forming the at least one first strip-shaped groove1011corresponding to each driving backplane to be cut11in the third surface1001of the driving backplane motherboard1000includes: forming the at least one first strip-shaped groove1011corresponding to each driving backplane to be cut11in the third surface1001of the driving backplane motherboard1000by using an etching process. For example, photoresist may be first coated on the third surface1001of the driving backplane motherboard1000, and then photoresist in a region where the at least one first strip-shaped groove to be formed is removed through an exposure process and a development process. Then, the driving backplane motherboard1000is etched by using a dry etching process to form the at least one first strip-shaped groove1011corresponding to each driving backplane to be cut11, and finally all the remaining photoresist is removed. In some embodiments, as shown inFIGS.8A and8B, the first strip-shaped groove1011is in contact with an edge of the peripheral region Q away from the display area A and extends along the edge of the peripheral region Q. In this way, a slotting process is simple, and the first strip-shaped groove1011may be easily formed. In some embodiments, the first strip-shaped groove1011formed in the third surface1001has a certain depth in a thickness direction of the base motherboard1100. For example, the depth of the first strip-shaped groove1011is half a thickness of the base motherboard1100. In this way, the base motherboard1100may be maintained a certain mechanical strength, and it is possible to prevent a fracture of the base motherboard1100along the first stripe-shaped groove1011in a subsequent manufacturing process due to an excessive depth of the first stripe-shaped groove1011. In S102, a plurality of first connecting lines105insulated from each other are formed in a region in which the first strip-shaped groove1011is located. Each first connecting line105extends to a surface of at least one first lead1010and is in contact with the at least one first lead1010. In some embodiments, forming the plurality of first connecting lines105insulated from each other in the region in which the first strip-shaped groove1011is located includes the following steps. In S1021, as shown in part (a) inFIG.9A, a first metal layer1013is formed on the third surface1001of the driving backplane motherboard1000by using a sputtering process. The first metal layer1013includes a portion filling the first strip-shaped groove1011. For example, taking one of copper, aluminum, copper alloy, or aluminum alloy as a target material, the first metal layer1013may be formed on the third surface1001of the driving backplane motherboard1000by using the sputtering process. In S1022, as shown in part (b) inFIG.9A, a first photoresist layer1014is formed on the first metal layer1013. In S1023, as shown in part (c) inFIG.9A, the first photoresist layer1014is exposed and developed to form a plurality of first photoresist patterns1015. An orthographic projection of each first photoresist pattern1015on the base motherboard1100overlaps with an orthographic projection of a first lead1010corresponding to a first connecting line to be formed on the base motherboard1100and an orthographic projection of the first strip-shaped groove1011on the base motherboard1100. That is, a position where the first photoresist pattern1015is located is a position where a first connecting line105will be formed. In S1024, as shown in part (d) inFIG.9A, the first metal layer1013is etched to form the plurality of first connecting lines105insulated from each other in the region in which the first strip-shaped groove1011is located. Each first connecting line105is in contact with at least one corresponding first lead1010. After the plurality of first connecting lines105are formed, all the remaining first photoresist patterns1015are removed. In some embodiments, before the first metal layer1013is formed on the third surface1001of the driving backplane motherboard1000, the method for manufacturing the substrate1further includes: as shown inFIG.9B, forming a first protective film401on the third surface1001, wherein the first protective film401exposes a connection terminal of each first lead1010for connecting a corresponding first connecting line105. The first protective film401is made of, for example, photoresist or polyimide. The first protective film401may protect the plurality of first leads1010and the driving circuit103to prevent the plurality of first leads1010and the driving circuit103from being damaged in a process of forming the first connecting lines105, or to prevent the plurality of first leads1010or the driving circuit103from being short-circuited due to deposited metal. In a subsequent process, the first protective film401will be removed. For example, after the driving backplane10, the plurality of first connecting lines105and the plurality of second connecting lines106are formed, the first protective film401is removed. In some other embodiments, forming the plurality of first connecting lines105insulated from each other in the region in which the first strip-shaped groove1011is located includes the following step. In S1025, the plurality of first connecting lines105insulated from each other are formed in the region in which the first strip-shaped groove1011is located by using a first mask through an evaporation process, to obtain the structure shown in part (d) inFIG.9A. The evaporation process is a process in which a material to be deposited is used as an evaporation source material, and due to a mask, the material to be deposited is directly deposited onto a region where a pattern to be formed is located. On this basis, after the plurality of first connecting lines105insulated from each other are formed, the method for manufacturing the substrate1further includes: as shown inFIG.10, turning the driving backplane motherboard1000180 degrees, placing the turned driving backplane motherboard1000on a temporary substrate20, and bonding the third surface1001of the driving backplane motherboard1000to the temporary substrate20by a temporary bonding adhesive30. The temporary substrate20is, for example, a glass substrate. The temporary bonding adhesive30is made of, for example, a resin material such as polycarbonate or acrylic acid. Bonding the third surface1001of the driving backplane motherboard1000to the temporary substrate20may prevent the driving backplane motherboard1000from being broken at the first strip-shaped groove1011in a subsequent process. In S103, as shown inFIG.11, at least one second strip-shaped hole1021is formed in a fourth surface1002of the driving backplane motherboard1000that is opposite to the third surface1001, and each second strip-shaped hole1021is connected to a corresponding first strip-shaped groove1011. That is, the number of the at least one second strip-shaped hole1021and the number of the at least one first strip-shaped groove1011are the same, and the positions of the two are in one-to-one correspondence. A method for forming the at least one second strip-shaped hole1021in the fourth surface1002of the driving backplane motherboard1000is similar to the method for forming the at least one strip-shaped groove1011in the third surface1001of the driving backplane motherboard1000, and different processes may be used according to different materials of the base motherboard1100. In some examples, the base motherboard1100is the glass motherboard. In this case, forming the at least one second strip-shaped hole1012in the fourth surface1002of the driving backplane motherboard1000includes: forming the at least one second strip-shaped hole1021in the fourth surface1002of the driving motherboard1000by using the laser cutting method. In some other examples, the base motherboard1100is the flexible resin motherboard. In this case, forming the at least one second strip-shaped hole1021in the fourth surface1002of the driving backplane motherboard1000includes: forming the at least one second strip-shaped hole1021in the fourth surface1002of the driving motherboard1000by using the etching process. In some embodiments, as shown inFIG.11, the second strip-shaped hole1021is in contact with an edge of the peripheral region Q away from the display area A and extends along the edge of the peripheral region Q. In this way, a slotting process is simple, and the second strip-shaped hole1021may be easily formed. In S104, a plurality of second connecting lines106insulated from each other are formed in a region in which the second strip-shaped hole1021is located, and each second connecting line106is in contact with a corresponding first connecting line105. The second connecting line106extends to a surface of at least one second lead1020and is in contact with the at least one second lead1020in the second lead group102. In some embodiments, forming the plurality of second connecting lines106insulated from each other in the region in which the second strip-shaped hole1021is located includes the following steps. In S1041, as shown in part (a) inFIG.12A, a second metal layer1023is formed on the fourth surface1002of the driving backplane motherboard1000by using the sputtering process. The second metal layer1023includes a portion filling the second strip-shaped hole1021. In S1042, as shown in part (b) inFIG.12A, a second photoresist layer1024is formed on the second metal layer1023. In S1043, as shown in part (c) inFIG.12A, the second photoresist layer1024is exposed and developed to form a plurality of second photoresist patterns1025. An orthographic projection of each second photoresist pattern1025on the base motherboard1100overlaps with an orthographic projection of a second lead1020corresponding to a second connecting line to be formed on the base motherboard1100and an orthographic projection of the second strip-shaped hole1021on the base motherboard1100. That is, a position where the second photoresist pattern1025is located is a position where a second connecting line106will be formed. In S1044, as shown in part (d) inFIG.12A, the second metal layer1023is etched to form the plurality of second connecting lines106insulated from each other in the region in which the second strip-shaped hole1021is located. Each second connecting line106is in contact with at least one corresponding second lead1020. After the plurality of second connecting lines106are formed, all the remaining second photoresist patterns1025are removed. In some embodiments, before the second metal layer1023is formed on the fourth surface1002of the driving backplane motherboard1000, the method for manufacturing the substrate1further includes: as shown inFIG.12B, forming a second protective film402on the fourth surface1002, wherein the second protective film402exposes a connection terminal of each second lead1020for connecting a corresponding second connecting line106. The second protective film402is made of, for example, photoresist or polyimide. The second protective film402may protect the plurality of second leads1020to prevent the plurality of second leads1020from being damaged in a process of forming the second connecting lines106, or to prevent the plurality of second leads1020from being short-circuited due to deposited metal. In a subsequent process, the second protective film402will be removed. For example, after the driving backplane10, the plurality of first connecting lines105and the plurality of second connecting lines106are formed, the second protective film402is removed. In some other embodiments, forming the plurality of second connecting lines106insulated from each other in the region in which the second strip-shaped hole1021is located includes the following step. In1045, the plurality of second connecting lines106insulated from each other are formed in the region in which the second strip-shaped hole1021is located by using a second mask through the evaporation process, to obtain the structure shown in part (d) inFIG.12A. On this basis, after the plurality of second connecting lines106are formed, the method for manufacturing the substrate1further includes: separating the temporary substrate20from the driving backplane motherboard1000to obtain the structure shown inFIG.13. For example, according to different materials of the temporary bonding adhesive30, the temporary bonding adhesive30may be removed by using a heating method or an illumination method to debond the temporary substrate20from the driving backplane motherboard1000, thereby separating the temporary substrate20from the driving backplane motherboard1000. In S105, the driving backplane motherboard1000is cut into at least one driving backplane10. The plurality of first connecting lines105insulated from each other and the plurality of second connecting lines106insulated from each other are formed on at least one side face of each driving backplane10. In some embodiments, cutting the driving backplane motherboard1000includes: cutting the driving backplane motherboard1000along inner walls of the second strip-shaped hole1021and the corresponding first strip-shaped groove1011away from the display area A by using a laser cutting method. For example, a portion of the base motherboard1100on a side of the first and second connecting lines105and106away from the first and second leads1010and1020may be separated from the first and second connecting lines105and106, by using the laser cutting method, thereby obtaining the structure shown inFIG.14. In some embodiments, the method for manufacturing the substrate1further includes: referring toFIG.4, forming the protective layer107at the at least one side face of the substrate1by using a transfer printing method or a pad printing method. The protective layer107covers the plurality of first connecting lines105and the plurality of second connecting lines106. The protective layer107is used to protect the plurality of first connecting lines105and the plurality of second connecting lines106, to prevent them from being oxidized. The protective layer107may also prevent the abrasion of the plurality of first connecting lines105and the plurality of second connecting lines106on different substrates1which is caused by the relative movement between the substrates1during the splicing. In some examples, the protective layer107may include the resin material, such as the epoxy resin or the acrylic resin. In some other examples, the protective layer107further includes the black dye (e.g., the carbon black). On this basis, the protective layer107may also prevent the reflection of the light by the plurality of first connecting lines105and the plurality of second connecting lines106which may affect the display effect. The forgoing descriptions are merely specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art could conceive of changes or replacements within the technical scope of the present disclosure, which shall all be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims. | 43,672 |
11942486 | Elements of the prior art in the drawings are designated by reference numerals listed below.first sub-pixel110; second sub-pixel120; common electrode wiring111;first data line112; second data line1124; horizontal scan line117;vertical scan line118; pixel electrode119; non-display area102;display area101; vertical portion1121;upper lateral portion1122of first electrode branch;via hole112; substrate201; first metal layer202;first insulating layer203; second metal layer204; third metal layer205;passivation layer206; color resist layer207; second insulating layer208;first branch200; lateral portion1123of first electrode branch;active layer302; gate insulating layer303; gate304;first insulating layer203; second metal layer204; second insulating layer208;source/drain metal layer308. DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. In the description of the present invention, it is to be understood that the terms “center”, “lateral”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside” and the like are based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the indicated devices or components must to be in particular orientations, or constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention. Furthermore, the terms “first”, “second”, etc. in the specification and claims of the present invention and the above figures are used to distinguish similar objects, and are not necessarily used to describe a specific order or prioritization. It should be understood that the objects so described are interchangeable when it is appropriate. Moreover, the terms “including” and “having” and any variations thereof are intended to cover a non-exclusive “inclusion”. As shown inFIG.5andFIG.6, the present invention provides a display panel100including sub-pixel groups100arranged in an array. The sub-pixel group100includes a first sub-pixel110and a second sub-pixel120. The second sub-pixel120is provided on the left side of the first sub-pixel110. The first sub-pixel110includes: a common electrode wiring111, a first data line112, a second data line1124, a horizontal scan line117, a vertical scan line118, and a pixel electrode119. The rectangle area enclosed by the common electrode wiring111serves as the display area101of the first sub-pixel110. The common electrode wiring111and the horizontal scan line117are formed in the first metal layer202together. The first data line112and the second data line1124are formed in the second metal layer204together. Specifically, when preparing the common electrode wiring111and the horizontal scan line117, the common electrode wiring111and the horizontal scan line117are obtained by depositing a metal material followed by patterning. Materials of the common electrode wiring111and the horizontal scan line117include copper and/or its alloys. When preparing the first data line112and the second data line1124, the first data line112and the second data line1124are obtained by depositing a metal material followed by patterning. The materials of the first data line112and the second data line1124include copper and/or its alloys. In a cross-sectional structure, as shown inFIG.7, the second metal layer204is provided above the first metal layer202, and the second metal layer204is provided on and insulated from the first metal layer202. In a cross-sectional structure, the first data line112is disposed above the common electrode wiring111. In a planar structure, the first data line112extends from the non-display area102of the sub-pixel and passes through the display area101. In a cross-sectional structure, the second data line1124is arranged above the common electrode wiring111. In a planar structure, the second data line1124extends from the non-display area102of the first sub-pixel110and passes through the display area101. The first data line112and the second data line1124are insulated from each other and do not intersect each other, and the first data line112and the second data line1124are arranged opposite to each other in the display area101. More specifically, the first data line112is arranged on a left side of a center line of the first sub-pixel110, and the second data line1124is arranged on a right side of the center line of the first sub-pixel110, such that the planar structural layout enables the first data line112and the second data line1124to be arranged opposite to each other in the display area101. In the present invention, the electrical signals of the first data line112and the second data line1124are set to be opposite to each other. Furthermore, the voltages generated when the first data line112and the second data line1124are coupled to the sub-pixel can be offset by each other, and finally the problem of vertical crosstalk of the ultra-narrow border can be improved. The wiring portion of the first data line112in the display area101and the second data line1124are bilaterally symmetrical with respect to the center line of the first sub-pixel110. Specifically, the first data line112includes a trunk (not marked in the drawings. since the reference numeral112of the first data line has been marked, it can also be used as a trunk mark) and a first branch200. The trunk is provided in the non-display area102. The first branch200is disposed in the display area101, and the first branch200is connected to the trunk. The first branch200includes a vertical portion1121and two mutually parallel lateral portions (upper lateral portion1122and lower lateral portion1123). The upper lateral portion1122is connected to an upper end of the vertical portion1121, and the lower lateral portion1123is connected to a lower end of the vertical portion1121. The upper lateral portion1122corresponds to an upper boundary of the display area101, and the lower lateral portion1123corresponds to a lower boundary of the display area101. In other words, the upper lateral portion1122is correspondingly disposed on an upper short side of the rectangle area of the common electrode wiring111, and the lower lateral portion1123is correspondingly disposed on a lower short side of the rectangle area of the common electrode wiring111. The second data line1124only includes a second branch210. The second branch210has the same structure as the first branch200. The second branch210also includes a vertical portion and two horizontal portions parallel to each other. The two horizontal portions are not marked in the drawings, and their details can be referred to the description for the structure of the second branch. Specifically, the upper lateral portion of the second branch210is connected to the upper end of the vertical portion of the second branch210, and the lower lateral portion of the second branch210is connected to the lower end of the vertical portion1121. The upper lateral portion of the second branch210corresponds to the upper boundary of the display area101, and the lower lateral portion of the second branch210corresponds to the lower boundary of the display area101. In other words, the upper lateral portion of the second branch210is correspondingly disposed on an upper short side of the rectangle area of the common electrode wiring111, and the lower lateral portion of the second branch210is correspondingly disposed on a lower short side of the rectangle area of the common electrode wiring111. The second branch210and the first branch200are bilaterally symmetrical with respect to the center line of the display area101of the first sub-pixel110. In the display area101, the lateral portion of the first branch200and the lateral portion of the second branch210are correspondingly arranged on the same straight line. The vertical portion of the first branch200and the vertical portion of the second branch210are parallel to each other and are arranged on the left and right sides of the center line of the display area101. The opening direction of the pattern formed by the first branch200and the upper and lower lateral portions is opposite to the opening direction of the pattern formed by the second branch210and the upper and lower lateral portions. The second sub-pixel120is an adjacent pixel of the first sub-pixel110. The second sub-pixel120and the first sub-pixel110have the same structure. The present invention does not specifically limit the adjacent pixels, and the second sub-pixel120is arranged on the right side of the first sub-pixel110in this embodiment. The first data line branch121of the second sub-pixel120and the second data line1124of the first sub-pixel110share a trunk (marked by the reference numeral113). In other words, the upper lateral portion of the first data line branch121of the second sub-pixel120and the upper lateral portion of the second branch210of the second data line1124merge at the trunk113. It can also be said that when the data line trunk passes through the non-display area102and reaches the upper boundary of the display area101, the trunk113is divided into the first data line branch121of the second sub-pixel120and the second branch210of the second data line1124, and when the two branches respectively extends to the lower boundaries of the display area101from the display area of different sub-pixels, they merge into a data line (trunk). In summary, the present invention changes the wiring mode of the sub-pixel data lines, so that the non-display area102of the first sub-pixel110has a data line (the trunk of the first data line112), and the first branch200of the first data line112is arranged in the display area101. In addition, the display area101of the first sub-pixel110is further provided with a second data line1124. The second branch of the second data line1124and the first data line branch121of the second sub-pixel120shares the trunk of the non-display area102. Since the non-display area102only has one data line, the problem of narrow spacing between metals in the same layer of the structure can be avoided, and the number of the chips on film (COFs) used can be reduced, thereby reducing production costs. In addition, by setting opposite signals of the first data line112and the second data line1124, the coupling voltages of the two data line signals to the sub-pixels can be offset by each other, and the problem of vertical crosstalk of an ultra-narrow border display is improved. The present invention realizes the function of the pixel structure ofFIG.3. The common electrode wiring of the second sub-pixel120is connected to the common electrode wiring111of the first sub-pixel110, and the connection is set on a long side of the rectangle area, so as to realize the connection between the common electrode wirings of the first sub-pixel110and the second sub-pixel120. The lateral portions of the first data line112of the second sub-pixel120are respectively connected to the lateral portions of the second data line1124of the first sub-pixel110. Therefore, the data lines is designed to have a pattern of a “mouth shape” in the present invention. It can also be said that the present invention provides a data line trunk between the non-display area102of adjacent sub-pixels (the first sub-pixel110and the second sub-pixel120), and when the data line (trunk) extends to the display area101, it is divided into two branch structures, and the two branch structures enter different sub-pixels, respectively, wherein one of the two branch structures enters the first sub-pixel110and extends in the right area of the first sub-pixel110, the other one of the two branch structures enters the second sub-pixel120and extends in the left area of the second sub-pixel120, and finally the data line branches pass through the display area101and merge together at the lower boundary of the display area101, thereby controlling the data signal of the sub-pixel in a next row. The horizontal scan line117is disposed in the non-display area102, and the trunk of the horizontal scan line117and the first data line112are perpendicular to each other. From a perspective ofFIG.6, the vertical scan line118is provided between the first sub-pixel110and the second sub-pixel120, and the vertical scan line118is connected to the horizontal scan line117. The material of the vertical scan line118includes copper and/or its alloys. In terms of a layered structure, the vertical scan line118and the horizontal scan line117are arranged in different layers. The pixel electrode119is disposed above the display area101and made of a material including indium tin oxide. The pixel electrode119includes an electrode trunk and a plurality of electrode branches arranged in parallel. The electrode branch pattern has a fishbone-like shape, and an angle between the electrode branch and the electrode trunk is generally set to 45 degrees. The horizontal scan line117and the vertical scan line118are respectively formed in different metal layers, and the horizontal scan line117is connected to the vertical scan line118through a via hole112. Furthermore, the problem of narrow spacing between metals in the same layer can be avoided. In the present invention, the horizontal scan line117and the common electrode wiring111are prepared in the same layer. When preparing the common electrode wiring111and the horizontal scan line117, a metal material is first deposited and then patterned to obtain the common electrode wiring111and the horizontal scan line117. The vertical scan line118and the data line can be arranged on the same layer, and can be obtained by depositing and patterning together during preparation. Therefore, the material of the vertical scan line118is the same as that of the data line. As shown inFIG.7, at the via hole112, the cross-sectional structure of the sub-pixel includes: a substrate201, a first metal layer202, a first insulating layer203, a second metal layer204, a second insulating layer208, a third metal layer205, a passivation layer206, and a color resist layer207. The substrate201is a flexible substrate, and made of polyimide. The first metal layer202is disposed on the substrate201. The material of the first metal layer202includes copper and/or its alloys. The gate of the thin film transistor is formed in the first metal layer202. The first insulating layer203is disposed on the substrate201and covers the first metal layer202, and the first insulating layer203includes the via hole112. The material of the first insulating layer203includes silicon nitride or silicon oxide. The second metal layer204is disposed on the first insulating layer203, and the second metal layer204is connected to the first metal layer202through the via hole112. The material of the second metal layer204includes copper and/or its alloys. The second insulating layer208is disposed on the second metal layer204and the first insulating layer203. The material of the second insulating layer208includes silicon nitride or silicon oxide. The third metal layer205is disposed on the second insulating layer208. The material of the third metal layer205includes copper and/or its alloys. The first data line112and the second data line1124are prepared in the third metal layer205by vapor deposition. The passivation layer206is disposed on the second insulating layer205and covers the third metal layer205. The material of the passivation layer206includes silicon nitride or silicon oxide. The color resist layer207is disposed on the passivation layer206, and the color resist layer207includes a red color resist (R), a blue color resist (B), and a green color resist (G). In an embodiment, the common electrode wiring111and the horizontal scan line117are provided in the first metal layer202; and the vertical scan line118is provided in the second metal layer204. In an embodiment, the common electrode wiring111and the horizontal scan line117may be provided in the second metal layer204; and the vertical scan line118is provided in the first metal layer202. The present invention can avoid the problem of narrow pacing between metals in the same layer by arranging metal wirings in different layers. In an embodiment, the first sub-pixel110further includes: a thin film transistor. As shown inFIG.8, the thin film transistor is disposed in the non-display area102, wherein the layered structure at the thin film transistor specifically includes: a substrate201, an active layer302, a gate insulating layer303, a gate304, a first insulating layer203, a second metal layer204, a second insulating layer208, a source/drain metal layer308, a passivation layer206, and a first electrode layer310. Some of the layers inFIG.8are the same as those inFIG.7. The substrate201includes a glass substrate2011, a barrier layer2012, and a buffer layer2013. The barrier layer2012is provided on the glass substrate2011; and the buffer layer2013is provided on a side of the barrier layer2012away from the glass substrate2011. The material of the barrier layer2012includes silicon nitride and/or silicon oxide. The active layer302is disposed on the substrate201; and the active layer302is made of polysilicon material. The gate insulating layer303is disposed on the active layer302and the substrate201. The gate304is disposed on the gate insulating layer303; and the material of the gate304includes aluminum, copper, and/or copper-aluminum alloy. That is, the material of the gate304may be selected from aluminum, copper, or copper aluminum alloy. Among them, aluminum has the best electrical conductivity, and aluminum and copper have better flexibility, which are suitable for preparing the flexible display panel100. The grid304of the display panel100of the present invention is made of copper-aluminum alloy, whose conductivity and bending resistance are far superior to molybdenum used for the existing gate material, and can be well suited for foldable display panels or curlable display panels. The gate304is prepared in the first metal layer202, and can be prepared together with the common electrode wiring111and the horizontal scan line117by vapor deposition. The first insulating layer203is disposed on the gate304and the gate insulating layer303. The second metal layer204is disposed on the first insulating layer203. The second insulating layer208is disposed on the second metal layer204and the first insulating layer203. The source/drain metal layer308is disposed on the second insulating layer208and connected to the active layer302; the source/drain metal layer308has a source wiring3081and a drain wiring3082. The source wiring3081and the drain wiring3082are respectively connected to the active layer302. The source/drain metal layers308are prepared in the third metal layer205by vapor deposition. The passivation layer206is provided on the source/drain metal layer308and the second insulating layer208; the first electrode layer310is provided on the passivation layer206; and the first electrode layer310is patterned to obtain the pixel electrode119 The present invention changes the wiring mode of the sub-pixel data lines, so that the non-display area102of the first sub-pixel110only has a trunk of the first data line112, and the first branch200of the first data line112is arranged in the display area101. In addition, the display area101of the first sub-pixel110is further provided with a second data line1124. In the present invention, by setting opposite signals of the first data line112and the second data line1124, the coupling voltages of the two data line signals to the sub-pixels can be offset by each other, and the problem of vertical crosstalk of an ultra-narrow border display is improved. In one of the sub-pixel groups, the second branch210of the second data line1124and the first data line branch121of the second sub-pixel120share the trunk of the non-display area102. While the present invention realizes the function of the pixel structure inFIG.3, since there is only one data line in the non-display area102, the number of COFs can be reduced and the production cost can be reduced. In the present invention, the horizontal scan line117and the vertical scan line118are arranged in different layers, which can avoid the problem of the narrow spacing between metals in the same layer of the structure. The present invention also provides a display device, which includes the display panel100of the present invention. While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. | 21,274 |
11942487 | Elements in the drawings are designated by reference numerals listed below.1. shared metal wiring,2. scan line,3. data wiring,10. transistor area,11. main transistor unit,12. sub-transistor unit,13. shared transistor unit,20. pixel area,21. main pixel area,211. first pixel electrode,22, sub-pixel area,221, second pixel electrode,31. glass substrate,32, first metal layer,33, gate insulating layer,34. second metal layer,35. passivation layer,36. via hole,100. array substrate,101. widened portion110. pixel unit. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The preferred embodiments of the present invention are described below with reference to the accompanying drawings, which are used to exemplify the embodiments of the present invention, which can fully describe the technical contents of the present invention to make the technical content of the present invention clearer and easy to understand. However, the present invention may be embodied in many different forms of embodiments, and the scope of the present invention is not particularly limited to the embodiments set forth herein. In the present invention, unless otherwise expressly stated and limited, the formation of a first feature over or under a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the first feature “above”, “over” and “on” the second feature includes the first feature directly above and above the second feature, or merely indicating that the first feature is at a level higher than the second feature. The first feature “below”, “under” and “beneath” the second feature includes the first feature directly below and obliquely below the second feature, or merely the first feature has a level lower than the second feature. In the description of this application, it should be understood that the terms “center”, “longitudinal”, “transverse”, “length”, “width”, “thickness”, “upper”, “lower”, “front”, “Rear”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, and the like are based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, structure and operation in a specific orientation, which should not be construed as limitations on the present invention. In addition, the terms “first” and “second” are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of “a plurality” is two or more, unless specifically defined otherwise. In the drawings, the thickness of layers and areas are exaggerated for clarity. For example, for ease of description, the thicknesses and sizes of the elements in the drawings are arbitrarily shown, and therefore, the described technical scope is not particularly limited by the drawings. As shown inFIG.3andFIG.4, an array substrate100is provided in an embodiment of the present application, which is provided with a plurality of rows of pixel units110; the plurality of rows of pixel units110are arranged in tandem to form an array structure. As shown inFIG.3, each of the pixel units110includes a transistor area10and a pixel area20; and a main transistor unit11, a sub-transistor unit12, and a shared transistor unit13are provided in the transistor area10. Each of the main transistor unit11, the sub-transistor unit12, and the shared transistor unit13includes a source and a drain; each row of the pixel units110includes a shared metal wiring1; the shared metal wiring1is provided above the transistor area10, extends along the arrangement direction of the pixel units110in the corresponding one of the rows, and is electrically connected to the source of the shared transistor unit13in each of the pixel units110in turn. The shared metal wiring1is exactly above positions of the sources of the shared transistor units13, and meanwhile, the shared metal wiring1is electrically connected to the source of the shared transistor unit in each of the pixel units110in turn, so that the source wirings of the shared transistor units13can be saved, thereby increasing the aperture ratio and reducing the manufacturing cost. As shown inFIG.5, in this embodiment, the shared transistor unit13includes a glass substrate31, a first metal layer32, a gate insulating layer33, a second metal layer34, a passivation layer35, and the shared metal wiring1, which are stacked; wherein the first metal layer32is disposed on the glass substrate31; the gate insulating layer33is disposed on the glass substrate31and covers the first metal layer32; the second metal layer34is disposed on the gate insulating layer33; the passivation layer35is disposed on the gate insulating layer33, covers the second metal layer34, and includes a via hole36to expose an upper surface of the second metal layer34; the shared metal wiring1is disposed on the passivation layer35and passes through the via hole36to electrically connect the second metal layer34. In this embodiment, the material of the shared metal wiring1includes indium tin oxide, which is a transparent material, so that the shared metal wiring1is a transparent wiring, which improves the light transmittance. In this embodiment, the shared metal wiring1includes a widened portion101at a position corresponding to the via hole36, and the widened portion101protrudes from an edge of the shared metal wiring1toward a side of the transistor area10. The provision of the widened portion101can facilitate the reduction of the width of the shared metal wiring1so as to increase the light transmittance while ensuring that the shared metal wiring1passes through the via hole36and is electrically connect the second metal layer34, thus avoiding the problem of disconnection. In this embodiment, the pixel unit110includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the shared metal wiring1is electrically connected to the blue sub-pixel. Since the driving voltage of the blue sub-pixel is higher than the driving voltages of the red sub-pixel and the green sub-pixel, the signal voltage of the shared metal wiring1will be higher, which is beneficial to control leakage condition of the shared transistor unit13, thereby avoiding the leakage of the shared transistor unit13. In this embodiment, the transistor area10includes a scan line2, and the shared metal wiring1is arranged in parallel with the scan line2. That is, the shared metal wiring1extends along the arrangement direction of a row of the pixel units110. The first metal layer32can be used as the gate of the shared transistor unit13to connect the scan line2. In this embodiment, the shared metal wiring1made of transparent indium tin oxide is electrically connected to the source of the shared transistor unit13of each of the pixel units110, so that the source of the shared transistor unit13does not need to penetrate through the pixel area20, thereby increasing the aperture ratio of the pixel area20and increasing the transmittance of the display panel; and the shared metal wiring1connects the shared transistor units13to uniformly control the leakage of the shared transistor unit13. It has been verified that compared with the 8-domain pixel structure shown inFIG.2of the prior art, this embodiment can increase the aperture ratio of the pixel area20by 7%-10% compared with the 8-domain pixel structure shown inFIG.2. Accordingly, the light transmittance of the display panel is increased by 7%-10%, thereby improving the image quality and enhancing the competitiveness of the product. In this embodiment, the pixel area20is disposed on one side of the transistor area10; the arrangement direction of the pixel area20and the transistor area10is perpendicular to the extending direction of the shared metal wiring1. That is, the pixel area20and the transistor area10are arranged in a longitudinal direction and perpendicular to the scan line2. In this embodiment, the pixel area20includes a main pixel area21and a sub-pixel area22; the main pixel area21is arranged adjacent to the transistor area10and is electrically connected to the source of the main transistor unit11. The sub-pixel area22is disposed on the side of the main pixel area21away from the transistor area10, and is electrically connected to the drains of the sub-transistor unit12and the shared transistor unit13. In more detail, the main pixel area21is disposed on one side of the transistor area10, and a first pixel electrode211is provided in the main pixel area21. The first pixel electrode211is electrically connected to the drain of the main transistor unit11, and the sub-pixel area22is disposed on the side of the main pixel area21away from the transistor area10. The sub-pixel area22is U-shaped to half-enclose around the main pixel area21, wherein the U-shaped half-enclosed surrounding may also be referred to half-enclosed wrapping, three-side surrounding, wrapping along the transistor area10, etc. A second pixel electrode221is provided in the sub-pixel area22, and the second pixel electrode221and the first pixel electrode211are not electrically connected to each other, and the second pixel electrode221is electrically connected to the drains of the sub-transistor unit12and the shared transistor unit13. In this embodiment, each of the first pixel electrode211and the second pixel electrode221includes a trunk and a branch. The trunks located in the main pixel area21and the sub-pixel area22extend in a longitudinal direction on the same straight line, and preferably the straight line extending in the longitudinal direction where the trunks are located is the median line of the main pixel area21and the sub-pixel area22. In this embodiment, by placing the main pixel area21and the sub-pixel area22on the same side of the transistor area10, the area occupied by the transistor area10is reduced. Meanwhile, the sub-pixel area22forms a semi-enclosed structure to surrounds the main pixel area21, which can reduce the coupling capacitance formed in the main pixel area21and improve the color shift. In this embodiment, the top view projection of the main pixel area21is an axially symmetrical pattern, and the axially symmetrical pattern may be symmetrical with respect to the transverse axis or symmetrical with respect to the longitudinal axis. The shape of the top view projection of the main pixel area21specifically includes, but is not particularly limited to, a symmetrical cone, a symmetrical triangle, a symmetrical semicircle, a symmetrical inverted trapezoid, a concave rectangle, an hourglass shape, or a rectangle. In this embodiment, it is preferably a rectangle, as shown inFIG.3andFIG.4. In this embodiment, the array substrate100further includes a data wiring3, which is arranged between adjacent ones of the sub-pixel areas22; the data wiring3is electrically connected to the sources of the first transistor unit and the second transistor unit. In this embodiment, the area of the main pixel area21is smaller than the area of the sub pixel area22. In this way, the sub-pixel area22can be arranged in a U-shaped to half-enclose around the main pixel area21, and the distance between the main pixel area21and the data wiring3can be increased, thereby reducing the coupling capacitance therebetween, thus improving color shift. In this embodiment, the data wiring3is provided under the second pixel electrodes221in adjacent ones of the sub-pixel areas22, and a projection of the data wiring3overlaps a projection of the second pixel electrode221, so that a capacitor can be formed between the data wiring3and the second pixel electrode221, and the common electrode wiring between adjacent ones of the sub-pixel areas, and the source and the drain wirings surrounding the main pixel area and the sub-pixel area as shown inFIG.2in the prior art can be removed, which can shorten the distance between the borders of the second pixel electrodes of adjacent ones of the sub-pixel areas22, thereby increasing the distribution width of the pixel electrodes in the main pixel area21and the sub-pixel area22, thus increasing the aperture ratio. In this embodiment, the projections of the data wiring3and the main pixel area21do not overlap each other, so that the formation of the coupling capacitance between the data wiring3and the main pixel area21, thereby improving color shift. Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, and the display device includes the array substrate100provided by the any of the above embodiments. The display panel in the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. The working principle of the display panel provided in this embodiment is consistent with the working principle of the foregoing embodiment of the array substrate100. Specific structural relationships and working principles can be referred to the foregoing embodiment of the array substrate100, and will not be repeated herein for brevity. The technical effect of the present application is to provide an array substrate and a display panel. On the one hand, a shared metal wiring made of indium tin oxide is electrically connected to the source of the shared transistor unit of each of the pixel units, such that the source of the shared transistor unit does not need to penetrate through the pixel area, thereby increasing the aperture ratio of the pixel area and increasing the transmittance of the display panel; and the shared metal wiring connects the shared transistor units, which can uniformly control the leakage of the shared transistor units. On the other hand, by arranging the main pixel area and the sub-pixel area on the same side of the transistor area, the area occupied by the transistor area is reduced; and meanwhile, the sub-pixel area forms a structure to half-enclose around the main pixel area, which can increase the distance between the main pixel area and the main data area to reduces the coupling capacitance therebetween and improve the color shift. On further the other hand, the common electrode wiring between adjacent ones of the sub-pixel areas, and the source and the drain wirings surrounding the main pixel area and the sub-pixel area are removed, which can shorten the distance between the borders of the second pixel electrodes of adjacent ones of the sub-pixel areas, thereby increasing the distribution width of the pixel electrodes in the main pixel area and the sub-pixel area, thus increasing the aperture ratio. Those skilled in the art should understand that the scope of the invention involved in this application is not a technical solution formed by a specific combination of the above technical features, and should also cover the replacement of the above technical features without departing from the inventive concept. Other technical solutions formed by arbitrarily combining the same features. For example, the above-mentioned features are similar to those disclosed in this application (but not limited to). The above-mentioned are only the preferred embodiments of the present invention. It is appropriately pointed out that for those of ordinary skill in the art, they can substitute without departing from the principle of the present invention. Next, some improvements and modifications can also be made, and these improvements and modifications should also be regarded as the protection scope of the present invention. The array substrate and the display panel provided in the embodiments of the present application have been described in detail above. Specific examples are used in this document to explain the principles and implementation of the present invention. The descriptions of the above embodiments are only for understanding the method of the present invention and its core ideas, to help understand the technical solution of the present application and its core ideas, and a person of ordinary skill in the art should understand that it can still modify the technical solution described in the foregoing embodiments, or equivalently replace some of the technical features. Such modifications or replacements do not depart the spirit of the corresponding technical solutions beyond the scope of the technical solutions of the embodiments of the present application. | 17,115 |
11942488 | DETAILED DESCRIPTION Aspects of some example embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be more thorough and more complete, and will more fully convey the scope of embodiments according to the invention to those skilled in the art. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numbers indicate the same components throughout the specification. In the attached figures, the thickness of layers and regions is exaggerated for clarity. Although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements, should not be limited by these terms. These terms may be used to distinguish one element from another element. Thus, a first element discussed below may be termed a second element without departing from teachings of one or more embodiments. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms “first”, “second”, etc. may also be used herein to differentiate different categories or sets of elements. For conciseness, the terms “first”, “second”, etc. may represent “first-category (or first-set)”, “second-category (or second-set)”, etc., respectively. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments without substantially departing from the principles of embodiments according to the present invention. Therefore, the disclosed example embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation. Hereinafter, specific embodiments will be described in more detail with reference to the attached drawings. FIG.1is a plan view of a display device1according to some example embodiments.FIG.2is a schematic block diagram of the display device1according to some example embodiments. The display device1is a device for displaying moving (e.g., video) images or still (e.g., static) images. The display device1may be used as a display screen in portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs), as well as in various products such as televisions, notebook computers, monitors, billboards and the Internet of things (IoT). The display device1according to some example embodiments may be substantially rectangular in a plan view (e.g., when viewed in a direction perpendicular or normal with respect to the primary plane of the display surface). The display device1may be shaped like a rectangle with right-angled corners in a plan view. However, embodiments according to the present disclosure are not limited thereto, and the display device1may also be shaped like a rectangle with rounded corners in a plan view. In the drawings, a first direction DR1indicates a horizontal direction of the display device1in a plan view, and a second direction DR2indicates a vertical direction of the display device1in a plan view. In addition, a third direction DR3indicates a thickness direction of the display device1. The first direction DR1and the second direction DR2perpendicularly intersect each other, and the third direction DR3perpendicularly intersects both the first direction DR1and the second direction DR2in a direction intersecting a plane in which the first direction DR1and the second direction DR2lie. However, directions mentioned with respect to the described example embodiments should be understood as relative directions, and the embodiments are not limited to the mentioned directions. Unless otherwise defined, the terms “upper,” “upper surface” and “upper side” used herein based on the third direction DR3refer to a display surface side of the display device1, and the terms “lower,” “lower surface” and “lower side” refer to an opposite side of the display device1from the display surface side. The display device1according to some example embodiments may include a display panel10, a timing controller21, a data driver22, and a scan driver30. The display panel10may be an organic light emitting display panel. In the following example embodiments, an embodiment where an organic light emitting display panel is utilized as the display panel10will be described as an example. However, embodiments according to the present disclosure are not limited to this embodiment, and other types of display panels such as a liquid crystal display (LCD) panel, a quantum-dot organic light emitting display (QD-OLED) panel, a quantum-dot LCD (QD-LCD) panel, a quantum-nano light emitting display (QNED) panel, and a micro light emitting diode (Micro LED) display panel are also applicable. The display panel10may include a display area DA where a images may be displayed and a non-display area NDA where images are not displayed (e.g., a bezel area, or a region where there are no pixels). The display panel10may be divided into the display area DA and the non-display area NDA in a plan view. The non-display area NDA may surround the display area DA. The non-display area NDA may form a bezel. The display area DA may be shaped like a rectangle with right-angled corners or a rectangle with rounded corners in a plan view. The planar shape of the display area DA is not limited to the rectangle, but may also be a circle, an ellipse, or various other shapes. The display area DA may include a plurality of pixels PX. The pixels PX may be arranged in a matrix shape. Each of the pixels PX may include a light emitting layer and a circuit layer for controlling the amount of light emitted from the light emitting layer. The circuit layer may include a wiring, an electrode, and at least one transistor. The light emitting layer may include an organic light emitting material. The light emitting layer may be sealed by an encapsulation layer. The detailed configuration of each pixel PX will be described in more detail later. The non-display area NDA may be located adjacent to both short sides and both long sides of the display area DA. In this case, the non-display area NDA may surround all sides of the display area DA and form edges of the display area DA. However, embodiments according to the present disclosure are not limited thereto, and the non-display area NDA may also be located adjacent to only both short sides or both long sides of the display area DA. In the display area DA, not only the pixels PX, but also a plurality of scan lines SL1through SLk (where k is an integer of 2 or more), a plurality of data lines DL1through DLj (where j is an integer of 2 or more) and a plurality of power lines connected to the pixels PX may be arranged. The scan lines SL (SL1through SLk) may extend in the first direction DR1and may be arranged along the second direction DR2. The data lines DL (DL1through DLj) may extend in the second direction DR2and may be arranged along the first direction DR1. The display panel10includes the pixels PX located at intersections of the scan lines SL1through SLk (where k is an integer of 2 or more) and the data lines DL1through DLj (where j is an integer of 2 or more) and arranged in a matrix shape. Each of the pixels PX may be connected to at least any one of the scan lines SL (SL1through SLk) and any one of the data lines DL (DL1through DLj). The timing controller21receives digital video data DATA and timing signals from a host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The host system may be an application processor of a smartphone or tablet PC or a system on chip of a monitor or television (TV). The timing controller21generates control signals CS for controlling the operation timing of the data driver22and the scan driver30. The control signals CS may include a source control signal CONT2for controlling the operating timing of the data driver22and a scan control signal CONT1for controlling the operation timing of the scan driver30. The scan driver30receives the scan control signal CONT1from the timing controller21. The scan driver30generates scan signals S1through Sk (where k is an integer of 2 or more) according to the scan control signal CONT1and supplies the scan signals S1through Sk to the scan lines SL1through SLk of the display panel10. The scan driver30may include a plurality of thin-film transistors and may be formed in the non-display area NDA of the display panel10. Alternatively, the scan driver30may be formed as an integrated circuit. In this case, the scan driver30may be mounted on a gate flexible film attached to another side of the display panel10. The data driver22receives the digital video data DATA and the source control signal CONT2from the timing controller21. The data driver22converts the digital video data DATA into analog data voltages according to the source control signal CONT2and supplies the analog data voltages to the data lines DL1through DLj of the display panel10. Each of the pixels PX emits light of a luminance level (e.g., a predetermined luminance level) according to a driving current supplied to a light emitting element in response to one of data signals D1through Dj (where j is an integer of 2 or more) received through the data lines DL1through DLm. A power supply circuit may generate voltages necessary for driving the display panel10from main power applied from a system board and supply the generated voltages to the display panel10. For example, the power supply circuit may generate from the main power a first power supply voltage ELVDD (seeFIG.3) and a second power supply voltage ELVSS (seeFIG.3) for driving light emitting elements OLED of the display panel10and supply the generated voltages ELVDD and ELVSS to a first power line ELVDL (seeFIG.3) and a second power line ELVSL (seeFIG.3) of the display panel10. In addition, the power supply circuit may generate driving voltages for driving the timing controller21, the data driver22, the scan driver30, etc. from the main power and supply the generated voltages. The power supply circuit may be formed as an integrated circuit and mounted on a circuit board, but embodiments according to the present disclosure are not limited thereto. FIG.3is an equivalent circuit diagram of one pixel PX of the display device1according to some example embodiments. Referring toFIG.3, the pixel PX may include a first transistor TR1, a second transistor TR2, a light emitting element OLED, and a capacitor Cst. Although each pixel PX has a 2TIC structure including two transistors TR1and TR2and one capacitor Cst inFIG.3, embodiments according to the present disclosure are not limited thereto. Each pixel PX may also include a plurality of pixels and a plurality of capacitors. For example, each pixel PX may also have various modified pixel structures such as a 3TIC structure, a 6TIC structure, and a 7TIC structure. Each of the first and second transistors TR1and TR2may include a first source/drain electrode, a second source/drain electrode, and a gate electrode. One of the first source/drain electrode and the second source/drain electrode may be a source electrode, and the other may be a drain electrode. Each of the first and second transistors TR1and TR2may be formed as a thin-film transistor. In addition, although each of the transistors TR1and TR2is described as an N-type metal oxide semiconductor field effect transistor (MOSFET) inFIG.3, the present disclosure is not limited thereto. Each of the first transistor TR1and the second transistor TR2may also be formed as a P-type MOSFET. In this case, positions of the source electrode and the drain electrode of each of the first transistor TR1and the second transistor TR2may be changed. An embodiment in which each of the first and second transistors TR1and TR2is an N-type MOSFET will be described in more detail below. The first transistor TR1may be a driving transistor. For example, the gate electrode of the first transistor TR1is connected to the second source/drain electrode of the second transistor TR2and a second electrode of the capacitor Cst. The first source/drain electrode of the first transistor TR1is connected to the first power line ELVDL. The second source/drain electrode of the first transistor TR1is connected to an anode of the light emitting element OLED. The first transistor TR1receives a data signal Dj (where j is an integer of 1 or more) according to a switching operation of the second transistor TR2and supplies a driving current to the light emitting element OLED. The gate electrode of the second transistor TR2is connected to a scan line SL. The first source/drain electrode of the second transistor TR2is connected to a data line DL. The second source/drain electrode of the second transistor TR2is connected to the gate electrode of the first transistor TR1and the second electrode of the capacitor Cst. The second transistor TR2is turned on by a scan signal Sk (where k is an integer of 1 or more) to perform a switching operation for transmitting the data signal Dj (where j is an integer of 1 or more) to the gate electrode of the first transistor TR1. A first electrode of the capacitor Cst may be connected to the first power line ELVDL and the first source/drain electrode of the first transistor TR1, and the second electrode of the capacitor Cst may be connected to the gate electrode of the first transistor TR1and the second source/drain electrode of the second transistor TR2. The capacitor Cst may keep a data voltage applied to the gate electrode of the first transistor TR1constant. The light emitting element OLED may emit light according to a driving current of the first transistor TR1. The light emitting element OLED may be an organic light emitting diode including an anode (or a first electrode), an organic light emitting layer, and a cathode (or a second electrode). The anode of the light emitting element OLED may be connected to the second source/drain electrode of the first transistor TR1, and the cathode of the light emitting element OLED may be connected to the second power line ELVSL to which the second power supply voltage ELVSS lower than the first power supply voltage ELVDD is applied. The planar layout and cross-sectional structure of the above-described pixel PX will now be described in more detail. FIG.4is a layout view of one pixel PX of the display device1according to some example embodiments.FIG.5is a layout view of a buffer layer120according to some example embodiments.FIG.6is a layout view of a semiconductor layer130according to some example embodiments.FIG.7is a cross-sectional view taken along the line VII-VII′ ofFIG.4. Referring toFIGS.4through7, the pixel PX may include an emission area EA and a circuit area CA. The emission area EA is an area in which the light emitting element OLED is arranged and emits light. The circuit area CA is electrically connected to the data line DL and the scan line SL and includes the first transistor TR1, the second transistor TR2, and the capacitor Cst. Furthermore, the circuit area CA may include a first transistor region TRR1, a second transistor region TRR2, and a capacitor region CPR. The circuit area CA is an area for driving the light emitting element OLED. Each of the transistors TR1and TR2includes a conductive layer forming an electrode, a semiconductor pattern forming a channel, and an insulating layer. The capacitor Cst includes conductive layers forming an electrode and an insulating layer arranged between the conductive layers. For example, the capacitor Cst includes a first electrode113(or a capacitor lower electrode) of the capacitor Cst, a second electrode143(or a capacitor upper electrode) of the capacitor Cst, and an insulating layer arranged between the first electrode113and the second electrode143. The conductive materials or conductive layers, the semiconductor layers, and the insulating layers described above are arranged on a base substrate101. The display panel10according to some example embodiments includes the semiconductor layer130, a plurality of conductive layers and a plurality of insulating layers arranged on the base substrate101. The conductive layers may include a first conductive layer110, a second conductive layer140, and an anode ANO. The insulating layers may include the buffer layer120, a gate insulating layer GI, a passivation layer PVX, and a via layer VIA. The layers of the display panel10may be arranged on the base substrate101in the order of a barrier layer102, the first conductive layer110, the buffer layer120, the semiconductor layer130, the gate insulating layer GI, the second conductive layer140, the passivation layer PVX, the via layer VIA, the anode ANO, and a pixel defining layer PDL. Each of the above layers may be a single layer or a stack of a plurality of layers. Another layer may also be arranged between the above layers. The base substrate101supports each layer arranged thereon. The base substrate101may be made of an insulating material such as polymer resin. The polymer material may be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination of the same. The base substrate101may also include a metal material. The base substrate101may be a flexible substrate that can be bent, folded, rolled, etc. The material that forms the flexible substrate may be, but is not limited to, polyimide (PI). When an organic light emitting display device is of a bottom emission type or a double-sided emission type, a transparent substrate may be used. When the organic light emitting display device is of a top emission type, not only a transparent substrate but also a translucent or opaque substrate may be applied. The barrier layer102may be arranged on the base substrate101. The barrier layer102may prevent or reduce diffusion of impurity ions, prevent or reduce penetration of moisture or outside air, and perform a surface planarization function. The barrier layer102may include silicon nitride, silicon oxide, or silicon oxynitride. The barrier layer102can be omitted depending on the type of the base substrate101or processing conditions. The first conductive layer110is arranged on the barrier layer102. However, the present disclosure is not limited thereto. When the barrier layer102is omitted, the first conductive layer110may be arranged on the base substrate101. The first conductive layer110may be arranged in the display area DA and may include a first power wiring111corresponding to the first power line ELVDL (seeFIG.3), a lower light blocking pattern114, a data wiring112corresponding to the data line DL (seeFIG.3), and the first electrode113of the capacitor Cst. The first power wiring111may be located on a right side of the pixel PX in plan view. The first power wiring111may extend in the second direction DR2. The first power wiring111may extend to another pixel PX neighboring the pixel PX in the second direction DR2. The first power wiring111may pass through the first transistor region TRR1. In the drawings, a part of the first power wiring111extending in the second direction DR2protrudes in the first direction DR1, and the protruding part overlaps the first transistor region TRR1. However, the present disclosure is not limited thereto. For example, the first power wiring111may also pass through the first transistor region TRR1without the above protruding part while extending in the second direction DR2. The first power wiring111may pass through at least a part of the first transistor region TRR1to overlap in the thickness direction and directly contact at least a part of a first source/drain electrode141aof the first transistor TR1which will be described later. In other words, the first source/drain electrode141aof the first transistor TR1may be formed on the first power wiring111, and at least a part of an upper surface and/or a side surface of the first power wiring111may be covered by the first source/drain electrode141aof the first transistor TR1. The data wiring112may be located on a left side of the pixel PX in plan view and extend in the second direction DR2. The data wiring112may extend to another pixel PX neighboring the pixel PX in the second direction DR2. The data wiring112may be located on the left side of the first power wiring111and spaced apart from the first power wiring111. The data wiring112may pass through the second transistor region TRR2. In the drawings, a part of the data wiring112extending in the second direction DR2protrudes in the first direction DR1, and the protruding part overlaps the second transistor region TRR2. However, the present disclosure is not limited thereto. For example, the data wiring112may also pass through the second transistor region TRR2without the above protruding part while extending in the second direction DR2. The data wiring112may pass through at least a part of the second transistor region TRR2to overlap in the thickness direction and directly contact at least a part of a first source/drain electrode142aof the second transistor TR2which will be described later. In other words, the first source/drain electrode142aof the second transistor TR2may be formed on the data wiring112, and at least a part of an upper surface and/or a side surface of the data wiring112may be covered by the first source/drain electrode142aof the second transistor TR2. The first electrode113of the capacitor Cst may protrude in the first direction DR1from the first power wiring111and may be generally located in a central part of the circuit area CA. The first electrode113of the capacitor Cst may be arranged between the first power wiring111and the data wiring112in plan view. For example, on the left side of the first power wiring111and on the right side of the data wiring112, the first electrode113of the capacitor Cst may be connected to the first power wiring111and spaced apart from the data wiring112. According to some example embodiments, the first electrode113of the capacitor Cst may be generally rectangular, but the present disclosure is not limited thereto. The lower light blocking pattern114may be formed in the first transistor region TRR1. The lower light blocking pattern114may prevent or reduce light incident from under the display panel10from entering a semiconductor pattern131of the first transistor TR1located above the lower light blocking pattern114, in particular, a channel region131cof the semiconductor pattern131. That is, the lower light blocking pattern114may cover at least the channel region131cof the semiconductor pattern131of the first transistor TR1and, by extension, cover the whole of the semiconductor pattern131of the first transistor TR1. That is, the lower light blocking pattern114may overlap at least the channel region131cof the semiconductor pattern131of the first transistor TR1. In addition, the lower light blocking pattern114may be used as another gate electrode of an oxide transistor. In this case, the lower light blocking pattern114may be electrically connected to a gate electrode141cof the first transistor TR1. The first conductive layer110may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer110may be a single layer or a multilayer. The buffer layer120is arranged on the first conductive layer110. The buffer layer120may be entirely arranged on the first conductive layer110and the barrier layer102exposed by the first conductive layer110in the display area DA and the non-display area NDA. The buffer layer120may cover the first conductive layer110in the display area DA and the non-display area NDA and may be arranged on the entire surface of the barrier layer102. The buffer layer120may serve as an interlayer insulating film that insulates the first conductive layer110and the semiconductor layer130from each other. As will be described later, the buffer layer120may be formed to have the same planar shape as the semiconductor layer130. The buffer layer120may include a first buffer region121, a second buffer region122, and a third buffer region123. The first buffer region121and the second buffer region122may be arranged in each pixel PX, and the third buffer region123may be arranged over a plurality of pixels PX. The first buffer region121and the second buffer region122may be arranged in the circuit area CA of each pixel PX, and the third buffer region123may be arranged in most of the emission area EA and the circuit area CA of each pixel PX while being arranged over a plurality of pixels PX as described above. For example, the first buffer region121may be arranged in the first transistor region TRR1, and the second buffer region122may be arranged in the second transistor region TRR2. A part of the third buffer region123may be arranged in the capacitor region CPR to fill the remaining area of the pixel PX in which the first buffer region121and the second buffer region122are not arranged. That is, the third buffer region123may occupy most of the area of the buffer layer120. The first buffer region121and the second buffer region122may extend in the first direction DR1and may be spaced apart from each other. However, the present disclosure is not limited thereto, and the first buffer region121and/or the second buffer region122may also extend in the second direction DR2. Alternatively, the first buffer region121and the second buffer region122may be connected to each other and spaced apart from the third buffer region123. The buffer layer120may further include a first buffer opening OPB1and a second buffer opening OPB2defined by the third buffer region123. The first buffer opening OPB1and the second buffer opening OPB2may be arranged in the circuit area CA and spaced apart from each other. The first buffer region121may be arranged in the first buffer opening OPB1, and the second buffer region122may be arranged in the second buffer opening OPB2. The first buffer region121and the second buffer region122may be spaced apart from each other and formed in an island shape in plan view. The first buffer region121and the second buffer region122may be spaced apart from the third buffer region123and surrounded by the third buffer region123. The first buffer opening OPB1and the second buffer opening OPB2may expose at least a part of the underlying barrier layer102and/or at least a part of the underlying first conductive layer110in an area where the first buffer region121and the second buffer region122are not arranged. At least a part of the first conductive layer110may be arranged in the first buffer opening OPB1and the second buffer opening OPB2. In the drawings, only a part of the first power wiring111and only a part of the data wiring112are arranged in the first buffer opening OPB1and the second buffer opening OPB2, and the whole of the lower light blocking pattern114is arranged in the first buffer opening OPB1. However, the present disclosure is not limited thereto. The first buffer opening OPB1may overlap the first transistor region TRR1, and the second buffer opening OPB2may overlap the second transistor region TRR2. In other words, the first transistor TR1may be arranged in the first buffer opening OPB1in plan view. That is, the semiconductor pattern131, the first source/drain electrode141a, a second source/drain electrode141band the gate electrode141cof the first transistor TR1may overlap the first buffer opening OPB1in the thickness direction (the third direction DR3). In addition, the second transistor TR2may be arranged in the second buffer opening OPB2in plan view. That is, a semiconductor pattern132, the first source/drain electrode142a, a second source/drain electrode142band a gate electrode142cof the second transistor TR2may overlap the second buffer opening OPB2in the thickness direction (the third direction DR3). The second conductive layer140, the passivation layer PVX, and/or the via layer VIA may be arranged in a space between the first buffer region121, the second buffer region122, and the third buffer region123. That is, the second conductive layer140, the passivation layer PVX and/or the via layer VIA may fill a space in which the first buffer region121and the second buffer region122are not arranged in the first buffer region OPB1and the second buffer region OPB2. The buffer layer120may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The buffer layer120can be omitted depending on the type of the base substrate101or processing conditions. The semiconductor layer130may be arranged on the buffer layer120. In other words, the semiconductor layer130may overlap the buffer layer120and have the same planar shape as the buffer layer120. The semiconductor layer130may be arranged on the entire surface of the buffer layer120in the display area DA and the non-display area NDA. The semiconductor layer130may be arranged in the emission area EA and the circuit area CA of the pixel PX. For example, the semiconductor layer130may include the semiconductor pattern131of the first transistor TR1, the semiconductor pattern132of the second transistor TR2, and a semiconductor dummy part133. The semiconductor pattern131of the first transistor TR1may be an active layer of the first transistor TR1, and the semiconductor pattern132of the second transistor TR2may be an active layer of the second transistor TR2. The semiconductor dummy part133may be a part of the semiconductor layer130excluding the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2and may occupy most of the area of the semiconductor layer130. The semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2may be arranged in each pixel PX, and the semiconductor dummy part133may be arranged over a plurality of pixels PX. The semiconductor pattern131of the first transistor TR1may be arranged in the first transistor region TRR1, and the semiconductor pattern132of the second transistor TR2may be arranged in the second transistor region TRR2. The semiconductor dummy part133may be arranged in the capacitor region CPR and arranged in most of the circuit area CA and the emission area EA of the pixel PX. The semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2may extend in the first direction DR1and may be spaced apart from each other. However, the present disclosure is not limited thereto, and the semiconductor pattern131of the first transistor TR1and/or the semiconductor pattern132of the second transistor TR2may also extend in the second direction DR2. Alternatively, the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2may be connected to each other and spaced apart from the semiconductor dummy part133. The semiconductor pattern131of the first transistor TR1, the semiconductor pattern132of the second transistor TR2and the semiconductor dummy part133of the semiconductor layer130may have substantially the same planar shapes as the first buffer region121, the second buffer region122and the third buffer region123of the buffer layer120, respectively. For example, the planar shape of the semiconductor pattern131of the first transistor TR1may be substantially the same as the planar shape of the first buffer region121of the buffer layer120. A length of the semiconductor pattern131of the first transistor TR1extending in the first direction DR1may be equal to or smaller than a length of the first buffer region121extending in the first direction DR1. In addition, a width of the semiconductor pattern131of the first transistor TR1in the second direction DR2may be equal to or smaller than a width of the first buffer region121in the second direction DR2. In this case, the semiconductor pattern131of the first transistor TR1and the first buffer region121may completely overlap each other so that side surfaces of the semiconductor pattern131of the first transistor TR1are aligned with side surfaces of the first buffer region121or that the whole of the semiconductor pattern131of the first transistor TR1overlaps at least a part of the first buffer region121. The planar shape of the semiconductor pattern132of the second transistor TR2may be substantially the same as the planar shape of the second buffer region122of the buffer layer120. A length of the semiconductor pattern132of the second transistor TR2extending in the first direction DR1may be equal to or smaller than a length of the second buffer region122extending in the first direction DR1. In addition, a width of the semiconductor pattern132of the second transistor TR2in the second direction DR2may be equal to or smaller than a width of the second buffer region122in the second direction DR2. In this case, the semiconductor pattern132of the second transistor TR2and the second buffer region122may completely overlap each other so that side surfaces of the semiconductor pattern132of the second transistor TR2are aligned with side surfaces of the second buffer region122or that the whole of the semiconductor pattern132of the second transistor TR2overlaps at least a part of the second buffer region122. The planar shape of the semiconductor dummy part133may be substantially the same as the planar shape of the third buffer region123of the buffer layer120. The semiconductor dummy part133may completely overlap the third buffer region123of the buffer layer120, and side surfaces of the semiconductor dummy part133may be aligned with side surfaces of the third buffer region123of the buffer layer120. However, the present disclosure is not limited thereto, and the whole of the semiconductor dummy part133may also overlap a part of the third buffer region123. The semiconductor layer130may further include a first semiconductor opening OPS1and a second semiconductor opening OPS2defined by the semiconductor dummy part133. The first semiconductor opening OPS1and the second semiconductor opening OPS2of the semiconductor layer130may be formed to have substantially the same shape as the first buffer opening OPB1and the second buffer opening OPB2of the buffer layer120, respectively. In other words, the planar shape of the first semiconductor opening OPS1may be substantially the same as the planar shape of the first buffer opening OPB1, and the first semiconductor opening OPS1may overlap the first buffer opening OPB1. The planar shape of the second semiconductor opening OPS2may be substantially the same as the planar shape of the second buffer opening OPB2, and the second semiconductor opening OPS2may overlap the second buffer opening OPB2. The semiconductor pattern131of the first transistor TR1may be arranged in the first semiconductor opening OPS1, and the semiconductor pattern132of the second transistor TR2may be arranged in the second semiconductor opening OPS2. That is, the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2may be spaced apart from each other and formed in an island shape in plan view. In addition, the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2may be spaced apart from the semiconductor dummy part133and surrounded by the semiconductor dummy part133. The second conductive layer140, the passivation layer PVX, and/or the via layer VIA may be arranged in a space between the semiconductor pattern131of the first transistor TR1, the semiconductor pattern132of the second transistor TR2, and the semiconductor dummy part133. That is, the second conductive layer140, the passivation layer PVX and/or the via layer VIA may fill a space in which the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2are not arranged in the first semiconductor opening OPS1and the second semiconductor opening OPS2. The first semiconductor opening OPS1may overlap the first transistor region TRR1, and the second semiconductor opening OPS2may overlap the second transistor region TRR2. The semiconductor pattern131of the first transistor TR1may include the channel region131cof the first transistor TR1which is overlapped by the overlying gate electrode141cof the first transistor TR1in the thickness direction and a first source/drain region131aof the first transistor TR1and a second source/drain region131bof the first transistor TR1which are located on a side and the other side of the channel region131c, respectively. The first and second source/drain regions131aand131bof the first transistor TR1may be conducting regions and may have higher conductivity and lower electrical resistance than the channel region131cof the first transistor TR1. The semiconductor pattern132of the second transistor TR2may include a channel region132cof the second transistor TR2which is overlapped by the overlying gate electrode142cof the second transistor TR2in the thickness direction and a first source/drain region132aof the second transistor TR2and a second source/drain region132bof the second transistor TR2which are located on a side and the other side of the channel region132c, respectively. The first and second source/drain regions132aand132bof the second transistor TR2may be conducting regions and may have higher conductivity and lower electrical resistance than the channel region132cof the second transistor TR2. The semiconductor layer130may include an oxide semiconductor. Examples of the oxide semiconductor may include a binary compound (ABx), a ternary compound (ABxCy) and a quaternary compound (ABxCyDz) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. According to some example embodiments, the semiconductor layer130may include indium tin zinc oxide (IGZO). The gate insulating layer GI is arranged on the semiconductor layer130. The gate insulating layer GI may be arranged on only a part of the semiconductor layer130. That is, the gate insulating layer GI may overlap a part of the semiconductor layer130. The gate insulating layer GI may cover the channel regions131cand132cof the semiconductor layer130and expose the first and second source/drain regions131a,131b,132aand132band side surfaces of the semiconductor layer130. The gate insulating layer GI may include a first gate insulating layer region GI1, a second gate insulating layer region GI2, and a third gate insulating layer region GI3. The first gate insulating layer region GI1may be arranged in the first transistor region TRR1, and the second gate insulating layer region GI2may be located in the second transistor region TRR2. The third gate insulating layer region GI3may be located in the capacitor region CPR and located in most of the non-display area NDA and the circuit area CA and the emission area EA of the display area DA. The third gate insulating layer region GI3may occupy most of the area of the gate insulating layer GI. However, the present disclosure is not limited thereto, and the third gate insulating layer region GI3can be removed depending on the process. The first gate insulating layer region GI1may have substantially the same planar shape as the gate electrode141cof the first transistor TR1located on the first gate insulating layer region GI1, and the second gate insulating layer region GI2may have substantially the same planar shape as the gate electrode142cof the second transistor TR2located on the second gate insulating layer region GI2. The third gate insulating layer region GI3may have substantially the same planar shape as the semiconductor dummy part133of the semiconductor layer130and the third buffer region123of the buffer layer120located under the third gate insulating layer region GI3. Side surfaces of the third gate insulating layer region GI3may be aligned with the side surfaces of the semiconductor dummy part133and the side surfaces of the third buffer region123. The gate insulating layer GI may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer GI may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These materials may be used alone or in combination with each other. The second conductive layer140is located on the gate insulating layer GI. The second conductive layer140may include the first source/drain electrode141a, the second source/drain electrode141band the gate electrode141cof the first transistor TR1, the first source/drain electrode142a, the second source/drain electrode142band the gate electrode142cof the second transistor TR2, the second electrode143(or the upper electrode) of the capacitor Cst, and a scan wiring144corresponding to the scan line SL (seeFIG.3). The first source/drain electrode141a, the second source/drain electrode141band the gate electrode141cof the first transistor TR1may be located in the first transistor region TRR1, and the first source/drain electrode142a, the second source/drain electrode142band the gate electrode142cof the second transistor TR2may be located in the second transistor region TRR2, and the second electrode143of the capacitor Cst may be located in the capacitor region CPR. The first source/drain electrode141a, the second source/drain electrode141band the gate electrode141cof the first transistor TR1may overlap the first semiconductor opening OPS1and the first buffer opening OPB1, or at least a part of each of the first source/drain electrode141a, the second source/drain electrode141band the gate electrode141cof the first transistor TR1may be located in the first semiconductor opening OPS1and the first buffer opening OPB1. Furthermore, the first source/drain electrode141aand the second source/drain electrode141bof the first transistor TR1may cover an upper surface and/or the side surfaces of the semiconductor pattern131of the first transistor TR1while covering an upper surface and/or side surfaces of a part (e.g., the first power wiring111and the lower light blocking pattern114) of the first conductive layer110. For example, the first source/drain electrode141aof the first transistor TR1may directly contact at least a part of an upper surface and/or a side surface of the first source/drain region131aof the semiconductor pattern131of the first transistor TR1and cover at least a part of the upper surface and/or the side surface of the first source/drain region131aof the semiconductor pattern131of the first transistor TR1. The first source/drain electrode141aof the first transistor TR1may directly contact a side surface of the first buffer region121of the buffer layer120and cover the side surface of the first buffer region121. The first source/drain electrode141aof the first transistor TR1may directly contact a part of the first conductive layer110, that is, at least a part of the upper surface and/or a side surface of the first power wiring111and cover at least a part of the upper surface and/or the side surface of the first power wiring111. In addition, the first source/drain electrode141aof the first transistor TR1may contact an upper surface of the barrier layer102, although the present disclosure is not limited thereto. That is, the first source/drain electrode141aof the first transistor TR1may extend along a side surface of the semiconductor pattern131of the first transistor TR1and a side surface of the first buffer region121, directly contact the first source/drain region131aof the first transistor TR1and the first power wiring111without through contact holes, and electrically connect the first source/drain region131aof the first transistor TR1to the first power wiring111. The second source/drain electrode141bof the first transistor TR1may overlap at least a part of the semiconductor pattern131of the first transistor TR1, in particular, at least a part of the second source/drain region131bof the first transistor TR1and/or at least a part of the first conductive layer110, in particular, at least a part of the lower light blocking pattern114. For example, the second source/drain electrode141bof the first transistor TR1may directly contact at least a part of an upper surface and/or a side surface of the second source/drain region131bof the semiconductor pattern131of the first transistor TR1and cover at least a part of the upper surface and/or the side surface of the second source/drain region131bof the semiconductor pattern131of the first transistor TR1. The second source/drain electrode141bof the first transistor TR1may directly contact a side surface of the first buffer region121of the buffer layer120and cover the side surface of the first buffer region121. The second source/drain electrode141bof the first transistor TR1may directly contact a part of the first conductive layer110, that is, at least a part of an upper surface and/or a side surface of the lower light blocking pattern114and cover at least a part of the upper surface and/or the side surface of the lower light blocking pattern114. In addition, the second source/drain electrode141bof the first transistor TR1may contact the upper surface of the barrier layer102, although the present disclosure is not limited thereto. That is, the second source/drain electrode141bof the first transistor TR1may extend along a side surface of the semiconductor pattern131of the first transistor TR1and a side surface of the first buffer region121, directly contact the second source/drain region131bof the first transistor TR1and the lower light blocking pattern114without through contact holes, and electrically connect the second source/drain region131bof the first transistor TR1to the lower light blocking pattern114. The gate electrode141cof the first transistor TR1may protrude from an upper side of the second electrode143of the capacitor Cst. The gate electrode141cof the first transistor TR1may branch upward in the second direction DR2from the second electrode143of the capacitor Cst to overlap the channel region131cof the semiconductor pattern131of the first transistor TR1. The first source/drain electrode142a, the second source/drain electrode142band the gate electrode142cof the second transistor TR2may overlap the second semiconductor opening OPS2and the second buffer opening OPB2, or at least a part of each of the first source/drain electrode142a, the second source/drain electrode142band the gate electrode142cof the second transistor TR2may be located in the second semiconductor opening OPS2and the second buffer opening OPB2. Furthermore, the first source/drain electrode142aand the second source/drain electrode142bof the second transistor TR2may cover an upper surface and/or the side surfaces of the semiconductor pattern132of the second transistor TR2while covering an upper surface and/or side surfaces of a part (e.g., the data wiring112) of the first conductive layer110. The first source/drain electrode142aof the second transistor TR2may overlap at least a part of the semiconductor pattern132of the second transistor TR2, in particular, at least a part of the first source/drain region132aof the second transistor TR2and/or at least a part of the first conductive layer110, in particular, at least a part of the data wiring112. For example, the first source/drain electrode142aof the second transistor TR2may directly contact at least a part of an upper surface and/or a side surface of the first source/drain region132aof the semiconductor pattern132of the second transistor TR2and cover at least a part of the upper surface and/or the side surface of the first source/drain region132aof the semiconductor pattern132of the second transistor TR2. The first source/drain electrode142aof the second transistor TR2may directly contact a side surface of the second buffer region122of the buffer layer120and cover the side surface of the second buffer region122. The first source/drain electrode142aof the second transistor TR2may directly contact a part of the first conductive layer110, that is, at least a part of the upper surface and/or a side surface of the data wiring112and cover at least a part of the upper surface and/or the side surface of the data wiring112. In addition, the first source/drain electrode142aof the second transistor TR2may contact the upper surface of the barrier layer102, although the present disclosure is not limited thereto. That is, the first source/drain electrode142aof the second transistor TR2may extend along a side surface of the semiconductor pattern132of the second transistor TR2and a side surface of the second buffer region122, directly contact the first source/drain region132aof the second transistor TR2and the data wiring112without through contact holes, and electrically connect the first source/drain region132aof the second transistor TR2to the data wiring112. The second source/drain electrode142bof the second transistor TR2may directly contact at least a part of an upper surface and/or a side surface of the second source/drain region132bof the semiconductor pattern132of the second transistor TR2and cover at least a part of the upper surface and/or the side surface of the second source/drain region132bof the semiconductor pattern132of the second transistor TR2. The second source/drain electrode142bof the second transistor TR2may directly contact a side surface of the second buffer region122of the buffer layer120and cover the side surface of the second buffer region122. In addition, the second source/drain electrode142bof the second transistor TR2may contact the upper surface of the barrier layer102, although the present disclosure is not limited thereto. The gate electrode142cof the second transistor TR2may protrude from the scan wiring144. The gate electrode142cof the second transistor TR2may branch upward in the second direction DR2from the scan wiring144to overlap the channel region132cof the semiconductor pattern132of the second transistor TR2. The second electrode143of the capacitor Cst may be located on the first electrode113of the capacitor Cst to overlap at least a part of the first electrode113of the capacitor Cst. The shape of the second electrode143of the capacitor Cst may be generally similar to the shape of the first electrode113of the capacitor Cst. The second electrode143of the capacitor Cst may be smaller in area than the first electrode113of the capacitor Cst to expose a part of the first electrode113of the capacitor Cst. The second electrode143of the capacitor Cst may overlap the first electrode113of the capacitor Cst with the third buffer region123of the buffer layer120, the semiconductor dummy part133of the semiconductor layer130, and the third gate insulating layer region GI3of the gate insulating layer GI interposed between them, thereby forming the capacitor Cst. The third buffer region123of the buffer layer120, the semiconductor dummy part133of the semiconductor layer130and the third gate insulting layer region GI3of the gate insulating layer GI interposed between the first electrode113of the capacitor Cst and the second electrode143of the capacitor Cst may be a dielectric of the capacitor Cst. However, the third gate insulating layer region GI3of the gate insulating layer GI can be removed depending on the process. The second electrode143of the capacitor Cst may be located in the entire capacitor region CPR. The second electrode143of the capacitor Cst may be located in the entire capacitor region CPR and may partially extend to be connected to the gate electrode141cof the first transistor TR1and the second source/drain electrode142bof the second transistor TR2. For example, the second electrode143of the capacitor Cst may be located in the capacitor region CPR and may be physically and/or electrically connected to the gate electrode141cof the first transistor TR1located in the first transistor region TRR1and the second source/drain electrode142bof the second transistor TR2located in the second transistor region TRR2. The second electrode143of the capacitor Cst, the gate electrode141cof the first transistor TR1, and the second source/drain electrode142bof the second transistor TR2may be integrated into one second conductive layer pattern. The scan wiring144may be located on a lower side of the pixel PX (or a lower side of the circuit area CA) in plan view. The scan wiring144may extend in the first direction DR1. The scan wiring144may extend to another pixel PX neighboring the pixel PX in the first direction DR1. The scan wiring144may be located on a different layer from the first power wiring111and the data wiring112and may be located above the first power wiring111and the data wiring112. The scan wiring144extending in the first direction DR1may intersect the first power wiring111and the data wiring112extending in the second direction DR2. However, at an intersection of the scan wiring144and each of the first power wiring111and the data wiring112, one or more insulating layers may be located between the scan wiring144and each of the first power wiring111and the data wiring112to insulate the scan wiring144from each of the first power wiring111and the data wiring112. The scan wiring144may be located under the second electrode143of the capacitor Cst and spaced apart from the second electrode143of the capacitor Cst. The second conductive layer140may be made of a material with low resistivity. The second conductive layer140may include, but is not limited to, one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The passivation layer PVX is located on the second conductive layer140. The passivation layer PVX covers the second conductive layer140to protect the second conductive layer140. The passivation layer PVX may be formed not only on the second conductive layer140but also in the first semiconductor opening OPS1, the second semiconductor opening OPS2, the first buffer opening OPB1, and the second buffer opening OPB2. For example, the passivation layer PVX may cover not only upper and side surfaces of the second conductive layer140but also an upper surface and/or side surfaces of the gate insulating layer GI, an upper surface and/or the side surfaces of the semiconductor layer130, an upper surface and/or side surfaces of the buffer layer120, an upper surface and/or side surfaces of the first conductive layer110, and the upper surface of the barrier layer102. The passivation layer PVX may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide. According to some example embodiments, the passivation layer PVX may be formed in the display area DA and may not be formed in at least a part of the non-display area NDA. The via layer VIA is located on the passivation layer PVX. The via layer VIA may be located on the passivation layer PVX to completely cover an upper surface of the passivation layer PVX. The via layer VIA may also be located in the first semiconductor opening OPS1, the second semiconductor opening OPS2, the first buffer opening OPB1, and the second buffer opening OPB2. When the via layer VIA is made of an organic layer, its upper surface may be flat despite a step under the via layer VIA. The via layer VIA may include an inorganic insulating material or an organic insulating material such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenylenethers resin, polyphenylenesulfides resin or benzocyclobutene (BCB). The via layer VIA may further include a photosensitive material, but the present disclosure is not limited thereto. The anode ANO is located on the via layer VIA. The anode ANO may be located separately in each pixel. The anode ANO may be electrically connected to the second source/drain region141bof the first transistor TR1through a contact hole CNT that penetrates the via layer VIA and exposes a part of the second source/drain region141bof the first transistor TR1. The anode ANO may be located in the display area DA and may not be located in the non-display area NDA. The anode ANO may have, but is not limited to, a stacked structure in which a material layer having a high work function such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture of the same are stacked. The material layer having a high work function may be located on the reflective material layer to be close to a light emitting layer EL. The anode ANO may have, but is not limited to, a multilayer structure of ITO/Mg, ITO/MgF, ITO/Ag, or ITO/Ag/ITO. The pixel defining layer PDL may be located on the anode ANO. The pixel defining layer PDL may include an opening that partially exposes the anode ANO. The pixel defining layer PDL may be made of an organic insulating material or an inorganic insulating material. For example, the pixel defining layer PDL may include at least one of polyimide resin, acrylic resin, a silicone compound, and polyacrylic resin. The light emitting layer EL, a cathode CAT, and a thin-film encapsulation layer150may be further arranged on the anode ANO exposed by the pixel defining layer PDL. The light emitting layer EL may include an organic material layer. The organic material layer of the light emitting layer EL may include an organic light emitting layer and may further include a hole injection/transport layer and/or an electron injection/transport layer. The cathode CAT maybe located on the light emitting layer EL. The cathode CAT may be a common electrode located entirely without distinction between the pixels PX. The anode ANO, the light emitting layer EL and the cathode CAT may constitute the organic light emitting element OLED. The cathode CAT may include a material layer having a small work function, such as Li, Ca, LiF/Ca, LiF/AI, Al, Mg, Ag, Pt, Pd, Ni, Au Nd, Ir, Cr, BaF, Ba, or a compound or mixture of the same (e.g., a mixture of Ag and Mg). The cathode CAT may further include a transparent metal oxide layer located on the material layer having a small work function. The thin-film encapsulation layer150is located on the cathode CAT. The thin-film encapsulation layer150may include a first inorganic layer151, a first organic layer152, and a second inorganic layer153. According to some example embodiments, the first inorganic layer151and the second inorganic layer153may contact each other at an end of the thin-film encapsulation layer150. The first organic layer152may be sealed by the first inorganic layer151and the second inorganic layer153. Each of the first inorganic layer151and the second inorganic layer153may include silicon nitride, silicon oxide, or silicon oxynitride. The first organic layer152may include an organic insulating material. A method of fabricating the above-described display device1will now be described with reference toFIGS.8through18. FIG.8is a flowchart illustrating a method of fabricating a display device according to some example embodiments.FIGS.9through18are cross-sectional views illustrating operations in the method of fabricating a display device ofFIG.7 Referring toFIGS.8and9, a barrier layer102is formed on the entire surface of a base substrate101, and a patterned first conductive layer110is formed on the barrier layer102(operation S01). The patterned first conductive layer110may be formed by a mask process. For example, a material layer for a first conductive layer may be deposited on the entire surface of the barrier layer102and then patterned through a photolithography process to form the first conductive layer110as illustrated inFIG.9. Next, referring toFIGS.10through14, a buffer layer material120a, a semiconductor layer material130a, and a gate insulating layer material GIa are collectively etched (operation S02) to collectively pattern a buffer layer120and a semiconductor layer130and then a gate insulating layer GI (operation S03). The above processes (operations SO2and S03) may be performed using a halftone mask HFM, but the present disclosure is not limited thereto. The buffer layer material120a, the semiconductor layer material130a, and the gate insulating layer material GIa may be patterned into the buffer layer120, the semiconductor layer130, and the gate insulating layer GI, respectively. For example, the buffer layer material120a, the semiconductor layer material130aand the gate insulating layer material GIa are sequentially coated on the entire surface of the barrier layer102to cover the first conductive layer110, and a photoresist PRO is coated on the gate insulating layer material GIa and then exposed to light using the halftone mask HFM. The halftone mask HFM may be divided into a light blocking part BL, a first light transmitting part HT, and a second light transmitting part TR according to light transmittance (or transmissivity). The transmittance of the second light transmitting part TR may be greater than that of the first light transmitting part HT. The photoresist PRO may be divided into a first region R1, a second region R2, and a third region R3. The first region R1may correspond to the first light transmitting part HT of the halftone mask HFM, and the second region R2may correspond to the second light transmitting part TR of the halftone mask HFM. In addition, the third region R3may correspond to the light blocking part BL of the halftone mask HFM. The light blocking part BL may block light provided from the outside to prevent or reduce the light reaching the third region R3of the photoresist PRO. The first light transmitting part HT may transmit only a part of the light provided from the outside by controlling the transmittance of the light and allow only the part of the light to reach the first region R1of the photoresist PRO. The second light transmitting part TR may transmit most of the light provided from the outside and allow most of the light to reach the second region R2of the photoresist PRO. For example, in the case of a positive photoresist exposed to light, a sensitizer may be decomposed, and an acid may be formed. As a result, a region in which the sensitizer is decomposed has a characteristic of melting well in a developer. Here, of the photoresist of the substrate, any one of a part exposed to light and a part not exposed to light may be removed using a developer (e.g., a predetermined developer) according to chemical change characteristics of the exposed part and the unexposed part, thereby forming a photoresist pattern. However, when the halftone mask HFM is used, only a part of the photoresist in a part (e.g., the first region R1) corresponding to a part (e.g., the first light transmitting part HT) that transmits only a part of light provided from the outside may be removed, and the other part of the photoresist may remain without being removed. Therefore, the photoresist PRO of the third region R3may remain to a first height h1, and the photoresist PRO of the first region R1may remain to a second height h2. The first height h1may be greater than the second height h2. In addition, the photoresist of the second region R2may be completely removed to expose a part of an upper surface of the gate insulating layer material GIa in the second region R2. In the case of a negative photoresist, the photoresist PRO may remain to opposite heights in the third region R3and the first region R1. Next, the gate insulating layer material GIa, the semiconductor layer material130aand the buffer layer material120aare collectively etched in the second region R2from which the photoresist PRO has been completely removed. For example, the gate insulating layer material GIa, the semiconductor layer material130aand the buffer layer material120aare collectively etched in the second region R2from which the photoresist PRO has been completely removed to form the semiconductor layer130and the buffer layer120. In the process of etching the gate insulating layer material GIa, the semiconductor layer material130aand the buffer layer material120a, the etching of the semiconductor layer material130amay result in the formation of a semiconductor pattern131of a first transistor TR1, a semiconductor pattern132of a second transistor TR2, a semiconductor dummy part133, a first semiconductor opening OPS1, and a second semiconductor opening OPS2. In addition, the etching of the buffer layer material120ain the above process may result in the formation of a first buffer region121, a second buffer region122, a third buffer region123, a first buffer opening OPB1, and a second buffer opening OPB2. Next, after the gate insulating layer material GIa, the semiconductor layer material130a, and the buffer layer material120aare collectively etched, an ashing process is performed. Then, the gate insulating layer GI is patterned. For example, the ashing process may partially remove the photoresist PRO of the third region R3to leave an amount (e.g., a predetermined amount) of the photoresist PRO while completely removing the photoresist PRO of the first region R1. Accordingly, the gate insulating layer material GIa of the third region R3may not be exposed, but the gate insulating layer material GIa of the first region R1may be exposed. The exposed gate insulating layer material GIa of the first region R1may be removed by etching, thereby forming the gate insulating layer GI including a first gate insulating layer region GI1, a second gate insulating layer region GI2, and a third gate insulating layer region GI3. As described above, according to some example embodiments, the gate insulating layer GI, the semiconductor layer130, and the buffer layer120may be formed by one mask process. That is, because a separate mask process for forming each of the gate insulating layer GI, the semiconductor layer130, and the buffer layer120is not necessary, the number of mask processes can be reduced, thereby improving process efficiency. Next, referring toFIG.15, a patterned second conductive layer140is formed on the gate insulating layer GI (operation S04). The patterned second conductive layer140may be formed by a mask process. For example, a material layer for a second conductive layer is deposited on the entire surface of the gate insulating layer GI. In the deposition process, the material layer for the second conductive layer may also be deposited on an upper surface and/or side surfaces of the semiconductor layer130, side surfaces of the buffer layer120, and an upper surface and/or side surfaces of the first conductive layer110. Therefore, first and second source/drain electrodes141aand141bof the first transistor TR1and first and second source/drain electrodes142aand142bof the second transistor TR2may be physically and/or electrically connected to the semiconductor pattern131of the first transistor TR1and the semiconductor pattern132of the second transistor TR2, respectively. Furthermore, the first and second source/drain electrodes141aand141bof the first transistor TR1and the first and second source/drain electrodes142aand142bof the second transistor TR2may be physically and/or electrically connected to a first power wiring111, a lower light blocking pattern114, and a data wiring112, respectively. Next, a photoresist layer is coated on the material layer for the second conductive layer and exposed and developed to form a photoresist pattern. Then, the material layer for the second conductive layer is etched using the photoresist pattern as an etch mask. Next, the photoresist pattern is removed through a strip or ashing process to complete the patterned second conductive layer140as illustrated inFIG.15. Next, referring toFIG.16, a passivation layer PVX and a via layer VIA are formed on the second conductive layer140, and a contact hole CNT is formed to expose a part of the second source/drain electrode141bof the first transistor TR1(operation S05). For example, the passivation layer PVX is deposited on an upper surface and/or side surfaces of the gate insulating layer GI, the upper surface and/or the side surfaces of the semiconductor layer130, the side surfaces of the buffer layer120, the upper surface and/or the side surfaces of the first conductive layer110and an upper surface of the barrier layer102to cover the second conductive layer140. After the passivation layer PVX is deposited, a material layer for a via layer is coated to form the via layer VIA. Then, the via layer VIA and the passivation layer PVX are etched to form the contact hole CNT that penetrates the via layer VIA and the passivation layer PVX to expose a part of the second source/drain electrode141bof the first transistor TR1. Next, referring toFIG.17, an anode ANO is formed on the via layer VIA (operation S06). The anode ANO may be formed by a mask process. For example, a material layer for an anode is deposited on the entire surface of the via layer VIA. In the deposition process, the material layer for the anode may be deposited into the contact hole CNT. Therefore, the anode ANO may be connected to the second source/drain electrode141bof the first transistor TR1. Next, a photoresist layer is coated on the material layer for the anode and exposed and developed to form a photoresist pattern. Then, the material layer for the anode is etched using the photoresist pattern as an etch mask. Next, the photoresist pattern is removed through a strip or ashing process to complete the patterned anode ANO as illustrated inFIG.17. Next, referring toFIG.18, a patterned pixel defining layer PDL is formed on the via layer VIA to cover the anode ANO (operation S07). For example, the pixel defining layer PDL may include, for example, an organic material including a photosensitive material. In this case, the patterned pixel defining layer PDL may be formed by coating an organic material layer for a pixel defining layer and exposing and developing the organic material layer for the pixel defining layer. The pixel defining layer PDL may be formed along a boundary of a pixel PX and may partially overlap the anode ANO. The pixel defining layer PDL may be formed to overlap the contact hole CNT. When the anode ANO only partially fills an inner space of the contact hole CNT instead of completely filling the inner space, the pixel defining layer PDL may completely fill the inner space of the contact hole CNT. Hereinafter, other embodiments will be described. In the following embodiments, a description of the same elements as those described above will be omitted or given briefly, and differences will be mainly described. FIG.19is a layout view of a buffer layer120_1according to some example embodiments.FIG.20is a layout view of a semiconductor layer130_1according to some example embodiments.FIG.21is a layout view of one pixel PX of a display device according to some example embodiments.FIG.22is a cross-sectional view taken along the line XXII-XXII′ ofFIG.21.FIG.23is a cross-sectional view taken along the line XXIII-XXIII′ ofFIG.21. Referring toFIGS.19through23, the current embodiment is different from the embodiment ofFIG.4in that a third buffer region123_1of the buffer layer120_1, a semiconductor dummy part133_1of the semiconductor layer130_1and a third gate insulating layer region GI3_1of a gate insulating layer GI_1arranged in a display panel10_1are arranged in only a portion of a circuit area CA. For example, the buffer layer120_1includes a first buffer region121, a second buffer region122and the third buffer region123_1, the semiconductor layer130_1includes a semiconductor pattern131of a first transistor TR1, a semiconductor pattern132of a second transistor TR2and the semiconductor dummy part133_1, and the gate insulating layer GI_1includes a first gate insulting layer region GI1, a second gate insulating layer region GI2and the third gate insulating layer region GI3_1. Here, the third buffer region123_1, the semiconductor dummy part133_1, and the third gate insulating layer region GI3_1may be arranged only in a capacitor region CPR. That is, the third buffer region123_1, the semiconductor dummy part133_1, and the third gate insulating layer region GI3_1may not be arranged in a region excluding a first transistor region TRR1, a second transistor region TRR2, and the capacitor region CPR. In this case, a scan wiring144_1may be located only in one pixel PX without extending to another pixel PX neighboring the pixel PX in the first direction DR1. The scan wiring144_1may not be directly connected to the scan wiring144_1of the neighboring pixel PX but may be electrically connected to the scan wiring144_1of the neighboring pixel PX by a connection wiring CTE and contact holes CNT_S1and CNT_S2located on a different layer from the scan wiring144_1, a first power wiring111and a data wiring112. The connection wiring CTE may be formed on a via layer VIA and electrically connected to the scan wiring144_1of the pixel PX through the contact holes CNT_S1and CNT_S2that penetrate the via layer VIA and a passivation layer PVX to expose the scan wiring144_1. Here, one connection wiring CTE may be electrically connected not only to the scan wiring144_1of the pixel PX but also to the scan wiring144_1of another pixel PX neighboring the pixel PX in the first direction DR1. Accordingly, even if the scan wiring144_1is arranged only in the pixel PX, it may be electrically connected to the scan wiring144_1of the neighboring pixel PX by the connection wiring CTE. The connection wiring CTE may intersect the first power wiring111and the data wiring112. The passivation layer PVX and the via layer VIA are arranged between the connection wiring CTE and each of the first power wiring111and the data wiring112to insulate the connection wiring CTE from each of the first power wiring111and the data wiring112. That is, even if the third buffer region123_1, the semiconductor dummy part133_1and the third gate insulating layer region GI3_1are arranged only in the capacitor region CPR, the scan wiring144_1of the pixel PX may be electrically connected to the scan wiring144_1of a neighboring pixel PX by the connection wiring CTE without a short (or a short-circuit) with the first power wiring111and the data wiring112. The connection wiring CTE may be formed together with an anode ANO by using the same mask. The contact holes CNT_S1and CNT_S2electrically connecting the connection wiring CTE and the scan wiring144_1may be formed together with a contact hole CNT electrically connecting the anode ANO and a second source/drain electrode141bof the first transistor TR1by using the same mask. Therefore, a separate mask for forming the connection wiring CTE or the contact holes CNT_S1and CNT_S2is unnecessary. In this case, because a separate mask process for forming each of the gate insulating layer GI_1, the semiconductor layer130_1and the buffer layer120_1is also not necessary, the number of mask processes can be reduced, thereby improving process efficiency. According to some example embodiments, the first power wiring111and the data wiring112extend to a neighboring pixel PX, the scan wiring144_1is located only in the pixel PX without extending to the neighboring pixel PX, and the scan wiring144_1of the pixel PX is electrically connected to the scan wiring144_1of the neighboring pixel PX by the connection wiring CTE as described above. However, the present disclosure is not limited thereto, and the scan wiring144_1may also extend to another pixel PX neighboring the pixel PX in the first direction DR1, and the first power wiring111and the data wiring112may also be located only in the pixel PX and electrically connected to the first power wiring111and the data wiring112of the neighboring pixel PX by the connection wiring CTE. FIG.24is a cross-sectional view of a display panel10_2according to some example embodiments. Referring toFIG.24, the current embodiment is different from the embodiment ofFIG.7in that a part of an upper surface of a barrier layer102_2arranged in the display panel10_2is etched. For example, in an etching process for patterning a buffer layer120and a semiconductor layer130, a buffer layer material120a(seeFIG.12) may be etched to pattern the buffer layer120, and then the exposed barrier layer102_2may be further etched. In this case, not only side surfaces of the buffer layer120and side surfaces of the semiconductor layer130but also side surfaces of some regions of the etched barrier layer102_2may be aligned. In addition, a thickness of at least a part of the barrier layer102_2in a region overlapping a first semiconductor opening OPS_1, a second semiconductor opening OPS_2, a first buffer opening OPB_1or a second buffer opening OPB_2may be smaller than a thickness of the other part of the barrier layer102_2. In this case, because a separate mask process for forming each of a gate insulating layer GI, the semiconductor layer130and the buffer layer120is also not necessary, the number of mask processes can be reduced, thereby improving process efficiency. FIG.25is a cross-sectional view of a display panel10_3according to some example embodiments. Referring toFIG.25, the current embodiment is different from the embodiment ofFIG.7in that a buffer layer120_3arranged in the display panel10_3does not expose a barrier layer102located under the buffer layer120_3. For example, in an etching process for patterning the buffer layer120_3, a buffer layer material120a(seeFIG.12) may not be completely removed but may remain to a small thickness. In this case, a first buffer region121, a second buffer region122and a third buffer region123of the buffer layer120_3may be connected. However, a thickness of the buffer layer120_3arranged between the first buffer region121, the second buffer region122and the third buffer region123may be smaller than a thickness of each of the first buffer region121, the second buffer region122and the third buffer region123. In this case, an upper surface and/or side surfaces of a first conductive layer110may also be partially exposed, and the first conductive layer110may also be electrically connected to a semiconductor pattern131of a first transistor TR1and a semiconductor pattern132of a second transistor TR2by a second conductive layer140. In this case, because a separate mask process for forming each of a gate insulating layer GI, a semiconductor layer130and the buffer layer120_3is also not necessary, the number of mask processes can be reduced, thereby improving process efficiency. While the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications can be made without departing from the scope of the present disclosure and without changing essential features. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation. | 80,652 |
11942489 | MODE FOR CARRYING OUT THE INVENTION Image reading devices according to embodiments of the present invention will be described hereinafter with reference to the drawings. The following embodiments are merely examples, and various changes may be made within the scope of the present invention. In the figures, coordinate axes of an XYZ orthogonal coordinate system are shown to facilitate understanding of the description. The X axis is a coordinate axis parallel to a main scanning direction of an image reading device. The Y axis is a coordinate axis parallel to a sub-scanning direction of the image reading device. The Z axis is a coordinate axis orthogonal to the X axis and the Y axis. First Embodiment Configuration of Image Reading Device FIG.1is a perspective view schematically showing a main configuration of an image reading device100according to a first embodiment.FIG.2is a cross-sectional view of the image reading device100shown inFIG.1taken along line A2-A2.FIG.3is a cross-sectional view of the image reading device100shown inFIG.1taken along line A3-A3. As shown inFIGS.1through3, the image reading device100includes an imaging optical unit1, an illumination optical unit2, and a top panel glass7as a document placing table. When illumination light25is irradiated from the illumination optical unit2to a document6as an imaging object placed on the top panel glass7, the illumination light25is reflected on the document6to serve as reflected light. The reflected light is received by the imaging optical unit1so that image information of the document6is thereby read. In the first embodiment, to allow the imaging optical unit1to acquire two-dimensional image information of the document6, the document6is conveyed by a conveyor (not shown) along the top panel glass7in a sub-scanning direction (i.e., Y-axis direction) orthogonal to a main scanning direction (i.e., X-axis direction). Accordingly, the entire document6is allowed to be scanned. The scanning of the entire document6may be performed by moving the imaging optical unit1in the Y-axis direction with the document6being stationary. The document6is an example of an imaging object captured by the imaging optical unit1. The document6is, for example, a printed material on which characters, images, or the like are printed. The document6is placed on a predetermined reference surface S. The reference surface S is a surface on which the document6is placed, that is, the surface on the top panel glass7. The top panel glass7is located between the document6and the imaging optical unit1. The top panel glass7has a thickness of, for example, 1.0 mm. The configuration having the reference surface S on which the document6is placed is not limited to the top panel glass7. The imaging optical unit1includes a plurality of light-receiving pixels10, a first light-shielding member11including a plurality of first openings31, a second light-shielding member12including a plurality of second openings32, a third light-shielding member13including a plurality of third openings33, and a plurality of condenser lenses14. FIG.4is a plan view showing a part of the imaging sensor unit3including the plurality of light-receiving pixels10. As shown inFIGS.1and4, the plurality of light-receiving pixels10included in an imaging sensor chip8. The imaging sensor chip8is mounted on an imaging sensor board9. The imaging sensor board9is a mounting board of a non-translucent member. The plurality of light-receiving pixels10are arranged in the X-axis direction that is a predetermined arrangement direction. The plurality of light-receiving pixels10include a first line8aof light-receiving pixels10arranged in the X-axis direction, and a second line8bof light-receiving pixels10arranged in the X-axis direction. The light-receiving pixels10receive reflected light reflected on the document6. The size of a light-receiving region of one light-receiving pixel10is, for example, 63 μm×63 μm. A distance p in the X-axis direction between center positions of light-receiving pixels10adjacent to each other in the X-axis direction is, for example, 252 μm. A distance q in the Y-axis direction between the center positions of the light-receiving pixels10is, for example, 252 μm. InFIG.4, the plurality of light-receiving pixels10are arranged in a staggered pattern. Specifically, the second line8bof light-receiving pixels10are shifted in the X-axis direction by a distance p/2 of ½ of the distance p, from the adjacent first line8aof light-receiving pixels10. Accordingly, each of the light-receiving pixels10in the second line8bis located at an intermediate position in the X-axis direction between the adjacent light-receiving pixels10in the first line8aof light-receiving pixels10. As shown inFIGS.1through3, the first light-shielding member11is disposed between the plurality of light-receiving pixels10and the reference surface S. The first light-shielding member11includes the plurality of first openings31through which reflected light reflected on the document6passes. A portion of the first light-shielding member11except the first openings31is a first light-shielding portion41that blocks reflected light. The second light-shielding member12is disposed between the plurality of first openings31and the reference surface S. The second light-shielding member12includes the plurality of second openings32through which reflected light reflected on the document6passes. A portion of the second light-shielding member12except the second openings32is a second light-shielding portion42that blocks reflected light. A first light-transmissive member51is disposed between the first light-shielding member11and the second light-shielding member12. The first light-shielding portion41of the first light-shielding member11and the second light-shielding portion42of the second light-shielding member12are thin light-shielding layers formed of chromium oxide films deposited on the first light-transmissive member51. The first light-shielding member11is formed on a surface51a(shown inFIG.2) of the first light-transmissive member51facing the light-receiving pixels10, and the second light-shielding member12is formed on a surface51b(shown inFIG.2) of the first light-transmissive member51facing the reference surface S. The first and second openings31and32are formed by etching using a deposited chromium oxide film as a mask pattern. Each of the first openings31has, for example, a square shape of 48 μm×48 μm, and each of the second openings32has, for example, a square shape of 76 μm×76 μm. The plurality of first openings31are arranged to correspond to the plurality of light-receiving pixels10respectively. In the first embodiment, when seen in the Z-axis direction, the plurality of first openings31overlap the plurality of light-receiving pixels10respectively. The plurality of second openings32are arranged to correspond to the plurality of light-receiving pixels10respectively. In the first embodiment, when seen in the Z-axis direction, the plurality of second openings32overlap the plurality of light-receiving pixels10respectively. The plurality of first openings31are arranged in two lines. The plurality of second openings32are arranged in two lines. The first openings31in each line are arranged in the X-axis direction. The second openings32in each line are arranged in the X-axis direction. The plurality of first openings31are arranged in a staggered pattern. The second openings32are arranged in a staggered pattern. The first light-transmissive member51is a member that allows light to pass therethrough. The first light-transmissive member51is, for example, a transparent glass board. The first light-transmissive member51does not need to be completely transparent and may be translucent. The first light-transmissive member51has a refractive index n of, for example, 1.52. In the first embodiment, the first light-transmissive member51is constituted by one glass board. The first light-transmissive member51has a thickness t1(shown inFIG.3) of, for example, 210 μm. The first light-transmissive member51is disposed at a distance t0(shown inFIG.3) from the light-receiving pixels10in the Z-axis direction. The distance t0between the light-receiving pixels10and the first light-transmissive member51is, for example, 250 μm. A part or a whole of a gap between the first openings31and the second openings32may be space where no light-transmissive member is present. In a case where wire bonding is employed as a method for electrically connecting the imaging sensor chip8and the imaging sensor board9to each other, a wire might jut from the surface of the imaging sensor chip8at +Z-axis side in the +Z-axis direction by about 100 μm to 200 μm. In the first embodiment, since the distance t0is 250 μm, which is longer than the wire, the wire jutting from the imaging sensor chip8does not interfere with the first light-transmissive member51. In the first embodiment, a spacer member (not shown) having a thickness of 250 μm is disposed between the light-receiving pixels10and the first light-transmissive member51to thereby accurately obtain the distance t0of 250 μm. The plurality of condenser lenses14are disposed between the plurality of second openings32and the reference surface S. The optical axis of each of the condenser lenses14is denoted by reference numeral40. The condenser lenses14are disposed at a distance from the plurality of second openings32in an optical-axis direction (i.e., the Z-axis direction). The condenser lenses14have a function of concentrating reflected light reflected on the document6. The condenser lenses14are, for example, convex lenses. The plurality of condenser lenses14are arranged to correspond to the plurality of light-receiving pixels10respectively. In the first embodiment, when seen in the Z-axis direction, the plurality of condenser lenses14overlap the plurality of light-receiving pixels10respectively. The plurality of condenser lenses14are arranged in two lines. The condenser lenses14in each line are arranged in the X-axis direction. The plurality of condenser lenses14are arranged in a staggered pattern. The condenser lenses14arranged in the staggered pattern constitute a condenser lens array60. In the first embodiment, the diameter of each of the condenser lenses14is set in the range from several micrometers to several millimeters. A radius of curvature of a surface of each condenser lens14is, for example, 0.35 mm. The condenser lens array60is a microlens array including the plurality of tiny condenser lenses14. The plurality of condenser lenses14overlap the plurality of first openings31respectively, and also overlap the plurality of second openings32respectively. The third light-shielding member13is disposed between the second light-shielding member12and the plurality of condenser lenses14. The third light-shielding member13includes the plurality of third openings33through which reflected light reflected on the document6passes. A portion of the third light-shielding member13except the third openings33is a third light-shielding portion43that blocks reflected light. A second light-transmissive member52is disposed between the second openings32and the third openings33. The third light-shielding portion43(shown inFIG.3) of the third light-shielding member13is a thin light-shielding layer formed of a chromium oxide film deposited on the second light-transmissive member52. The third light-shielding member13is formed on a surface52b(shown inFIG.2) of the second light-transmissive member52facing the reference surface S. The third openings33are formed by etching using a deposited chromium oxide film as a mask pattern. InFIG.1, each of the third openings33is circular. The opening area of each of the third openings33is larger than that of each of the first and second openings31and32. That is, a diameter Φ of each of the third openings33is larger than each side of the first and second openings31and32. For example, the diameter Φ is 170 μm. The plurality of third openings33are arranged to correspond to the plurality of light-receiving pixels10respectively. In the first embodiment, when seen in the Z-axis direction, the plurality of third openings33overlap the plurality of light-receiving pixels10respectively. The plurality of third openings33are arranged in two lines. The third openings33in each line are arranged in the X-axis direction. The plurality of third openings33are arranged in a staggered pattern. The plurality of third openings33overlap the plurality of first openings31respectively, and also the plurality of second openings32respectively. In addition, the plurality of third openings33overlap the plurality of condenser lenses14respectively. The second light-transmissive member52is a member that allows light to pass therethrough. The second light-transmissive member52is, for example, a transparent glass board. The second light-transmissive member52does not need to be completely transparent and may be translucent. The second light-transmissive member52has a refractive index n of, for example, 1.52. As shown inFIG.3, the second light-transmissive member52has a thickness t2larger than the thickness t1of the first light-transmissive member51. The thickness t2of the second light-transmissive member52is, for example, 700 μm. A part or a whole of a gap between the second openings32and the third openings33may be space where no light-transmissive member is present. As shown inFIG.2, the second light-transmissive member52is fixed to the first light-transmissive member51by bonding with, for example, an adhesive such that center positions93of the third openings33overlap center positions91of the first openings31and center positions92of the second openings32. To increase accuracy in positioning in adhering the second light-transmissive member52to the first light-transmissive member51, the surface52aof the second light-transmissive member52and the surface51bof the first light-transmissive member51may include alignment marks for positioning. FIG.5is a diagram schematically showing a configuration of the illumination optical unit2illustrated inFIG.1and illumination light irradiated from the illumination optical unit2. As shown inFIGS.2and5, the illumination optical unit2includes a light source20and a light guide21. The light source20is disposed at an end face21aof the light guide21. The light source20emits light20atoward the inside of the light guide21. The light source20is, for example, a semiconductor light source. The semiconductor light source is, for example, a light emitting diode (LED). As shown inFIG.5, the light guide21causes light20aemitted from the light source20to travel toward the document6. The light guide21is, for example, a cylindrical member of a light-transmissive resin material. Light20aemitted from the light source20propagates while repeating total internal reflection in the light guide21. A scattering region22is formed on a part of the inner surface of the light guide21. Light20ais scattered on the scattering region22to be scattered light. Part of the scattered light serves as illumination light25irradiating the document6. As shown inFIG.2, illumination light25irradiated to the document6is reflected on the document6and becomes reflected light. The reflected light sequentially passes through the condenser lenses14, the third openings33, the second light-transmissive member52, the second openings32, the first light-transmissive member51, and the first openings31in this order. Condition for Acquiring Image not Affected by Stray Light A condition for acquiring an image not affected by stray light in the image reading device100will now be described.FIG.6is a diagram showing a part of the configuration illustrated inFIG.3, and reflected light passing through the second openings32and the first openings31. With reference toFIG.6, a condition for acquiring an image not affected by stray light traveling in the X-axis direction will be described. InFIG.6, the plurality of light-receiving pixels10arranged in the X-axis direction are also denoted by10a,10b, and10c. Similarly, the plurality of first openings31are also denoted by31a,31b, and31c, and the plurality of second openings32are also denoted by32a,32b, and32c. In the first and second openings31and32overlapping the light-receiving pixels10, lines connecting the centers of the second openings32, the centers of the first openings31, and the light-receiving pixels10will also be referred to as optical axes40a,40b, and40c. InFIG.6, reflected light passing through the second openings32and the first openings31are represented as light beams L1through L3. As shown inFIG.6, the light beam L1enters the light-receiving pixel10aafter passing through the second opening32aand the first opening31a. In other words, the light beam L1entering the light-receiving pixel10ais a light beam that has passed through the second opening32aand the first opening31alocated on the same optical axis40aas that of the light-receiving pixel10a. The light beam L2is a light beam passing through the second opening32band the first opening31blocated on the optical axis40bdifferent from the optical axis40a. The light beam L3is a light beam passing through the first openings31clocated on the optical axis40cdifferent from the optical axis40a. The light beam L2and the light beam L3do not reach the light-receiving pixel10a. In this case, the imaging optical unit1can obtain an image not affected by stray light traveling in the X-axis direction. In the first embodiment, the light beam that has passed through the second openings32and the first openings31located on the optical axis of the light-receiving pixels10enter the light-receiving pixels10on this optical axis. That is, the light-receiving pixels10and the first openings31have an optically one-to-one relationship, and the light-receiving pixels10and the second openings32have an optically one-to-one relationship. FIGS.7A and7Bare diagrams for describing a condition that reflected light that has passed through the second openings32and the first openings31corresponding to light-receiving pixels10enter the light-receiving pixels10, in the image reading device100. As shown inFIGS.7A and7B, the first light-transmissive member51having the refractive index n is disposed at the distance t0from the light-receiving pixels10. An air layer is present between the light-receiving pixels10and the first light-transmissive member51. If the following conditions 1 and 2 are satisfied, reflected light that has passed through the second openings32and the first openings31corresponding to the light-receiving pixels10enter these light-receiving pixels10. (Condition 1) There are no light beams passing through the second openings32and the first openings31having different optical axes. (Condition 2) Light beams that have passed through the second openings32and the first openings31having the same optical axis do not reach any portion except the light-receiving pixels10on this optical axis. Conditions 1 and 2 will be described with reference toFIGS.7A and7B. As shown inFIG.7A, Condition 1 is established when the light beam satisfies a total internal reflection condition. Specifically, a light-receiving pixel10vof the plurality of light-receiving pixels10and light-receiving pixels10uand10wadjacent to the light-receiving pixel10vwill be described. If an incident angle θ1of a light beam L4passing through a point P3in a first opening31voverlapping the light-receiving pixel10vand a point P4in a second opening32woverlapping the light-receiving opening32wis larger than a critical angle θc, the light beam entering the first opening31vsatisfies the total internal reflection condition. Here, the incident angle θ1of the light beam L4is an angle formed by a normal N0to the first light-shielding member11and the light beam L4. The point P3is an end portion of the first opening31vclosest to the first opening31w. The point P4is an end portion of the second opening32wclosest to the second opening32v. A light beam L5shown inFIG.7Ais a light beam passing through the second opening32wand enters a first opening31u. Since the light beam L4is totally reflected in the first opening31v, the light beam L5having an incident angle larger than that of the light beam L4is totally reflected in the first opening31u. Thus, the light beam L5does not pass through the first opening31u. Here, a half opening width that is ½ of the opening width of the first opening31in the X-axis direction is defined as X1, and a half opening width that is ½ of the opening width of the second opening32in the X-axis direction is defined as X2. A distance D1, in the X-axis direction, between an end of the second opening32win the −X-axis direction and an end of the first opening31vin the +X-axis direction is obtained by Equation (1): D1=p−X1−X2(1) As is obvious fromFIG.7A, with respect to the incident angle θ1of the light beam L4, Equation (2) is established: tan θ1=D1/t1=(p−X1−X2)/t1(2) Here, in order for the light beam L4entering at the incident angle θ1to satisfy the total internal reflection condition, it is necessary to satisfy Equation (3): n·sin θ1>1 (3) From Equation (2) and Equation (3), with respect to the thickness t1of the first light-transmissive member51satisfying Condition 1, Equation (4) below is derived: t1<√{square root over (n2−1)}·(p−X1−X2) (4) Specifically, if the thickness t1of the first light-transmissive member51is smaller than the value at the right side of Equation (4), the light beam L4satisfies the total internal reflection condition. In this case, Condition 1 is established. Next, Condition 2 will be described with reference toFIG.7B. One light-receiving pixel10bof the plurality of light-receiving pixels10and light-receiving pixels10aand10cadjacent to both sides of the light-receiving pixel10bin the X-axis direction will be described as an example. Condition 2 is established if a light beam L6passing through a point P5in the second opening32boverlapping the light-receiving pixel10band a point P6in the first opening31boverlapping the light-receiving pixel10breaches a region between the light-receiving pixel10aand the light-receiving pixel10cand does not enter any of the light-receiving pixel10aand the light-receiving pixel10c. The region between the light-receiving pixel10aand the light-receiving pixel10cis a region sandwiched between the right end of the light-receiving pixel10aand the left end of the light-receiving pixel10cshown inFIG.7B. The light beam L6shown inFIG.7Bis a light beam passing through the second opening32band the first opening31boverlapping the second opening32b. InFIG.7B, the light beam L6passes through an end portion of the second opening32bclosest to the second opening32c, and then passes through an end portion of the first opening31bclosest to the first opening31a. The light beam L6that has passed through the first opening31breaches a point Q0. Here, the point Q0represents a point which is located between the light-receiving pixel10aand the light-receiving pixel10cand which the light beam L6reaches. InFIG.7B, the point Q0is a point farthest from the light-receiving pixel10bin the −X-axis direction, that is, a point closest to the light-receiving pixel10a. In a case where the light beam L6reaches a portion of the light-receiving pixel10acloser to the light-receiving pixel10bthan the end portion of the light-receiving pixel10aclosest to the light-receiving pixel10b, the light beam that has passed through the second opening32band the first opening31bdoes not reach light-receiving pixels (e.g., the light-receiving pixels10aand10c)) except for light-receiving pixel10b. Here, supposing an emission angle of the light beam L6is α1, and an incident angle of the light beam L6is α2, the incident angle α2is obtained by Equation (5): tan α2=(X1+X2)/t1(5) According to the Snell's law, a relationship between the emission angle α1and the incident angle α2is expressed by Equation (6): n·sin α2=sin α1(6) A distance D2from the optical axis40bto the point Q0is obtained by Equation (7): D2=X1+t0·tan α1(7) Here, supposing a half width of the light-receiving pixel10bthat is ½ of the width of the light-receiving pixel10bin the X-axis direction is X0, a condition that the point Q0is located closer to the light-receiving pixel10bthan an end portion of the light-receiving pixel10ain the +X-axis direction is expressed by Equation (8): p−X0>X1+t0·tan α1(8) From Equation (5) through Equation (8), with respect to the thickness t1of the first light-transmissive member51satisfying Condition 2, Equation (9) below is derived: t1>(X1+X2)·n2-1+n2·t02(p-X1-X0)2(9) That is, if the thickness t1of the first light-transmissive member51is larger than a value at the right side of Equation (9), the above described Condition 2 is established. In an example of the first embodiment, X0=31.5 μm, X1=24 μm, X2=38 μm, n=1.52, t0=250 μm, and p=252 μm. If these values are substituted into Equation (4) and Equation (9), the right side of Equation (4) is 217.5 μm, and the right side of Equation (9) is 139 μm. In this example, since the thickness t1of the first light-transmissive member51is 210 μm, Equation (4) that defines the upper limit of the thickness t1and Equation (9) that defines the lower limit of the thickness t1are satisfied. Accordingly, reflected light that has passed through the second openings32and the first openings31corresponding to the light-receiving pixels10enters the light-receiving pixels10, and thus, an image not affected by stray light is acquired. Next, other advantages obtained by the presence of the first and second light-shielding members11and12in the image reading device100will be described. As shown inFIG.7A, the light beam L4that has passed through the second opening32wis totally reflected in the first opening31v, and thus, does not reach the light-receiving pixel10v. The light beam L5is also totally reflected in the first opening31u, and thus, does not reach the light-receiving pixel10u. In addition, as shown inFIG.7B, a light beam L7that has passed through the second opening32cis blocked by the first light-shielding portion41of the first light-shielding member11. Even if part of the light beam L7is reflected on the first light-shielding member11and travels in the +Z-axis direction as a light beam L20, the light beam L20is blocked by the second light-shielding portion42of the second light-shielding member12. Here, as an image reading device, a configuration in which a light-absorbing member having a through hole elongated in the Z-axis direction is disposed between a light-receiving pixel and a reference surface instead of the first and second light-shielding members11and12and the first light-transmissive member51shown inFIGS.7A and7Bis considered for comparison. In this configuration, a light beam traveling in parallel with the axis of the through hole reaches the light-receiving pixel after passing through the through hole. The inner surface of the through hole functions as a light-shielding wall that blocks a light beam having a tilt angle with respect to the axis. However, part of the light beam that has entered the through hole might be scattered at the light-shielding wall. In this case, if the scattered light beam enters a light-receiving pixel not corresponding to the through hole, image information acquired from the light-receiving pixel is affected by stray light. On the other hand, in the first embodiment, since the light beam that has passed through the second openings32is totally reflected in the first openings31or blocked by the first and second light-shielding members11and12as shown inFIGS.7A and7B, an image not affected by stray light can be acquired as compared to a configuration in which the image reading device includes a light-absorbing member. Then, description will be given on a condition for preventing a light beam that has passed through the second openings32and the first openings31at locations overlapping the light-receiving pixels10in one of two lines of the light-receiving pixels10from entering the light-receiving pixels10in the other line in the image reading device100.FIG.8is a cross-sectional view of the image reading device100shown inFIG.1taken along line A8-A8. More specifically,FIG.8is a cross-sectional view of a plane including the point P1and the point P2shown inFIG.1. In the following description, the light-receiving pixels10arranged in the first line8a(shown inFIG.4) will also be referred to as a light-receiving pixel10a, and the light-receiving pixels10arranged in the second line8b(shown inFIG.4) will also be referred to as a light-receiving pixel10e. The first and second openings31and32overlapping the light-receiving pixel10awill also be denoted by31aand32a, and the first and second openings31and32overlapping the light-receiving pixel10ewill also be denoted by31eand32e. The condenser lens14overlapping the second opening32awill also be denoted by14a, and the condenser lens14overlapping the second opening32ewill also be denoted by14e. The optical axis of the condenser lens14ais denoted by40a, and the optical axis of the condenser lens14eis denoted by40e. Next, a condition for preventing a light beam that has passed through the second opening32eand the first opening31efrom entering the light-receiving pixel10awill be described. In this description, as shown inFIG.8, a back light beam L8that is an imaginary light beam traveling from the light-receiving pixel10atoward the first opening31eis used. The back light beam L8is a light beam passing from a point R1to a point R2and reaching a point R3. The point R1is an end of the light-receiving pixel10aclosest to the light-receiving pixel10e. The point R2is an end of the first opening31eclosest to the first opening31a. The point R3is a point located at an outer side of an end portion of the second opening32efarthest from the second opening32a. If the back light beam L8reaches the first light-shielding portion41or the second light-shielding portion42, a light beam that has passed through the second opening32eand the first opening31edoes not enter the light-receiving pixel10a. InFIG.8, a case where the back light beam L8reaches the second light-shielding portion42will be described as an example. InFIG.8, a distance between the point R3and the optical axis40eis denoted by D3, and a length of ½ of a diagonal length of the square second opening32eis denoted by X20. If the distance D3is larger than the length X20, the back light beam L8reaches the second light-shielding portion42. Accordingly, the light beam that has passed through the second opening32eand the first opening31edoes not enter the light-receiving pixel10a. Even in a case where the distance D3is smaller than the length X20and the back light beam L8passes through the second opening32e, if the distance q shown inFIG.4is large, the back light beam L8reaches the third light-shielding portion43of the third light-shielding member13. Thus, even in the case where the distance D3is smaller than the length X20, since the distance q is large and the image reading device100includes the third light-shielding member13, the light beam that has passed through the second opening32eand the first opening31edoes not enter the light-receiving pixel10a. Image Restoration A method for restoring an image of the document6by the imaging optical unit1based on image information acquired from the light-receiving pixels10will now be described. In the first embodiment, since the plurality of light-receiving pixels10are arranged in a staggered pattern as shown inFIG.4, the center positions of the light-receiving pixels10in the first line8aand the center positions of the light-receiving pixels10in the second line8bare shifted from each other in the Y-axis direction by a distance q. Thus, it is necessary to restore the image to an image without a positional shift even in a case where the document6is scanned in the Y-axis direction. Specifically, it is sufficient to perform a process of shifting image information by the number of pixels corresponding to the distance q in the Y-axis direction after an image processing circuit (not shown) acquires image information from the light-receiving pixels10in the first line8aand image information from the light-receiving pixels10in the second line8b. InFIG.4, the light-receiving pixels10in the second line8bare shifted from the light-receiving pixels10in the first line8ain the X-axis direction by a distance p/2 that is ½ of the distance p. The image processing circuit acquires outputs from the light-receiving pixels10at time intervals in which the document6is conveyed in the Y-axis direction by a distance p/2. In the first embodiment, a resolution in the X-axis direction is equal to a resolution in the Y-axis direction. The distance q indicating the amount of positional shift of image information is preferably an integral multiple of the distance p/2, but the present invention is not limited to this example. The image processing circuit may estimate a luminance value at a sub-pixel position by using a pixel interpolation process to synthesize image information using the estimated luminance value. The image processing circuit may synthesize the acquired image information by shifting a timing when the light-receiving pixels10in the first line8aacquire image information and a timing when the light-receiving pixels10in the second line8bacquire image information are shifted from each other. Increase in Depth of Field A configuration in which the depth of field of the image reading device100is increased will now be described in comparison to first and second comparative examples. The following description is directed to an example of a configuration in which the depth of field is increased in order to acquire an image with a resolution of 200 dpi (i.e., distance p=252 μm). FIG.9is a diagram schematically showing reflected light entering the light-receiving pixel10bin an image reading device100aaccording to a first comparative example. As shown inFIG.9, the image reading device100aof the first comparative example is different from the image reading device100according to the first embodiment (shown inFIG.15described later) in including none of the third light-shielding member13, the condenser lenses14, and the second light-transmissive member52in the first embodiment. Light beams L11through L14are light beams illustrated as representatives of light beams entering the light-receiving pixel10b. In the following description, a group of a plurality of light beams will be referred to as a light flux. The light beam L11is a light beam entering one end portion of the light-receiving pixel10bin the X-axis direction, and the light beam L12is a light beam entering the other end portion of the light-receiving pixel10bin the X-axis direction. The light beam L13is a light beam entering a portion near the center of the light-receiving pixel10b, and the light beam L14is another light beam entering a portion near the center of the light-receiving pixel10b. Each of the distance between the light beams L11and L12in the X-axis direction and the distance between the light beams L13and L14in the X-axis direction increase as the distance from the second opening32bin the +Z-axis direction increases. FIG.10is a diagram showing imaginary back light beams61bthrough63btraveling from the light-receiving pixel10bin the +Z-axis direction, in the image reading device100aaccording to the first comparative example. The back light beams61bthrough63bare back light beams traveling in the +Z-axis direction from an object surface that is a light receiving surface of the light-receiving pixel10b. The back light beam61bis a back light beam traveling in the +Z-axis direction from a point which is an object height h=0 on the object surface. The back light beam62bis a back light beam traveling in the +Z-axis direction from a point which is an object height h=X0/2 on the object surface. The back light63bis a back light beam traveling in the +Z-axis direction from a point which is an object height h=X0on the object surface. InFIG.10andFIGS.13,16, and20described later, the first light-transmissive member51having the refractive index n and the thickness t1is replaced by a first light-transmissive member51having a refractive index 1 and a thickness t1/n. FIG.11is a diagram showing spread of the back light beams61bthrough63billustrated inFIG.10. InFIG.11, to emphasize the spread of the back light beams61bthrough63b, the imaging optical unit101ashown inFIG.10is downsized. InFIG.11, targets71through73are placed at an interval (e.g., 2 mm) from the imaging optical unit101ain the +Z-axis direction. In a case where all the back light beams pass through the targets71through73, a sufficiently large depth of field is obtained. Here, in the case of acquiring an image with a resolution of 200 dpi, as a guide, when a light beam from a range of two pixels or less on a document reaches one light-receiving pixel in the imaging optical unit, a resolution of 200 dpi is obtained. The reason why a sufficient resolution is obtained even with spread of two pixels is that a light flux on the optical axis reaches the light-receiving pixel with a minimum loss and the amount of the light flux coming from visual field ends of the two pixels on the document and reaching the light-receiving pixel is small. InFIG.11, each width of the targets71through73in the X-axis direction is a size corresponds to two pixels. In the example of the first embodiment, since the distance p in the X-axis direction between light-receiving pixels10adjacent to each other in the X-axis direction is 252 μm, the width of the targets71through73in the X-axis direction is 252 μm. InFIG.11, a position at which spread of the light flux of the back light beams61bthrough63bcorresponds to two pixels on the document6(shown inFIG.1) is denoted by70. In the following description, in each of the image reading devices according to the first and second comparative examples and the first embodiment, a distance from the imaging optical unit to the position70is denoted by Lz. In the image reading device, the document placing table needs to be placed at the +Z-axis side of the imaging optical unit. As in the first embodiment, the illumination optical unit is disposed between the imaging optical unit and the document placing table in some cases. Thus, the depth of field necessary for acquiring an image with a resolution of 200 dpi is represented by a distance from the document placing table (the top panel glass7inFIG.9) to the position70. In the following description, the depth of field of the image reading devices according to the first and second comparative examples and the first embodiment is denoted by DOF. As shown inFIGS.10and11, in the first comparative example, the back light beams61bthrough63bcontinuously spread in the X-axis direction even after passing through the second opening32b, and thus, the position70is located close to the imaging optical unit101a, and the distance Lzis small. In the first comparative example, the distance Lzis, for example, about 0.5 mm. Thus, as shown inFIG.9, if the top panel glass7having substantially the same thickness as the distance Lzis disposed between the second opening32band the reference surface S, the depth of field DOF cannot be sufficiently large in the first comparative example. In the first comparative example, it is difficult to dispose the illumination optical unit2between the imaging optical unit101aand the top panel glass7. FIG.12is a diagram schematically showing reflected light entering the light-receiving pixel10bin an image reading device100baccording to a second comparative example. The second comparative example is different from the image reading device100according to the first embodiment (shown inFIG.15described later) in including none of the third light-shielding member13and the second light-transmissive member52in the first embodiment. The second comparative example is also different from the image reading device100according to the first embodiment in disposing the condenser lenses14on the second light-shielding member12. FIG.13is a diagram showing imaginary back light beams61bthrough63btraveling from the light-receiving pixel10bin the +Z-axis direction, in the image reading device100baccording to the second comparative example. In the second comparative example, a focal length of the condenser lens14bis set such that a point on the light-receiving pixel10bcomes into a focus on the target73in the targets71through73farthest from the imaging optical unit101bin the +Z-axis direction. Here, the distance from the light-receiving pixel10bto the condenser lens14bis expressed by t0+t1/n. For example, in the second comparative example, if t0=0.25 mm, t1=0.21 mm, and n=1.52, the distance from the light-receiving pixel10bto the condenser lens14bis 0.39 mm. In a case where the targets71through73are arranged at a distance of 2.0 mm from the imaging optical unit101b, the distance from the imaging optical unit101bto the target73is 6.0 mm. Thus, the distance from the light-receiving pixel10bto the condenser lens14bis considerably smaller than the distance from the imaging optical unit101bto the target73. Thus, the focal length of the condenser lens14bis approximately 0.39 mm. At this time, as shown inFIG.13, back light beams constituting the light flux of the back light beam61bthat has passed through the condenser lens14btravel in parallel. Back light beams constituting the light flux of the back light beam62balso travel in parallel after passing through the condenser lens14b, and back light beams constituting the light flux of the back light63balso travel in parallel after passing through the condenser lens14b. The term “travel in parallel” herein includes “travel substantially in parallel”. FIG.14is a diagram showing spread of the back light beams61bthrough63billustrated inFIG.13. InFIG.14, to emphasize spread of the back lights61bthrough63b, the imaging optical unit101bshown inFIG.13is downsized. As shown inFIGS.13and14, in the second comparative example, the light flux of the back light beam61b, the light flux of the back light beam62b, and the light flux of the back light63bare focused by the condenser lens14b. Accordingly, the position70moves away in the +Z-axis direction, and the distance Lzis larger than that in the first comparative example. In the second comparative example, the distance Lzis, for example, about 1.0 mm. However, as shown inFIG.12, if the top panel glass7and the illumination optical unit2are disposed between the condenser lenses14and the reference surface S, the depth of field DOF is not sufficiently long, either, in the second comparative example. FIG.15is a diagram schematically showing reflected light entering the light-receiving pixel10bin the image reading device100according to the first embodiment. As shown inFIG.15, in the image reading device100, the condenser lenses14are disposed at a distance from the second light-shielding member12in the +Z-axis direction. Specifically, the condenser lenses14are disposed at a sufficient distance from the second light-shielding member12with the second light-transmissive member52and the third light-shielding member13interposed therebetween. FIG.16is a diagram showing the imaginary back light beams61bthrough63btraveling from the light-receiving pixel10bin the +Z-axis direction, in the image reading device100according to the first embodiment. InFIG.16andFIG.20described later, the second light-transmissive member52having the refractive index n and the thickness t2is replaced by a second light-transmissive member52having a refractive index 1 and a thickness t2/n, for convenience of description. As shown inFIG.16, the condenser lens14is disposed at the distance t2/n from the second light-shielding member12. FIG.17is a diagram showing spread of the back light beams61bthrough63billustrated inFIG.16. InFIG.17, to emphasize spread of the back lights61bthrough63b, the imaging optical unit1shown inFIG.16is downsized. In the image reading device100, the focal length of the condenser lens14bis set such that a point on the light-receiving pixel10bcomes into a focus at a point located between the target71and the target72(e.g., a point at a distance of 3.0 mm from the imaging optical unit1in the +Z-axis direction). As shown inFIGS.16and17, main light beams of the light fluxes of the back light beams61bthrough63bthat have passed through the condenser lens14bare substantially in parallel in the Z-axis direction. Here, the main light beams are light beams passing through the center of the light flux. In addition, as shown inFIG.17, in the image reading device100, since the position70is farther than the position70in the second comparative example in the +Z-axis direction, the distance Lzin the first embodiment is larger than the distance Lzin the second comparative example. In the image reading device100, the distance Lzis, for example, about 3.5 mm. Accordingly, in the image reading device100, even if the top panel glass7and the illumination optical unit2are disposed between the second opening32band the reference surface S, a sufficiently large depth of field DOF can be obtained. For example, in a case where a space of 1.5 mm is needed to dispose the top panel glass7and the illumination optical unit2, a depth of field DOF of 2.0 mm can be obtained. Thus, in the image reading device100according to the first embodiment, the condenser lens14bis disposed at a distance from the second openings32so that the depth of field DOF of the image reading device100is larger than the depths of field DOF in the first and second comparative examples. In the image reading device100, even in a case where the half width X0of the light-receiving pixels10, the half opening width X1of the first openings31, and the half opening width X2of the second openings32are increased, since the depth of field DOF can be increased, the increase in the depth of field DOF can be made with an increase in the amount of received light by the light-receiving pixels10. Lower Limit of Thickness of Second Light-Transmissive Member A lower limit of the thickness t2of the second light-transmissive member52necessary for increasing the depth of field DOF will now be described.FIG.18is a diagram showing imaginary back light beams61band63bfrom the light-receiving pixel10bin the +Z-axis direction in the image reading device100in a case where one of the first and second openings31or32is an aperture stop. Reference numeral30inFIG.18denotes the aperture stop of the imaging optical unit1. In other words, the aperture stop30is one of the first and second opening31,32. InFIG.18, a distance from the light-receiving pixel10bto the aperture stop30is denoted by L0, and a distance from the aperture stop30to the third opening33bis denoted by L1. Here, if the first opening31is the aperture stop30, the distance L0and the distance L1are expressed by Equation (10) and Equation (11): L0=t0(10) L1=t1/n+t2/n(11) If the second opening32is the aperture stop30, the distance L0and the distance L1are expressed by Equation (12) and Equation (13): L0=t0+t1/n(12) L1=t2/n(13) InFIG.18, a back light beam passing through the center of the aperture stop30in the back light beam61btraveling from the center of the light-receiving pixel10btoward the aperture stop30is represented as a main light beam64b. A back light beam passing through the center of the aperture stop30in the back light beam63btraveling from an end portion of the light-receiving pixel10bin the +X-axis direction toward the aperture stop30is represented as a main light beam65b. If the main light beam64band the main light beam65bare in parallel at the +Z axis side of the condenser lenses14, the back light beams61band63bis collected. The optical system in which the main light beam64band the main light beam65bare in parallel is called a telecentric optical system. To achieve the telecentric optical system, it is necessary that a focal length f of the condenser lens14bcoincides with the distance L1. That is, the telecentric optical system is achieved if Equation (14) below is satisfied: f=L1(14) InFIG.18, a plane including a point on which the back light beams61band63bis collected and is parallel to the XY plane is denoted by80, and the distance from the condenser lens14bto the plane80is denoted by L2. InFIG.18, the distance from the imaging optical unit1(i.e., the condenser lens14b) to the target74is denoted by L2. The range in which the target74is irradiated with a light flux is substantially equal to the opening width of the third opening33in the X-axis direction. The opening width of the third opening33corresponds to a size of two pixels. The target74is located at a position at the distance L2from the plane80in the +Z-axis direction. To increase the depth of field DOF, the distance Lzneeds to be increased. As the distance L2increases, the distance Lzincreases. Here, from the lens formula, Equation (15) below is obtained: 1/(L0+L1)+1/L2=1/f(15) From Equation (14) and Equation (15), with respect to the distance L2, Equation (16) below is derived: L2=L1·(L0+L1)/L0(16) Equation (16) shows that as the distance L1increases, the distance L2increases. To increase the distance L1, it is necessary to increase the thickness t2of the second light-transmissive member52(shown inFIG.3). In view of this, the lower limit of the thickness t2of the second light-transmissive member52is considered. First, to increase the depth of field DOF, the distance L2needs to be larger than the sum of the distance L0and the distance L1as expressed by Equation (17): L2>L0+L1(17) The sum of the distance L0and the distance L1is obtained from Equations (10) and (11) or Equations (12) and (13) by Equation (18): L0+L1=t0+(t1/n)+(t2/n) (18) In the example of the first embodiment, since t0=0.25 mm, t1=0.21 mm, t2=0.70 mm, and n=1.52, if these values are substituted into Equation (18), the sum of the distance L0and the distance L1is 0.85 mm. Thus, to increase the depth of field DOF, the distance L2needs to be larger than 0.85 mm. InFIG.18, the distance Lzis about twice as larger as the distance L2. Since the lower limit of the distance L2is, for example, 0.85 mm, the lower limit of the distance Lzis 1.7 mm in the example of first embodiment. To increase the depth of field DOF, the distance Lzneeds to be, for example, 1.7 mm or more. Next, with reference to a relationship between the distance L1and the distance L0, from Equation (16) and Equation (17), Equation (19) below is derived: L1>L0(19) Here, in the case where the first opening31is the aperture stop30, if Equation (10) and Equation (11) are substituted into Equation (19), Equation (20) regarding the thickness t2of the second light-transmissive member52is derived: t2>n·t0−t1(20) In the case where the second opening32is the aperture stop30, if Equation (12) and Equation (13) are substituted into Equation (19), Equation (21) regarding the thickness t2of the second light-transmissive member52is derived: t2>n·t0+t1(21) If the thickness t2of the second light-transmissive member satisfies Equation (21), the thickness t2also satisfies Equation (20), and thus, the lower limit of the thickness t2of the second light-transmissive member52necessary for increasing the depth of field DOF is n·t0−t1expressed by Equation (20). Thus, if the thickness t2of the second light-transmissive member52satisfies Equation (20), a sufficiently large depth of field DOF can be obtained. Upper Limit of Thickness of Second Light-Transmissive Member The upper limit of the thickness t2of the second light-transmissive member52will now be described in comparison with a comparative example.FIG.19is a diagram showing an imaginary back light beam81btraveling from the light-receiving pixel10bin the +Z-axis direction, in an image reading device100caccording to a third comparative example. The back light beam81bis back light passing through a portion of the aperture stop30bnear an end of the aperture stop30bin the −X-axis direction from an end portion of the light-receiving pixel10bin the +X-axis direction, and passing through the third opening33a. The distance L1from the aperture stop30bto the third opening33bin the third comparative example is larger than the distance L1in the image reading device100shown inFIG.18. Thus, the back light beam81bdoes not pass through the third opening33blocated at a position different from the light-receiving pixel10bbut the third opening33alocated at a position not overlapping the light-receiving pixel10b. The back light beam81bbecomes the back light beam82bafter passing through the third opening33aand the condenser lens14a. The distance between the back light beam82band the optical axis40bin the X-axis direction increases with away from the condenser lens14ain the +Z-axis direction. That is, in the third comparative example, an excessively large distance L1causes the presence of light beams passing through third openings except the third opening33bat a different position from the light-receiving pixel10b, and the imaging optical unit1acquires an image affected by stray light. The following description is directed to the upper limit of the distance L1necessary for preventing the back light beam81bfrom passing through the third opening33aadjacent to the third opening33boverlapping the light-receiving pixel10band the upper limit of the thickness t2of the second light-transmissive member52. Next, inFIG.19, a half opening width that is a width of ½ of the opening width of each of the third openings33aand33bin the X-axis direction is denoted by X3. Since the distance between the center positions of the adjacent third openings33aand33bin the X-axis direction is p, the half opening width X3is smaller than ½ of the distance p. Thus, the relationship between the half opening width X3and the distance p is expressed by Equation (22): X3<p/2 (22) A half opening width that is a width of ½ of the opening width of the opening30bin the X-axis direction is denoted by X4. If the first opening31(shown inFIG.1) is the aperture stop30b, the half opening width X4is expressed by Equation (23): X4=X1(23) If the second opening32(shown inFIG.1) is the aperture stop30b, the half opening width X4is expressed by Equation (24): X4=X2(24) InFIG.19, an angle formed by the back light beam81bwith respect to the optical axis40bis denoted by θ2. In a case where the back light beam81btraveling from an end portion of the light-receiving pixel10bin the +X-axis direction toward an end portion of the aperture stop30bin the −X-axis direction, the angle θ2is expressed by Equation (25): tan θ2=(X0+X4)/L0(25) Here, supposing the distance between the point R4in the third opening33awhere the back light beam81breaches and the optical axis40bis A, the angle θ2formed by the back light beam81bwith respect to the optical axis40bis expressed by Equation (26) described below, which is different from Equation (25). tan θ2=(X0+A)/(L0+L1) (26) From Equation (26) and Equation (27), with respect to the distance A, Equation (27) is derived: A=((L0+L1)·(X0+X4)/L0)−X0(27) A condition for preventing the back light beam81bfrom passing through the third opening33ais expressed by Equation (28): A<p−X3(28) From Equation (27) and Equation (28), Equation (29) regarding the upper limit of the distance L1is derived. L1<L0·(p−X3−X4)/(X0+X4) (29) Thus, if the distance L1satisfies Equation (29), the back light beam81bdoes not pass through the third opening33aadjacent to the third opening33boverlapping the light-receiving pixel10b. Next, the upper limit of the thickness t2of the second light-transmissive member52is obtained from Equation (29). If the first opening31is the aperture stop30, from Equations (10), (11), and (23) and Equation (29), Equation (30) regarding the thickness t2of the second light-transmissive member52is derived: t2<(n·t0·(p−X3−X1)/(X0+X1))−t1(30) Next, if the second opening32is the aperture stop30, from Equations (12), (13), and (24) and Equation (29), Equation (31) regarding the thickness t2of the second light-transmissive member is derived: t2<(n·t0+t1)·(p−X3−X2)/(X0+X2) (31) FIG.20is a diagram showing an imaginary back light beam81btraveling from the light-receiving pixel10bin the +Z-axis direction in the image reading device100according to the first embodiment in the case where the first opening31bis the aperture stop30b(shown inFIG.19). As shown inFIG.20, the back light beam81btraveling from an end portion of the light-receiving pixel10bin the +X-axis direction toward the first opening31bpasses through the second opening32b. The back light beam81bthat has passed through the second opening32breaches the third light-shielding member13. Here, supposing a line extending from a point at which the back light beam81breaches the third light-shielding member13toward an imaginary line V is a line83b, the line83bintersects with the imaginary line V at the point Q1. The imaginary line V is a line passing through an end portion of the third opening33ain the +X-axis direction and parallel to the optical axes40aand40b. A point at which a line84bconnecting an end portion of the light-receiving pixel10bin the +X-axis direction and an end portion of the second opening32bin the −X-axis direction intersects with the imaginary line V is denoted by Q2. The line84bdoes not pass through the first opening31b, and thus, a light beam traveling along the line84bis blocked by the first light-shielding member11. Here, the distance from the point Q1to the second light-shielding member12corresponds to a value obtained by dividing the right side of Equation (30) by the refractive index n of the second light-transmissive member52(i.e., M1/n). The distance from the point Q2to the second light-shielding member12corresponds to a value obtained by dividing the right side of Equation (31) by the refractive index n (i.e., M2/n). Here, M1 and M2 are individually expressed by Equation (32) and Equation (33): M1=(n·t0·(p−X3−X1)/(X0+X1))−t1(32) M2=(n·t0+t1)·(p−X3−X2)/(X0+X2) (33) If the first opening31is the aperture stop30, M1≥M2 is established. InFIG.20, since the first opening31is the aperture stop30, from Equation (30) and Equation (32), the thickness t2of the second light-transmissive member52is smaller than M1. Accordingly, there is no back light passing through the third opening33aat a position not overlapping the light-receiving pixel10b, and an image not affected by stray light can be acquired. InFIG.20, since the point Q2is located at the −Z axis side of the third opening33a, the thickness t2of the second light-transmissive member52is larger than M2. However, as described above, a light beam traveling along the line84bis blocked by the first light-shielding member11. Accordingly, if the first opening31is the aperture stop30, the relationship between the thickness t2of the second light-transmissive member52and M2 is not taken into consideration, and it is necessary to satisfy the condition that the thickness t2of the second light-transmissive member52is smaller than M1. If the second opening32is the aperture stop30, M2≥M1 is established. In this case, if the thickness t2of the second light-transmissive member52is smaller than M2, there is no back light passing through the third opening33aat a position not overlapping the light-receiving pixel10b. As described above, the upper limit of the thickness t2of the second light-transmissive member52necessary for preventing back light from passing through the third opening33ais obtained by Equation (34): t2<MAX{M1,M2} (34) In the example of the first embodiment, since t0=250 μm, t1=210 μm, n=1.52, X0=35.0 μm, X1=27.0 μm, X2=43.0 μm, and X3=85.0 μm, if these values are substituted into Equation (32) and Equation (33), M1=769 μm, and M2=1095 μm are obtained. Thus, from Equation (34), the upper limit of the thickness t2of the second light-transmissive member52is 1095 μm. In the example of the first embodiment, since the thickness t2of the second light-transmissive member52is 700 μm, Equation (34) is satisfied. As described above, to increase the depth of field, the focal length f of the condenser lenses14needs to coincide with the distance L1. However, as described above, the value of the distance L1varies depending on which one of the first openings31or the second openings32is the aperture stop30. Thus, the focal length f of the condenser lenses14needs to satisfy the condition represented by Equation (35): t2/n≤f≤(t1/n)+t2/n(35) Even if Equation (35) is satisfied, spread of back light is large is some cases. Thus, it is necessary to determine the position of a preferable focus F of the condenser lens14in order to reduce spread of back light. Focus Position of Condenser Lens A position of the focus F of the condenser lens14necessary for reducing spread of back light will now be described by using a tracking result of back light.FIG.21Ais a diagram showing imaginary back light beams traveling from the light-receiving pixel10bin the +Z-axis direction, in an image reading device100daccording to a fourth comparative example. In the fourth comparative example, the position of the focus F of the condenser lens14bin the Z-axis direction overlaps the position of the light-receiving pixel10bin the Z-axis direction. As shown inFIG.21A, in the fourth comparative example, the distance Lzfrom the condenser lenses14to the plane80is small, and the depth of field is small. FIG.21Bis a diagram showing imaginary back light beams traveling from the light-receiving pixel10bin the +Z-axis direction, in an image reading device100eaccording to a fifth comparative example. In the fifth comparative example, the position of a focus F of the condenser lens14bin the Z-axis direction overlaps the position of the second opening32bin the Z-axis direction. In the fifth comparative example, a light condensing power of the condenser lens14bis high, and the position at which back light comes into a focus is close to the condenser lens14b. Accordingly, in the fifth comparative example, spread of back light that has passed through the plane80is large, and thus, the distance Lzis small, and as in the fourth comparative example, the depth of field is small. FIG.22Ais a diagram showing the imaginary back light traveling from the light-receiving pixel10bin the +Z-axis direction, in the image reading device100according to the first embodiment. In the image reading device100, the position of the focus F of the condenser lens14bin the Z-axis direction is located between the light-receiving pixel10band the first opening31b.FIG.22Bis a diagram showing imaginary back light traveling from the light-receiving pixel10bin a +Z-axis direction, in an image reading device110according to a variation of the first embodiment. In the image reading device110, the position of the focus F of the condenser lens14bin the Z-axis direction overlaps the position of the first opening31bin the Z-axis direction. The value of distance Lzshown inFIG.22Bis substantially equal to the value of the distance Lzshown inFIG.22A. In the image reading devices100and110, as compared to the fourth and fifth comparative examples, the distances Lzare large, and the depths of field can be increased. FromFIGS.21A and21BandFIGS.22A and22B, when the position of the focus F of the condenser lens14bis set between the light-receiving pixel10bcorresponding to the condenser lens14band the second opening32bcorresponding to the light-receiving pixel10b, spread of back light can be reduced, and the depth of field of the image reading device100can be increased. A region between the light-receiving pixel10band the second opening32bis a region sandwiched between the surface of the second light-shielding member12toward the −Z-axis direction and the surface of the light-receiving pixels10toward the +Z-axis direction shown inFIG.2. Third Light-Shielding Member Next, with reference toFIGS.1,2,3, and16, the third light-shielding member13of the image reading device100according to the first embodiment will be described. As shown inFIG.1, the third light-shielding member13includes circular third openings33. The opening width (i.e., diameter) of each of the third openings33is smaller than an effective diameter of each of the condenser lenses14. Thus, a back light beam66bshown inFIG.16reaches the third light-shielding member13. That is, since the image reading device100includes the third light-shielding member13, scattered light generated on the document6is blocked by the third light-shielding member13, and thus, scattered light does not reach the light-receiving pixel10b. Accordingly, in the image reading device100, degradation of contrast of an image or generation of a ghost image is prevented, and thus, the image reading device100is capable of reading an image with a high quality. The diameter Φ of the third opening33bshown inFIG.16is larger than the width of light flux of each of the back light beams61bthrough63bin the X-axis direction. Accordingly, all the back light beams61bthrough63bpass through the third opening33b. Thus, as shown inFIGS.2and3, in the configuration in which the third light-shielding member13including the third openings33and the condenser lenses14are disposed between the second openings32and the reference surface S, a decrease in the amount of light received by the light-receiving pixels10is small. Advantages of First Embodiment As described above, in the image reading device100according to the first embodiment, the condenser lenses14are disposed at a distance from the second openings32. Thus, even in the case where the width of the light-receiving pixels10in the X-axis direction and the opening areas of the first and second openings31and32are increased in order to increase the amount of light received by the light-receiving pixels10, the depth of field can be increased. In addition, in the image reading device100according to the first embodiment, since the focus F of the condenser lens14is located between the light-receiving pixels10and the second openings32, the depth of field can be further increased. In the image reading device100according to the first embodiment, the thickness t2of the second light-transmissive member52satisfies Equation (20) so that the depth of field can be further increased. In the image reading device100according to the first embodiment, the thickness t1of the first light-transmissive member51satisfies Equation (4), reflected light beams that have passed through the second openings32and the first openings31corresponding to the light-receiving pixels10enter the light-receiving pixels10, and thus, an image not affected by stray light can be acquired. In the image reading device100according to the first embodiment, the thickness t1of the first light-transmissive member51satisfies Equation (9) so that reflected light beams that have passed through the second openings32and the first openings31corresponding to the light-receiving pixels10enter the light-receiving pixels10, and thus, an image not affected by stray light can be acquired. In addition, in the image reading device100according to the first embodiment, the thickness t2of the second light-transmissive member52satisfies Equation (34) so that reflected light beams that have passed through the third opening, second openings32and the first openings31corresponding to the light-receiving pixels10enter the light-receiving pixels10, and thus, an image not affected by stray light can be acquired. Variation of First Embodiment FIG.23is a diagram showing imaginary back light beams L15through L18traveling from the light-receiving pixel10bin the +Z-axis direction, in an image reading device120according to a variation of the first embodiment. The image reading device120is different from the image reading device100in arrangement positions of the condenser lenses14athrough14c. Specifically, in the image reading device120, center positions94of the condenser lenses14athrough14care shifted in the +X-axis direction from center positions90of the light-receiving pixels10athrough10c. As shown inFIG.23, in the image reading device120, back light beams L15through L17pass through the condenser lens14b, and then are tilted in the +X-axis direction. This tilt, however, does not affect image performance such as resolution. The back light beam L18is a back light traveling from an end portion of the light-receiving pixel10bin the +X-axis direction toward the third light-shielding member13through the second opening32b. The back light beam L18includes a back light beam L18ablocked by the third light-shielding member13, and a back light beam L18bpassing through the condenser lens14aif the image reading device120is assumed not to include the third light-shielding member13. The back light beam L18btravels in a direction different from the back light beams L15through L17(i.e., a direction tilted in the −X-axis direction). InFIG.23, however, since the image reading device120includes the third light-shielding member13, the back light beam L18ais blocked by the third light-shielding portion43. Here, a difference between the diameter of the third openings33athrough33cand the effective diameter of the condenser lenses14athrough14cis an allowable error of arrangement positions of the condenser lenses14athrough14c. In the image reading device120, the diameter of the third openings33athrough33cis smaller than the effective diameter of the condenser lenses14athrough14c. Thus, even when the arrangement positions of the condenser lenses14athrough14cto the light-receiving pixels10athrough10care shifted, an image not affected by stray light can be acquired. FIG.24is a perspective view showing an imaging optical unit1aof an image reading device130according to a variation of the first embodiment of the present invention.FIG.25is a diagram schematically showing reflected light entering light-receiving pixels10in the image reading device130shown inFIG.24. The same reference characters as those inFIG.1designate the same or corresponding components as those shown inFIG.1, and description thereof will be omitted. The image reading device130is different from the image reading device100according to the first embodiment in arrangement positions of the condenser lenses14. As shown inFIGS.24and25, in the image reading device130, the third light-transmissive member53is disposed between the second light-transmissive member52and the condenser lenses14. The third light-transmissive member53is, for example, a transparent glass member. The third light-transmissive member does not need to be completely transparent and may be translucent. The third light-transmissive member53is fixed to the third light-shielding member13by bonding with, for example, an adhesive. The condenser lenses14are disposed on the third light-transmissive member53. The condenser lenses14are formed on a surface53aof the third light-transmissive member53facing the reference surface S (shown inFIG.1). Since the condenser lenses14are formed on the surface53aof the third light-transmissive member53, the step of forming the condenser lenses14and the step of positioning the condenser lenses14and the third openings33are separate steps, and thus, accuracy in positioning the condenser lenses14and the third openings33can be enhanced. In the image reading device130, no light-shielding member is present between the third light-transmissive member53and the condenser lenses14. Thus, stray light occurs unless light beams L11and L12passing through both ends of the third openings33in light beams passing through the third openings33are included within the range of the opening diameter of the condenser lenses14. Here, the light beams L11and L12are light beams whose spread in the X-axis direction gradually increases as the distance from the third openings33in the +Z-axis direction increases. Thus, as a thickness t3of the third light-transmissive member53increases, spread of back light of the light beams L11and L12increases. In view of this, in the image reading device130, since the thickness t3of the third light-transmissive member53is sufficiently thin, the light beams L11and L12are included within the range of effective diameter of the condenser lens14a. Thus, in the image reading device130, an image not affected by stray light can be acquired. The thickness t3of the third light-transmissive member53is smaller than the thickness t2of the second light-transmissive member52, and is, for example, 210 μm. Since the light beams L11and L12are included within the range of effective diameter of the condenser lenses14, not only the configuration in which the thickness t3of the third light-transmissive member53is reduced but also a configuration in which the opening width of the third openings33is reduced may be employed. Regarding the other aspects, the image reading device130according to the variation of the first embodiment is the same as the image reading device100according to the first embodiment. Second Embodiment FIG.26is a perspective view schematically showing a configuration of an imaging optical unit201of an image reading device200according to a second embodiment. InFIG.26, the same reference characters as those inFIG.1designate the same or corresponding components as those shown inFIG.1. The image reading device200is different from the image reading device100according to the first embodiment in further including a fourth light-shielding member15. As shown inFIG.26, in the imaging optical unit201of the image reading device200, the fourth light-shielding member15is disposed between the first light-shielding member11and the second light-shielding member12. The fourth light-shielding member15includes a plurality of fourth openings35. The plurality of fourth openings35are arranged to correspond to the plurality of first openings31respectively and correspond to the plurality of second openings32respectively. The plurality of fourth openings35are arranged in two lines. The plurality of fourth openings35are arranged in the X-axis direction. The plurality of fourth openings35are arranged in a staggered pattern. When seen in the Z-axis direction, the plurality of fourth openings35overlap the plurality of first openings31respectively and overlap the plurality of second openings32respectively. In the image reading device200, reflected light that has passed through the third openings33sequentially passes through the second openings32, the fourth openings35, and the first openings31in this order, and enters the light-receiving pixels10. The first light-transmissive member251is formed by bonding a plurality of (two in this example) glass boards251aand251btogether with, for example, an adhesive. A first light-shielding member11is provided on a surface of the glass board251afacing the light-receiving pixels10, and a second light-shielding member12is provided on a surface of the glass board251bfacing the condenser lenses14. The fourth light-shielding member15is provided between the glass boards251aand251b. The fourth light-shielding member15may be formed on any one of the surface of the glass board251afacing the condenser lenses14or the surface of the glass board251bfacing the light-receiving pixels10. In the first embodiment in which the first light-transmissive member51is constituted by one glass board, to suppress occurrence of stray light, the thickness t1of the first light-transmissive member51needs to satisfy the conditions expressed by Equation (4) and Equation (9). On the other hand, in the second embodiment, since the fourth light-shielding member15is disposed between the first light-shielding member11and the second light-shielding member12and the first light-transmissive member251is constituted by the glass boards251aand251b, the thickness t1of the first light-transmissive member51does not need to satisfy the conditions expressed by Equation (4) and Equation (9). A plurality of light-shielding members may be disposed between the first light-shielding member11and the second light-shielding member12. That is, the first light-transmissive member251may be constituted by three or more glass boards and another light-shielding member may be provided between adjacent glass boards. Regarding the other aspects, the image reading device200according to the second embodiment is the same as the image reading device100according to the first embodiment. The image reading device200according to the second embodiment can obtain advantages same as those of the image reading device100according to the first embodiment. In the image reading device200according to the second embodiment, since the fourth light-shielding member15is disposed between the first light-shielding member11and the second light-shielding member12, even when the distance between openings adjacent to each other in the X-axis direction is reduced, reflected light that has passed through the second openings32, the fourth openings35, and the first openings31corresponding to the light-receiving pixels10enters the light-receiving pixels10. As a result, in the image reading device200according to the second embodiment, an image with a high resolution can be acquired. Third Embodiment FIG.27is a perspective view schematically showing a configuration of an imaging optical unit301of an image reading device300according to a third embodiment of the present invention. InFIG.27, the same reference characters as those inFIG.1designate the same or corresponding components as those shown inFIG.1. The image reading device300is different from the image reading device100according to the first embodiment in arrangement of light-receiving pixels and arrangement of openings. As shown inFIG.27, in the imaging optical unit301of the image reading device300, a plurality of light-receiving pixels310are arranged in a line. A plurality of first openings331are arranged in a line. A plurality of second openings332are arranged in a line. A plurality of third openings333are arranged in a line. A plurality of condenser lenses314are arranged in a line. Accordingly, a fabrication process of the image reading device300can be eased. In the third embodiment, to acquire an image with a resolution of 200 dpi, an arrangement pitch p (i.e., distance between adjacent light-receiving pixels310) of the light-receiving pixels310needs to be set at 126 μm, which is ½ of an arrangement pitch (i.e., distance between adjacent light-receiving pixels10) in the first embodiment. Here, in the third embodiment, a thickness t1of a first light-transmissive member351necessary for acquiring an image not affected by stray light is considered. If the half width X0=31.5 μm of the light-receiving pixels310, the refractive index n=1.52 of the first light-transmissive member51, the half opening width X1=20.0 μm of the first openings331, the half opening width X2=20.0 μm of the second openings332, and the distance t0=100 μm from the light-receiving pixels310to the first openings331are substituted into Equation (4) and Equation (9) described in the first embodiment, Equation (36) is derived: 93.6 μm≤t1≤98.4 μm (36) Thus, in the image reading device300according to the third embodiment, to acquire an image not affected by stray light, the thickness t1of the first light-transmissive member351needs to satisfy Equation (36). In the third embodiment, to acquire an image with a resolution of 100 dpi, it is necessary that the half width X0of light-receiving pixels310is 31.5 μm, the refractive index n of the first light-transmissive member351is 1.52, the half opening width X1of the first openings331is 24.0 μm, the half opening width X2of the second openings332is 38.0 μm, the half opening width X3of the third openings333is 850 μm, the distance t0from the light-receiving pixels310to the first openings331is 250 μm, and the thickness t2of the second light-transmissive member52is 700 μm. Regarding aspects except for those described above, the image reading device300according to the third embodiment is the same as the image reading device100according to the first embodiment. The image reading device300according to the third embodiment can obtain advantages same as those of the image reading device100according to the first embodiment. Accordingly, in the image reading device300according to the third embodiment, a fabrication process of the image reading device300can be eased. Fourth Embodiment FIG.28is a perspective view schematically showing a configuration of an imaging optical unit401of an image reading device400according to a fourth embodiment of the present invention. InFIG.28, the same reference characters as those inFIG.1designate the same or corresponding components as those shown inFIG.1. The image reading device400is different from the image reading device100according to the first embodiment in arrangement of the light-receiving pixels, arrangement of the first opening, arrangement of the second opening, arrangement of the third opening, and arrangement of the condenser lenses. Accordingly, the document6does not need to be conveyed, and two-dimensional image information can be acquired from the stationary document6. As shown inFIG.28, in the imaging optical unit401of the image reading device400, a plurality of light-receiving pixels410are arranged in a matrix, that is, in columns and rows. A plurality of first openings431are arranged in a matrix. A plurality of second openings432are arranged in a matrix. A plurality of third openings433are arranged in a matrix. A plurality of condenser lenses414are arranged in a matrix. Regarding aspects except for those described above, the image reading device400according to the fourth embodiment is the same as the image reading device100according to the first embodiment. The image reading device400according to the fourth embodiment can obtain advantages same as those of the image reading device100according to the first embodiment. In the image reading device400according to the fourth embodiment, the document6does not need to be conveyed, and two-dimensional image information can be acquired from the stationary document6. INDUSTRIAL APPLICABILITY The image reading devices according to the first through fourth embodiments are applicable to copying machines, bill readers, and so forth. DESCRIPTION OF REFERENCE CHARACTERS 6document,10,310,410light-receiving pixel,11first light-shielding member,12second light-shielding member,13third light-shielding member,14,14a,314,414condenser lens,15fourth light-shielding member,31,331,431first opening,32,332,432second opening,33,333,433third opening,35fourth opening,51,251,351first light-transmissive member,52second light-transmissive member,53third light-transmissive member,100,110,120,130,200,300,400image reading device, F focus, S reference surface. | 83,013 |
11942490 | DETAILED DESCRIPTION A photon counting radiation detector according to one or more embodiments includes: a cell structure including a substrate, and an epitaxial layer provided on the substrate, radiation being incident on the epitaxial layer; an inclination θ of the substrate satisfying Formula (1) below, where tsubis a thickness of the substrate, tepiis a thickness of the epitaxial layer, L is a length of the substrate, and the inclination θ is an inclination of the substrate with respect to an incident direction of the radiation. θ≦tanθ≦L±L2-4tsub(tsub+tepi)2(tsub+tepi).(1) FIG.1illustrates an example of the cell structure. InFIG.1,1denotes the cell structure,2denotes the epitaxial layer,3denotes the substrate,100denotes the photon counting radiation detector, tsubdenotes the thickness of the substrate, tepidenotes the thickness of the epitaxial layer2, L denotes the length of the substrate, and θ denotes the inclination of the substrate with respect to an X-ray incident direction. The photon counting radiation detector100includes the cell structure1. The photon counting radiation detector is formed by disposed wiring, an insulating layer, and the like (not illustrated) in the cell structure. Herein, the cell structure will mainly be described. Also, the photon counting radiation detector100is capable of detecting radiation, such as X-rays and gamma rays. In the example described herein, the photon counting radiation detector100detects X-rays. The technology described below can also be applied in a similar manner to a photon counting radiation detector100that detects gamma rays. FIG.2illustrates an example of an array structure including cell structures arranged side by side. InFIG.2,2denotes the epitaxial layer,3denotes the substrate, tsubdenotes the thickness of the substrate, tepidenotes the thickness of the epitaxial layer2, θ denotes the inclination of the substrate with respect to an X-ray incident direction,6denotes a spacer, and10denotes the array structure. Note that the thickness tsubof the substrate is a value that includes the thickness of the substrate, the electrode, and the insulating layer. The thickness tsubof the substrate is, in other words, the length of the substrate3in a first direction D1connecting the epitaxial layer2and the substrate3. The thickness tepiof the epitaxial layer is the length of the epitaxial layer2in the first direction D1. The length L of the substrate is the length of the substrate3in a second direction D2perpendicular to the first direction D1. The second direction D2is parallel with a plane that runs in both the first direction D1and an X-ray incident direction DX. The inclination θ corresponds to the angle between the X-ray incident direction and the second direction D2. The relationship between the thickness tsubof the substrate, the thickness tepiof the epitaxial layer, the length L of the substrate, and the inclination θ of the substrate satisfies the following Formula (2). (L-tsubtanθ)sinθ=tsub+tepicosθ-(tsub+tepi)cosθ(2) The cell structure includes the substrate3and the epitaxial layer2provided on the substrate3. The substrate of the cell structure is inclined with respect to the X-ray incident direction. Note that for the inclination θ of the substrate, the X-ray incident direction is 0°. Also, when the substrate is inclined to the down and right, θ is a positive angle. When the substrate is inclined to the down and left, θ is a negative angle. In the state illustrated inFIG.2, θ is a positive angle. Also, in Formula (2), the inclination θ of the substrate3is an absolute value. In other words, in Formula (2), the inclination θ is given as a positive angle even when it is a negative angle. The incident direction is perpendicular to the direction in which the plurality of cell structures1are arranged side by side, for example. The substrate3is used to form the epitaxial layer2. Also, the epitaxial layer2is capable of converting incident X-ray photons into electrical signals. By the epitaxial layer being present continuously with respect to the X-ray incident direction, the regions incapable of detecting X-ray photons can be reduced. However, the plurality of cell structures need to be disposed without overlapping the epitaxial layers2of adjacent cell structures with respect to the X-ray incident direction. If adjacent epitaxial layers2are overlapped, contamination occurs when X-ray photons are detected. As a result, X-ray photons are unable to be accurately detected. Contamination is image blur caused by a plurality of the epitaxial layers2detecting the same X-ray photon. In Patent Document 2, contamination of X-ray photon detection is prevented by covering the semiconductor element with a shielding material. Lead is used in the shielding material. However, lead is a toxic material that is hard to use. In the cell structure according to one or more embodiments, the inclination θ of the substrate with respect to the X-ray incident direction is set within a specific range. By setting the inclination of the substrate depending on the thickness of the substrate, the length of the substrate, and the thickness of the epitaxial layer, the regions incapable of detection can be reduced and detection contamination can be suppressed. Formula (2) will now be described. First, as illustrated inFIG.2, [(tsub+tepi)/cos θ−(tsub+tepi)cos θ] must take a value equal to or greater than 0. (tsub+tepi)/cos θ is the width of a single epitaxial layer2as seen from the X-ray incident direction. (tsub+tepi)/cos θ is the pixel size. (tsub+tepi)cos θ is the width from the lower end portion of the substrate3to the lower end portion of the epitaxial layer2as seen from the X-ray incident direction. The width is, in other words, the length in the direction perpendicular to the X-ray incident direction and in the direction in which the cell structures1are arranged. As [(tsub+tepi)/cos θ−(tsub+tepi)cos θ] approaches zero, the angle between the inclination θ of the substrate3and the X-ray incident direction decreases. Also, the relationship of Formula (3) is applied so that adjacent cell structures are disposed with the epitaxial layers2not overlapped with respect to the X-ray incident direction. L-tsubtanθ=(tsub+tepi)(1+tan2θtanθ-1tanθ)=(tsub+tepi)tanθ(3) Formula (3) is represented by Formula (4). 0≤L2−4tsub(tsub+tepi) (4) From Formula (4), the relationship of Formula (1) is satisfied for the inclination θ of the substrate. θ≦tanθ≦L±L2-4tsub(tsub+tepi)2(tsub+tepi)(1) Also, the following Formula (4) is satisfied. 0≤L2−4tsub(tsub+tepi) (4) Formula (1) being satisfied for the inclination θ of the substrate3means that adjacent cell structures are disposed with the epitaxial layers2not overlapped with respect to the X-ray incident direction. If the epitaxial layers2of adjacent cell structures are overlapped with respect the X-ray incident direction, image blur occurs. This is because a single X-ray photon is detected by two cells. Also, the inclination θ of the substrate is an absolute value of the angle of the substrate with respect to the X-ray incident direction. Thus, the angle of the substrate with respect to the X-ray incident direction may be a positive angle or a negative angle. Also, the inclination θ of the substrate is preferably a value greater than 0°. When the inclination θ of the substrate is 0°, the substrate is parallel with the X-ray incident direction. When the inclination θ of the substrate is 0°, contamination (image blur) of the detection by adjacent cell structures does not occur. However, the region of the thickness tsubof the substrate3is made a region incapable of detecting X-ray photons. In other words, when a gap is formed between the epitaxial layers2of adjacent cell structures with respect to the X-ray incident direction, a region incapable of detection is formed. Also, increasing the inclination θ of the substrate makes (tsub+tepi)/cos θ decrease. This allows the pixels to be made smaller. In other words, by adjusting the inclination θ of the substrate while satisfying Formula (1), image blur can be prevented and the pixels can be made smaller. Thus, the inclination θ of the substrate3is preferably a value greater than 0°, while satisfying Formula (1). By setting the inclination θ of the substrate3within this range, detection contamination suppression and higher resolution can both be achieved in a compatible manner. The cell structure includes the epitaxial layer2provided on the substrate3. The epitaxial layer2preferably includes one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Also, the substrate3preferably includes one type selected from SiC, Ga2O3, GaAs, GaN, diamond, and CdTe. Furthermore, the epitaxial layer2is preferably a layer grown epitaxially on the substrate3. Because of this, the materials of the epitaxial layer2and the substrate3are preferably the same. Also, the epitaxial layer2and the substrate3are preferably made from SiC or Ga2O3. Epitaxial growth on the substrate is easy when these materials are used. Also, the substrate can be easily thinned using the etching process described below. Furthermore, because X-rays pass through these substrate materials, there are no negative effects on the detection of X-rays via the epitaxial layer2. The epitaxial layer2and the substrate3may be made of a single crystal. Also, when SiC is used in the epitaxial layer2, 4H—SiC is preferably used. SiC polytypes include 4H—SiC, 6H—SiC, and 3C—SiC. Of these, 4H—SiC has the largest band gap of 3.25 eV. By using a material with a large band gap, leakage current can be reduced. These materials also allow for operations at room temperature. The epitaxial layer2is a high-quality layer compared to the substrate3. Specifically, the impurity concentration and the density of defect states of the epitaxial layer2per unit volume is less than those of the substrate3by at least two orders of magnitude. For example, when the impurity concentration of a SiC substrate is approximately 1018cm−3, the impurity concentration of a SiC epitaxial layer is 1016cm−3or less. The same holds true for the density of defect states. Also, the epitaxial layer2and the substrate3are discernable by observing the cross-sectional structure. The epitaxial layer2has a higher density than the substrate3. In particular, by using a single-crystal substrate, the epitaxial layer2can also be single crystal. When a single-crystal substrate3is used, a high-quality epitaxial layer can be easily formed. Also, the amount of impurities can be calculated from the relationship between the reverse voltage and the depletion layer capacitance. The reverse voltage is set as V, the depletion layer capacitance is set as C, the Schottky barrier is set as φB, the load is set as q, the impurity concentration is set as Nd, and the dielectric constant of the material is set as ε. The relationship between the reverse voltage V and the depletion layer capacitance C satisfies the relationship formula: 1/C2=−2(V−φB)/qNdε. The dielectric constant ε of the material is the dielectric constant of the material the epitaxial layer2and the substrate3are made of. For example, the dielectric constant ε of SiC is 9.7, the dielectric constant ε of GaN is 9.0, the dielectric constant ε of Ga2O3is 10.0, and the dielectric constant ε of diamond is 5.5. By measuring the reverse voltage V and the depletion layer capacitance C (1/C2), the impurity concentration Ndcan be calculated using the relationship formula described above. The impurity concentration Ndis also referred to as donor concentration. Also, for the reverse voltage V, preferably an LCR meter capable of applying a high voltage of approximately −200 V is used. By applying a high voltage, depletion of the substrate3begins after the depletion of the epitaxial layer2. This allows measurements to be performed with the epitaxial layer2and the substrate3in an integrally formed state. Also, by setting the inclination θ of the substrate to a predetermined value, the side surface of the epitaxial layer2can be an X-ray incident surface. This allows the incident surface to be made smaller. By making the incident surface smaller, the detection pixels can be made smaller. Also, the thickness tepiof the epitaxial layer is preferably 100 μm or less. The thickness tepiof the epitaxial layer is more preferably 30 μm or less, and even more preferably 10 μm or less. A thin thickness tepiallows the detection pixels to be made smaller. The minimum value of the thickness tepiof the epitaxial layer2is not particularly limited, but is preferably 1 μm or greater. A thickness tepiof less than 1 μm produces an electrical signal that is too small. The thickness tsubof the substrate is preferably 500 μm or less. When the thickness tsubof the substrate is greater than 500 μm, regions incapable of detection may increase. Thus, the thickness tsubof the substrate is preferably 500 μm or less, and more preferably 100 μm or less. Also, the lower limit value of the thickness tsubof the substrate is not particularly limited, but is preferably 5 μm or greater. When the thickness tsubof the substrate is less than 5 μm, the strength of the substrate is reduced. A substrate with low strength may be easily damaged when the array structure is assembled. Thus, the thickness tsubof the substrate preferably ranges from 5 μm to 500 μm, and more preferably ranges from 5 μm to 100 μm. By making the substrate thin, the regions incapable of detection can be reduced and the spatial resolution can be improved. Also, the thickness of the substrate can be adjusted by using a substrate with a predetermined thickness or by thinning the substrate via machining/finishing or etching. Furthermore, the thickness of the electrode, the insulating layer, and the like are included in the thickness tsubof the substrate. An electrode is preferably provided in the cell structure. The electrode provided in the cell structure preferably includes one or more types selected from the group consisting of carbon, silicon, titanium, platinum, and nickel. FIG.3illustrates an example of a cell structure provided with electrodes. InFIG.3,1denotes the cell structure,2denotes the epitaxial layer,3denotes the substrate,4denotes a front electrode,5denotes a rear electrode, and100denotes the photon counting radiation detector. InFIG.3, the electrode provided on the side the epitaxial layer2is provided on corresponds to the front electrode4, and the electrode provided on the side of the substrate3corresponds to the rear electrode5. Also, inFIG.3, the cell structure is illustrated as seen from the side surface. The front electrode4is provided on the entire surface or a portion of the epitaxial layer2. Also, a plurality of the front electrodes4may be provided on the front surface of the epitaxial layer2. The rear electrode5is provided on the entire surface or a portion of the rear surface of the substrate3. Also, a plurality of the rear electrodes5may be provided on the rear surface of the substrate3. The thickness tsubof the substrate corresponds to the sum of the thickness of the substrate3, the thickness of the front electrode4, and the thickness of the rear electrode5. Also, the electrode material is preferably one type selected from a metal, a metal oxide, a metal carbide, and a metal silicide. For a metal electrode, one type selected from titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), platinum (Pt), and nickel (Ni) is preferably used. For a metal oxide electrode, titanium oxide (TiO2) is preferably used. For a metal carbide electrode, one type selected from titanium carbide (TIC), tungsten carbide (WC), molybdenum carbide (Mo2C), tantalum carbide (TaC), and niobium carbide (NbC) is preferably used. For a metal silicide electrode, one type selected from titanium silicide (TiSi2), tungsten silicide (WSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), and niobium silicide (NbSi2) is preferably used. When the epitaxial layer2and the substrate3include silicon carbide (SiC) or diamond, a metal carbide electrode or a metal silicide electrode is preferably provided. Among these, Mo2C, W, WC, and W2C are preferable. When the epitaxial layer2and the substrate3include a carbon component, a metal carbide electrode or a metal silicide electrode can be used to help suppress a reaction between the electrode and the epitaxial layer (or the substrate). In this way, stable electrical characteristics can be obtained. Also, the cell structure can have a long service life. Also, when the epitaxial layer2and the substrate3include gallium oxide (Ga2O3), gallium arsenide (GaAs), gallium nitride (GaN), or cadmium telluride (CdTe), a metal electrode or a metal oxide electrode is preferably used. Among these, Pt, Ni, and TiO2are preferable. Also, titanium nitride (TiN) may be used in the electrode. This can help suppress a reaction between the electrode and the epitaxial layer (or the substrate). The metal electrode, the metal carbide electrode, and the metal silicide electrode can be formed via sputtering. Methods that may be used other than sputtering include chemical vapor deposition (CVD), ion plating, vapor deposition, thermal spraying, plating, and the like. FIG.4is a schematic diagram illustrating an example of a configuration of a photon counting radiation detector according to one or more embodiments. InFIG.4,8denotes a control unit. The front electrode and the rear electrode of each cell is connected to the control unit8. A voltage is applied between the front electrode and the rear electrode of each cell by the control unit8. The X-rays passing through the test subject are incident on the epitaxial layer2of the cell structure1. Incident X-ray photons are absorbed by the epitaxial layer2. When X-ray photons are absorbed, carriers (electrons and holes) are generated in the epitaxial layer2. The electrons and holes move toward the front electrode and the rear electrode, respectively. This makes a current i flow between the control unit and the front electrode, and the control unit and the rear electrode, as illustrated inFIG.4. In other words, in the epitaxial layer2, the X-ray photons are directly converted into an electrical signal. The control unit8detects the magnitude of the current i. The magnitude of the current i is proportional to the number of X-ray photons passing through the test subject. In other words, by detecting the magnitude of the current i, the number of X-ray photons can be counted. Note that the direction of the voltage applied between the front electrode and the rear electrode and the current i can be changed as appropriate. The photon counting radiation detector preferably includes an array structure in which cell structures are arranged side by side in the lateral direction interposed by insulating spacers.FIG.5illustrates an example of an array structure. The array structure10has a structure in which a plurality of the cell structures1and a plurality of spacers6are alternately arranged side by side. The spacers6preferably have insulating properties. As illustrated inFIG.3, the cell structure1is provided with the front electrode4and the rear electrode5. As illustrated inFIG.4, the front electrode4and the rear electrode5of each of the cell structures1are connected to the control unit8. Providing insulating spacers allows for conduction between adjacent cell structures to be prevented. For example, the spacer6may be an insulating resin (including pressure-sensitive adhesives), an insulating film, or the like. Also, an adhesive layer with an insulating film on both sides, such as double-sided tape, may be used. The thickness of the spacer6is preferably 200 μm or less, and more preferably 100 μm or less. By making the thickness of the spacer6thin, the regions incapable of detection can be reduced and the spatial resolution can be increased. Note that the number of cell structures arranged side by side is a discretionary number. When the spacers6are provided, the thickness tsubof a single substrate corresponds to the sum of the thickness of a single substrate3, the thickness of a single front electrode4, the thickness of a single rear electrode5, and the thickness of a single spacer6. As illustrated inFIG.6, the photon counting radiation detector may have a structure in which the array structures10are stacked in the X-ray incident direction. By stacking the array structures10, which include the cell structures1arranged side by side in the lateral direction, in the X-ray incident direction, the amount of information able to be measured at one time can be increased. Also, for a structure including stacked array structures10, preferably X-rays are passed through the epitaxial layer2. Note that the size of the epitaxial layers2of the cell structures1forming the array structures10stacked vertically may be the same or may be different. In a similar manner, the inclination θ of the substrates may be the same or may be different. By having different sized epitaxial layers2or different inclinations θ, an X-ray transmission distance C can be different between the upper and lower cells. Also, when the array structures10are stacked, the upper and lower epitaxial layers may overlap or may not overlap. Note that the upper and lower epitaxial layers overlapping is indicative of a structure in which X-rays passing through the upper epitaxial layer2are capable of being detected at the lower epitaxial layer2. Also, even with a structure in which the array structures10are stacked in the X-ray incident direction, the inclinations θ of the substrates are preferably within the range of Formula (1). FIG.7illustrates another example of the array structure10. In this example, the X-rays are radially emitted from a light source toward a test subject. The X-rays passing through the test subject are incident on the cell structures1of the array structure10. With radially emitted X-rays, the X-ray incident angle is different for each cell structure. For example, the array structure10includes a cell structure1-1, a cell structure1-3, and a cell structure1-2located therebetween in the lateral direction. An incident direction DX1of X-rays for the cell structure1-1, an incident direction DX2of X-rays for the cell structure1-2, and an incident direction DX3of X-rays for the cell structure1-3are different from one another. In this case, inclinations θ1to θ3of the substrates of the cell structures1-1to1-3are set on the basis of the incident directions DX1to DX3of the X-rays. The inclinations θ1to θ3of the substrates of the cell structures1-1to1-3are set, with respect to the incident directions DX1to DX3of the X-rays, to satisfy Formula (1). The plurality of cell structures1may be arranged side by side in a straight line as illustrated inFIG.5or may be arranged side by side along a curve in the lateral direction as illustrated inFIG.7. Herein, the plurality of cell structures1being arranged side by side in the lateral direction includes in its meaning the example illustrated inFIG.5of the plurality of cell structures1being arranged side by side in a straight line in the lateral direction and the example of the plurality of cell structures1being arranged side by side along a curve in the lateral direction. FIG.8illustrates another example of the array structure10. As illustrated inFIG.8, the cell structures1may be arranged in two directions that intersect one another and are perpendicular to the incident direction DXof the X-rays. For example, the cell structures1are arranged in a first arrangement direction AD1and a second arrangement direction AD2orthogonal to one another and perpendicular to the incident direction DX. The plurality of cell structures1arranged side by side in the first arrangement direction AD1are arranged as illustrated inFIG.5orFIG.7, for example. The inclinations of the substrates of the cell structures1arranged in two directions preferably satisfy Formula (1). Also, the plurality of cell structures1arranged in two directions as illustrated inFIG.8may be stacked in the X-ray incident direction DXas illustrated inFIG.6. Also, the photon counting radiation detector according to one or more embodiments may be used in a radiation detector.FIG.9is a conceptual diagram of a radiation detector. In the diagram,8denotes a computer functioning as the control unit,10denotes the array structure,21denotes a test subject,22denotes an X-ray tube,24denotes a display,25denotes an image,20denotes an X-ray CT device (radiographic inspection device), and100denotes the photon counting radiation detector. An X-ray CT device, which is a type of radiographic inspection device, will now be described usingFIG.9. The X-ray CT device20is provided with the photon counting radiation detector100including the array structure10. In the array structure10, the cell structures1are arranged side by side along a curve in the lateral direction. The array structure10is attached to the inner wall of a cylindrical body in which the portion of the test subject21to be imaged is placed. The X-ray tube22that emits X-rays is disposed roughly in the center of the arc along which the array structure10is attached. The test subject21is fixed and placed between the array structure10and the X-ray tube22. The array structure10and the X-ray tube22are configured to rotate about the test subject21in a rotation direction23while X-ray imaging is performed. In the image processing of the test subject21, images are collected from different angles in a three-dimensional space. The signals obtained from the X-ray imaging (electrical signals obtained via conversion by the cell structure1) are processed by the computer8and displayed as the image25on the display24. The image25is a tomogram of the test subject21, for example. In the photon counting radiation detector100of one or more embodiments, the X-ray incident surface can be made smaller, allowing for higher resolution. This can dramatically increase the medical diagnostic capability of the X-ray CT device20. Also, the radiographic inspection device according to one or more embodiments is not limited to being applied to inspection devices for medical diagnosis and may also be applied to industrial X-ray non-destructive inspection devices. The radiographic inspection device according to one or more embodiments may also be used in detectors for radiation other than X-rays (for example, gamma rays). Next, a method for manufacturing the photon counting radiation detector100according to one or more embodiments will be described. The photon counting radiation detector100according to one or more embodiments is only required to have the configuration described above and is not limited in terms of the manufacturing method. However, an example of a method that can produce a good yield is given below. First, a substrate for forming an epitaxial layer is prepared. The substrate includes one type selected from SiC, Ga2O3, gallium arsenide (GaAs), gallium nitride (GaN), diamond, cadmium telluride (CdTe), IGZO, and a material having a perovskite crystal structure. Note that IGZO is a compound of indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The thickness tsubof the substrate preferably ranges from 10 μm to 700 μm, and more preferably ranges from 15 μm to 400 μm. Also, the substrate is preferably a single crystal substrate. The thickness of the single crystal substrate preferably ranges from 5 μm to 200 μm. The size of the substrate in terms of length and width is discretionary. A substrate larger than the substrate3constituting a cell structure is preferably used. Forming cell structures by cutting smaller substrates from larger substrates with epitaxial growth improves mass productivity. Also, this cutting process may be performed before providing the electrodes or after providing the electrodes. Furthermore, the purity of the substrate is preferably 99.0 wt % or greater. When the substrate has low purity, impurities are more likely to contaminate the epitaxial layer. Thus, the purity of the substrate is preferably 99.0 wt % or greater, and more preferably 99.9 wt % or greater. Also, the surface of the substrate is preferably a flat surface with a surface roughness Ra of 0.2 μm or less. Next, epitaxial growth on the substrate is performed to form the epitaxial layer. Epitaxial growth is a method of growing a crystal on a crystal substrate. A crystal can be grown in the same orientation as the crystal surface of the substrate (substrate used as a base). When the substrate is a single crystal, a single crystal epitaxial layer can also be obtained. Also, when the substrate and the epitaxial layer are the same material, the growth is called homoepitaxial growth. When the substrate and the epitaxial layer are different materials, the growth is called heteroepitaxial growth. Furthermore, methods of epitaxial growth include vapor-phase epitaxy, liquid-phase epitaxy, solid-phase epitaxy, molecular-beam epitaxy, and the like. Vapor-phase epitaxy is a method of depositing a component in the gas-phase on a substrate crystal surface. Vapor-phase epitaxy is also referred to as VPE or chemical vapor deposition (CVD). An example of a type of CVD includes mist CVD. Also, liquid-phase epitaxy is also referred to as LPE and is a method in which a crystal component is precipitated from a super saturated solution onto a substrate crystal surface. Solid-phase epitaxy is a method in which material deposited on a substrate crystal surface is heated by electron beam irradiation to change the structure of the material to the same crystal structure as the substrate crystal. Solid-phase epitaxy is also referred to as SPE. Also, molecular-beam epitaxy is a method in which an element for forming the target crystal or a material including the element is heated and evaporated in an ultra-high vacuum (from 10−3to 10−9Pa) and a crystal is deposited on a heated substrate crystal. Molecular-beam epitaxy is also referred to as MBE. Epitaxial growth is continued until the epitaxial layer reaches the target thickness. The grown epitaxial layer here corresponds to the epitaxial layer2. The thickness of the epitaxial layer2is preferably 100 μm or less, and more preferably ranges from 1 μm to 30 μm. After forming the epitaxial layer2, the thickness tsubof the substrate is adjusted as necessary. A thinner thickness tsubof the substrate allows the spatial resolution to be improved. Thus, the thickness tsubof the substrate preferably ranges from 5 μm to 500 μm, and more preferably ranges from 5 μm to 100 μm. Also, the thickness tsubof the substrate can be reduced by machining/finishing and etching. Next, the process of providing the electrodes is performed. The electrode material is preferably one type selected from a metal, a metal oxide, a metal carbide, and a metal silicide. Also, sputtering, chemical vapor deposition (CVD), ion plating, vapor deposition, thermal spraying, plating, and the like may be used as the film forming method. These film forming methods allow electrodes to be formed at discretionary locations. Also, the electrode may be formed on the entire front surface of the epitaxial layer2or may be formed on a portion of the front surface. Furthermore, a plurality of electrodes may be formed on the front surface of the epitaxial layer2. In a similar manner, the electrode provided on the rear surface of the substrate3may be formed on the entire rear surface or may be formed on a portion of the rear surface. A plurality of electrodes may be formed on the rear surface of the substrate3. Also, after an electrode is provided on the entire front surface of the epitaxial layer2or on the entire rear surface of the substrate3, the electrode may be patterned via etching. Heat treatment may be performed in addition as necessary. Also, heating may be performed during the film forming of the electrode. When the epitaxial layer2or the substrate3includes silicon carbide (SiC) or diamond, a metal carbide electrode or a metal silicide electrode is preferable. Among these, Mo2C, W, WC, or W2C is preferable. When the epitaxial layer2and the substrate3include a carbon component, a metal carbide electrode or a metal silicide electrode can be used to help prevent a reaction between the electrode and the epitaxial layer or between the electrode and the substrate. In this way, stable electrical characteristics can be obtained. Also, the cell structure can have a long service life. Also, when the epitaxial layer2or the substrate3includes gadolinium oxide (Ga2O3), gallium arsenide (GaAs), gallium nitride (GaN), or cadmium telluride (CdTe), a metal electrode or a metal oxide electrode is preferable. Among these, Pt, Ni, or TiO2is preferable. Also, the electrode may include titanium nitride (TiN). This can help suppress a reaction between the electrode and the epitaxial layer or between the electrode and the substrate. In the process of forming cell structures, smaller substrates are cut from larger substrates with epitaxial growth as necessary. The cell structures are completed via the process described above. Next, an array structure is manufactured by arranging the cell structures side by side. First, wiring is connected to the electrodes of each cell structure. Next, the cell structures are arranged side by side interposed by the spacers. Here, the cell structures are arranged with the inclination θ of the substrate satisfying Formula (1) with respect to the X-ray incident direction. The spacers preferably have insulating properties. The cell structures1are each provided with the front electrode4and the rear electrode5. Providing insulating spacers allows for conduction between adjacent cell structures to be prevented. For example, the spacer6may be an insulating resin (including pressure-sensitive adhesives) or an insulating film. Also, an adhesive layer with insulating film on both sides, such as double-sided tape, may be used. The thickness of the spacer is preferably 200 μm or less, and more preferably 100 μm or less. By making the thickness of the spacer thin, the regions incapable of detection can be reduced and the spatial resolution can be increased. Note that the number of cell structures arranged side by side is a discretionary number. Also, after the array structure is formed, the array structure may be resin-molded as necessary. Resin molding allows the strength of the array structure to be increased. EXAMPLES Examples 1 to 9, Comparative Example 1 SiC substrates according to Examples 1 to 3 were prepared. Epitaxial growth was performed on the SiC layer on the SiC substrate. For Examples 4 to 6, Ga2O3substrates were prepared. Epitaxial growth was performed on the Ga2O3layer on the Ga2O3substrate. For Examples 7 to 9, GaN substrates were prepared. Epitaxial growth was performed on the GaN layer on the GaN substrate. A single crystal was used for the SiC substrates, the Ga2O3substrates, and the GaN substrates. Thus, single crystal epitaxial layers were obtained. Also, the sizes of the substrates and the epitaxial layers are as listed in Table 1. Furthermore, the thickness tsubof the substrate is a thickness that includes the thickness of the electrodes and the insulating layer. TABLE 1Substrate (including insulatingEpitaxial layerlayer)ImpurityImpurityThicknessconcentrationThicknessconcentrationMaterialtepi(μm)(cm−3)Materialtsub(μm)(cm−3)Example 1SiC2<1015SiC3601018Example 2SiC5<1015SiC2001018Example 3SiC10<1015SiC1501018Example 4Ga2O32<1015Ga2O3501018Example 5Ga2O34<1015Ga2O31001018Example 6Ga2O38<1015Ga2O31501018Example 7GaN2<1015GaN501018Example 8GaN4<1015GaN1001018Example 9GaN8<1015GaN1501018 Next, for Examples 1 to 9, electrode layers were provided. The material of the electrode layers is as listed in Table 2. Note that the front electrode and the rear electrode have the same material, and the film thickness is 20 μm in all Examples. In this way, cell structures according to the Examples were manufactured. Also, an insulating layer ranging from 10 μm to 150 μm was used, this value being included in the thickness tsubof the substrate listed in Table 1. TABLE 2SampleElectrode materialExample 1-1Example 1WCExample 2-1Example 2TiCExample 2-2Example 2Mo2CExample 2-3Example 2WExample 2-4Example 2WCExample 2-5Example 2W2CExample 3-1Example 3WCExample 4-1Example 4TiNExample 5-1Example 5TiNExample 6-1Example 6NiExample 7-1Example 7PtExample 8-1Example 8NiExample 9-1Example 9Ni The I-V characteristics of the cell structures of Examples 2-1 to 2-5 were examined. The I-V characteristics were examined after heat treating the cell structures at temperatures of 500° C., 700° C., 800° C., 900° C., and 1000° C. in a nitrogen atmosphere for 1 minute. The I-V characteristics of Examples 2-1 to 2-5 are shown inFIGS.10to14. For the I-V characteristics shown inFIGS.10to14, the horizontal axis indicates voltage (V), and the vertical axis indicates current density (A/cm2). Also, inFIGS.10to14, asdepo indicates the characteristics of the unheat treated cell structure. The I-V characteristics shown inFIGS.10to14were used to examine for increases in the reverse leakage current at each temperature of the heat treatment. Large differences in the I-V characteristics graph at the different heat treatment temperatures indicate an increase in the reverse leakage current. Also, a large current density when the voltage is in the negative region indicates a large reverse leakage current. By comparingFIGS.10to14, it can be seen that the TiC electrode (FIG.10) has a strong tendency toward an increase in the reverse leakage current. Compared to this, the Mo2C electrode (FIG.11), the W electrode (FIG.12), the WC electrode (FIG.13), and the W2C electrode (FIG.14) have little reverse leakage current. This tells us that, in a cell structure using a SiC epitaxial layer or a SiC substrate, the electrode material is preferably one type selected from Mo2C, W, WC, and W2C. Also, cell structures using a Ga2O3epitaxial layer or a GaN epitaxial layer also followed this pattern. The cell structures were manufactured with the substrate lengths L listed in Table 3. Array structures were manufactured by arranged the cell structures side by side. Also, the length L of each cell are the values listed in Table 3. The sizes in terms of length and width are the same. Also, the inclination θ of each substrate of the array structures are the values listed in Table 3. Next, the inclination θ of the substrate of the cell structure with respect to the X-ray incident direction was changed, and X-ray detection was examined. When X-ray detection was examined, the presence of detection contamination was examined. The pixel size is also listed. The pixel size is found via (tsub+tepi)/cos θ). In the Examples, Mathematical Formula 1 is satisfied, but in the Comparative Examples, Formula (1) is not satisfied. In Table 3, configurations that satisfy Formula (1) are marked by “∘”, and configurations that do not satisfy Formula (1) are marked by “x”. The results are listed in Table 3. TABLE 3PixelCellSubstrateMathematicalInclination θ ofsizeDetectionstructurelength LFormula 1substrate (°)(μm)contaminationExample AExample 1-11cm∘50563NoExample BExample 1-11mm∘10368NoComparative Example AExample 1-11mmx40472YesExample CExample 2-11cm∘1205NoExample DExample 2-21mm∘1205NoExample EExample 2-31mm∘3205NoExample FExample 2-41mm∘5205NoExample GExample 2-51mm∘10208NoComparative Example BExample 2-21mmx25226YesExample HExample 3-11cm∘0.6160NoExample IExample 3-11mm∘6160NoComparative Example CExample 3-11cmx20170YesExample JExample 4-11cm∘0.352NoExample KExample 4-11mm∘252NoExample MExample 5-11cm∘1104NoExample NExample 5-11mm∘4104NoExample OExample 6-11cm∘1158NoExample PExample 6-11mm∘6159NoComparative Example DExample 6-11mmx20168YesExample QExample 7-11mm∘252NoExample RExample 8-11cm∘1104NoExample SExample 9-11mm∘6159NoComparative Example EExample 7-11mmx20168Yes Radiation detectors according to the embodiments described above exhibit excellent performance. In the Examples, due to Formula (1) being satisfied, no detection contamination in adjacent cell structures was found. Also, it can be seen that even in configurations with the same substrate length L, for example, Example B and Comparative Example A, when the inclination θ of the substrate satisfies Formula (1), the detection pixel can be made smaller. Thus, higher resolution can be achieved. Also, photon counting radiation detectors according to the Examples display good sensitivity due to the detection layer being an epitaxial layer. Furthermore, even when the pixel size is reduced to 1 mm (1000 μm) or less, X-ray photons can be detected. Photon counting radiation detectors according to the Examples are also capable of detecting a current of a few μA (microamperes) based on an X-ray photon. Furthermore, it was confirmed that increasing the inclination θ of the substrate increases the detection current. This is because the distance of the X-rays passing through the epitaxial layer is increased. Embodiments of the invention have been described above. However, these embodiments are presented as examples are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, modifications, and the like can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and spirit of the invention and are included within the scope and equivalents thereof set forth in the claims. Also, the embodiments described above can be combined with one another. θ≦tanθ≦L±L2-4tsub(tsub+tepi)2(tsub+tepi)(1)(L-tsubtanθ)sinθ=tsub+tepicosθ-(tsub+tepi)cosθ(2)L-tsubtanθ=(tsub+tepi)(1+tan2θtanθ-1tanθ)=(tsub+tepi)tanθ(3)0≦L2-4tsub(tsub+tepi)(4) TABLE 1Substrate (including insulatingEpitaxial layerlayer)ImpurityImpurityThicknessconcentrationThicknessconcentrationMaterialtepi(μm)(cm−3)Materialtsub(μm)(cm−3)Example 1SiC2<1015SiC3601018Example 2SiC5<1015SiC2001018Example 3SiC10<1015SiC1501018Example 4Ga2O32<1015Ga2O3501018Example 5Ga2O34<1015Ga2O31001018Example 6Ga2O38<1015Ga2O31501018Example 7GaN2<1015GaN501018Example 8GaN4<1015GaN1001018Example 9GaN8<1015GaN1501018 SampleElectrode materialExample 1-1Example 1WCExample 2-1Example 2TiCExample 2-2Example 2Mo2CExample 2-3Example 2WExample 2-4Example 2WCExample 2-5Example 2W2CExample 3-1Example 3WCExample 4-1Example 4TiNExample 5-1Example 5TiNExample 6-1Example 6NiExample 7-1Example 7PtExample 8-1Example 8NiExample 9-1Example 9Ni TABLE 3PixelCellSubstrateMathematicalInclination θ ofsizeDetectionstructurelength LFormula 1substrate (°)(μm)contaminationExample AExample 1-11cm∘50563NoExample BExample 1-11mm∘10368NoComparative Example AExample 1-11mmx40472YesExample CExample 2-11cm∘1205NoExample DExample 2-21mm∘1205NoExample EExample 2-31mm∘3205NoExample FExample 2-41mm∘5205NoExample GExample 2-51mm∘10208NoComparative Example BExample 2-21mmx25226YesExample HExample 3-11cm∘0.6160NoExample IExample 3-11mm∘6160NoComparative Example CExample 3-11cmx20170YesExample JExample 4-11cm∘0.352NoExample KExample 4-11mm∘252NoExample MExample 5-11cm∘1104NoExample NExample 5-11mm∘4104NoExample OExample 6-11cm∘1158NoExample PExample 6-11mm∘6159NoComparative Example DExample 6-11mmx20168YesExample QExample 7-11mm∘252NoExample RExample 8-11cm∘1104NoExample SExample 9-11mm∘6159NoComparative Example EExample 7-11mmx20168Yes | 43,664 |
11942491 | In order to help understand the present disclosure all drawing numerals appearing in the present disclosure are listed below:light sensing unit11base10red light sensing sub-unit111N type first semiconductor layer111aP type first semiconductor layer111bred light sensing layer111cgreen light sensing sub-unit112N type second semiconductor layer112aP type second semiconductor layer112bgreen light sensing layer112cblue light sensing sub-unit113N type third semiconductor layer113aP type third semiconductor layer113bblue light sensing layer113cGaN-based image sensor1substrate21light sensing processing circuit210metal interconnection layer22metal interconnection structure220display apparatus2,2′display drive circuit30 DETAILED DESCRIPTION OF THE EMBODIMENTS In order to make the above objects, features and advantages of the present disclosure clear and understandable, the specific embodiments of the present disclosure will be described in detail below in combination with the accompanying drawings. FIG.1is a schematic diagram illustrating a sectional structure of a light sensing unit according to a first embodiment of the present disclosure. With reference toFIG.1, the light sensing unit11includes:a red light sensing sub-unit111, a green light sensing sub-unit112and a blue light sensing sub-unit113; where materials of a red light sensing layer111cof the red light sensing sub-unit111, a green light sensing layer112cof the green light sensing sub-unit112, and a blue light sensing layer113cof the blue light sensing sub-unit113are all gallium nitride(GaN)-based materials containing indium(In); the materials of the red light sensing layer111c, the green light sensing layer112cand the blue light sensing layer113ccontain different contents or amounts of In, such that the corresponding red light sensing sub-unit111, green light sensing sub-unit112and blue light sensing sub-unit113are enabled to generate or not generate light sensing electrical signals in response to different wave lengths of received lights. The content of In of the red light sensing layer111cmay be greater than the content of In of the green light sensing layer112c, and the content of In of the green light sensing layer112cmay be greater than the content of In of the blue light sensing layer113c. In this embodiment, as shown inFIG.1, the light sensing unit11is formed on a base10. Before the epitaxial growth of the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113, a mask layer may be formed on the base10. The mask layer has three openings respectively corresponding to one light sensing unit111, and the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113correspond to one opening, respectively. The opening corresponding to the red light sensing sub-unit111is smaller than the opening corresponding to the green light sensing sub-unit112, and the opening corresponding to the green light sensing sub-unit112is smaller than the opening corresponding to the blue light sensing sub-unit113. Due to different sizes of the openings, a reactant gas has different flow rates in different openings during growth of the light sensing layers, and thus element In and element Ga have different doping rates, that is, due to different doping rates of the element In, the component In has different proportions in the grown light sensing layers. Specifically, the smaller the opening is, the faster the basic material GaN of the light sensing layer in the opening will grow, and hence, the doping of the element In has better selectivity and the doping rate of the In element is further larger than the doping rate of the element Ga. As a result, the smaller the opening is, the higher the content of element In in the light sensing layer indium gallium nitride (InGaN) is. The material of the base10may be sapphire, silicon carbide, silicon, GaN, aluminium nitride (AlN) or diamond or the like. The content of In in the red light sensing layer111cmay be in a range of 0.4-0.6, and the wave length of light required for generating light sensing electrical current may be in a range of 400 nm-720 nm. The content of In in the green light sensing layer112cmay be in a range of 0.2-0.3, and the wave length of light required for generating light sensing electrical current may be in a range of 400 nm-600 nm. The content of In in the blue light sensing layer113cmay be in a range of 0.01-0.1, and the wave length of light required for generating light sensing electrical current may be in a range of 400 nm-500 nm. It is noted that, the content of In in the red light sensing layer111crefers to a percentage of the amount of the substance of In to a sum of the amounts of the substances of all positively-charged elements in the red light sensing layer111c. For example, if the material of the red light sensing layer111cis InGaN, the content of In refers to a percentage of the amount of the substance of In to a sum of the amount of the substance of In and the amount of the substance of Ga; and if the material of the red light sensing layer111cis indium aluminium gallium nitride (InAlGaN) and the content of In refers to a percentage of the amount of the substance of In to a sum of the amount of the substance of In, the amount of the substance of Al and the amount of the substance of Ga. The content of In in the green light sensing layer112crefers to a percentage of the amount of the substance of In to a sum of the amounts of the substances of all positively-charged elements in the green light sensing layer112c. The content of In in the blue light sensing layer113crefers to a percentage of the amount of the substance of In to a sum of the amounts of the substances of all positively-charged elements in the blue light sensing layer113c. Furthermore, in this embodiment, each value range includes endpoint values. Therefore, in a case of blue light irradiation, the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113each can generate light sensing electrical signals. In a case of green light irradiation, the red light sensing sub-unit111and the green light sensing sub-unit112can generate light sensing electrical signals. In a case of red light irradiation, only the red light sensing sub-unit111can generate light sensing electrical signals. In this embodiment, at least one of the red light sensing layer111c, the green light sensing layer112c, or the blue light sensing layer113cis a single layer structure. In other embodiments, at least one of the red light sensing layer111c, the green light sensing layer112c, or the blue light sensing layer113cmay also be a layer-stacked structure, for example, a multiple quantum well layer, including two barrier layers and a potential well layer sandwiched between the two barrier layers. In this embodiment, as shown inFIG.1, the red light sensing sub-unit111includes an N type first semiconductor layer111aand a P type first semiconductor layer111b, and the N type first semiconductor layer111aand the P type first semiconductor layer111bare located at both sides of the red light sensing layer111crespectively; the green light sensing sub-unit112includes an N type second semiconductor layer112aand a P type second semiconductor layer112b, and the N type second semiconductor layer112aand the P type second semiconductor layer112bare located at both sides of the green light sensing layer112crespectively; the blue light sensing sub-unit113includes an N type third semiconductor layer113aand a P type third semiconductor layer113b, and the N type third semiconductor layer113aand the P type third semiconductor layer113bare located at both sides of the blue light sensing layer113crespectively. Any two of the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113aare disconnected and any two of the P type first semiconductor layer111b, the P type second semiconductor layer112band the P type third semiconductor layer113bare disconnected. In other embodiments, the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113amay also be connected together, or the P type first semiconductor layer111b, the P type second semiconductor layer112band the P type third semiconductor layer113bare connected together. In other embodiments, the P type first semiconductor layer111b, the P type second semiconductor layer112band the P type third semiconductor layer113bmay also be close to the base10, and the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113aare away from the base10. The material of at least one of the N type first semiconductor layer111a, the N type second semiconductor layer112aor the N type third semiconductor layer113amay be N type GaN; the material of at least one of the P type first semiconductor layer111b, the P type second semiconductor layer112bor the P type third semiconductor layer113bmay be P type GaN or P type InGaN. Based on the light sensing unit11described above, the first embodiment of the present disclosure further provides a GaN-based image sensor.FIG.2is a schematic cross-sectional structure diagram illustrating a GaN-based image sensor. As shown inFIG.2, the GaN-based image sensor1includes:a base21, including a light sensing processing circuit210;a metal interconnection layer22, located on a surface of the substrate21and internally provided with a metal interconnection structure220; anda plurality of above light sensing units11, located on the metal interconnection layer22, where the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113are electrically connected to the light sensing processing circuit210through the metal interconnection structure220to obtain a blue light incidence signal, a green light incidence signal and a red light incidence signal. The light sensing processing circuit210may include a plurality of transistors on the base10. In this embodiment, since any two of the N type first semiconductor layer111a, the N type second semiconductor layer112a, the N type third semiconductor layer113aare disconnected, that is, after the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113generate light sensing electrical currents due to light irradiation, the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113amay have unequal potentials. Therefore, the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113amay be connected to the metal interconnection structure220. In other embodiments, when the N type first semiconductor layer111a, the N type second semiconductor layer112aand the N type third semiconductor layer113aare connected together, and any two of the P type first semiconductor layer111b, the P type second semiconductor layer112band the P type third semiconductor layer113bare disconnected, the P type first semiconductor layer111b, the P type second semiconductor layer112band the P type third semiconductor layer113bmay be connected to the metal interconnection structure220. The light sensing processing circuit210detects light sensing electrical signals generated by the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113. Specifically, if the light sensing processing circuit210detects light sensing electrical signals at each of the red light sensing sub-unit111, the green light sensing sub-unit112and the blue light sensing sub-unit113in one light sensing unit11, a blue light incidence signal is stored;if the light sensing processing circuit210detects light sensing electrical signals only at each of the red light sensing sub-unit111and the green light sensing sub-unit112in one light sensing unit11, a green light incidence signal is stored;if the light sensing processing circuit210detects light sensing electrical signals only at the red light sensing sub-unit111in one light sensing unit11, a red light incidence signal is stored. FIG.3is a modular structural diagram illustrating a display apparatus according to a second embodiment of the present disclosure. Based on the GaN-based image sensor of the first embodiment, the second embodiment of the present disclosure further provides a display apparatus. As shown inFIG.3, the display apparatus2includes:a GaN-based image sensor1;a display drive circuit30, where an input end of the display drive circuit30receives a red light incidence signal, a green light incidence signal and a blue light incidence signal of the light sensing unit11in a first region from the light sensing processing circuit210, and generates a corresponding red display drive signal, a corresponding green display drive signal and a corresponding blue display drive signal;an output end of the display drive circuit30is connected with the metal interconnection structure220, and the red display drive signal, the green display drive signal and the blue display drive signal are transmitted to a red light-emitting sub-unit, a green light-emitting sub-unit and a blue light-emitting sub-unit in a second region through the metal interconnection structure220; where, the red light-emitting sub-unit is the red light sensing sub-unit111, the green light-emitting sub-unit is the green light sensing sub-unit112and the blue light-emitting sub-unit is the blue light sensing sub-unit113. In the display apparatus2of the present embodiment, the GaN-based image sensor1can not only achieve light sensing function but also realize display function. The display apparatus2, for example, may realize a true full screen display (full view display) and achieve light sensing function through light-emitting units without disposing one or more cameras and regions in the display screen for disposing the one or more cameras. When the light sensing unit11in the first region senses light, the metal interconnection structure220is connected with the light sensing processing circuit210and disconnected with the display drive circuit30, and the GaN-based image sensor1achieves light sensing function; when the light-emitting units in the second region perform displaying, the metal interconnection structure220is disconnected with the light sensing processing circuit210and connected with the display drive circuit30, and the GaN-based image sensor1achieves display function. Since the metal interconnection structure220has two states, the light sensing function and the display function can be carried out in a time-sharing manner. For example, in one frame of refresh period, the light sensing function is achieved in the former part of the period, that is, image collection is carried out; the display function is achieved in the latter part of the period, that is, the collected image is displayed. As shown inFIG.3, in this embodiment, the first region and the second region are a same region. In other words, after light is irradiated on the light sensing unit11, the red light sensing sub-unit111in the light sensing unit11generates a red light incidence signal, the red light incidence signal passes the display drive circuit30to generate a corresponding red display drive signal, the red display drive signal is displayed on the same red light sensing sub-unit111. The green light sensing sub-unit112and the blue light sensing sub-unit113operate in the similar way. The first region and the second region may be all or part of a display region of the display apparatus. For example, a picture taken by a user is displayed across a full screen or in a window. FIG.4is a modular structure diagram illustrating a display apparatus according to a third embodiment of the present disclosure. As shown inFIG.4, the display apparatus2′ in this embodiment is substantially same as the display apparatus2of the second embodiment, except that the first region and the second region are different. In other words, the light sensing unit11and the light-emitting unit are different. Image data can be processed such that the first region has a larger area than the second region or the first region has a smaller area than the second region. In some embodiments, the first region and the second region may also be partially overlapped. Although the present disclosure is described as above, the present disclosure is not limited hereto. Various modification and changes may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. Thus, the scope of protection of the present disclosure shall be limited by the appended claims. | 16,930 |
11942492 | DETAILED DESCRIPTION This patent document provides implementations and examples of an image sensing device and the disclosed features may be implemented to achieve one or more advantages in more applications. Some implementations of the disclosed technology suggest designs of an image sensing device which can reduce power consumption needed for sensing, and at the same time can improve depth characteristics. Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts. In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter. In order to acquire a three-dimensional (3D) image using the image sensor, color information of the 3D image and the distance (or depth) between a target object and the image sensor are needed. Methods for measuring depth information about a target object using one or more image sensors include a triangulation method and a time of flight (TOF) method. Among these depth measurement methods, the TOF method is being widely used because of its wide range of applications, a high processing speed, and a cost efficiency. In some implementations, the TOF method measures a distance using light emitted from the light source and light reflected from the object. The TOF method may be classified into two different types, a direct method and an indirect method, depending on whether a round-trip time or a phase difference of light is used to determine the distance between the TOF sensor and an object. The direct method may calculate a round trip time using emitted light and reflected light and measure the distance between the TOF sensor and a target object (i.e., depth) using the round-trip time. The indirect method may measure the distance between the TOF sensor and the target object using a phase difference. The direct method is used to measure a longer distance and thus is widely used in automobiles. The indirect method is used to measure a shorter distance and thus is used for a game machine or a mobile camera that is used at a shorter distance and requires a faster processing speed. The indirect TOF sensor can be implemented using a simple circuit at a low cost. In some implementations, the indirect ToF sensor may utilize a current-assisted photonic demodulator (CAPD) structure for detecting electrons that have been generated in a substrate using a hole current acquired by applying a voltage to the substrate, such that the CAPD structure can more quickly detect electrons. In addition, the CAPD can detect electrons formed at a deep depth in the substrate. FIG.1is a block diagram illustrating an example of an image sensing device ISD based on some implementations of the disclosed technology. Referring toFIG.1, the image sensing device ISD may measure the distance between the image sensing device ISD and a target object1using the indirect Time of Flight (TOF) method. The TOF method based on some implementations may be a direct TOF method or an indirect TOF method. The indirect TOF method may measure the distance between the image sensing device ISD and the target object1by emitting modulated light to the target object1, sensing light reflected from the target object1, and calculating a phase difference between the modulated light and the reflected light. The image sensing device ISD may include a light source10, a lens module20, a pixel array30, and a control block40. The light source10may emit light to a target object1upon receiving a modulated light signal (MLS) from the control block40. The light source10may be a laser diode (LD) or a light emitting diode (LED) for emitting light (e.g., near infrared (NIR) light, infrared (IR) light or visible light) having a specific wavelength band, or may be any one of a Near Infrared Laser (NIR), a point light source, a monochromatic light source combined with a white lamp or a monochromator, and a combination of other laser sources. For example, the light source10may emit infrared light having a wavelength of 800 nm to 1000 nm. AlthoughFIG.1shows only one light source10by way of example, a plurality of light sources may also be arranged in the vicinity of the lens module20. The lens module20may collect light reflected from the target object1, and may allow the collected light to be focused onto pixels (PXs) of the pixel array30. For example, the lens module20may include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module20may include a plurality of lenses that is arranged to focus light to an optical axis. The pixel array30may include unit pixels (PXs) consecutively arranged in rows and columns in a two-dimensional (2D) matrix array. The unit pixels (PXs) may be formed over a semiconductor substrate. Each unit pixel (PX) may convert incident light received through the lens module20into an electrical signal corresponding to the amount of incident light rays, and may thus output a pixel signal using the electrical signal. In some implementations, the pixel signal may indicate the distance between the image sensing device ISD and the target object1. For example, each unit pixel (PX) may be a current-assisted photonic demodulator (CAPD) pixel for capturing photocharges generated in a semiconductor substrate by incident light using a difference between electric potential levels of an electric field. The structure and operations of each unit pixel (PX) will hereinafter be described with reference to the drawings fromFIG.2. The control block40may emit light to the target object1by controlling the light source10. Upon receipt of the reflected light from the target object1, the control block40may process each pixel signal corresponding to light reflected from the target object1by operating unit pixels (PXs) of the pixel array30and measure the distance between the image sensing device ISD and the surface of the target object1based on the pixel signal. The control block40may include a row driver41, a demodulation driver42, a light source driver43, a timing controller (T/C)44, and a readout circuit45. In some implementations, the image sensing device ISD may include a control circuit such as the row driver41and the demodulation driver42. The control circuit may activate unit pixels (PXs) of the pixel array30in response to a timing signal generated from the timing controller44. The control circuit may generate a control signal that is used to select and control at least one row from among the plurality of rows in the pixel array30. In some implementations, the control signal may include a demodulation control signal for generating a pixel current in the substrate, a reset signal for controlling a reset transistor, a transmission signal for controlling transmission of photocharges accumulated in a detection node, a floating diffusion signal for providing additional electrostatic capacity at a high illuminance level, a selection signal for controlling a selection transistor. The pixel current may include a current for moving photocharges generated by the substrate to the detection node. In this case, the row driver41may generate a reset signal, a transmission signal, a floating diffusion signal, and a selection signal, and the demodulation driver42may generate a demodulation control signal. In some implementations, the row driver41and the demodulation driver42may be separate elements. In other implementations, the row driver41and the demodulation driver42may be incorporated into a single element disposed at one side of the pixel array30. The light source driver43may generate a modulated light signal MLS that is used to operate the light source10in response to a control signal from the timing controller44. The modulated light signal MLS may be a signal that is modulated at a predetermined frequency. The timing controller44may generate a timing signal to control the row driver41, the demodulation driver42, the light source driver43, and the readout circuit45. The readout circuit45may process pixel signals received from the pixel array30based on the timing signal or other control signals provided by the timing controller44, and may generate pixel data by converting analog pixel signals to digital signals. To this end, the readout circuit45may include a correlated double sampler (CDS) circuit for performing correlated double sampling (CDS) on the pixel signals generated by the pixel array30. In addition, the readout circuit45may include an analog-to-digital converter (ADC) for converting output signals of the CDS circuit into digital signals. In addition, the readout circuit45may include a buffer circuit that temporarily stores pixel data generated from the analog-to-digital converter (ADC) and outputs the pixel data based on the timing signal or other control signals provided by the timing controller44. In some implementations, the pixel array30includes current-assisted photonic demodulator (CAPD) pixels. Therefore, two column signal lines for transmitting the pixel signal may be assigned to each column of the pixel array30, and circuitry for processing the pixel signal generated from each column line may correspond to the respective column lines. The light source10may emit light (i.e., modulated light) modulated at a predetermined frequency toward an object or scene (e.g., target objects1) captured by the image sensing device ISD. The image sensing device ISD may sense modulated light (i.e., incident light) reflected from the target objects1included in the scene, and may thus generate depth information for each unit pixel (PX). A time delay between the modulated light and the incident light is determined based on the distance between the image sensing device ISD and each target object1. The time delay may be determined based on a phase difference between the signal generated by the image sensing device ISD and the light modulation signal MLS controlling the light source10. An image processor (not shown) may calculate a phase difference generated in the output signal of the image sensing device ISD, and may thus generate a depth image including depth information for each unit pixel (PX). FIG.2is a schematic diagram illustrating an example layout of a unit pixel included in the pixel array30shown inFIG.1based on some implementations of the disclosed technology. Referring toFIG.2, the unit pixel PX may be any one of the plurality of pixels (PXs) shown inFIG.1.FIG.2illustrates only one unit pixel PX by way of example, and other pixels PXs in the pixel array30may have the same structure and operate in the same way as the unit pixel PX illustrated inFIG.2. The unit pixel PX may include a photoelectric conversion region100and a circuit region200. The photoelectric conversion region100may include a first tap TA (or a first demodulation node) and a second tap TB (or a second demodulation node) that are formed in a semiconductor substrate. AlthoughFIG.2shows the photoelectric conversion region100of a unit pixel PX as including two taps TA and TB, a unit pixel PX may include three or more taps. In some implementations, the plurality of taps may receive the same demodulation control signal. In other implementations, the plurality of taps may receive demodulation control signals that have different phases and/or timings. AlthoughFIG.2shows the first tap TA and the second tap TB as being arranged in a Y-axis direction (or a column direction), the first tap TA and the second tap TB can also be arranged in an X-axis direction (or a row direction) or in a diagonal direction. The first tap TA may include a first control node CNA and a first detection node DNA surrounding the first control node CNA. In some implementations, as illustrated inFIG.2, the first control node CNA may have an octagonal shape and the first detection node DNA is structured to surround the octagonal first control node CNA. In other implementations, the first control node CNA may have any shape that allows the first detection node DNA to surround the first control node CNA. The annular-shaped structure structured to surround the first control node CNA allows the first detection node DNA to have a large inner surface facing the first control node CNA. In this way, the first detection node DNA can more easily capture charge carriers moving along a pixel current formed by the first control node CNA. In other implementations, the first detection node DNA may not be formed in a single annular shape completely surround the first control node CNA, and may be formed in a manner that a plurality of elements separated each other surround the first control node CNA. The second tap TB may include a second control node CNB and a second detection node DNB surrounding the second control node CNB. The second control node CNB and the second detection node DNB may correspond to the first control node CNA and the first detection node DNA, respectively. The first and second control nodes CNA and CNB and the first and second detection nodes DNA and DNB may be formed in the substrate. For example, each of the first and second control nodes CNA and CNB may be a P-type impurity region, and each of the first and second detection nodes DNA and DNB may be an N-type impurity region. The first control node CNA and the first detection node DNA may be spaced apart from each other by a predetermined distance corresponding to the width of a device isolation layer (ISO) that is structured to physically isolate the first control node CNA from the first detection node DNA. In addition, the second control node CNB and the second detection node DNB can also be isolated from each other by the device isolation layer (ISO). The device isolation layer (ISO) may include a shallow trench isolation (STI) structure formed by filling, with insulation materials, a trench formed by etching the substrate to a predetermined depth. The first tap TA and the second tap TB may also be spaced apart from each other by the device isolation layer (ISO). The circuit region200may be disposed at one side of the photoelectric conversion region100. The circuit region200may include a plurality of pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B for generating a pixel signal corresponding to charge carriers captured by the detection nodes DNA and DNB. The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may generate a pixel signal corresponding to charge carriers captured by the first detection node DNA, and may output the pixel signal. The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may be disposed near the first tap TA. The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may generate a pixel signal corresponding to charge carriers captured by the second detection node DNB. The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may be disposed near the second tap TB. The pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be arranged in the circuit region200. In one example, the circuit region200may extend in one direction (e.g., Y direction as shown inFIG.2). In this case, the pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A for the first tap TA and the pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B for the second tap TB may be arranged symmetrically to each other as shown inFIG.2. A contact for applying a bias voltage VSS to a well region may be formed between the pixel transistors SX_A and FDX_A, and another contact for applying a bias voltage VSS to a well region may be formed between the pixel transistors SX_B and FDX_B. Here, the contact may include any type of structure with a gap filled with a conductive material. The pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be formed in an active region ACT. The active region ACT may be isolated from the taps TA and TB by the device isolation layer (ISO). The active region ACT may be formed over the entirety of the circuit region200. For example, the active region ACT may be formed in a line shape extending in a Y-axis direction over the entirety of the circuit region200. Each of gate terminals of the pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may have a narrower width in X direction than the active region ACT. In the circuit region200, a well (e.g., P-well) region may be formed in a manner that a width of an upper region of the well is different from a width of a lower region of the well. For example, the well (P-well) region may be formed in a manner that a width (i.e., width in X direction) of a well region formed below the active region ACT is smaller than that of a well region formed in the active region ACT. FIG.3is a diagram illustrating an example circuit of the unit pixel shown inFIG.2based on some implementations of the disclosed technology. InFIG.3, the photoelectric conversion region100shows a cross-sectional view of the photoelectric conversion region taken along the line A-A′ shown inFIG.2. The circuit region200shows the circuit diagram of the pixel transistors. Referring toFIG.3, the first control node CNA may receive a first demodulation control signal (CSa) from the demodulation driver42, and the second control node CNB may receive a second demodulation control signal (CSb) from the demodulation driver42. A voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may generate a pixel current (PC) that can be used to control the flow of charge carriers that are generated in the substrate by incident light. For example, when the first demodulation control signal (CSa) has a higher voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the first control node CNA to the second control node CNB. In contrast, when the first demodulation control signal (CSa) has a lower voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the second control node CNB to the first control node CNA. Each of the first detection node DNA and the second detection node DNB may capture charge carriers moving along the flow of the pixel current PC, and may accumulate the captured charge carriers. The photocharge can be captured in the photoelectric conversion region100during a first period and a second period that follows the first period. In the first period, light incident upon the pixel PX may be converted into electron-hole pairs in the substrate. In some implementations, the photocharge may include such photo-generated electrons. In some implementations, the demodulation driver42may supply a first demodulation control signal (CSa) to the first control node CNA, and may supply a second demodulation control signal (CSb) to the second control node CNB. In one example, the first demodulation control signal (CSa) may have a higher voltage than the second demodulation control signal (CSb). Here, the voltage of the first demodulation control signal (CSa) may be defined as an active voltage or an activation voltage, and the voltage of the second demodulation control signal (CSb) may be defined as an inactive voltage or a deactivation voltage. For example, the voltage of the first demodulation control signal (CSa) may be set to 1.2 V, and the voltage of the second demodulation control signal (CSb) may be 0 V. A voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, and thus the pixel current PC may flow from the first control node CNA to the second control node CNB. That is, holes in the substrate may move toward the second control node CNB, and electrons in the substrate may move toward the first control node CNA. Electrons moving toward the first control node CNA may be captured by the first detection node DNA adjacent to the first control node CNA. Therefore, electrons in the substrate may be used as charge carriers for detecting the intensity of incident light. In the second period, light incident upon the pixel PX may be converted into electron-hole pairs. In some implementations, the demodulation driver42may supply the first demodulation control signal (CSa) to the first control node CNA, and may supply the second demodulation control signal (CSb) to the second control node CNB. In one example, the first demodulation control signal (CSa) may have a lower voltage than the second demodulation control signal (CSb). Here, the voltage of the first demodulation control signal (CSa) may be defined as an inactive voltage or deactivation voltage, and the voltage of the second demodulation control signal (CSb) may be defined as an active voltage or activation voltage. For example, the voltage of the first demodulation control signal (CSa) may be 0 V, and the voltage of the second demodulation control signal (CSb) may be set to 1.2 V. A voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, and the pixel current PC may flow from the second control node CNB to the first control node CNA. That is, holes in the substrate may move toward the first control node CNA, and electrons in the substrate may move toward the second control node CNB. Electrons moving toward the second control node CNB may be captured by the second detection node DNB adjacent to the second control node CNB. Therefore, electrons in the substrate may be used as charge carriers for detecting the intensity of incident light. In other implementations, the sequence of the first and second periods may vary, and thus the first period may follow the second period. The circuit region200may include a plurality of elements (pixel transistors) DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B structured to convert photocharges captured by the first and second detection nodes DNA and DNB into electrical signals. The circuit region200may further include interconnects such as metal lines structured to carry electrical signals between the elements DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B. Control signals RST, TRG, FDG, and SEL may be supplied from the row driver41to the circuit region200. In addition, a pixel voltage (Vpx) may be a power-supply voltage (VDD). The photocharges captured by the first detection node DNA may be converted into electrical signals as will discussed below. The circuit region200may include a reset transistor RX_A, a transfer transistor TX_A, a first capacitor C1_A, a second capacitor C2_A, a floating diffusion transistor FDX_A, a drive transistor DX_A, and a selection transistor SX_A. The reset transistor RX_A may be activated to enter an active state in response to a logic high level of the reset signal RST supplied to a gate electrode thereof, such that the voltage of the floating diffusion node FD_A and the voltage of the first detection node DNA may be reset to the pixel voltage (Vpx) level. In addition, when the reset transistor RX_A is activated (i.e., active state), the transfer transistor TX_A can also be activated (i.e., active state) to reset the floating diffusion node FD_A. The transfer transistor TX_A may be activated (i.e., active state) in response to a logic high level of the transfer signal TRG supplied to a gate electrode thereof, such that electrical charges accumulated in the first detection node DNA can be transmitted to the floating diffusion node FD_A. The first capacitor C1_A may be coupled to the floating diffusion node FD_A, such that the first capacitor C1_A can provide predefined electrostatic capacity to the floating diffusion node FD_A. The second capacitor C2_A may be selectively coupled to the floating diffusion node FD_A based on the operations of the floating diffusion (FD) transistor FDX_A, such that the second capacitor C2_A can provide additional predefined electrostatic capacity to the floating diffusion node FD_A. Each of the first capacitor C1_A and the second capacitor C2_A may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor. The floating diffusion transistor FDX_A may be activated in response to a logic high level of the floating diffusion signal FDG supplied to a gate electrode thereof, such that the floating diffusion transistor FDX_A may couple the second capacitor C2_A to the floating diffusion node FD_A. For example, the row driver41may turn on (or activate) the floating diffusion transistor FDX_A when the intensity of incident light satisfies a predetermined high illuminance condition, such that the floating diffusion transistor FDX_A enters the active state and the floating diffusion node FD_A can be coupled to the second capacitor C2_A. As a result, when the incident light is at a high illuminance level, the photocharge accumulated at the floating diffusion node FD_A increases, accomplishing a high dynamic range (HDR). On the other hand, when the incident light is at a relatively low illuminance level, the row driver41may turn off (or deactivate) the floating diffusion transistor FDX_A, such that the floating diffusion node FD_A can be isolated from the second capacitor C2_A. In some other implementations, the floating diffusion transistor FDX_A and the second capacitor C2_A may be omitted as necessary. A drain electrode of the drive transistor DX_A is coupled to the pixel voltage (Vpx) and a source electrode of the drive transistor DX_A is coupled to a vertical signal line SL_A through the selection transistor SX_A. A gate electrode of the drive transistor DX_A is coupled to the floating diffusion node FD_A, such that the drive transistor DX_A may operate as a source follower transistor for outputting a current (pixel signal) corresponding to potential of the floating diffusion node FD_A. The selection transistor SX_A may be activated (i.e., active state) in response to a logic high level of the selection signal SEL supplied to a gate electrode thereof, such that the pixel signal generated from the drive transistor DX_A can be output to the vertical signal line SL_A. In order to process photocharges captured by the second detection node DNB, the circuit region200may include a reset transistor RX_B, a transfer transistor TX_B, a first capacitor C1_B, a second capacitor C2_B, a floating diffusion transistor FDX_B, a drive transistor DX_B, and a selection transistor SX_B. The operation timing of elements for processing photocharges captured by the second detection node DNB is different from that of the elements for processing photocharges captured by the first detection node DNA. However, the elements for processing photocharges captured by the second detection node DNB may be similar or identical to the elements for processing photocharges captured by the first detection node DNA. The pixel signal transferred from the circuit region200to the vertical signal lines SL_A and the pixel signal transferred from the circuit region200to the vertical signal line SL_B may be processed using a noise cancellation technique and analog-to-digital (ADC) conversion processing to convert the pixel signals into image data. Although each of the reset signal RST, the transmission signal TRG, the floating diffusion signal FDG, and the selection signal SEL shown inFIG.3is supplied to the circuit region200through one signal line, each of the reset signal RST, the transmission signal TRG, the floating diffusion signal FDG, and the selection signal SEL can be supplied to the circuit region200through a plurality of signal lines (e.g., two signal lines), such that elements for processing photocharges captured by the first detection node DNA and the other elements for processing photocharges captured by the second detection node DNB can operate at different timings. The image processor (not shown) may process the image data acquired from photocharges captured by the first detection node DNA and the image data acquired from photocharges captured by the second detection node DNB to produce a phase difference using the image data. The image processor may calculate depth information indicating the distance between the image sensor pixels and the target object1based on a phase difference corresponding to each pixel, and may generate a depth image including depth information corresponding to each pixel. FIG.4Ais a cross-sectional view illustrating an example of the unit pixel taken along the line B-B′ shown inFIG.2based on some implementations of the disclosed technology.FIG.4Bis a cross-sectional view illustrating an example of the unit pixel taken along the line C-C′ shown inFIG.2based on some implementations of the disclosed technology. Referring toFIGS.4A and4B, in the photoelectric conversion region100, the first control node CNA may include P-type impurity regions (e.g., P−region and P+region) having different doping concentrations. For example, the P-type impurity region (e.g., P−region) having a relatively low doping concentration may be formed in the substrate310to a first depth, and the P-type impurity region (e.g., P+region) having a relatively high doping concentration may be formed in the substrate310to a second depth less than the first depth at the same position as the above P−-type impurity implantation position. In this case, the first depth may be greater than the second depth. The first detection node DNA may have N-type impurity regions (e.g., N−region and N+region) having different doping concentrations. For example, the N-type impurity region (e.g., N−region) having a relatively low doping concentration may be implanted into the substrate310to a first depth, and the N-type impurity region (e.g., N+region) having a relatively high doping concentration may be implanted into the substrate310to a second depth less than the first depth at the same position as the above N−-type impurity implantation position. In this case, the depth of the P−-type impurity region of the first control node CNA may be greater than the depth of the N−-type impurity region of the first detection node DNA, thereby facilitating flow of the pixel current PC. AlthoughFIG.4Aillustrates only the first tap TA, the second control node CNB and the second detection node DNB of the second tap TB may have the same structures as the first control node CNA and the first detection node DNA of the first tap TA, respectively. In the circuit region200, the well region320may include an upper well region320U and a lower well region320D having different X-directional widths. In some implementations, the upper well region320U may be formed over the entirety of the active region ACT. Impurity regions such as source/drain regions (S/D) of the pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be formed in the upper well region320U. The upper well region320U may include P-type (P−) impurities. The lower well region320D may be formed below the active region ACT so that the lower well region320D can be in contact with a bottom surface of the upper well region320U. For example, the lower well region320D may be formed to protrude downward from the bottom surface of the upper well region320, such that a top surface of the lower well region320D is in contact with the bottom surface of the upper well region320U. In some implementations, the depth of the lower well region320D may be less than the depth of each of the control nodes CNA and CNB. The lower well region320D may include P-type (P−) impurities having the same doping concentration as the upper well region320U. In addition, the width (length in X direction) of the lower well region320D may be less than the width of the upper well region320U. For example, the lower well region320D may be formed to extend in the Y direction such that the Y-directional length of the extended lower well region320D is similar or identical to that of the upper well region320U, the width (length in X direction) of the extended lower well region320D is less than that of the upper well region320U. In some implementations, the Y-directional length of each of the upper well region320U and the lower well region320D may be identical to that of the circuit region200of the corresponding unit pixel. In a conventional circuit region formed to include pixel transistors, a region formed below the active region from among the well region may extend to a lower portion of a device isolation layer (ISO) in a manner that both sides of the region vertically overlap with the device isolation layer (ISO) of the photoelectric conversion region, and the region formed below the active region may also extend in a downward direction. However, in some implementations of the disclosed technology, in forming the well region320of the circuit region200including pixel transistors therein, the width of the lower well region320D formed below the active region ACT may be less than the width of the upper well region320U, and the depth of the lower well region320D may be less than the depth of the impurity region (P−region) of each of the control nodes CNA and CNB. Since the lower well region320D is formed to have a smaller width as described above, the well region320may be spaced farther away from the control nodes CNA and CNB than the other case in which the lower well region320D is formed to have a larger width. Moreover, when the lower well region320D is formed to have a smaller depth, a distance between the well region320and each of the control nodes CNA and CNB becomes longer. That is, as shown inFIG.4A, as the distance between the well region320and each of the control nodes CNA and CNB increases, resistance between the well region320and each of the control nodes CNA and CNB also increases. As described above, in some implementations, as the distance between the well region320and each of the control nodes CNA and CNB becomes longer, resistance between the well region320and each of the control nodes CNA and CNB increases, such that leakage of a current (pixel current) flowing from the control nodes CNA and CNB to the circuit region200decreases, thereby reducing power consumption. In addition, as leakage of the pixel current decreases, the pixel current can be more concentrated into the photoelectric conversion region100, thereby improving the depth characteristics. However, if the well region320is formed to have a smaller width in the same manner as in the lower well region320D, a dark current may occur in a region (e.g., edge region) in which the well region is not formed in an active region. Accordingly, in some implementations, the upper well region320U may be entirely formed in the active region ACT. The lower well region320D may be formed below the upper well region320U in a manner that the Y-directional center axis of the lower well region320D can overlap with that of the upper well region320U. The width (length in X direction) of the lower well region320D may be larger than that of the source/drain regions (S/D) of the pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B. FIGS.5A and5Bare cross-sectional views illustrating examples of a method for forming a well structure of the circuit region shown inFIG.4Abased on some implementations of the disclosed technology. For convenience of description,FIGS.5A and5Billustrate only the circuit region200. Referring toFIG.5A, a mask pattern410for defining the circuit region200may be formed over the substrate310. In some implementations, the mask pattern410may include a photoresist pattern. Subsequently, P-type (P−) impurities may be implanted into the upper portion of the substrate310to a first depth through an ion implantation process using the mask pattern410, forming the upper well region320U. In some implementations, as shown inFIG.4A, the upper well region320U may be formed to a predetermined depth corresponding to the depth of the device isolation layer (ISO) for isolating the active region ACT of the circuit region200from the taps TA and TB of the photoelectric conversion region100. Referring toFIG.5B, a mask pattern420for defining the lower well region320D may be formed over the substrate320including the upper well region320U. The mask pattern420may include a photoresist pattern. Subsequently, P-type (P−) impurities may be implanted into a lower portion of the upper well region320to a second depth through an ion implantation process using the mask pattern420, forming the lower well region320D. In some implementations, the second depth may be less than the depth of the impurity region (P−region) of the control nodes CNA and CNB. Thereafter, the device isolation layer (not shown) for isolating the active region ACT including the upper well region320U from the taps TA and TB of the photoelectric conversion region100may be formed. In some implementations, the device isolation layer may be formed to have a shallow trench isolation (STI) structure. FIGS.6A and6Bare cross-sectional views illustrating examples of another method for forming a well structure of the circuit region shown inFIG.4Abased on some implementations of the disclosed technology. For convenience of description,FIGS.6A and6Billustrate only the circuit region200. Referring toFIG.6A, a mask pattern420for defining the lower well region320D may be formed over the substrate310. Subsequently, P-type (P−) impurities may be implanted into the substrate310to a second depth from the top surface of the substrate310through ion implantation using the mask pattern420, forming impurity regions320U1and320D. In some implementations, the second depth may be less than the depth of the impurity region (P−region) of the control nodes CNA and CNB. AlthoughFIG.6Ashows the impurity regions320U1and320D as being distinct from one another, the impurity regions320U1and320D may be formed to have the same doping concentration. Referring toFIG.6B, a mask pattern430may be formed over the substrate310in which the impurity regions320U1and320D are formed. The mask pattern430may allow the remaining regions other than the impurity regions320U1and320D in the circuit region200to be exposed outside. Subsequently, a P-type (P−) impurity region320U2may be implanted into both sides of the impurity region320U1in the upper portion of the substrate310through ion implantation using the mask pattern430, forming the impurity region320U. Thereafter, the device isolation layer (not shown) is formed to isolate the active region ACT including the upper well region320U from the taps TA and TB of the photoelectric conversion region100. In some implementations, the device isolation layer may be formed to have a shallow trench isolation (STI) structure. As is apparent from the above description, the image sensing device based on some implementations of the disclosed technology can reduce power consumption and improve depth image characteristics. Although a number of illustrative embodiments have been described, it should be understood that various modifications to the disclosed embodiments and other embodiments can be devised based on what is described and/or illustrated in this patent document. | 39,790 |
11942493 | DESCRIPTION OF EMBODIMENTS Embodiments of the present disclosure will be described below with reference to the figures. In the illustration of the figures referred to in the following description, the same or similar portions will be denoted by the same or similar reference numerals. However, it should be noted that the figures are schematic and relationships between thicknesses and planar dimensions, ratios of thicknesses of respective layers, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined by taking the following description into consideration. In addition, it is needless to say that portions having different dimensional relationships and ratios between the figures are included in the figures. It is to be understood that definitions of directions such as upward, downward, and the like in the following description are merely definitions provided for convenience of explanation and are not intended as limiting technical ideas of the present disclosure. For example, it is obvious that when an object is observed after being rotated 90°, upward and downward directions are interpreted as being converted into leftward and rightward directions, and when an object is observed after being rotated 180°, upward and downward directions are interpreted as being inverted. In the following description, for example, in a P type semiconductor, + may be added to a conductive type for description. The P type semiconductor with + added means that a P type impurity concentration is relatively higher than that of a P type semiconductor without +. However, when semiconductors have the same P and P, it does not mean that impurity concentrations of the respective semiconductors are exactly the same. First Embodiment (Overall Configuration) FIG.1is a schematic diagram showing a configuration example of an imaging device100according to a first embodiment of the present disclosure. The imaging device100includes, for example, a first substrate unit110, a second substrate unit120, and a third substrate unit130. The imaging device100is an imaging device having a three-dimensional structure configured by bonding the first substrate unit110, the second substrate unit120, and the third substrate unit130. The first substrate unit110, the second substrate unit120, and the third substrate unit130are laminated in order. The first substrate unit110has a semiconductor substrate111, and a plurality of sensor pixels112provided on the semiconductor substrate111. The plurality of sensor pixels112perform photoelectric conversion. The plurality of sensor pixels112are provided in a matrix shape in a pixel region113of the first substrate unit110. The second substrate unit120has a semiconductor substrate121, a read circuit122provided on the semiconductor substrate121, a plurality of pixel drive lines123provided on the semiconductor substrate121to extend in a row direction, and a plurality of vertical signal lines124provided on the semiconductor substrate121to extend in a column direction. The read circuit122outputs pixel signals based on electric charges output from the sensor pixels112. One read circuit122is provided for every four sensor pixels112. The third substrate unit130has a semiconductor substrate131, and a logic circuit132provided on the semiconductor substrate131. The logic circuit132has a function of processing the pixel signals and has, for example, a vertical drive circuit133, a column signal processing circuit134, a horizontal drive circuit135, and a system control circuit136. The vertical drive circuit133selects, for example, the plurality of sensor pixels112row by row in order. The column signal processing circuit134performs correlated double sampling (CDS) processing on the pixel signal output from each sensor pixel112in a row selected by the vertical drive circuit133, for example. The column signal processing circuit134extracts a signal level of the pixel signal by performing the CDS processing, for example, and holds pixel data corresponding to an amount of light received by each sensor pixel112. The horizontal drive circuit135, for example, sequentially outputs the pixel data held in the column signal processing circuit134to the outside. The system control circuit136controls, for example, drive of each block (the vertical drive circuit133, the column signal processing circuit134, and the horizontal drive circuit135) in the logic circuit132. Also, althoughFIG.1shows a case in which the first substrate unit110and the second substrate unit120are configured of separate substrates, this is only an example. The first substrate unit110and the second substrate unit120may be configured of one substrate. For example, the first substrate unit110may be provided with the plurality of sensor pixels112and the read circuit122.FIGS.3and17, which will be described later, exemplify a case in which the plurality of sensor pixels112and the read circuit122(including an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL) are provided on the first substrate unit110.FIG.4, which will be described later, exemplifies a case in which the sensor pixels112are provided on the first substrate unit110and the read circuit122is provided on the second substrate unit120. FIG.2is a circuit diagram showing a configuration example of a pixel unit PU according to the first embodiment of the present disclosure. As shown inFIG.2, in the imaging device100, four sensor pixels112are electrically connected to one read circuit122to form one pixel unit PU. The four sensor pixels112share one read circuit122, and each output of the four sensor pixels112is input to the shared read circuit122. Each sensor pixel112has constituent elements common to each other. InFIG.2, in order to distinguish the constituent elements of each sensor pixel112from each other, an identification number 1, 2, 3, or 4 is added to ends of reference numerals (for example, PD, TG, and FD, which will be described later) of the constituent elements of each sensor pixel112. In cases below in which it is not necessary to distinguish the constituent elements of each sensor pixel112from each other, the identification numbers at the ends of the reference numerals of the constituent elements of each sensor pixel112will be omitted. Each sensor pixel112has, for example, a photodiode PD (an example of the “light receiving element” of the present disclosure), a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds an electric charge output from the photodiode PD via the transfer transistor TR. The transfer transistor TR is an N type field effect transistor. The floating diffusion FD is an N type impurity diffusion layer. The photodiode PD performs photoelectric conversion to generate the electric charge (an electrical signal) in accordance with an amount of received light. A cathode of the photodiode PD is electrically connected to a source of the transfer transistor TR, and an anode of the photodiode PD is electrically connected to a reference potential line (for example, a ground). A drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and a gate electrode of the transfer transistor TR is electrically connected to the pixel drive line123. The transfer transistor TR is, for example, a complementary metal oxide semiconductor (CMOS) transistor. The gate electrode of the transfer transistor TR is called a transfer gate TG. The floating diffusions FD of each of the sensor pixels112that share one read circuit122are electrically connected to each other and are also electrically connected to an input end of the common read circuit122. The read circuit122includes, for example, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL. The amplification transistor AMP, the reset transistor RST, and the selection transistor SEL are N type field effect transistors. Also, the selection transistor SEL may be omitted if necessary. A source of the reset transistor RST (the input end of the read circuit122) is electrically connected to the floating diffusions FD, and a drain of the reset transistor RST is electrically connected to a drain of the amplification transistor AMP and a power supply line VDD. A gate electrode of the reset transistor RST is electrically connected to the pixel drive line123(seeFIG.1). A source of the amplification transistor AMP is electrically connected to a drain of the selection transistor SEL, and a gate electrode of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. A source of the selection transistor SEL (an output end of the read circuit122) is electrically connected to the vertical signal line124, and a gate electrode of the selection transistor SEL is electrically connected to the pixel drive line123(seeFIG.1). Due to the above connection relationship, the transfer transistor TR switches the connection between the photodiode PD and the floating diffusion FD on or off. The amplification transistor AMP amplifies the electrical signal temporarily stored in the floating diffusion FD. The selection transistor SEL switches the connection between the amplification transistor AMP and the vertical signal line124on or off. The reset transistor RST switches the connection between the floating diffusion FD and the power supply line VDD on or off. When the transfer transistor TR is turned on, the transfer transistor TR transfers the electrical charge of the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls an output timing of the pixel signal (electric signal) from the read circuit122. The amplification transistor AMP generates a voltage signal serving as the pixel signal in accordance with a level of the electric charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source follower type amplifier and outputs the pixel signal having a voltage corresponding to the level of electric charge generated by the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit134via the vertical signal line124. (Arrangement and Configuration of Field Effect Transistors) FIG.3is a plan view schematically showing a first arrangement example of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL in the imaging device100according to the first embodiment of the present disclosure, As described above, in the example shown inFIG.3, the photodiode PD, the transfer transistor TR, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided on the first substrate unit110. A main surface (for example, an upper surface) of the semiconductor substrate111(seeFIG.1) constituting the first substrate unit110has a crystal plane that is a (100) plane or a plane equivalent to the (100) plane. Also, as the plane equivalent to the (100) plane, a (010) plane, a (001) plane, a (−100) plane, a (0-10) plane, and a (00-1) plane can be mentioned. In the present specification, for convenience of explanation, the plane equivalent to the (100) plane may be simply referred to as the (100) plane. In addition, a normal direction of the crystal plane is a crystal orientation. The crystal orientation of the (100) plane is a <100> direction. In the present specification, for convenience of explanation, not only the crystal orientation of the (100) plane but also a crystal orientation of the plane equivalent to the (100) plane is simply referred to as the <100> direction. As shown inFIG.3, in the first substrate unit110, the transfer transistor TR is disposed such that a gate length direction thereof is parallel to the <100> direction. The gate length direction is a direction from a source to a drain of a field effect transistor. Similarly, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are also disposed such that their gate length directions are parallel to the <100> direction. In the embodiment of the present disclosure, in at least the amplification transistor AMP among the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, a shape of a semiconductor layer in which a channel is formed is a fin shape. Not only in the amplification transistor AMP but also in the reset transistor RST and the selection transistor SEL, a shape of a semiconductor layer in which a channel is formed may be a fin shape. FIG.4is a plan view schematically showing a second arrangement example of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL in the imaging device100according to the first embodiment of the present disclosure. As described above, in the example shown inFIG.4, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided in the second substrate unit120. InFIG.4, in order to illustrate gate electrodes RG, AG, and SG of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, and semiconductor layers21, Illustration of an interlayer insulating film57(seeFIG.7) is omitted. FIGS.5and6are cross-sectional views showing a configuration example of the amplification transistor AMP according to the first embodiment of the present disclosure.FIG.5shows a cross-section of the plan view shown inFIG.4along line A-A.FIG.6shows a cross-section of the plan view shown inFIG.4along line B-B′.FIG.7is a cross-sectional view showing a configuration example of the imaging device100according to the first embodiment of the present disclosure.FIG.7shows a cross-section of the plan view shown inFIG.4along line C-C′ and shows a cross-section of a laminate including the first substrate unit110and the second substrate unit120. As shown inFIG.4, the second substrate unit120is provided with the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL. As shown inFIGS.4to7, the amplification transistor AMP has a P type semiconductor layer21in which a channel is formed, a gate electrode AG that covers the semiconductor layer21, and a gate insulating film25disposed between the semiconductor layer21and the gate electrode AG. A main surface (for example, an upper surface) of the semiconductor substrate121(seeFIG.1) constituting the second substrate unit120has a crystal plane that is a (100) plane or a plane equivalent to the (100) plane. The semiconductor layer21is, for example, a part of the semiconductor substrate121and is made of single crystal silicon. The semiconductor layer21is a portion formed by etching a part of an upper surface21aside of the semiconductor substrate121. A shape of the semiconductor layer21is, for example, a fin shape. The fin shape is, for example, a rectangular parallelepiped shape that is long in its gate length direction and short in its gate width direction orthogonal to the gate length direction. A length (width) L1of the semiconductor layer21in the gate width direction is preferably 300 nm or less. Thus, a fin confinement effect can be obtained. The fin confinement effect is an effect that a semiconductor layer serving as a channel is surrounded with a gate electrode, whereby a current flows in a portion separated from an interface between the semiconductor layer and a gate oxide film. The semiconductor layer21has the upper surface21a(an example of the “main surface” of the present disclosure), a first side surface21b, and a second side surface21c. In the gate width direction of the amplification transistor AMP, the first side surface21bis located on one end side of the upper surface21a, and the second side surface21cis located on one end side of the upper surface21a. A crystal plane of each of the upper surface21a, the first side surface21b, and the second side surface21cis a (100) plane, and a crystal orientation thereof, which is a normal direction of the crystal plane, is the <100> direction. The amplification transistor AMP has a plurality of fin-shaped semiconductor layers21. The plurality of semiconductor layers21are disposed side by side at intervals in the gate width direction of the amplification transistor AMP. The gate insulating film25is provided to cover the upper surface21a, the first side surface21b, and the second side surface2121cof the semiconductor layer21. The gate insulating film20is made of, for example, a silicon oxide film (SiO2film). The gate electrode AG covers the semiconductor layer21via the gate insulating film25. For example, the gate electrode AG has a first portion31that faces the upper surface21aof the semiconductor layer21via the gate insulating film25, a second portion32that faces the first side surface21bof the semiconductor layer21via the gate insulating film25, and a third portion33that faces the second side surface21cof the semiconductor layer21via the gate insulating film25. The second portion32and the third portion33are connected to a lower surface of the first portion31. Thus, the gate electrode AG can simultaneously apply a gate voltage to the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21. That is, the gate electrode30can simultaneously apply the gate voltage to the semiconductor layer21from a total of three directions, an upper side, and both left and right sides. Thus, the gate electrode30can completely deplete the semiconductor layer21. The gate electrode30is made of, for example, a polysilicon (Poly-Si) film. A source region41and a drain region42are provided in regions of the semiconductor substrate121which are exposed from below the gate electrode AG. In the gate length direction of the amplification transistor AMP, the source region41is connected to one side of the semiconductor layer21in which the channel is formed, and the drain region42is connected to the other side of the semiconductor layer21in which the channel is formed. Conductive types of the source region41and the drain region42are, for example, N types. The selection transistor SEL and the reset transistor RST have the same configuration as the amplification transistor AMP. That is, the selection transistor SEL has a fin-shaped semiconductor layer21, a gate insulating film25, and a gate electrode SG. The semiconductor layer21has an upper surface21a, a first side surface21b, and a second side surface21c. Also in the selection transistor SEL, a crystal plane of each of the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21is a (100) plane, and a crystal orientation thereof is the <100> direction. The selection transistor SEL has a plurality of fin-shaped semiconductor layers21. The plurality of semiconductor layers21are disposed side by side at intervals in the gate width direction of the selection transistor SEL. The gate electrode SG covers the upper surface21a, the first side surface21b, and the second side surface21cof the plurality of semiconductor layers21via the gate insulating film25. The reset transistor RST has a fin-shaped semiconductor layer21, a gate insulating film25, and a gate electrode RG. The semiconductor layer21has an upper surface21a, a first side surface21b, and a second side surface21c. Also in the reset transistor RST, a crystal plane of each of the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21is a (100) plane, and a crystal orientation thereof is the <100> direction. The selection transistor SEL has one fin-shaped semiconductor layer21. The gate electrode RG covers the upper surface21a, the first side surface21b, and the second side surface21cof one semiconductor layer21via the gate insulating film25. As shown inFIG.7, in the second substrate unit120, the gate electrode AG of the amplification transistor AMP, the gate electrode SG of the selection transistor SEL, and the gate electrode RG of the reset transistor RST are separated from each other by an insulating film52and covered with the interlayer insulating film57. The insulating film52for element separation is configured of, for example, a silicon oxide film (SiO2film). The interlayer insulating film57is configured of, for example, a SiO2film, a silicon nitride film (SiN film), or a film in which these are laminated. The interlayer insulating film57is provided with a plurality of through holes. Through wirings54and59are provided in these through holes. Further, a wiring55is provided on the interlayer insulating film57. The gate electrode AG of the amplification transistor AMP is connected to the source of the reset transistor RST and the floating diffusion FD of the first substrate unit110via the through wirings54and59and the wiring55. As shown inFIG.7, the semiconductor substrate111of the first substrate unit110is provided with the photodiode PD, a P-well region43in which the channel of the transfer transistor TR is formed, and the floating diffusion FD corresponding to the drain of the transfer transistor TR. The photodiode PD is configured of an N type impurity diffusion layer47, and a P+type impurity diffusion layer48provided on the N type impurity diffusion layer47. The N type impurity diffusion layer47and the P+type impurity diffusion layer48are joined by PN junction. The floating diffusion FD is an N type impurity diffusion layer. Further, the transfer gate TG, which is a gate electrode of the transfer transistor TR, is provided on the semiconductor substrate111via a gate insulating film15. The transfer gate TG is covered with an interlayer insulating film46provided on the semiconductor substrate111. Although not shown inFIG.7, the third substrate unit130is disposed on the second substrate unit120. Further, in the first substrate unit110, a color filter and a light receiving lens are disposed on a side opposite to a surface provided with the interlayer insulating film46. (Positional Relationship Between Field Effect Transistor and Notch) FIG.8is a plan view schematically showing a positional relationship between a field effect transistor1and a notch3N in a case in which a 45° notch substrate is used in the embodiment of the present disclosure. As shown inFIG.8, the field effect transistor1has a source1S, a drain1D, and a gate electrode1G. A fin-shaped semiconductor layer2is disposed under the gate electrode1G. A semiconductor wafer3is, for example, a single crystal silicon wafer. A crystal plane of an upper surface3aof the semiconductor wafer3(that is, a surface on which the field effect transistor1is formed) is a (100) plane. In addition, the semiconductor wafer3is provided with the notch3N in the <100> direction. Regarding a crystal orientation thereof, the <100> direction is tilted by 45° with respect to a <110> direction. In the present specification, the semiconductor wafer3provided with the notch3N in the <100> direction is also referred to as a 45° notch substrate. In the 45° notch substrate, each of a notching direction of the notch3N and a direction orthogonal to the notching direction is the <100> direction. Thus, as shown inFIG.8, crystal planes of the first side surface2band the second side surface2clocated at both ends of the semiconductor layer2in the gate width direction are (100) planes. In the embodiment of the present disclosure, the semiconductor substrate121of the second substrate unit120corresponds to the semiconductor wafer3shown inFIG.8. The amplification transistor AMP corresponds to the field effect transistor1shown inFIG.8. Further, in addition to the amplification transistor AMP, one or more of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL may correspond to the field effect transistor1. (Manufacturing Method) Next, a method for manufacturing the imaging device100shown inFIG.7will be described. The imaging device100is manufactured by using various devices such as a film forming device (including a chemical vapor deposition (CVD) device and a sputtering device), an ion implantation device, a heat treatment device, an etching device, a chemical mechanical polishing (CMP) device, and a bonding device. Hereinafter, these devices are collectively referred to as a manufacturing device. FIGS.9to14are cross-sectional views showing the method for manufacturing the imaging device100according to the first embodiment of the present disclosure in the order of processes. As shown inFIG.9, the manufacturing device forms the P-well region43on the semiconductor substrate111. Any substrate can be used for the semiconductor substrate111. As an example, for the semiconductor substrate111, a 45° notch substrate whose main surface is the (100) plane is used. Next, the manufacturing device forms the gate insulating film15on the P-well region43and forms the transfer gate TG on the gate insulating film15. Next, the manufacturing device forms the floating diffusion FD and the photodiode PD configured of the N type impurity diffusion layer47and the P+type impurity diffusion layer48on the semiconductor substrate111. In a process of forming the floating diffusion FD and a process of forming the photodiode PD, the manufacturing device may use the transfer gate TG as a part of a mask for ion implantation. Next, the manufacturing device forms the interlayer insulating film46on the semiconductor substrate111. Through the above processes, the first substrate unit110is manufactured. Next, as shown inFIG.10, the manufacturing device bonds the semiconductor substrate121on the interlayer insulating film46of the first substrate unit110. For the semiconductor substrate121, a 45° notch substrate whose main surface is the (100) plane is used. Next, the manufacturing device polishes or etches the upper surface of the semiconductor substrate121to form the semiconductor substrate121to a preset thickness. By using the (100) substrate for the semiconductor substrate121, the upper surface21aof the semiconductor layer21becomes the (100) plane. Next, as shown inFIG.11, the manufacturing device etches the semiconductor substrate121to form the fin-shaped semiconductor layer21. In this etching process, the semiconductor substrate121is etched with a mask (for example, a resist pattern or a hard mask) disposed on the semiconductor substrate121. In a process of disposing the mask, a position of the notch is adjusted in advance such that the notching direction of the notch (for example, the <100> direction as shown inFIG.7) is parallel or perpendicular to the gate length direction of the semiconductor layer21formed by using the mask. Thus, the first side surface21band the second side surface21cof the semiconductor layer21formed by using the mask become the (100) plane. Next, the manufacturing device thermally oxidizes the semiconductor layer21. Thus, as shown inFIG.12, the manufacturing device forms the gate insulating film25on the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21. Next, the manufacturing device uses the CVD method to form a polysilicon film on the interlayer insulating film46. The manufacturing device forms, for example, a polysilicon film doped with P-type impurities. Next, the manufacturing device etches the polysilicon film to form the gate electrodes SG, AG, and RG as shown inFIG.13. Conductive types of the gate electrodes SG, AG, and RG are, for example, P+types. Next, the manufacturing device performs ion implantation of N type impurities into the semiconductor layer21using the gate electrodes SG, AG, and RG as masks. Next, the manufacturing device performs heat treatment for the semiconductor layer21in which the N type impurities are ion-implanted. This forms the source region and drain region of the selection transistor SEL, the source region41(seeFIG.5) and the drain region42(seeFIG.5) of the amplification transistor AMP, and the source region and the drain region of the reset transistor RST. Next, the manufacturing device uses the CVD method to form the insulating film52for element separation on the interlayer insulating film46. Next, the manufacturing device flattens the insulating film52by etching back or performing CMP processing on the insulating film52. Next, as shown inFIG.14, the manufacturing device uses the CVD method to form the interlayer insulating film57on the insulating film52and on the gate electrodes SG, AG, and RG. Next, the manufacturing device etches the interlayer insulating film57to form through holes h1on the gate electrodes SG, AG, and RG. Further, the manufacturing device etches the interlayer insulating film57, the insulating film52for element separation, and the interlayer insulating film46to form a through hole h2on the floating diffusion FD. The through holes h1and h2may be formed at the same time or separately. Next, the manufacturing device forms the through wiring59(seeFIG.7) in the through holes h1and the through wiring54(seeFIG.7) in the through hole h2. Further, the manufacturing device forms the wiring55(seeFIG.7) on the interlayer insulating film46. The through wirings54and59and the wiring55may be formed at the same time or separately. Through the above processes, the imaging device100shown inFIG.7is completed. As described above, the imaging device100according to the first embodiment of the present disclosure includes the photodiode PD, and the read circuit122for reading the electrical signal photoelectrically converted by the photodiode PD. The field effect transistor (for example, the amplification transistor AMP) included in the read circuit122has the semiconductor layer21in which the channel is formed, the gate electrode AG that covers the semiconductor layer21, and the gate insulating film25disposed between the semiconductor layer21and the gate electrode AG. The semiconductor layer21has the upper surface21a, and the first side surface21blocated on one end side of the upper surface21ain the gate width direction of the amplification transistor AMP. The gate electrode AG has the first portion31that faces the upper surface21avia the gate insulating film25, and the second portion32that faces the first side surface21bvia the gate insulating film25. The crystal plane of the first side surface21bis the (100) plane or a plane equivalent to the (100) plane. According to this, the amplification transistor AMP included in the read circuit122can reduce an interface state of the first side surface21bon which the channel is formed, and can reduce the electric charge (for example, electrons) trapped in the interface state. Thus, the imaging device100can reduce noise (for example, 1/f noise) caused by the above-mentioned interface state. Further, since the imaging device100can reduce noise, it is possible to shorten a gate length of the amplification transistor AMP. As a result, the imaging device100can reduce a pixel size and increase a degree of freedom in layout in the pixel. Further, the semiconductor layer21may further have the second side surface21clocated on the other end side of the upper surface21ain the gate width direction. The gate electrode AG may further have the third portion33that faces the second side surface21cvia the gate insulating film25. The crystal plane of the second side surface21cmay be the (100) plane or a plane equivalent to the (100) plane. According to this, a channel is formed not only on the first side surface21bof the semiconductor layer21but also on the second side surface21c. The amplification transistor AMP can widen a gate width and reduce on-resistance. In addition, the amplification transistor AMP can reduce the interface state also on the second side surface21c. Further, the crystal plane of the upper surface21aof the semiconductor layer21may be the (100) plane or a plane equivalent to a (100) plane. According to this, the amplification transistor AMP can also reduce the interface state on the upper surface21a. Further, in the embodiment of the present disclosure, each crystal plane of the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21may include some manufacturing error (an offset) with respect to the (100) plane. For example, in the process of forming the semiconductor layer21shown inFIG.11, when the semiconductor wafer is set in a state in which it is slightly displaced from a stage of the manufacturing device (for example, an exposure device), manufacturing errors may occur in the crystal planes of the first side surface21band the second side surface21c. The embodiment of the present disclosure tolerate such manufacturing errors. For example, in the embodiment of the present disclosure, a crystal plane closer to the (100) plane than an intermediate between the (100) plane and the (110) plane is treated as the (100) plane. In the embodiment of the present disclosure, a crystal plane whose inclination with respect to the (100) plane is less than ±22.5° (=45°±2) is treated as the (100) plane. It is preferable that each crystal plane of the first side surface21band the second side surface21cof the semiconductor layer21is exactly the (100) plane, but even in a case in which there are manufacturing errors as described above, the imaging device100can reduce the interface state of the semiconductor layer21in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. Modified Example 1 FIG.15is a cross-sectional view showing a configuration of an imaging device100A according to a modified example of the first embodiment of the present disclosure. As shown inFIG.15, in the imaging device100A, lower portions of the fin-shaped semiconductor layers21are connected to each other. This structure can be formed by leaving the semiconductor substrate121exposed from the mask thin instead of completely removing it by etching in the process of forming the semiconductor layer21shown inFIG.11. Similarly to the above-mentioned imaging device100, the imaging device100A can reduce the interface state of the semiconductor layer21in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. Modified Example 2 AlthoughFIGS.7and15show a case in which the amplification transistor AMP has two semiconductor layers21, the embodiment of the present disclosure is not limited thereto. The number of the semiconductor layers21included in the amplification transistor AMP may be one or three or more. In a case in which the number of semiconductor layers21included in the amplification transistor AMP is one, the amplification transistor AMP has the same structure as the reset transistor RST shown inFIGS.7and15. In addition, in a case in which the number of semiconductor layers21included in the amplification transistor AMP is three or more, the three or more semiconductor layers21are disposed side by side at intervals in the gate width direction of the amplification transistor AMP. Similarly to the imaging device100described above, the imaging device according to the second modified example can reduce the interface state of the semiconductor layer21in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. Second Embodiment In the above embodiment, it has been described that the semiconductor wafers (that is, the 45° notch substrates) in which notches are provided in the <100> direction are used for the semiconductor substrates111and121. However, the embodiment of the present disclosure is not limited thereto. In the embodiment of the present disclosure, semiconductor wafers in which notches are provided in the <110> direction instead of the <100> direction may be used for the semiconductor substrates111and121. In the present specification, a semiconductor wafer provided with a notch in the <110> direction is referred to as a 0° notch substrate. FIG.16is a plan view schematically showing a positional relationship between the field effect transistor1and the notch3N in a case in which the 0° notch substrate is used in the embodiment of the present disclosure. In the 0° notch substrate, each of the notching direction of the notch3N and the direction orthogonal to the notching direction is the <110> direction. As shown inFIG.16, in a case in which the 0° notch substrate is used, the field effect transistor1is formed on the semiconductor wafer3such that the direction inclined by 45° with respect to the notching direction of the notch3N is the gate length direction. Thus, the crystal planes of the first side surface2band the second side surface2cof the semiconductor layer2become (100) planes. FIG.17is a plan view schematically showing an arrangement example of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL in an imaging device100B according to a second embodiment of the present disclosure. As described above, in the example shown inFIG.17, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are provided on the first substrate unit110. In the second embodiment, a 0° notch substrate is used for the semiconductor substrate of the first substrate unit110. As shown inFIG.17, in the first substrate unit110, the transfer transistor TR is formed such that the notching direction of the notch is the gate length direction. Further, in the first substrate unit110, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are formed such that the direction inclined 45 degrees with respect to the notching direction of the notch is the gate length direction. In such a case, in each of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, each crystal plane of the upper surface21a, the first side surface21b, and the second side surface21cof the semiconductor layer21is also the (100) plane. Accordingly, similarly to the imaging device100according to the first embodiment, the imaging device100B according to the second embodiment can reduce the interface state of the semiconductor layer21in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. Also, the gate length direction of the transfer transistor TR is not limited to the above. The gate length direction of the transfer transistor TR may be perpendicular to the notching direction of the notch or may be inclined with respect to the notching direction of the notch. Further, the gate length directions of the reset transistor RST and the selection transistor SEL are not limited to the above. In the second embodiment, when at least the gate length direction of the amplification transistor AMP is inclined by 45° with respect to the notching direction of the notch, the above-mentioned interface state can be reduced, and noise (for example, 1/f noise) caused by the interface state can be reduced. <Measurement Results of Interface State> FIG.18is a diagram showing measurement results of an interface state of a field effect transistor according to an example of the present disclosure and an interface state of a field effect transistor according to a comparative example. The horizontal axis inFIG.18indicates a magnitude of the interface state. On the horizontal axis, “a” is an integer. In addition, the vertical axis inFIG.18shows a standard deviation σ of the interface state. In the field effect transistor according to the example, the first side surface and the second side surface of the semiconductor layer in which the channel is formed are (100) planes. In the field effect transistor according to the comparative example, the first side surface and the second side surface of the semiconductor layer in which the channel is formed are (110) planes. As shown inFIG.18, it was confirmed that the interface state of the field effect transistor according to the example is about ½ of the interface state of the field effect transistor according to the comparative example. SPECIFIC EXAMPLES The above-mentioned first and second embodiments and the modified examples thereof can be applied to imaging devices having various structures. Examples of imaging devices to which the embodiments of the present disclosure can be applied will be shown below as specific examples. First Specific Example FIG.19is a cross-sectional view showing a first specific example of an imaging device according to the embodiments of the present disclosure. As shown inFIG.19, the imaging device according to the first specific example is configured by laminating a first substrate unit210, a second substrate220, and a third substrate230in this order, and includes a color filter240, and a light receiving lens250on a back surface side (a light incidence surface side) of the first substrate unit210. One color filter240and one light receiving lens250are provided for each sensor pixel212. The imaging device shown inFIG.19is a back side illumination type imaging device. The first substrate unit210is configured by laminating an insulating layer246on a semiconductor substrate211. The first substrate unit210has the insulating layer246as a part of an interlayer insulating film251. The insulating layer246is provided in a gap between the semiconductor substrate211and a semiconductor substrate221, which will be described later. The semiconductor substrate211is configured of a silicon substrate. The semiconductor substrate211has a P-well region242in or near a part of a surface thereof, and has a photodiode PD in a region deeper than the P-well region242. The photodiode PD is configured of an N type semiconductor region. Further, the semiconductor substrate211has a floating diffusion FD, which is an N type semiconductor region, in the P-well region242. The first substrate unit210has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel212. The transfer transistor TR and the floating diffusion FD are provided on a front surface side of the semiconductor substrate211(a side opposite to the light incidence surface side, the second substrate220side). The first substrate unit210has an element separation portion243that separates the sensor pixels212from each other. The element separation portion243extends in a normal direction of the front surface of the semiconductor substrate211. The element separation portion243is provided between two sensor pixels212adjacent to each other and electrically separates the sensor pixels212adjacent to each other from each other. The element separation portion243is made of silicon oxide (SiO2). The element separation portion243penetrates the semiconductor substrate211. The first substrate unit210further has a P-well region244located between the element separation portion243and the photodiode PD. The first substrate unit210further has a fixed charge film245in contact with a back surface of the semiconductor substrate211. The fixed charge film245is negatively charged in order to inhibit generation of dark current due to an interface state of the semiconductor substrate211on a light receiving surface side thereof. The fixed charge film245is configured of an insulating film having a negative fixed charge. Examples of a material of such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. Due to an electric field induced by the fixed charge film245, a hole accumulation layer is formed at an interface on the light receiving surface side of the semiconductor substrate211. This hole accumulation layer inhibits generation of electrons from the interface. The color filter240is provided on the back surface side of the semiconductor substrate211. The color filter240is provided in contact with the fixed charge film245and is provided at a position facing the sensor pixel212via the fixed charge film245. The light receiving lens250is provided in contact with the color filter240, and is provided at a position facing the sensor pixel212via the color filter240and the fixed charge film245. The second substrate220is configured by laminating an insulating layer252on the semiconductor substrate221. The second substrate220has the insulating layer252as a part of the interlayer insulating film251. The insulating layer252is provided in a gap between the semiconductor substrate221and a semiconductor substrate231. The semiconductor substrate221is made of a silicon substrate. The second substrate220has one read circuit222for every four sensor pixels212. The second substrate220has a configuration in which the read circuit222is provided on a portion of the semiconductor substrate221on the front surface side (the third substrate230side). The second substrate220is bonded to the first substrate unit210with the back surface of the semiconductor substrate221facing the front surface side of the semiconductor substrate211. That is, the second substrate220is bonded to the first substrate unit210by a face to back bonding. The second substrate220further has an insulating layer253that penetrates the semiconductor substrate221in the same layer as the semiconductor substrate221. The second substrate220has the insulating layer253as a part of the interlayer insulating film251. The insulating layer253is provided to cover a side surface of a through wiring254, which will be described later. A laminate configured of the first substrate unit210and the second substrate220has the interlayer insulating film251, and the through wiring254provided in the interlayer insulating film251. The laminate has one through wiring254for each sensor pixel212. The through wiring254extends in a normal direction of the semiconductor substrate221and is provided so as to penetrate the portion of the interlayer insulating film251including the insulating layer253. The first substrate unit210and the second substrate220are electrically connected to each other by the through wiring254. Specifically, the through wiring254is electrically connected to the floating diffusion FD and a connection wiring255, which will be described later. The second substrate220has a plurality of connection portions259, which are electrically connected to the read circuit222and the semiconductor substrate221, in the insulating layer252. The second substrate220further has, for example, a wiring layer256on the insulating layer252. The wiring layer256has an insulating layer257, a plurality of pixel drive lines223provided in the insulating layer257, and a plurality of vertical signal lines224. The wiring layer256further has a connection wiring255for every four sensor pixels212. The connection wiring255is provided in the insulating layer257. The connection wiring255is electrically connected to the floating diffusions FD included in the four sensor pixels212that share the read circuit222via the through wiring254. The wiring layer256further has a plurality of pad electrodes258in the insulating layer257. Each pad electrode258is made of a metal such as copper (Cu) or aluminum (Al), for example. Each pad electrode258is exposed on a front surface of the wiring layer256. Each pad electrode258is used for electrical connection between the second substrate220and the third substrate230and for bonding the second substrate220and the third substrate230. The plurality of pad electrodes258are provided one by one for each of the pixel drive line223and the vertical signal line224. The third substrate230is configured by laminating an interlayer insulating film261on the semiconductor substrate231. The semiconductor substrate231is made of a silicon substrate. The third substrate230has a configuration in which a logic circuit232is provided on a portion on a front surface side of the semiconductor substrate231. The third substrate230further has a wiring layer262on the interlayer insulating film261. The wiring layer262has an insulating layer263and a plurality of pad electrodes264provided in the insulating layer263. The plurality of pad electrodes264are electrically connected to the logic circuit232. Each pad electrode264is made of, for example, copper (Cu). Each pad electrode264is exposed on a front surface of the wiring layer262. Each pad electrode264is used for electrical connection between the second substrate220and the third substrate230and for bonding the second substrate220and the third substrate230. Further, the number of pad electrodes264does not necessarily have to be plural, and one pad electrode264can also be electrically connected to the logic circuit232. The second substrate220and the third substrate230are electrically connected to each other by joining the pad electrodes258and264to each other. That is, the gate (transfer gate) TG of the transfer transistor TR is electrically connected to the logic circuit232via the through wiring254and the pad electrodes258and264. The third substrate230is bonded to the second substrate220with the front surface of the semiconductor substrate231facing the front surface side of the semiconductor substrate221. That is, the third substrate230is bonded to the second substrate220by a face to face bonding. The read circuit222shown inFIG.19has an amplification transistor AMP as shown inFIG.2, a reset transistor RST, and a selection transistor SEL. In addition, at least the amplification transistor AMP among the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL has a fin structure as shown inFIGS.5to7. That is, in the amplification transistor AMP shown inFIG.19, the semiconductor layer (semiconductor substrate221) in which the channel is formed has a fin shape. In addition, in the fin-shaped semiconductor layer, crystal planes of the first side surface and the second side surface located on both sides in a channel width direction are (100) planes. Thus, the first specific example of the imaging device can reduce the interface state of the semiconductor layer in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. Also, in the first specific example, the reset transistor RST and the selection transistor SEL may have a fin structure like the amplification transistor AMP or may have a structure different from that of the amplification transistor AMP (for example, a planar structure). Second Specific Example FIG.20is a cross-sectional view showing a second specific example of an imaging device according to the embodiments of the present disclosure. As shown inFIG.20, the imaging device according to the second specific example is an imaging device having a three-dimensional structure in which a first substrate unit310, a second substrate unit320, and a third substrate unit330are bonded together. The first substrate unit310, the second substrate unit320, and the third substrate unit330are laminated in this order. The first substrate unit310has a plurality of sensor pixels312that perform photoelectric conversion on a semiconductor substrate311. The plurality of sensor pixels312are provided in a matrix shape in a pixel region313of the first substrate unit310. The first substrate unit310has a plurality of drive wirings314extending in a row direction. The plurality of drive wirings314are electrically connected to a vertical drive circuit. The second substrate unit320has one read circuit322, which outputs a pixel signal based on an electric charge output from the sensor pixel312, for every one or a plurality of sensor pixels312on the semiconductor substrate321. A plurality of read circuits322are provided in a matrix shape in a read circuit region323of the second substrate unit320. The second substrate unit320has a plurality of drive wirings extending in a row direction and a plurality of vertical signal lines VSL extending in a column direction (seeFIG.21, which will be described later). The plurality of drive wirings provided on the second substrate unit320are electrically connected to the vertical drive circuit. The plurality of vertical signal line VSLs are electrically connected to a column signal processing circuit. The third substrate unit330has a logic circuit332, and a booster circuit333on a semiconductor substrate331. The logic circuit332controls each sensor pixel312and each read circuit322, and processes the pixel signal obtained from each read circuit322. The logic circuit332includes a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, and a system control circuit. The logic circuit332outputs an output voltage obtained from each sensor pixel312to the outside. FIG.21is a circuit diagram showing the second specific example of the imaging device according to the embodiments of the present disclosure, showing an example of the sensor pixel312and the read circuit322. Each sensor pixel312has constituent elements common to each other. Each sensor pixel312has a photodiode PD, a transfer transistor TR, and a floating diffusion FD. One floating diffusion FD is provided for a plurality of sensor pixels312that share the read circuit322. In addition, one floating diffusion FD may be provided for one sensor pixel312. In this case, in the plurality of sensor pixels312that share the read circuit322, a wiring for electrically connecting the floating diffusions FDs to each other is provided. An input end of the read circuit322is connected to the floating diffusion FD. Specifically, to the floating diffusion FD, the reset transistor RST of the read circuit322is connected, and the vertical signal line VSL is connected via the amplification transistor AMP and the selection transistor SEL. A capacitance Cfd is generated in the floating diffusion FD. As shown inFIG.21, the capacitance Cfd is generated between a wiring that connects each sensor pixel312to a FD junction electrode317and a region (a P-well region341) serving as a reference potential VSS in the first substrate unit310. As shown inFIG.21, the read circuit322has a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. A source of the reset transistor RST (the input end of the read circuit322) is electrically connected to the floating diffusion FD, and a drain of the reset transistor RST is electrically connected to a power supply line VDD and a drain of the amplification transistor AMP via a through wiring343. A gate of the reset transistor RST is electrically connected to the logic circuit332via a through wiring342. A source of the amplification transistor AMP is electrically connected to a drain of the selection transistor SEL, and a gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. A source of the selection transistor SEL (an output end of the read circuit322) is electrically connected to the logic circuit332via the vertical signal line VSL and the through wiring342, and a gate of the selection transistor SEL is electrically connected to the logic circuit332via the through wiring342. FIG.22is the second specific example of the imaging device according to the embodiments of the present disclosure and is a diagram showing an example of a cross-sectional configuration thereof in the vertical direction.FIG.22illustrates a cross-sectional configuration of a portion of the imaging device that faces the pixel region313(sensor pixel312) and a cross-sectional configuration of a region around the pixel region313. The imaging device includes a color filter340, and a light receiving lens350on a back surface side (a light incidence surface side) of the first substrate unit310. One color filter340and one light receiving lens350are provided for each sensor pixel312. The imaging device is a back side illumination type imaging device. The first substrate unit310is configured by laminating an insulating layer319on the semiconductor substrate311. The insulating layer319is an interlayer insulating film. The insulating layer319is provided between the semiconductor substrate311and the second substrate unit320. The first substrate unit310has the plurality of drive wirings314in the insulating layer319. The plurality of drive wirings314are provided one by one for each row in each of the plurality of sensor pixels312disposed in a matrix shape. The semiconductor substrate311is configured of a silicon substrate. The semiconductor substrate311has the P-well region341in or near a part of a front surface thereof, and has the photodiode PD in a region other than the P-well region (a region deeper than the P-well region341). The photodiode PD is configured of an N type semiconductor region. The semiconductor substrate311has the floating diffusion FD as an N type semiconductor region in the P-well region341. The first substrate unit310has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel312. The first substrate unit310has a configuration in which the transfer transistor TR and the floating diffusion FD are provided on a portion on a front surface side (a side opposite to the light incidence surface side, the second substrate unit320side) of the semiconductor substrate311. The first substrate unit310has an element separation portion that separates the sensor pixels312from each other. The element separation portion is formed to extend in a normal direction of the front surface of the semiconductor substrate311. The element separation portion is provided between two sensor pixels312adjacent to each other, and electrically separates the sensor pixels312adjacent to each other. The element separation portion is made of, for example, silicon oxide. The first substrate unit310further has a fixed charge film in contact with a back surface of the semiconductor substrate311. The color filter340is provided on the back surface side of the semiconductor substrate311. The color filter340is provided in contact with the fixed charge film and is provided at a position that faces the sensor pixel312via the fixed charge film. The light receiving lens350is provided in contact with the color filter340and is provided at a position facing the sensor pixel312via the color filter340and the fixed charge film. The first substrate unit310has a plurality of FD through wirings315, and a plurality of VSS through wirings316in the insulating layer319. The plurality of FD through wirings315and the plurality of VSS through wirings penetrate the insulating layer319. Each VSS through wiring316is disposed in a gap between two FD penetration wirings315adjacent to each other in the plurality of FD penetration wirings315. The first substrate unit310further has a plurality of FD junction electrodes317, and one VSS junction electrode318in the insulating layer319. The plurality of FD junction electrodes317and the one VSS junction electrode318are both exposed on a front surface of the insulating layer319. The plurality of FD through wirings315and the plurality of VSS through wirings316are provided in a region facing the pixel region313. Each VSS junction electrode318is formed in the same plane as each FD junction electrode317. The VSS junction electrode318is disposed in a gap between two FD junction electrodes317adjacent to each other in the plurality of FD junction electrodes317. In a case in which one floating diffusion FD is provided for a plurality of sensor pixels312that share the read circuit322, the plurality of FD through wirings315are provided one by one for each of the plurality of sensor pixels312that share the read circuit322. In a case in which one floating diffusion FD is provided for one sensor pixel312, a plurality of FD through wirings315are provided one by one for each sensor pixel312. Each FD through wiring315is connected to the floating diffusion FD and the FD junction electrode317. In a case in which one floating diffusion FD is provided for a plurality of sensor pixels312that share the read circuit322, the plurality of VSS through wirings316are provided one by one for each of the plurality of sensor pixels312that share the read circuit322. In a case in which one floating diffusion FD is provided for one sensor pixel312, the plurality of VSS through wirings316are provided one by one for each sensor pixel312. Each VSS through wiring316is connected to the P-well region341and the VSS junction electrode318. In any case, the plurality of VSS through wirings316are provided one by one for each read circuit322. The second substrate unit320is configured by laminating an insulating layer328on the semiconductor substrate321. The second substrate unit320has the insulating layer328as an interlayer insulating film. The insulating layer328is provided between the semiconductor substrate321and the first substrate unit310. The semiconductor substrate321is configured of a silicon substrate. The second substrate unit320has one read circuit322for every four sensor pixels312. The second substrate unit320has a configuration in which the read circuit322is provided on a portion on the front surface side (third substrate unit330side) of the semiconductor substrate321. The second substrate unit320is bonded to the first substrate unit310with the front surface of the semiconductor substrate321facing the front surface side of the semiconductor substrate311. The second substrate unit320has a plurality of FD through wirings326and a plurality of VSS through wirings327in the insulating layer328. The plurality of FD through wirings326and the plurality of VSS through wirings327penetrate the insulating layer328. Each VSS through wiring327is disposed in a gap between two FD through wirings326adjacent to each other in the plurality of FD through wirings326. The second substrate unit320further has a plurality of FD junction electrodes324and one VSS junction electrode325in the insulating layer328. The plurality of FD junction electrodes324and one VSS junction electrode325are both exposed on a front surface of the insulating layer328. The plurality of FD junction electrodes324are provided one by one for each FD junction electrode317of the first substrate unit310. The FD junction electrode324is electrically connected to the FD junction electrode317. The FD junction electrode324and the FD junction electrode317are made of, for example, copper and are bonded to each other. The VSS junction electrode325is electrically connected to the VSS junction electrode318of the first substrate unit310. The VSS junction electrode325and the VSS junction electrode318are made of, for example, copper and are bonded to each other. Each VSS junction electrode325is formed in the same plane as each FD junction electrode324. The VSS junction electrode325is disposed in a gap between two FD junction electrodes324adjacent to each other in the plurality of FD junction electrodes324. The sensor pixel312and the read circuit322are electrically connected to each other by joining the FD junction electrodes317and24to each other. The FD junction electrodes317and324are disposed at positions facing the floating diffusions FD. In a case in which the floating diffusion FD is shared by four sensor pixels312, the floating diffusion FD is provided in a central portion of a region consisting of four sensor pixels312. Accordingly, in a case in which the floating diffusion FD is shared by the four sensor pixels312, each of the FD junction electrodes317and324is disposed at positions facing the central portion of the region consisting of four sensor pixels312. Each of the FD junction electrodes317and324has, for example, a rectangular shape. The plurality of FD junction electrodes324and the plurality of FD through wiring326are provided in a region facing the pixel region313. The plurality of FD through wirings326are provided one by one for each FD through wiring315. Each FD through wiring326is connected to the FD junction electrode324and the read circuit322(specifically, the gate of the amplification transistor AMP). The plurality of VSS junction electrodes325and the plurality of VSS through wiring327are provided in the region facing the pixel region313. The plurality of VSS through wiring327are provided one by one for each VSS through wiring316. Each VSS through wiring327is connected to a VSS junction electrode325and a region (a reference potential region of the read circuit322) to which the reference potential VSS is applied in the second substrate unit320. A laminate configured of the first substrate unit310and the second substrate unit320has the plurality of through wirings342that penetrate the first substrate unit310and the second substrate unit320in the region around the pixel region313. The plurality of through wirings342are provided one by one for each drive wiring314of the first substrate unit310. Each through wiring342is connected to the drive wiring314and the vertical drive circuit of the logic circuit332. Accordingly, the logic circuit332controls the sensor pixels312and the read circuit322via the plurality of through wirings342. Each through wiring342is configured of a through silicon via (TSV). Also, instead of each through wiring342, a through wiring that penetrates the insulating layer319(hereinafter referred to as a “through wiring a”), a through wiring that penetrates the insulating layer328(hereinafter referred to as a “through wiring b”), a junction electrode connected to the through wiring a (hereinafter referred to as a “junction electrode c”), and a junction electrode connected to the through wiring b (hereinafter referred to as a “junction electrode d”) may be provided. In this case, the junction electrodes c and d are made of, for example, copper, and the junction electrodes c and d are joined to each other. The laminate configured of the first substrate unit310and the second substrate unit320further has a through wiring343and a through wiring344that penetrate the first substrate unit310and the second substrate unit320around the pixel region313. The through wirings343and344are configured of TSVs. The through wiring343is connected to the booster circuit333of the third substrate unit330and has a potential (power supply potential) of the power supply line VDD. The power supply potential is, for example, a value in the range of 2.5V to 2.8V. The through wiring344is electrically connected to a region (reference potential region of the third substrate unit330) to which the reference potential VSS is applied in the third substrate unit330and has a reference potential VSS. The reference potential VSS is, for example, zero volt. The third substrate unit330is configured by laminating an insulating layer336on the semiconductor substrate331. The third substrate unit330has the insulating layer336as an interlayer insulating film. The insulating layer336is provided between the semiconductor substrate331and the second substrate unit320. The semiconductor substrate331is configured of a silicon substrate. The third substrate unit330has a configuration in which the logic circuit332is provided on a portion on the front surface side (second substrate unit320side) of the semiconductor substrate331. The third substrate unit330is bonded to the second substrate unit320with the front surface of the semiconductor substrate331facing the back surface side of the semiconductor substrate321. The read circuit322shown inFIG.20has the amplification transistor AMP (seeFIG.21), the reset transistor RST (seeFIG.21), and the selection transistor SEL (seeFIG.21). At least the amplification transistor AMP among the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL has a fin structure as shown inFIGS.5to7. In the fin-shaped semiconductor layer (for example, the semiconductor substrate321) of the amplification transistor AMP, crystal planes of the first side surface and the second side surface located on both sides in the channel width direction are (100) planes. Thus, the second specific example of the imaging device can reduce the interface state of the semiconductor layer in which the channel of the amplification transistor AMP is formed, and can reduce noise (for example, 1/f noise) caused by the interface state. In addition, in the second specific example, the reset transistor RST and the selection transistor SEL may have a fin structure like the amplification transistor AMP or may have a structure different from that of the amplification transistor AMP (for example, a planar structure). <Examples of Application to Electronic Devices> For example, the technique according to the present disclosure (the present technique) can be applied to various electronic devices such as an imaging system such as a digital still camera, a digital video camera, or the like (hereinafter collectively referred to as a camera), a mobile device such as a mobile phone having an imaging function, or other devices having an imaging function. For example, the present technique can be applied to an electronic device having an imaging function. FIG.23is a conceptual diagram showing an example in which the technique according to the present disclosure (the present technique) is applied to an electronic device300. As shown inFIG.23, the electronic device300is, for example, a camera and has a solid-state imaging device401, an optical lens410, a shutter device411, a drive circuit412, and a signal processing circuit413. The optical lens410is an example of the “optical component” of the present disclosure. Light transmitted through the optical lens410is incident on the solid-state imaging device401. For example, the optical lens410forms an image of image light (incident light) from a subject on an imaging surface of the solid-state imaging device401. Thus, signal charges are accumulated in the solid-state imaging device401for a certain period of time. The shutter device411controls a light irradiation period and a light blocking period for the solid-state imaging device401. The drive circuit412supplies a drive signal for controlling a transfer operation of the solid-state imaging device401and a shutter operation of the shutter device411. Signal transfer of the solid-state imaging device401is performed by the drive signal (timing signal) supplied from the drive circuit412. The signal processing circuit413performs various signal processing. For example, the signal processing circuit413processes a signal output from the solid-state imaging device401. A video signal that has undergone signal processing is stored in a storage medium such as a memory, or is output to a monitor. In the electronic device300, one or more of the imaging device100according to the first embodiment, the imaging device100A according to the second embodiment, and the imaging devices according to the first and second specific examples described above are applied to the solid-state imaging device401. Thus, it is possible to obtain the electronic device300with improved performance. Also, the electronic device300is not limited to the camera. The electronic device300may be a mobile device such as a mobile phone having an imaging function, or other devices having an imaging function. Other Embodiments As mentioned above, the present disclosure has been described with the embodiments and the modified examples, but descriptions and figures that form a part of the present disclosure should not be understood as limiting the present disclosure. It is to be understood that various alternative embodiments, examples, and operable techniques will become apparent from the present disclosure to those skilled in the art. It is needless to say that the present technique includes various embodiments that are not described here. At least one of various omissions, substitutions and modifications of constituent elements may be made without departing from the gist of the embodiments, the modified examples, and the specific examples described above. Also, the effects described in the present specification are merely exemplary and not intended as limiting, and other effects may be obtained. Further, the present disclosure may also have the following structures. (1) An imaging device including: a light receiving element; and a read circuit configured to read an electrical signal photoelectrically converted by the light receiving element, wherein a field effect transistor included in the read circuit includes a semiconductor layer in which a channel is formed, a gate electrode configured to cover the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode, the semiconductor layer includes a main surface, and a first side surface located on one end side of the main surface in a gate width direction of the field effect transistor, the gate electrode includes a first portion configured to face the main surface via the gate insulating film, and a second portion configured to face the first side surface via the gate insulating film, and a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane. (2) The imaging device according to the above (1), wherein the semiconductor layer further includes a second side surface located on the other end side of the main surface in the gate width direction, the gate electrode further includes a third portion configured to face the second side surface via the gate insulating film, and a crystal plane of the second side surface is a (100) plane or a plane equivalent to the (100) plane. (3) The imaging device according to the above (1) or (2), wherein a crystal plane of the main surface is a (100) plane or a plane equivalent to the (100) plane. (4) The imaging device according to any one of the above (1) to (3), wherein the read circuit includes, as the field effect transistor, an amplification transistor configured to amplify the electric signal. (5) The imaging device according to the above (4), wherein the read circuit further includes, as the field effect transistor, a selection transistor configured to switch connection between the amplification transistor and a signal line on or off. (6) The imaging device according to the above (4) or (5), wherein the read circuit further includes, as the field effect transistor, a reset transistor configured to switch connection between the floating diffusion for temporarily holding the electric signal output from the light receiving element and a power supply line on or off. (7) The imaging device according to any one of the above (1) to (6), wherein the field effect transistor includes a plurality of the semiconductor layers, and the plurality of the semiconductor layers are disposed side by side at intervals in the gate width direction of the field effect transistor. (8) An electronic device comprising: an optical component; an imaging device on which light transmitted through the optical component is incident; and a signal processing circuit configured to process a signal output from the imaging device, wherein the imaging device includes a light receiving element; and a read circuit configured to read an electric signal photoelectrically converted by the light receiving element, a field effect transistor included in the read circuit includes a semiconductor layer in which a channel is formed, a gate electrode configured to cover the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode, the semiconductor layer includes a main surface, and a first side surface located on one end side of the main surface in a gate width direction of the field effect transistor, the gate electrode includes a first portion configured to face the main surface via the gate insulating film, and a second portion configured to face the first side surface via the gate insulating film, and a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane. REFERENCE SIGNS LIST 1Field effect transistor1D Drain1G Gate electrode1S Source2Semiconductor layer2b,21bFirst side surface2c,21cSecond side surface3Semiconductor wafer3aUpper surface3N Notch15Gate insulating film20Gate insulating film21Semiconductor layer21aUpper surface25Gate insulating film30Gate electrode31First portion32Second portion33Third portion41Source region42Drain region43P-well region46,57Interlayer insulating film47N type impurity diffusion layer48P+type impurity diffusion layer52Insulating film54Through wiring55Wiring59Through wiring100,100A,100B Imaging device110First substrate unit111Semiconductor substrate112Sensor pixel113Pixel region120Second substrate unit121Semiconductor substrate122Read circuit123Pixel drive line124Vertical signal line130Third substrate unit131Semiconductor substrate132Logic circuit133Vertical drive circuit134Column signal processing circuit135Horizontal drive circuit136System control circuit300Electronic device401Solid-state imaging device410Optical lens411Shutter device412Drive circuit413Signal processing circuitAG, RG, SG Gate electrodeAMP Amplification transistorRST Reset transistorSEL Selection transistorTG Transfer gateTG Gate (transfer gate)TR Transfer transistor | 77,917 |
11942494 | MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present disclosure will be described on the basis of embodiments with reference to the drawings. The present disclosure is not limited to the embodiments, and various numerical values and materials in the embodiments are examples. In the following description, the same elements or elements having the same function will be denoted by the same symbols, without redundant description. Note that the description will be given in the following order.1. Description of imaging device according to present disclosure and general2. First Embodiment3. Application Example4. Configuration of present disclosure Description of Imaging Device According to Present Disclosure and General As described above, the imaging device according to the present disclosure isan imaging device including:a wiring substrate;an image sensor package mounted on the wiring substrate;a package frame attached to a light receiving surface side of the image sensor package; anda lens holder arranged to cover the package frame and holding a lens unit so that the lens unit faces the light receiving surface of the image sensor package, in whichthe package frame includes a material having a larger coefficient of linear expansion than a material of the lens holder, and includes a wall portion that extends in a direction perpendicular to the wiring substrate toward the wiring substrate,a gap is provided between the wall portion of the package frame and the image sensor package, and between an end of the wall portion of the package frame and the wiring substrate,the lens holder includes a wall portion facing the wall portion of the package frame, andan end of the wall portion of the lens holder is fixed to the end of the wall portion of the package frame while being separated from the wiring substrate. In the imaging device of the present disclosure,the material of the package frame and a length of the wall portion of the package frame extending in the direction perpendicular to the wiring substrate, and the material of the lens holder and a length of the wall portion of the lens holder extending in the direction perpendicular to the wiring substrate can be selected, so that a distance between the light receiving surface of the image sensor package and the lens unit is kept constant regardless of an ambient temperature. Alternatively, in the imaging device of the present disclosure,the material of the package frame and a length of the wall portion of the package frame extending in the direction perpendicular to the wiring substrate, and the material of the lens holder and a length of the wall portion of the lens holder extending in the direction perpendicular to the wiring substrate can be set, so that a distance between the light receiving surface of the image sensor package and the lens unit changes with a predetermined sensitivity according to an ambient temperature. In this case, the change in the distance between the light receiving surface of the image sensor package and the lens unit with the predetermined sensitivity according to the ambient temperature can compensate for an influence of a characteristic change of the lens unit that occurs according to the ambient temperature. In the imaging device of the present disclosure including the above-described various preferable configurations, the package frame can include a resin material. In particular, it is preferable to select an epoxy resin material having a relatively large coefficient of linear expansion among the resin materials. In the imaging device of the present disclosure including the above-described various preferable configurations, the lens holder can include a metal material. In particular, it is preferable to select a material such as aluminum or aluminum alloy, which has a relatively small coefficient of linear expansion, among the metal materials. In the imaging device of the present disclosure including the above-described various preferable configurations, a lens included in the lens unit may include a glass material or a plastic material. Generally, a plastic lens is cheaper than a glass lens, but its optical characteristics change largely with temperature. Even in this case, by performing setting so that the distance between the light receiving surface of the image sensor package and the lens unit changes with a predetermined sensitivity according to the ambient temperature, it is possible to effectively curb deterioration of resolution due to the temperature change. In the imaging device of the present disclosure including the above-described various preferable configurations, a cushion member can be arranged between the end of the wall portion of the lens holder and the wiring substrate. The cushion member can prevent entry of dust and the like. The cushion member preferably includes a sponge material so as not to hinder the shape change of the package frame due to thermal expansion. In the imaging device of the present disclosure including the above-described various preferable configurations, the end of the wall portion of the lens holder can be fixed to a surface of a flange provided on the end of the wall portion of the package frame. Alternatively, a side surface near the end of the wall portion of the lens holder can be fixed to a side surface near the end of the wall portion of the package frame, a side surface near the end of the wall portion of the lens holder can be fixed to a side surface near the end of the wall portion of the package frame by a fixing member, or a side surface near the end of the wall portion of the lens holder can be fixed to a side surface near the end of the wall portion of the package frame by fitting. Additionally, a step for setting a mounting position of the lens holder can be provided near the end of the wall portion of the package frame. The image sensor used in the image sensor package is not particularly limited. For example, it is possible to use an image sensor such as a CMOS sensor or a CCD sensor in which pixels including photoelectric conversion elements and various pixel transistors are arranged in a two-dimensional matrix in the row direction and the column direction. The image sensor may be configured to capture a monochrome image or may be configured to capture a color image. In the case of capturing a color image, a color filter is usually arranged on the light incident surface side of a photoelectric conversion unit. For example, in the case of capturing a color image in a Bayer array, color imaging is performed using a group of photoelectric conversion elements corresponding to [red, green, green, blue]. While examples of the pixel values of the image sensor include resolutions for image display such as U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536), (3840, 2160), and (7680, 4320), the values are not limited to these values. Various conditions of the present specification are satisfied not only in a case where the conditions are mathematically strictly established, but also in a case where the conditions are substantially established. Various variations caused by design or manufacturing are permissible. Additionally, drawings used in the following description are schematic, and do not show actual dimensions or the ratio thereof. For example,FIG.1to be described later shows a cross-sectional structure of an imaging device, but does not show the ratio of width, height, thickness, and the like. First Embodiment A first embodiment relates to an imaging device according to the present disclosure. FIG.1is a schematic cross-sectional view for describing the structure of the imaging device according to the first embodiment. First, an outline of the imaging device will be described. An imaging device1shown inFIG.1includes:a wiring substrate60;an image sensor package40mounted on the wiring substrate60;a package frame30attached to the light receiving surface side of the image sensor package40; anda lens holder20arranged so as to cover the package frame30and holding a lens unit10so that the lens unit10faces a light receiving surface of the image sensor package40. The image sensor package40includes a chip-shaped image sensor43in which pixels including photoelectric conversion units are arranged in a two-dimensional matrix, a package substrate44provided with connection wiring to the image sensor43, a transparent seal glass41arranged on the light receiving surface side of the image sensor43, a sealing member42, and the like. The image sensor package40is mounted on the wiring substrate60by joining the package substrate44and the wiring substrate60by solder bumps50. The package frame30includes a material having a larger coefficient of linear expansion than a material of the lens holder20. Specifically, the lens holder20includes a metal material such as aluminum, and the package frame30includes an epoxy resin material. The package frame30has a coefficient of linear expansion of about several times to ten times that of the lens holder20, depending on the selected material. The package frame30includes a wall portion31that extends in a direction perpendicular to the wiring substrate60toward the wiring substrate60, and a gap is provided between the wall portion31of the package frame30and the image sensor package40, and between an end of the wall portion30of the package frame30and the wiring substrate60. These gaps are indicated by symbols GP1and GP2. The package frame30has an opening corresponding to the light receiving surface of the image sensor package40, has a shape that covers the image sensor package40, and can take various forms. The appearance of the package frame30will be described later with reference to later-mentionedFIGS.16A,16B,17A,17B,17C,18A,18B,19A, and19B. The lens holder20includes a wall portion21that faces the wall portion31of the package frame30. An end of the wall portion21of the lens holder20is fixed to the end of the wall portion31of the package frame30while being separated from the wiring substrate60. More specifically, the end of the wall portion21of the lens holder20is fixed to a surface of a flange provided at the end of the wall portion31of the package frame30. The lens unit10held by the lens holder20includes lenses11,11A, and11B and a barrel portion12. The lens included in the lens unit10includes a glass material or a plastic material. Generally, optical characteristics of a lens including a glass material do not change largely by temperature change. In such a case, the material of the package frame30and the length of the wall portion of the package frame30extending in a direction perpendicular to the wiring substrate60, and the material of the lens holder20and the length of the wall portion of the lens holder20extending in a direction perpendicular to the wiring substrate60are selected, so that the distance between the light receiving surface of the image sensor package40and the lens unit10is kept constant regardless of the ambient temperature. On the other hand, optical characteristics of a lens including a plastic material change largely by temperature change. Usually, the characteristics of the lens change in such a manner that the focal length is extended by thermal expansion. In such a case, the material of the package frame30and the length of the wall portion of the package frame30extending in a direction perpendicular to the wiring substrate60, and the material of the lens holder20and the length of the wall portion of the lens holder20extending in a direction perpendicular to the wiring substrate60are set, so that the distance between the light receiving surface of the image sensor package40and the lens unit10changes with a predetermined sensitivity according to the ambient temperature. Then, the change in the distance between the light receiving surface of the image sensor package40and the lens unit10with a predetermined sensitivity according to the ambient temperature compensates for the influence of the characteristic change of the lens unit10that occurs according to the ambient temperature. The outline of the imaging device1has been described above. Next, in order to facilitate understanding of the present disclosure, first, a problem of the imaging device of a reference example will be described. FIG.2is a schematic cross-sectional view for describing the structure of an imaging device according to the reference example.FIG.3is a schematic cross-sectional view for describing the influence of thermal expansion in the imaging device according to the reference example. In an imaging device9shown inFIG.2, an end of a wall portion21A of a lens holder20A is fixed to a wiring substrate60. The length of the wall portion21A at a certain predetermined reference temperature is indicated by symbol L1, and the distance between a light receiving surface of an image sensor package40and the lens unit10is indicated by symbol L3. The description will be given on the assumption that focus characteristics are optimized when the positional relationship between an end of the lens unit10and the image sensor package40is in this state. In the imaging device9shown inFIG.2, when there is a temperature change indicated by a symbol ΔT from the certain predetermined reference temperature, the length of the wall portion21A of the lens holder20A changes and the resolution of the imaging device9decreases. This will be described with reference toFIG.3. When the coefficient of linear expansion of the material of the lens holder20A is indicated by a symbol al, the length of the wall portion21A is (1+α1×ΔT)×L1. Accordingly, the distance between the light receiving surface of the image sensor package40and the lens unit10is L3+α1×ΔT×L1. Hence, when there is a temperature change indicated by the symbol ΔT, the image sensor package40is separated from the lens unit10by the amount indicated by α1×ΔT×L1. For this reason, focus shift occurs and the resolution decreases. The problem of the imaging device of the reference example has been described above. Subsequently, the configuration of the imaging device1will be described in detail. For convenience of description, here, it is assumed that the influence of thermal expansion of the components of the image sensor package can be ignored. FIG.4is a schematic cross-sectional view for describing a state when the imaging device according to the first embodiment is at a reference temperature. As shown inFIG.4, in the imaging device1, at a certain predetermined reference temperature, the length of the wall portion21is indicated by a symbol L1, the length of the wall portion31is indicated by a symbol L2, and the distance between the light receiving surface of the image sensor package40and the lens unit10is indicated by a symbol L3. The description will be given on the assumption that focus characteristics are optimized when the positional relationship between an end of the lens unit10and the image sensor package40is in this state. FIG.5is a schematic cross-sectional view for describing a state when the temperature of the imaging device according to the first embodiment changes by ΔT from the reference temperature. When the coefficient of linear expansion of the material of the lens holder20A is indicated by a symbol α1, the length of the wall portion21is (1+α1×ΔT)×L1. Additionally, when the coefficient of linear expansion of the material of the package frame30is indicated by a symbol α2, the length of the wall portion31is (1+α1×ΔT)×L2. Since the wall portion31thermally expands toward the wiring substrate60, the distance between the light receiving surface of the image sensor package40and the lens unit10is L3+(α1×L1−α2×L2)×ΔT. Accordingly, when (α1×L1−α2×L2) is selected to be substantially 0, the distance between the light receiving surface of the image sensor package40and the lens unit10is kept constant regardless of the ambient temperature. Since optical characteristics of a lens including a glass material usually do not change largely by temperature change, it is preferable that the distance between the light receiving surface of the image sensor package40and the lens unit10is kept constant. On the other hand, optical characteristics of a lens including a plastic material change largely by temperature change. First, the characteristic change of the lens unit will be described. FIG.6is a schematic diagram for describing the image formation state of the lens unit at the reference temperature and the image formation state of the lens unit at the temperature changed by ΔT. Usually, in a lens including a plastic material, the focal length tends to become longer as the temperature rises. When the temperature change coefficient of the focal length is indicated by a symbol β1, the focal length changes by β1×ΔT when the temperature changes by ΔT from the reference temperature. In such a case, when (α1×L1−α2×L2) is selected to be substantially equal to β1, the distance between the light receiving surface of the image sensor package40and the lens unit10is set so as to change with a predetermined sensitivity according to the ambient temperature. Additionally, the change in the distance between the light receiving surface of the image sensor package40and the lens unit10with a predetermined sensitivity according to the ambient temperature can compensate for the influence of the characteristic change of the lens unit10that occurs according to the ambient temperature. Additionally, in a case where the influence of thermal expansion of the components of the image sensor package40cannot be ignored, it is only required to select the values of (α1×L1−α2×L2) so as to compensate for this characteristic change. The configuration of the imaging device1has been described above in detail. Various modifications can be made in the imaging device1. Hereinafter, various modifications will be described with reference to the drawings. FIG.7is a schematic cross-sectional view for describing a first modification according to the first embodiment. In an imaging device1A shown inFIG.7, a cushion member70is arranged between an end of a wall portion of a lens holder20and a wiring substrate60. The cushion member70includes a sponge material. The cushion member70can prevent entry of dust and the like. FIG.8is a schematic cross-sectional view for describing a second modification according to the first embodiment. In the imaging device1shown inFIG.1, the end of the wall portion of the lens holder is fixed to the surface of the flange provided at the end of the wall portion of the package frame. On the other hand, in an imaging device1B shown inFIG.8, a side surface near an end of a wall portion21of a lens holder20is fixed to a side surface near an end of a wall portion31of a package frame30. Reference numeral71indicates a fixed portion. FIG.9is a schematic cross-sectional view for describing a third modification according to the first embodiment. In an imaging device1C shown inFIG.9, a side surface near an end of a wall portion21of a lens holder20is fixed to a side surface near an end of a wall portion31of a package frame30by a fixing member73. Reference numeral72indicates a receiving surface provided on the side surfaces. FIG.10is a schematic cross-sectional view for describing a fourth modification according to the first embodiment. In an imaging device1D shown inFIG.10, a side surface near an end of a wall portion21of a lens holder20is fixed to a side surface near an end of a wall portion31of a package frame30by fitting. Reference numeral22indicates a protrusion provided on the lens holder20. FIG.11is a schematic cross-sectional view for describing a fifth modification according to the first embodiment. In an imaging device1E shown inFIG.11, too, a side surface near an end of a wall portion21of a lens holder20is fixed to a side surface near an end of a wall portion31of a package frame30by fitting. The shape of a protrusion23from the wall portion21and the shape of a recess in the wall portion31are shapes that are easier to fit than inFIG.10. FIG.12is a schematic cross-sectional view for describing a sixth modification according to the first embodiment. In an imaging device1F shown inFIG.12, a positioning groove is formed on a side surface of a wall portion of a package frame30. Reference numeral24indicates a fixed portion positioned by the groove. FIG.13is a schematic cross-sectional view for describing a seventh modification according to the first embodiment. In an imaging device1G shown inFIG.13, steps for setting the mounting position of a lens holder20are provided near an end of a wall portion31of a package frame30. An optimum step can be selected and fixed according to the design. Reference numeral74indicates a fixing member. FIG.14is a schematic cross-sectional view for describing an eighth modification according to the first embodiment. In an imaging device1H shown inFIG.14, too, steps for setting the mounting position of a lens holder20are provided near an end of a wall portion31of a package frame30. An optimum step can be selected and fixed according to the design. FIG.15is a schematic cross-sectional view for describing a ninth modification according to the first embodiment. In an imaging device1J shown inFIG.15, too, steps for setting the mounting position of a lens holder20are provided near an end of a wall portion31of a package frame30. An optimum step can be selected and fixed according to the design. Reference numeral75indicates a fixing member. Various modifications have been described above. Next, the appearance of the package frame and the like will be described. FIGS.16A and16Bare schematic perspective views for describing the appearance of the package frame. As described above, the package frame30has an opening corresponding to the light receiving surface of the image sensor package40, and has a shape that covers the image sensor package40.FIGS.16A and16Bshow an example in which the package frame30has a rectangular outer periphery. The opening may be rectangular as inFIG.16Aor circular as inFIG.16B. FIGS.17A,17B, and17Care schematic perspective views for describing the appearance of the package frame, followingFIG.16B. InFIGS.16A and16B, the flange was provided over the entire outer periphery of the package frame30.FIGS.17A,17B, and17Cshow examples in which a flange is provided in a part of the outer periphery. FIGS.18A and18Bare schematic perspective views for describing the appearance of the package frame, followingFIG.17C.FIGS.18A and18Bshow an example in which the outer periphery of the package frame is circular. The opening may be rectangular as inFIG.18Aor circular as inFIG.18B. FIGS.19A and19Bare schematic perspective views for describing the appearance of the package frame, followingFIG.18B.FIGS.19A and19Bare schematic diagrams illustrating an example of a package frame having no flange. FIG.20is a schematic perspective view for describing a joining state of the package frame and the lens holder.FIG.20shows an example in which an end of the wall portion of the lens holder is fixed to the surface of the flange provided at an end of the wall portion of the package frame. In the various imaging devices according to the present disclosure described above, the package frame includes a material having a larger coefficient of linear expansion than the material of the lens holder, and the package frame includes a wall portion that extends in a direction perpendicular to the wiring substrate toward the wiring substrate. A gap is provided between the wall portion of the package frame and the image sensor package, and between the end of the wall portion of the package frame and the wiring substrate. Then, the lens holder includes a wall portion that faces the wall portion of the package frame, and the end of the wall portion of the lens holder is fixed to the end of the wall portion of the package frame while being separated from the wiring substrate. According to this structure, the change in shape due to thermal expansion of the package frame and the lens holder is offset, so that reduction in resolution due to the temperature change can be more effectively curbed. Application Example The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be implemented as a device mounted on any type of movable bodies including a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), and the like. FIG.21is a block diagram showing a schematic configuration example of a vehicle control system7000which is an example of a mobile control system to which the technology according to the present disclosure can be applied. The vehicle control system7000includes multiple electronic control units connected through a communication network7010. In the example shown inFIG.21, the vehicle control system7000includes a drive system control unit7100, a body system control unit7200, a battery control unit7300, an outside information detection unit7400, an inside information detection unit7500, and an integrated control unit7600. The communication network7010connecting the multiple control units may be an on-vehicle communication network compliant with an arbitrary standard such as controller area network (CAN), local interconnect network (LIN), local area network (LAN), and FlexRay (registered trademark), for example. Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores a program executed by the microcomputer or parameters used for various arithmetic operations, and a drive circuit that drives various devices to be controlled. Each control unit includes a network I/F for communicating with other control units through the communication network7010, and a communication I/F for communicating with devices, sensors, or the like inside or outside the vehicle by wired communication or wireless communication. InFIG.21, as the functional configuration of the integrated control unit7600, a microcomputer7610, a general-purpose communication I/F7620, a dedicated communication I/F7630, a positioning unit7640, a beacon receiving unit7650, an in-vehicle device I/F7660, an audio image output unit7670, an in-vehicle network I/F7680, and a storage unit7690are illustrated. The other control units similarly include a microcomputer, a communication I/F, a storage unit, and the like. The drive system control unit7100controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit7100functions as a controller of a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates a braking force of the vehicle, and the like. The drive system control unit7100may have a function as a controller such as an antilock brake system (ABS) or an electronic stability control (ESC). A vehicle state detection unit7110is connected to the drive system control unit7100. The vehicle state detection unit7110includes, for example, at least one of a gyro sensor that detects the angular velocity of the shaft rotational movement of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor for detecting an accelerator pedal operation amount, a brake pedal operation amount, a steering wheel steering angle, an engine speed, a wheel rotation speed, or the like. The drive system control unit7100performs arithmetic processing using a signal input from the vehicle state detection unit7110to control an internal combustion engine, a drive motor, an electric power steering device, a brake device, or the like. The body system control unit7200controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit7200functions as a controller of a keyless entry system, a smart key system, a power window device, or various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp. In this case, the body system control unit7200may receive input of radio waves transmitted from a portable device substituting a key or signals of various switches. The body system control unit7200receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle. The battery control unit7300controls a secondary battery7310that is the power supply source of the drive motor according to various programs. For example, the battery control unit7300receives input of information such as the battery temperature, the battery output voltage, or the remaining capacity of the battery from a battery device including the secondary battery7310. The battery control unit7300performs arithmetic processing using these signals to control the temperature adjustment of the secondary battery7310or control a cooling device or the like provided in the battery device. The outside information detection unit7400detects information outside the vehicle equipped with the vehicle control system7000. For example, at least one of an imaging unit7410or an outside information detection portion7420is connected to the outside information detection unit7400. The imaging unit7410includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, or other cameras. The outside information detection portion7420includes at least one of an environment sensor for detecting the current weather, or an ambient information detection sensor for detecting another vehicle around the vehicle equipped with the vehicle control system7000, an obstacle, a pedestrian, or the like, for example. The environment sensor may be at least one of a raindrop sensor that detects rainy weather, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, or a snow sensor that detects snowfall, for example. The ambient information detection sensor may be at least one of an ultrasonic sensor, a radar device, or a light detection and ranging or laser imaging detection and ranging (LIDAR) device, for example. The imaging unit7410and the outside information detection portion7420may be provided as independent sensors or devices, or may be provided as a device in which multiple sensors or devices are integrated. Here,FIG.22shows an example of the installation positions of the imaging unit7410and the outside information detection portion7420. For example, imaging units7910,7912,7914,7916, and7918are provided in at least one of positions of a front nose, a side mirror, a rear bumper, a back door, and an upper portion of a windshield in the vehicle interior of a vehicle7900. The imaging unit7910provided on the front nose and the imaging unit7918provided on the upper portion of the windshield in the vehicle interior mainly acquire images of the front of the vehicle7900. The imaging units7912and7914provided on the side mirrors mainly acquire images of the sides of the vehicle7900. The imaging unit7916provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle7900. The imaging unit7918provided on the upper portion of the windshield in the vehicle interior is mainly used to detect a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like. Note thatFIG.22shows an example of the imaging ranges of the imaging units7910,7912,7914, and7916. An imaging range a indicates the imaging range of the imaging unit7910provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units7912and7914provided on the side mirrors, respectively, and an imaging range d indicates the imaging range of the imaging unit7916provided on the rear bumper or the back door. For example, by superimposing the pieces of image data captured by the imaging units7910,7912,7914, and7916, a bird's eye view image of the vehicle7900as viewed from above can be obtained. Outside information detection portions7920,7922,7924,7926,7928, and7930provided on the front, rear, sides, corners, and the upper portion of the windshield in the vehicle interior of the vehicle7900may be ultrasonic sensors or radar devices, for example. The outside information detection portions7920,7926, and7930provided on the front nose, the rear bumper, the back door, and the upper portion of the windshield in the vehicle interior of the vehicle7900may be LIDAR devices, for example. These outside information detection portions7920to7930are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, or the like. Returning toFIG.21, the description will be continued. The outside information detection unit7400causes the imaging unit7410to capture an image of the outside of the vehicle, and receives the captured image data. Additionally, the outside information detection unit7400also receives detection information from the outside information detection portion7420connected thereto. In a case where the outside information detection portion7420is an ultrasonic sensor, a radar device, or a LIDAR device, the outside information detection unit7400causes transmission of ultrasonic waves, electromagnetic waves, or the like, and receives information on the received reflected waves. The outside information detection unit7400may perform object detection processing or distance detection processing of a person, a vehicle, an obstacle, a sign, characters on a road surface, or the like on the basis of the received information. The outside information detection unit7400may perform environment recognition processing for recognizing rainfall, fog, road surface conditions, or the like on the basis of the received information. The outside information detection unit7400may calculate the distance to the object outside the vehicle on the basis of the received information. Additionally, the outside information detection unit7400may perform object recognition processing or distance detection processing of a person, a vehicle, an obstacle, a sign, characters on a road surface, or the like on the basis of the received image data. The outside information detection unit7400may perform processing such as distortion correction or position adjustment on the received image data, combine image data captured by different imaging units7410, and generate a bird's eye view image or a panoramic image. The outside information detection unit7400may perform viewpoint conversion processing using image data captured by different imaging units7410. The inside information detection unit7500detects information inside the vehicle. For example, a driver state detection unit7510that detects a state of a driver is connected to the inside information detection unit7500. The driver state detection unit7510may include a camera that images the driver, a biometric sensor that detects biometric information of the driver, a microphone that collects voice in the vehicle interior, and the like. For example, the biometric sensor is provided on a seat surface, a steering wheel, or the like, and detects biometric information of an occupant sitting in a seat or a driver who grips a steering wheel. The inside information detection unit7500may calculate the degree of fatigue or concentration of the driver or determine whether or not the driver is asleep, on the basis of detection information input from the driver state detection unit7510. The inside information detection unit7500may perform processing such as noise canceling processing on the collected audio signal. The integrated control unit7600controls overall operations in the vehicle control system7000according to various programs. An input unit7800is connected to the integrated control unit7600. The input unit7800is implemented by a device such as a touch panel, a button, a microphone, a switch, or a lever on which an occupant can perform input operation, for example. The integrated control unit7600may receive input of data obtained by voice recognition of voice input by a microphone. The input unit7800may be a remote control device using infrared rays or other radio waves, or an external connection device such as a mobile phone or a personal digital assistant (PDA) compatible with the operation of the vehicle control system7000, for example. The input unit7800may be a camera, for example, in which case the occupant can input information by gesture. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant may be input. Moreover, the input unit7800may include an input control circuit or the like that generates an input signal on the basis of information input by the occupant or the like using the above input unit7800, and outputs the input signal to the integrated control unit7600, for example. By operating the input unit7800, the occupant or the like inputs various data or gives an instruction on a processing operation to the vehicle control system7000. The storage unit7690may include a read only memory (ROM) that stores various programs executed by the microcomputer, and a random access memory (RAM) that stores various parameters, calculation results, sensor values, or the like. Additionally, the storage unit7690may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like. The general-purpose communication I/F7620is a general-purpose communication I/F that mediates communication with various devices existing in an external environment7750. The general-purpose communication I/F7620may implement a cellular communication protocol such as global system of mobile communications (GSM) (registered trademark), WiMAX, long term evolution (LTE) or LTE-advanced (LTE-A), or another wireless communication protocol such as wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). For example, the general-purpose communication I/F7620may connect to a device (e.g., application server or control server) existing in an external network (e.g., Internet, cloud network, or network unique to business operator) through a base station or an access point. Additionally, for example, the general-purpose communication I/F7620may connect with a terminal (e.g., terminal of driver, pedestrian, or store, or machine type communication (MTC) terminal) existing in the vicinity of the vehicle by using the peer to peer (P2P) technology. The dedicated communication I/F7630is a communication I/F that supports a communication protocol designed for use in a vehicle. The dedicated communication I/F7630may implement wireless access in vehicle environment (WAVE), which is a combination of the lower layer IEEE802.11p and the upper layer IEEE1609, dedicated short range communications (DSRC), or a standard protocol such as a cellular communication protocol, for example. The dedicated communication I/F7630performs V2X communication, which is a concept that typically includes one or more of vehicle to vehicle communication, vehicle to infrastructure communication, vehicle to home communication, and vehicle to pedestrian communication. For example, the positioning unit7640receives a global navigation satellite system (GNSS) signal from a GNSS satellite (e.g., (global positioning system (GPS) signal from GPS satellite) to perform positioning and generate position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit7640may specify the current position by exchanging signals with a wireless access point, or may acquire position information from a terminal such as a mobile phone, a PHS, or a smartphone having a positioning function. The beacon receiving unit7650receives radio waves or electromagnetic waves transmitted from a radio station or the like installed on the road, and acquires information such as current location, traffic congestion, traffic restrictions, or required time, for example. Note that the function of the beacon receiving unit7650may be included in dedicated communication I/F7630described above. The in-vehicle device I/F7660is a communication interface that mediates connection between the microcomputer7610and various in-vehicle devices7760existing in the vehicle. The in-vehicle device I/F7660may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or Wireless USB (WUSB). Additionally, the in-vehicle device I/F7660may establish a wired connection such as universal serial bus (USB), high-definition multimedia interface (HDMI) (registered trademark), mobile high-definition link (MHL), or the like through a connection terminal (and, if necessary, a cable) not shown. The in-vehicle device7760may include at least one of a mobile device or a wearable device that an occupant owns, or an information device that is carried in or attached to the vehicle, for example. Additionally, the in-vehicle device7760may include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I/F7660exchanges control signals or data signals with these in-vehicle devices7760. The in-vehicle network I/F7680is an interface that mediates communication between the microcomputer7610and the communication network7010. The in-vehicle network I/F7680transmits and receives signals and the like according to a predetermined protocol supported by the communication network7010. The microcomputer7610of the integrated control unit7600controls the vehicle control system7000according to various programs, on the basis of information acquired through at least one of the general-purpose communication I/F7620, the dedicated communication I/F7630, the positioning unit7640, the beacon receiving unit7650, the in-vehicle device I/F7660, or the in-vehicle network I/F7680. For example, the microcomputer7610may calculate a control target value of the drive force generation device, the steering mechanism, or the braking device on the basis of acquired information on the inside and outside of the vehicle, and output a control command to the drive system control unit7100. For example, the microcomputer7610can perform coordinated control aimed to achieve functions of an advanced driver assistance system (ADAS) including collision avoidance or shock mitigation of a vehicle, follow-up traveling based on an inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, vehicle lane departure warning, or the like. Additionally, the microcomputer7610may control the drive force generation device, the steering mechanism, the braking device, or the like on the basis of acquired information on the surrounding of the vehicle, to perform coordinated control aimed for automatic driving of traveling autonomously without depending on the driver's operation, for example. The microcomputer7610may generate, on the basis of information acquired through at least one of the general-purpose communication I/F7620, the dedicated communication I/F7630, the positioning unit7640, the beacon receiving unit7650, the in-vehicle device I/F7660, or the in-vehicle network I/F7680, three-dimensional distance information between the vehicle and surrounding objects such as structures and persons, and create local map information including peripheral information of the current position of the vehicle. Additionally, the microcomputer7610may predict a risk of a vehicle collision, proximity of a pedestrian or the like, entry into a closed road, or the like on the basis of the acquired information, and generate a warning signal. The warning signal may be a signal for sounding a warning sound or lighting a warning lamp, for example. The audio image output unit7670transmits an output signal of at least one of audio or an image to an output device capable of visually or aurally giving notification of information to an occupant or the outside of the vehicle. In the example ofFIG.21, an audio speaker7710, a display unit7720, and an instrument panel7730are shown as examples of the output device. The display unit7720may include at least one of an onboard display or a head-up display, for example. The display unit7720may have an augmented reality (AR) display function. The output device may be a device other than these devices, such as headphones, a wearable device such as a glasses-type display worn by an occupant, a projector, or a lamp. In a case where the output device is a display device, the display device visually displays results obtained by various processing performed by the microcomputer7610or information received from another control unit in various formats such as text, images, tables, and graphs. Additionally, in a case where the output device is a voice output device, the voice output device converts an audio signal including reproduced voice data, acoustic data, or the like into an analog signal and outputs the analog signal audibly. Note that, in the example shown inFIG.21, at least two control units connected through the communication network7010may be integrated as one control unit. Alternatively, each control unit may include multiple control units. Moreover, the vehicle control system7000may include another control unit not shown. Additionally, in the above description, some or all of the functions of any control unit may be given to another control unit. That is, as long as information is transmitted and received through the communication network7010, the predetermined arithmetic processing may be performed by any control unit. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other through the communication network7010. Of the configurations described above, the technology according to the present disclosure is applicable to the imaging unit of the outside information detection unit, for example. While embodiments of the present disclosure have been specifically described above, the present disclosure is not limited to the above-described embodiments, and various modifications based on the technical idea of the present disclosure are possible. For example, the numerical values, structures, substrates, raw materials, processes, and the like mentioned in the above embodiments are merely examples, and different numerical values, structures, substrates, raw materials, processes, and the like may be used as necessary. Configuration of Present Disclosure Note that the technology of the present disclosure can also be configured in the following manner. [A1] An imaging device including:a wiring substrate;an image sensor package mounted on the wiring substrate;a package frame attached to a light receiving surface side of the image sensor package; anda lens holder arranged to cover the package frame and holding a lens unit so that the lens unit faces the light receiving surface of the image sensor package, in whichthe package frame includes a material having a larger coefficient of linear expansion than a material of the lens holder, and includes a wall portion that extends in a direction perpendicular to the wiring substrate toward the wiring substrate,a gap is provided between the wall portion of the package frame and the image sensor package, and between an end of the wall portion of the package frame and the wiring substrate,the lens holder includes a wall portion facing the wall portion of the package frame, andan end of the wall portion of the lens holder is fixed to the end of the wall portion of the package frame while being separated from the wiring substrate. [A2] The imaging device according to [A1] above, in whichthe material of the package frame and a length of the wall portion of the package frame extending in the direction perpendicular to the wiring substrate, and the material of the lens holder and a length of the wall portion of the lens holder extending in the direction perpendicular to the wiring substrate are selected, so that a distance between the light receiving surface of the image sensor package and the lens unit is kept constant regardless of an ambient temperature. [A3] The imaging device according to [A1] above, in whichthe material of the package frame and a length of the wall portion of the package frame extending in the direction perpendicular to the wiring substrate, and the material of the lens holder and a length of the wall portion of the lens holder extending in the direction perpendicular to the wiring substrate are set, so that a distance between the light receiving surface of the image sensor package and the lens unit changes with a predetermined sensitivity according to an ambient temperature. [A4] The imaging device according to [A3] above, in whichthe change in the distance between the light receiving surface of the image sensor package and the lens unit with the predetermined sensitivity according to the ambient temperature compensates for an influence of a characteristic change of the lens unit that occurs according to the ambient temperature. [A5] The imaging device according to any one of [A1] to [A4] above, in whichthe package frame includes a resin material. [A6] The imaging device according to any one of [A1] to [A5] above, in whichthe lens holder includes a metal material. [A7] The imaging device according to any one of [A1] to [A6] above, in whicha lens included in the lens unit includes a glass material or a plastic material. [A8] The imaging device according to any one of [A1] to [A7] above, in whicha cushion member is arranged between the end of the wall portion of the lens holder and the wiring substrate. [A9] The imaging device according to [A8] above, in whichthe cushion member includes a sponge material. [A10] The imaging device according to any one of [A1] to [A9] above, in whichthe end of the wall portion of the lens holder is fixed to a surface of a flange provided on the end of the wall portion of the package frame. [A11] The imaging device according to any one of [A1] to [A9] above, in whicha side surface near the end of the wall portion of the lens holder is fixed to a side surface near the end of the wall portion of the package frame. [A12] The imaging device according to any one of [A1] to [A9] above, in whicha side surface near the end of the wall portion of the lens holder is fixed to a side surface near the end of the wall portion of the package frame by a fixing member. [A13] The imaging device according to any one of [A1] to [A9] above, in whicha side surface near the end of the wall portion of the lens holder is fixed to a side surface near the end of the wall portion of the package frame by fitting. [A14] The imaging device according to any one of [A1] to [A9] above, in whicha step for setting a mounting position of the lens holder is provided near the end of the wall portion of the package frame. REFERENCE SIGNS LIST 1,9Imaging device10Lens unit11,11A,11B Lens12Lens barrel20Lens holder21Wall portion of lens holder30Package frame31Wall portion of package frame40Image sensor package41Seal glass42Sealing member43Image sensor44Package substrate50Solder bump60Wiring substrate | 51,896 |
11942495 | MODES FOR CARRYING OUT THE INVENTION Next, modes for carrying out the present disclosure (the modes will be hereinafter referred to as embodiments) are described with reference to the drawings. In the drawings mentioned below, the same or similar components are denoted by the same or similar reference numerals. However, the drawings are schematic, and the dimensional ratios and the like of the respective components do not always match the actual ones. Further, it is needless to say that the dimensional relationships and ratios may differ between the drawings. Further, explanation of the embodiments will be made in the following order.1. First Embodiment2. Second Embodiment3. Third Embodiment4. Fourth Embodiment5. Fifth Embodiment6. Sixth Embodiment7. Seventh Embodiment8. Eighth Embodiment9. Ninth Embodiment10. Tenth Embodiment11. Eleventh Embodiment12. Twelfth Embodiment13. Thirteenth Embodiment14. Fourteenth EmbodimentFifteenth Embodiment16. Sixteenth Embodiment17. Seventeenth Embodiment18. Eighteenth Embodiment19. Nineteenth Embodiment20. Configuration of an imaging device21. Example application to a camera 1. First Embodiment [External Shape of an Imaging Apparatus] FIG.1is a diagram showing an example configuration of an imaging apparatus according to an embodiment of the present disclosure. This drawing is a diagram showing an example of the external shape of an imaging apparatus1including an imaging device as a semiconductor chip. A semiconductor device according to the present disclosure is now described, with the imaging apparatus1in the drawing being taken as an example. The imaging apparatus1in the drawing has an imaging device20enclosed in a semiconductor package. In this semiconductor package, a heat releasing plate30and a circuit board40are stacked, and the imaging device20is mounted on the heat releasing plate30. A frame60and a cover glass70constitute a lid unit, and are arranged so as to cover the imaging device20. The circuit board40and the heat releasing plate30are bonded to each other with an adhesive member11(not shown). [Configuration of an Imaging Apparatus] FIG.2is a plan view showing an example configuration of an imaging apparatus according to a first embodiment of the present disclosure. This drawing is a diagram showing example configurations of the circuit board40, the heat releasing plate30, and the imaging device20. The imaging device20is a semiconductor device that captures an image of an object, and is a semiconductor device formed in the shape of a semiconductor chip. In this imaging device20, pixels that generate image signals depending on light from the object are arranged in a two-dimensional grid pattern. The plurality of pixels forms a pixel array unit202. The pixels generate and output image signals on the basis of an input control signal. The control signal is input from the circuit board40to the imaging device20, and the image signals are output from the imaging device20to the circuit board40. Pads201that are electrodes for transmitting signals are disposed around the imaging device20. Note that the imaging device20is an example of the semiconductor chip disclosed in the claims. The heat releasing plate30has the imaging device20disposed thereon, and releases heat from the imaging device20. As will be described later, the imaging device20can be disposed on (bonded to) the heat releasing plate30by die bonding. The imaging device20generates heat during operation. Particularly, in a high-resolution imaging device20, it is necessary to generate and output, at high speed, image signals generated by a large number of pixels, which leads to an increase in power consumption. As a result, the amount of heat generated by the imaging device20increases. Therefore, the imaging device20is disposed on the heat releasing plate30for heat release, so that the imaging device20can be cooled. Meanwhile, the imaging device20and the circuit board40need to exchange signals. This signal exchange can be performed through openings301formed in the heat releasing plate30. This drawing shows an example in which four openings301are formed along the sides of the imaging device20. The four openings301separate the region in which the imaging device20is disposed from the peripheral portions, and the region in the heat releasing plate30in which the imaging device20is disposed is suspended by four beam-like regions. Hereinafter, the region in the heat releasing plate30in which the imaging device20is disposed will be referred to as the semiconductor chip placement region. The heat releasing plate30preferably includes a metal such as copper (Cu). This is because a metal has a relatively low thermal resistance, and heat release properties will improve accordingly. Note that the heat releasing plate30can also include a resin. As described above, the circuit board40transmits signals such as control signals and image signals to the imaging device A semiconductor device such as the imaging device20is used while being connected to electronic circuits, and exchanges signals with the electronic circuits. In the imaging device20, a control signal generated by a control circuit is input to the pixels, and the image signals output from the pixels are processed by a processing circuit. The control circuit and the processing circuit correspond to the electronic circuits. Such electronic circuits can be mounted on the circuit board40. Also, signals may be relayed between the imaging device20, and the control circuit and the processing circuit disposed outside the imaging apparatus1, for example. Like the imaging device the circuit board40also has pads (pads401) disposed thereon. The pads201and the pads401can be connected by conductive wires50. The circuit board40may be a circuit board formed by stacking an insulating layer including a resin such as epoxy or ceramics and a wiring layer including a metal such as Cu, for example. Signals are transmitted through this wiring layer. The adhesive member11bonds the circuit board40to the heat releasing plate30. This adhesive member11is disposed in a region on the outer side of the openings301in the heat releasing plate30, to perform bonding. The adhesive member11may be an adhesive such as resin, for example. Note that the drawing shows an example in which the adhesive member11is disposed on the entire circumference of the edge portion of the heat releasing plate30. The conductive wires50electrically connect the imaging device20and the circuit board40. The conductive wires50connect the pads201of the imaging device20to the pads401of the circuit board40via the openings301of the heat releasing plate30. The conductive wires50may be formed with gold (Au) wires, for example. Also, the connecting of the conductive wires50can be performed by wire bonding, for example. The conductive wires50connect the pads201and the pads401on a one-on-one basis. Note that the conductive wires50are an example of the conductive member disclosed in the claims. FIG.3is a cross-sectional view showing an example configuration of an imaging apparatus according to the first embodiment of the present disclosure. This drawing is a cross-sectional view showing an example configuration of the imaging apparatus1. As shown in the drawing, the imaging device20is bonded to and disposed on the heat releasing plate30with a die bond material13. The frame60is formed in the shape of a wall surrounding the imaging device20, and seals the imaging device20together with the cover glass70. This frame60is bonded to the heat releasing plate30with an adhesive12. The frame60can include a metal or a resin. The cover glass70is a transparent plate that seals the imaging device20. Light from the object is emitted to the imaging device20through the cover glass70. The cover glass70and the frame60are bonded to each other with an adhesive14. In this manner, the circuit board40, the heat releasing plate30, the frame60, and the cover glass70constitute a semiconductor package having a sealed structure. With this semiconductor package, the imaging device20can be hermetically sealed. As shown in the drawing, the openings301are formed in the heat releasing plate30on the outer side of the semiconductor chip placement region. Further, the adhesive member11is disposed on the surface on which the imaging device20is not disposed on the heat releasing plate30on the outer side of the region in which the openings301are formed, and the circuit board40and the heat releasing plate30are bonded to each other. Therefore, the heat releasing plate30and the circuit board40are disposed in a non-fixed state in the region to which the imaging device20is bonded. That is, in the vicinity of the region to which the imaging device20is bonded, the heat releasing plate30is placed movably with respect to the circuit board40. The drawing also shows an example in which an air gap10is formed between the heat releasing plate30and the circuit board40in the vicinity of the region to which the imaging device20is bonded. This air gap10is a gap formed depending on the thickness and the like of the adhesive member11, and may have a thickness of 20 μm, for example. [Method for Manufacturing an Imaging Apparatus] FIGS.4A,4B,4C,4D,5A, and5Bare diagrams showing an example of a method for manufacturing an imaging apparatus according to the first embodiment of the present disclosure.FIGS.4A,4B,4C,4D,5A, and5Bare diagrams showing the process of manufacturing the imaging apparatus1. First, the adhesive member11is disposed on the circuit board40. At this stage, the adhesive member11is disposed in the region on the outer side of the openings301of the heat releasing plate30(FIG.4A). Next, the heat releasing plate30is placed on top of the adhesive member11, to harden the adhesive member11(FIG.4B). As a result, the circuit board40and the heat releasing plate30are bonded to each other. This process corresponds to a bonding process. Next, the imaging device20is disposed on the heat releasing plate30. This can be done by bonding the imaging device20to the heat releasing plate30with the die bond material13(FIG.4C). This process corresponds to a semiconductor chip placement process. Next, the imaging device20and the circuit board40are connected to each other with the conductive wires50via the openings301. This can be done by performing wire bonding (FIG.4D). This process corresponds to a connecting process. Next, the frame60is bonded to the heat releasing plate30with the adhesive12(FIG.5A). Next, the cover glass70is bonded to the frame60with the adhesive14(FIG.5B). Through the process described above, the imaging apparatus1can be manufactured. [Wire Bonding Method] FIG.6is a diagram showing an example of wire bonding according to the first embodiment of the present disclosure. This drawing is a diagram for explaining the wire bonding described inFIG.4D. As described above, the air gap10is formed between the heat releasing plate30and the circuit board40. Therefore, there are cases where the imaging device20moves during the wire bonding, which may cause a positional shift in the bonding. In view of this, the heat releasing plate30is brought into close contact with the circuit board40. Specifically, a hole409is formed in the circuit board40, and the heat releasing plate30is sucked through the hole409, so that the region of the heat releasing plate30in which the imaging device20is placed is brought into close contact with the circuit board40. The white arrow in the drawing indicates the suction of the heat releasing plate30. As a result, the heat releasing plate30is fixed to the circuit board40, and a positional shift during the wire bonding can be prevented. Note that, after the wire bonding, the hole409can be closed with a resin or the like. [Modifications] FIG.7is a plan view showing an example configuration of an imaging apparatus according to a modification of the first embodiment of the present disclosure. The imaging apparatus1in the drawing shows an example in which the pads201are disposed on the two short sides of the imaging device20. Two openings301are formed in the heat releasing plate30, and are arranged adjacent to the two short sides of the imaging device20. FIGS.8A,8B,8C, and8Dare cross-sectional views showing other example configurations of imaging apparatuses according to modifications of the first embodiment of the present disclosure. In the drawing,FIG.8Aindicates an example in which a circuit board41formed with a flexible board is used in place of the circuit board40. As shown inFIG.8Ain the drawing, the circuit board41can be formed in a shape having a portion extended from a lower portion of the heat releasing plate30. The extended portion of the circuit board41can be used as a flexible connector, for example. In the drawing,FIG.8Bindicates an example in which a frame61having mounting holes611formed therein is used. Meanwhile,FIG.8Cin the drawing indicates an example of a heat releasing plate31in which mounting holes311are formed. These mounting holes611and311are holes for screwing the imaging apparatus1to the housing or the heat releasing plate of the apparatus or the like that use the imaging apparatus1. Further,FIG.8Din the drawing indicates an example in which solder balls15are disposed on the bottom of the circuit board40. With the solder balls15, the imaging apparatus1can be mounted on the circuit board of the apparatus that uses the imaging apparatus1. Effects FIGS.9A and9Bare diagrams for explaining the effects of an embodiment of the present disclosure. This drawing is diagrams showing cases where the circuit board40is warped. In the drawing,FIGS.9A and9Bshow cases where the circuit board40is curved downward and upward, respective, to cause warpage in the imaging apparatus1. The circuit board40including an organic material such as a resin has a greater linear expansion coefficient than those of the imaging device20and the heat releasing plate30, and the distortion due to a change in temperature becomes larger. Further, changes in humidity cause expansion and contraction of the circuit board40. Since the circuit board40has a lower rigidity than those of the heat releasing plate30and the like, the circuit board40is warped due to such a change in the shape of the circuit board40with respect to the heat releasing plate and the like. Further, since the semiconductor package of the imaging apparatus1has a closed structure, the internal pressure changes due to fluctuations in atmospheric pressure. In this case, the circuit board40is also warped. Even in such a case, it is possible to prevent the imaging device20from being deformed due to the influence of warpage of the circuit board40. This is because the heat releasing plate is not fixed to the circuit board40in the semiconductor chip placement region, and the warping stress of the circuit board40is not directly applied to the heat releasing plate30in the semiconductor chip placement region. The warping stress of the circuit board40is applied to the heat releasing plate via the adhesive member11. At this stage, stress in the tensile or compressive direction is applied to the heat releasing plate30in the semiconductor chip placement region. Accordingly, the amount of warpage of the imaging device20can be made substantially zero. Further, as described above with reference toFIG.3, in the imaging apparatus1in the drawing, the air gap10is formed between the heat releasing plate30and the circuit board40. Accordingly, even in a case where the circuit board40shown inFIG.9Bin the drawing warps toward the inside of the imaging apparatus1, deformation of the imaging device20can be prevented. On the other hand, in a case where the heat releasing plate and the circuit board40in the region adjacent to the imaging device20are bonded to each other, the heat releasing plate30and the imaging device20are warped due to warpage of the circuit board40. As an image is distorted, the distance between the imaging lens disposed on the outer side of the imaging apparatus1and the surface (the light receiving surface) of the imaging device20changes, resulting in blurring of the image. As described above, in the imaging apparatus1of the first embodiment of the present disclosure, the heat releasing plate30having the imaging device20disposed thereon and the circuit board40are stacked, and the imaging device20and the circuit board40are connected via the openings301formed in the heat releasing plate30. As the heat releasing plate30and the circuit board40are bonded to each other with the adhesive member11in the region on the outer side of the openings301, deformation of the imaging device20due to warpage of the circuit board40can be reduced. As a result, degradation of image quality can be prevented. 2. Second Embodiment The imaging apparatus1of the first embodiment described above includes the circuit board40disposed therein. On the other hand, a second embodiment of the present disclosure differs from the above imaging apparatus1in including electronic components in the circuit board40. As described above, the imaging device20requires electronic circuits such as a circuit that generates a control signal and a circuit that processes an image signal. In a case where such electronic circuits are included in the imaging device20, there is a problem that the configuration of the imaging device20becomes complicated. On the other hand, in a case where electronic circuits are mounted on the surface of the circuit board40or on a board outside the imaging apparatus1, there is a problem that the area occupied by the imaging apparatus1including the attached electronic circuits becomes larger. Therefore, the electronic circuits are included in the circuit board40. This allows the electronic circuits to be disposed in the vicinity of the imaging device20, or, for example, immediately below the imaging device20. [Configuration of an Imaging Apparatus] FIG.10is a cross-sectional view showing an example configuration of an imaging apparatus according to the second embodiment of the present disclosure. The imaging apparatus1in the drawing differs from the imaging apparatus1described above with reference toFIG.3in including a circuit board42in place of the circuit board40. The circuit board42is a circuit board containing semiconductor chips402. The semiconductor chips402are devices that form the electronic circuits connected to the imaging device20. The semiconductor chips402may be an analog-to-digital converter that converts an image signal generated by a pixel of the imaging device20into a digital image signal, and a memory that stores the digital image signal, for example. Such a circuit board42can be manufactured by stacking an insulating layer and a wiring layer on both surfaces of a core substrate that is the circuit board having the semiconductor chips402mounted on its surface, for example. The analog-to-digital converter and the memory mentioned above operate at high speed, and therefore, consume a large amount of power. As a result, when such semiconductor chips402are disposed in the circuit board40, the temperature of the circuit board40rises, and warpage occurs. However, the imaging apparatus1in the drawing can reduce deformation of the imaging device20even in a case where the circuit board40is warped. FIG.11is a cross-sectional view showing another example configuration of an imaging apparatus according to the second embodiment of the present disclosure. The imaging apparatus1in the drawing differs from the imaging apparatus1described above with reference toFIG.3in including a circuit board43in place of the circuit board40. Further, solder balls15are disposed on the bottom of the circuit board43. The circuit board43has recesses403for mounting the elements of electronic circuits. Elements404such as chip resistors forming electronic circuits other than the semiconductor chips402can be disposed in the recesses403, and be mounted by soldering or the like. After that, the semiconductor chips402and the like can be sealed with a sealing resin410. As a result, the scale of the electronic circuits to be mounted can be made larger than those of the circuit board42described above, and elements having different thicknesses can be mounted. The recesses403can be formed in the front surface of the circuit board43on which the imaging device20is disposed, or in the back surface, which is a different surface from the surface on which the imaging device20is disposed. In a conventional imaging apparatus in which the imaging device20is disposed on a circuit board without the heat releasing plate30, in a case where the recesses403are formed in the front surface, the recesses403need to be designed to be smaller in size than the imaging device20. This is to prevent hindrance in the wire bonding of the imaging device20. Therefore, the restrictions on the scale of the electronic circuits mounted in the recesses403become greater. Further, since the imaging device20is disposed on the circuit board in which the recesses403are formed, there are also problems that the contact area between the imaging device20and the circuit board becomes smaller, and heat release from the imaging device20is not sufficient. In a case where the recesses403are formed in the back surface of the circuit board, on the other hand, there is a problem that the region on the back surface of the circuit board on which the solder balls15are disposed becomes narrower. Meanwhile, in the imaging apparatus1in the drawing, the heat releasing plate30is disposed between the imaging device and the circuit board43, and the imaging device20and the circuit board43are connected to each other with the conductive wires50via the openings301in the heat releasing plate30. As a result, in a case where the recesses403are formed in the front surface of the circuit board43, the recesses403can be designed to have a larger area than the imaging device20. This is because the recesses403can be widened to the region to which the conductive wires50are connected. Further, being formed in a different surface from the back surface on which the solder balls15are disposed, the recesses403can be located at positions overlapping the regions in which the solder balls15are disposed. Thus, the regions in which the solder balls15are disposed can be easily ensured. In this manner, the heat releasing plate30is disposed in the imaging apparatus1, and the imaging device20and the circuit board43are connected to each other via the openings301in the heat releasing plate30. Thus, relatively large-scale electronic circuits can be mounted on the circuit board43. Further, the heat releasing plate30and the circuit board43are bonded to each other with the adhesive member11in the region on the outer side of the openings301. Thus, even in a case where the circuit board43is warped, deformation of the imaging device20can be reduced, as in the imaging apparatus1described above with reference toFIG.11. Note that the recesses403can be formed in the back surface of the circuit board43. Further, the recesses403can be formed on both surfaces (the front surface and the back surface) of the circuit board43. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the second embodiment of the present disclosure, the elements of the electronic circuits connected to the imaging device20are included in the circuit board43, and thus, the imaging apparatus1can be made smaller in size. 3. Third Embodiment In the imaging apparatus1of the first embodiment described above, the heat releasing plate30in the region in which the imaging device20is disposed is not bonded to the circuit board40, and the imaging device20is movably placed. On the other hand, an imaging apparatus1of a third embodiment of the present disclosure differs from the first embodiment described above in that restrictions are put on vertical movement of the heat releasing plate30in the region in which the imaging device20is disposed. The imaging device20is disposed on the heat releasing plate30, and the heat releasing plate30having the imaging device20disposed thereon can move with respect to the circuit board40. However, when the imaging device20moves in a vertical direction, the optical path length from the imaging lens disposed outside the imaging apparatus1varies, and therefore, the focal position shifts. As a result, an image is blurred. Therefore, the heat releasing plate30in the region in which the imaging device20is disposed is fixed. This has the effect to restrict vertical movement of the heat releasing plate30in the region in which the imaging device20is disposed. [Configurations of Imaging Apparatuses] FIGS.12A and12Bare cross-sectional views showing example configurations of imaging apparatuses according to the third embodiment of the present disclosure. The imaging apparatuses1in the drawing differ from the imaging apparatus1described above with reference toFIG.3in including locking portions81. The locking portions81are designed to lock the semiconductor chip placement region in the heat releasing plate30. As the heat releasing plate30in the region is locked, vertical movement of the imaging device20can be restricted. Here, the vertical direction is a direction perpendicular to the surface of the imaging device20irradiated with incident light. In the drawing,FIG.12Ais a diagram showing an example of the locking portions81disposed between the frame60and the heat releasing plate30. The upper ends of the locking portions81are bonded to the brim portion of the frame60, and the lower ends of the locking portions81are bonded to the heat releasing plate30. At this stage, the locking portions81can be bonded to the heat releasing plate30with the die bond material13, as shown in the drawing. In the drawing,FIG.12Bis a diagram showing an example of the locking portions81disposed between the cover glass70and the heat releasing plate30. InFIG.12Bin the drawing, the upper ends of the locking portions81are bonded to the cover glass70. The locking portions81can include a metal or a resin, for example. Note that the locking portions81may be bonded to the heat releasing plate30with an adhesive different from the die bond material13. [Arrangement of Locking Portions] FIG.13is a plan view showing an example configuration of locking portions according to the third embodiment of the present disclosure. This drawing is a diagram showing an example arrangement of the locking portions81. As shown in the drawing, the locking portions81can be disposed in the vicinity of the four respective corners of the imaging device20. A method for manufacturing an imaging apparatus1including the locking portions81is now described, with reference to the imaging apparatus1inFIG.12Aas an example. The locking portions81are bonded to the heat releasing plate30after the wire bonding described above with reference toFIG.4Dis performed. Next, an adhesive is applied to the upper ends of the locking portions81. After that, when the frame60described above with reference toFIG.5Ais bonded to the heat releasing plate30, the upper ends of the locking portions81are bonded to the brim portion of the frame60. At this stage, in a case where the hole409described above with reference toFIG.6is formed in the circuit board40, the adhesive is hardened while the lower surface of the heat releasing plate30is pushed upward with a stick-like protruding object via the hole409. Thus, the locking portions81can be bonded to the frame60without fail. Note that the locking portions81may be bonded to the frame60first, and the lower ends of the locking portions81may be bonded to the heat releasing plate30when the frame60is bonded to the heat releasing plate30. [Another Configuration of an Imaging Apparatus] FIG.14is a cross-sectional view showing another example configuration of an imaging apparatus according to the third embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1shown inFIGS.12A and12B, in including locking portions82in place of the locking portions81. The locking portions82each include a hook-like protrusion83at the bottom. The locking portions82hook, with the protrusions83, the heat releasing plate30having the imaging device20disposed thereon. [Another Arrangement of Locking Portions] FIG.15is a plan view showing another example configuration of locking portions according to the third embodiment of the present disclosure. As shown in this drawing, the locking portions82are disposed at positions where the locking portions82partially overlap with the openings301. Note that the locking portions81and82are examples of the lid locking portion disclosed in the claims. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the third embodiment of the present disclosure, the region of the heat releasing plate30on which the imaging device20is disposed is locked to the lid unit with locking portions. Thus, the imaging device20can be prevented from moving in a vertical direction, and degradation of image quality can be avoided. 4. Fourth Embodiment In the imaging apparatus1of the third embodiment described above, the heat releasing plate30in the semiconductor chip placement region is locked to the lid unit. On the other hand, an imaging apparatus1of a fourth embodiment of the present disclosure differs from the third embodiment described above in that the heat releasing plate30in the region in which the imaging device20is disposed is brought into contact with the circuit board40. [Configuration of an Imaging Apparatus] FIG.16is a cross-sectional view showing an example configuration of an imaging apparatus according to the fourth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3in including elastic members84in place of the locking portions81. The elastic members84are designed to bring the heat releasing plate30in the semiconductor chip placement region into contact with the circuit board40. The elastic members84are disposed between the frame60and the heat releasing plate30, and press the heat releasing plate30against the circuit board40, to bring the heat releasing plate30in the semiconductor chip placement region into contact with the circuit board40. The drawing shows an example in which spring-like elastic members84are used. As the elastic members84are compressed and are disposed between the frame60and the heat releasing plate30, the heat releasing plate30can be pressed. As the heat releasing plate30is brought into contact with the circuit board40, it is possible to restrict vertical movement of the imaging device20disposed on the heat releasing plate30. Further, the heat releasing plate30comes into contact with the circuit board40, but is not fixed to the circuit board40. Accordingly, even in a case where the circuit board40is expanded, the heat releasing plate30slides on the surface of the circuit board40, so that the stress in the tensile direction to be applied from the circuit board40to the heat releasing plate30is reduced. Deformation of the imaging device20can be reduced. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the fourth embodiment of the present disclosure, the region of the heat releasing plate30in which the imaging device20is disposed is brought into contact with the circuit board40with the elastic members84. Thus, vertical movement of the imaging device20can be restricted, and degradation of image quality can be prevented. 5. Fifth Embodiment In the imaging apparatus1of the fourth embodiment described above, the heat releasing plate30in the semiconductor chip placement region is brought into contact with the circuit board40with the elastic members84. On the other hand, an imaging apparatus1of a fifth embodiment of the present disclosure differs from the fourth embodiment described above in that the shape of the heat releasing plate is changed to bring the heat releasing plate into contact with the circuit board40. [Configuration of an Imaging Apparatus] FIG.17is a cross-sectional view showing an example configuration of an imaging apparatus according to the fifth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.16in that the elastic members84are eliminated, and the heat releasing plate30is replaced with a heat releasing plate32. The heat releasing plate32includes beam portions302. The beam portions302are beam portions obliquely provided in the direction in which the circuit board40is disposed. Here, the beam portions are beam-like regions connecting the region on the outer side of the openings301in the heat releasing plate to the region on the inner side of the openings301. As the beam portions are obliquely provided, the heat releasing plate in the region in which the imaging device20is disposed can be brought into contact with the circuit board40. [Another Configuration of an Imaging Apparatus] FIG.18is a cross-sectional view showing another example configuration of an imaging apparatus according to the fifth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.17in including a heat releasing plate33and a circuit board44in place of the heat releasing plate32and the circuit board40. The heat releasing plate33is a heat releasing plate including protrusions303. Meanwhile, the circuit board44is a circuit board having holes405. The protrusions303are designed to lock the semiconductor chip placement region to the circuit board44, and bring the semiconductor chip placement region into contact with the circuit board44. The protrusions303can be formed by bending part of the heat releasing plate33in the direction toward the circuit board44. The holes405are holes into which the protrusions303are inserted. [Configuration of a Heat Releasing Plate] FIG.19is a plan view showing an example configuration of a heat releasing plate according to the fifth embodiment of the present disclosure. This drawing is a diagram showing an example configuration of the heat releasing plate33. Dot-and-dash lines in the drawing indicate the protrusions303before the protrusions303are bent in the direction toward the circuit board44described above. Recesses304for securing the protrusions303are formed in the openings301in the drawing. [Method for Manufacturing an Imaging Apparatus] FIGS.20A and20Bare diagrams showing an example of a method for manufacturing an imaging apparatus according to the fifth embodiment of the present disclosure. These diagrams are diagrams showing the process of manufacturing the imaging apparatus1described above with reference toFIG.19. When the heat releasing plate33is bonded to the circuit board44, the protrusions303are inserted into the holes405(FIG.20A). After the adhesive member11is hardened, the tips of the protrusions303are bent in the direction in which the circuit board44is hooked while the semiconductor chip placement region is brought into contact with the circuit board40(FIG.20B). Thus, the semiconductor chip placement region can be brought into contact with the circuit board44. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the fifth embodiment of the present disclosure, the shape of the heat releasing plate30is changed, to bring the semiconductor chip placement region into contact with the circuit board40. Thus, vertical movement of the imaging device20can be prevented, and degradation of image quality can be avoided. 6. Sixth Embodiment This embodiment suggests a cover glass that is used in an imaging apparatus1of one of the embodiments described above. [Material of a Cover Glass] The cover glass70described above with reference toFIG.3may be glass of a material suitable for the purpose of use of the imaging apparatus1. For example, infrared absorbing glass is used, so that the occurrence of ghosts and flares in images can be reduced, and the color balance in the images can be adjusted. Phosphate-based glass, fluorophosphate-based glass, and silicate-based glass can be used as such infrared absorbing glass. Note that fluorophosphate-based glass can also block either near-ultraviolet light or near-infrared light. In a case where infrared light blocking glass with an ultraviolet light transmittance of 50% or higher is used, an ultraviolet cure adhesive can be used as the adhesive14that bonds the cover glass70to the frame60, and the process of manufacturing the imaging apparatus1can be simplified. Note that, to prevent the unhardened adhesive14from moving toward the central portion of the cover glass70at this stage, a groove or a step may be formed in the cover glass70. Further, borosilicate-based glass containing an alkali metal oxide may be used, to improve light resistance. Also, inorganic oxide glass may be used, to improve light resistance and increase strength. [Shape of a Cover Glass] FIGS.21A,21B, and21Care cross-sectional views showing example configurations of imaging apparatuses according to a sixth embodiment of the present disclosure. This drawing is diagrams showing example configurations of the cover glass of the imaging device20. An imaging apparatus1inFIG.21Ain the drawing includes a cover glass71in place of the cover glass70. This cover glass71is a cover glass in which roughened portions701are formed in the regions to be bonded to the frame60. The roughened portions701can increase the adhesive strength with the frame60. The roughened portions701can be formed by performing etching on a surface of the cover glass, for example. In a case where the fluorophosphate-based glass mentioned above is used as the glass of the cover glass71, hardness can be increased by the etching, and vibration resistance can be improved. In a case where the phosphate-based glass is adopted, on the other hand, a chromium (Cr) film may be formed, to form the roughened portions701. An imaging apparatus1inFIG.21Bin the drawing includes a cover glass72in place of the cover glass70. This cover glass72has a concave portion702that is curved toward the inside of the imaging apparatus1. This concave portion702can reduce the occurrence of ghosts and flares in images. In the drawing,FIG.21Cshows an example case where a film73is disposed on the surface of the cover glass70. The film73may be a film73that blocks alpha rays, for example. With this arrangement, errors in image signals can be reduced. Also, a film73including a hygroscopic resin may be used, to prevent dew condensation on the cover glass70, for example. A film73formed with a transparent conductive film may be used, and the film73may be energized and heated, to prevent dew condensation. In this case, the generation of static electricity can also be prevented. Further, in a case where a film73having a light blocking effect is used, entrance of light reflected by a housing or the like can be prevented. As the cover glass70having such a film73disposed thereon is used, productivity can be made higher than that in a case where the film73is provided after the imaging apparatus1is manufactured. Note that a heat-resistant protective film is disposed on the surface of the cover glass70, so that the surface of the cover glass70can be thermally protected. Also, a microlens may be formed on the surface of the cover glass70so that the process of manufacturing the imaging device20can be simplified. Further, an optical low-pass filter and an infrared light blocking filter may be stacked on the surface of the cover glass70so that reflection from the surface of the cover glass70can be prevented. In this case, the distance between the cover glass70and the imaging device20can be shortened. Also, a Cr film may be formed on the surface of the cover glass70so that the surface of the cover glass70can be smoothed, and dust can be prevented from adhering to the surface. Further, the outer circumferences of the cover glass70and the frame60may be molded with a resin or the like so that dust can be prevented from entering. [Adhesive] As a sealing resin having a low reflectance is used as the adhesive14that bonds the cover glass70to the frame60, reflection by the adhesive14can be prevented, and ghosts and flares in images can be reduced. Two adhesives having different low elasticities may be used as the adhesive14so that the stress on the cover glass70can be reduced. Further, a moisture-proof seal may be provided on the outer circumference of the adhesive14so that moisture can be prevented from entering the imaging apparatus1. An ultraviolet cure adhesive having a high glass transition point and a relatively low elastic modulus may be used as the adhesive14so that the generation of stress due to temperature changes can be reduced. Further, when the thickness of the adhesive14is adjusted, the spacer may be dispersed in the adhesive14so that the thickness can be adjusted. 7. Seventh Embodiment In the imaging apparatus1of the first embodiment described above, the conductive wires50are wire-bonded to the pads401disposed on the circuit board40. On the other hand, an imaging apparatus1of a seventh embodiment of the present disclosure differs from the first embodiment described above, in that the conductive wires50are wire-bonded to thickened pads. In the imaging apparatus1described above with reference toFIG.3, the heat releasing plate30is disposed between the imaging device20and the circuit board40, and the conductive wires50are wire-bonded to the imaging device20and the circuit board40via the openings301in the heat releasing plate30. Therefore, the conductive wires50are longer than those in a case without the heat releasing plate30. Since the resistance and the inductance of the conductive wires50become higher, the image quality is degraded due to a propagation delay of a control signal or a change in the waveform of an image signal. Further, the conductive wires50might sag and come into contact with the heat releasing plate30in some cases. Therefore, shortening of the conductive wires50is suggested herein. [Configuration of an Imaging Apparatus] FIG.22is a cross-sectional view showing an example configuration of an imaging apparatus according to the seventh embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3in including a circuit board45in place of the circuit board40. The circuit board45is a circuit board on which pads406are disposed in place of the pads401. The pads406are pads in the form of thick films, and are formed in a shape protruding from the surface of the circuit board45. As the conductive wires50are wire-bonded to these pads406, the conductive wires50can be shortened. The pads406can be formed by thick-film plating, for example. Alternatively, to form the pads406, substrate posts or bumps including Cu may be soldered to the wiring layer on the surface of the circuit board45, for example. Further, to form the pads406, the portions of the surface of the circuit board other than the pad portions may be ground and thinned, for example. Note that the pads406are an example of the thick-film pad disclosed in the claims. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the seventh embodiment of the present disclosure, the pads406having a shape protruding from the surface of the circuit board are disposed on the circuit board, and the conductive wires50are wire-bonded to these pads406, so that the conductive wires50can be shortened. Thus, degradation of the signal waveform and sagging of the conductive wires50can be prevented. 8. Eighth Embodiment In the imaging apparatus1of the first embodiment described above, the imaging device20and the circuit board40are connected to each other by the conductive wires50. This embodiment suggests an imaging apparatus that increases the mechanical strength of the conductive wires50. In the imaging apparatus1described above with reference toFIG.3, the conductive wires50are wire-bonded to the imaging device20and the circuit board40via the openings301in the heat releasing plate30. Therefore, there is a problem that the conductive wires50become longer, and the mechanical strength decreases. There is also a problem that, when the movable semiconductor chip placement region moves, stress concentrates on the wire bonding portions of the conductive wires50, resulting in damage. Therefore, an increase in the strength of the conductive wires50is suggested herein. [Configuration of an Imaging Apparatus] FIG.23is a cross-sectional view showing an example configuration of an imaging apparatus according to an eighth embodiment of the present disclosure. This drawing is an enlarged view of regions connected by a conductive wire50. The imaging apparatus1in the drawing differs from the imaging apparatus1described above with reference toFIG.3, in that protective portions503are formed at the bonding portions between the conductive wires50, and the imaging device20and the circuit board40. A conductive wire50is connected by a device called a capillary. This capillary is a device that inserts a metallic wire including Au or the like, which is the material of the conductive wire50, into a hole formed at the central portion, heats the metallic wire, and applies ultrasonic waves while pressing the imaging device20and the like. The conductive wire50can be formed by the capillary in the following order. First, the capillary is heated to a high temperature, to melt the metallic wire inserted into the capillary and form a spherical ball. This ball is pressed against a pad201of the imaging device20, and heating and ultrasonic wave application are performed, following by connecting (ball bonding). Next, the capillary is moved to the position of a pad401of the circuit board40while pushing out the metallic wire. At this stage, the capillary is moved in a loop-like form, so that a loop of the metallic wire can be formed. Next, the metallic wire is pressed against the pad401, and ultrasonic waves are applied, to perform connecting (wedge bonding). After that, the metallic wire is cut, so that the conductive wire50is formed. In the drawing, the portions at which the conductive wire50is connected to the pads201and401are represented by connecting portions501and502, respectively. The connecting portions501and502correspond to the connecting portions formed by ball bonding and wedge bonding, respectively. Protective portions503are disposed at these connecting portions501and502. The protective portions503include a resin or the like, and are disposed so as to cover the connecting portions501and502, to reinforce the connecting portions501and502. Note that the protective portions503can be disposed at both the connecting portions501and502, as shown in the drawing. Alternatively, the protective portions503may be disposed at either the connecting portions501or502. Note that wires of a metal having a higher rigidity than that of Au may be used as the conductive wires50, so that the strength of the conductive wires50can be increased. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the eighth embodiment of the present disclosure, the protective portions are disposed at the connecting portions of the conductive wires50, so that the strength of the conductive wires50can be increased. Thus, it is possible to prevent breaking and the like of the conductive wires50in a case where the semiconductor chip placement region moves. 9. Ninth Embodiment In the imaging apparatus1of the eighth embodiment described above, the conductive wires50are connected to the imaging device20and the circuit board40in this order. On the other hand, an imaging apparatus1of a ninth embodiment of the present disclosure differs from the eighth embodiment described above, in that the connecting order of the conductive wires50is changed. [Configuration of an Imaging Apparatus] FIG.24is a cross-sectional view showing an example configuration of an imaging apparatus according to the ninth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.23, in that the protective portions503are eliminated, and conductive wires51are provided in place of the conductive wires50. Further, bumps203are disposed on the pads201of the imaging device20. In a conductive wire51, a connecting portion501formed by ball bonding and a connecting portion502formed by wedge bonding are formed on a pad401of the circuit board40and a bump203of the imaging device20, respectively. That is, the conductive wire51is connected to the bump203of the imaging device20after being connected to the pad401of the circuit board40. As a result, the loop of the conductive wire51can be shortened, and the curvature of the line in the vicinities of the connecting portions501and502can be made smaller. Thus, the stress concentration can be reduced. Note that the protective portions503described above with reference toFIG.23can also be disposed at the connecting portions501and502. Note that the bump203is a bump that is provided so that the surface to be connected to the conductive wire51is located higher than the surface of the imaging device20. Even in a case where the pad201is formed at a deeper position than the surface of the imaging device20, the top of the connecting portion501formed by ball bonding can be located at a higher position than the surface of the imaging device20by virtue of a height increasing effect of the ball. On the other hand, the bump203is provided at the connecting portion502formed by wedge bonding, which does not form a ball. As bonding is performed via the bump203, the pad201formed deep in the imaging device20and the conductive wire51can be connected. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the ninth embodiment of the present disclosure, the connection starting position at the time of connection of a conductive wire to the circuit board40and the like is changed, so that the strength of the conductive wires51can be increased. Thus, it is possible to prevent breaking and the like of the conductive wires50in a case where the semiconductor chip placement region moves. 10. Tenth Embodiment In the imaging apparatus1of the first embodiment described above, the semiconductor chip placement region is designed to be movable. On the other hand, an imaging apparatus1of a tenth embodiment of the present disclosure differs from the first embodiment described above, in that the semiconductor chip placement region is hooked on the circuit board40. [Configuration of an Imaging Apparatus] FIG.25is a plan view showing an example configuration of an imaging apparatus according to the tenth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.2in including locking portions85. The locking portions85are disposed between the heat releasing plate30and the circuit board40via the openings301, and hooks the semiconductor chip placement region to the circuit board40. This drawing shows an example in which the locking portions85are disposed at the four corners of the semiconductor chip placement region. [Configuration of Locking Portions] FIGS.26A and26Bare cross-sectional views showing example configurations of locking portions according to the tenth embodiment of the present disclosure. In the drawing,FIG.26Ashows an example of a locking portion85formed with a highly rigid metallic wire. Meanwhile,FIG.26Bin the drawing shows an example of a pillar-like locking portion86. As such locking portions are provided, movement of the semiconductor chip placement region is restricted, and the stress on the conductive wires50can be reduced. Note that the locking portions85and86are examples of the circuit board locking portion disclosed in the claims. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the tenth embodiment of the present disclosure, the semiconductor chip placement region is hooked to the circuit board40with the locking portions85and86. Thus, the stress on the conductive wires50can be reduced, and breaking and the like of the conductive wires50can be prevented. 11. Eleventh Embodiment In the imaging apparatus1of the first embodiment described above, the imaging device20and the circuit board40are connected to each other with the conductive wires50. On the other hand, an imaging apparatus1of an eleventh embodiment of the present disclosure differs from the first embodiment described above, in that the connection is performed with flexible wiring plates. [Configuration of an Imaging Apparatus] FIG.27is a cross-sectional view showing an example configuration of an imaging apparatus according to the eleventh embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3, in including flexible wiring plates52in place of the conductive wires50. The flexible wiring plates52are flexible wiring plates that are formed by stacking film-like insulating layers504on both surfaces of each wiring layer505including a metal such as Cu. Each wiring layer505is formed in the shape of a band for each corresponding one of the pads201(bump203) and401, and the plurality of band-like wiring layers505is arranged like a blind, to transmit signals. Note that pads506are provided for the wiring layers505, and are connected to the bumps203and the pads401by soldering, for example. As the flexible wiring plates52are highly flexible and are reinforced by the insulating layers504, signals can be transmitted without causing damage such as breaking of a wire even in a case where the semiconductor chip placement region moves. Further, in a case where the conductive wires50are used, stress concentrates on a single conductive wire50. On the other hand, the flexible wiring plates52have a configuration in which a plurality of wiring layers505is provided and connected simultaneously to a plurality of pads201of the imaging device20. Thus, stress concentration can be reduced. Note that the flexible wiring plates52are an example of the conductive member disclosed in the claims. The bumps203are also disposed on the pads201of the imaging device20, and the connecting portions are raised above the surface of the imaging device20. These bumps203may be bumps formed by plating, or stud bumps. Alternatively, the bumps203may be bumps that are disposed in multiple heights. [Other Configuration of Imaging Apparatuses] FIGS.28A and28Bare cross-sectional views showing other example configurations of imaging apparatuses according to the eleventh embodiment of the present disclosure. In this drawing,FIG.28Ashows an example in which flexible wiring plates53are provided in place of the flexible wiring plates52. The flexible wiring plates53are flexible wiring plates that are folded back after performing connection in the direction reverse from that inFIG.27at the portions connected to the imaging device20. With such folded-back portions, it is possible to reduce stress in a case where stress in the tensile direction is applied to the flexible wiring plates53due to the expansion/contraction difference between the heat releasing plate30and the circuit board40. In the drawing,FIG.28Bshows an example in which the flexible wiring plates52are connected to the bumps203by the anisotropic conductive films (ACFs)87. As shown inFIG.28Bin the drawing, the ACFs87can be used for connection to both the imaging device20and the circuit board40. Alternatively, the ACFs87can be used for either the imaging device20or the circuit board40, for example. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the eleventh embodiment of the present disclosure, the imaging device20and the circuit board40are connected by the flexible wiring plates. Thus, breaking and the like of the connecting portions of the imaging device20and the circuit board40can be prevented. 12. Twelfth Embodiment In the imaging apparatus1of the eleventh embodiment described above, the pads201are disposed in the upper surface of the imaging device20. On the other hand, an imaging apparatus1of a twelfth embodiment of the present disclosure differs from the eleventh embodiment described above, in that an imaging device20having the pads201in its lower surface is connected to the circuit board40. [Configuration of an Imaging Apparatus] FIG.29is a cross-sectional view showing an example configuration of an imaging apparatus according to the twelfth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.27, in that the pads201and the bumps203are disposed on the lower surface of the imaging device20, and the flexible wiring plates54are provided in place of the flexible wiring plates52. The flexible wiring plate54in this drawing is disposed along the heat releasing plate30. The imaging device20is connected to this flexible wiring plate54by flip-chip bonding. This connection may be direct connection of the bump203and the pad506, or connection with an ACF. After this connection, a liquid adhesive204is applied between the imaging device20and the heat releasing plate30, and is hardened. Thus, the imaging device20can be bonded to the heat releasing plate30. This adhesive204is referred to as underfill. [Another Configuration of an Imaging Apparatus] FIG.30is a cross-sectional view showing another example configuration of an imaging apparatus according to the twelfth embodiment of the present disclosure. The heat releasing plate in this drawing differs from that of the imaging apparatus1described above with reference toFIG.29, in that a wiring region is formed on the surface on which the imaging device20is disposed. In the heat releasing plate30in this drawing, a wiring region including an insulating layer322and a wiring layer305is formed on the surface on which the imaging device20is disposed. Further, pads306are formed on the wiring layer305. The bumps203of the imaging device20are connected to the wiring layer305via the pads306. Further, the flexible wiring plates53are connected between the circuit board40and the wiring layer305. Note that the wiring layer305is an example of the conductive member disclosed in the claims. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the twelfth embodiment of the present disclosure, in a case where an imaging device20having the pads201and the bumps203disposed on the lower surface is used, the imaging device20is mounted by flip-chip bonding. Thus, the imaging device20can be connected to the circuit board40. 13. Thirteenth Embodiment In the imaging apparatus1of the first embodiment described above, the imaging device20is bonded to the flat heat releasing plate30. On the other hand, an imaging apparatus1of a thirteenth embodiment of the present disclosure differs from the first embodiment described above, in that the imaging device20is bonded to a heat releasing plate30having recesses. In the imaging apparatus1, an image of the object is formed on the pixel array unit202by an imaging lens disposed outside. At that stage, the distance from the imaging lens differs between the central portion and the edge portion of the pixel array unit202, and the peripheral portion is blurred, resulting in degradation of image quality. Therefore, the imaging device20is curved, so that the distances from the imaging lens to the central portion and the edge portion of the pixel array unit202can be made substantially equal. [Configurations of Imaging Apparatuses] FIGS.31A and31Bare cross-sectional views showing example configurations of imaging apparatuses according to the thirteenth embodiment of the present disclosure. In the imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3, in that a heat releasing plate34is used in place of the heat releasing plate30, and an imaging device21is used in place of the imaging device20. In the heat releasing plate34in the drawing, a recess307is formed in the region to which the imaging device20is to be bonded. This recess307is a concave portion curved in a spherical shape. Further, the imaging device21in the drawing is an imaging device that is thinned by grinding the imaging device20. As the thinned imaging device21is bonded to the recess307, the shape of the recess307can be transferred to the imaging device21, so that the imaging device21can be curved. As the spherically curved recess307is used, the accuracy of the curvature of the imaging device21can be increased. Note that the recess307can be formed as a concave portion curved in a cylindrical shape. In the drawing,FIG.31Bshows an example of a heat releasing plate34including a recess308having a rectangular cross-section. With the recess308having a rectangular shape, the manufacture of the heat releasing plate34can be simplified. [Method for Manufacturing an Imaging Apparatus] FIGS.32A,32B, and32Care diagrams showing an example of a method for manufacturing an imaging apparatus according to the thirteenth embodiment of the present disclosure. This drawing shows the process of bonding the imaging device20to the heat releasing plate34. The manufacturing process is now described, with the imaging apparatus1inFIG.31Abeing an example. First, the die bond material13is applied to the recess307of the heat releasing plate34bonded to the circuit board40(FIG.32A). Next, the imaging device20is placed on the die bond material13(FIG.32B). Next, air is blown onto the imaging device21to harden the die bond material13, while the imaging device21is pressed against the recess307(FIG.32C). Note that the white arrow inFIG.32Cin the drawing indicates the air to be blown. Thus, the imaging device21can be curved. [Another Configuration of an Imaging Apparatus] FIG.33is a diagram showing another example configuration of an imaging apparatus according to the thirteenth embodiment of the present disclosure. The heat releasing plate34in this drawing differs from the heat releasing plate34described above with reference toFIG.31A, in that a hole309is formed. The hole309is a hole for sucking the imaging device21. When the imaging device21is bonded to the heat releasing plate34, the imaging device21is sucked through the hole309, so that the imaging device21can be pressed against the recess307of the heat releasing plate34. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the thirteenth embodiment of the present disclosure, the heat releasing plate34having a recess is used to curve the imaging device21. Thus, degradation of image quality can be reduced. 14. Fourteenth Embodiment In the imaging apparatus1of the first embodiment described above, the imaging device20is bonded to the heat releasing plate30. On the other hand, an imaging apparatus1of a thirteenth embodiment of the present disclosure differs from the first embodiment described above, in that the heat release properties of the heat releasing plate are improved. As the air gap10is formed between the heat releasing plate30having the imaging device20disposed thereon and the circuit board40, heat conduction from the heat releasing plate to the circuit board40is hindered, and the heat release properties of the imaging device20are degraded. Therefore, a heat releasing plate that improves heat release properties is suggested herein. [Configurations of Imaging Apparatuses] FIGS.34A and34Bare cross-sectional views showing example configurations of imaging apparatuses according to the fourteenth embodiment of the present disclosure. The imaging apparatus1inFIG.34Ain the drawing differs from the imaging apparatus1described above with reference toFIG.3, in that a heat releasing plate35is used in place of the heat releasing plate30. The heat releasing plate35inFIG.34Ain the drawing has a heat releasing portion310on a different surface from the surface to which the imaging device20is bonded in the semiconductor chip placement region. The heat releasing portion310widens the area of contact with the gas (air) enclosed in the imaging apparatus1, to improve the heat release properties of the heat releasing plate35, and reduce the increase in the temperature of the imaging device20. The heat releasing portion310can be formed by performing etching on the surface of the heat releasing plate35and form irregularities in the surface, for example. Alternatively, the surface of the heat releasing plate35may be roughened by sandblasting or the like, for example, to form the heat releasing portion310. In the drawing,FIG.34Bshows an example in which blackened portions320and408are formed on the surfaces of the heat releasing plate30and the circuit board40, respectively. Heat release and radiation is facilitated by the blackened portions320and408, so that the heat release properties of the heat releasing plate30can be improved. The blackened portions320and408can be formed by blackening the surfaces, for example. Alternatively, the blackened portions320and408can be formed by applying a black paint to the surfaces, for example. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, the imaging apparatus1according to the fourteenth embodiment of the present disclosure improves the heat release properties of the heat releasing plate30. Thus, the increase in the temperature of the imaging device20can be reduced. 15. Fifteenth Embodiment In the imaging apparatus1of the first embodiment described above, the semiconductor chip placement region is designed to be movable. On the other hand, a fifteenth embodiment of the present disclosure suggests a configuration that restricts vibration of the semiconductor chip placement region. As the semiconductor chip placement region is designed to be movable, an imaging apparatus1vibrates due to external impact. This vibration causes damage such as breaking of the conductive wires50. Therefore, the vibration of the semiconductor chip placement region is reduced, to prevent damage to the conductive wires50. [Configurations of Heat Releasing Plates] FIGS.35A and35Bare plan views showing example configurations of heat releasing plates according to the fifteenth embodiment of the present disclosure. Heat releasing plates36in the drawing have openings in the semiconductor chip placement region. The heat releasing plate36inFIG.35Ain the drawing has a plurality of openings312in the semiconductor chip placement region. Further, the heat releasing plate36inFIG.35Bin the drawing has openings313. The openings313are combinations of the openings301described above with reference toFIG.3and openings formed in the semiconductor chip placement region. By virtue of such openings312or the like formed in the semiconductor chip placement region, the heat releasing plate36can be made lighter. Thus, vibration of the heat releasing plate36can be reduced. Note that the openings312or the like increase the thermal resistances of the imaging device20and the heat releasing plate36. Therefore, the size and the number of the openings312need to be adjusted in accordance with the amount of heat generated from the imaging device20. Also, the openings312or the like may be arranged in a non-uniform manner, to prevent the occurrence of resonance of the semiconductor chip placement region, and reduce vibration of the semiconductor chip placement region. Alternatively, the heat releasing plate in the semiconductor chip placement region may be ground, to be thinner and lighter, for example. FIG.36is a plan view showing another example configuration of a heat releasing plate according to the fifteenth embodiment of the present disclosure. A heat releasing plate37in the drawing is a heat releasing plate that has the openings301, and openings314and315in different shapes from that of the openings301. The opening315is an opening formed in a trapezoidal shape. As the opening315is formed in a trapezoidal shape, the areas of the beam portions between the openings can be widened, while the regions for wire bonding of the conductive wires50are secured. Thus, vibration of the semiconductor chip placement region can be reduced. Meanwhile, the openings314are miniaturized openings formed by dividing an opening formed in the vicinity of one side of the imaging device20. Thus, beam portions can be formed in regions other than those in the vicinities of the four corners of the imaging device20, and vibration can be reduced. Note that, in a case where a plurality of such beam portions is formed, the beam portions are arranged asymmetrically, so that resonance in the semiconductor chip placement region can be prevented. FIGS.37A,37B, and37Care plan views showing other example configurations of heat releasing plates according to the fifteenth embodiment of the present disclosure. Heat releasing plates38in this drawing include vibration damping portions that reduce vibration of the semiconductor chip placement region. Vibration damping portions are disposed at beam portions that suspend the semiconductor chip placement region. In the drawing,FIGS.37A and37Bshow examples in which vibration damping portions316and317formed in meander shapes are adopted, respectively. Further,FIG.37Cin the drawing shows an example of a vibration damping portion318that is formed by creating recesses in the beam portions on the front and back surfaces, the recesses extending in the thickness direction. With such vibration damping portions316to318, vibration of the semiconductor chip placement region can be reduced. FIG.38is a plan view showing another example configuration of a heat releasing plate according to the fifteenth embodiment of the present disclosure. In the heat releasing plate30shown in this drawing, vibration damping portions321are disposed at the beam portions. The vibration damping portions321include an elastic material such as rubber, and are disposed at the beam portions of the heat releasing plate30, to reduce vibration of the semiconductor chip placement region. The vibration damping portions321can be formed in a sheet-like shape, for example, and be bonded to the beam portions. Alternatively, gel-like vibration damping portions321may be applied onto the beam portions. The vibration damping portions321can be disposed on either the front surface or the back surface, or on both surfaces of the heat releasing plate30. Further, the vibration damping portions321can be used in conjunction with the vibration damping portions316or the like described above with reference toFIGS.37A,37B, and37C. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, the imaging apparatus1of the fifteenth embodiment of the present disclosure reduces vibration of the semiconductor chip placement region. Thus, damage to the conductive wires50can be prevented. 16. Sixteenth Embodiment In the imaging apparatus1of the first embodiment described above, the frame60is bonded to the heat releasing plate30. On the other hand, a sixteenth embodiment of the present disclosure suggests a configuration that improves heat release properties in the frame60. The frame60includes a metal such as Cu, and the surfaces thereof are blackened. For example, black plating is performed. Thus, heat release properties can be improved. Further, by the blackening, reflection of incident light on the frame60can be reduced. For example, in a case where the reflectance is reduced to 1% or lower by the blackening, the occurrence of flares and the like can be prevented. Further, a solder or a metal-containing paste is used as the adhesive12that bonds the frame to the heat releasing plate30, so that the heat from the heat releasing plate30and the circuit board40can be effectively transferred to the frame60. To reduce the thermal resistance at this stage, the plating or the like on the surfaces of the frame60is preferably removed. Note that, in a case where a solder or the like is used as the adhesive12, a paste-like solder is applied to the heat releasing plate30, and the frame60is placed. After that, reflow soldering is performed, so that bonding can be performed. [Configuration of a Frame] FIG.39is a cross-sectional view showing an example configuration of a frame according to the sixteenth embodiment of the present disclosure. A frame63in this drawing has heat releasing fins603formed on the side surfaces. Irregularities are formed in the side surfaces of the frame63, so that the heat releasing fins603can be formed. The heat releasing fins603can improve the heat release properties of the frame63. [Configuration of a Heat Releasing Plate] FIG.40is a cross-sectional view showing an example configuration of a heat releasing plate according to the sixteenth embodiment of the present disclosure. A heat releasing plate350in this drawing is a heat releasing plate that has a wall portion surrounding the imaging device20, and is integrally formed with the frame. As the heat releasing plate350is integrally formed with the frame, thermal resistance can be lowered, and heat release properties can be improved. [Another Configuration of a Frame] FIG.41is a cross-sectional view showing another example configuration of a frame according to the sixteenth embodiment of the present disclosure. A frame64in this drawing has a protrusion604at the brim portion of the upper surface. This protrusion604prevents emission of incident light onto the regions in which the conductive wires50are connected to the imaging device20. This protrusion604can prevent reflection of incident light by the conductive wires50, and reduce the occurrence of flares and the like. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, the imaging apparatus1according to the sixteenth embodiment of the present disclosure improves the heat release properties of the frame. Thus, the increase in the temperature of the imaging device20can be reduced. 17. Seventeenth Embodiment In the imaging apparatus1of the first embodiment described above, the air gap10is formed between the heat releasing plate30having the imaging device20disposed thereon and the circuit board40. On the other hand, a seventeenth embodiment of the present disclosure differs from the first embodiment described above, in that a heat storage portion is provided in the air gap. Since the power consumption of the imaging device20fluctuates, the amount of heat generated by the imaging device also changes. At this stage, in a case where a heat release capacity is set in accordance with the maximum power consumption of the imaging device20in the imaging apparatus1, there is a problem, for example, that a cooling mechanism such as the heat releasing plate30of the imaging apparatus1becomes larger than necessary. Therefore, the amount of heat generated from the imaging device20is leveled, so that a cooling mechanism having a necessary and sufficient capacity can be formed. [Configuration of an Imaging Apparatus] FIG.42is a cross-sectional view showing an example configuration of an imaging apparatus according to the seventeenth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3, in including a heat storage portion88between the semiconductor chip placement region and the circuit board40. The heat storage portion88stores heat from the imaging device20. As the heat storage portion88is disposed between the semiconductor chip placement region and the circuit board the heat generated in the imaging device20and transferred to the heat releasing plate30is temporarily stored in the heat storage portion88. The heat stored in the heat storage portion88is leveled when the heat is transferred to the circuit board40. The heat storage portion88needs to be configured by a low-elasticity material, so as not to affect warpage of the heat releasing plate30. For example, the heat storage portion88can be formed by dispersing heat storage microcapsules containing paraffin or inorganic hydrated salt coated with a polymer in an epoxy-based or acrylic-based resin having a low elastic modulus. Alternatively, a composite material containing particles of vanadium oxide, tin alloy, or the like can also be used. Further, as the heat storage portion88is provided, it is possible to reduce warpage of the imaging device20due to expansion and contraction of the components disposed below the imaging device20, during the process of manufacturing the imaging apparatus1. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the seventeenth embodiment of the present disclosure, the heat storage portion88is provided, so that the cooling mechanism such as the heat releasing plate30can be optimized (miniaturized). 18. Eighteenth Embodiment In the imaging apparatus1of the first embodiment described above, the air gap10is formed between the heat releasing plate30having the imaging device20disposed thereon and the circuit board40. On the other hand, an eighteenth embodiment of the present disclosure differs from the first embodiment described above, in that a buffer portion is provided in the air gap. [Configuration of an Imaging Apparatus] FIG.43is a cross-sectional view showing an example configuration of an imaging apparatus according to the eighteenth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3, in including a buffer portion91between the semiconductor chip placement region and the circuit board40. The buffer portion91alleviates vibrational impact on the semiconductor chip placement region. As the buffer portion91is provided, the vibrational impact at the time of wire bonding of the conductive wires50can be alleviated, for example, and damage to the conductive wires50can be prevented. The buffer portion91can be formed with urethane rubber or natural rubber, for example. Also, the buffer portion91can be formed with a gel-like acrylic or urethane resin, for example. Further, the buffer portion91can be formed with a material having thixotropic properties. Also, silicon-based thermal grease can be used, to improve heat release properties as well as buffering properties. Further, a magnetic sheet can be provided, to use the magnetic repulsive force for alleviating vibrational impact. [Configurations of Buffer Portions] FIGS.44A,44B,44C,44D,44E, and44Fare plan views showing example configurations of buffer portions according to the eighteenth embodiment of the present disclosure. This drawing is diagrams showing the shapes of buffer portions91provided in heat releasing plates30. In the drawing,FIG.44Ashows an example of a buffer portion91that is disposed in substantially the same area as the imaging device20. In the drawing,FIGS.44B and44Cshow examples in which a buffer portion91is formed in a smaller area and a larger area than the imaging device20, respectively. In the drawing,FIG.44Dshows an example in which a plurality of circular buffer portions91is provided. In the drawing,FIG.44Eshows an example in which a buffer portion91is formed along the diagonal lines of the imaging device20. In the drawing,FIG.44Fshows an example in which buffer portions91are provided at the central portion and an outer circumferential portion of the imaging device20. A rubber buffer portion91can be placed on the circuit board40before the heat releasing plate30is bonded to the circuit board40, for example. Alternatively, a gel-like buffer portion91can be injected into the air gap10through the hole409described above with reference toFIG.6, after the conductive wires50are wire-bonded to the imaging device20. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the eighteenth embodiment of the present disclosure, the buffer portion91is provided, so that vibrational impact on the semiconductor chip placement region can be alleviated. 19. Nineteenth Embodiment The imaging apparatus1of the eighteenth embodiment described above has the buffer portion91disposed therein. On the other hand, a nineteenth embodiment of the present disclosure differs from the nineteenth embodiment described above, in that buffer portions are disposed on the heat releasing plate. [Configuration of a Heat Releasing Plate] FIG.45is a plan view showing an example configuration of a heat releasing plate according to the nineteenth embodiment of the present disclosure. A heat releasing plate39in this drawing has spring portions319formed in part of the semiconductor chip placement region. [Configuration of an Imaging Apparatus] FIG.46is a cross-sectional view showing an example configuration of an imaging apparatus according to the nineteenth embodiment of the present disclosure. The imaging apparatus1in this drawing differs from the imaging apparatus1described above with reference toFIG.3, in including the above heat releasing plate39in place of the heat releasing plate30. As shown in the drawing, the spring portions319are bent toward the circuit board40, and the tips of the bent portions are brought into contact with the circuit board40, so that buffer portions can be formed. As a result, the configuration can be made simpler than the imaging apparatus1described above with reference toFIG.43. The other components of the imaging apparatus1are similar to the components of the imaging apparatus1described in the first embodiment of the present disclosure, and therefore, explanation of them is not made herein. As described above, in the imaging apparatus1of the nineteenth embodiment of the present disclosure, buffer portions are disposed on the heat releasing plate, so that vibrational impact on the semiconductor chip placement region can be alleviated. <20. Example Configuration of an Imaging Device> [Configuration of an Imaging Device] FIG.47is a diagram showing an example configuration of an imaging device according to an embodiment of the present disclosure. The imaging device20in this drawing includes a pixel array unit202, a vertical drive unit203, a column signal processing unit204, and a control unit205. The pixel array unit202is formed with pixels210arranged in a two-dimensional grid pattern. Here, a pixel210generates an image signal in accordance with emitted light. The pixel210includes a photoelectric conversion unit that generates an electric charge in accordance with the emitted light. The pixel210further includes a pixel circuit. This pixel circuit generates an image signal based on the electric charge generated by the photoelectric conversion unit. The generation of the image signal is controlled by a control signal generated by the vertical drive unit203described later. In the pixel array unit202, signal lines206and207are arranged in an X-Y matrix. The signal lines206are signal lines that transmit control signals for the pixel circuits in the pixels210, are provided for the respective rows in the pixel array unit202, and are designed to be shared by the pixels210aligned in each row. The signal lines207are signal lines that transmit image signals generated by the pixel circuits of the pixels210, are provided for the respective columns in the pixel array unit202, and are designed to be shared by the pixels210aligned in each column. These photoelectric conversion units and pixel circuits are formed in a semiconductor substrate. The vertical drive unit203generates control signals for the pixel circuits of the pixels210. This vertical drive unit203transmits the generated control signals to the pixels210via the signal lines206in the drawing. The column signal processing unit204processes image signals generated by the pixels210. This column signal processing unit204processes the image signals transmitted from the pixels210via the signal lines207in the drawing. The processing at the column signal processing unit204corresponds to analog-to-digital conversion for converting analog image signals generated in the pixels210into digital image signals, for example. The image signals processed by the column signal processing unit204are output as image signals of the imaging apparatus1. The control unit204controls the entire imaging apparatus1. This control unit205generates and outputs control signals for controlling the vertical drive unit203and the column signal processing unit204, to control the imaging device20. The control signals generated by the control unit205are transmitted to the vertical drive unit203and the column signal processing unit204through signal lines208and209, respectively. <21. Example Application to a Camera> The technology (the present technology) according to the present disclosure can be applied to various products. For example, the present technology may be embodied as an imaging device mounted in an imaging apparatus such as a camera. FIGS.48A and48Bare diagrams showing a schematic example configuration of a camera that is an example of an imaging apparatus to which the present technology can be applied. In this drawing,FIG.48Ais a diagram showing the exterior of a camera100. Further,FIG.48Bin the drawing is a block diagram showing an example configuration of the camera100. The camera100includes a CPU101, a ROM102, a RAM103, an input/output interface105, an input unit106, an output unit107, a storage unit108, a communication unit109, an imaging unit110, a drive111, and a removable storage medium112. The CPU101, the ROM102, and the RAM103are connected to one another by a bus104. Also, the input/output interface105is further connected to the bus104. The input unit106, the output unit107, the storage unit108, the communication unit109, the imaging unit110, and the drive111are further connected to the input/output interface105. The input unit106is formed with a keyboard and a mouse. The output unit107is formed with a display, a speaker, and the like. The storage unit108is formed with a hard disk and a semiconductor memory. The communication unit109is formed with a network interface or the like, for example. A plurality of imaging apparatuses1described with reference toFIG.1can be included in the imaging unit110. An image generated by the imaging unit110is supplied to the CPU101via the input/output interface105. The drive111drives the removable storage medium112such as a semiconductor memory. In a system configured as above, the CPU101loads a program stored in the storage unit108into the RAM103via the input/output interface105and the bus104, for example, and executes the program, so that the above described series of processes is performed. Also, the program can be installed into the storage unit108via the input/output interface105when the removable recording medium112is mounted on the drive111. Alternatively, the program can also be received by the communication unit109via a wired or wireless transmission medium, such as a local area network, the Internet, or digital satellite broadcasting, and be then installed into the storage unit108. Other than the above, the program can be installed beforehand into the ROM102or the storage unit108. Lastly, the explanation of each embodiment described above is an example of the present disclosure, and the present disclosure is not limited to the embodiments described above. Accordingly, other than the respective embodiments described above, various changes may of course be made depending on the design and the like, without departing from the technical idea according to the present disclosure. Note that the present technology may also be embodied in the configurations described below. (1) A semiconductor device including:a semiconductor chip;a circuit board that transmits a signal of the semiconductor chip;a heat releasing plate on which the semiconductor chip is disposed, the heat releasing plate having an opening in a region on an outer side of a semiconductor chip placement region, the semiconductor chip placement region being a region in which the semiconductor chip is disposed;an adhesive member that bonds the circuit board and the heat releasing plate to each other, the adhesive member being disposed in a region on an outer side of the opening on a surface of the heat releasing plate, the surface of the heat releasing plate being different from a surface on which the semiconductor chip is disposed; anda conductive member that connects the semiconductor chip and the circuit board to each other via the opening. (2) The semiconductor device according to (1), in which an air gap is formed between the heat releasing plate and the circuit board. (3) The semiconductor device according to (1), in which the circuit board includes an electronic circuit that receives and transmits the transmitted signal. (4) The semiconductor device according to (2), in which the circuit board contains an element forming the electronic circuit. (5) The semiconductor device according to (2), in which the circuit board has a recess in which an element forming the electronic circuit is disposed. (6) The semiconductor device according to (5), in which the circuit board has the recess having an opening in a surface close to the heat releasing plate. (7) The semiconductor device according to any one of (1) to (6), further including a lid unit that is bonded to the heat releasing plate and covers the semiconductor chip. (8) The semiconductor device according to (7), further including a lid locking portion that locks the semiconductor chip placement region to the lid unit. (9) The semiconductor device according to any one of (1) to (8), in which the heat releasing plate has the semiconductor chip placement region in contact with the circuit board. (10) The semiconductor device according to (9), further including:a lid unit that is bonded to the heat releasing plate and covers the semiconductor chip; andan elastic member that is disposed between the lid unit and the heat releasing plate, and presses the heat releasing plate, to bring the semiconductor chip placement region into contact with the circuit board. (11) The semiconductor device according to (9), in which the heat releasing plate has a beam portion that is a region connecting a region on an outer side of the opening and a region on an inner side of the opening, the beam portion being obliquely positioned to bring the semiconductor chip placement region into contact with the circuit board. (12) The semiconductor device according to (9), in which the heat releasing plate includes a protrusion that locks the semiconductor chip placement region to the circuit board, to bring the semiconductor chip placement region into contact with the circuit board. (13) The semiconductor device according to any one of (1) to (12), in which the circuit board has a thick-film pad having a shape protruding from a surface, and the conductive member is connected to the thick-film pad. (14) The semiconductor device according to any one of (1) to (13), in which the conductive member is formed with a metallic wire. (15) The semiconductor device according to (14), further including a protective portion disposed on at least one of a connecting portion between the conductive member and the semiconductor chip, or a connecting portion between the conductive member and the circuit board. (16) The semiconductor device according to (14), in which the conductive member is connected to the semiconductor chip after being connected to the circuit board. (17) The semiconductor device according to any one of (1) to (15), in which the conductive member is formed with a flexible wiring plate. (18) The semiconductor device according to (1), further including a circuit board locking portion that locks the semiconductor chip placement region to the circuit board. (19) The semiconductor device according to any one of (1) to (17), in which the heat releasing plate has a heat releasing portion disposed on a different surface from a surface on which the semiconductor chip is disposed in the semiconductor chip placement region. (20) The semiconductor device according to (19), in which the heat releasing portion is formed with a plurality of irregularities formed on the heat releasing plate. (21) The semiconductor device according to (19), in which the heat releasing portion is formed by roughening a surface of the heat releasing plate. (22) The semiconductor device according to any one of (1) to (21), in which the heat releasing plate has a blackened portion formed on a surface. (23) The semiconductor device according to any one of (1) to (22), in which the circuit board has a blackened portion formed on a surface facing the heat releasing plate. (24) The semiconductor device according to any one of (1) to (23), in which the heat releasing plate further has a second opening in a region in which the semiconductor chip is disposed. (25) The semiconductor device according to any one of (1) to (24), in which the heat releasing plate further includes a vibration damping portion that reduces vibration of the semiconductor chip placement region. (26) The semiconductor device according to any one of (1) to (25), further including a buffer portion disposed between the semiconductor chip placement region and the circuit board. (27) An imaging apparatus including:an imaging device;a circuit board that transmits a signal of the imaging device;a heat releasing plate on which the imaging device is disposed, the heat releasing plate having an opening in a region on an outer side of a semiconductor chip placement region, the semiconductor chip placement region being a region in which the imaging device is disposed;an adhesive member that bonds the circuit board and the heat releasing plate to each other, the adhesive member being disposed in a region on an outer side of the opening on a surface of the heat releasing plate, the surface of the heat releasing plate being different from a surface on which the imaging device is disposed; and a conductive member that connects the imaging device and the circuit board to each other via the opening. (28) A method for manufacturing a semiconductor device,the method including:a bonding step of bonding a circuit board and a heat releasing plate with an adhesive member, the circuit board exchanging signals with a semiconductor chip, the semiconductor chip being disposed on the heat releasing plate, the heat releasing plate having an opening in a region on an outer side of a region in which the semiconductor chip is disposed, the adhesive member being disposed in a region on an outer side of the opening on a different surface of the heat releasing plate from a surface on which the semiconductor chip is disposed;a semiconductor chip placing step of placing the semiconductor chip on the bonded heat releasing plate; anda connecting step of connecting the semiconductor chip and the circuit board with a conductive member via the opening. REFERENCE SIGNS LIST 1Imaging apparatus10Air gap11Adhesive member12,14,204Adhesive13Die bond material15Solder ball20,21Imaging device30to39Heat releasing plate40to45Circuit board50,51Conductive wire52Flexible wiring plate60to64Frame70to72Cover glass81,82,85,86Locking portion83,303Protrusion84Elastic member87ACF88Heat storage portion91Buffer portion100Camera110Imaging unit202Pixel array unit203Bump210Pixel301,312to315Opening302Beam portion304,307,308,403,702Recess309,311,405,409,611Hole310Heat releasing portion316,318,321Vibration damping portion319Spring portion320,408Blackened portion350Heat releasing plate406Pad410Sealing resin501,502Connecting portion503Protective portion603Heat releasing fin604Protrusion701Roughened portion | 99,164 |
11942496 | DETAILED DESCRIPTION The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. A digital image sensor package30in a glass-on-die packaging arrangement is shown inFIG.3. An image sensor substrate32is disposed on a printed circuit board (PCB)31, and photodiodes33are formed in or on the image sensor substrate32. A transparent adhesive layer34physically couples a covering35(e.g., glass, such as a glass lens) over the image sensor substrate32. In greater detail, the glass covering35has a top surface35a, a bottom surface35b, and a sidewall35cdelimiting a perimeter edge of the glass covering. The bottom surface35bof the glass covering35is physically coupled to the image sensor substrate32over the photodiodes33by the transparent adhesive layer34. The top surface35aof the glass covering35is greater in diameter and/or surface area than the bottom surface35b, such that the sidewall35cis angled with respect to normal (i.e., is angled away from a direction perpendicular to the bottom surface35band/or the plane within which the photodiodes33are formed for the substrate32and/or the bottom of the PCB31). In particular, the angle formed by the sidewall35cand the bottom surface35bis an obtuse angle (greater than 90°), and/or the angle formed by the sidewall35cand the top surface35ais an acute angle (less than 90°. The purpose of the angles formed by the sidewall35cwith respect to the top surface35aand/or bottom surface35bof the glass covering35is to cause incoming light IL that reflects off the sidewall35cto reflect along a trajectory that avoids the photodiodes33, as illustrated. This way, despite the fact that incoming light IL is reflecting off the sidewall35c, it does not contribute to noise in the information about the scene captured by the photodiodes33, thereby providing for better image quality. In addition, another benefit provided by sidewall35cshape of the glass covering35is that photoabsorbent materials (such as used in the design ofFIG.2) are not necessary. Indeed, the digital image sensor package30is devoid of photoabsorbent materials positioned between the sidewall35cand the top of the image sensor substrate32, and no such photoabsorbent materials (such as those used in the design ofFIG.2) are present between the sidewall35cand the top of the image sensor substrate32. By eliminating such photoabsorbent materials, steps for forming such materials and attaching them to the glass covering35during manufacture are eliminated. Another digital image sensor package30′ is shown inFIG.4. This digital image sensor package30′ is in a land-grid-array arrangement. In greater detail, as with the digital image sensor package30ofFIG.3, the image sensor substrate32is disposed on the printed circuit board31, and photodiodes33are formed in or on the image sensor substrate32. Here, however, mounting hardware36is affixed to the printed circuit board31, and surrounds at least a portion of the periphery of the image sensor substrate32in a spaced apart fashion so as to not contact the image sensor substrate32. The mounting hardware36is comprised of a first portion36aaffixed to the printed circuit board31and extending upwardly therefrom, a second portion36cextending inwardly from the periphery of the image sensor substrate32toward the photodiodes33, and an intermediate connecting portion36bthat connects the first portion36ato the second portion36c. An adhesive layer34(which may be transparent) physically couples a glass covering35(e.g., a lens) to the top surface of the second portion36cof the mounting hardware36, such that the glass covering35overlies the image sensor substrate32. The glass covering35has a top surface35a, a bottom surface35b, and a sidewall35c. The periphery of the bottom surface35bof the glass covering35is physically coupled to the second portion36cof the mounting hardware36. The top surface35aof the glass covering35is greater in diameter and/or surface area than the bottom surface35b, such that the sidewall35cis angled with respect to normal (as defined noted above). As stated earlier, the angle formed by the sidewall35cand the bottom surface35bis an obtuse angle (greater than 90°), and/or the angle formed by the sidewall35cand the top surface35ais an acute angle (less than 90°), and the purpose of the angles formed by the sidewall35cwith respect to the top surface35aand bottom surface35bof the glass covering35is to cause incoming light IL that reflects off the sidewall35cto reflect along a trajectory that avoids the photodiodes33. The glass covering35ofFIGS.3-4may be formed to have the above described angles by suitable cutting methodologies, for example using mechanical sawing or chemical etching. The angle formed by sidewall35cwith respect to the top surface35amay be in the range of 40° to 60° for example, and the angle formed by the sidewall35cwith respect to the bottom surface35bmay be in the range of 120° to 140° for example. Other suitable angles may be used as well. The top surface35aand bottom surface35bare illustrated as being straight and not curved, although in some applications, the top surface35aand bottom surface35bmay be concave or convex as desired. In addition, in some instances, the sidewall35cmay be concave or convex as desired. While some incoming light IL may still reflect off the sidewall35cin a trajectory that results in it impinging upon the photodiodes33, such instances are reduced with the designs ofFIGS.3-4as compared to the designs ofFIGS.1-2. Note that although the covering35is described as being constructed from glass, it may also be constructed from other materials, such as acrylic. In addition, note that inFIGS.3-4, the covering35may be a lens, but may also not be a lens and may simply act as a cover for the image sensor substrate32. While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims. | 6,568 |
11942497 | DETAILED DESCRIPTION OF THE INVENTION Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases. It is also to be noted that the same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases. Note that the ordinal numbers such as “first” and “second” in this specification are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which specify one embodiment of the present invention in some cases. For example, in this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, another connection relationship is included in the drawings or the texts. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Examples of the case where X and Y are directly connected include the case where an element that allows an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) is not connected between X and Y, and the case where X and Y are connected without the element that allows the electrical connection between X and Y provided therebetween. Examples of the case where X and Y are electrically connected include the case where one or more elements that allow an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) can be connected between X and Y. Note that the switch is controlled to be turned on or off. That is, the switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not. Alternatively, the switch has a function of selecting and changing a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected. Examples of the case where X and Y are functionally connected include the case where one or more circuits that allow functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a D/A converter circuit, an A/D converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up converter, or a step-down converter) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; and/or a control circuit) can be connected between X and Y. For example, even when another circuit is interposed between X and Y, X and Y are functionally connected if a signal output from X is transmitted to Y. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected. Note that an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the description “X and Y are connected”. For example, any of the following expressions can be used for the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to one part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z2 and another part of Z2 is directly connected to Y. Examples of the expressions include, “X Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order”. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope. Other examples of the expression include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2 is on the third connection path” and “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path on which Z1 is provided, the first connection path does not include a second connection path, the second connection path includes a connection path on which the transistor is provided, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path on which Z2 is provided, and the third connection path does not include the second connection path”. Another examples of the expression include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path on which Z1 is provided, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) and a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path on which Z2 is provided, the third connection path does not include a fourth connection path, and the fourth connection path is a path between the drain (or a second terminal or the like) and the source (or the first terminal or the like) of the transistor. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope. Note that these expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer). Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, “electrical connection” in this specification includes in its category such a case where one conductive film has functions of a plurality of components. Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases. Note that in general, a potential (a voltage) is relative and is determined depending on the amount relative to a reference potential. Therefore, even when the expression “ground”, “GND”, or the like is used, the potential is not necessarily 0 V. For example, the “ground potential” or “GND” may be defined using the lowest potential in a circuit as a reference. Alternatively, the “ground potential” or “GND” may be defined using an intermediate potential in a circuit as a reference. In those cases, a positive potential and a negative potential are set using the potential as a reference. Embodiment 1 In this embodiment, an imaging device that is one embodiment of the present invention will be described with reference to drawings. Embodiments of the present invention are the structure and the manufacturing method of an imaging device having a three-dimensional integration structure formed by bonding a fabricated first structure and second structure to each other to bond metal layers included in the first and second structures to each other. The first structure may include a transistor including silicon in an active layer or an active region, a first metal layer electrically connected to the transistor, and a first insulating layer. The second structure may include a photoelectric conversion element, a transistor including an oxide semiconductor in an active layer, a second metal layer electrically connected to the transistor, and a second insulating layer. Alternatively, the first structure may include a first transistor including silicon in an active layer or an active region, a second transistor including an oxide semiconductor in an active layer, a third metal layer electrically connected to the second transistor, and a third insulating layer, and the second structure may include a photoelectric conversion element, a fourth metal layer electrically connected to the photoelectric conversion element, and a fourth insulating layer. Alternatively, the first structure, the second structure, and a third structure may be bonded to each other. In this case, the first structure may include a transistor including silicon in an active layer or an active region, a first metal layer electrically connected to the transistor, and a first insulating layer. The second structure may include a transistor including an oxide semiconductor in an active layer, a second metal layer electrically connected to the transistor, a third metal layer, a second insulating layer, and a third insulating layer. The third structure may include a photoelectric conversion element, a fourth metal layer electrically connected to the photoelectric conversion element, and a fourth insulating layer. The transistor including the oxide semiconductor in an active layer has a low off-state current and therefore facilitates construction of a memory for retaining data in the pixel of an imaging device. FIGS.1A and1Bare a cross-sectional schematic view of a pixel20included in an imaging device of one embodiment of the present invention and a circuit diagram thereof, respectively. Note that an example in which transistors are n-channel transistors is illustrated inFIGS.1A,1B, and the like; however, one embodiment of the present invention is not limited to this, and some transistors may be replaced with p-channel transistors. In the pixel20, one electrode of a photoelectric conversion element PD is electrically connected to one of a source and a drain of a transistor41. The other of the source and the drain of the transistor41is electrically connected to one of a source and a drain of a transistor42. The other of the source and the drain of the transistor41is electrically connected to a gate of a transistor43. One of a source and a drain of the transistor43is electrically connected to one of a source and a drain of a transistor44. Here, a node FD to which the other of the source and the drain of the transistor41, one of the source and the drain of the transistor42, and the gate of the transistor43are connected is a charge detection portion. Note that a capacitor may be connected to the node FD as illustrated inFIG.20A. InFIGS.1A and1B, the other electrode of the photoelectric conversion element PD is electrically connected to a wiring71(VPD). The other of the source and the drain of the transistor42is electrically connected to a wiring72(VRS). The other of the source and the drain of the transistor43is electrically connected to a wiring73(VPI). The other of the source and the drain of the transistor44is electrically connected to a wiring91(OUT1). Note that connection configuration between a component (e.g., a transistor, a photoelectric conversion element, or the like) and a wiring inFIGS.1A and1Bis an example Components might be electrically connected to different wirings, or a plurality of components might be electrically connected to the same wiring. The wiring71(VPD), the wiring72(VRS), and the wiring73(VPI) can function as power supply lines. For example, the wiring71(VPD) can function as a low potential power supply line. The wiring72(VRS) and the wiring73(VPI) can function as high potential power supply lines. A gate of the transistor41is electrically connected to a wiring61(TX). A gate of the transistor42is electrically connected to a wiring62(RS). A gate of the transistor44is electrically connected to a wiring63(SE). The wirings61(TX),62(RS), and63(SE) can function as signal lines for controlling the conduction states of the transistors to which the respective wirings are connected. The transistor41can function as a transistor for transferring the potential of a cathode of the photoelectric conversion element PD. The transistor42can function as a transistor for resetting the potential of the node FD. The transistor43can function as a transistor for outputting a signal corresponding to the potential of the node FD. The transistor44can function as a transistor for selecting the pixel20. Note that the above structure of the pixel20is just an example, and some of the circuits, some of the transistors, some of the capacitors, some of the wirings, or the like are not included in some cases. Alternatively, a circuit, a transistor, a capacitor, a wiring, or the like that is not included in the above structure might be included. Alternatively, a connection configuration of some wirings might be different from the above configuration. An imaging device of one embodiment of the present invention includes a layer1100, a layer1200, and a layer1300as illustrated inFIG.1A. The layer1100may include the photoelectric conversion element PD. A photodiode with two terminals can be used for the photoelectric conversion element PD, for example. As the photodiode, a PN photodiode using a single crystal silicon substrate, a PIN photodiode using an amorphous silicon thin film, a micro crystal silicon thin film, or a polycrystalline silicon thin film, selenium or a compound thereof, or a photodiode using an organic compound can be used. The layer1200may include the transistors41and42. As the transistors41and42, a transistor including an oxide semiconductor in an active layer (hereinafter, referred to as an OS transistor) is preferably used. In addition, the layer1200includes a metal layer401belectrically connected to one of the source and the drain of the transistor41and one of the source and the drain of the transistor42. An OS transistor has an extremely low off-state current. A period during which charge can be held in the node FD can be extremely long owing to the low off-state current of the transistors41and42. Therefore, a global shutter system in which charge accumulation operation is performed in all the pixels at the same time can be used without a complicated circuit configuration and an operation method. Note that the imaging device of one embodiment of the present invention can also be operated in a rolling shutter system. The OS transistor has lower temperature dependence of change in electrical characteristics than a transistor including silicon in an active region or an active layer (hereinafter, referred to as a Si transistor), and thus can be used in an extremely wide range of temperatures. Therefore, an imaging device and a semiconductor device which include the OS transistors are suitable for use in automobiles, aircrafts, and spacecrafts. Moreover, the OS transistor has higher drain withstand voltage than the Si transistor. To utilize avalanche multiplication, a photoelectric conversion element including a selenium-based material in a photoelectric conversion layer is preferably operated while a relatively high voltage (e.g., 10 V or more) is applied. Therefore, by combination of the OS transistor and the photoelectric conversion element in which the selenium-based material is used for the photoelectric conversion layer, a highly reliable imaging device can be obtained. The layer1300may include the transistors43and44. As the transistors43and44, a transistor including silicon in an active layer or an active region is preferably used. Such a transistor has a high on-state current and efficiently amplifies the potential of the node FD. Moreover, the layer1200includes a metal layer401aelectrically connected to the gate of the transistor44. As illustrated inFIG.1A, the metal layers401aand401bare provided in a position to be in contact with each other directly and include a connection portion401at which the metal layers401aand401bare electrically connected to each other. Alternatively, the imaging device of one embodiment of the present invention may have a structure illustrated inFIG.2A. In a structure illustrated inFIG.2A, the layer1100includes the photoelectric conversion element PD, a metal layer402belectrically connected to one electrode of the photoelectric conversion element PD, and a metal layer403belectrically connected to the other electrode of the photoelectric conversion element PD. Note that the metal layer403bis not necessarily provided in the layer1100. The layer1200includes the transistor41, the transistor42, a metal layer402aelectrically connected to one of the source and the drain of the transistor41, and a metal layer403aelectrically connected to the wiring71. Note that the wiring71and the metal layer403aare not necessarily provided in the layer1200. The layer1300includes the transistors43and44. As illustrated inFIG.2A, the metal layers402aand402bare provided in a position to be in contact with each other directly and include a connection portion402at which the metal layers402aand402bare electrically connected to each other. Furthermore, the metal layers403aand403bare provided in a position to be in contact with each other directly and include a connection portion403at which the metal layers403aand403bare electrically connected to each other. An imaging device of one embodiment of the present invention may have a structure illustrated inFIG.2B. In a structure illustrated inFIG.2B, the layer1100includes the photoelectric conversion element PD, a metal layer402belectrically connected to one electrode of the photoelectric conversion element PD, and a metal layer403belectrically connected to the other electrode of the photoelectric conversion element PD. Note that the metal layer403bis not necessarily provided in the layer1100. The layer1200includes the transistor41, the transistor42, the metal layer402aelectrically connected to one of the source and the drain of the transistor41, the metal layer403aelectrically connected to the wiring71, and the metal layer401belectrically connected to one of the source and the drain of each of the transistors41and42. Note that the wiring71and the metal layer403ais not necessarily provided in the layer1200. The layer1300includes the transistors43and44and the metal layer401aelectrically connected to the gate of the transistor43. As illustrated inFIG.2B, the metal layers402aand402bare provided in a position to be in contact with each other directly and include the connection portion402at which the metal layers402aand402bare electrically connected to each other. Furthermore, the metal layers403aand403bare provided in a position to be in contact with each other directly and include the connection portion403at which the metal layers403aand403bare electrically connected to each other. Moreover, the metal layers401aand401bare provided in a position to be in contact with each other directly and include the connection portion401at which the metal layers401aand401bare electrically connected to each other. FIGS.3A,3B, and3Ceach illustrate a specific structure of the pixel20corresponding toFIG.1A.FIG.3Ais a cross-sectional view of the transistors41to44in the channel length direction.FIG.3Bis a cross-sectional view which is taken along dashed-dotted line X1-X2inFIG.3Aand which illustrates a cross section of the transistor41in the channel width direction.FIG.3Cis a cross-sectional view which is taken along dashed-dotted line Y1-Y2inFIG.3Aand which illustrates a cross section of the transistor42in the channel width direction. Although the wirings, the electrodes, the metal layers, and contact plugs (conductors82) are illustrated as independent components in the cross-sectional views in this embodiment, some of them are provided as one component in some cases when they are electrically connected to each other. In addition, a structure in which the components such as wirings, electrodes, and metal layers are connected to each other through the conductors82is only an example, and the components may be directly connected to each other not through the conductor82. Insulating layers81ato81jeach functioning as a protective film, an interlayer insulating film, or a planarization film are provided over the components such as transistors. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layers81ato81j. Alternatively, an organic insulating film such as an acrylic resin film or a polyimide resin film may be used. Top surfaces of the insulating layers81ato81jare preferably subjected to planarization treatment as necessary by chemical mechanical polishing (CMP) or the like. In some cases, one or more of the wirings and the like illustrated in the drawing are not provided, or a wiring, a transistor, or the like that is not illustrated in the drawing is included in each layer. In some cases, a layer that is not illustrated in the drawing is included. Furthermore, one or more of the layers illustrated in the drawing are not included in some cases. Insulating layers80aand80bare provided between a region including an OS transistor and a region including a Si device (a Si transistor or a Si photodiode). Dangling bonds of silicon are terminated with hydrogen in insulating layers provided in the vicinities of the active regions of the transistors43and44. Therefore, the hydrogen has an effect of improving the reliability of the transistors43and44. Meanwhile, hydrogen in insulating layers which are provided in the vicinity of the oxide semiconductor layer that is the active layer of the transistors41and42causes generation of carriers in the oxide semiconductor layer. Therefore, the hydrogen might reduce the reliability of the transistors41and42. For this reason, the insulating layer80bthat has a function of preventing diffusion of hydrogen is preferably provided between one layer including the Si transistor and another layer stacked thereover that includes the OS transistor. Hydrogen is confined in one layer by the insulating layer80b, so that the reliability of the transistors43and44can be improved. Furthermore, diffusion of hydrogen from the one layer to the other layer is inhibited, so that the reliability of the transistors41and42can also be improved. For this reason, the insulating layer80athat has a function of preventing diffusion of hydrogen is preferably provided between one layer including the Si photodiode and another layer including the OS transistor. The insulating layers80aand80bcan be, for example, formed using, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ). InFIG.3A, the photoelectric conversion element PD included in the layer1100is a PN photodiode using a single crystal silicon substrate. The photoelectric conversion element PD may include aregion620, a p−region630, an n-type region640, and aregion650. The n-type region640is electrically connected to a metal layer405. Theregion650is electrically connected to a metal layer406. The metal layers405and406are provided to penetrate an insulating layer81g. The transistors41and42which are OS transistors are provided in the layer1200. Although each of the transistors41and42includes a back gate, only the transistor41may include a back gate, for example. As illustrated inFIG.3B, the back gate might be electrically connected to a front gate of the transistor, which is provided to face the back gate. Alternatively, different fixed potentials might be supplied to the back gate and the front gate. The metal layer401bincludes a region embedded in an insulating layer81dand the metal layer401bis electrically connected to the other of the source and the drain of the transistor41and one of the source and the drain of the transistor42through a conductive layer, the conductor82, or the like. One of the source and the drain of the transistor41is electrically connected to the metal layer405through the conductive layer, the conductor82, or the like. In addition, the wiring71is electrically connected to the metal layer406through the conductor82. The transistors43and44which are Si transistors are provided in the layer1300. AlthoughFIG.3Ashows the transistors43and44of a fin type, the transistors may be of a planar type as illustrated inFIG.4A. Alternatively, as illustrated inFIG.4B, transistors each including an active layer660formed using a silicon thin film may be used. The active layer660can be formed using polycrystalline silicon or single crystal silicon of a silicon-on-insulator (SOI) structure. The metal layer401aincludes a region embedded in an insulating layer81cand the metal layer401ais electrically connected to the gate of the transistor43through the conductive layer, the conductor82, or the like. The metal layers401aand401bare preferably formed using metal elements using the same main component. Moreover, the insulating layers81cand81dare preferably formed using the same component. For example, Cu, Al, Sn, Zn, W, Ag, Pt, Au, or the like can be used for the metal layers401aand401b. Preferably, Cu, Al, W, or Au is used for easy bonding. In addition, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used for the insulating layers81cand81d. When the above same metal materials and the above insulating materials are used for the metal layers401aand401band the insulating layers81cand81d, respectively, a bonding step can be performed at a bonding portion a inFIG.3. The metal layers401aand401bcan be electrically connected to each other through the bonding step. Furthermore, the connection between the insulating layers81cand81dcan obtain mechanical strength. For bonding the metal layers to each other, surface activated bonding and diffusion bonding can be used. Surface activated bonding is a method in which an oxide film and a layer adsorbing impurities over the surface of the metal layer are removed by sputtering treatment and the cleaned and activated surfaces of the metal layers are made to be in contact with each other to be bonded to each other. Diffusion bonding is a method in which the surfaces of the metal layers are bonded to each other by using temperature and pressure together. Both methods can cause bonding at an atomic level, thereby obtaining not only electric but also mechanical strength. For bonding the insulating layers to each other, hydrophilic bonding or the like can be used after obtaining high planarity by polishing or the like. Hydrophilic bonding is the following method: the surfaces of the metal layers are subjected to hydrophilicity treatment by oxygen plasma or the like, made to be in contact with each other to be bonded to each other temporarily, and then dehydrated by heat treatment so that final bonding is performed. Also the hydrophilic bonding can cause bonding at an atomic level; thus, the connection can obtain mechanical strength. The insulating layers and the metal layers are mixed on the bonding surfaces of the layers1300and1200; therefore, surface activated bonding and hydrophilic bonding are preferably performed together when the layers1300and1200are bonded to each other. For example, the following method can be used: the surfaces of the layers1300and1200are made clean after polishing, the surfaces of the metal layers are subjected to antioxidant treatment and hydrophilicity treatment, and then bonding is performed. Alternatively, hydrophilicity treatment may be performed on the surfaces of the metal layers with the use of hardly oxidizable metal such as Au. Note that a bonding method other than the above method may be used. Bonding is performed after the devices are completed, so that OS transistors and Si transistors can be fabricated using an optimal process for each of them. Therefore, the electric characteristics and reliability of the transistors can be improved. Moreover, bonding is performed after top-gate transistors are completed, so that front gate electrodes of the OS transistors and gate electrodes of the Si transistors are provided so that top surfaces thereof face each other. Alternatively, the pixel20may have a stacked structure illustrated inFIG.5. The pixel20inFIG.5is different from that inFIG.3Aonly in the structure of the layer1100and the other structures are the same. InFIG.5, the photoelectric conversion element PD included in the layer1100is a photodiode using selenium for a photoelectric conversion layer. The photoelectric conversion element PD may include a photoelectric conversion layer561, a light-transmitting conductive layer562, an electrode566, a partition wall567, and a wiring571. The electrode566is electrically connected to the metal layer405. The light-transmitting conductive layer562is electrically connected to the metal layer406through the wiring571. The metal layers405and406are provided to penetrate the insulating layer81g. FIG.5illustrates the photoelectric conversion element PD including a selenium-based material for the photoelectric conversion layer561. The photoelectric conversion element PD including a selenium-based material has high external quantum efficiency with respect to visible light. Furthermore, the selenium-based material has a high light-absorption coefficient, making the photoelectric conversion layer561thin easily. The photoelectric conversion element PD including a selenium-based material can be a highly sensitive sensor in which the amount of amplification of electrons is large because of avalanche multiplication. In other words, the use of a selenium-based material for the photoelectric conversion layer561allows a sufficient amount of photocurrent to be obtained even when the pixel area is reduced. Thus, the photoelectric conversion element PD including a selenium-based material is also suitable for imaging in a low-illuminance environment. Amorphous selenium or crystalline selenium can be used as a selenium-based material. Crystalline selenium can be obtained by, for example, depositing amorphous selenium and then performing heat treatment. When the crystal grain size of crystalline selenium is smaller than a pixel pitch, variation in characteristics between pixels can be reduced. Moreover, crystalline selenium has higher spectral sensitivity to visible light and light-absorption coefficient for visible light than those of amorphous selenium. Although the photoelectric conversion layer561is a single layer inFIG.5, gallium oxide, cerium oxide, an In—Ga—Zn oxide, or the like may be provided as a hole-blocking layer568on a light-receiving surface side as illustrated inFIG.6A. Alternatively, as illustrated inFIG.6B, nickel oxide, antimony sulfide, or the like may be provided as an electron injection blocking layer569on the electrode566side. Alternatively, as illustrated inFIG.6C, the hole-blocking layer568and the electron injection blocking layer569may be provided. The photoelectric conversion layer561may be a layer including a compound of copper, indium, and selenium (CIS). Alternatively, a layer including a compound of copper, indium, gallium, and selenium (CIGS) may be used. A photoelectric conversion element including the CIS layer or the CIGS layer can also utilize avalanche multiplication like the photoelectric conversion element including a layer of selenium alone. In the photoelectric conversion element PD using the selenium-based material, for example, the photoelectric conversion layer561can be provided between the electrode566formed using a metal material or the like and the light-transmitting conductive layer562. Furthermore, CIS and CIGS are p-type semiconductors, and an n-type semiconductor such as cadmium sulfide or zinc sulfide may be provided in contact with the p-type semiconductor in order to form a junction. Although the light-transmitting conductive layer562is directly in contact with the wiring571inFIG.5, they may be in contact with each other through a wiring588as illustrated inFIG.6D. Although the photoelectric conversion layer561and the light-transmitting conductive layer562are not divided between pixel circuits inFIG.5, they may be divided between circuits as illustrated inFIG.6E. In a region between pixels where the electrode566is not provided, the partition wall567formed of an insulator is preferably provided, thereby preventing generation of a crack in the photoelectric conversion layer561and the light-transmitting conductive layer562. However, the partition wall567is not necessarily provided as illustrated inFIGS.7A and7B. The electrode566, the wiring571, and the like may be a multilayer. For example, as illustrated inFIG.7C, the electrode566can include two conductive layers566aand566band the wiring571can include two conductive layers571aand571b. In the structure inFIG.7C, for example, the conductive layers566aand571amay be made of a low-resistance metal or the like, and the conductive layers566band571bmay be made of a metal or the like that exhibits an excellent contact property with the photoelectric conversion layer561. Such a structure improves the electrical properties of the photoelectric conversion element PD. Note that some kinds of metal may cause electrochemical corrosion by being in contact with the light-transmitting conductive layer562. Even when such a metal is used in the conductive layer571a, electrochemical corrosion can be prevented by the conductive layer571b. The conductive layers566band571bcan be formed using, for example, molybdenum, tungsten, or the like. The conductive layers566aand571acan be formed using, for example, aluminum, titanium, or a stack of titanium, aluminum, and titanium that are stacked in that order. As illustrated inFIG.7D, the light-transmitting conductive layer562may be connected to the wiring571through the conductor82and the wiring588. The partition wall567can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition wall567may be colored black or the like in order to shield the transistors and the like from light and/or to determine the area of a light-receiving portion in each pixel. Alternatively, the pixel20may have a stacked structure illustrated inFIG.8A. The pixel20inFIG.8Ais different from the pixel20inFIG.3Aonly in the structure of the layer1100and the other structures are the same. InFIG.8A, the photoelectric conversion element PD included in the layer1100is a PIN photodiode using an amorphous silicon film or a microcrystalline silicon film in a photoelectric conversion layer. The photoelectric conversion element PD may include an n-type semiconductor layer565, an i-type semiconductor layer564, a p-type semiconductor layer563, the electrode566, the wiring571, and the wiring588. The electrode566is electrically connected to the metal layer405. The p-type semiconductor layer563is electrically connected to the metal layer406through the wirings588and571. The metal layers405and406are provided to penetrate the insulating layer81g. The i-type semiconductor layer564is preferably formed using amorphous silicon. The p-type semiconductor layer563and the n-type semiconductor layer565can each be formed using amorphous silicon, microcrystalline silicon, or the like that includes a dopant imparting the corresponding conductivity type. A photodiode in which a photoelectric conversion layer is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and therefore can easily sense weak visible light. FIGS.8B to8Dshow other examples of the structure of the photoelectric conversion element PD having a structure of a PIN thin film photodiode and the connection configuration between the photoelectric conversion element PD and the wirings. Note that the structure and the connection configuration are not limited to the above examples, and other configurations may be applied. FIG.8Billustrates a structure of the photoelectric conversion element PD that includes the light-transmitting conductive layer562in contact with the p-type semiconductor layer563. The light-transmitting conductive layer562serves as an electrode and can increase the output current of the photoelectric conversion element PD. For the light-transmitting conductive layer562, the following can be used: indium tin oxide; indium tin oxide containing silicon; indium oxide containing zinc; zinc oxide; zinc oxide containing gallium; zinc oxide containing aluminum; tin oxide; tin oxide containing fluorine; tin oxide containing antimony; graphene; graphene oxide; or the like. The light-transmitting conductive layer562is not limited to a single layer, and may be a stacked layer of different films. In the structure ofFIG.8C, the light-transmitting conductive layer562and the wiring571are connected to each other through the conductor82and the wiring588. Note that the p-type semiconductor layer563of the photoelectric conversion element PD and the wiring571may be connected to each other through the conductor82and the wiring588. In the structure ofFIG.8C, the light-transmitting conductive layer562is not necessarily provided. FIG.8Dillustrates a structure in which an opening exposing the p-type semiconductor layer563is provided in an insulating layer81kcovering the photoelectric conversion element PD, and the light-transmitting conductive layer562covering the opening is electrically connected to the wiring571. The photoelectric conversion element PD including the aforementioned selenium-based material, amorphous silicon, or the like can be formed through general semiconductor manufacturing processes such as a deposition process, a lithography process, and an etching process. In addition, because the resistance of the selenium-based material is high, the photoelectric conversion layer561does not need to be divided between circuits as illustrated inFIG.5. Therefore, the imaging device in one embodiment of the present invention can be manufactured with a high yield at low cost. Note that the photoelectric conversion element PD included in the pixel20inFIG.5andFIG.8Ais a stack of thin films; thus, the photoelectric conversion element PD is preferably formed after the bonding step. Alternatively, the pixel20may have a stacked structure illustrated inFIG.9. In the pixel20inFIG.9, the layer1200is formed over the layer1300and the layer1200and the layer1100which are formed separately are bonded to each other at a bonding portion b. That is, a bonding portion of metal layers is provided between the layers1300and1200in a stacked structure inFIG.3Aand between the layers1200and1100in a stacked structure inFIG.9. InFIG.9, the photoelectric conversion element PD included in the layer1100is a PN photodiode using a single crystal silicon substrate. The photoelectric conversion element PD may include theregion620, the p−region630, the n-type region640, and theregion650. The n-type region640is electrically connected to the metal layer402b. Theregion650is electrically connected to the metal layer403b. The metal layers405and406are provided to penetrate an insulating layer81g. The metal layers402aand403aare provided in the layer1200. The metal layer402aincludes a region embedded in an insulating layer81hand the metal layer402ais electrically connected to one of the source and the drain of the transistor41through the conductive layer, the conductor82, or the like. The metal layer403aincludes a region embedded in an insulating layer81hand the metal layer403ais electrically connected to the wiring71through the conductor82. The transistors43and44which are Si transistors are provided in the layer1300. The gate of the transistor43is electrically connected to the other of the source and the drain of the transistor41and one of the source and the drain of the transistor42through the conductive layer, the conductor82, or the like. Alternatively, the pixel20may have a structure illustrated inFIG.10. In the pixel20inFIG.10, the layers1300,1200and1100are formed separately and the layers1300and1200are bonded to each other at the bonding portion a and the layers1200and1100are bonded to each other at the bonding portion b. That is, bonding portions of metal layers are provided between the layers1300and1200and between the layers1200and1100. InFIG.10, the photoelectric conversion element PD included in the layer1100is a PN photodiode using a single crystal silicon substrate. The photoelectric conversion element PD may include theregion620, the p−region630, the n-type region640, and theregion650. The n-type region640is electrically connected to a metal layer402b. The p° region650is electrically connected to a metal layer403b. The metal layers402aand403bare provided penetrating an insulating layer81g. The metal layers401b,402a, and403aare provided in the layer1200. The metal layer401bincludes a region embedded in the insulating layer81dand the metal layer401bis electrically connected to the other of the source and the drain of the transistor41and one of the source and the drain of the transistor42through the conductive layer, the conductor82, or the like. The metal layer402aincludes a region embedded in an insulating layer81gand the metal layer402ais electrically connected to one of the source and the drain of the transistor41through the conductive layer, the conductor82, or the like. The metal layer403aincludes a region embedded in an insulating layer81gand the metal layer403ais electrically connected to the wiring71through the conductor82. The metal layer401ais provided in the layer1300. The metal layer401aincludes a region embedded in an insulating layer81cand the metal layer401ais electrically connected to one of the source and the drain of the transistor41through the conductive layer, the conductor82, or the like. An example of the method for fabricating the stacked structure inFIG.3Awill be described with reference to FIGS.11A1,11A2, and11A3. First, the layer1300including the insulating layer81cand the metal layer401ain the uppermost layer is formed (see FIG.11A1). The metal layer401amay be formed using the following method, for example: a through-hole reaching a wiring layer electrically connected to the gate electrode of the transistor43is formed in the insulating layer81c, a metal layer is provided by a CVD method, a plating method, or the like so as to fill the through-hole, and an surplus metal layer is removed by polishing surface thereof. Alternatively, the following method may be used: the metal layer401ais formed in advance by a CVD method, a sputtering method, or the like, the insulating layer81cis formed to cover the metal layer401a, and the top surface of the metal layer401ais exposed by polishing the surface of the insulating layer81c. In any of the methods, a level difference between the metal layer401aand the insulating layer81cis preferably reduced as much as possible by flattening the entire surface of each layer by a CMP method or the like. Next, the photoelectric conversion element PD is formed and the layer1200including the insulating layer81dand the metal layer401bin the uppermost layer is formed over the photoelectric conversion element PD. The photoelectric conversion element PD is formed by, for example, forming an impurity region in a single crystal silicon substrate670by a diffusion method, a doping method, or the like. Then, components such as an OS transistor are electrically connected to each other to be formed and the insulating layer81dand the metal layer401bare formed in the uppermost layer of the photoelectric conversion element PD. The metal layer401bcan be formed in a manner similar to that of the metal layer401aand the surfaces of the insulating layer81dand the metal layer401bare planarized by a CMP method or the like. Then, the aforementioned treatment before bonding is performed on the planarized surfaces of the layers1300and1200. Subsequently, bonding is performed after positioning so that the metal layers401aand401bare in contact with each other and the metal layers401aand401band the insulating layers81cand81dare bonded to each other by an appropriate process (see FIG.11A2). After bonding, an unnecessary region of the single crystal silicon substrate670is polished to expose a light-receiving surface of the photoelectric conversion element PD and a protective film such as an insulating layer is formed as necessary (see FIG.11A3). Through the above steps, the stacked structure inFIG.3Ais completed. Note that polishing of the single crystal silicon substrate670may be performed before the bonding step or forming an OS transistor. In this case, polishing is preferably performed using a peelable adhesive or the like and a support substrate as appropriate. An example of the method for fabricating the stacked structure inFIG.5andFIG.8Awill be described with reference to FIGS.11B1,11B2,11B3, and11B4. Note that the aforementioned fabricating method of the pixel20inFIG.3Acan be referred to for the fabricating method of the layer1300and the bonding step of the layers1300and1200. First, the layer1300including the insulating layer81cand the metal layer401ais formed in the uppermost layer (see FIG.11B1). Next, a separation layer1800is provided over a flat support substrate1700such as a glass substrate or a semiconductor substrate, and the layer1200including the insulating layer81dand the metal layer401bin the uppermost layer is formed over the separation layer1800. The separation layer1800can be formed using a stack of a tungsten film and a silicon oxide film, for example. The stack is thermally stable; therefore, separation can be performed in the vicinity of the interface between the tungsten film and the silicon oxide film by applying a physical force after the manufacturing process of the transistors. Alternatively, a polyimide film may be used as the separation layer1800. In the case of using a polyimide film, a light-transmitting substrate is preferably used. Accordingly, the polyimide film is made to be fragile by a light such as laser light emitted from a light-transmitting substrate side and separation can be performed after the manufacturing process of the transistors. Alternatively, a thermally stable peelable adhesive or the like may be used as the separation layer1800. Then, bonding of the layers1300and1200is performed (see FIG.11B2). After bonding, a stack of the layers1300and1200is separated from the support substrate1700. When part of the separation layer remains over the surface of the layer1200, part of the separation layer is removed by washing, etching, or the like to expose the surfaces of the metal layers405and406(see FIG.11B3andFIG.3A). Subsequently, the layer1100including the photoelectric conversion element PD is formed over the layer1200(see FIG.11B4). Through the above steps, the stacked structure inFIG.5orFIG.8Ais completed. An example of the method for fabricating the stacked structure inFIG.9will be described with reference to FIGS.12A1,12A2,12A3, and12A4. Note that the fabricating method of the stacked structure inFIG.3Acan be referred to for the fabricating method of the metal layers at a bonding portion and the bonding method thereof. First, the layer1300is formed (see FIG.12A1) and the layer1200including the insulating layer81hand the metal layers402aand403ain the uppermost layer is formed over the layer1300(see FIG.12A2). Then, the components included in the layers1300and1200are electrically connected to each other as necessary. Next, the layer1200and the single crystal silicon substrate670in which the photoelectric conversion element PD is provided are bonded to each other and the metal layers402aand402b, the metal layers403aand403b, and the insulating layers81hand81gare bonded to each other (see FIG.12A3). After bonding, an unnecessary region of the single crystal silicon substrate670is polished to expose the light-receiving surface of the photoelectric conversion element PD and a protective film such as an insulating layer is formed as necessary (see FIG.12A4). Through the above steps, the layer1100can be formed and the stacked structure inFIG.9is completed. Note that polishing of the single crystal silicon substrate670may be performed before the bonding step. In this case, polishing is preferably performed using a peelable adhesive or the like and a support substrate as appropriate. An example of the method for fabricating the stacked structure inFIG.10will be described with reference to FIGS.12B1,12B2,12B3,12B4and12B5. Note that the fabricating method of the stacked structure inFIG.3Acan be referred to for the fabricating method and the bonding method of the metal layers at a bonding portion. First, the layer1300including the insulating layer81cand the metal layer401ain the uppermost layer is formed (see FIG.12B1). Next, the separation layer1800is provided over the flat support substrate1700such as a glass substrate or a semiconductor substrate, and the layer1200including the insulating layer81gand the metal layers402aand403ain the lowermost layer and including the insulating layer81dand the metal layer401bin the uppermost layer is formed over the separation layer1800. Then, bonding of the layers1300and1200will be performed (see FIG.12B2). After bonding, a stack of the layers1300and1200is separated from the support substrate1700. When part of the separation layer remains over the surface of the layer1200, part of the separation layer is removed by washing, etching, or the like to expose the surfaces of the metal layers402aand403a(see FIG.12B3). Next, the layer1200and the single crystal silicon substrate670in which the photoelectric conversion element PD is provided are bonded to each other and the metal layers402aand402b, the metal layers403aand403b, and the insulating layers81hand81gare bonded to each other (see FIG.12B4). After bonding, an unnecessary region of the single crystal silicon substrate670is polished to expose the light-receiving surface of the photoelectric conversion element PD and a protective film such as an insulating layer is formed as necessary (see FIG.12B5). Through the above steps, the layer1100can be formed and the stacked structure inFIG.10is completed. Note that polishing of the single crystal silicon substrate670may be performed before the bonding step. In this case, polishing is preferably performed using a peelable adhesive or the like and a support substrate as appropriate. Alternatively, in an imaging device of one embodiment of the present invention, a circuit different from a pixel circuit can be provided by Si transistors formed in the layer1300. Examples of the circuit include a driver circuit such as a column driver and a row driver, a data converter circuit such as an A/D converter, a noise reduction circuit such as a CDS circuit, and a control circuit of a whole imaging device. A transistor46and a transistor47included in any of the above circuits are illustrated inFIG.13. The transistors46and47can be formed in a region overlapping with the photoelectric conversion element PD. Alternatively, one or both of the transistors46and47may be formed in a region overlapping with one or both of the transistors41and42. That is, the above circuit is formed in a region overlapping with the pixel20. Note that although a structure example of a CMOS inverter where the transistor46is a p-channel transistor and the transistor47is an n-channel transistor is illustrated inFIG.13, another circuit configuration may also be employed. Alternatively, as illustrated inFIG.14, the transistor47may be an OS transistor provided in the layer1200. In the configuration illustrated inFIG.14, the transistors46and47can be provided in a region overlapping with each other in a bonding step, so that the area of the circuit can be reduced. In addition, when p-channel transistors are formed as the transistors44and45included in the pixel20, all the transistors provided over a single-crystal silicon substrate600can be p-channel transistors; thus, forming of n-channel Si transistors can be omitted. Note that althoughFIG.13andFIG.14each illustrate the stacked structure in which the transistors46and47are added to the pixel20inFIG.3A, the transistors46and47can also be added to the pixel20inFIG.5,FIG.9, orFIG.10. FIG.15Ais a block diagram illustrating a circuit configuration of an imaging device of one embodiment of the present invention. The imaging device includes a pixel array21including the pixels20arranged in a matrix, a circuit22(row driver) having a function of selecting a row of the pixel array21, a circuit23(CDS circuit) for performing correlated double sampling (CDS) on an output signal of the pixel20, a circuit24(A/D converter circuit or the like) having a function of converting analog data output from the circuit23to digital data, and a circuit25(column driver) having a function of selecting and reading data converted in the circuit24. Note that a configuration not including the circuit23can be employed. Furthermore, the circuits23to25are collectively referred to as a circuit30. FIG.15Billustrates a circuit diagram of the circuit23and a block diagram of the circuit24; the circuit23and the circuit24are connected to one column of the pixel array21. The circuit23can include a transistor51, a transistor52, a capacitor C3, and a capacitor C4. Furthermore, the circuit24can include a comparator circuit27and a counter circuit29. A transistor53serves as a current supply circuit. The wiring91(OUT1) is electrically connected to one of a source and a drain of the transistor53, and a power supply line is connected to the other of the source and the drain of the transistor53. As the power supply line, a low potential power supply line (VSS) can be used, for example Bias voltage is always applied to a gate of the transistor53. In the circuit23, one of a source and a drain of the transistor51is electrically connected to one of a source and a drain of the transistor52. One of the source and the drain of the transistor51is electrically connected to one electrode of the capacitor C3. The other of the source and the drain of the transistor52is electrically connected to one electrode of the capacitor C4. The other of the source and the drain of the transistor52is electrically connected to a wiring92(OUT2). The other of the source and the drain of the transistor51is electrically connected to a high potential power supply line (CDSVDD) through which a reference potential is supplied, for example. The other electrode of the capacitor C4is electrically connected to a low potential power supply line (CDSVSS), for example. An operation example of the circuit23when the circuit23is connected to the pixel20inFIG.1Bwill be described. First, the transistors51and52are turned on. Next, the potential of imaging data is output from the pixel20to the wiring91(OUT1), and the reference potential (CDSVDD) is held in the wiring92(OUT2). Then, the transistor51is turned off and a reset potential (here, a potential higher than the potential of the imaging data, for example, a VDD potential) is output from the pixel20to the wiring91(OUT1). At this time, the potential of the wiring92(OUT2) is a value obtained by adding the absolute value of a difference between the potential of the imaging data and the reset potential to the reference potential (CDSVDD). Thus, a potential signal with little noise that is obtained by adding the net potential of the imaging data to the reference potential (CDSVDD) can be supplied to the circuit24. In the case where the reset potential is lower than the potential of the imaging data (for example, in the case where the reset potential is a potential GND or the like), the potential of the wiring92(OUT2) is a value obtained by subtracting the absolute value of the difference between the potential of the imaging data and the reset potential from the reference potential (CDSVDD). In the circuit24, a signal potential that is input from the circuit23to the comparator circuit27and a reference potential (RAMP) that is swept to be increased or decreased are compared. Then, in accordance with the output of the comparator circuit27, the counter circuit29operates to output a digital signal to a wiring93(OUT3). In an imaging device of one embodiment of the present invention, a stacked structure of the pixel array21and a circuit portion35including the circuit30can be employed. For example, a stacked structure as illustrated in the perspective view inFIG.16C, which includes the pixel array21having the top view inFIG.16Aand the circuit portion35having the top view in FIGS.16B1and16B2can be obtained. With such a structure, transistors suitable for respective elements can be used, and the area of the imaging device can be reduced. Note that the layouts of the circuit in FIGS.16B1and16B2are examples, and another layout may be used. Although a control circuit26is provided in the circuit portion35, the control circuit26may be provided outside the circuit portion35. FIG.16B1illustrates a structure where the circuits22and30are divided into two parts and placed not at the edge portion but near the center. Shift register circuits included in the circuits22and30may be operated independently in divided portions or operated as one shift register circuit. The circuits22and30in FIG.16B2are divided into two parts in a manner similar to that in FIG.16B1but placed obliquely. With the structure illustrated in FIG.16B1or16B2, loads of the wirings connected to the pixel20can be reduced as compared with the case where the circuits22and30are placed at the edge portion. Although the loads of the wirings are not uniform, it does not matter when wiring capacity and wiring resistance are small. To achieve both a high-speed operation and the configuration of a CMOS circuit, the circuits22and30are preferably formed using transistors including silicon (hereinafter, referred to as Si transistors). For example, the circuit portion35can be formed over a silicon substrate. The pixel array21is preferably formed using transistors including an oxide semiconductor (hereinafter, referred to as OS transistors). Note that some transistors included in the circuits22and30may be formed using OS transistors. FIG.17Ais a cross-sectional view of an example of a mode in which a color filter and the like are added to an imaging device. The cross-sectional view illustrates part of a region including pixel circuits for three pixels. An insulating layer2500is formed over the layer1100where the photoelectric conversion element PD is formed. As the insulating layer2500, a silicon oxide film or the like with a high visible-light transmitting property can be used. In addition, a silicon nitride film may be stacked as a passivation film. In addition, a dielectric film of hafnium oxide or the like may be stacked as an anti-reflection film. A light-blocking layer2510may be formed over the insulating layer2500. The light-blocking layer2510has a function of inhibiting color mixing of light passing through an upper color filter. The light-blocking layer2510can be formed of a metal layer of aluminum, tungsten, or the like, or a stack of the metal layer and a dielectric film functioning as an anti-reflection film. An organic resin layer2520can be provided as a planarization film over the insulating layer2500and the light-blocking layer2510. A color filter2530(a color filter2530a, a color filter2530b, and a color filter2530c) is formed in each pixel. For example, the color filter2530a, the color filter2530b, and the color filter2530ceach have a color of red (R), green (G), blue (B), yellow (Y), cyan (C), magenta (M), or the like, so that a color image can be obtained. A light-transmitting insulating layer2560or the like can be provided over the color filter2530. As illustrated inFIG.17B, an optical conversion layer2550may be used instead of the color filter2530. Such a structure enables an imaging device to take images in various wavelength regions. For example, when a filter that blocks light having a wavelength shorter than or equal to that of visible light is used as the optical conversion layer2550, an infrared imaging device can be obtained. When a filter that blocks light having a wavelength shorter than or equal to that of near infrared light is used as the optical conversion layer2550, a far-infrared imaging device can be obtained. When a filter that blocks light having a wavelength longer than or equal to that of visible light is used as the optical conversion layer2550, an ultraviolet imaging device can be obtained. Furthermore, when a scintillator is used as the optical conversion layer2550, an imaging device that takes an image visualizing the intensity of radiations and is used for an X-ray imaging device or the like can be obtained. Radiation such as X-rays passes through an object to enter a scintillator, and then is converted into light (fluorescence) such as visible light or ultraviolet light owing to a phenomenon known as photoluminescence. Then, the photoelectric conversion element PD detects the light to obtain image data. Furthermore, the imaging device having the structure may be used in a radiation detector or the like. A scintillator is formed of a substance that, when irradiated with radiation such as X-rays or gamma-rays, absorbs energy of the radiation to emit visible light or ultraviolet light. For example, a resin or ceramics in which any of Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, and ZnO is dispersed can be used. FIG.47Ais a photograph of an X-ray imaging panel fabricated using an OS transistor. The panel size is 100.5 mm×139 mm, the number of pixels is 384×512, the pixel size is 120 □m×120 □m, the resolution is 106 ppi, and amorphous silicon is used for a photodiode. In addition, a row driver for selecting a pixel and a multiplexer for controlling an output signal are incorporated in the panel. FIG.47Bis a photograph obtained by X-ray imaging captured with the X-ray imaging panel to which a scintillator (Gd2O2S:Tb) is added. A lead board, a coin of copper, and a clock whose exterior is a resin are placed on the panel and irradiated with X-rays from above to obtain an image. The scintillator does not emit light under the lead board which blocks X-rays, so that the photograph is black. The photograph under the coin of copper which transmits X-rays more easily than lead is gray. In addition, the clock whose exterior is a resin transmits X-rays; therefore, an image of inside metal components is taken. In the photoelectric conversion element PD using a selenium-based material, radiation such as X-rays can be directly converted into charge; thus, the scintillator is not necessarily used. Alternatively, as illustrated inFIG.17C, a microlens array2540may be provided over the color filters2530a,2530b, and2530c. Light penetrating lenses included in the microlens array2540goes through the color filters positioned thereunder to reach the photoelectric conversion element PD. Alternatively, as illustrated inFIG.17D, the microlens array2540may be provided over the optical conversion layer2550. Note that a region other than the layer1100inFIGS.17A to17Dis referred to as a layer1600. FIG.18illustrates a specific example of a stacked structure of the pixel20of one embodiment of the present invention, the microlens array2540illustrated inFIG.17C, and the like. In the example illustrated inFIG.18, the structure of the pixel20illustrated inFIG.3Ais used. In the example illustrated inFIG.19, the structure of the pixel illustrated inFIG.9is used. The photoelectric conversion element PD and the circuit of the pixel20can be positioned so as to overlap with each other in this manner, leading to a reduction in the size of the imaging device. As illustrated inFIG.18andFIG.19, a diffraction grating1500may be provided above the microlens array2540. An image of an object through the diffraction grating1500(i.e., a diffraction pattern) can be scanned into a pixel, and an input image (an object image) can be formed from a captured image in the pixel by arithmetic processing. In addition, the use of the diffraction grating1500instead of a lens can reduce the cost of electronic devices or the like including the imaging device. The diffraction grating1500can be formed using a light-transmitting material. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin film or a polyimide resin film may be used. Alternatively, a stack of the inorganic insulating film and the organic insulating film may be used. In addition, the diffraction grating1500can be formed by a lithography process using a photosensitive resin or the like. Alternatively, the diffraction grating1500can be formed by a lithography process and an etching process. Alternatively, the diffraction grating1500can be formed by nanoimprint lithography, laser scribing, or the like. A space X may be provided between the diffraction grating1500and the microlens array2540. The space X can be less than or equal to 1 mm, preferably less than or equal to 100 □m. The space may be an empty space or may be a sealing layer or an adhesion layer formed using a light-transmitting material. For example, an inert gas such as nitrogen or a rare gas can be sealed in the space. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided in the space. Alternatively, a liquid such as silicone oil may be provided. Even in the case where the microlens array2540is not provided, the space X may be provided between the color filter2530and the diffraction grating1500. The pixel20may have a circuit configuration illustrated inFIG.20B. The connection direction of the photoelectric conversion element PD in the pixel20inFIG.20Bis different from that in the pixel20inFIG.1A. In this case, the pixel20can be operated when the potentials of the wiring71(VPD) and the wiring72(VRS) in the description of the circuit inFIG.1Bare reversed. The transistors41to44in the pixel20may each have a back gate as illustrated inFIG.21A.FIG.21Aillustrates a configuration of applying a constant potential to the back gates, which enables control of the threshold voltages. Wirings75to78connected to the respective back gates can be supplied with a different potential separately. Alternatively, as illustrated inFIG.21B, the wirings connected to the respective back gates of the transistors41and42may be electrically connected to each other. The wirings connected to the back gates of the transistors43and44may be electrically connected to each other. In n-channel transistors, the threshold voltage is shifted in a positive direction when a potential lower than a source potential is applied to a back gate. In contrast, the threshold voltage is shifted in a negative direction when a potential higher than a source potential is applied to a back gate. Therefore, in the case where on/off of each of the transistors is controlled by the predetermined gate voltage, the off-state current can be reduced when a potential lower than a source potential is applied to a back gate and the on-state current can be reduced when a potential higher than a source potential is applied to a back gate. The node FD is desired to have high potential retention capability in the circuits inFIG.1,FIGS.20A and20B, andFIGS.21A and21B, so that OS transistors with a low off-state current are preferably used for the transistors41and42as described above. The off-state current can be reduced when a potential lower than a source potential is applied to the back gates of the transistors41and42. Therefore, the node FD can have high potential retention capability. As described above, Si transistors with a high on-state current are preferably used for the transistors43and44. The on-state current can be increased when a potential higher than a source potential is applied to the back gates of the transistors43and44. Therefore, a reading potential output to the wiring91(OUT1) can be defined immediately, that is, the transistors43and44can be operated at high frequency. Note that the same potential may be applied to a front gate and the back gate of the transistor44as illustrated inFIG.21C. Alternatively, the transistors43and44may not be Si transistors but OS transistors. Although the on-state current of the OS transistor is relatively low, the on-state current can be increased by providing a back gate, so that the OS transistor can be operated at high frequency. A plurality of potentials such as a signal potential and a potential applied to the back gate are used inside an imaging device besides power supply potentials. Supply of a plurality of potentials from the outside of an imaging device increases the number of terminals; thus, an imaging device preferably has a power supply circuit generating a plurality of potentials inside the imaging device. The operation of the pixel inFIG.21Awill be described using a timing chart inFIG.22. In the timing chart, “V1” can be a potential higher than a reference potential, such as a high power supply potential (VDD). “V0” can be a reference potential (source potential) such as 0 V, a potential GND, and a low power supply potential (VS S). First, at Time T1, the transistors41and42are turned on and the node FD is reset to a reset potential (e.g., VDD) when the potentials of the wiring75(RS) and the wiring61(TX) are set to “V1” (reset operation). At this time, the on-state current of the transistors41and42is increased when the potentials of the wirings75and76are set to potentials higher than “V0” (>“V0”), so that the reset operation can be performed immediately. At Time T2, the transistor42is turned off and the reset operation is terminated to start accumulation operation when the potential of the wiring75(RS) is set to “V0”. At this time, the off-state current of the transistor42can be reduced and supply of charge to the node FD by leakage current can be prevented when the potential of the wiring76is set to a potential lower than “V0”. Alternatively, at Time T2, the potential of the wiring75may be “V0”. At Time T3, the transistor41is turned off and the potential of the node FD is defined and held (holding operation) when the potential of the wiring61(TX) is set to “V0”. At this time, the off-state current of the transistor41can be reduced and leakage of charge from the node FD by leakage current can be prevented when the potential of the wiring75is set to a potential lower than “V0” (<“V0”). At Time T4, the transistor44is turned on and the potential of the wiring91(OUT1) changes depending on a current flowing through the transistor43when the potential of the wiring63(SE) is set to “V1” (reading operation). At this time, the on-state current of the transistors43and44is increased and the potential of the wiring91(OUT1) can be defined immediately when the potentials of the wirings77and78are set to potentials higher than “V0” (>“V0”). At Time5, the transistor44is turned off when the potential of the wiring63(SE) is set to “V0”, so that the reading operation is completed. Note that the potentials of the wirings75and76are preferably held lower than “V0” (<“V0”) so that the potential of the node FD does not change until the reading operation is completed. Alternatively, the potentials of the wirings75and76may be changed at the same timing in the above description. Through the above steps, a signal based on the potential of the node FD can be read. Note that the pixel20inFIG.1Amay be operated without controlling the wirings75to78in the timing chart inFIG.22. The pixel20inFIG.21Bmay be operated without controlling the wirings76and78in the timing chart inFIG.22. In a pixel circuit of one embodiment of the present invention, transistors may be shared among a plurality of pixels as illustrated inFIGS.23A and23B. FIG.23Aillustrates a pixel in which transistors are shared among a plurality of pixels. In the pixel, pixels20ato20deach include the photoelectric conversion element PD and the transistor41and share the transistors42to44and a capacitor C1. The operation of each of the transistors41included in the pixels20ato20dis controlled by wirings61ato61d. With this circuit configuration, reset operation, accumulation operation, holding operation, and reading operation can be sequentially performed by each pixel. This configuration is mainly suitable for imaging using a rolling shutter system. FIG.23Billustrates a pixel in which transistors are shared among a plurality of pixels. In the pixel, the pixels20ato20dinclude the photoelectric conversion elements PD, the transistors41, and the transistors45individually and share the transistors42to44and the capacitor C1. A potential can be held in the cathode of the photoelectric conversion element PD by providing the transistor45, whose operation is controlled by the potential of wiring65(GPD), between the photoelectric conversion element PD and the wiring71(VPD). This configuration is suitable for imaging using a global shutter system, in which reset operation, accumulation operation, and holding operation are sequentially performed in all the pixels at the same time and reading operation is performed by each pixel. In the pixel circuits illustrated inFIGS.23A and23B, the plurality of pixels (the pixels20ato20d) aligned in the direction in which the wiring91(OUT1) extends (hereinafter, referred to as a vertical direction) share the transistors; however, a plurality of pixels aligned in the direction in which the wiring63(SE) extends (hereinafter, referred to as a horizontal direction) may share transistors. Alternatively, a plurality of pixels aligned in the horizontal and vertical directions may share transistors. Alternatively, the number of pixels which share transistors is not limited to four, and may be two, three, or five or more. Although the wiring72(VRS) and the wiring73(VPI) are merged into one wiring and the wiring72(VRS) is omitted in a configuration inFIGS.23A and23B, the wiring72(VRS) may be included. In addition, although the other electrode of the capacitor C1is connected to the wiring73(VPI), the other electrode of the capacitor C1may be connected to the wiring71(VPD). As illustrated in FIGS.24A1and24B1, the imaging device may be bent. FIG.24A1illustrates a state in which the imaging device is bent along dashed-two dotted line Y1-Y2. FIG.24A2is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2in FIG.24A1. FIG.24A3is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2in FIG.24A1. FIG.24B1illustrates a state where the imaging device is bent along dashed-two dotted line X3-X4and dashed-two dotted line Y3-Y4. FIG.24B2is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4in FIG.24B1. FIG.24B3is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4in FIG.24B1. The bent imaging device enables the curvature of field and astigmatism to be reduced. Thus, the optical design of lens and the like, which is used in combination with the imaging device, can be facilitated. For example, the number of lenses used for aberration correction can be reduced; accordingly, the size or weight of semiconductor devices including the imaging device can be easily reduced. In addition, the quality of a captured image can be improved. In this embodiment, one embodiment of the present invention has been described. Other embodiments of the present invention are described in other embodiments. Note that one embodiment of the present invention is not limited thereto. In other words, various embodiments of the invention are described in this embodiment and the other embodiments, and one embodiment of the present invention is not limited to a particular embodiment. Although an example in which one embodiment of the present invention is applied to an imaging device is described, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, one embodiment of the present invention is not necessarily applied to an imaging device. One embodiment of the present invention may be applied to a semiconductor device with another function, for example Although an example in which a channel formation region, a source region, a drain region, or the like of a transistor includes an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention may include, for example, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor. Alternatively, for example, depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention does not necessarily include an oxide semiconductor. Although an example in which a global shutter system is employed is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, another system such as a rolling shutter system may be employed in one embodiment of the present invention. Alternatively, depending on circumstances or conditions, the global shutter system is not necessarily employed. This embodiment can be implemented in appropriate combinations with the configurations described in the other embodiments. Embodiment 2 In this embodiment, an OS transistor that can be used in one embodiment of the present invention will be described with reference to drawings. In the drawings in this embodiment, some components are enlarged, reduced in size, or omitted for easy understanding. FIGS.25A and25Bare a top view and a cross-sectional view illustrating a transistor101of one embodiment of the present invention.FIG.25Ais the top view, andFIG.25Billustrates a cross section in the direction of dashed-dotted line B1-B2inFIG.25A. A cross section in the direction of dashed-dotted line B3-B4inFIG.25Ais illustrated inFIG.27A. The direction of dashed-dotted line B1-B2is referred to as a channel length direction, and the direction of dashed-dotted line B3-B4is referred to as a channel width direction. The transistor101includes an insulating layer120in contact with a substrate115; an oxide semiconductor layer130in contact with the insulating layer120; conductive layers140and150electrically connected to the oxide semiconductor layer130; an insulating layer160in contact with the oxide semiconductor layer130and the conductive layers140and150; a conductive layer170in contact with the insulating layer160; an insulating layer175in contact with the conductive layers140and150, the insulating layer160, and the conductive layer170; and an insulating layer180in contact with the insulating layer175. The insulating layer180may function as a planarization film as necessary. The conductive layer140, the conductive layer150, the insulating layer160, and the conductive layer170can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively. A region231, a region232, and a region233inFIG.25Bcan function as a source region, a drain region, and a channel formation region, respectively. The region231and the region232are in contact with the conductive layer140and the conductive layer150, respectively. When a conductive material that is easily bonded to oxygen is used for the conductive layers140and150, the resistance of the regions231and232can be reduced. Specifically, since the oxide semiconductor layer130is in contact with the conductive layers140and150, an oxygen vacancy is generated in the oxide semiconductor layer130, and interaction between the oxygen vacancy and hydrogen that remains in the oxide semiconductor layer130or diffuses into the oxide semiconductor layer130from the outside changes the regions231and232to n-type regions with low resistance. Note that functions of a “source” and a “drain” of a transistor are sometimes interchanged with each other when a transistor of opposite polarity is used or when the direction of current flow is changed in a circuit operation, for example Therefore, the terms “source” and “drain” can be interchanged with each other in this specification. In addition, the term “electrode layer” can be replaced with the term “wiring”. The conductive layer170includes two layers, a conductive layer171and a conductive layer172, in the drawing, but also may be a single layer or a stack of three or more layers. The same can apply to other transistors described in this embodiment. Each of the conductive layers140and150is a single layer in the drawing, but also may be a stack of two or more layers. The same can apply to other transistors described in this embodiment. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.25C and25D.FIG.25Cis a top view of a transistor102. A cross section in the direction of dashed-dotted line C1-C2inFIG.25Cis illustrated inFIG.25D. A cross section in the direction of dashed-dotted line C3-C4inFIG.25Cis illustrated inFIG.27B. The direction of dashed-dotted line C1-C2is referred to as a channel length direction, and the direction of dashed-dotted line C3-C4is referred to as a channel width direction. The transistor102has the same structure as the transistor101except that an end portion of the insulating layer160functioning as a gate insulating film is not aligned with an end portion of the conductive layer170functioning as a gate electrode layer. In the transistor102, wide areas of the conductive layers140and150are covered with the insulating layer160and accordingly the resistance between the conductive layer170and the conductive layers140and150is high; therefore, the transistor102has a feature of a low gate leakage current. The transistors101and102each have a top-gate structure including a region where the conductive layer170overlaps with the conductive layers140and150. To reduce parasitic capacitance, the width of the region in the channel length direction is preferably greater than or equal to 3 nm and less than 300 nm. Since an offset region is not formed in the oxide semiconductor layer130in this structure, a transistor with a high on-state current can be easily formed. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.25E and25F.FIG.25Eis a top view of a transistor103. A cross section in the direction of dashed-dotted line D1-D2inFIG.25Eis illustrated inFIG.25F. A cross section in the direction of dashed-dotted line D3-D4inFIG.25Eis illustrated inFIG.27A. The direction of dashed-dotted line D1-D2is referred to as a channel length direction, and the direction of dashed-dotted line D3-D4is referred to as a channel width direction. The transistor103includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; the insulating layer160in contact with the oxide semiconductor layer130; the conductive layer170in contact with the insulating layer160; the insulating layer175covering the oxide semiconductor layer130, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers140and150electrically connected to the oxide semiconductor layer130through openings provided in the insulating layers175and180. The transistor103may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers140and150as necessary. The conductive layer140, the conductive layer150, the insulating layer160, and the conductive layer170can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively. The region231, the region232, and the region233inFIG.25Fcan function as a source region, a drain region, and a channel formation region, respectively. The regions231and232are in contact with the insulating layer175. When an insulating material containing hydrogen is used for the insulating layer175, for example, the resistance of the regions231and232can be reduced. Specifically, interaction between an oxygen vacancy generated in the regions231and232by the steps up to formation of the insulating layer175and hydrogen that diffuses into the regions231and232from the insulating layer175changes the regions231and232to n-type regions with low resistance. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, or the like can be used. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.26A and26B.FIG.26Ais a top view of a transistor104. A cross section in the direction of dashed-dotted line E1-E2inFIG.26Ais illustrated inFIG.26B. A cross section in the direction of dashed-dotted line E3-E4inFIG.26Ais illustrated inFIG.27A. The direction of dashed-dotted line E1-E2is referred to as a channel length direction, and the direction of dashed-dotted line E3-E4is referred to as a channel width direction. The transistor104has the same structure as the transistor103except that the conductive layers140and150are in contact with the oxide semiconductor layer130so as to cover end portions of the oxide semiconductor layer130. InFIG.26B, regions331and334can function as a source region, regions332and335can function as a drain region, and a region333can function as a channel formation region. The resistance of the regions331and332can be reduced in a manner similar to that of the regions231and232in the transistor101. The resistance of the regions334and335can be reduced in a manner similar to that of the regions231and232in the transistor103. In the case where the length of the regions334and335in the channel length direction is less than or equal to 100 nm, preferably less than or equal to 50 nm, a gate electric field prevents a significant decrease in on-state current. Therefore, a reduction in resistance of the regions334and335is not performed in some cases. The transistors103and104each have a self-aligned structure that does not include a region where the conductive layer170overlaps with the conductive layers140and150. A transistor with a self-aligned structure, which has extremely low parasitic capacitance between a gate electrode layer and source and drain electrode layers, is suitable for applications that require high-speed operation. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.26C and26D.FIG.26Cis a top view of a transistor105. A cross section in the direction of dashed-dotted line F1-F2inFIG.26Cis illustrated inFIG.26D. A cross section in the direction of dashed-dotted line F3-F4inFIG.26Cis illustrated inFIG.27A. The direction of dashed-dotted line F1-F2is referred to as a channel length direction, and the direction of dashed-dotted line F3-F4is referred to as a channel width direction. The transistor105includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; conductive layers141and151electrically connected to the oxide semiconductor layer130; the insulating layer160in contact with the oxide semiconductor layer130and the conductive layers141and151; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the oxide semiconductor layer130, the conductive layers141and151, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor105may further include, for example, an insulating layer in contact with the insulating layer180and the conductive layers142and152as necessary. The conductive layers141and151are in contact with the top surface of the oxide semiconductor layer130and are not in contact with side surfaces of the oxide semiconductor layer130. The transistor105has the same structure as the transistor101except that the conductive layers141and151are provided, that the openings are provided in the insulating layers175and180, and that the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through the openings are provided. The conductive layer140(the conductive layers141and142) can function as a source electrode layer, and the conductive layer150(the conductive layers151and152) can function as a drain electrode layer. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.26E and26F.FIG.26Eis a top view of a transistor106. A cross section in the direction of dashed-dotted line G1-G2inFIG.26Eis illustrated inFIG.26F. A cross section in the direction of dashed-dotted line G3-G4inFIG.26Eis illustrated inFIG.27A. The direction of dashed-dotted line G1-G2is referred to as a channel length direction, and the direction of dashed-dotted line G3-G4is referred to as a channel width direction. The transistor106includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; the conductive layers141and151electrically connected to the oxide semiconductor layer130; the insulating layer160in contact with the oxide semiconductor layer130; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the insulating layer120, the oxide semiconductor layer130, the conductive layers141and151, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor106may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers142and152as necessary. The conductive layers141and151are in contact with the top surface of the oxide semiconductor layer130and are not in contact with side surfaces of the oxide semiconductor layer130. The transistor106has the same structure as the transistor103except that the conductive layers141and151are provided. The conductive layer140(the conductive layers141and142) can function as a source electrode layer, and the conductive layer150(the conductive layers151and152) can function as a drain electrode layer. In the structures of the transistors105and106, the conductive layers140and150are not in contact with the insulating layer120. These structures make the insulating layer120less likely to be deprived of oxygen by the conductive layers140and150and facilitate oxygen supply from the insulating layer120to the oxide semiconductor layer130. An impurity for forming an oxygen vacancy to increase conductivity may be added to the regions231and232in the transistor103and the regions334and335in the transistors104and106. As an impurity for forming an oxygen vacancy in an oxide semiconductor layer, for example, one or more of the following can be used: phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon. As a method for adding the impurity, plasma treatment, ion implantation, ion doping, plasma immersion ion implantation, or the like can be used. When the above element is added as an impurity element to the oxide semiconductor layer, a bond between a metal element and oxygen in the oxide semiconductor layer is cut, so that an oxygen vacancy is formed. Interaction between an oxygen vacancy in the oxide semiconductor layer and hydrogen that remains in the oxide semiconductor layer or is added to the oxide semiconductor layer later can increase the conductivity of the oxide semiconductor layer. When hydrogen is added to an oxide semiconductor in which an oxygen vacancy is formed by addition of an impurity element, hydrogen enters an oxygen vacant site and forms a donor level in the vicinity of the conduction band. Consequently, an oxide conductor can be formed. Here, an oxide conductor refers to an oxide semiconductor having become a conductor. Note that the oxide conductor has a light-transmitting property like the oxide semiconductor. The oxide conductor is a degenerated semiconductor and it is suggested that the conduction band edge equals or substantially equals the Fermi level. For that reason, an ohmic contact is made between an oxide conductor layer and conductive layers functioning as a source electrode layer and a drain electrode layer; thus, contact resistance between the oxide conductor layer and the conductive layers functioning as a source electrode layer and a drain electrode layer can be reduced. The transistor in one embodiment of the present invention may include the conductive layer173between the oxide semiconductor layer130and the substrate115as illustrated in cross-sectional views in the channel length direction inFIGS.28A to28Fand cross-sectional views in the channel width direction inFIGS.27C and27D. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be increased or the threshold voltage can be controlled. In the cross-sectional views inFIGS.28A to28F, the width of the conductive layer173may be shorter than that of the oxide semiconductor layer130. Moreover, the width of the conductive layer173may be shorter than that of the conductive layer170. In order to increase the on-state current, for example, the conductive layers170and173are made to have the same potential, and the transistor is driven as a double-gate transistor. Furthermore, in order to control the threshold voltage, a fixed potential that is different from the potential of the conductive layer170is applied to the conductive layer173. To set the conductive layers170and173at the same potential, for example, as illustrated inFIG.27D, the conductive layers170and173may be electrically connected to each other through a contact hole. Although the transistors101to106inFIGS.25A to25FandFIGS.26A to26Fare examples in which the oxide semiconductor layer130is a single layer, the oxide semiconductor layer130may be a stacked layer. The oxide semiconductor layer130in the transistors101to106can be replaced with the oxide semiconductor layer130inFIGS.29B and29CorFIGS.29D and29E. FIG.29Ais a top view of the oxide semiconductor layer130, andFIGS.29B and29Care cross-sectional views of the oxide semiconductor layer130with a two-layer structure.FIGS.29D and29Eare cross-sectional views of the oxide semiconductor layer130with a three-layer structure. Oxide semiconductor layers with different compositions, for example, can be used as an oxide semiconductor layer130a, an oxide semiconductor layer130b, and an oxide semiconductor layer130c. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.30A and30B.FIG.30Ais a top view of a transistor107. A cross section in the direction of dashed-dotted line H1-H2inFIG.30Ais illustrated inFIG.30B. A cross section in the direction of dashed-dotted line H3-H4inFIG.30Ais illustrated inFIG.32A. The direction of dashed-dotted line H1-H2is referred to as a channel length direction, and the direction of dashed-dotted line H3-H4is referred to as a channel width direction. The transistor107includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the conductive layers140and150electrically connected to the stack; the oxide semiconductor layer130cin contact with the stack and the conductive layers140and150; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the conductive layers140and150, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; and the insulating layer180in contact with the insulating layer175. The insulating layer180may function as a planarization film as necessary. The transistor107has the same structure as the transistor101except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232, that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233, and that part of the oxide semiconductor layer (the oxide semiconductor layer130c) exists between the insulating layer160and the conductive layers140and150. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.30C and30D.FIG.30Cis a top view of a transistor108. A cross section in the direction of dashed-dotted line I1-I2inFIG.30Cis illustrated inFIG.30D. A cross section in the direction of dashed-dotted line13-14inFIG.30Cis illustrated inFIG.32B. The direction of dashed-dotted line I1-I2is referred to as a channel length direction, and the direction of dashed-dotted line13-14is referred to as a channel width direction. The transistor108differs from the transistor107in that end portions of the insulating layer160and the oxide semiconductor layer130care not aligned with the end portion of the conductive layer170. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.30E and30F.FIG.30Eis a top view of a transistor109. A cross section in the direction of dashed-dotted line J1-J2inFIG.30Eis illustrated inFIG.30F. A cross section in the direction of dashed-dotted line J3-J4inFIG.30Eis illustrated inFIG.32A. The direction of dashed-dotted line J1-J2is referred to as a channel length direction, and the direction of dashed-dotted line J3-J4is referred to as a channel width direction. The transistor109includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the oxide semiconductor layer130cin contact with the stack; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175covering the stack, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers140and150electrically connected to the stack through openings provided in the insulating layers175and180. The transistor109may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers140and150as necessary. The transistor109has the same structure as the transistor103except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.31A and31B.FIG.31Ais a top view of a transistor110. A cross section in the direction of dashed-dotted line K1-K2inFIG.31Ais illustrated inFIG.31B. A cross section in the direction of dashed-dotted line K3-K4inFIG.31Ais illustrated inFIG.32A. The direction of dashed-dotted line K1-K2is referred to as a channel length direction, and the direction of dashed-dotted line K3-K4is referred to as a channel width direction. The transistor110has the same structure as the transistor104except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions331and332and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region333. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.31C and31D.FIG.31Cis a top view of a transistor111. A cross section in the direction of dashed-dotted line L1-L2inFIG.31Cis illustrated inFIG.31D. A cross section in the direction of dashed-dotted line L3-L4inFIG.31Cis illustrated inFIG.32A. The direction of dashed-dotted line L1-L2is referred to as a channel length direction, and the direction of dashed-dotted line L3-L4is referred to as a channel width direction. The transistor111includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the conductive layers141and151electrically connected to the stack; the oxide semiconductor layer130cin contact with the stack and the conductive layers141and151; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the stack, the conductive layers141and151, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor111may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers142and152as necessary. The transistor111has the same structure as the transistor105except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232, that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233, and that part of the oxide semiconductor layer (the oxide semiconductor layer130c) exists between the insulating layer160and the conductive layers141and151. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.31E and31F.FIG.31Eis a top view of a transistor112. A cross section in the direction of dashed-dotted line M1-M2inFIG.31Eis illustrated inFIG.31F. A cross section in the direction of dashed-dotted line M3-M4inFIG.31Eis illustrated inFIG.32A. The direction of dashed-dotted line M1-M2is referred to as a channel length direction, and the direction of dashed-dotted line M3-M4is referred to as a channel width direction. The transistor112has the same structure as the transistor106except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions331,332,334, and335and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region333. The transistor in one embodiment of the present invention may include the conductive layer173between the oxide semiconductor layer130and the substrate115as illustrated in cross-sectional views in the channel length direction inFIGS.33A to33Fand cross-sectional views in the channel width direction inFIGS.32C and32D. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be further increased or the threshold voltage can be controlled. In the cross-sectional views inFIGS.33A to33F, the width of the conductive layer173may be shorter than that of the oxide semiconductor layer130. Moreover, the width of the conductive layer173may be shorter than that of the conductive layer170. The transistor in one embodiment of the present invention may have a structure illustrated inFIGS.34A and34B.FIG.34Ais a top view andFIG.34Bis a cross-sectional view taken along dashed-dotted line N1-N2and dashed-dotted line N3-N4inFIG.34A. Note that for simplification of the drawing, some components are not illustrated in the top view inFIG.34A. A transistor113illustrated inFIGS.34A and34Bincludes the substrate115, the insulating layer120over the substrate115, the oxide semiconductor layer130(the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130c) over the insulating layer120, the conductive layers140and150that are in contact with the oxide semiconductor layer130and are apart from each other, the insulating layer160in contact with the oxide semiconductor layer130c, and the conductive layer170in contact with the insulating layer160. Note that the oxide semiconductor layer130, the insulating layer160, and the conductive layer170are provided in an opening that is provided in an insulating layer190over the transistor113and reaches the oxide semiconductor layers130aand130band the insulating layer120. The transistor113has a smaller region in which a conductor serving as a source electrode or a drain electrode overlaps with a conductor serving as a gate electrode than the other transistors described above; thus, the parasitic capacitance in the transistor113can be reduced. Therefore, the transistor113is preferable as a component of a circuit for which high-speed operation is needed. As illustrated inFIG.34B, a top surface of the transistor113is preferably planarized by a chemical mechanical polishing (CMP) method or the like, but is not necessarily planarized. As shown in the top views inFIGS.35A and35B(showing only the oxide semiconductor layer130, the conductive layer140, and the conductive layer150), the widths (WSD) of the conductive layer140(source electrode layer) and the conductive layer150(drain electrode layer) in the transistor of one embodiment of the present invention may be either longer than or shorter than the width (WOS) of the oxide semiconductor layer130. When WOSWSD(WSDis less than or equal to WOS) is satisfied, a gate electric field is easily applied to the entire oxide semiconductor layer130, so that electrical characteristics of the transistor can be improved. As illustrated inFIG.35C, the conductive layers140and150may be formed only in a region that overlaps with the oxide semiconductor layer130. In the transistor in one embodiment of the present invention (any of the transistors101to113), the conductive layer170functioning as a gate electrode layer electrically surrounds the oxide semiconductor layer130in the channel width direction with the insulating layer160functioning as a gate insulating film positioned therebetween. This structure increases the on-state current. Such a transistor structure is referred to as a surrounded channel (s-channel) structure. In the transistor including the oxide semiconductor layers130aand130band the transistor including the oxide semiconductor layers130ato130c, selecting appropriate materials for the two or three layers forming the oxide semiconductor layer130allows current to flow in the oxide semiconductor layer130b. Since current flows in the oxide semiconductor layer130b, the current is hardly influenced by interface scattering, leading to a high on-state current. Thus, increasing the thickness of the oxide semiconductor layer130bimproves the on-state current in some cases. With the above structure, the electrical characteristics of the transistor can be improved. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. Embodiment 3 In this embodiment, components of the transistors described in Embodiment 2 are described in detail. As the substrate115, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate with an insulated surface, or the like can be used. Alternatively, a silicon substrate provided with a transistor, a photodiode, or the like can be used, and an insulating layer, a wiring, a conductor functioning as a contact plug, and the like may be provided over the silicon substrate. Note that when p-channel transistors are formed using the silicon substrate, a silicon substrate with n−-type conductivity is preferably used. Alternatively, an SOI substrate including an n−-type or i-type silicon layer may be used. In the case where a p-channel transistor is formed on the silicon substrate, it is preferable to use a silicon substrate in which a plane where the transistor is formed is a (110) plane orientation. Forming a p-channel transistor with the (110) plane can increase mobility. The insulating layer120can have a function of supplying oxygen to the oxide semiconductor layer130as well as a function of preventing diffusion of impurities from a component included in the substrate115. For this reason, the insulating layer120is preferably an insulating film containing oxygen and further preferably, the insulating layer120is an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. The insulating layer120is a film in which the amount of released oxygen when converted into oxygen atoms is preferably greater than or equal to 1.0×1019atoms/cm3in TDS analysis. In the TDS analysis, the film surface temperature is higher than or equal to 100 □C and lower than or equal to 700 □C, or higher than or equal to 100 □C and lower than or equal to 500 □C. In the case where the substrate115is provided with another device, the insulating layer120also has a function of an interlayer insulating film. In that case, the insulating layer120is preferably subjected to planarization treatment such as CMP treatment so as to have a flat surface. For example, the insulating layer120can be formed using an oxide insulating film including aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating film including silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a mixed material of any of these. The insulating layer120may be a stack of any of the above materials. The oxide semiconductor layer130can have a three-layer structure in which the oxide semiconductor layers130ato130care sequentially stacked from the insulating layer120side. Note that in the case where the oxide semiconductor layer130is a single layer, a layer corresponding to the oxide semiconductor layer130bdescribed in this embodiment is used. In the case where the oxide semiconductor layer130has a two-layer structure, a stack in which layers corresponding to the oxide semiconductor layer130aand the oxide semiconductor layer130bare sequentially stacked from the insulating layer120side is used. In such a case, the oxide semiconductor layers130aand130bcan be replaced with each other. For the oxide semiconductor layer130b, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the oxide semiconductor layers130aand130cis used. In such a structure, when an electric field is applied to the conductive layer170, a channel is formed in the oxide semiconductor layer130bwhose conduction band minimum is the lowest in the oxide semiconductor layer130. Therefore, the oxide semiconductor layer130bcan be regarded as having a region serving as a semiconductor, while the oxide semiconductor layer130aand the oxide semiconductor layer130ccan be regarded as having a region serving as an insulator or a semi-insulator. An oxide semiconductor that can be used for each of the oxide semiconductor layers130ato130cpreferably contains at least In or Zn. Both In and Zn are preferably contained. In order to reduce variations in electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer such as Al, Ga, Y, or Sn in addition to In and Zn. The oxide semiconductor layers130ato130cpreferably include crystal parts. In particular, when crystals with c-axis alignment are used, the transistor can have stable electrical characteristics. Moreover, crystals with c-axis alignment are resistant to bending; therefore, using such crystals can improve the reliability of a semiconductor device using a flexible substrate. As the conductive layer140functioning as a source electrode layer and the conductive layer150functioning as a drain electrode layer, for example, a single layer or a stacked layer formed using a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, and Sc and alloys or conductive nitrides of any of these metal materials can be used. It is also possible to use a stack of any of the above materials and Cu or an alloy such as Cu—Mn, which has low resistance. In the transistors105,106,111, and112, for example, it is possible to use W for the conductive layers141and151and use a stack of Ti and Al for the conductive layers142and152. The above materials are capable of extracting oxygen from an oxide semiconductor film Therefore, in a region of the oxide semiconductor film that is in contact with any of the above materials, oxygen is released from the oxide semiconductor layer and an oxygen vacancy is formed. Hydrogen slightly contained in the layer and the oxygen vacancy are bonded to each other, so that the region is markedly changed to an n-type region. Accordingly, the n-type region can serve as a source or a drain of the transistor. In the case where W is used for the conductive layers140and150, the conductive layers140and150may be doped with nitrogen. Doping with nitrogen can appropriately lower the capability of extracting oxygen and prevent the n-type region from spreading to a channel region. It is possible to prevent the n-type region from spreading to a channel region also by using a stack of W and an n-type semiconductor layer as the conductive layers140and150and putting the n-type semiconductor layer in contact with the oxide semiconductor layer. As the n-type semiconductor layer, an In—Ga—Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like to which nitrogen is added can be used. The insulating layer160functioning as a gate insulating film can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer160may be a stack of any of the above materials. The insulating layer160may contain La, N, Zr, or the like as an impurity. An example of a stacked-layer structure of the insulating layer160is described. The insulating layer160includes, for example, oxygen, nitrogen, silicon, or hafnium. Specifically, the insulating layer160preferably includes hafnium oxide and silicon oxide or silicon oxynitride. Hafnium oxide and aluminum oxide have higher dielectric constants than silicon oxide and silicon oxynitride. Therefore, the insulating layer160using hafnium oxide or aluminum oxide can have larger thickness than the insulating layer160using silicon oxide, so that leakage current due to tunnel current can be reduced. That is, a transistor with a low off-state current can be provided. Moreover, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to provide a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to these examples. For the insulating layers120and160in contact with the oxide semiconductor layer130, a film that releases less nitrogen oxide is preferably used. In the case where the oxide semiconductor is in contact with an insulating layer that releases a large amount of nitrogen oxide, the density of states due to nitrogen oxide increases in some cases. For the insulating layers120and160, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film that releases less nitrogen oxide can be used. A silicon oxynitride film that releases less nitrogen oxide is a film that releases ammonia more than nitrogen oxide in TDS; the amount of released ammonia is typically greater than or equal to 1×1018and less than or equal to 5×1019. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of the film becomes higher than or equal to 50 □C and lower than or equal to 650 □C, preferably higher than or equal to 50 □C and lower than or equal to 550 □C. By using the above oxide insulating layer for the insulating layers120and160, a shift in the threshold voltage of the transistor can be reduced, which leads to reduced fluctuations in the electrical characteristics of the transistor. For the conductive layer170functioning as a gate electrode layer, for example, a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, or W can be used. Alternatively, an alloy or a conductive nitride of any of these materials may be used. Alternatively, a stack of a plurality of materials selected from these materials, alloys of these materials, and conductive nitrides of these materials may be used. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. Alternatively, Cu or an alloy such as Cu—Mn, which has low resistance, or a stack of any of the above materials and Cu or an alloy such as Cu—Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer171and tungsten is used for the conductive layer172to form the conductive layer170. As the conductive layer170, an oxide conductive layer of an In—Ga—Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like may be used. As the insulating layer175, a silicon nitride film, an aluminum nitride film, or the like containing hydrogen can be used. In the transistors103,104,106,109,110, and112described in Embodiment 2, when an insulating film containing hydrogen is used as the insulating layer175, part of the oxide semiconductor layer can have n-type conductivity. In addition, a nitride insulating film functions as a blocking film against moisture and the like and can improve the reliability of the transistor. An aluminum oxide film can also be used as the insulating layer175. It is particularly preferable to use an aluminum oxide film as the insulating layer175in the transistors101,102,105,107,108, and111described in Embodiment 2. The aluminum oxide film has a significant effect of blocking both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can suitably function as a protective film that has effects of preventing entry of impurities such as hydrogen and moisture into the oxide semiconductor layer130, preventing release of oxygen from the oxide semiconductor layer, and preventing unnecessary release of oxygen from the insulating layer120. The insulating layer180is preferably formed over the insulating layer175. The insulating layer180can be formed using an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer180may be a stack of any of the above materials. Here, like the insulating layer120, the insulating layer180preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer180can be diffused into the channel formation region in the oxide semiconductor layer130through the insulating layer160, so that oxygen vacancies formed in the channel formation region can be filled with oxygen. In this manner, stable electrical characteristics of the transistor can be achieved. High integration of a semiconductor device requires miniaturization of a transistor. However, that miniaturization of a transistor tends to cause deterioration of electrical characteristics of the transistor. For example, a decrease in channel width causes a reduction in on-state current. In the transistors107to112in one embodiment of the present invention, the oxide semiconductor layer130cis formed to cover the oxide semiconductor layer130bwhere a channel is formed; thus, a channel formation layer is not in contact with the gate insulating film. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating film can be reduced and the on-state current of the transistor can be increased. In the transistor in one embodiment of the present invention, as described above, the gate electrode layer (the conductive layer170) is formed to electrically surround the oxide semiconductor layer130in the channel width direction; accordingly, a gate electric field is applied to the oxide semiconductor layer130in a direction perpendicular to its side surface in addition to a direction perpendicular to its top surface. In other words, a gate electric field is applied to the entire channel formation layer and an effective channel width is increased, leading to a further increase in on-state current. Although the variety of films such as the metal films, the semiconductor films, and the inorganic insulating films that are described in this embodiment typically can be formed by sputtering or plasma-enhanced CVD, such films may be formed by another method such as thermal CVD. Examples of the thermal CVD include metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Since plasma is not used for deposition, thermal CVD has an advantage that no defect due to plasma damage is generated. Deposition by thermal CVD may be performed in such a manner that a source gas and an oxidizer are supplied to the chamber at the same time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate. Deposition by ALD is performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are introduced into the chamber and reacted, and then the sequence of gas introduction is repeated. An inert gas (e.g., argon or nitrogen) may be introduced as a carrier gas with the source gases. For example, two or more kinds of source gases may be sequentially supplied to the chamber. In that case, after reaction of a first source gas, an inert gas is introduced, and then a second source gas is introduced so that the source gases are not mixed. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate and reacted to form a first layer, and then, the second source gas introduced is adsorbed and reacted. As a result, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of gas introduction is controlled and repeated more than once until desired thickness is obtained, so that a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of gas introduction; therefore, ALD makes it possible to accurately adjust thickness and thus is suitable for manufacturing a minute FET. The variety of films such as the metal film, the semiconductor film, and the inorganic insulating film that have been disclosed in the above embodiments can be formed by thermal CVD such as MOCVD or ALD. For example, in the case where an In—Ga—Zn—O film is formed, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. Without limitation to the above combination, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. For example, in the case where a hafnium oxide film is formed by a deposition apparatus using ALD, two kinds of gases, i.e., ozone (O3) as an oxidizer and a source gas that is obtained by vaporizing liquid containing a solvent and a hafnium precursor (hafnium alkoxide and a hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide)hafnium) are used. For example, in the case where an aluminum oxide film is formed by a deposition apparatus using ALD, two kinds of gases, i.e., H2O as an oxidizer and a source gas that is obtained by vaporizing liquid containing a solvent and an aluminum precursor (e.g., trimethylaluminum (TMA, Al(CH3)3)) are used. Examples of another material include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). For example, in the case where a silicon oxide film is formed by a deposition apparatus using ALD, hexachlorodisilane is adsorbed on a surface where a film is to be formed, and radicals of an oxidizing gas (e.g., O2or dinitrogen monoxide) are supplied to react with the adsorbate. For example, in the case where a tungsten film is formed by a deposition apparatus using ALD, a WF6gas and a B2H6gas are sequentially introduced to form an initial tungsten film, and then a WF6gas and an H2gas are sequentially introduced to form a tungsten film. Note that an SiH4gas may be used instead of a B2H6gas. For example, in the case where an oxide semiconductor film, e.g., an In—Ga—Zn—O layer is formed by a deposition apparatus using ALD, an In(CH3)3gas and an O3gas) are sequentially introduced to form an In—O layer, a Ga(CH3)3gas and an O3gas) are sequentially introduced to form a Ga—O layer, and then a Zn(CH3)2gas and an O3gas) are sequentially introduced to form a Zn—O layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by using these gases. Although an H2O gas that is obtained by bubbling with an inert gas such as Ar may be used instead of an O3gas), it is preferable to use an O3gas), which does not contain H. A facing-target-type sputtering apparatus can be used for deposition of an oxide semiconductor layer. Deposition using the facing-target-type sputtering apparatus can also be referred to as vapor deposition SP (VDSP). When an oxide semiconductor layer is deposited using a facing-target-type sputtering apparatus, plasma damage to the oxide semiconductor layer at the time of deposition can be reduced. Thus, oxygen vacancies in the film can be reduced. In addition, the use of the facing-target-type sputtering apparatus enables low-pressure deposition. Accordingly, the concentration of impurities (e.g., hydrogen, a rare gas (e.g., argon), and water) in a deposited oxide semiconductor layer can be lowered. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. Embodiment 4 In this embodiment, the material of an oxide semiconductor that can be used for one embodiment of the present invention will be described. An oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained as an element M. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained as an element M. Here, the case where an oxide semiconductor contains indium, an element M, and zinc will be considered. First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to the present invention will be described with reference toFIGS.36A,36B, and36C. Note that the proportion of oxygen atoms is not shown. The terms of the atomic ratio of indium, the element M, and zinc contained in the oxide semiconductor are denoted by [In], [M], and [Zn], respectively. InFIGS.36A to36C, broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):1, where −1≤α≤1, a line where the atomic ratio [In]:M:[Zn] is (1+α):(1−α):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):3, a line where the atomic ratio [In]:M:[Zn] is (1+α):(1−α):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+α):(1−α):5. Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, where β≥0, a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β. The oxide semiconductor illustrated inFIGS.36A to36Cwith an atomic ratio of [In]:M :[Zn]=0:2:1 or an atomic ratio which is in the neighborhood is likely to have a spinel crystal structure. FIGS.36A and36Bshow examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor of one embodiment of the present invention. FIG.37shows an example of the crystal structure of InMZnO4whose atomic ratio [In]:[M]:[Zn] is 1:1:1. Note thatFIG.37illustrates the crystal structure of InMZnO4observed from a direction parallel to a b-axis. Note that a metal element in a layer that contains M, Zn, and oxygen (hereinafter, referred to as an “(M,Zn) layer”) inFIG.37represents the element M or zinc. In that case, the proportion of the element M is the same as the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random. InMZnO4has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter, referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as illustrated inFIG.37. Indium and the element M can be replaced with each other. Therefore, when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained. An oxide semiconductor whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. In other words, if [Zn] is higher than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide semiconductor is crystallized. Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide semiconductor, the oxide semiconductor might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide semiconductor might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three (M,Zn) layers. For example, in the case where the oxide semiconductor is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition. A plurality of phases (e.g., two phases or three phases) exist in the oxide semiconductor in some cases. For example, with an atomic ratio [In]:M:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:M:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures. In addition, the oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility). This is because in an oxide semiconductor containing indium, the element M, and zinc, the s orbital of heavy metal mainly contributes to carrier transfer, and when the indium content in the oxide semiconductor is increased, overlaps of the s orbitals of indium atoms are increased; therefore, an oxide semiconductor having a high content of indium has higher carrier mobility than an oxide semiconductor having a low content of indium. In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C inFIG.36C), insulation performance becomes better. Accordingly, an oxide semiconductor of one embodiment of the present invention preferably has an atomic ratio represented by a region A inFIG.36A. With the atomic ratio, a layered structure with high carrier mobility and a few grain boundaries is easily obtained. A region B inFIG.36Brepresents an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4.1 and the vicinity thereof. The vicinity includes an atomic ratio of [In]:M:[Zn]=5:3: 4. An oxide semiconductor with an atomic ratio represented by the region B is an excellent oxide semiconductor that has particularly high crystallinity and high carrier mobility. Note that conditions where a layered structure of an oxide semiconductor is formed are not uniquely determined by the atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide semiconductor has a layered structure, and boundaries of the regions A to C are not clear. Next, the case where the oxide semiconductor is used for a transistor will be described. Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability. An oxide semiconductor with low carrier density is preferably used for the transistor. For example, an oxide semiconductor whose carrier density is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, more preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3is used. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources and thus can have a low carrier density. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases. Charge trapped by the trap states in the oxide semiconductor takes a long time to be released and may behave like fixed charge. Thus, the transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases. In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. In order to reduce the concentration of impurities in the oxide semiconductor, the concentration of impurities in a film which is adjacent to the oxide semiconductor is preferably reduced. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given. Here, the influence of impurities in the oxide semiconductor will be described. When silicon or carbon that is one of Group 14 elements is contained in the oxide semiconductor, defect states are formed. Thus, the oxide semiconductor is formed to have a region where the concentration of silicon or carbon (measured by secondary ion mass spectrometry (SIMS)) is controlled to be lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3in the oxide semiconductor or the vicinity of an interface between the oxide semiconductor and a layer in contact therewith. When the oxide semiconductor contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor which contains alkali metal or alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal of the oxide semiconductor. Specifically, the oxide semiconductor is formed to have a region where the concentration of alkali metal or alkaline earth metal measured by SIMS is controlled to be lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3. When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor whose semiconductor includes an oxide semiconductor that contains nitrogen is likely to be normally-on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the oxide semiconductor is formed to have a region where the concentration of nitrogen measured by SIMS is controlled to be lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still more preferably lower than or equal to 5×1017atoms/cm3, specifically. Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes an oxygen vacancy, in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor which contains hydrogen is likely to be normally on. Accordingly, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the oxide semiconductor is formed to have a region where the concentration of hydrogen measured by SIMS is controlled to be lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, still further preferably lower than 1×1018atoms/cm3. When an oxide semiconductor with sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics. A transistor in which the above highly purified oxide semiconductor is used for a channel formation region exhibits an extremely low off-state current. When voltage between a source and a drain is set at about 0.1 V, 5 V, or 10 V, for example, the off-state current per channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer. Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A band diagram of insulators that are in contact with a stacked structure of an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3and a band diagram of insulators that are in contact with a stacked structure of the oxide semiconductor S2and the oxide semiconductor S3are described with reference toFIG.38. Note that the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3correspond to the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130c, respectively. FIG.38Ais an example of a band diagram of a stacked structure of an insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and an insulator12in a film thickness direction.FIG.38Bis an example of a band diagram of a stacked structure of the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator12in a film thickness direction. Note that for easy understanding, the band diagrams show the energy level of the conduction band minimum (Ec) of each of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator12. The energy level of the conduction band minimum of each of the oxide semiconductors Si and S3is closer to the vacuum level than that of the oxide semiconductor S2. Typically, a difference in energy level between the conduction band minimum of the oxide semiconductor S2and the conduction band minimum of each of the oxide semiconductors S1and S3is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. That is, the electron affinity of the oxide semiconductor S2is higher than the electron affinity of each of the oxide semiconductors Si and S3, and the difference between the electron affinity of each of the oxide semiconductors Si and S3and the electron affinity of the oxide semiconductor S2is greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV, preferably. As illustrated inFIGS.38A and38B, the conduction band minimum of each of the oxide semiconductors Si to S3is gradually varied. In other words, the energy level of the conduction band minimum is continuously varied or continuously connected. In order to obtain such a band diagram, the density of defect states in a mixed layer formed at an interface between the oxide semiconductors Si and S2or an interface between the oxide semiconductors S2and S3is preferably made low. Specifically, when the oxide semiconductors Si and S2or the oxide semiconductors S2and S3contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide semiconductor S2is an In—Ga—Zn oxide semiconductor, it is preferable to use an In—Ga—Zn oxide semiconductor, a Ga—Zn oxide semiconductor, gallium oxide, or the like as each of the oxide semiconductors Si and S3. At this time, the oxide semiconductor S2serves as a main carrier path. Since the density of defect states at the interface between the oxide semiconductors S1and S2and the interface between the oxide semiconductors S2and S3can be made low, the influence of interface scattering on carrier conduction is small, and a high on-state current can be obtained. When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor is shifted in a positive direction. The oxide semiconductors Si and S3can make the trap state apart from the oxide semiconductor S2. This structure can prevent the positive shift of the threshold voltage of the transistor. A material whose conductivity is sufficiently lower than that of the oxide semiconductor S2is used for the oxide semiconductors Si and S3. In that case, the oxide semiconductor S2, the interface between the oxide semiconductors Si and S2, and the interface between the oxide semiconductors S2and S3mainly function as a channel region. For example, an oxide semiconductor with high insulation performance and the atomic ratio represented by the region C inFIG.36Ccan be used as the oxide semiconductors Si and S3. In the case where an oxide semiconductor with the atomic ratio represented by the region A is used as the oxide semiconductor S2, it is particularly preferable to use an oxide semiconductor with an atomic ratio where [M]/[In] is greater than or equal to 1, preferably greater than or equal to 2 as each of the oxide semiconductors S1and S3. In addition, it is suitable to use an oxide semiconductor with sufficiently high insulation performance and an atomic ratio where [M]/([Zn]+[In]) is greater than or equal to 1 as the oxide semiconductor S3. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 5 The structure of an oxide semiconductor that can be used for one embodiment of the present invention will be described below. In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80□ and less than or equal to 100□, and accordingly also includes the case where the angle formed between two straight lines is greater than or equal to 85° and less than or equal to 95°. In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. <Structure of Oxide Semiconductor> The structure of an oxide semiconductor will be described below. An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS. An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not to have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example. In other words, a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties. <CAAC-OS> First, a CAAC-OS will be described. A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets). Analysis of a CAAC-OS by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS including an InGaZnO4crystal that is classified into the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as illustrated inFIG.39A. This peak is derived from the (009) plane of the InGaZnO4crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film. Note that a peak sometimes appears at a 2θ of around 36° in addition to the peak at a 2θ of around 31°. The peak at a 2θ of around 36° is derived from a crystal structure classified into the space group Fd-3m. Therefore, it is preferred that the CAAC-OS do not show the peak at a 2θ of around 36°. On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO4crystal. When analysis (ϕ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector to the sample surface as an axis (ϕ axis), as illustrated inFIG.39B, a peak is not clearly observed. In contrast, in the case where single crystal InGaZnO4is subjected to ϕ scan with 2θ fixed at around 56°, as illustrated inFIG.39C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4crystal in a direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) illustrated inFIG.39Dcan be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,FIG.39Eshows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As illustrated inFIG.39E, a ring-like diffraction pattern is observed. Thus, the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular orientation. The first ring inFIG.39Eis considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO4crystal. The second ring inFIG.39Eis considered to be derived from the (110) plane and the like. In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a crystal grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. FIG.40Ashows a high-resolution TEM image of a cross section of the CAAC-OS that is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. FIG.40Ashows pellets in which metal atoms are arranged in a layered manner.FIG.40Aproves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS. FIGS.40B and40Cshow Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.FIGS.40D and40Eare images obtained through image processing ofFIGS.40B and40C. The method of image processing is as follows. The image inFIG.40Bis subjected to fast Fourier transform (FFT), so that an FFT image is obtained. Then, mask processing is performed such that a range of from 2.8 nm−1to 5.0 nm−1from the origin in the obtained FFT image remains. After the mask processing, the FFT image is processed by inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is called an FFT filtering image. The FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted, and shows a lattice arrangement. InFIG.40D, a portion where a lattice arrangement is broken is shown by a dashed lines. A region surrounded by a dashed line is one pellet. The portion denoted with the dashed line is a junction of pellets. The dashed line draws a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases. InFIG.40E, a dotted line denotes a boundary between a region with a regular lattice arrangement and another region with a regular lattice arrangement. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of the atomic arrangement in an a-b plane direction, an interatomic bond distance changed by substitution of a metal element, and the like. As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal. The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. <nc-OS> Next, an nc-OS will be described. Analysis of an nc-OS by XRD will be described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation. For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of a thinned nc-OS including an InGaZnO4crystal in a direction parallel to the formation surface, a ring-shaped diffraction pattern (nanobeam electron diffraction pattern) illustrated inFIG.41Ais observed.FIG.41Bshows a diffraction pattern obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. As illustrated inFIG.41B, a plurality of spots are observed in a ring-like region. In other words, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm. Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as illustrated inFIG.41Cwhen an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm. This means that an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions. FIG.41Dshows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed from the direction substantially parallel to the formation surface. In a high-resolution TEM image, an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines inFIG.41D, and a region in which a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or specifically, greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary cannot clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. As described above, in the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC). The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. <A-Like OS> An a-like OS is an oxide semiconductor having a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor. FIGS.42A and42Bare high-resolution cross-sectional TEM images of an a-like OS.FIG.42Ais the high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation.FIG.42Bis the high-resolution cross-sectional TEM image of a-like OS after electron (e) irradiation at 4.3×108e−/nm2.FIGS.42A and42Bshow that stripe-like bright regions extending vertically are observed in the a-like OS from the start of electron irradiation. It can also be found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region. The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below. An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide. First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. It is known that a unit cell of an InGaZnO4crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The spacing between these adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to 0.29 nm from crystal structure analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4crystal. FIG.43shows a change in the average size of crystal parts (at 22 to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.FIG.42indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As illustrated inFIG.42, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e) dose of 4.2×108e−/nm2. In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108e−/nm2. As illustrated inFIG.42, the crystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For the electron beam irradiation and TEM observation, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of electron beam irradiation were as follows: the accelerating voltage was 300 kV; the current density was 6.7×105e−/(nm2·s); and the diameter of the irradiation region was 230 nm. In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation in some cases. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. It is difficult to deposit an oxide semiconductor whose density is lower than 78% of the density of the single crystal oxide semiconductor. For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3and lower than 6.3 g/cm3. Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to estimate the density. As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example. <Carrier Density of Oxide Semiconductor> Next, the carrier density of an oxide semiconductor will be described below. Examples of a factor affecting the carrier density of an oxide semiconductor include oxygen vacancy (VO) and impurities in the oxide semiconductor. As the amount of oxygen vacancy in the oxide semiconductor increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancy (this state is also referred to as VOH). The density of defect states also increases with an increase in the amount of impurity in the oxide semiconductor. Hence, the carrier density of an oxide semiconductor can be controlled by controlling the density of defect states in the oxide semiconductor. Here, a transistor using the oxide semiconductor in a channel region will be considered. The carrier density of the oxide semiconductor is preferably reduced in order to inhibit the negative shift of the threshold voltage of the transistor or reduce the off-state current of the transistor. In order to reduce the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. The carrier density of a highly purified intrinsic oxide semiconductor is lower than 8×1015cm−3, preferably lower than 1×1011cm−3, and further preferably lower than 1×1010cm−3and is higher than or equal to 1×10−9cm−3. In contrast, the carrier density of the oxide semiconductor is preferably increased in order to improve the on-state current of the transistor or improve the field-effect mobility of the transistor. In order to increase the carrier density of the oxide semiconductor, the impurity concentration or the density of defect states in the oxide semiconductor is slightly increased. Alternatively, the bandgap of the oxide semiconductor is preferably narrowed. For example, an oxide semiconductor that has a slightly high impurity concentration or a slightly high density of defect states in the range where a favorable on/off ratio is obtained in the Id-Vgcharacteristics of the transistor can be regarded as substantially intrinsic. Furthermore, an oxide semiconductor that has a high electron affinity and thus has a narrow bandgap so as to increase the density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that a transistor using an oxide semiconductor with higher electron affinity has lower threshold voltage. The oxide semiconductor with an increased carrier density has somewhat n-type conductivity; thus, it can be referred to as a “slightly-n” oxide semiconductor. The carrier density of a substantially intrinsic oxide semiconductor is preferably higher than or equal to 1×105cm−3and lower than 1×1018cm−3, further preferably higher than or equal to 1×107cm−3and lower than or equal to 1×1017cm−3, still further preferably higher than or equal to 1×109cm−3and lower than or equal to 5×1016cm−3, yet further preferably higher than or equal to 1×1010cm−3and lower than or equal to 1×1016cm−3, and yet still preferably higher than or equal to 1×1011cm−3and lower than or equal to 1×1015cm−3. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 6 In this embodiment, examples of a package and a camera module each including an image sensor chip are described. For the image sensor chip, the structure of an imaging device of one embodiment of the present invention can be used. FIG.44Ais an external perspective view showing the top surface side of a package including an image sensor chip. The package includes a package substrate810to which an image sensor chip850is fixed, a cover glass820, an adhesive830for bonding the package substrate810and the cover glass820to each other, and the like. FIG.44Bis an external perspective view showing the bottom surface side of the package. On the bottom surface of the package, a ball grid array (BGA) including solder balls as bumps840is formed. Although the BGA is employed here, a land grid array (LGA), a pin grid array (PGA), or the like may be alternatively employed. FIG.44Cis a perspective view of the package, in which the cover glass820and the adhesive830are partly illustrated.FIG.44Dis a cross-sectional view of the package. Electrode pads860are formed over the package substrate810, and electrically connected to the bumps840through through-holes880and lands885. The electrode pads860are electrically connected to electrodes of the image sensor chip850through wires870. FIG.45Ais an external perspective view showing the top surface side of a camera module in which an image sensor chip is mounted on a package with a built-in lens. The camera module includes a package substrate811to which an image sensor chip851is fixed, a lens cover821, a lens835, and the like. Furthermore, an IC chip890having functions of a driver circuit, a signal conversion circuit, and the like of an imaging device is provided between the package substrate811and the image sensor chip851. Thus, a system in package (SiP) is formed. FIG.45Bis an external perspective view showing the bottom surface side of the camera module. On the bottom surface and four side surfaces of the package substrate811, mounting lands841are provided; this structure can be called a quad flat no-lead package (QFN). Although QFN is employed here, a quad flat package (QFP), the above BGA, or the like may be alternatively employed. FIG.45Cis a perspective view of the module, in which the lens cover821and the lens835are partly illustrated.FIG.45Dis a cross-sectional view of the camera module. The lands841are partly used as electrode pads861. The electrode pads861are electrically connected to electrodes of the image sensor chip851and the IC chip890through wires871. The image sensor chip can be easily mounted on the package having the above structure, and can be incorporated into a variety of semiconductor devices and electronic devices. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. Embodiment 7 Examples of an electronic device that can use the imaging device according to one embodiment of the present invention, a display device, and a semiconductor device including both of them include display devices, personal computers, image memory devices or image reproducing devices provided with storage media, mobile phones, game machines (including portable game machines), portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio players and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.FIGS.46A to46Fillustrate specific examples of these electronic devices. FIG.46Aillustrates a monitoring camera, which includes a housing951, a lens952, a support portion953, and the like. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the monitoring camera. Note that a “monitoring camera” is a common name and does not limit the uses. For example, a device that has a function of a monitoring camera can also be called a camera or a video camera. FIG.46Billustrates a video camera, which includes a first housing971, a second housing972, a display portion973, operation keys974, a lens975, a joint976, and the like. The operation keys974and the lens975are provided for the first housing971, and the display portion973is provided for the second housing972. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the video camera. FIG.46Cillustrates a digital camera, which includes a housing961, a shutter button962, a microphone963, a light-emitting portion967, a lens965, and the like. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the digital camera. FIG.46Dillustrates a wrist-watch-type information terminal, which includes a housing931, a display portion932, a wristband933, operation buttons935, a winder936, a camera939, and the like. The display portion932may be a touch panel. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the information terminal. FIG.46Eillustrates a portable game machine, which includes housings901and902, display portions903and904, a microphone905, speakers906, an operation key907, a stylus908, a camera909, and the like. Although the portable game machine inFIG.46Ehas the two display portions903and904, the number of display portions included in a portable game machine is not limited to this. The imaging device of one embodiment of the present invention can be included as one component for obtaining an image in the portable game machine. FIG.46Fillustrates a portable data terminal, which includes a housing911, a display portion912, a camera919, and the like. A touch panel function of the display portion912enables input and output of information. The imaging device of one embodiment of the present invention can be included as one component for obtaining an image in the portable data terminal. This embodiment can be combined with any of the other embodiments in this specification as appropriate. This application is based on Japanese Patent Application serial No. 2015-256138 filed with Japan Patent Office on Dec. 28, 2015 and Japanese Patent Application serial No. 2016-171454 filed with Japan Patent Office on Sep. 2, 2016, the entire contents of which are hereby incorporated by reference. | 180,476 |
11942498 | DETAILED DESCRIPTION Embodiments of the present invention relate to imaging systems that include single-photon avalanche diodes (SPADs). Some imaging systems include image sensors that sense light by converting impinging photons into electrons or holes that are integrated (collected) in pixel photodiodes within the sensor array. After completion of an integration cycle, collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In complementary metal-oxide semiconductor (CMOS) image sensors, the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage can also be later converted on-chip to a digital equivalent and processed in various ways in the digital domain. In single-photon avalanche diode (SPAD) devices (such as the ones described in connection withFIGS.1-4), on the other hand, the photon detection principle is different. The light sensing diode is biased slightly above its breakdown point and when an incident photon generates an electron or hole, this carrier initiates an avalanche breakdown with additional carriers being generated. The avalanche multiplication may produce a current signal that can be easily detected by readout circuitry associated with the SPAD. The avalanche process needs to be stopped (quenched) by lowering the diode bias below its breakdown point. Each SPAD may therefore include a passive and/or active quenching circuit for quenching the avalanche. This concept can be used in two ways. First, the arriving photons may simply be counted (e.g., in low light level applications). Second, the SPAD pixels may be used to measure photon time-of-flight (ToF) from a synchronized light source to a scene object point and back to the sensor, which can be used to obtain a 3-dimensional image of the scene. FIG.1is a circuit diagram of an illustrative SPAD device202. As shown inFIG.1, SPAD device202includes a SPAD204that is coupled in series with quenching circuitry206between a first supply voltage terminal208(e.g., a ground power supply voltage terminal) and a second supply voltage terminal210(e.g., a positive power supply voltage terminal). During operation of SPAD device202, supply voltage terminals208and210may be used to bias SPAD204to a voltage that is higher than the breakdown voltage. Breakdown voltage is the largest reverse voltage that can be applied without causing an exponential increase in the leakage current in the diode. When SPAD204is biased above the breakdown voltage in this manner, absorption of a single-photon can trigger a short-duration but relatively large avalanche current through impact ionization. Quenching circuitry206(sometimes referred to as quenching element206) may be used to lower the bias voltage of SPAD204below the level of the breakdown voltage. Lowering the bias voltage of SPAD204below the breakdown voltage stops the avalanche process and corresponding avalanche current. There are numerous ways to form quenching circuitry206. Quenching circuitry206may be passive quenching circuitry or active quenching circuitry. Passive quenching circuitry may, without external control or monitoring, automatically quench the avalanche current once initiated. For example, FIG.1shows an example where a resistor is used to form quenching circuitry206. This is an example of passive quenching circuitry. After the avalanche is initiated, the resulting current rapidly discharges the capacity of the device, lowering the voltage at the SPAD to near to the breakdown voltage. The resistance associated with the resistor in quenching circuitry206may result in the final current being lower than required to sustain itself. The SPAD may then be reset to above the breakdown voltage to enable detection of another photon. This example of passive quenching circuitry is merely illustrative. Active quenching circuitry may also be used in SPAD device202. Active quenching circuitry may reduce the time it takes for SPAD device202to be reset. This may allow SPAD device202to detect incident light at a faster rate than when passive quenching circuitry is used, improving the dynamic range of the SPAD device. Active quenching circuitry may modulate the SPAD quench resistance. For example, before a photon is detected, quench resistance is set high and then once a photon is detected and the avalanche is quenched, quench resistance is minimized to reduce recovery time. SPAD device202may also include readout circuitry212. There are numerous ways to form readout circuitry212to obtain information from SPAD device202. Readout circuitry212may include a pulse counting circuit that counts arriving photons. Alternatively or in addition, readout circuitry212may include time-of-flight circuitry that is used to measure photon time-of-flight (ToF). The photon time-of-flight information may be used to perform depth sensing. In one example, photons may be counted by an analog counter to form the light intensity signal as a corresponding pixel voltage. The ToF signal may be obtained by also converting the time of photon flight to a voltage. The example of an analog pulse counting circuit being included in readout circuitry212is merely illustrative. If desired, readout circuitry212may include digital pulse counting circuits. Readout circuitry212may also include amplification circuitry if desired. The example inFIG.1of readout circuitry212being coupled to a node between diode204and quenching circuitry206is merely illustrative. Readout circuitry212may be coupled to any desired portion of the SPAD device. In some cases, quenching circuitry206may be considered integral with readout circuitry212. Because SPAD devices can detect a single incident photon, the SPAD devices are effective at imaging scenes with low light levels. Each SPAD may detect how many photons are received within a given period of time (e.g., using readout circuitry that includes a counting circuit). However, as discussed above, each time a photon is received and an avalanche current initiated, the SPAD device must be quenched and reset before being ready to detect another photon. As incident light levels increase, the reset time becomes limiting to the dynamic range of the SPAD device (e.g., once incident light levels exceed a given level, the SPAD device is triggered immediately upon being reset). Multiple SPAD devices may be grouped together to increase dynamic range.FIG.2is a circuit diagram of an illustrative group220of SPAD devices202. The group of SPAD devices may be referred to as a silicon photomultiplier (SiPM). As shown inFIG.2, silicon photomultiplier220may include multiple SPAD devices that are coupled in parallel between first supply voltage terminal208and second supply voltage terminal210.FIG.2shows N SPAD devices202coupled in parallel (e.g., SPAD device202-1, SPAD device202-2, SPAD device202-3, SPAD device202-4, . . . , SPAD device202-N). More than two SPAD devices, more than ten SPAD devices, more than one hundred SPAD devices, more than one thousand SPAD devices, etc. may be included in a given silicon photomultiplier. Herein, each SPAD device may be referred to as a SPAD pixel202. Although not shown explicitly inFIG.2, readout circuitry for the silicon photomultiplier may measure the combined output current from all of SPAD pixels in the silicon photomultiplier. In this way, the dynamic range of an imaging system including the SPAD pixels may be increased. Each SPAD pixel is not guaranteed to have an avalanche current triggered when an incident photon is received. The SPAD pixels may have an associated probability of an avalanche current being triggered when an incident photon is received. There is a first probability of an electron being created when a photon reaches the diode and then a second probability of the electron triggering an avalanche current. The total probability of a photon triggering an avalanche current may be referred to as the SPAD's photon-detection efficiency (PDE). Grouping multiple SPAD pixels together in the silicon photomultiplier therefore allows for a more accurate measurement of the incoming incident light. For example, if a single SPAD pixel has a PDE of 50% and receives one photon during a time period, there is a 50% chance the photon will not be detected. With the silicon photomultiplier220ofFIG.2, chances are that two of the four SPAD pixels will detect the photon, thus improving the provided image data for the time period. The example of a plurality of SPAD pixels having a common output in a silicon photomultiplier is merely illustrative. In the case of an imaging system including a silicon photomultiplier having a common output for all of the SPAD pixels, the imaging system may not have any resolution in imaging a scene (e.g., the silicon photomultiplier can just detect photon flux at a single point). It may be desirable to use SPAD pixels to obtain image data across an array to allow a higher resolution reproduction of the imaged scene. In cases such as these, SPAD pixels in a single imaging system may have per-pixel readout capabilities. Alternatively, an array of silicon photomultipliers (each including more than one SPAD pixel) may be included in the imaging system. The outputs from each pixel or from each silicon photomultiplier may be used to generate image data for an imaged scene. The array may be capable of independent detection (whether using a single SPAD pixel or a plurality of SPAD pixels in a silicon photomultiplier) in a line array (e.g., an array having a single row and multiple columns or a single column and multiple rows) or an array having more than ten, more than one hundred, or more than one thousand rows and/or columns. While there are a number of possible use cases for SPAD pixels as discussed above, the underlying technology used to detect incident light is the same. All of the aforementioned examples of devices that use SPAD pixels may collectively be referred to as SPAD-based semiconductor devices. A silicon photomultiplier with a plurality of SPAD pixels having a common output may be referred to as a SPAD-based semiconductor device. An array of SPAD pixels with per-pixel readout capabilities may be referred to as a SPAD-based semiconductor device. An array of silicon photomultipliers with per-silicon-photomultiplier readout capabilities may be referred to as a SPAD-based semiconductor device. An imaging system10with a SPAD-based semiconductor device is shown inFIG.3. Imaging system10may be an electronic device such as a digital camera, a computer, a cellular telephone, a medical device, or other electronic device. Imaging system10may be an imaging system on a vehicle (sometimes referred to as vehicular imaging system). Imaging system may be used for LIDAR applications. Imaging system14may include one or more SPAD-based semiconductor devices14(sometimes referred to as semiconductor devices14, devices14, SPAD-based image sensors14, or image sensors14). One or more lenses28may optionally cover each semiconductor device14. During operation, lenses28(sometimes referred to as optics28) may focus light onto SPAD-based semiconductor device14. SPAD-based semiconductor device14may include SPAD pixels that convert the light into digital data. The SPAD-based semiconductor device may have any number of SPAD pixels (e.g., hundreds, thousands, millions, or more). The SPAD-based semiconductor device14may optionally include additional circuitry such as bias circuitry (e.g., source follower load circuits), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital (ADC) converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc. Image data from SPAD-based semiconductor device14may be provided to image processing circuitry16. Image processing circuitry16may be used to perform image processing functions such as automatic focusing functions, depth sensing, data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. For example, during automatic focusing operations, image processing circuitry16may process data gathered by the SPAD pixels to determine the magnitude and direction of lens movement (e.g., movement of lens28) needed to bring an object of interest into focus. Image processing circuitry16may process data gathered by the SPAD pixels to determine a depth map of the scene. Imaging system10may provide a user with numerous high-level functions. In a computer or advanced cellular telephone, for example, a user may be provided with the ability to run user applications. To implement these functions, the imaging system may include input-output devices22such as keypads, buttons, input-output ports, joysticks, and displays. Additional storage and processing circuitry such as volatile and nonvolatile memory (e.g., random-access memory, flash memory, hard drives, solid state drives, etc.), microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, and/or other processing circuits may also be included in the imaging system. Input-output devices22may include output devices that work in combination with the SPAD-based semiconductor device. For example, a light-emitting component may be included in the imaging system to emit light (e.g., infrared light or light of any other desired type). Semiconductor device14may measure the reflection of the light off of an object to measure distance to the object in a LIDAR (light detection and ranging) scheme. FIG.4shows one example for a semiconductor device14that includes an array120of SPAD pixels202(sometimes referred to herein as image pixels or pixels) arranged in rows and columns. Array120may contain, for example, hundreds or thousands of rows and columns of SPAD pixels202. Each SPAD pixel may be coupled to an analog pulse counter that generates a corresponding pixel voltage based on received photons. Each SPAD pixel may additionally or instead be coupled to a time-of-flight to voltage converter circuit. In both types of readout circuits, voltages may be stored on pixel capacitors and may later be scanned in a row-by-row fashion. Control circuitry124may be coupled to row control circuitry126and image readout circuitry128(sometimes referred to as column control circuitry, readout circuitry, processing circuitry, or column decoder circuitry). Row control circuitry126may receive row addresses from control circuitry124and supply corresponding row control signals to SPAD pixels202over row control paths130. One or more conductive lines such as column lines132may be coupled to each column of pixels202in array120. Column lines132may be used for reading out image signals from pixels202and for supplying bias signals (e.g., bias currents or bias voltages) to pixels202. If desired, during pixel readout operations, a pixel row in array120may be selected using row control circuitry126and image signals generated by image pixels202in that pixel row can be read out along column lines132. Image readout circuitry128may receive image signals (e.g., analog or digital signals from the SPAD pixels) over column lines132. Image readout circuitry128may include sample-and-hold circuitry for sampling and temporarily storing image signals read out from array120, amplifier circuitry, analog-to-digital conversion (ADC) circuitry, bias circuitry, column memory, latch circuitry for selectively enabling or disabling the column circuitry, or other circuitry that is coupled to one or more columns of pixels in array120for operating pixels202and for reading out signals from pixels122. ADC circuitry in readout circuitry128may convert analog pixel values received from array120into corresponding digital pixel values (sometimes referred to as digital image data or digital pixel data). Alternatively, ADC circuitry may be incorporated into each SPAD pixel202. Image readout circuitry128may supply digital pixel data to control and processing circuitry124and/or image processing and data formatting circuitry16(FIG.1) over path125for pixels in one or more pixel columns. The example of image sensor14having readout circuitry to read out signals from the SPAD pixels in a row-by-row manner is merely illustrative. In other embodiments, the readout circuitry in the image sensor may simply include digital pulse counting circuits coupled to each SPAD pixel. Any other desired readout circuitry arrangement may be used. If desired, array120may be part of a stacked-die arrangement in which pixels202of array120are split between two or more stacked substrates. Alternatively, pixels202may be formed in a first substrate and some or all of the corresponding control and readout circuitry may be formed in a second substrate. Each of the pixels202in the array120may be split between the two dies at any desired node within pixel. It should be understood that instead of having an array of SPAD pixels as inFIG.4, SPAD-based semiconductor device14may instead have an array of silicon photomultipliers (each of which includes multiple SPAD pixels with a common output). As shown inFIG.5, each SPAD pixel202in a group220of SPAD devices (seeFIG.2) may be covered by a microlens502(alternatively, each SPAD pixel202in the array of SPAD pixels shown inFIG.4may be covered by a microlens502). In particular, each microlens502may focus incident light on an associated one of SPAD pixels202. In general, microlenses502may be any desired shape to focus the light as needed. However, because of the large photosensitive regions in SiPM devices, traditional spherical lenses, such as microlenses502ofFIG.5, may be too thin to focus light properly on the photosensitive regions when formed using conventional manufacturing methods and equipment. In particular, the SiPM devices may have SPAD pixels with pitches that are approximately between 20 microns and 35 microns wide. To focus light incident on image sensor onto the array of SPAD pixels, spherical microlenses with thicknesses of approximately 20 microns may be required. This is thicker than traditional microlenses, which may have thicknesses of approximately 5 microns, and standard equipment may therefore not be capable of forming microlenses for SiPM devices. As shown inFIG.6, toroidal microlenses602may overlie SPAD pixels202. In particular, toroidal lenses may focus incident light more effectively than spherical microlenses, resulting in more efficient light detection by the underlying SPAD pixels202. This is because toroidal lenses may have smaller radii of curvature than spherical microlenses and therefore may focus light onto a smaller area. Toroidal lenses may achieve effective light focusing with thicknesses of less than 10 microns, less than 5 microns, greater than 3 microns, or less than 4 microns. However, this is merely illustrative. In general, toroidal lenses with any desired thicknesses may be used, but toroidal lenses generally require smaller thicknesses than spherical microlenses. Standard microlens manufacturing equipment may be equipped to form microlenses of this thickness, allowing the toroidal microlenses to be formed more efficiently. In general, SPAD pixels may have active and inactive areas. The active areas may be sensitive to photons in incident light and therefore may be used to determine whether a photon is incident on the SPAD pixels. Conversely, the inactive areas may not be sensitive to light and instead contain circuitry or other material. In some cases, although toroidal lenses may focus light better than spherical lenses, the toroidal lenses may spread light outside of active areas606. In particular, if toroidal lenses602are circular, but the underlying SPAD pixels202are square, light that passes through toroidal lenses602may be directed outside of active areas606. For example, microlens portions602A and602B may focus some of the light incident on SPAD pixel202-1into inactive area608. This may result in inaccurate determinations as to whether light is incident on SPAD pixel202-1and lower the overall efficiency of the SPAD pixel. Therefore, it may be desired to use toroidal lenses that match the shape of the underlying SPAD pixels. In one embodiment, square toroidal microlenses may be used. The square toroidal lenses may have a square shape that matches the square shape of the underlying SPAD pixels202. The square toroidal lenses may focus more light onto active areas606and therefore be more efficient than circular toroidal lenses (e.g., less light will be focused onto inactive areas608). In general, however, SPAD pixels202may have any desired geometry, and toroidal lenses602may have shapes that match that geometry to increase the amount of light that reaches active regions606. As shown inFIG.7, square toroidal microlenses702may be arranged in an array. For example, each square toroidal microlens702may overlie a respective one of SPAD pixels202(e.g., in SPAD device group220ofFIG.2or in array120ofFIG.4). In particular, square toroidal microlenses702may be formed over SPAD pixels, such as SPAD pixels202. As shown inFIG.7, four square toroidal microlenses may be formed in a grid pattern. The square toroidal microlenses may focus more light onto active areas of the underlying SPAD pixels (e.g., active areas606of SPAD pixels202inFIG.6) and therefore efficiently focus light on the underlying pixels. In general, square toroidal microlenses may have a gap704in the center of the microlenses. This is also illustrated by gap604inFIG.6. Moreover, although square toroidal microlenses702are shown as having no gaps between any adjacent two microlenses, this is merely illustrative. In general, a mask may be applied to form gaps between adjacent microlenses (e.g., there may be a gap between microlens702-1and microlens702-2, a gap between microlens702-1and microlens702-3, and/or a gap between microlens702-1and microlens702-3). In some cases, it may be desired to remove or fill one or more of the gaps in the center of the square toroidal microlenses or between adjacent square toroidal microlenses to ensure that more of the light incident on the image sensor is directed to the underlying SPAD pixels. Illustrative steps for forming toroidal microlenses and filling gaps in the centers of the microlenses, such as gap704in square toroidal microlens702, are shown inFIG.8. As shown inFIG.8, wafer802may be coated with microlens material804. Microlens material804may be formed from acrylic, silicon, any other desired material, or any desired combination of materials. Wafer802may be formed from silicon or any other desired semiconductor material. In general, wafer802may have a first portion810that corresponds with the active area of SPAD pixel808and a second portion812that corresponds with the inactive area of SPAD pixel808. For example, circuitry required in image sensor14may be routed over the second portions of wafer802. Microlens material804may be applied over parts of both first portion810and second portion812, as shown inFIG.8. The microlens material may be applied over the entire wafer802in a single step, or the microlens material may be applied to different portions of wafer802in multiple steps. In general, the amount and location of microlens material applied to wafer802may be adjusted as desired. After microlens material804has been applied to wafer802, a reflow process may be used to shape the microlens material into toroidal microlens814. This reflow process may be applied in a single step or may be applied in multiple steps. Toroidal microlens814may be a square toroidal microlens, such as square microlens702-1ofFIG.7. The curvature of each portion of toroidal microlens814, as well as the other microlenses formed on wafer802, may be controlled through the reflow process. For example, it may be desired to have some microlenses with different radii of curvature than other microlenses, or all of the microlenses may have the same curvature. However, this is merely illustrative. In general, any desired microlenses may be formed on wafer814through the reflow process. In some cases, it may be desired to apply square toroidal microlenses (or other toroidal microlenses) over the underlying SPAD pixels. In this case, the process ofFIG.8may be complete with apparatus820, which includes microlenses814and underlying wafer802. However, in some cases, it may be desired to fill in gaps in the square toroidal microlenses, such as gaps816, and/or it may be desired to fill in gaps between adjacent square toroidal microlenses, such as gaps818. To fill gaps816, additional microlens material822may be applied in each of gaps816. Additional microlens material822may be formed from the same material as microlens material804, or it may be formed from different material. For example, additional microlens material822may have a higher index of refraction than microlens material804, which may direct more incident light to the underlying SPAD pixels for detection. However, this is merely illustrative. In general, additional microlens material822may have a lower index of refraction than microlens material804, or additional microlens material822may have the same index of refraction as microlens material804. After additional microlens material822has been applied to wafer802, an additional reflow process may be used to shape the additional microlens material into microlens824. As shown inFIG.8, microlens824and toroidal microlens814may form a continuously convex shape, which may focus more light toward the active area of an underlying SPAD pixel, such as active area606of SPAD pixel202-1inFIG.6, than a conventional toroidal lens. However, this is merely illustrative. In general, the microlens material, the additional microlens material, and the reflow conditions may be adjusted to form any desired microlens shape. An illustrative method of steps for forming toroidal lenses with filled centers, such as those described above in connection withFIG.8, is shown inFIG.9A. At step902, a wafer, such as a silicon wafer or a wafer formed from other semiconductor material, may be coated with a microlens material. The microlens material may be formed from acrylic, silicon, or any other desired material. At step904, the microlens material may be exposed with a mask that has gaps between neighboring lens locations and may be developed. In particular, the mask may have gaps corresponding to gaps818ofFIG.8. The gaps may be required to avoid merging between neighboring microlenses. For example, if gaps are not provided, microlens material corresponding to a first microlens may merge with microlens material corresponding to a second microlens that is adjacent to the first microlens. By separating neighboring lenses with gaps, however, all of the microlens material may be reflowed to form microlenses simultaneously. At step906, a reflow process may be used to reflow the microlens material to form outer toroidal lenses. The outer toroidal lenses may correspond to toroidal lenses814ofFIG.8, for example. In general, the outer toroidal lenses may have any desired shape and/or curvature. In some cases, the outer toroidal lenses may have square shapes to match the shapes of underlying square SPAD pixels to maximize the amount of incident light that reaches active areas of the SPAD pixels. However, this is merely illustrative. At step908, the wafer may be coated with additional microlens material to fill gaps in the outer toroidal lenses, such as gaps816ofFIG.8. The additional microlens material may be formed from the same material as the microlens material used to form the outer toroidal lenses, or it may be formed from different material. For example, the additional microlens material may have a higher index of refraction than the microlens material used to form the outer toroidal lenses, which may allow more light to be focused on the underlying SPAD pixels for detection. However, this is merely illustrative. In general, the additional microlens material may have a lower index of refraction than the microlens material used to form the outer toroidal lenses, or the additional microlens material may have the same index of refraction as microlens material used to form the outer toroidal lenses. At step910, the additional microlens material may be exposed with a fill-in mask pattern and may be developed. The fill-in mask pattern may be adjusted to ensure that the additional microlens material is aligned with the gaps in the outer toroidal lenses and that a desired shape and amount of material is used for each center lens. At step912, an additional reflow process may be used to reflow the additional microlens material to form fill-in lens portions (e.g., lens portions that correspond to microlens824ofFIG.8). Together, the fill-in lens portions and the outer toroidal lenses may form a continuously convex shape, which may focus light toward the active area of an underlying SPAD pixel, such as active area606of SPAD pixel202-1ofFIG.6. However, this is merely illustrative. In general, the microlens material, the additional microlens material, and the reflow conditions may be adjusted to form any desired microlens shape. In general, the method illustrated inFIG.9Amay require gaps between neighboring toroidal microlenses to avoid merging between the microlenses. These gaps may correspond to gaps818ofFIG.8, for example. These gaps may be necessary because all of the microlenses are formed simultaneously. In some cases, it may be desired to avoid gaps between neighboring microlenses. For example, it may be desired to form the microlenses to direct light between neighboring pixels into a single one of the pixels, which may increase the efficiency of the array of pixels. An illustrative method of steps for forming toroidal lens with filled centers and without gaps between neighboring lenses is shown inFIG.9B. At step920, a wafer, such as a silicon wafer or a wafer formed from other semiconductor material, may be coated with a microlens material. The microlens material may be formed from acrylic, silicon, or any other desired material. At step922, the microlens material may be exposed with a first mask that defines every other toroid shape in the array of lenses, and may be developed. For example, the first mask may define the lens locations that correspond to microlenses702-1and702-4ofFIG.7. However, first mask may alternatively define the lens locations that correspond to microlenses702-2and702-3. In general, the first mask may define lens locations that correspond with every other lens of the finished array of lenses. At step924, a reflow process may be used to reflow the microlens material to form a first set of outer toroidal lenses. The first set of outer toroidal lenses may correspond with outer toroidal lenses702-1and702-4ofFIG.7, for example. In general, the outer toroidal lenses may have any desired shape and/or curvature. In some cases, the outer toroidal lenses may have square shapes to match the shapes of underlying square SPAD pixels to maximize the amount of incident light that reaches active areas of the SPAD pixels. However, this is merely illustrative. At step926, the wafer may be coated with more microlens material. The microlens material may be formed from acrylic, silicon, or any other desired material. Generally, the microlens material may be the same as the microlens material that is used to form the first set of outer toroidal lenses. However, the microlens material may be different, if desired. At step928, the microlens material may be exposed with a second mask that defines a second set of toroid shapes that is complementary to the first set of toroid shapes, and may be developed. For example, if the first mask may define the lens locations that correspond to microlenses702-1and702-4ofFIG.7, the second mask may define the lens locations that correspond to microlenses702-2and702-3. However, second mask may alternatively define the lens locations that correspond to microlenses702-1and702-4. In general, the second mask may define lens locations that are complementary to the first set of outer toroidal lenses. At step930, a reflow process may be used to reflow the microlens material to form a second set of outer toroidal lenses. The second set of outer toroidal lenses may correspond with outer toroidal lenses702-2and702-3ofFIG.7, for example. In general, the outer toroidal lenses may have any desired shape and/or curvature. In some cases, the outer toroidal lenses may have square shapes to match the shapes of underlying square SPAD pixels to maximize the amount of incident light that reaches active areas of the SPAD pixels. However, this is merely illustrative. Because the first set of outer toroidal lenses and the second set of outer toroidal lenses are formed sequentially (e.g., rather than simultaneously as illustrated inFIG.9A), gaps between neighboring toroidal lenses, such as gaps818ofFIG.8may be eliminated, if desired. In other words, neighboring toroidal lenses may be in direct contact with one another. Because reflow operations are conducted for the first set of outer toroidal lenses prior to applying the microlens material for the second set of outer toroidal lenses, there may not be a risk of neighboring lenses merging together when reflowing the second set of lenses, and gaps between neighboring lenses may not be necessary. At step932, the wafer may be coated with additional microlens material to fill gaps in the outer toroidal lenses, such as gaps816inFIG.8. The additional microlens material may be formed from the same material as the microlens material used to form the first and second sets of outer toroidal lenses, or it may be formed from different material. For example, the additional microlens material may have a higher index of refraction than the microlens material used to form the first and second sets outer toroidal lenses, which may allow more light to reach the underlying SPAD pixels for detection. However, this is merely illustrative. In general, the additional microlens material may have a lower index of refraction than the microlens material used to form the first and second sets of outer toroidal lenses, or the additional microlens material may have the same index of refraction as microlens material used to form the first and second outer toroidal lenses. At step934, the additional microlens material may be exposed with a fill-in mask pattern and may be developed. The fill-in mask pattern may be adjusted to ensure that the additional microlens material is aligned with the gaps in the first and second sets of outer toroidal lenses and that a desired shape and amount of material is used for each center lens. At step936, an additional reflow process may be used to reflow the additional microlens material to form fill-in lens portions (e.g., lens portions that correspond to microlens824ofFIG.8). Together, the fill-in lens portions and the outer toroidal lenses of the first and second sets of outer toroidal lenses may form a continuously convex shape, which may focus light toward the active area of an underlying SPAD pixel, such as active area606of SPAD pixel202-1inFIG.6. However, this is merely illustrative. In general, the microlens material, the additional microlens material, and the reflow conditions may be adjusted to form any desired microlens shape. Although the processes illustrated inFIGS.8and9have been described as filling in gaps in toroidal microlenses, this is merely illustrative. In general, the processes described inFIGS.8and9may fill gaps in any desired microlenses. For example, as shown inFIG.10, multiple microlenses may be formed over each SPAD pixel. As shown, spherical microlenses1002may be arranged in a two-by-two array over each SPAD pixel. Spherical microlenses1002may define a center portion that may be filled by the processes described in connection withFIGS.8and9, thereby forming a continuous, convex shaped microlens that may focus the light effectively on the underlying SPAD pixels. In any of the aforementioned embodiments, it should be understood that a silicon photomultiplier (with multiple SPAD pixels having a common output) may be used in place of a single SPAD pixel. Each SPAD pixel in the silicon multiplier may be covered by a microlens, or multiple SPAD pixels within the silicon multiplier may be covered by a single microlens, if desired. Although each of the aforementioned embodiments have been described as applying a microlens over SPAD pixels, the microlenses may be formed over any desired pixel type. For example, the foregoing microlenses may be applied over pixels in conventional CMOS imagers. In various embodiments of the present invention, a semiconductor device may include a plurality of single-photon avalanche diode pixels, a plurality of first microlenses, at least one of which may cover each of the plurality of single-photon avalanche diode pixels, and a plurality of second microlenses, each of which may fill a gap in the plurality of first microlenses. In accordance with an embodiment, each first microlens may be a toroidal microlens that has a central opening, and each second microlens may fill a respective one of the central openings in the first microlenses. The plurality of single-photon avalanche diode pixels may each have a first shape, and each of the first microlenses may have a second shape that matches the first shape. In some embodiments, the first shape and the second shape may both be square. In accordance with an embodiment, each of the first microlenses may be formed from a material having a first index of refraction, and each of the second microlenses may be formed from a material having a second index of refraction that is different from the first index of refraction. The second index of refraction may be higher than the first index of refraction. In accordance with an embodiment, the first microlenses and the second microlenses may together form a plurality of microlenses, each of which may overlap a respective one of the plurality of single-photon avalanche diode pixels. Alternatively or additionally, the first microlenses and the second microlenses may be at least partially formed from the same material. In accordance with an embodiment, the first microlenses may be spherical microlenses, and the spherical microlenses may be formed in a two-by-two array over each single-photon avalanche diode pixel. The second microlenses may fill the gap between the four spherical microlenses over each pixel. In accordance with an embodiment, the first microlenses may be square toroidal microlenses, and adjacent first microlenses may be in direct contact with one another. The second microlenses may fill center gaps in the square toroidal microlenses. In accordance with various embodiments, microlenses may be formed over a plurality of single-photon avalanche diodes by applying first microlens material over a semiconductor wafer, exposing the first microlens material with a first mask, reflowing the first microlens material to form a first set of non-overlapping outer toroidal microlenses, applying second microlens material over the semiconductor wafer, exposing the second microlens material with a second mask, and reflowing the second microlens material to form a second set of complementary outer toroidal microlenses. In accordance with an embodiment, exposing the first microlens material with the first mask and reflowing the first microlens material may form a first set of square toroidal microlenses, and exposing the second microlens material with the second mask and reflowing the second microlens material may form a second set of square toroidal microlenses. The second microlens material may be applied after reflowing the first microlens material, if desired. In accordance with an embodiment, the microlens may be further formed by applying additional microlens material over the semiconductor wafer, exposing the additional microlens material with a fill-in mask, and reflowing the additional microlens material to form fill-in lens portions. The additional microlens material may fill openings in the first and second sets of outer toroidal microlenses. Moreover, the fill-in lens portions and the first and second sets of outer toroidal microlenses may form a plurality of convex microlenses over the plurality of SPAD pixels. In accordance with an embodiment, the first microlens material and the second microlens material may be applied over the entire semiconductor wafer, and the first and second microlens material may be exposed and reflowed after both sets of material have been applied. In accordance with various embodiments, a semiconductor device may include a single-photon avalanche diode pixel, a toroidal microlens over the single-photon avalanche diode pixel having a central opening, and a fill-in microlens that fills the central opening of the toroidal microlens. In accordance with an embodiment, the single-photon avalanche diode pixel may have a square shape and the toroidal microlens may be a square toroidal microlens. The square toroidal microlens may have a first index of refraction and the fill-in microlens may have a second index of refraction that is higher than the first index of refraction. The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination. | 41,722 |
11942499 | DETAILED DESCRIPTION Hereinafter, example embodiments of inventive concepts will be described with reference to the accompanying drawings. FIG.1is a block diagram schematically illustrating an image sensor according to an embodiment of inventive concepts. Referring toFIG.1, an image sensor1may include a pixel array10, a logic circuit20, and the like. The pixel array10may include a plurality of pixels PX arranged in an array shape along a plurality of rows and a plurality of columns. Each of the plurality of pixels PX may include at least one photoelectric conversion element that generates charge in response to light, a pixel circuit that generates a pixel signal corresponding to the charge generated by the photoelectric conversion element, and the like. The photoelectric conversion element may include a photodiode formed of a semiconductor material, an organic photodiode formed of an organic material, and/or the like. For example, the pixel circuit may include a floating diffusion, a transfer transistor, a reset transistor, a driving transistor, and a select transistor. A configuration of the pixels PX may vary according to embodiments. As an example, each of the pixels PX may include an organic photodiode including an organic material or may be implemented as a digital pixel. When the pixels PX are implemented as digital pixels, each of the pixels PX may include an analog-to-digital converter for outputting a digital pixel signal. The logic circuit20may include circuits for controlling the pixel array10. For example, the logic circuit20may include a row driver21, a readout circuit22, a column driver23, a control logic24, and the like. The row driver21may drive the pixel array10in units of row lines. For example, the row driver21may generate a transmission control signal for controlling the transfer transistor of the pixel circuit, a reset control signal for controlling the reset transistor, a select control signal for controlling the select transistor, etc., to input them into the pixel array10in units of row lines. The readout circuit22may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), or the like. The correlated double samplers may be connected to the pixels PX through column lines. The correlated double samplers may read a pixel signal through column lines, from the pixels PX connected to a row line selected by a row line select signal of the row driver21. The analog-to-digital converter may convert the pixel signal detected by the correlated double sampler into a digital pixel signal, and may transmit the digital pixel signal to the column driver23. The column driver23may include a latch circuit or a buffer circuit for temporarily storing the digital pixel signal, an amplifying circuit, and the like, and may process the digital pixel signal received from the readout circuit22. The row driver21, the readout circuit22, and the column driver23may be controlled by the control logic24. The control logic24may include a timing controller for controlling operation timing of the row driver21, the readout circuit22, and the column driver23, and the like. Among the pixels PX, pixels PX disposed at the same position in a horizontal direction may share the same column line. For example, pixels PX disposed at the same position in a vertical direction may be simultaneously selected by the row driver21, and may output pixel signals through column lines. In an embodiment, the readout circuit22may simultaneously acquire the pixel signals through column lines, from the pixels PX selected by the row driver21. The pixel signal may include a reset voltage and a pixel voltage. The pixel voltage may be a voltage in which charges generated in response to light in each of the pixels PX are reflected in the reset voltage. In an embodiment, the pixel array10may include at least one autofocusing pixel. The autofocusing pixel may include two or more photodiodes. The logic circuit20may use a difference in pixel signals acquired from photodiodes included in each of the autofocusing pixels, to implement an autofocusing function of an image sensor1and/or an autofocusing function of a camera device including the image sensor1. To accurately calculate a difference in pixel signals acquired from two or more photodiodes included in an autofocusing pixel, the autofocusing pixel may include a pixel internal isolation layer for separating the photodiodes. Since the photodiodes may be separated from each other by the pixel internal isolation layer, a light-receiving area of each of the photodiodes may be determined according to a position of the pixel internal isolation layer. When the position of the internal isolation layer inside the pixel is not accurately aligned and a difference occurs in the light-receiving area of each of the photodiodes, the autofocusing function of the image sensor1may be deteriorated. In an embodiment of inventive concepts, to reduce and/or minimize an error in the light-receiving area of each of the photodiodes in the autofocusing pixel, the pixel internal isolation layer may be formed from a first surface of a substrate, similar to a pixel isolation layer between the pixels PX. For example, the first surface may be a surface on which a pixel circuit included in each of the pixels PX is formed. For example, the pixel internal isolation layer may be formed in the same process as the pixel isolation layer. Therefore, an alignment error of the pixel internal isolation layer may be reduced and/or minimized, and an error in the light-receiving area of each of the photodiodes may be reduced, to improve an autofocusing function of the image sensor1. In addition, even when an area of each of the pixels PX decreases to increase resolution of the image sensor1, an autofocusing function of the image sensor1may be effectively implemented. FIGS.2to4are views schematically illustrating a pixel array of an image sensor according to embodiments of inventive concepts. First, referring toFIG.2, a pixel array100of an image sensor according to an embodiment of inventive concepts may include a plurality of pixels110and120. For example, the pixel array100may include a general pixel110and an autofocusing pixel120. The general pixel110and the autofocusing pixel120may be provided in plural, respectively, and the number of each of them may be variously changed. For example, the number of general pixels110may be greater than the number of autofocusing pixels120. In addition, a position of the autofocusing pixel120is not limited to those illustrated inFIG.2, and may be variously changed. The autofocusing pixel120may include a first photodiode and a second photodiode. In the autofocusing pixel120, the first photodiode and the second photodiode may be arranged in one direction (the horizontal direction), and the first photodiode and the second photodiode may share one (1) microlens. According to embodiments, in a portion of the autofocusing pixels120, the first photodiode and the second photodiode may be arranged in a direction, different from the one direction. Referring toFIG.3, a pixel array100A may include a plurality of pixels110A. Each of the plurality of pixels110A may include a first photodiode and a second photodiode. In the embodiment illustrated inFIG.3, each of the pixels110A included in the pixel array100A may be an autofocusing pixel. Similar to as described above with reference toFIG.2, in at least a portion of the pixels110A, the first photodiode and the second photodiode may be arranged in different directions, for example, in the vertical direction. According to embodiments, only a portion of the pixels110A may be used for an autofocusing function. Next, referring toFIG.4, a pixel array100B may include a plurality of pixel groups110B. Each of the plurality of pixel groups110B may include unit pixels PX. The unit pixels PX included in each of the pixel groups110B may include color filters having the same color. In the embodiment illustrated inFIG.4, each of the unit pixels PX may include a first photodiode and a second photodiode. According to embodiments, only a portion of the unit pixels PX may include the first photodiode and the second photodiode, or arrangement directions of the first photodiode and the second photodiode in at least a portion of the unit pixels PX may be different. In the embodiments described with reference toFIGS.2to4, a pixel internal isolation layer may be disposed between the first photodiode and the second photodiode. For example, a light-receiving area of each of the first photodiode and the second photodiode may be determined by the pixel internal isolation layer. When the pixel internal isolation layer is not correctly aligned between the first photodiode and the second photodiode, a difference between a light-receiving area of the first photodiode and a light-receiving area of the second photodiode may occur to deteriorate an autofocusing function of an image sensor. In an embodiment of inventive concepts, a pixel internal isolation layer may be formed together with a pixel isolation layer separating the pixels from each other. For example, a trench for forming the pixel isolation layer and a trench for forming the pixel internal isolation layer may be simultaneously formed by a single process. Therefore, the pixel internal isolation layer may be accurately aligned and a difference in light-receiving area of the first photodiode and the second photodiode may be reduced and/or minimized, to limit and/or prevent deterioration of an autofocusing function of an image sensor. FIG.5is a view schematically illustrating a pixel circuit of an image sensor according to an embodiment of inventive concepts. As an example,FIG.5may be a circuit diagram illustrating a pixel circuit of a pixel including a first photodiode and a second photodiode, separated from each other by a pixel internal isolation layer and providing an autofocusing function. The pixel circuit of the pixel providing the autofocusing function is not necessarily limited as illustrated inFIG.5, and elements may be added or omitted as necessary. Referring toFIG.5, the pixel circuit may be connected to a first photodiode PD1and a second photodiode PD2, and may output a reset voltage and a pixel voltage through a column line COL. For example, the pixel circuit may include a first transfer transistor TX1, a second transfer transistor TX2, a reset transistor RX, a driving transistor DX, a select transistor SX, and a conversion gain transistor DCX. The pixel circuit may be connected to a logic circuit of the image sensor through the column line COL. The logic circuit may acquire a reset voltage and a pixel voltage through the column line COL to generate a pixel signal. When the first photodiode PD1and the second photodiode PD2are exposed to light during an exposure time period to generate charge, the first transfer transistor TX1and the second transfer transistor TX2may be sequentially turned on. The logic circuit may use a first pixel signal acquired after turning on the first transfer transistor TX1and a second pixel signal acquired after turning on the second transfer transistor TX2, to provide an autofocusing function. A reset signal RG may be used to turn on and turn off the reset transistor RX. A conversion gain signal DCR may be used to turn on and turn off the conversion gain transistor DCX. A first transfer signal TG1and a second transfer signal TG2may be used to turn on and turn off the first transfer transistor TX1and the second transfer transistor TX2, respectively. A selection signal SEL may be used to turn on and turn off the select transistor SX. A floating diffusion node FD may be between the first transfer transistor TX1and the driving transistor DX and between the second transfer transistor TX2and the conversion gain transistor DCX. The pixel circuit may be configured to receive a power supply voltage VDD through electrical connections to the reset transistor RX and driving transistor DX. FIGS.6to11are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. FIG.6may be a simplified view illustrating a portion of pixels PX1to PX4included in an image sensor200according to an embodiment of inventive concepts.FIG.7may be a cross-sectional view ofFIG.6taken along cut line I-I′, andFIG.8may be a cross-sectional view ofFIG.6taken along cut line II-II′. Referring toFIGS.6to8, a pixel isolation layer210may be disposed between pixels PX1to PX4, and each of the pixels PX1to PX4may include a pixel internal isolation layer220. The pixel internal isolation layer220may be disposed between a first photodiode PD1and a second photodiode PD2. The pixel isolation layer210and the pixel internal isolation layer220may extend in a first direction (a Z-axis direction) within a substrate201including a semiconductor material. A pixel circuit may be disposed below the first photodiode PD1and the second photodiode PD2. For example, the pixel circuit may include a plurality of elements230, wiring patterns231connected to the plurality of elements230, an insulating layer232covering the plurality of elements230and the wiring patterns231, and the like, and may be disposed on a first surface of the substrate201. The pixel circuit may include floating diffusions FD1and FD2. For example, each of the pixels PX1to PX4may include a first floating diffusion FD1and a second floating diffusion FD2. The first floating diffusion FD1may be disposed below the first photodiode PD1, and the second floating diffusion FD2may be disposed below the second photodiode PD2. The first floating diffusion FD1and the second floating diffusion FD2may be electrically connected to each other by at least one of the wiring patterns231, and a location, an area, and the like of the first floating diffusion FD1and the second floating diffusion FD2may be variously changed according to embodiments. The first floating diffusion FD1and the second floating diffusion FD2may be disposed on both sides of the pixel internal isolation layer220. Elements230adjacent to the first floating diffusion FD1and the second floating diffusion FD2may be a first transfer transistor and a second transfer transistor, respectively. A gate of each of the first transfer transistor and the second transfer transistor may have a vertical structure in which at least a partial region is embedded in the substrate201. Each of the pixels PX1to PX4may include color filters202and203, a light transmitting layer204, and a microlens205, arranged on a second surface of the substrate201. As an example, each of the pixels PX1to PX4may include one (1) microlens205disposed on or above the first photodiode PD1and the second photodiode PD2. Therefore, light that has passed through the one (1) microlens205may be directed into the first photodiode PD1and the second photodiode PD2. Referring toFIG.6, the pixel isolation layer210may have a first width W1, and the pixel internal isolation layer220may have a second width W2, narrower than the first width W1. For example, the pixel internal isolation layer220may be configured to have a narrower width than the pixel isolation layer210, to simultaneously form the pixel isolation layer210and the pixel internal isolation layer220by a single process. According to embodiments, the pixel isolation layer210and the pixel internal isolation layer220may be formed to have the same width. In addition, referring toFIGS.7and8, in the first direction, the pixel isolation layer210may have a first length d1, the pixel internal isolation layer220may have a second length d2, and the first length d1may be longer than the second length d2. For example, the pixel isolation layer210may completely pass through the substrate201, and may extend from the first surface of the substrate201to the second surface of the substrate201. In an embodiment, the internal pixel isolation layer220may have a length, shorter than a length of the first photodiode PD1and a length of the second photodiode PD2in the first direction. Charges of the first photodiode PD1and the second photodiode PD2may move with the pixel internal isolation layer220interposed therebetween. Therefore, when light is concentrated on the first photodiode PD1or the second photodiode PD2, excessively generated charges may move to limit and/or prevent saturation of the photodiodes PD1and PD2. In the embodiment illustrated inFIGS.6to8, the pixel isolation layer210and the pixel internal isolation layer220may be formed by the same process, and the pixel isolation layer210and the pixel internal isolation layer220may extend from the first surface of the substrate201on which the pixel circuit is disposed. The pixel isolation layer210and the pixel internal isolation layer220may be formed by the same process to accurately align a position of the pixel internal isolation layer220within each of the pixels PX1to PX4and reduce and/or minimize a difference in the light-receiving area of the first photodiode PD1and the second photodiode PD2, to improve an autofocusing function of the image sensor200. Next, referring toFIG.9, in pixels PX1to PX4, respectively, a pixel internal isolation layer220may include a first pixel internal isolation layer221and a second pixel internal isolation layer222. The first pixel internal isolation layer221may extend from a first surface of a substrate201on which a pixel circuit is disposed, and the second pixel internal isolation layer222may extend from a second surface of the substrate201on which color filters202and203, a light transmitting layer204, a microlens205, and the like are arranged. In the first direction, a length of the first pixel internal isolation layer221may be longer than a length of the second pixel internal isolation layer222. In an embodiment, the first pixel internal isolation layer221may be formed of a first material, and the second pixel internal isolation layer222may be formed of a second material, different from the first material. For example, the second material may have reflectivity higher than reflectivity of the first material. In addition, in an embodiment, the first pixel internal isolation layer221may be formed of a conductive material, and the second pixel internal isolation layer222may be formed of an insulating material. For example, the first pixel internal isolation layer221may be formed of polysilicon, and the second pixel internal isolation layer222may be formed of silicon oxide. The second pixel internal isolation layer222may be formed of a material having relatively high reflectivity, to reflect light passed through the microlens205against the second pixel internal isolation layer222and direct the reflected light into the first photodiode PD1or the second photodiode PD2. Therefore, sensitivity of an image sensor200A may be improved. In addition, the first pixel internal isolation layer221may be formed of a conductive material and a predetermined bias voltage, for example, a negative voltage may be applied, to reduce dark current generated in the pixels PX1to PX4. An impurity region240may be disposed between the first pixel internal isolation layer221and the second pixel internal isolation layer222. For example, the impurity region240may be a region doped with a P-type impurity. The impurity region240between the first pixel internal isolation layer221and the second pixel internal isolation layer222may provide an efficient charge transfer path between the first photodiode PD1and the second photodiode PD2. According to embodiments, the impurity region240may be doped with an N-type impurity. According to embodiments, as illustrated inFIG.10, only an impurity region240may be disposed between a pixel internal isolation layer220and color filters202and203without a second pixel internal isolation layer222. In an embodiment, an impurity region240may be formed by a process of forming a first pixel internal isolation layer221. For example, a trench for forming the first pixel internal isolation layer221, extending from a first surface of a substrate201, may be formed, and impurities may be implanted in the trench to prepare the impurity region240. The trench for forming the first pixel internal isolation layer221may be first formed and the impurities may be then implanted, to reduce an alignment error between the impurity region240and a pixel internal isolation layer220, and perform the impurity implantation operation with relatively low energy. Depending on the impurity implantation operation, at least a portion of the impurity region240may overlap a second pixel internal isolation layer222. Next, referring toFIG.11, in pixels PX1to PX4, respectively, a pixel internal isolation layer220may include a first pixel internal isolation layer221and a second pixel internal isolation layer222, and an impurity region240may be formed between the first pixel internal isolation layer221and the second pixel internal isolation layer222. The first pixel internal isolation layer221, the second pixel internal isolation layer222, and the impurity region240can be understood with reference to the descriptions described above with reference toFIGS.9and10. In the embodiment illustrated inFIG.11, a pixel isolation layer210may include a first pixel isolation layer211and a second pixel isolation layer212. In the first direction, a length of the first pixel isolation layer211may be longer than a length of the second pixel isolation layer212. Also, the second pixel isolation layer212may be formed of a material having reflectivity higher than reflectivity the first pixel isolation layer211. In an embodiment, the first pixel isolation layer211may be formed of the same material as the first pixel internal isolation layer221, and the second pixel isolation layer212may be formed of the same material as the second pixel internal isolation layer222. The second pixel isolation layer212may be formed of a material having relatively high reflectivity, to reflect portion of light passed through a microlens205against the second pixel isolation layer212and then direct the reflected light into a first photodiode PD1or a second photodiode PD2. To reduce an amount of light absorbed by the first pixel isolation layer211, the second pixel isolation layer212may be formed to have a length longer than a length of the second pixel internal isolation layer222in the first direction. Referring toFIG.11, in the first direction, a length of the first pixel isolation layer211may be shorter than a length of the first pixel internal isolation layer221, and a length of the second pixel isolation layer212may be longer than a length of the second pixel internal isolation layer222. FIGS.12to15are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. FIG.12may be a plan view illustrating a portion of pixels PX1to PX4included in an image sensor300according to an embodiment of inventive concepts, andFIG.13may be a cross-sectional view ofFIG.12taken along cut line III-III′.FIGS.14and15may be cross-sectional views ofFIG.12taken along cut line IV-IV′. First, referring toFIGS.12and13together, an image sensor300according to an embodiment may include a plurality of pixels PX1to PX4. A pixel isolation layer310may be disposed between the plurality of pixels PX1to PX4, and each of the pixels PX1to PX4may include a first photodiode PD1and a second photodiode PD2, separated from each other by a pixel internal isolation layer320. The pixel isolation layer310and the pixel internal isolation layer320may extend in the first direction (the Z-axis direction). In the embodiment described with reference toFIGS.12to15, the pixel internal isolation layer320may have a first vertical surface VS1and a second vertical surface VS2. The first vertical surface VS1and the second vertical surface VS2may be arranged to oppose each other in a third direction (an Y-axis direction), intersecting a second direction (an X-axis direction) in which the first photodiode PD1and the second photodiode PD2are arranged. Referring toFIG.12, the second vertical surface VS2may be in direct contact with the pixel isolation layer310, and the first vertical surface VS1may be separated from the pixel isolation layer310. In an embodiment, a floating diffusion FD may be disposed between the first vertical surface VS1and the pixel isolation layer310. Therefore, in each of the pixels PX1to PX4, the first photodiode PD1and the second photodiode PD2may share the floating diffusion FD. In addition, since excessively generated charges in at least one of the first photodiode PD1and/or the second photodiode PD2may move through the space between the first vertical surface VS1and the pixel isolation layer310, the pixel internal isolation layer320may completely pass through a substrate301, as illustrated inFIGS.13and15. As an example, the pixel internal isolation layer320may extend from a first surface of the substrate301on which a pixel circuit is disposed to a second surface of the substrate301on which color filters302and303, a light transmitting layer304, and a microlens305are arranged. Referring toFIG.15, a pixel internal isolation layer320may include a first pixel internal isolation layer321and a second pixel internal isolation layer322. The first pixel internal isolation layer321may be formed of a first material, the second pixel internal isolation layer322may be formed of a second material, different from the first material, and the second material may have reflectivity higher than reflectivity of the first material. Therefore, light passed through a microlens305and directly incident on the pixel internal isolation layer320, not a first photodiode PD1and a second photodiode PD2, may not be absorbed by and may be reflected against the pixel internal isolation layer320, and may be directed into the first photodiode PD1or the second photodiode PD2, to improve sensitivity of an image sensor300A. For example, the first material may be polysilicon, and the second material may be silicon oxide. In addition, althoughFIG.15illustrates that an interface between the first pixel internal isolation layer321and the second pixel internal isolation layer322is located to be lower than upper surfaces of the first photodiode PD1and the second photodiode PD2, the interface between the first pixel internal isolation layer321and the second pixel internal isolation layer322may be located to be higher than the upper surfaces of the first photodiode PD1and the second photodiode PD2. For example, in pixels PX1to PX4, respectively, the second internal isolation layer322may be in contact with a pixel isolation layer310in the third direction. For example, in the third direction, the second pixel internal isolation layer322may be connected to the pixel isolation layer310on both sides of each of the pixels PX1to PX4. In this case, a length of the first pixel internal isolation layer321may be shorter than a length of the second pixel internal isolation layer322in the third direction. FIGS.16and17are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. In the embodiments illustrated inFIGS.16and17, image sensors400and400A may include a plurality of pixels PX1to PX4separated by a pixel isolation layer410, respectively. Each of the plurality of pixels PX1to PX4may include a pixel internal isolation layer420, a first photodiode PD1, and a second photodiode PD2. First, referring toFIG.16, the pixel internal isolation layer420may include a first vertical surface VS1and a second vertical surface VS2, and one of the first vertical surface VS1and the second vertical surface VS2may be in direct contact with the pixel isolation layer410, the other thereof may be separated from the pixel isolation layer410. In addition, in the embodiment illustrated inFIG.16, pixels adjacent to each other in the third direction (the Y-axis direction), for example, a first pixel PX1and a third pixel PX3may form a structure in which the first pixel PX1and the third pixel PX3are vertically symmetrical to each other. In the embodiment illustrated inFIG.17, a first vertical surface VS1and a second vertical surface VS2of a pixel internal isolation layer420A may be separated from a pixel isolation layer410. Referring toFIG.17, in the third direction (the Y-axis direction), a first floating diffusion FD1may be disposed between the first vertical surface VS1and the pixel isolation layer410, and a second floating diffusion FD2may be disposed between the second vertical surface VS2and the pixel isolation layer410. The first floating diffusion FD1and the second floating diffusion FD2may be electrically connected to each other by a wiring pattern or the like. According to embodiments, only one of the first floating diffusion FD1and the second floating diffusion FD2may be disposed in each of the pixels PX1to PX4. Also in the embodiments illustrated inFIGS.16and17, each of the pixel internal isolation layers420and420A may include a first internal isolation layer and a second internal isolation layer. The first internal isolation layer and the second internal isolation layer may be in direct contact with each other or may be separated from each other. When the first internal isolation layer and the second internal isolation layer are separated from each other, an impurity region may be disposed therebetween. In addition, the first internal isolation layer and the second internal isolation layer may have different shapes. In an embodiment, the first internal isolation layer and the second internal isolation layer may have different lengths in the third direction. Alternatively, the impurity region may be formed between the first internal isolation layer and a color filter without the second internal isolation layer. FIGS.18and19are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. FIG.18may be a simplified view illustrating a portion of pixels PX1to PX4included in an image sensor500according to an embodiment of inventive concepts, andFIG.19may be a cross-sectional view ofFIG.18taken along cut line V-V′. Pixels PX1to PX4may be separated from each other by a pixel isolation layer510, and in each of the pixels PX1to PX4, a first photodiode PD1and a second photodiode PD2may be separated from each other by a pixel internal isolation layer520. The pixel isolation layer510and the pixel internal isolation layer520may extend inside a substrate501in the first direction (the Z-axis direction). The pixel isolation layer510may extend from a first surface of the substrate501to a second surface of the substrate501. For example, the first surface may be a surface on which a plurality of elements530, wiring patterns531, insulating layer532, and the like are arranged, and the second surface may be a surface on which color filters502and503, a light transmitting layer504, a microlens505, and the like are arranged. The pixel internal isolation layer520may include a first pixel internal isolation layer521and a second pixel internal isolation layer522. The first pixel internal isolation layer521and the second pixel internal isolation layer522may be intersected on the first surface of the substrate501. The first photodiode PD1and the second photodiode PD2may be separated from each other by the first pixel internal isolation layer521, and the second pixel internal isolation layer522may not overlap the first photodiode PD1and the second photodiode PD2in the second direction (the X-axis direction) and the third direction (the Y-axis direction). Referring toFIG.18, on the first surface, the second pixel internal isolation layer522may extend in the second direction, and the first pixel internal isolation layer521may extend in the third direction. Referring toFIG.19, the first pixel internal isolation layer521and the second pixel internal isolation layer522may be separated from each other in the first direction, and an impurity region540may be formed therebetween. The first pixel internal isolation layer521is illustrated to have a length shorter than a length of the first photodiode PD1and a length of the second photodiode PD2in the first direction, but is not limited thereto. The first pixel internal isolation layer521and the second pixel internal isolation layer522may be formed of different materials. For example, the first pixel internal isolation layer521may be formed of a conductive material, and the second pixel internal isolation layer522may be formed of an insulating material. In addition, in an embodiment, the second pixel internal isolation layer522may be formed to have reflectivity higher than reflectivity of the first pixel internal isolation layer521. In this case, light passed through the microlens505may be reflected from the second pixel internal isolation layer522, and may be then direct the reflected light into the first photodiode PD1or the second photodiode PD2. On the first surface of the substrate501, a width of the first pixel internal isolation layer521and a width of the second pixel internal isolation layer522may be equal to or narrower than a width of the pixel isolation layer510. In an embodiment, the first pixel internal isolation layer521and the second pixel internal isolation layer522may have the same width. FIGS.20to22are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. First, referring toFIG.20, pixels PX1to PX4of an image sensor600may be separated from each other by a pixel isolation layer610, and each of the pixels PX1to PX4may include a first pixel internal isolation layer621and a second pixel internal isolation layer622. Similar to the embodiment described above with reference toFIGS.18and19, the first pixel internal isolation layer621and the second pixel internal isolation layer622may be separated from each other in the first direction (the Z-axis direction). Also, the second pixel internal isolation layer622may not overlap a first photodiode PD1and a second photodiode PD2in the second direction (the X-axis direction) and the third direction (the Y-axis direction). In the embodiment illustrated inFIG.20, the second pixel internal isolation layer622may extend in each of the pixels PX1to PX4in a diagonal direction. According to embodiments, in at least a portion of the pixels PX1to PX4, the second pixel internal isolation layer622may extend in different directions. For example, in a first pixel PX1, the second pixel internal isolation layer622may extend in a direction of 45 degrees with respect to the second direction. In a second pixel PX2, the second pixel internal isolation layer622may extend in a direction of 135 degrees with respect to the second direction. As illustrated inFIG.20, the second pixel internal isolation layer622may be disposed in the diagonal direction, to use pixel signals acquired from each of the first photodiode PD1and the second photodiode PD2in implementing autofocusing functions in different directions. As an example, in the embodiment illustrated inFIG.20, the pixel signals acquired from each of the first photodiode PD1and the second photodiode PD2of the first pixel PX1may be also used to implement an autofocusing function in the vertical direction. In the embodiment illustrated inFIG.20, since the second pixel internal isolation layer622may extend in the diagonal direction, a length of the second pixel internal isolation layer622may be longer than a length of the first pixel internal isolation layer621, on a plane parallel to an upper surface of a substrate. Next, referring toFIG.21, pixels PX1to PX4of an image sensor700may be separated by a pixel isolation layer710, and each of the pixels PX1to PX4may include a pixel internal isolation layer720extending in the diagonal direction. Therefore, as illustrated inFIG.21, a first photodiode PD1and a second photodiode PD2may have a different shape, as compared to those of the image sensors200,300,400,500, and600according to the above-described embodiments. Each of the pixels PX1to PX4may include a first floating diffusion FD1and a second floating diffusion FD2, and the first floating diffusion FD1and the second floating diffusion FD2may be electrically connected to each other by a wiring pattern or the like. In addition, according to embodiments, in at least a portion of the pixels PX1to PX4, the pixel internal isolation layer720may extend in a diagonal direction, different from that illustrated inFIG.21. Next, in the embodiment illustrated inFIG.22, a pixel isolation layer810disposed between pixels PX1to PX4in an image sensor800may be separated as a plurality of regions. Referring toFIG.22, each of the pixels PX1to PX4may be surrounded by the pixel isolation layer810in the second direction (the X-axis direction) and the third direction (the Y-axis direction), and a pixel internal isolation layer820may be connected to a pair of pixel isolation layers810separated from each other in the third direction. Therefore, in the embodiment illustrated inFIG.22, at least a portion of the pixel isolation layer810may be separated without being connected to the pixel internal isolation layer820. FIGS.23to26are views schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. Referring toFIG.23, pixels PX1to PX4included in an image sensor900may be separated from each other by a pixel isolation layer910, and a first photodiode PD1and a second photodiode PD2included in each of the pixels PX1to PX4may be separated by a pixel internal isolation layer920. The pixel internal isolation layer920may include a plurality of regions separated by a desired and/or alternatively predetermined interval, in the third direction (the Y-axis direction) intersecting the second direction (the X-axis direction), which may be a direction in which the first photodiode PD1and the second photodiode PD2are arranged. A floating diffusion FD may be disposed between the plurality of regions included in the pixel internal isolation layer920. Referring toFIG.25illustrating a cross-sectional view ofFIG.23taken along cut line VII-VII′, the pixel internal isolation layer920may not be disposed on or above the floating diffusion FD. In the embodiment illustrated inFIG.23, intervals between the plurality of regions included in the pixel internal isolation layer920may be different in a portion of the pixels PX1to PX4. As an example, an interval in a first pixel PX1between the plurality of regions included in the pixel internal isolation layer920may be smaller than an interval in a second pixel PX2between the plurality of regions included in the pixel internal isolation layer920. an interval in a third pixel PX3between the plurality of regions included in the pixel internal isolation layer920may be smaller than the interval in the first pixel PX1between the plurality of regions included in the pixel internal isolation layer920. Referring toFIG.24illustrating a cross-sectional view ofFIG.23taken along cut line VI-VI′, the first pixel PX1may include a green color filter902, and the second pixel PX2may include a red color filter903. The third pixel PX3may include a blue color filter. As an example, in a pixel generating charges in response to light of a short wavelength band, intervals between the plurality of regions included in the pixel internal isolation layer920may be relatively reduced. Referring toFIG.24, a substrate901has a first surface on which a plurality of devices930, wiring patterns931, and an insulating layer932are arranged, and a second surface opposing the first surface. The pixel isolation layer910may extend from the first surface to the second surface. The internal pixel isolation layer920may extend from the first surface, and may have a length shorter than a length of the pixel isolation layer910in the first direction (the Z-axis direction). Referring toFIG.26, a pixel internal isolation layer920may include a first pixel internal isolation layer921extending from a first surface of a substrate and a second pixel internal isolation layer922extending from a second surface of the substrate. In pixels PX1to PX4, respectively, since the pixel internal isolation layer920may include a plurality of regions separated in the third direction, a charge path in which excessively generated charges in one of photodiodes PD1and PD2move to the other thereof may be implemented in each of the pixels PX1to PX4. In an image sensor900A according to the embodiment illustrated inFIG.26, the second pixel internal isolation layers922may be in contact with the pixel isolation layers910at both ends in the third direction. For example, unlike the first pixel internal isolation layer921having a plurality of regions separated from each other in the third direction, the second pixel internal isolation layer922may have a shape completely intersecting each of the pixels PX1to PX4. Therefore, a length of the second pixel internal isolation layer922may be longer than a length of the first pixel internal isolation layer921in the third direction. FIG.27is a view schematically illustrating pixels included in an image sensor according to an embodiment of inventive concepts. In an image sensor1000according to the embodiment illustrated inFIG.27, a pixel internal isolation layer1020in pixels PX1to PX4, respectively, may include a first pixel internal isolation layer1021and a second pixel internal isolation layer1022. The first pixel internal isolation layer1021may have a structure similar to the pixel internal isolation layer920described with reference toFIGS.23to26. The second pixel internal isolation layer1022may extend from each of the pixels PX1to PX4in the diagonal direction. In a similar manner to the embodiments described above, for example, in a similar manner to the embodiments described with reference toFIGS.18and19, an impurity region may be formed between the first pixel internal isolation layer1021and the second pixel internal isolation layer1022in the first direction (the Z-axis direction). The impurity region may be provided as a charge path for facilitating charge transfer between a first photodiode PD1and a second photodiode PD2. Alternatively, in a similar manner to the embodiment described with reference toFIG.26, the first pixel internal isolation layer1021and the second pixel internal isolation layer1022may be in contact with each other in the first direction. In this case, a length the first pixel internal isolation layer1021may be longer than a length of the first photodiode PD1and a length of the second photodiode PD2in the first direction. In addition, according to embodiments, an autofocusing function in the vertical direction may be implemented using a pixel signal corresponding to charges of the first photodiode PD1and a pixel signal corresponding to charges of the second photodiode PD2. FIGS.28to33are views illustrating a method of manufacturing an image sensor according to an embodiment of inventive concepts. First, referring toFIG.28, a method of manufacturing an image sensor may begin with forming a pixel isolation layer1110on a substrate1101. Referring also toFIG.29illustrating a cross-sectional view ofFIG.28taken along cut line VIII-VIII′, the pixel isolation layer1110may be formed from a first surface1101A of the substrate1101. For example, a trench extending from the first surface1101A of the substrate1101may be formed and the formed trench may be filled with a material such as polysilicon, to prepare the pixel isolation layer1110. Referring toFIGS.28and29, the pixel isolation layer1110may be formed together with a pixel internal isolation layer1120respectively disposed inside pixel regions PA1to PA4. The internal pixel isolation layer1120may be formed to have a width narrower than a width of the pixel isolation layer1110, and may include the same material as the pixel isolation layer1110, for example, polysilicon. Referring toFIG.29, in the first direction (the Z-axis direction), the pixel isolation layer1110may have a first length d1, and the pixel internal isolation layer1120may have a second length d2, shorter than the first length d1. Next, referring toFIGS.30and31, photodiodes PD1and PD2and a pixel circuit may be formed in each of the pixel regions PA1to PA4. The photodiodes PD1and PD2may be formed on both sides of the pixel internal isolation layer1120, and may be formed by an impurity implantation process of implanting an N-type impurity, for example. The pixel circuit may be formed on the first surface1101A of the substrate1101, and may include floating diffusions FD1and FD2, a plurality of elements1130, wiring patterns1131, and the like. An insulating layer1132covering the pixel circuit may be formed on the first surface1101A of the substrate1101. The insulating layer1132may be formed of silicon oxide, silicon nitride, or the like. The floating diffusions FD1and FD2may be formed to be adjacent to the pixel internal isolation layer1120, and elements1130adjacent to the floating diffusions FD1and FD2may be transfer transistors. Next, referring toFIG.32, a partial region of the substrate1101may be removed while the substrate1101is turned over to face the first surface1101A in a downward direction. For example, a partial region of the substrate1101may be removed by performing a polishing process or the like. In the embodiment illustrated inFIG.32, it is illustrated that a portion of the substrate1101may be removed by a polishing process to expose one surface of the pixel isolation layer1110. In a different manner to this, the pixel isolation layer1110may not be exposed. The one surface of the substrate1101exposed by the polishing process may be defined as a second surface1101B. Referring toFIG.33, color filters1102and1103, a light transmitting layer1104, and a microlens1105may be formed on the second surface1101B. The color filters1102and1103included in adjacent pixels PX1and PX2may transmit light of different colors. The light transmitting layer1104may be shared by the adjacent pixels PX1and PX2, and the microlens1105for each of the pixels PX1and PX2may be disposed. Therefore, the photodiodes PD1and PD2may be provided as a plurality of photodiodes below one (1) microlens1105. FIGS.34to41are views illustrating a method of manufacturing an image sensor according to an embodiment of inventive concepts. First, referring toFIG.34, in order to manufacture an image sensor, a first trench T1and a second trench T2may be formed in a substrate1201including a semiconductor material. Referring toFIG.35illustrating a cross-sectional view ofFIG.34taken along cut line IX-IX′ together, the first trench T1and the second trench T2may extend from a first surface1201A of the substrate1201, and may be formed simultaneously by an etching process. For example, the first trench T1may have a first length d1in the first direction (the Z-axis direction), perpendicular to the first surface1201A of the substrate1201, and the second trench T2may have a second length d2, shorter than the first length d1. Also, in a direction parallel to the first surface1201A, a width of the first trench T1may be wider than a width of the second trench T2. Pixel regions PA1to PA4may be defined by the first trench T1, and the second trench T2may be disposed inside each of the pixel regions PA1to PA4. Next, referring toFIG.36, impurities may be implanted through the second trench T2. An impurity region1240may be formed on or below the second trench T2by an impurity implantation process. For example, the impurity region1240may be provided as a charge path between photodiodes formed on or around both sides of the second trench T2, and may include a P-type impurity. According to embodiments, the impurity region1240may include an N-type impurity. As illustrated inFIG.36, the second trench T2together with the first trench T1may be formed, and the impurity implantation process may be performed, to complete the impurity implantation process with relatively low energy. According to embodiments, the impurity region1240may be formed to have a depth, substantially equal to a depth of a bottom surface of the first trench T1. Referring toFIGS.37and38, the first trench T1and the second trench T2may be filled with desired and/or alternatively predetermined materials to form a pixel isolation layer1210and a first pixel internal isolation layer1221, respectively. In addition, photodiodes PD1and PD2may be formed within the substrate1201, and a pixel circuit may be formed on the first surface1201A. The pixel circuit may include floating diffusions FD1and FD2, a plurality of elements1230, wiring patterns1231, and the like, and may be covered with an insulating layer1232. The pixel isolation layer1210and the first pixel internal isolation layer1221may be formed by filling the first trench T1and the second trench T2with materials such as polysilicon, respectively. As previously described with reference toFIG.36, since an impurity region1240may be formed by performing an impurity implantation process to pass through the second trench T2, the first pixel internal isolation layer1221and the impurity region1240may be accurately aligned. Referring toFIG.39, after the substrate1201is turned over, a polishing process may be performed. One surface of the substrate1201exposed by the polishing process may be defined as a second surface1201B. As an example, the polishing process may be performed until one surface of the pixel isolation layer1210forms a coplanar surface with the second surface1201B. Therefore, as illustrated inFIG.39, the pixel isolation layer1210may pass through the substrate1201. Referring toFIG.40, a second pixel internal isolation layer1222extending from the second surface1201B may be formed. The second pixel internal isolation layer1222may be formed to be aligned with the impurity region1240and the first pixel internal isolation layer1221in the second direction (the X-axis direction) and the third direction (the Y-axis direction). For example, the second pixel internal isolation layer1222may be formed on or above the impurity region1240, and may be provided together with the first pixel internal isolation layer1221to prepare a pixel internal isolation layer1220. In the embodiment illustrated inFIG.40, the second pixel internal isolation layer1222may have the same shape as the first pixel internal isolation layer1221. According to embodiments, the second pixel internal isolation layer1222may have various shapes, different from the first pixel internal isolation layer1221. For example, unlike the first pixel internal isolation layer1221extending in the third direction, the second pixel internal isolation layer1222may extend in the second direction or in a direction intersecting the second and third directions. Also, the second pixel internal isolation layer1222may not be formed according to embodiments. Next, referring toFIG.41, color filters1202and1203, a light transmitting layer1204, and a microlens1205may be formed on the substrate1201. The color filters1202and1203respectively included in a first pixel PX1and a second pixel PX2, adjacent to each other, may transmit light of different colors. In addition, one (1) microlens1205may be disposed in each of the pixels PX1and PX2. Therefore, the photodiodes PD1and PD2may be provided as a plurality of photodiodes below the one (1) microlens1205. FIGS.42and43are views schematically illustrating an electronic device including an image sensor according to an embodiment of inventive concepts. Referring toFIG.42, an electronic device2000may include a camera module group2100, an application processor2200, a power management integrated circuit (PMIC)2300, and an external memory2400. The camera module group2100may include a plurality of camera modules2100a,2100b, and2100c. Although the drawing illustrates an embodiment in which three (3) camera modules2100a,2100b, and2100care arranged, embodiments are not limited thereto. In an embodiment, the camera module group2100may be modified to include only two (2) camera modules. In addition, in an embodiment, the camera module group2100may be modified and implemented to include n (where n is a natural number of 4 or more) camera modules. In addition, in an embodiment, at least one of the plurality of camera modules2100a,2100b, and2100cincluded in the camera module group2100may include the image sensors described inFIGS.1to41. The external memory2400may be a nonvolatile memory, such as a flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferro-electric RAM (FRAM), or a volatile memory, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM). Hereinafter, referring toFIG.43, a configuration of the camera module2100bwill be described in more detail, but the following description may be equally applied to other camera modules2100aand2100caccording to an embodiment. Referring back toFIG.43, the camera module2100bmay include a prism2105, an optical path folding element (hereinafter referred to as “OPFE”)2110, an actuator2130, an image sensing device2140, and a storage device2150. The prism2105may include a reflective surface2107of a light reflecting material to change a path of light L externally incident. In an embodiment, the prism2105may change the path of the light L, incident in the first direction X, to the second direction Y, perpendicular to the first direction X. In addition, the prism2105may rotate the reflective surface2107of the light reflecting material in a direction A around a central axis2106, or may rotate the central axis2106in a direction B, to change the path of the light L, incident in the first direction X, to the second direction Y, perpendicular thereto. In this case, the OPFE2110may also move in the third direction Z, perpendicular to the first direction X and the second direction Y. In an embodiment, as illustrated, a maximum rotation angle of the prism2105may be 15 degrees or less in a positive (+) direction of the direction A, and may be greater than 15 degrees in a negative (−) direction of the direction A. Embodiments are not limited thereto. In an embodiment, the prism2105may move in a positive (+) direction or a negative (−) direction of the direction B by around 20 degrees, or between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees. In this case, a moving angle may be an angle that may move at the same angle, or may move to almost the same angle in a range of around 1 degree, in the positive (+) or negative (−) direction of the direction B. In an embodiment, the prism2105may move the reflective surface2107of the light reflecting material in the third direction (e.g., the direction Z), parallel to an extending direction of the central axis2106. The OPFE2110may include, for example, optical lenses of m (where m is a natural number) groups. The m optical lenses may move in the second direction Y to change an optical zoom ratio of the camera module2100b. For example, if a basic optical zoom magnification of the camera module2100bis Z, when the m optical lenses included in the OPFE2110move, an optical zoom magnification of the camera module2100bmay be changed to have an optical zoom magnification of3Z,5Z, or5Z or higher. The actuator2130may move the OPFE2110or an optical lens (hereinafter, referred to as an optical lens) to a specific position. For example, the actuator2130may adjust a position of the optical lens to locate an image sensor2142at a focal length of the optical lens for accurate sensation. The actuator2130may include an electric motor. The image sensing device2140may include an image sensor2142, a control logic2144, and a memory2146. The image sensor2142may sense an image of an object to be sensed by using light L provided through an optical lens. The control logic2144may control an overall operation of the camera module2100b. For example, the control logic2144may control an operation of the camera module2100baccording to a control signal provided through a control signal line CSLb. The memory2146may store information necessary for an operation of the camera module2100b, such as calibration data2147. The calibration data2147may include information necessary for the camera module2100bto generate image data using light L externally provided. The calibration data2147may include, for example, information on the degree of rotation, described above, information on a focal length, information on an optical axis, or the like. When the camera module2100bis implemented in the form of a multi-state camera of which focal length is changed according to a position of the optical lens, the calibration data2147may include a focal length value for each position (or state) of the optical lens, and information related to autofocusing. The storage device2150may store the image data sensed by the image sensor2142. The storage device2150may be disposed outside the image sensing device2140, and may be implemented in stacked form with a sensor chip constituting the image sensing device2140. In an embodiment, the storage device2150may be implemented as an electrically erasable programmable read-only memory (EEPROM), but embodiments are not limited thereto. Referring toFIGS.42and23together, in an embodiment, the plurality of camera modules2100a,2100b, and2100cmay include the actuator2130, respectively. Therefore, the plurality of camera modules2100a,2100b, and2100cmay include the same or different calibration data2147, respectively, according to an operation of the actuator2130included therein. In an embodiment, a camera module (e.g.,2100b), among the plurality of camera modules2100a,2100b, and2100c, may be a folded lens type camera module including the prism2105and the OPFE2110, described above, and remaining camera module(s) (e.g.,2100aor2100c) may be a vertical type camera module not including the prism2105and the OPFE2110, but embodiments are not limited thereto. In an embodiment, a camera module (e.g.,2100c), among the plurality of camera modules2100a,2100b, and2100c, may be a vertical type depth camera for extracting depth information using, for example, infrared ray (IR). In this case, the application processor2200may merge image data provided from the depth camera with image data provided from another camera module (for example,2100aor2100b) to generate a3D depth image. In an embodiment, at least two camera modules (e.g.,2100aand2100b), among the plurality of camera modules2100a,2100b, and2100c, may have different fields of view (e.g., field of view angles). In this case, for example, optical lenses of the at least two camera modules (e.g.,2100aand2100b), among the plurality of camera modules2100a,2100b, and2100c, may be different from each other, but are not limited thereto. In addition, in an embodiment, field of view angles of each of the plurality of camera modules2100a,2100b, and2100cmay be different. In this case, optical lenses included in each of the plurality of camera modules2100a,2100b, and2100cmay also be different from each other, but are not limited thereto. In an embodiment, each of the plurality of camera modules2100a,2100b, and2100cmay be arranged to be physically separated from each other. For example, a sensation area of one (1) image sensor2142may not be divided and used by the plurality of camera modules2100a,2100b, and2100c, but an independent image sensor2142inside each of the plurality of camera modules2100a,2100b, and2100cmay be disposed. Referring back toFIG.42, the application processor2200may include an image processing device2210, a memory controller2220, and an internal memory2230. The application processor2200may be implemented to be separated from the plurality of camera modules2100a,2100b, and2100c. For example, the application processor2200and the plurality of camera modules2100a,2100b, and2100cmay be implemented to be separated from each other, as separate semiconductor chips. The image processing device2210may include a plurality of sub-image signal processors2212a,2212b, and2212c, an image generator2214, and a camera module controller2216. The image processing device2210may include a plurality of sub-image signal processors2212a,2212b, and2212c, corresponding to the number of camera modules2100a,2100b, and2100c. Image data generated from each of the camera modules2100a,2100b, and2100cmay be provided to the corresponding sub-image signal processors2212a,2212b, and2212cthrough image signal lines ISLa, ISLb, and ISLc, separated from each other. For example, image data generated from the camera module2100amay be provided to the sub-image signal processor2212athrough the image signal line ISLa, image data generated from the camera module2100bmay be provided to the sub-image signal processor2212bthrough the image signal line ISLb, and image data generated from the camera module2100cmay be provided to the sub-image signal processor2212cthrough the image signal line ISLc. Transmission of such image data may be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but embodiments are not limited thereto. In an embodiment, a sub-image signal processor may be disposed to correspond to a plurality of camera modules. For example, the sub-image signal processor2212aand the sub-image signal processor2212cmay not be implemented to be separated from each other, as illustrated, but may be implemented to be integrated into a single sub-image signal processor, and image data provided from the camera module2100aand the camera module2100cmay be selected by a select element (e.g., a multiplexer) or the like, and may be then provided to the integrated sub-image signal processor. Image data provided to each of the sub-image signal processors2212a,2212b, and2212cmay be provided to the image generator2214. The image generator2214may use the image data provided from each of the sub-image signal processors2212a,2212b, and2212c, according to image generation information or a mode signal, to generate an output image. Specifically, the image generator2214may merge at least portion of the image data generated from the camera modules2100a,2100b, and2100chaving different field of view angles, according to image generation information or a mode signal, to generate an output image. In addition, the image generator2214may generate an output image by selecting any one of image data generated from camera modules2100a,2100b, and2100chaving different field of view angles according to image generation information or a mode signal. In an embodiment, the image generation information may include a zoom signal or a zoom factor. Further, in an embodiment, the mode signal may be, for example, a signal based on a mode selected by a user. When the image generation information is a zoom signal (e.g., a zoom factor) and each of the camera modules2100a,2100b, and2100chas different fields of view (e.g., field of view angles), the image generator2214may operate differently according to a type of the zoom signal. For example, when the zoom signal is a first signal, after merging image data output from the camera module2100aand image data output from the camera module2100c, the merged image signal and image data output from the camera module2100b, not used in the merging, may be used to generate an output image. When the zoom signal is a second signal, different from the first signal, the image generator2214may not perform such image data merging, and may select any one of the image data output from each of the camera module2100a,2100b, and2100c, to create an output image. Embodiments are not limited thereto, and a method of processing image data may be modified and performed as needed. In an embodiment, the image generator2214may receive a plurality of pieces of image data having different exposure points in time from at least one sub-image signal processor, among the plurality of sub-image signal processors2212a,2212b, and2212c, and may process high dynamic range (HDR) with respect to the plurality of pieces of image data, to generate merged image data having an increased dynamic range. The camera module controller2216may provide a control signal to each of the camera modules2100a,2100b, and2100c. The control signal generated from the camera module controller2216may be provided to the corresponding camera modules2100a,2100b, and2100cthrough control signal lines CSLa, CSLb, and CSLc, separated from each other. Any one of the plurality of camera modules2100a,2100b, and2100cmay be designated as a master camera (for example,2100b), according to image generation information including a zoom signal, or a mode signal, and remaining camera modules (for example,2100aand2100c) may be designated as slave cameras. Such information may be included in the control signal, and may be provided to the corresponding camera modules2100a,2100b, and2100cthrough the control signal lines CSLa, CSLb, and CSLc, separated from each other. Camera modules operating as masters and slaves may be changed according to a zoom factor or an operation mode signal. For example, when a field of view angle of the camera module2100ais wider than a field of view angle of the camera module2100band the zoom factor indicates a low zoom magnification, the camera module2100bmay operate as a master, and the camera module2100amay operate as a slave. When the zoom factor indicates a high zoom magnification, the camera module2100amay operate as a master and the camera module2100bmay operate as a slave. In an embodiment, a control signal provided from the camera module controller2216to each of the camera modules2100a,2100b, and2100cmay include a sync enable signal. For example, when the camera module2100bis a master camera and the camera modules2100aand2100care slave cameras, the camera module controller2216may transmit a sync enable signal to the camera module2100b. The camera module2100breceiving such a sync enable signal may generate a sync signal based on the sync enable signal, and may transmit the generated sync signal to the camera modules2100aand2100cthrough a sync signal line SSL. The camera module2100band the camera modules2100aand2100cmay be synchronized with the sync signal, to transmit image data to the application processor2200. In an embodiment, a control signal provided from the camera module controller2216to the plurality of camera modules2100a,2100b, and2100cmay include mode information according to a mode signal. Based on this mode information, the plurality of camera modules2100a,2100b, and2100cmay operate in a first operation mode and a second operation mode in relation to a sensation rate. In the first operation mode, the plurality of camera modules2100a,2100b, and2100cmay generate an image signal at a first rate (for example, generate an image signal having a first frame rate), may encode the generated image signal at a second rate, higher than the first rate (e.g., encode an image signal having a second frame rate, higher than the first frame rate), and may transmit the encoded image signal to the application processor2200. In this case, the second rate may be 30 times or less of the first rate. The application processor2200may store the transmitted image signal, e.g., the encoded image signal, in the internal memory2230, or in a storage2400outside the application processor2200, and may then read the encoded image signal from the internal memory2230or the storage2400, may decode the read image signal, and may display image data generated based on the decoded image signal. For example, a corresponding sub-image signal processor, among the plurality of sub-image signal processors2212a,2212b, and2212cof the image processing device2210, may decode the read image signal, and may also perform image processing on the decoded image signal. In the second operation mode, the plurality of camera modules2100a,2100b, and2100cmay generate an image signal at a third rate, lower than the first rate (e.g., generate an image signal having a third frame rate, lower than the first frame rate), and may transmit the image signal to the application processor2200. The image signal provided to the application processor2200may be a signal, not encoded. The application processor2200may perform image processing on the received image signal, or may store the received image signal in the internal memory2230or the storage2400. The PMIC2300may supply power, for example, a power voltage to each of the plurality of camera modules2100a,2100b, and2100c. For example, under control of the application processor2200, the PMIC2300may supply first power to the camera module2100athrough a power signal line PSLa, may supply second power to the camera module2100bthrough a power signal line PSLb, and may supply third power to the camera module2100cthrough a power signal line PSLc. The PMIC2300may generate power, corresponding to each of the plurality of camera modules2100a,2100b, and2100c, in response to a power control signal PCON from the application processor2200, and may also adjust a level of the power. The power control signal PCON may include a power adjustment signal for each operation mode of the plurality of camera modules2100a,2100b, and2100c. For example, the operation mode may include a low power mode. In this case, the power control signal PCON may include information on a camera module operating in the low power mode and a level of the power to be set. The levels of pieces of power provided to each of the plurality of camera modules2100a,2100b, and2100cmay be the same or different from each other. Also, the level of power may be dynamically changed. According to an embodiment of inventive concepts, an image sensor may include an autofocusing pixel, and the autofocusing pixel may include a first photodiode and a second photodiode, separated from each other by a pixel internal isolation layer. The pixel internal isolation layer may include a first pixel internal isolation layer and a second pixel internal isolation layer isolation layer, formed of different materials. The pixel internal isolation layer may extend from a first surface of a substrate together with a pixel isolation layer between pixels, and may provide a charge path through which charges may move between the first photodiode and the second photodiode. Therefore, alignment errors between the pixel isolation layer and the pixel internal isolation layer may be reduced and/or minimized, and capacitance of the pixels may be improved. One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. Various features and effects of inventive concepts are not limited to the above-described contents, and can be more easily understood in the course of describing specific embodiments of inventive concepts. While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of inventive concepts as defined by the appended claims. | 71,921 |
11942501 | DESCRIPTION OF EMBODIMENTS A solid-state image pickup apparatus according to the present invention is formed by placing a first substrate and a second substrate upon each other, with the first substrate being provided with a photoelectric conversion element and a gate electrode for transfer and the second substrate being provided with a peripheral circuit portion. A high-melting-metal compound layer is not provided at the first substrate, whereas a high-melting-metal compound layer is provided at the second substrate. By such a structure, it becomes easier to determine where to form the compound layer, and it becomes possible for a transistor at the peripheral circuit portion to operate at a higher speed, and a signal readout operation to be performed at a high speed while suppressing a reduction in the characteristics of the photoelectric conversion element. The present invention will hereunder be described in detail with reference to the drawings. First Embodiment A first embodiment of the present invention will be described with reference toFIGS.1and12. First, an exemplary circuit of a solid-state image pickup apparatus according to the first embodiment will be described with reference toFIG.12. A solid-state image pickup apparatus300shown inFIG.12includes a pixel portion301, in which a plurality of photoelectric conversion elements are arranged, and a peripheral circuit portion302, provided with a control circuit for performing a driving operation for reading out a signal from the pixel portion301and with a signal processing circuit that processes the readout signal. In the pixel portion301, a plurality of photoelectric conversion elements303, transfer transistors304, amplification transistors306, and reset transistors307are disposed. A structure including at least one photoelectric conversion element303is defined as a pixel. One pixel in the embodiment includes the photoelectric conversion element303, the transfer transistor304, the amplification transistor306, and the reset transistor307. A source of the transfer transistor304is connected to the photoelectric conversion element303, and a drain region of the transfer transistor304is connected to a gate electrode of the amplification transistor306. A node corresponding to the gate electrode of the amplification transistor306is defined as a node305. The reset transistor is connected to the node305, and an electric potential of the node305is set to any electric potential (for example, a reset electric potential). Here, the amplification transistor306is a portion of a source follower circuit, and a signal corresponding to the electric potential of the node305is output to a signal line RL. The peripheral circuit portion302includes a vertical scanning circuit VSR for supplying a control signal to the gate electrode of the transistor of the pixel portion301. The peripheral circuit portion302includes a readout circuit RC holding a signal output from the pixel portion301and including a signal processing circuit for amplification, addition, AD conversion, etc. In addition, the peripheral circuit portion302includes a horizontal scanning circuit HSR of a control circuit that controls timing with which signals from the readout circuit RC are successively output. Here, the solid-state image pickup apparatus300according to the first embodiment is formed by placing two chips upon each other. The two chips are a first chip308including a photoelectric conversion element303and a transfer transistor304of the pixel portion301, and a second chip309including an amplification transistor306and a reset transistor307of the pixel portion301and the peripheral circuit portion302. In such a structure, a control signal is supplied to the gate electrode of the transfer transistor304of the first chip308from the peripheral circuit portion302of the second chip309through a connection portion310. A signal generated at the photoelectric conversion element303of the first chip308is read out to the node305through a connection portion311connected to the drain region of the transfer transistor304. By providing the reset transistor307and the amplification transistor306at a different chip in this way, it is possible to increase the area of the photoelectric conversion element303, and to increase sensitivity. If the area of the photoelectric conversion element303is the same, many photoelectric conversion elements303can be provided, thereby making it possible to increase the number of pixels. Next, a solid-state image pickup apparatus according to an embodiment will be described with reference toFIG.1.FIG.1is a sectional view of a solid-state image pickup apparatus100corresponding to the solid-state image pickup apparatus300shown inFIG.12.FIG.1is a sectional view that is in correspondence with the photoelectric conversion elements303, the transfer transistors304, and the amplification transistors306shown inFIG.12. The other portions are not described.FIG.1shows a structure for two pixels. FIG.1shows a first chip101, a second chip102, and a bonding surface103of the first chip and the second chip. The first chip101corresponds to the first chip308shown inFIG.12, and the second chip102corresponds to the second chip309shown inFIG.12. The first chip101has a first substrate104. A surface of the first substrate104where a transistor is formed is a principal surface105, and a surface thereof opposite thereto is a back surface106. A portion constituting the photoelectric conversion element303and the transfer transistor304shown inFIG.12is disposed at the first substrate104. A multilayer wiring structure107, including a first wiring layer122and a second wiring layer123, which, for example, have wires whose main component is aluminum (aluminum wires), is provided on an upper portion at a principal-surface-105-side of the first substrate104of the first chip101. Here, a plurality of interlayer insulating films of the multilayer wiring structure107are described as an integral insulating film. The second chip102has a second substrate108. A surface of the second substrate108where a transistor is formed is a principal surface109, and a surface thereof opposite thereto is a back surface110. A multilayer wiring structure111, including a first wiring layer128and a second wiring layer129, which, for example, have aluminum wires, is provided on an upper portion of the principal surface109of the second substrate108. Even here, a plurality of interlayer insulating films of the multilayer wiring structure111are described as an integral insulating film. An amplification transistor306shown inFIG.12is disposed at the second substrate108. In the description, in each chip, a direction from the principal surface of the substrate to the back surface is defined as a downward direction or a deep direction, and a direction from the back surface to the principal surface is defined as an upward direction or a shallow direction. Here, in the solid-state image pickup apparatus according to the embodiment, the substrate principal surface105of the first chip101and the substrate principal surface109of the second chip102are placed upon each other so as to face each other. InFIG.1, in a structure of a connection portion of the first chip101and the second chip102, a connection between a floating diffusion region (FD region)113of the first chip101and the gate electrode126of an amplification transistor126of the second chip102is only shown. More specifically, the FD region113of the first chip101is connected to the gate electrode126of the amplification transistor through the multilayer wiring structure107, a connection portion311, and the multilayer wiring structure111. The connection portion310shown inFIG.12that supplies a control signal to the gate electrode114of the transfer transistor is not shown inFIG.1. The solid-state image pickup apparatus according to the embodiment is a backside-illumination solid-state image pickup apparatus upon which light is incident from the back surface106of the first substrate104. Each chip will be described in detail. First, a well115, an N-type charge storage region112constituting the photoelectric conversion element, and the gate electrode114of the transfer transistor are disposed at the first substrate104of the first chip101. Further, a P-type surface protection layer constituting the photoelectric conversion element is disposed on the upper portion of the charge storage region112. Further, a P-type semiconductor region116, an element isolation region117, and the drain region113of the transfer transistor are disposed at the first substrate104. The well115is a semiconductor region where the transistor and the photoelectric conversion element are disposed, and, here, may be either a N type or a P type. The P-type semiconductor region116can suppress dark current generated at an interface between a silicon oxide film and silicon of the back surface106of the first substrate104, and can even function as a portion of the photoelectric conversion element. The charge storage region112stores electric charge (electrons) generated at the photoelectric conversion element, and has a P-type surface protective layer at a gate-electrode-side of the transfer transistor inFIG.1. The element isolation region117is formed of a P-type semiconductor region, and, although not shown, may have an element isolation structure including an insulating film such as a LOCOS isolation layer or a STI isolation layer. The drain region113of the transfer transistor is an FD region, and constitutes the node305shown inFIG.12. A back-surface-106-side of the first substrate104of the first chip101is provided with an antireflection film118, a light-shielding film119, a color filter layer120including a planarizing layer, and a microlens121. Next, a well124, a source region and drain region125, and the gate electrode126of the amplification transistor306inFIG.12, and an element isolation region127are disposed at the second substrate108of the second chip102. The well124is a P-type semiconductor region. Here, the source region and drain region125of the transistor (the amplification transistor306shown inFIG.12), disposed at the second chip102of the solid-state image pickup apparatus according to the embodiment, include a high-melting-metal compound layer130. A region constituting the peripheral circuit portion302shown inFIG.12, disposed at the second chip102, is also similarly provided with a transistor including a high-melting-metal compound layer (not shown). The high-melting-metal compound layer is, for example, silicide using cobalt or titanium, which is a high-melting metal, when silicon is used in the semiconductor substrate. A high-melting-metal compound layer is not formed at, for example, the transistor of the first substrate104. The insulating film of a multilayer wiring structure is disposed at the upper portion of the principal surface105of the first substrate104. Accordingly, a high-melting-metal compound layer is not formed at the first substrate104and the transistor of the peripheral circuit portion disposed at the second substrate has a high-melting-metal compound layer, so that it is possible to increase the speed of operation of the transistor while reducing noise. In addition, by providing the transistor including such a high-melting-metal compound layer only at the second chip102, it is possible to reduce mixing of the high-melting metal into the photoelectric conversion element, and to reduce noise generated by the mixture of the high-melting metal. Since it is not necessary to form a region where a high-melting-metal compound layer is to be provided and a region where a high-melting-metal compound layer is not to be provided on the same substrate, it is not necessary to form, for example, a protective film to prevent the formation of a high-melting-metal compound layer, that is, it is possible for each substrate to have a simple structure and to manufacture it using a simple step. In the embodiment, in addition to the photoelectric conversion element, the FD region is formed at the first substrate104. This is because, if a high-melting-metal compound layer is provided at the photoelectric conversion element and the semiconductor region constituting the FD region which hold signal charges, noise generated when a high-melting metal is mixed into the semiconductor region mixes in the signal electric charges. If the amplification transistor is disposed at the first substrate, a high-melting-metal compound layer is not formed at the amplification transistor. Although, in the embodiment, each wiring layer is formed of aluminum wires, each wiring layer may be formed of wires whose main component is copper (copper wires). A diffusion prevention film, which prevents diffusion of copper, may also be provided at upper portions of the copper wires, and the diffusion prevention film, which prevents diffusion of copper, may be subjected to patterning. Second Embodiment A solid-state image pickup apparatus according to this embodiment will be described with reference toFIG.2. The solid-state image pickup apparatus according to the embodiment is similar to the solid-state image pickup apparatus according to the first embodiment in that its circuits are equivalent to those shown inFIG.12, and differs therefrom in its chip stacking structure. A description of the circuits will hereunder be omitted. The structure shown inFIG.2will hereunder be described. FIG.2is a sectional view of a solid-state image pickup apparatus200corresponding to the circuits shown inFIG.12.FIG.2is a sectional view for two pixels in correspondence with the photoelectric conversion elements303, the transfer transistors304, and the amplification transistors306shown inFIG.12, and does not show the other portions. FIG.2shows a first chip201, a second chip202, and a bonding surface203of the first chip and the second chip. The first chip201corresponds to the first chip308shown inFIG.12, and the second chip202corresponds to the second chip309shown inFIG.12. The first chip201has a first substrate204. A surface of the first substrate204where a transistor is formed is a principal surface205, and a surface thereof opposite thereto is a back surface206. A portion constituting the photoelectric conversion element303and the transfer transistor304shown inFIG.12is disposed at the first substrate204. A multilayer wiring structure207, including a first wiring layer222and a second wiring layer223, which, for example, have aluminum wires, is provided on an upper portion at the principal surface205of the first substrate204. Here, a plurality of interlayer insulating films of the multilayer wiring structure207are described as an integral insulating film. The second chip202has a second substrate208. A surface of the second substrate208where a transistor is formed is a principal surface209, and a surface thereof opposite thereto is a back surface210. A multilayer wiring structure211, including a first wiring layer228and a second wiring layer229, which, for example, have aluminum wires, is provided on an upper portion of the principal surface209of the second substrate208. Even here, a plurality of interlayer insulating films of the multilayer wiring structure211are described as an integral insulating film. An amplification transistor306shown inFIG.12is disposed at the second substrate208. Here, in the solid-state image pickup apparatus according to the embodiment, the principal surface205of the first substrate204and the back surface210of the second substrate208are placed upon each other so as to face each other. InFIG.2, in a structure of a connection portion of the first chip201and the second chip202, a connection between an FD region213of the first chip201and a gate electrode226of an amplification transistor of the second chip202is only shown. More specifically, the FD region213of the first chip201is connected to the gate electrode226of the amplification transistor through the multilayer wiring structure207, a connection portion311, and the multilayer wiring structure211. Here, a through electrode235constituting a portion of the connection portion311and penetrating the second substrate208is disposed. By the through electrode, the FD region213and the gate electrode226of the amplification transistor are connected to each other. The connection portion310shown inFIG.12that supplies a control signal to the gate electrode214of the transfer transistor is not shown inFIG.2. The solid-state image pickup apparatus according to the embodiment is a backside-illumination solid-state image pickup apparatus upon which light is incident from the back surface206of the first substrate204. Next, each chip will be described in detail. A well215, an N-type charge storage region212, constituting the photoelectric conversion element, and the gate electrode214of the transfer transistor are disposed at the first substrate204of the first chip201. Further, a P-type semiconductor region216, an element isolation region217, and the drain region213of the transfer transistor are disposed at the first substrate204. A back-surface-206-side of the first substrate204of the first chip201is provided with an antireflection film218, a light-shielding film219, a color filter layer220including a planarizing layer, and a microlens121. Next, a well224, a source region and drain region225, and the gate electrode226of the amplification transistor306inFIG.12, and an element isolation region227are disposed at the second substrate208of the second chip202. In addition, the first wiring layer228and the second wiring layer229are provided at the upper portion of the second substrate208, and an insulating layer234is provided at a deepest portion of the second substrate208. The structures of the first chip201and the second chip202are similar to those of the first embodiment, so that they will not be described below. In the second embodiment, an adhesive layer232and a supporting base233are further provided at the upper portion of the second chip202. The insulating layer, the adhesive layer232, and the supporting base233in the second embodiment will be described later. Here, the source region and drain region225and the gate electrode226of the transistor (the amplification transistor306shown inFIG.12) disposed at the second chip202of the solid-state image pickup apparatus according to the embodiment have high-melting-metal compound layers230. A region constituting the peripheral circuit portion302shown inFIG.12, disposed at the second chip202, is also similarly provided with a transistor including a high-melting-metal compound layer (not shown). The high-melting-metal compound layer is, for example, silicide using cobalt or titanium, which is a high-melting metal, when silicon is used in the semiconductor substrate. The transistor of, for example, the peripheral circuit portion disposed at the second substrate has a high-melting-metal compound layer, so that it is possible to increase the speed of operation of the transistor. In addition, by providing the transistor including such a high-melting-metal compound layer only at the second chip202, it is possible to reduce mixing of the high-melting metal into the photoelectric conversion element, while suppressing a reduction in the characteristics of the photoelectric conversion element of the first chip201. Since it is not necessary to form a region where a high-melting-metal compound layer is to be provided and a region where a high-melting-metal compound layer is not to be provided on the same substrate, it is not necessary to form, for example, a protective film to prevent the formation of a high-melting-metal compound layer, that is, it is possible for each substrate to have a simple structure and to manufacture it using a simple step. Third Embodiment A solid-state image pickup apparatus according to this embodiment will be described with reference toFIG.3. The solid-state image pickup apparatus according to the embodiment corresponds to the solid-state image pickup apparatus100according to the first embodiment, and differs therefrom in that it includes a diffusion prevention film. The structure shown inFIG.3will hereunder be described. The structural features that are equivalent to those of the first embodiment will not be described. In a solid-state image pickup apparatus400shown inFIG.3, a diffusion prevention film131is disposed between a first chip101and a second chip102. By providing such a diffusion prevention film131, it is possible to suppress diffusion of a high-melting metal of a high-melting-metal compound layer disposed at the second chip into multilayer wiring structures111and107and mixture of the high-melting metal into a semiconductor region constituting an FD region and a photoelectric conversion element of the first chip. Therefore, it is possible to further suppress generation of leakage current causing a white defect (of an image) or a dark current to be produced when the high-melting metal is mixed into the semiconductor region. A method of producing the solid-state image pickup apparatus400shown inFIG.3will be described with reference toFIGS.4A and4B and5A and5B. First, inFIG.4A, a photo-diode formation member (hereunder referred to as “PD formation member”)401, which becomes a first substrate104shown inFIG.3, and a circuit formation member402, which becomes a second substrate108shown inFIG.3, are provided. These members are, for example, silicon semiconductor substrates, and may be of any conductivity type. The PD formation member401includes a p-type semiconductor region116and an insulating layer403. The PD formation member401uses an SOI substrate, and the p-type semiconductor region116may be formed by epitaxial growth or ion implantation. Next, as shown inFIG.4B, elements such as a gate electrode114of a transfer transistor and a charge storage region112are formed at the PD formation member401. The multilayer wiring structure107is formed on the upper portion of the PD formation member401. The multilayer wiring structure107has a first wiring layer122and a second wiring layer123. The first wiring layer122and the second wiring layer123include a plurality of wires. The wires in the embodiment are aluminum wires. The multilayer wiring structure107has an interlayer insulating film for insulating the wires from each other. For example, the interlayer insulating film is disposed between the first wiring layer122and the gate electrode of the transfer transistor, and between the first wiring layer122and the second wiring layer123. For forming the multilayer wiring structure107, a general semiconductor process may be used. Finally, an interlayer insulating film covering the second wiring layer is formed, and portions thereof are removed so that some wires of the second wiring layer123are exposed. The exposed second wiring layer123constitute a connection portion311. A surface of the PD formation member401where the gate electrode of the transfer transistor is formed becomes a principal surface105of the first substrate described later. InFIG.4B, a well124and a peripheral circuit portion including a transistor such as an amplification transistor306are formed at the circuit formation member402. Then, a high-melting metal is deposited on predetermined positions, such as a source region, a drain region125, and a gate electrode126of the transistor, and heat treatment is performed, thereby forming a high-melting-metal compound layer130. Thereafter, a multilayer wiring structure111is formed at the upper portion of the circuit formation member402. The multilayer wiring structure111has a first wiring layer128and a second wiring layer129. The structure and production method of the multilayer wiring structure111are similar to those of the multilayer wiring structure107of the PD formation member401. Next, after forming the second wiring layer129, a diffusion prevention film131covering the second wiring layer129is formed. The diffusion prevention film131is formed of, for example, silicon nitride or silicon carbide. The diffusion prevention film131is for suppressing diffusion to the high-melting metal PD formation member401. Thereafter, portions of the diffusion prevention film131are removed so that some wires of the second wiring layer129constituting the connection portion311are exposed. Here, the diffusion prevention film may be removed by etching or CMP technology. Here, the circuit formation member402becomes the second substrate108. A principal surface109of the second substrate108is determined as shown inFIG.4B. Next, as shown inFIG.5A, the principal surfaces (105,109) of the PD formation member401and the circuit formation member402are disposed so as to face each other, and are joined to each other by, for example, a micro-bump. Finally, as shown inFIG.5B, an undesired portion404and the insulating layer403of the PD formation member401are removed by, for example, CMP or etching, so that the PD formation member401is made thinner, to form the first substrate104. Thereafter, an antireflection film118, formed of silicon carbide, is formed at the upper portion of a back surface106of the first substrate104. After forming the antireflection film118, a tungsten film is formed at the upper portion of the antireflection film118for patterning, thereby forming a light-shielding film119. Thereafter, a planarizing layer and a color filter120are formed, and a microlens121is formed. Such a production method makes it possible to produce the solid-state image pickup apparatus400shown inFIG.3. Here, according to the structure of the embodiment, after forming the interlayer insulating film of the multilayer wiring structure107, it is possible to perform heat treatment at a high-temperature or for a long time for improving characteristics such as recovery from defects of the photoelectric conversion element. If the first substrate is provided with a high-melting-metal compound layer, a high-melting metal semiconductor compound layer is formed before forming the interlayer insulating film. After forming the interlayer insulating film, it becomes difficult to perform heat treatment at a high temperature or for a long time due to problems such as diffusion of the high-melting metal. Therefore, according to the structure of the embodiment, since heat treatment for recovering from defects of the photoelectric conversion element may be optionally performed, it is possible to suppress a reduction in the characteristics of the photoelectric conversion element. In a desirable form, for increasing connection resistance of a contact provided at an FD region, it is desirable to perform ion implantation and heat treatment on the semiconductor region that is connected to a plug. However, as mentioned above, if the first substrate is provided with a high-melting-metal compound layer, it becomes difficult to perform heat treatment in a contact formation step that is carried out after forming the interlayer insulating film. Therefore, according to the structure of the embodiment, it is possible to perform sufficient heat treatment in the step of forming the contact at the FD region where the high-melting-metal compound layer is not provided while the high-melting-metal compound layer is provided at the peripheral circuit portion. Therefore, it is possible to properly connect the contact at the FD region while reducing contamination of the high-melting metal at the FD region. As discussed above, according to the solid-state image pickup apparatus of the embodiment, it is possible to further suppress generation of dark current at the photoelectric conversion element while increasing the speed of operation of the transistor at the peripheral circuit portion and increasing the speed of a signal readout operation. Fourth Embodiment A solid-state image pickup apparatus according to this embodiment will be described with reference toFIG.6. The structure of the solid-state image pickup apparatus according to this embodiment corresponds to the structure of the solid-state image pickup apparatus according to the second embodiment, and differs therefrom in that it includes a diffusion prevention film. The structure shown inFIG.6will hereunder be described. The structural features that are equivalent to those of the second embodiment will not be described. In a solid-state image pickup apparatus500shown inFIG.6, a diffusion prevention film231, which prevents diffusion of a high-melting metal, is disposed between a first chip201and a second chip202. By providing such a diffusion prevention film231, it is possible to further suppress mixing of a high-melting metal of a high-melting-metal compound layer disposed at the second chip into a semiconductor region constituting an FD region and a photoelectric conversion element of the first chip. Therefore, it is possible to suppress production of a white defect (of an image) or a dark current. The diffusion prevention film231is a film formed of, for example, silicon nitride or silicon carbide. Next, a method of producing the solid-state image pickup apparatus500shown inFIG.6will be described with reference toFIGS.7A to9. First, inFIG.7A, a photo-diode formation substrate (hereunder referred to as “PD formation member”)501, which becomes a first substrate204shown inFIG.6, and a circuit formation member502, which becomes a second substrate208shown inFIG.6, are provided. The PD formation member501includes a p-type semiconductor region216and an insulating layer503. The PD formation member501uses an SOI substrate, and the p-type semiconductor region216may be formed by epitaxial growth or ion implantation. The circuit formation member502uses an SOT substrate and includes an insulating layer234. Next, in the PD formation member501shown inFIG.7B, elements such as a gate electrode214of a transfer transistor, a charge storage region212, and a well215are formed. A multilayer wiring structure207is formed on the upper portion of the PD formation member501. The multilayer wiring structure207includes a first wiring layer222and a second wiring layer223. The structure and production method of the multilayer wiring structure207are similar to those of the third embodiment, so that they will not be described. Next, an interlayer insulating film covering the second wiring layer223is formed, and portions of the interlayer insulating film are removed so that wires of the second wiring layer223are exposed. The second wiring layer223constitutes a connection portion311. Then, a diffusion prevention film231covering the second wiring layer223and formed of, for example, silicon nitride or silicon carbide is formed. The interlayer insulating film covering the second wiring layer233may be disposed between the second wiring layer223and the diffusion prevention film231. In the circuit formation member502shown inFIG.7B, a transistor including an amplification transistor and a well224are formed. Then, a high-melting metal is deposited on predetermined positions, such as a source region, a drain region, and a gate electrode of the transistor, and heat treatment is performed, thereby forming a high-melting-metal compound layer230. Thereafter, a multilayer wiring structure211is formed on the upper portion of the circuit formation member502. The multilayer wiring structure211has a first wiring layer228. The structure and production method of the first wiring layer228are similar to those of the third embodiment. Next, inFIG.8A, an adhesive layer506and a supporting base507are formed at the upper portion of the first wiring layer228at the circuit formation member502. Then, an undesired portion504of the circuit formation member502is removed by abrasion or etching, and the second substrate208is formed. InFIG.8B, a principal surface205of the PD formation member501, which becomes the first substrate204shown inFIG.6, and a back surface210of the second substrate208are placed upon each other so as to face each other, and are joined together by, for example, a micro-bump. Then, the first adhesive layer506and the first supporting base507are removed. Thereafter, an interlayer insulating film is formed on the upper portion of the first wiring layer228at the second substrate208, and a through electrode235for electrical connection with the first substrate204is formed. The through electrode235may be produced by a general semiconductor process. Then, the through electrode235is covered, and the second wiring layer229is formed. Next, as shown inFIG.9, an adhesive layer232and a supporting base233are provided on the upper portion of the second wiring layer229at the second substrate208. Then, an undesired portion505at the PD formation member501is removed by, for example, CMP or etching, and the first substrate204is formed. Thereafter, an antireflection film218, formed of, for example, silicon nitride, is formed at the upper portion of a back surface206of the first substrate204. Then, a light-shielding film219, formed of, for example, tungsten, is formed at the upper portion of the antireflection film218. Further, a planarizing layer and a color filter120are formed at the upper portion of the light-shielding film219, and a microlens121is formed. Such a production method makes it possible to produce the solid-state image pickup apparatus500shown inFIG.6. Even in the structure according to the embodiment, since heat treatment of a contact or a photoelectric conversion element can be optionally performed, it is possible to suppress a reduction in the characteristics of the photoelectric conversion element and an increase in the connection resistance of the contact. As discussed above, according to the solid-state image pickup apparatus of the embodiment, it is possible to further suppress generation of dark current at the photoelectric conversion element while increasing the speed of operation of the transistor at the peripheral circuit portion and increasing the speed of a signal readout operation. Fifth Embodiment A solid-state image pickup apparatus according to this embodiment will be described with reference toFIGS.10A to10C. The structures of solid-state image pickup apparatuses600,610, and620according to the embodiment shown inFIGS.10A to10Ccorrespond to the structure of the solid-state image pickup apparatus400according to the third embodiment, with the disposition of the diffusion prevention film131being modified. The structural features that are equivalent to those of the third embodiment will not be described below. In the solid-state image pickup apparatus600shown inFIG.10A, the diffusion prevention film131is disposed between a first substrate104and a second substrate108, and serves as an interlayer insulating film included in a multilayer wiring structure107disposed at the upper portion of the first substrate104. By virtue of such a structure, it is possible to omit the step of forming an interlayer insulating film, and to make the solid-state image pickup apparatus thin. In addition, since the solid-state image pickup apparatus600is a backside-illumination solid-state image pickup apparatus, even if the diffusion prevention film131, formed of, for example, silicon nitride, is provided on the entire top surface of a photoelectric conversion element, for example, reflection resulting from the difference between the refractive indices of the diffusion prevention film131and a silicon oxide film, which is a general interlayer insulating film, does not occur. Therefore, it is possible to suppress diffusion of a high-melting metal from the second substrate108while suppressing a reduction in the optical characteristics. The structure in which the diffusion prevention film131serves as an interlayer insulating film is not limited to the structure shown inFIG.10A. For example, an interlayer insulating film in a multilayer wiring structure111disposed at the upper portion of the second substrate108may be used. Next, in the solid-state image pickup apparatus610shown inFIG.10B, the diffusion prevention film131is disposed between a first substrate104and a second substrate108. In addition, the diffusion prevention film131is formed so as to contact a high-melting-metal compound layer130on a source region and drain region125and a gate electrode126at the second substrate108. By virtue of such a structure, it is possible to use the diffusion prevention film131as an etching stop layer when forming a contact hole of the second substrate108. Next, in the solid-state image pickup apparatus620shown inFIG.10C, the diffusion prevention film131is disposed between a first substrate104and a second substrate108, and contacts the upper portion of a first wiring layer228at the second substrate108. The first wiring layer228is formed of copper wires. The diffusion prevention film131also functions as a diffusion prevention film, which prevents diffusion of copper. By virtue of such a structure, it is possible to omit the step of forming the diffusion prevention film, which prevents diffusion of copper, and to make the solid-state image pickup apparatus thin. The structure in which the diffusion prevention film131serves as a diffusion prevention film, which prevents diffusion of copper, is not limited to the structure shown inFIG.10C. For example, a multilayer wiring structure107disposed on the upper portion of the first substrate104may be formed of copper wires, and the diffusion prevention film131may be formed for each wiring layer. Sixth Embodiment A solid-state image pickup apparatus according to this embodiment will be described with reference toFIGS.11A to11C. The structures of solid-state image pickup apparatuses700,710, and720according to the embodiment shown inFIGS.11A to11Ccorrespond to the structure of the solid-state image pickup apparatus500according to the fourth embodiment, with the disposition of the diffusion prevention film231being modified. The structural features that are equivalent to those of the fourth embodiment will not be described below. In the solid-state image pickup apparatus700shown inFIG.11A, the diffusion prevention film231is disposed between a first substrate204and a second substrate208, and serves as an interlayer insulating film included in a multilayer wiring structure207disposed at the upper portion of the first substrate104. By virtue of such a structure, it is possible to omit the step of forming an interlayer insulating film, and to make the solid-state image pickup apparatus thin. In addition, the solid-state image pickup apparatus700is a backside-illumination solid-state image pickup apparatus. Therefore, even if the diffusion prevention film231, formed of, for example, silicon nitride, is provided on the entire top surface of a photoelectric conversion element, it is not necessary to consider reflection of incident light resulting from the difference between the refractive indices of the diffusion prevention film231and a silicon oxide film, which is a general interlayer insulating film. Therefore, it is possible to suppress diffusion of a high-melting metal from the second substrate208. In the solid-state image pickup apparatus710shown inFIG.11B, the diffusion prevention film231is disposed between a first substrate204and a second substrate208, and contacts the upper portion of a first wiring layer222at the first substrate208. The first wiring layer222is formed of copper wires. The diffusion prevention film231also functions as a diffusion prevention film, which prevents diffusion of copper. By virtue of such a structure, it is possible to omit the step of forming the diffusion prevention film, which prevents diffusion of copper, and to make the solid-state image pickup apparatus thin. The structure in which the diffusion prevention film231serves as a diffusion prevention film, which prevents diffusion of copper, is not limited to the structure shown inFIG.11B. For example, as shown inFIG.11C, of portions of a multilayer wiring structure207disposed at the upper portion of the first substrate204, the second wiring layer223may be formed of copper wires, and the diffusion prevention film231may be disposed on the upper portion of the second wiring layer223. Here, the diffusion prevention film231may be disposed at the upper portion of the first wiring layer222. In order to reduce the capacity between the wiring layers, it is possible to perform patterning of a diffusion prevention film, which prevents diffusion of copper, in accordance with the forms of the wires at the upper portion of the first wiring layer222, and remove a portion thereof. As shown inFIG.11C, a multilayer wiring structure211, disposed on the upper portion of a second substrate208, may be formed of copper wires, and may include a copper diffusion prevention film901. Seventh Embodiment In the embodiment, a case in which a photoelectric conversion apparatus according to the present invention is applied as an image pickup apparatus to an image pickup system is described in detail. The image pickup system may be, for example, a digital still camera or a digital camcorder. A block diagram of a case in which a photoelectric conversion apparatus is applied to a digital still camera, which is an example of the image pickup system, is shown inFIG.13. InFIG.13, reference numeral1denotes a barrier for protecting a lens, reference numeral2denotes a lens where an optical image of an object is formed at an image pickup apparatus4, and reference numeral3denotes an aperture stop for varying the quantity of light transmitted through the lens2. Reference numeral4denotes the image pickup apparatus, which is the solid-state image pickup apparatus described in any of the aforementioned embodiments. The image pickup apparatus4converts the optical image formed by the lens2as image data. Here, an AD converter is disposed at the image pickup apparatus4. More specifically, the AD converter is formed at the second chip. Reference numeral7denotes a signal processing section that performs various corrections and data compression on image pickup data output from the image pickup apparatus4. In addition, inFIG.13, reference numeral8denotes a timing generating section that outputs various timing signals to the image pickup apparatus4and the signal processing section7, and reference numeral9denotes an overall control/operation section that performs various operations and that controls the entire digital still camera. Reference numeral10denotes a memory section that temporarily stores the image data, reference numeral11denotes an interface section for performing a recording operation or a readout operation on a recording medium, and reference numeral12denotes the recording medium that is removable, such as a semiconductor memory for recording or reading out the image pickup data. In addition, reference numeral13denotes an interface section for performing communication with, for example, an external computer. Here, for example, a timing signal may be input from outside the image pickup system, and the image pickup system may include at least the image pickup apparatus4and the signal processing section7that processes an image pickup signal output from the image pickup apparatus. Although, in the embodiment, the case in which the AD converter is provided at the image pickup apparatus4is used, the image pickup apparatus and the AD converter may be provided at different chips. In addition, the signal processing section7, etc. may be provided at the image pickup apparatus4. Since a high-melting-metal compound layer is formed at the second chip of the image pickup apparatus4, signal processing, etc. can be performed at a high speed. Accordingly, the photoelectric conversion apparatus according to the present invention is applicable to an image pickup system. By applying the photoelectric conversion apparatus according to the present invention to an image pickup apparatus, high-speed shooting can be performed. As mentioned above, the solid-state image pickup apparatus according to the present invention makes it possible to provide a solid-state image pickup apparatus that can perform high-speed operations. Further, the diffusion prevention film makes it possible to reduce dark current, and to suppress the production of a white defect in an image. The embodiments are not limited to the described structures, and the embodiments may be combined as required. For example, the solid-state image pickup apparatus may include a plurality of diffusion prevention films, which prevents diffusion of a high-melting metal. The high-melting-metal compound layer may be formed at a portion where an electrical potential is applied to a semiconductor region, such as a well contact, in addition to the source region, the drain region, and the gate electrode of a transistor. According to the present invention, it is possible to provided, by using a simple structure, a solid-state image pickup apparatus in which a high-melting-metal compound layer is disposed at a peripheral circuit portion while a reduction in the characteristics of a photoelectric conversion element is suppressed. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. INDUSTRIAL APPLICABILITY The present invention is applicable to a solid-state image pickup apparatus used in an image pickup system, such as a digital still camera or a digital camcorder. REFERENCE SIGNS LIST 101first chip102second chip103bonding surface104first substrate107multilayer wiring structure108second substrate111multilayer wiring structure112photoelectric conversion element124well125source/drain region126gate electrode of amplification transistor130high-melting-metal compound layer | 46,015 |
11942502 | MODES FOR CARRYING OUT THE INVENTION The following is a description of modes (hereinafter referred to as embodiments) for carrying out the present technology. Note that explanation will be made in the following order. 1. General example configuration of a solid-state imaging device 2. Example pixel circuit configuration of a first embodiment 3. Example cross-section configuration of the first embodiment 4. Manufacturing method according to the first embodiment 5. Example pixel circuit configuration of a second embodiment 6. Example cross-section configuration of the second embodiment 7. Example cross-section configuration of a three-layer stack structure 8. Example applications to electronic apparatuses 9. Example application to an in-vivo information acquisition system 10. Example application to an endoscopic surgery system 11. Example applications to mobile structures <1. General Example Configuration of a Solid-State Imaging Device> FIG.1schematically shows an example configuration of a solid-state imaging device to which present technology is applied. A solid-state imaging device1shown inFIG.1includes a pixel array unit3having pixels2arranged in a two-dimensional array, and a peripheral circuit unit around the pixel array unit3. The peripheral circuit unit includes a vertical drive circuit4, column signal processing circuits5, a horizontal drive circuit6, an output circuit7, a control circuit8, and the like. A pixel2includes a photodiode as a photoelectric conversion element, and pixel transistors. The pixel transistors are a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, for example, and are formed with MOS transistors. The control circuit8receives an input clock and data that designates an operation mode and the like, and also outputs data such as internal information about the solid-state imaging device1. Specifically, on the basis of a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit8generates a clock signal and a control signal that serve as the references for operation of the vertical drive circuit4, the column signal processing circuits5, the horizontal drive circuit6, and the like. The control circuit8then outputs the generated clock signal and control signal to the vertical drive circuit4, the column signal processing circuits5, the horizontal drive circuit6, and the like. The vertical drive circuit4is formed with a shift register, for example, selects a predetermined pixel drive line10, supplies the selected pixel drive line10with a pulse for driving the pixels2, and drives the pixels2on a row-by-row basis. Specifically, the vertical drive circuit4sequentially selects and scans the respective pixels2of the pixel array unit3on a row-by-row basis in the vertical direction, and supplies pixel signals based on signal charges generated in accordance with the amounts of light received in the photoelectric conversion portions of the respective pixels2, to the column signal processing circuits5through vertical signal lines9. The column signal processing circuits5are provided for the respective columns of the pixels2, and performs signal processing such as denoising, on a column-by-column basis, on signals that are output from the pixels2of one row. For example, the column signal processing circuits5perform signal processing such as correlated double sampling (CDS) for removing fixed pattern noise inherent to pixels and AD conversion. The horizontal drive circuit6is formed with a shift register, for example, sequentially selects the respective column signal processing circuits5by sequentially outputting horizontal scan pulses, and causes the respective column signal processing circuits5to output pixel signals to a horizontal signal line11. The output circuit7performs signal processing on signals sequentially supplied from the respective column signal processing circuits5through the horizontal signal line11, and outputs the processed signals. The output circuit7might perform only buffering in some cases, or might perform black level control, column variation correction, various kinds of digital signal processing, and the like in other cases, for example. An input/output terminal13exchanges signals with the outside. The solid-state imaging device1having the configuration as above is a so-called column AD-type CMOS image sensor in which the column signal processing circuits5that perform CDS and AD conversion are provided for the respective pixel columns. <2. Example Pixel Circuit Configuration of a First Embodiment> FIG.2shows an example circuit configuration of a first embodiment of each pixel2shown inFIG.1. A pixel2includes a photodiode PD as a photoelectric conversion element, a first transfer transistor Tr1, a second transfer transistor Tr2, a reset transistor Tr3, an amplification transistor Tr4, a selection transistor Tr5, a drain transistor Tr6, and a memory portion MEM. The photodiode PD is a photoelectric conversion portion that generates and stores electric charges (signal charges) depending on the amount of received light. The anode terminal of the photodiode21is grounded, and the cathode terminal is connected to the memory portion MEM via the first transfer transistor Tr1and the second transfer transistor Tr2. The cathode terminal of the photodiode21is also connected to the drain transistor Tr6. When turned on by a transfer signal TRG1, the first transfer transistor Tr1reads out the electric charges generated by the photodiode PD, and transfers the electric charges to the second transfer transistor Tr2. When turned on by a transfer signal TRG2, the second transfer transistor Tr2transfers the electric charges transferred from the first transfer transistor Tr1to the memory portion MEM. The memory portion MEM is a charge retention portion that temporarily retains the electric charges transferred from the photodiode PD, until outputting the electric charges via a vertical signal line9. A control potential TRG3that performs control to completely transfer the electric charges from the photodiode PD is applied to a second electrode on the opposite side of the memory portion MEM from a first electrode connected to the drain of the second transfer transistor Tr2and the gate of the amplification transistor Tr4. Note that, as the memory portion MEM, it is preferable to use the capacitance of a metal-insulator-metal (MIM) structure that is a capacitor with a small leak current (dark current) per unit area, the capacitance of a polysilicon-insulator-polysilicon (PIP) structure, or the capacitance of a metal oxide semiconductor (MOS) structure. With this arrangement, the resistance to noise is improved, and a high-quality signal can be obtained. When turned on by a reset signal RST, the reset transistor Tr3causes draining of the electric charges retained in the memory portion MEM to a power-supply voltage VDD, to reset the potential of the memory portion MEM. The amplification transistor Tr4outputs a pixel signal corresponding to the potential of the memory portion MEM. Specifically, the amplification transistor Tr4forms a source follower circuit with a load MOS (not shown) as a constant-current source, and a pixel signal indicating the level corresponding to the electric charges retained in the memory portion MEM is output from the amplification transistor Tr4to the column signal processing circuit5(FIG.1) via the selection transistor Tr5. The load MOS is disposed in the column signal processing circuit5, for example. The selection transistor Tr5is turned on when the pixel2is selected by a selection signal SEL, and outputs the pixel signal of the pixel2to the column signal processing circuit5via the vertical signal line9. When turned on by a drain signal PDRST, the drain transistor Tr6drains the unnecessary electric charges stored in the photodiode PD to the power-supply voltage VDD. The transfer signals TRG1and TRG2, the reset signal RST, the selection signal SEL, and the drain signal PDRST are controlled by the vertical drive circuit4, and are supplied via the pixel drive line10(FIG.1). Operation of the pixel2is now briefly described. First, before the exposure is started, a high-level drain signal PDRST is supplied to the drain transistor Tr6, to turn on the drain transistor Tr6. As a result, the electric charges stored in the photodiode PD are drained to the power-supply voltage VDD, and thus, the photodiode PD is reset. After the photodiode PD is reset, the drain transistor Tr6is turned off by a low-level drain signal PDRST, so that exposure is started in all the pixels. Next, a high-level reset signal RST is supplied to the reset transistor Tr3. As a result, the electric charges retained in the memory portion MEM are drained to the power-supply voltage VDD, and thus, the potential of the memory portion MEM is reset. After a predetermined exposure time has passed, the first transfer transistor Tr1is turned on by a high-level transfer signal TRG1, and the second transfer transistor Tr2is turned on by a high-level transfer signal TRG2in all the pixels of the pixel array unit3. As a result, the electric charges stored in the photodiode21are transferred to the memory portion MEM. After the first transfer transistor Tr1is turned off, the electric charges retained in the memory portion MEM of each pixel2are sequentially read out to the column signal processing circuits5row by row. In the read operation, the selection transistor Tr5is turned on by a high-level selection signal SEL, so that the pixel signal indicating the level corresponding to the electric charges retained in the memory portion MEM is transmitted from the amplification transistor Tr4to the column signal processing circuit5vis the selection transistor Tr5. As described above, the circuit of the pixel2shown inFIG.2is a circuit that performs a global shutter operation (imaging) in which the same exposure time is set in all the pixels of the pixel array unit3, and electric charges temporarily retained in the memory portions MEM after the end of the exposure are sequentially read from the memory portions MEM row by row. As will be described later with reference toFIG.3and others, the solid-state imaging device1shown inFIG.1is formed by bonding two semiconductor substrates. The dashed line inFIG.2indicates the joining surfaces of the two semiconductor substrates. <3. Example Cross-Section Configuration of the First Embodiment> FIG.3is a cross-sectional view of the pixel2according to the first embodiment shown inFIG.2. The circuit of the pixel2shown inFIG.2is formed by stacking a first semiconductor substrate41and a second semiconductor substrate71, as shown inFIG.3. An on-chip lens42is formed for each pixel on the light incidence face side of the first semiconductor substrate41, which is the upper side inFIG.3, and a wiring layer43is formed on the opposite side of the first semiconductor substrate41from the light incidence face side. Note that, in addition to the on-chip lens42, an inter-pixel light blocking film, a color filter, an antireflection film, a planarizing film, and the like may be further formed on the upper surface of the first semiconductor substrate41on the light incidence face side. In the first semiconductor substrate41, an n-type semiconductor region52is formed in a predetermined region within a p-type semiconductor region (p-well)51, so that a photodiode PD is formed for each pixel. The wiring layer43formed on the first semiconductor substrate41on the side of the second semiconductor substrate71includes insulating layers53and54, and metallic wiring lines M1through M6. The metallic wiring lines M1through M3, M5, and M6formed in the insulating layer53are wiring lines that transmit the transfer signal TRG1, the drain signal PDRST, the power-supply voltage VDD, a pixel signal, and the like, and the metallic wiring line M4is a light blocking film designed to prevent incident light from entering the side of the second semiconductor substrate71. As a light blocking film is formed with the metallic wiring line M4at a position below the photodiode PD on the opposite side from the light incidence face side, it is possible to prevent incident light from leaking into the second semiconductor substrate71. The first transfer transistor Tr1and the drain transistor Tr6are formed in the interface under the first semiconductor substrate41adjacent to the photodiode PD. The first transfer transistor Tr1includes a gate electrode G1including polysilicon, and an n-type impurity region55. The n-type impurity region55is a floating diffusion (FD) portion in an electrically floating state. The drain transistor Tr6includes a gate electrode G6including polysilicon, and an n-type impurity region56. Note that, although not shown in the drawing, a gate insulating film is formed between the first semiconductor substrate41and the gate electrodes G1and G6. An insulating layer72is formed on the second semiconductor substrate71on the side of the first semiconductor substrate41, and the insulating layer54of the first semiconductor substrate41and the insulating layer72of the second semiconductor substrate71are joined to each other by plasma bonding, for example. A dashed line L1between the insulating layer54and the insulating layer72corresponds to the substrate junction plane shown inFIG.2. A multilayer wiring layer73including three insulating layers81through83, metallic wiring lines M11through M16, and metallic wiring lines M21through M28is formed on the surface of the second semiconductor substrate71on the opposite side from the first semiconductor substrate41. The second transfer transistor Tr2, the memory portion MEM, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5are formed in the interface of the second semiconductor substrate71on the side of the multilayer wiring layer73. Further, a p-type semiconductor region84, and n-type semiconductor regions85through89that form, for example, the source/drain regions of the pixel transistors are formed in the second semiconductor substrate71. The second transfer transistor Tr2includes a gate electrode G2including polysilicon, and n-type impurity regions85and86as source/drain regions. The transfer signal TRG2is applied to the gate electrode G2of the second transfer transistor Tr2via the metallic wiring line M12, a via wiring line94, and the metallic wiring line M23. The n-type impurity region85of the second transfer transistor Tr2is connected to the metallic wiring line M2on the side of the first semiconductor substrate41, via the metallic wiring line M11, a via wiring line93, a connecting wiring line101, and a through electrode92. The memory portion MEM includes an n-type impurity region86corresponding to the first electrode, and a second electrode Gm including polysilicon. The control potential TRG3is applied to the second electrode Gm of the memory portion MEM via the metallic wiring line M13, a via wiring line95, and the metallic wiring line M24. The reset transistor Tr3includes a gate electrode G3including polysilicon, and n-type impurity regions86and87as source/drain regions. The n-type impurity region86as the source region of the reset transistor Tr3is connected to a gate electrode G4of the amplification transistor Tr4via the metallic wiring line M14. The reset signal RST is applied to the gate electrode G3of the reset transistor Tr3at a location not shown in the drawing. The amplification transistor Tr4includes a gate electrode G4including polysilicon, and n-type impurity regions87and88as source/drain regions. The gate electrode G4is connected to the drain region of the second transfer transistor Tr2and the n-type impurity region86as the source region of the reset transistor Tr3, via the metallic wiring line M14. The power-supply voltage VDD is applied to the n-type impurity region87as the drain region of the amplification transistor Tr4and the drain region of the reset transistor Tr3, at a location not shown in the drawing. The selection transistor Tr5includes a gate electrode G5including polysilicon, and n-type impurity regions88and89as source/drain regions. The selection signal SEL is applied to the gate electrode G5of the selection transistor Tr5via the metallic wiring line M15, a via wiring line96, and the metallic wiring line M25. The n-type impurity region89as the source region of the selection transistor Tr5is connected to the vertical signal line9via the metallic wiring line M16, a via wiring line97, and the metallic wiring line M26. The metallic wiring line M21formed in the insulating layer83is connected to the metallic wiring line M1of the wiring layer43of the first semiconductor substrate41, via a through electrode91. The metallic wiring line M1is connected to the metallic wiring line M3connected to the gate electrode G1of the first transfer transistor Tr1at a position not shown in the drawing, and the transfer signal TRG1is supplied to the gate electrode G1of the first transfer transistor Tr1via the metallic wiring line M21, the through electrode91, the metallic wiring line M1, and the metallic wiring line M3. The metallic wiring line M27formed in the insulating layer83is connected to the metallic wiring line M5of the wiring layer43of the first semiconductor substrate41, via a through electrode98. The drain signal PDRST is supplied to the gate electrode G6of the drain transistor Tr6via the metallic wiring line M27, the through electrode98, and the metallic wiring line M5. The metallic wiring line M28formed in the insulating layer83is connected to the metallic wiring line M6of the wiring layer43of the first semiconductor substrate41, via a through electrode99. The power-supply voltage VDD is supplied to the n-type impurity region56via the metallic wiring line M28, the through electrode99, and the metallic wiring line M6. Note that, although not shown in the drawing, a gate insulating film is formed between the second semiconductor substrate71, and the gate electrodes G2through G5and the second electrode Gm. An n-type impurity region for threshold voltage adjustment may be formed in the interface of the second semiconductor substrate71under the gate insulating film. As shown inFIG.3, the first semiconductor substrate41and the second semiconductor substrate71are electrically connected only by the four through electrodes91,92,98, and99in the pixel region. The material of the metallic wiring lines M1through M6, the metallic wiring lines M11through M16, and the metallic wiring lines M21through M28is tungsten (W), which is a refractory metallic wiring material, for example, but may be some other material such as aluminum (Al), copper (Cu), or gold (Au). The material of the through electrodes91and92, the via wiring lines93through97, and the through electrodes98and99is copper, for example, but some other metallic material may be used. Meanwhile, the insulating layers53and54and the insulating layers81through83are formed with a SiO2 film, a low-k film (a low-dielectric-constant insulating film), a SiOC film, or the like, for example. The materials of the insulating layers53and54and the insulating layers81through83are not necessarily the same. In the pixel2formed as described above, after a predetermined exposure time has passed, the first transfer transistor Tr1is turned on by a high-level transfer signal TRG1, and the second transfer transistor Tr2is turned on by a high-level transfer signal TRG2. As a result, the electric charges stored in the photodiode21are transferred to the n-type impurity region86of the memory portion MEM via the n-type impurity regions55and85that are FD portions. After that, in a read period of the pixel2, the selection transistor Tr5is turned on by a high-level selection signal SEL, and the electric charges stored in the n-type impurity region86of the memory portion MEM are transferred as a pixel signal, via the gate electrode G4of the amplification transistor Tr4, and the selection transistor Tr5. In the pixel structure according to the first embodiment shown inFIG.3, the wiring layer43on the front surface side that is the wiring layer formation surface of the first semiconductor substrate41, and the insulating layer72on the back surface side that is the opposite side from the wiring layer formation surface of the second semiconductor substrate71are joined to each other. At least the photodiode PD that photoelectrically converts incident light, and the first transfer transistor Tr1that transfers electric charges of the photodiode PD are disposed in the first semiconductor substrate41. At least the memory portion MEM as the charge retention portion that retains the electric charges transferred by the first transfer transistor Tr1, and the through electrode92that penetrates the second semiconductor substrate71and serves as a transmission path for transmitting the electric charges transferred from the first transfer transistor Tr1to the memory portion MEM are disposed in the second semiconductor substrate71. Because the memory portion MEM as the charge retention portion that retains electric charges in a global shutter operation is formed in the second semiconductor substrate71different from the first semiconductor substrate41in which the photodiode PD that is a photoelectric conversion portion is formed, a sufficiently large photoelectric conversion region can be secured in the first semiconductor substrate41. Furthermore, because the metallic wiring line M4as a light blocking film is disposed in the wiring layer43between the first semiconductor substrate41and the second semiconductor substrate71, it is possible to prevent incident light from leaking into the memory portion MEM, and enhance the PLS characteristics. <4. Manufacturing Method According to the First Embodiment> Referring now toFIGS.4through7, a manufacturing method according to the first embodiment is described. First, as shown in A ofFIG.4, the photodiode PD, the first semiconductor substrate41on which the wiring layer43including the first transfer transistor Tr1, the drain transistor Tr6, and the like is formed, and the second semiconductor substrate71temporarily bonded to a support substrate121are prepared. The first semiconductor substrate41in A ofFIG.4is in a state before having its thickness reduced to the thickness shown inFIG.3. The insulating layer72is formed on one surface of the second semiconductor substrate71, and polysilicon123is formed on the entire other surface of the second semiconductor substrate71. The support substrate121is temporarily bonded to the surface of the second semiconductor substrate71on which the polysilicon123is formed, via an insulating layer122. As shown in B ofFIG.4, the wiring layer43of the first semiconductor substrate41and the insulating layer72of the second semiconductor substrate71are joined to each other by plasma bonding, for example, and the support substrate121temporarily bonded to the second semiconductor substrate71is then peeled off. After the support substrate121is peeled off, the polysilicon123formed on an entire surface of the second semiconductor substrate71is exposed. The surface on which the polysilicon123is formed is the front surface of the second semiconductor substrate71. In the plasma bonding, a film such as a plasma TEOS film, a plasma SiN film, a SiON film (a block film), or a SiC film is formed on each of the joining surfaces of the first semiconductor substrate41and the second semiconductor substrate71, and the joining surfaces are brought into contact with each other through a plasma treatment. After that, an annealing treatment is performed, to join the two joining surfaces to each other. Instead of the plasma bonding, bonding may be performed with an adhesive. Next, as shown in A ofFIG.5, ions of an n-type impurity such as phosphorus (P) or arsenic (As) are injected into a predetermined region in the vicinity of the front surface of the second semiconductor substrate71of the p-type, for example, so that the n-type impurity regions85through89are formed. Also, patterning is performed on the polysilicon123, so that the second transfer transistor Tr2, the memory portion MEM, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5are formed. Next, as shown in B ofFIG.5, the insulating layer81, the metallic wiring lines M11through M16, and the insulating layer82are formed on the upper surface of the second semiconductor substrate71in which pixel transistors such as the second transfer transistor Tr2are formed. The material of the metallic wiring lines M11through M16formed in the insulating layer81is tungsten, for example. Next, as shown in A ofFIG.6, through connecting holes131through134penetrating the second semiconductor substrate71to reach the metallic wiring line M1, M2, M5, or M6of the first semiconductor substrate41, and connecting holes141through145reaching the metallic wiring line M11, M12, M13, M15, or M16formed in the insulating layer81are formed by dry etching or the like. The opening sizes of the through connecting holes131through134and the connecting holes141through145are tapered so as to be the largest in the uppermost surface, and be the smallest in the deepest portion that is the bottom surface. The cross-sectional diameters of the through connecting holes131through134in the junction plane L1are smaller than or the same as the cross-sectional diameters of the portions penetrating the second semiconductor substrate71. Further, comparisons between the opening sizes of the through connecting holes131through134and the opening sizes of the connecting holes141through145show that the opening sizes of the through connecting holes131through134penetrating the second semiconductor substrate71are the larger. Next, as shown in B ofFIG.6, an insulating layer83A that is part of the insulating layer83is formed, and copper (Cu) as a connecting conductor is buried in the through connecting holes131through134and the connecting holes141through145formed in the step illustrated in A ofFIG.6, and in a predetermined region of the insulating layer83A on the through connecting holes131through134and the connecting holes141through145, so that the through electrodes91and92, the via wiring lines93through97, the through electrodes98and99, the connecting wiring line101in the same layer as the insulating layer83A, and the like are formed. Note that the connecting conductors buried in the through connecting holes131through134and the connecting holes141through145may be tungsten (W), polysilicon, or the like, instead of copper. Further, before burying the connecting conductor, an insulating film for insulating the connecting conductor from the second semiconductor substrate71is formed on the inner wall surfaces of the through connecting holes131through134. Next, as shown in A ofFIG.7, an insulating layer83B and the metallic wiring lines M21through M28are formed on the upper surface of the insulating layer83A, so that the multilayer wiring layer73is completed. The insulating layers83A and83B correspond to the insulating layer83shown inFIG.3. The material of the metallic wiring lines M21through M28formed in the insulating layer83B is tungsten, for example. After the multilayer wiring layer73is formed, the first semiconductor substrate41and the second semiconductor substrate71joined to each other are collectively reversed. As shown in B ofFIG.7, the thickness of the first semiconductor substrate41is then reduced so that the photodiode PD is located closer to the interface, and the on-chip lens42is formed. Thus, the state shown inFIG.3is created. As described above, it is possible to manufacture the pixel structure shown inFIG.3by: forming the photodiode PD that photoelectrically converts incident light and the first transfer transistor Tr1that transfers the electric charges of the photodiode PD in the first semiconductor substrate41; bonding the front surface side, which is the wiring layer formation surface of the first semiconductor substrate41, to the back surface side, which is the opposite side from the wiring layer formation surface of the second semiconductor substrate71; forming the memory portion MEM that retains the electric charges transferred by the first transfer transistor Tr1in the bonded second semiconductor substrate71; and forming the through electrode92that penetrates the second semiconductor substrate71, and transmits the electric charges transferred from the first transfer transistor Tr1to the memory portion MEM. According to the manufacturing method described above, as shown in A ofFIG.8, after the wiring layer43of the first semiconductor substrate41and the insulating layer72of the second semiconductor substrate71are joined to each other by plasma bonding, for example, the second transfer transistor Tr2, the memory portion MEM, the reset transistor Tr3, the amplification transistor Tr4, and the selection transistor Tr5are formed on the upper surface (front surface) of the second semiconductor substrate71. The formation of the n-type impurity regions85through89in the second semiconductor substrate71and the patterning of the polysilicon123are performed through high-precision position control, with the reference being the alignment mark formed in the bonded first semiconductor substrate41. Thus, the positional deviation from the position designed for an element formed in the first semiconductor substrate41can be restricted to 0.1 μm or less with precision. On the other hand, in a case where the first semiconductor substrate41and the second semiconductor substrate71are bonded to each other after the pixel transistors are formed in the second semiconductor substrate71, as shown in B ofFIG.8, there is a deviation of several μm from the designed position, for example. Therefore, with the pixel structure and the manufacturing method described above, there is no need to secure the tolerance assumed on the basis of the variation in the bonding position of the first semiconductor substrate41and the second semiconductor substrate71, and thus, the elements can be miniaturized. In other words, with the pixel structure and the manufacturing method according to the present technology, it is possible to provide a pixel structure and a manufacturing method that are compatible with miniaturization of pixels. <5. Example Pixel Circuit Configuration of a Second Embodiment> FIG.9shows an example circuit configuration of a second embodiment of each pixel2shown inFIG.1. A pixel2includes a photodiode PD as a photoelectric conversion element, a transfer transistor Tr11, a reset transistor Tr12, a first amplification transistor Tr13, a selection transistor Tr14, a sample-and-hold transistor Tr15, a clamp transistor Tr16, a second amplification transistor Tr17, a load transistor Tr18, a first charge retention portion161, and a second charge retention portion162. A dashed line inFIG.9indicates the junction plane between two semiconductor substrates, as in the first embodiment. The photodiode PD is a photoelectric conversion portion that generates and stores electric charges (signal charges) depending on the amount of received light. The transfer transistor Tr11transfers a photoelectric conversion signal stored in the photodiode PD to the gate terminal of the first amplification transistor Tr13, in accordance with a transfer signal TRG. At this point of time, the photoelectric conversion signal transferred by the transfer transistor Tr11is stored into a node capacitance FD. The node capacitance FD is a capacitance accompanying a node connected to the gate terminal of the first amplification transistor Tr13. The first amplification transistor Tr13is a charge-voltage conversion portion that converts the electric charges stored in the node capacitance FD into a signal voltage, and outputs the converted signal voltage to the first charge retention portion161. The reset transistor Tr12resets the photoelectric conversion signal in the pixel to a power-supply voltage VDD, in accordance with a reset signal RST. The load transistor Tr18operates as a load of the first amplification transistor Tr13that outputs a signal voltage, in accordance with a bias signal BIAS. The load transistor Tr18supplies the first amplification transistor Tr13with a current for driving the first amplification transistor Tr13that outputs a signal voltage. The first charge retention portion161is a capacitor that retains (stores) the signal voltage output from the first amplification transistor Tr13. The clamp transistor Tr16clamps the first charge retention portion161and the second charge retention portion162at a fixed potential VREF, in accordance with a clamp signal CLP. As a result, the first charge retention portion161and the second charge retention portion162retain the clamped fixed potential VREF. The sample-and-hold transistor Tr15causes the second charge retention portion162to hold a signal, in accordance with a control signal SHP. The second charge retention portion162is a capacitor that retains (stores) a signal voltage (a signal from which noise components have been removed in the pixel) that has been input via the sample-and-hold transistor Tr15. In the pixel2of the second embodiment, a denoising process for removing noise components derived from leakage current (dark current) is performed with a configuration formed with the load transistor Tr18, the sample-and-hold transistor Tr15, the clamp transistor Tr16, the first charge retention portion161, and the second charge retention portion162. The second charge retention portion162then retains (stores) the signal subjected to the denoising process. Note that, as the first charge retention portion161and the second charge retention portion162, it is preferable to use a capacitance of an MIM structure that is a capacitor with a small leakage current (dark current) per unit area, a capacitance of a PIP structure, or a capacitance of a MOS structure. With this arrangement, the resistance to noise is improved, and a high-quality signal can be obtained. The second amplification transistor Tr17outputs a voltage of the gate terminal, which is a signal voltage corresponding to the noise-removed signal stored in the second charge retention portion162. The selection transistor Tr14outputs the signal voltage output from the second amplification transistor Tr17, as the pixel signal to be output by the pixel2, to a vertical signal line9, in accordance with a selection signal SEL. As a result, the pixel signal corresponding to the photoelectric conversion signal of the photodiode PD is read out to the vertical signal line9. <6. Example Cross-Section Configuration of the Second Embodiment> FIG.10is a cross-sectional view of the pixel2according to the second embodiment shown inFIG.9. The circuit of the pixel2according to the second embodiment is configured by joining the first semiconductor substrate41and the second semiconductor substrate71to each other, as in the first embodiment. An on-chip lens42is formed for each pixel on the light incidence face side of the first semiconductor substrate41, which is the upper side inFIG.10, and a wiring layer43is formed on the opposite side of the first semiconductor substrate41from the light incidence face side. Note that, in addition to the on-chip lens42, an inter-pixel light blocking film, a color filter, an antireflection film, a planarizing film, and the like may be further formed on the upper surface of the first semiconductor substrate41on the light incidence face side. In the first semiconductor substrate41, an n-type semiconductor region52is formed in a predetermined region within a p-type semiconductor region (p-well)51, so that a photodiode PD is formed for each pixel. The wiring layer43formed on the first semiconductor substrate41on the side of the second semiconductor substrate71includes insulating layers53and54, and metallic wiring lines M41through47. The metallic wiring lines M41through M44, M46, and M47formed in the insulating layer53are wiring lines that transmit the transfer signal TRG, the reset signal RST, the power-supply voltage VDD, a pixel signal, and the like, and the metallic wiring line M45is a light blocking film designed to prevent incident light from entering the side of the second semiconductor substrate71. As a light blocking film is formed with the metallic wiring line M45at a position below the photodiode PD on the opposite side from the light incidence face side, it is possible to prevent incident light from leaking into the second semiconductor substrate71. The transfer transistor Tr11, the reset transistor Tr12, and the first amplification transistor Tr13are formed in the interface under the first semiconductor substrate41adjacent to the photodiode PD. The transfer transistor Tr11includes a gate electrode G11including polysilicon, and an n-type impurity region181. The reset transistor Tr12includes a gate electrode G12including polysilicon, and n-type impurity regions181and182as source/drain regions. The first amplification transistor Tr13includes a gate electrode G13including polysilicon, and n-type impurity regions182and183as source/drain regions. The gate electrode G13of the first amplification transistor Tr13is connected to the drain region (FD portion) of the transfer transistor Tr11and the n-type impurity region181as the source region of the reset transistor Tr12, via the metallic wiring line M43. Note that, although not shown in the drawing, a gate insulating film is formed between the first semiconductor substrate41and the gate electrodes G11, G12, and G13. An insulating layer72is formed on the second semiconductor substrate71on the side of the first semiconductor substrate41, and the insulating layer54of the first semiconductor substrate41and the insulating layer72of the second semiconductor substrate71are joined to each other by plasma bonding, for example. A dashed line L1between the insulating layer54and the insulating layer72corresponds to the substrate junction plane shown inFIG.9. A multilayer wiring layer73including three insulating layers81through83, metallic wiring lines M51through M60, and metallic wiring lines M71through M79is formed on the surface of the second semiconductor substrate71on the opposite side from the first semiconductor substrate41. The first charge retention portion161, the load transistor Tr18, the sample-and-hold transistor Tr15, the clamp transistor Tr16, the second amplification transistor Tr17, and the selection transistor Tr14are formed in the interface of the second semiconductor substrate71on the side of the multilayer wiring layer73. Further, a p-type semiconductor region84, and n-type semiconductor regions191through197that form, for example, the source/drain regions of the pixel transistors are formed in the second semiconductor substrate71. The first charge retention portion161includes the n-type impurity region191corresponding to the first electrode, and a second electrode G19including polysilicon. The n-type impurity region191of the first charge retention portion161is connected to the n-type impurity region183serving as the source region of the first amplification transistor Tr13, via the metallic wiring line M51, a via wiring line203, a connecting wiring line204, a through electrode202, and the metallic wiring line M42. With this arrangement, the photoelectric conversion signal stored in the photodiode PD is transmitted from the side of the first semiconductor substrate41to the side of the second semiconductor substrate71via the through electrode202, and is stored into the first charge retention portion161. The load transistor Tr18includes a gate electrode G18including polysilicon, and n-type impurity regions191and192as source/drain regions. The bias signal BIAS is applied to the gate electrode G18of the load transistor Tr18, via the metallic wiring line M53, a via wiring line205, and the metallic wiring line M73. A GND voltage is applied to the n-type impurity region192as the source region of the load transistor Tr18, via the metallic wiring line M54, a via wiring line206, and the metallic wiring line M74. The sample-and-hold transistor Tr15includes a gate electrode G15including polysilicon, and n-type impurity regions193and194as source/drain regions. The control signal SHP is applied to the gate electrode G15of the sample-and-hold transistor Tr15, via the metallic wiring line M56, a via wiring line207, and the metallic wiring line M75. The clamp transistor Tr16includes a gate electrode G16including polysilicon, and n-type impurity regions194and195as source/drain regions. The clamp signal CLP is applied to the gate electrode G16of the clamp transistor Tr16at a location not shown in the drawing. The second amplification transistor Tr17includes a gate electrode G17including polysilicon, and n-type impurity regions195and196as source/drain regions. The gate electrode G17of the second amplification transistor Tr17is connected to the source region of the clamp transistor Tr16, the drain region of the sample-and-hold transistor Tr15, and one end of the second charge retention portion162, at a position not shown in the drawing. The selection transistor Tr14includes a gate electrode G14including polysilicon, and n-type impurity regions196and197as source/drain regions. The selection signal SEL is applied to the gate electrode G14of the selection transistor Tr14, via the metallic wiring line M59, a via wiring line208, and the metallic wiring line M76. The n-type impurity region197as the drain region of the selection transistor Tr14is connected to the vertical signal line9, via the metallic wiring line M60, a via wiring line209, and the metallic wiring line M77. The metallic wiring line M71formed in the insulating layer83is connected to the metallic wiring line M41of the wiring layer43of the first semiconductor substrate41, via a through electrode201. The through electrode201supplies the power-supply voltage VDD from the side of the second semiconductor substrate71to the side of the first semiconductor substrate41. The metallic wiring line M78formed in the insulating layer83is connected to the metallic wiring line M46of the wiring layer43of the first semiconductor substrate41, via a through electrode210. The through electrode210transmits the reset signal RST from the side of the second semiconductor substrate71to the side of the first semiconductor substrate41. The metallic wiring line M79formed in the insulating layer83is connected to the metallic wiring line M47of the wiring layer43of the first semiconductor substrate41, via a through electrode211. The through electrode211transmits the transfer signal TRG from the side of the second semiconductor substrate71to the side of the first semiconductor substrate41. Note that, although not shown in the drawing, a gate insulating film is formed between the second semiconductor substrate71, and the gate electrodes G14through G18and the second electrode G19. An n-type impurity region for threshold voltage adjustment may be formed in the interface of the second semiconductor substrate71under the gate insulating film. The material of the metallic wiring lines M41through M47, the metallic wiring lines M51through M60, and the metallic wiring lines M71through M79is tungsten (W), which is a refractory metallic wiring material, for example, but may be some other material such as aluminum (Al), copper (Cu), or gold (Au). Copper is used as the material of the through electrodes201and202, the via wiring lines203and205through209, the through electrodes210and211, and the connecting wiring line204, for example, but some other metallic material may be used instead. In the pixel structure according to the second embodiment shown inFIG.10, the wiring layer43on the front surface side that is the wiring layer formation surface of the first semiconductor substrate41, and the insulating layer72on the back surface side that is the opposite side from the wiring layer formation surface of the second semiconductor substrate71are joined to each other. At least the photodiode PD that photoelectrically converts incident light, the transfer transistor Tr11that transfers electric charges of the photodiode PD, and the like are disposed in the first semiconductor substrate41. At least the first charge retention portion161as a charge/voltage retention portion that retains the voltage corresponding to the electric charges transferred by the transfer transistor Tr11, and the through electrode202that penetrates the second semiconductor substrate71and serves as a transmission path for transmitting the electric charges transferred from the transfer transistor Tr11to the first charge retention portion161are disposed in the second semiconductor substrate71. Because the first charge retention portion161as the charge/voltage retention portion that retains a voltage corresponding to electric charges in a global shutter operation is formed in the second semiconductor substrate71different from the first semiconductor substrate41in which the photodiode PD that is a photoelectric conversion portion is formed, a sufficiently large photoelectric conversion region can be secured in the first semiconductor substrate41. Furthermore, because the metallic wiring line M45as a light blocking film is disposed in the wiring layer43between the first semiconductor substrate41and the second semiconductor substrate71, it is possible to prevent incident light from leaking into the first charge retention portion161, and enhance the PLS characteristics. <7. Example Cross-Section Configuration of a Three-Layer Stack Structure> The first and second embodiments described above are examples in which two semiconductor substrates are joined to each other to form the solid-state imaging device1. However, as shown inFIGS.11and12, it is possible to form configurations in which three semiconductor substrates are stacked. FIG.11is a cross-sectional view of a first configuration in which three semiconductor substrates are stacked. Note thatFIGS.11and12each show a configuration in a case where the pixel configuration according to the first embodiment shown inFIG.3has a three-layer structure. The portions corresponding to those shown inFIG.3are denoted by the same reference numerals as those inFIG.3, and explanation of them will not be repeated. Meanwhile, the on-chip lens42is not shown due to limitations of space. In the cross-sectional view of the first configuration inFIG.11, a third semiconductor substrate231is stacked, in addition to the first semiconductor substrate41and the second semiconductor substrate71. In the insulating layer83closest to the third semiconductor substrate231in the multilayer wiring layer73formed on the second semiconductor substrate71, layers of metallic wiring lines M101are stacked. On the upper surface of the third semiconductor substrate231, which is the upper side inFIG.11, a multilayer wiring layer232including layers of metallic wiring lines M111and an interlayer insulating film241is formed. A plurality of transistors Trx is formed at the interface between the third semiconductor substrate231and the multilayer wiring layer232. The multilayer wiring layer73of the second semiconductor substrate71and the multilayer wiring layer232of the third semiconductor substrate231are joined to each other at the junction plane L2. The multilayer wiring layer73and the multilayer wiring layer232are electrically connected, as some of the metallic wiring lines M101and some of the metallic wiring lines M111are connected by Cu—Cu metal joining in a plurality of predetermined regions251. A logic circuit that performs predetermined signal processing is formed in the plurality of transistors Trx and the multilayer wiring layer232formed on the third semiconductor substrate231, and corresponds to the output circuit7inFIG.1, for example. FIG.12is a cross-sectional view of a second configuration in which three semiconductor substrates are stacked. InFIG.12, the components corresponding to those shown inFIG.11are denoted by the same reference numerals as those used inFIG.11, and explanation of them will not be repeated below. In the cross-sectional view of the second configuration inFIG.12, the multilayer wiring layer73of the second semiconductor substrate71and the multilayer wiring layer232of the third semiconductor substrate231are electrically connected by a twin-contact structure and Cu—Cu metal joining, not in the pixel array unit3having the pixels2arranged in a two-dimensional array, but in the peripheral circuit unit at the outer periphery of the pixel array unit3. Specifically, the twin-contact structure includes two through electrodes271and272penetrating the first semiconductor substrate41and the second semiconductor substrate71, and a connecting wiring line273formed in the uppermost surface of the first semiconductor substrate41. The through electrode271is connected to a metallic wiring line M121of the multilayer wiring layer73of the second semiconductor substrate71, and the through electrode272is connected to a metallic wiring line M122of the multilayer wiring layer232of the third semiconductor substrate231. The through electrode271and the through electrode272are connected by the connecting wiring line273on the uppermost surface of the first semiconductor substrate41. Further, regarding Cu—Cu metal joining, in a predetermined region261of the junction plane L2between the multilayer wiring layer73of the second semiconductor substrate71and the multilayer wiring layer232of the third semiconductor substrate231, one of the metallic wiring lines M101and one of the metallic wiring lines M111are Cu—Cu connected. As described above, the solid-state imaging device1shown inFIG.1may have a three-layer structure in which the third semiconductor substrate231is further stacked, while the photodiode PD as a photoelectric conversion portion, and the charge retention portion are disposed in different semiconductor substrates that are the first semiconductor substrate41and the second semiconductor substrate71. Note that, while it is essential that the photodiode PD as a photoelectric conversion portion is disposed in the first semiconductor substrate41on the light incidence face side, the charge retention portion that retains electric charges in a global shutter operation may be disposed in the third semiconductor substrate231, instead of the second semiconductor substrate71. Alternatively, the logic circuit may be disposed in the second semiconductor substrate71, and the charge retention portion may be disposed in the third semiconductor substrate231. In the description ofFIG.1, the solid-state imaging device1has a column AD configuration in which a signal processing circuit that performs AD conversion processes is provided for each column. However, an AD conversion circuit is not necessarily provided for each column, but may be provided for each pixel or for each unit formed with a plurality of pixels. Further, in the examples described above, the photodiode PD as a photoelectric conversion element, the memory portion MEM that temporarily retains electric charges transferred from the photodiode PD, and the like are provided for each pixel. However, It is also possible to adopt a sharing pixel structure in which some pixel transistors are shared by a plurality of pixels. In a sharing pixel structure, the photodiode PD, the first transfer transistor Tr1(or the transfer transistor Tr11), and the like are provided for each pixel, but the memory portion MEM as a charge retention portion, the second charge retention portion162, the selection transistor Tr5(Tr14), and the like are provided for each set of pixels forming a sharing unit, and are shared among the pixels. <8. Example Applications to Electronic Apparatuses> The present technology is not necessarily applied to a solid-state imaging device. Specifically, the present technology can be applied to any electronic apparatus using a solid-state imaging device as an image capturing unit (a photoelectric conversion portion), such as an imaging apparatus like a digital still camera or a video camera, a mobile terminal device having an imaging function, or a copying machine using a solid-state imaging device as the image reader. A solid-state imaging device may be in the form of a single chip, or may be in the form of a module that is formed by packaging an imaging unit and a signal processing unit or an optical system, and has an imaging function. FIG.13is a block diagram showing an example configuration of an imaging apparatus as an electronic apparatus to which the present technology is applied. An imaging apparatus300shown inFIG.13includes an optical unit301formed with lenses and the like, a solid-state imaging device (an imaging device)302that adopts the configuration of the solid-state imaging device1shown inFIG.1, and a digital signal processor (DSP) circuit303that is a camera signal processing circuit. The imaging apparatus300also includes a frame memory304, a display unit305, a recording unit306, an operation unit307, and a power supply unit308. The DSP circuit303, the frame memory304, the display unit305, the recording unit306, the operation unit307, and the power supply unit308are connected to one another via a bus line309. The optical unit301gathers incident light (image light) from an object, and forms an image on the imaging surface of the solid-state imaging device302. The solid-state imaging device302converts the amount of the incident light, which has been gathered as the image on the imaging surface by the optical unit301, into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal. As the solid-state imaging device302, it is possible to use the solid-state imaging device1shown inFIG.1, which is a solid-state imaging device that has the photodiode PD as a photoelectric conversion portion and the charge retention portion that retains electric charges in a global shutter operation in different semiconductor substrates, and enables miniaturization of pixels. The display unit305is formed with a flat-panel display such as a liquid crystal display (LCD) or an organic electro-luminescence (EL) display, for example, and displays a moving image or a still image formed by the solid-state imaging device302. The recording unit306records the moving image or the still image formed by the solid-state imaging device302on a recording medium such as a hard disk or a semiconductor memory. When operated by a user, the operation unit307issues operating instructions as to various functions of the imaging apparatus300. The power supply unit308supplies various power sources as the operation power sources for the DSP circuit303, the frame memory304, the display unit305, the recording unit306, and the operation unit307, as appropriate. As described above, the solid-state imaging device1to which each of embodiments described above is applied is used as the solid-state imaging device302, so that the PLS characteristics can be enhanced. Furthermore, as elements are formed in the second semiconductor substrate after the first semiconductor substrate including the photoelectric conversion portion and the second semiconductor substrate including the charge retention portion are bonded to each other, the element can be miniaturized. Accordingly, it is also possible to achieve high image quality and downsizing of captured images in the imaging apparatus300such as a video camera, a digital still camera, and a camera module for mobile devices like portable telephones. <Examples of Use of an Image Sensor> FIG.14is a diagram showing examples of use of an image sensor using the solid-state imaging device1described above. An image sensor using the solid-state imaging device1described above can be used in various cases where light, such as visible light, infrared light, ultraviolet light, or X-rays, is to be sensed, as listed below, for example.Devices configured to take images for appreciation activities, such as digital cameras and portable devices with camera functions.Devices for transportation use, such as vehicle-mounted sensors configured to take images of the front, the back, the surroundings, the inside, and the like of an automobile to perform safe driving such as an automatic stop and recognize the driver's condition and the like, surveillance cameras for monitoring running vehicles and roads, and ranging sensors for measuring distances between vehicles or the like.Devices to be used in conjunction with home electric appliances, such as television sets, refrigerators, and air conditioners, to take images of gestures of users and operate the appliances in accordance with the gestures.Devices for medical care use and health care use, such as endoscopes and devices for receiving infrared light for angiography.Devices for security use, such as surveillance cameras for crime prevention and cameras for personal authentication.Devices for beauty care use, such as skin measurement devices configured to image the skin and microscopes for imaging the scalp.Devices for sporting use, such as action cameras and wearable cameras for sports and the like.Devices for agricultural use such as cameras for monitoring conditions of fields and crops. <9. Example Application to an In-Vivo Information Acquisition System> The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to a patient in-vivo information acquisition system that uses a capsule endoscope. FIG.15is a block diagram schematically showing an example configuration of a patient's in-vivo information acquisition system using a capsule endoscope to which the technology (the present technology) according to the present disclosure may be applied. An in-vivo information acquisition system10001includes a capsule endoscope10100and an external control device10200. The capsule endoscope10100is swallowed by the patient at the time of examination. The capsule endoscope10100has an imaging function and a wireless communication function. Before naturally discharged from the patient, the capsule endoscope10100moves inside the internal organs such as the stomach and the intestines by peristaltic motion or the like, sequentially captures images of the inside of the internal organs (these images will be hereinafter also referred to as in-vivo images) at predetermined intervals, and sequentially transmits information about the in-vivo images to the external control device10200outside the body in a wireless manner. Further, the external control device10200controls the overall operation of the in-vivo information acquisition system10001. The external control device10200also receives the information about the in-vivo images transmitted from the capsule endoscope10100, and, on the basis of the received in-vivo image information, generates image data for displaying the in-vivo images on a display device (not shown). In this manner, the in-vivo information acquisition system10001can acquire in-vivo images showing the states of the inside of the body of the patient at any appropriate time until the swallowed capsule endoscope10100is discharged. The configurations and the functions of the capsule endoscope10100and the external control device10200are now described in greater detail. The capsule endoscope10100has a capsule-like housing10101, and the housing10101houses a light source unit10111, an imaging unit10112, an image processing unit10113, a wireless communication unit10114, a power feeder unit10115, a power supply unit10116, and a control unit10117. The light source unit10111is formed with a light source such as a light emitting diode (LED), for example, and emits light onto the imaging field of view of the imaging unit10112. The imaging unit10112is formed with an imaging device and an optical system including a plurality of lenses provided in front of the imaging device. Reflected light of light emitted to body tissue as the current observation target (this reflected light will be hereinafter referred to as the observation light) is collected by the optical system, and enters the imaging device. In the imaging unit10112, the observation light incident on the imaging device is photoelectrically converted, and an image signal corresponding to the observation light is generated. The image signal generated by the imaging unit10112is supplied to the image processing unit10113. The image processing unit10113is formed with a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various kinds of signal processing on the image signal generated by the imaging unit10112. The image processing unit10113supplies the image signal subjected to the signal processing as RAW data to the wireless communication unit10114. Further, the wireless communication unit10114performs predetermined processing such as modulation processing on the image signal subjected to the signal processing by the image processing unit10113, and transmits the image signal to the external control device10200via an antenna10114A. The wireless communication unit10114also receives a control signal related to control of driving of the capsule endoscope10100from the external control device10200via the antenna10114A. The wireless communication unit10114supplies the control signal received from the external control device10200to the control unit10117. The power feeder unit10115includes an antenna coil for power reception, a power regeneration circuit that regenerates electric power from the current generated in the antenna coil, a booster circuit, and the like. In the power feeder unit10115, electric power is generated according to a so-called non-contact charging principle. The power supply unit10116is formed with a secondary battery, and stores the electric power generated by the power feeder unit10115. InFIG.15, to avoid complication of the drawing, an arrow or the like indicating the destination of power supply from the power supply unit10116is not shown. However, the electric power stored in the power supply unit10116is supplied to the light source unit10111, the imaging unit10112, the image processing unit10113, the wireless communication unit10114, and the control unit10117, and can be used for driving these units. The control unit10117is formed with a processor such as a CPU, and drives the light source unit10111, the imaging unit10112, the image processing unit10113, the wireless communication unit10114, and the power feeder unit10115unit as appropriate in accordance with a control signal transmitted from the external control device10200. The external control device10200is formed with a processor such as a CPU or a GPU, or a microcomputer, a control board, or the like on which a processor and a storage element such as a memory are mounted together. The external control device10200controls operation of the capsule endoscope10100by transmitting a control signal to the control unit10117of the capsule endoscope10100via an antenna10200A. In the capsule endoscope10100, the conditions for emitting light to the current observation target in the light source unit10111can be changed in accordance with the control signal from the external control device10200, for example. Further, the imaging conditions (such as the frame rate and the exposure value in the imaging unit10112, for example) can also be changed in accordance with the control signal from the external control device10200. Further, the contents of the processing in the image processing unit10113and the conditions (such as the transmission intervals and the number of images to be transmitted, for example) for the wireless communication unit10114to transmit image signals may be changed in accordance with the control signal from the external control device10200. Further, the external control device10200also performs various kinds of image processing on the image signal transmitted from the capsule endoscope10100, and generates image data for displaying a captured in-vivo image on the display device. Examples of the image processing include various kinds of signal processing, such as a development process (a demosaicing process), an image quality enhancement process (a band emphasizing process, a super-resolution process, a noise reduction (NR) process, a camera shake correction process, and/or the like), and/or an enlargement process (an electronic zooming process), for example. The external control device10200controls driving of the display device, to cause the display device to display an in-vivo image captured on the basis of the generated image data. Alternatively, the external control device10200may cause a recording device (not shown) to record the generated image data, or cause a printing device (not shown) to print out the generated image data. An example of an in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit10112in the above described configuration. Specifically, the solid-state imaging device1described above can be used as the imaging unit10112. As the technology according to the present disclosure is applied to the imaging unit10112, the capsule endoscope10100can be made smaller, and thus, the burden on the patient can be further reduced. Furthermore, clearer images of the surgical site can be obtained, while the capsule endoscope10100is made smaller. Thus, the accuracy of examination is increased. <10. Example Application to an Endoscopic Surgery System> The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system. FIG.16is a diagram schematically showing an example configuration of an endoscopic surgery system to which the technology (the present technology) according to the present disclosure may be applied. FIG.16shows a situation where a surgeon (a physician)11131is performing surgery on a patient11132on a patient bed11133, using an endoscopic surgery system11000. As shown in the drawing, the endoscopic surgery system11000includes an endoscope11100, other surgical tools11110such as a pneumoperitoneum tube11111and an energy treatment tool11112, a support arm device11120that supports the endoscope11100, and a cart11200on which various kinds of devices for endoscopic surgery are mounted. The endoscope11100includes a lens barrel11101that has a region of a predetermined length from the top end to be inserted into a body cavity of the patient11132, and a camera head11102connected to the base end of the lens barrel11101. In the example shown in the drawing, the endoscope11100is configured as a so-called rigid scope having a rigid lens barrel11101. However, the endoscope11100may be configured as a so-called flexible scope having a flexible lens barrel. At the top end of the lens barrel11101, an opening into which an objective lens is inserted is provided. A light source device11203is connected to the endoscope11100, and the light generated by the light source device11203is guided to the top end of the lens barrel by a light guide extending inside the lens barrel11101, and is emitted toward the current observation target in the body cavity of the patient11132via the objective lens. Note that the endoscope11100may be a forward-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope. An optical system and an imaging device are provided inside the camera head11102, and reflected light (observation light) from the current observation target is converged on the imaging device by the optical system. The observation light is photoelectrically converted by the imaging device, and an electrical signal corresponding to the observation light, or an image signal corresponding to the observation image, is generated. The image signal is transmitted as RAW data to a camera control unit (CCU)11201. The CCU11201is formed with a central processing unit (CPU), a graphics processing unit (GPU), or the like, and collectively controls operations of the endoscope11100and a display device11202. Further, the CCU11201receives an image signal from the camera head11102, and subjects the image signal to various kinds of image processing, such as a development process (demosaicing process), for example, to display an image based on the image signal. Under the control of the CCU11201, the display device11202displays an image based on the image signal subjected to the image processing by the CCU11201. The light source device11203is formed with a light source such as a light emitting diode (LED), for example, and supplies the endoscope11100with illuminating light for imaging the surgical site or the like. An input device11204is an input interface to the endoscopic surgery system11000. The user can input various kinds of information and instructions to the endoscopic surgery system11000via the input device11204. For example, the user inputs an instruction or the like to change imaging conditions (such as the type of illuminating light, the magnification, and the focal length) for the endoscope11100. A treatment tool control device11205controls driving of the energy treatment tool11112for tissue cauterization, incision, blood vessel sealing, or the like. A pneumoperitoneum device11206injects a gas into a body cavity of the patient11132via the pneumoperitoneum tube11111to inflate the body cavity, for the purpose of securing the field of view of the endoscope11100and the working space of the surgeon. A recorder11207is a device capable of recording various kinds of information about the surgery. A printer11208is a device capable of printing various kinds of information relating to the surgery in various formats such as text, images, graphics, and the like. Note that the light source device11203that supplies the endoscope11100with the illuminating light for imaging the surgical site can be formed with an LED, a laser light source, or a white light source that is a combination of an LED and a laser light source, for example. In a case where a white light source is formed with a combination of RGB laser light sources, the output intensity and the output timing of each color (each wavelength) can be controlled with high precision. Accordingly, the white balance of an image captured by the light source device11203can be adjusted. Alternatively, in this case, laser light from each of the RGB laser light sources may be emitted onto the current observation target in a time-division manner, and driving of the imaging device of the camera head11102may be controlled in synchronization with the timing of the light emission. Thus, images corresponding to the respective RGB colors can be captured in a time-division manner. According to the method, a color image can be obtained without any color filter provided in the imaging device. Further, the driving of the light source device11203may also be controlled so that the intensity of light to be output is changed at predetermined time intervals. The driving of the imaging device of the camera head11102is controlled in synchronism with the timing of the change in the intensity of the light, and images are acquired in a time-division manner and are then combined. Thus, a high dynamic range image with no black portions and no white spots can be generated. Further, the light source device11203may also be designed to be capable of supplying light of a predetermined wavelength band compatible with special light observation. In special light observation, light of a narrower band than the illuminating light (or white light) at the time of normal observation is emitted, with the wavelength dependence of light absorption in body tissue being taken advantage of, for example. As a result, so-called narrow band imaging is performed to image predetermined tissue such as a blood vessel in a mucosal surface layer or the like, with high contrast. Alternatively, in the special light observation, fluorescence observation for obtaining an image with fluorescence generated through emission of excitation light may be performed. In fluorescence observation, excitation light is emitted to body tissue so that the fluorescence from the body tissue can be observed (autofluorescence observation). Alternatively, a reagent such as indocyanine green (ICG) is locally injected into body tissue, and excitation light corresponding to the fluorescence wavelength of the reagent is emitted to the body tissue so that a fluorescent image can be obtained, for example. The light source device11203can be designed to be capable of suppling narrowband light and/or excitation light compatible with such special light observation. FIG.17is a block diagram showing an example of the functional configurations of the camera head11102and the CCU11201shown inFIG.16. The camera head11102includes a lens unit11401, an imaging unit11402, a drive unit11403, a communication unit11404, and a camera head control unit11405. The CCU11201includes a communication unit11411, an image processing unit11412, and a control unit11413. The camera head11102and the CCU11201are communicably connected to each other by a transmission cable11400. The lens unit11401is an optical system provided at the connecting portion with the lens barrel11101. Observation light captured from the top end of the lens barrel11101is guided to the camera head11102, and enters the lens unit11401. The lens unit11401is formed with a combination of a plurality of lenses including a zoom lens and a focus lens. The imaging unit11402is formed with an imaging device. The imaging unit11402may be formed with one imaging device (a so-called single-plate type), or may be formed with a plurality of imaging devices (a so-called multiple-plate type). In a case where the imaging unit11402is of a multiple-plate type, for example, image signals corresponding to the respective RGB colors may be generated by the respective imaging devices, and be then combined to obtain a color image. Alternatively, the imaging unit11402may be designed to include a pair of imaging devices for acquiring right-eye and left-eye image signals compatible with three-dimensional (3D) display. As the 3D display is conducted, the surgeon11131can grasp more accurately the depth of the body tissue at the surgical site. Note that, in a case where the imaging unit11402is of a multiple-plate type, a plurality of lens units11401is provided for the respective imaging devices. Further, the imaging unit11402is not necessarily provided in the camera head11102. For example, the imaging unit11402may be provided immediately behind the objective lens in the lens barrel11101. The drive unit11403is formed with an actuator, and, under the control of the camera head control unit11405, moves the zoom lens and the focus lens of the lens unit11401by a predetermined distance along the optical axis. With this arrangement, the magnification and the focal point of the image captured by the imaging unit11402can be appropriately adjusted. The communication unit11404is formed with a communication device for transmitting and receiving various kinds of information to and from the CCU11201. The communication unit11404transmits the image signal obtained as RAW data from the imaging unit11402to the CCU11201via the transmission cable11400. Further, the communication unit11404also receives a control signal for controlling the driving of the camera head11102from the CCU11201, and supplies the control signal to the camera head control unit11405. The control signal includes information about imaging conditions, such as information for specifying the frame rate of captured images, information for specifying the exposure value at the time of imaging, and/or information for specifying the magnification and the focal point of captured images, for example. Note that the above imaging conditions such as the frame rate, the exposure value, the magnification, and the focal point may be appropriately specified by the user, or may be automatically set by the control unit11413of the CCU11201on the basis of an acquired image signal. In the latter case, the endoscope11100has a so-called auto-exposure (AE) function, an auto-focus (AF) function, and an auto-white-balance (AWB) function. The camera head control unit11405controls the driving of the camera head11102, on the basis of a control signal received from the CCU11201via the communication unit11404. The communication unit11411is formed with a communication device for transmitting and receiving various kinds of information to and from the camera head11102. The communication unit11411receives an image signal transmitted from the camera head11102via the transmission cable11400. Further, the communication unit11411also transmits a control signal for controlling the driving of the camera head11102, to the camera head11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, or the like. The image processing unit11412performs various kinds of image processing on an image signal that is RAW data transmitted from the camera head11102. The control unit11413performs various kinds of control relating to display of an image of the surgical portion or the like captured by the endoscope11100, and a captured image obtained through imaging of the surgical site or the like. For example, the control unit11413generates a control signal for controlling the driving of the camera head11102. Further, the control unit11413also causes the display device11202to display a captured image showing the surgical site or the like, on the basis of the image signal subjected to the image processing by the image processing unit11412. In doing so, the control unit11413may recognize the respective objects shown in the captured image, using various image recognition techniques. For example, the control unit11413can detect the shape, the color, and the like of the edges of an object shown in the captured image, to recognize the surgical tool such as forceps, a specific body site, bleeding, the mist at the time of use of the energy treatment tool11112, and the like. When causing the display device11202to display the captured image, the control unit11413may cause the display device11202to superimpose various kinds of surgery aid information on the image of the surgical site on the display, using the recognition result. As the surgery aid information is superimposed and displayed, and thus, is presented to the surgeon11131, it becomes possible to reduce the burden on the surgeon11131, and enable the surgeon11131to proceed with the surgery in a reliable manner. The transmission cable11400connecting the camera head11102and the CCU11201is an electrical signal cable compatible with electric signal communication, an optical fiber compatible with optical communication, or a composite cable thereof. Here, in the example shown in the drawing, communication is performed in a wired manner using the transmission cable11400. However, communication between the camera head11102and the CCU11201may be performed in a wireless manner. An example of an endoscopic surgery system to which the technique according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit11402of the camera head11102, among the configurations described above. Specifically, the solid-state imaging device1described above can be applied as the imaging unit11402. As the technology according to the present disclosure is applied to the imaging unit11402, it is possible to obtain a clearer surgical site image, while reducing the size of the camera head11102. Note that, although an endoscopic surgery system has been described as an example herein, the technique according to the present disclosure may be applied to some other system, such as a microscopic surgery system, for example. <11. Example Applications to Mobile Structures> The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be embodied as an apparatus mounted on any type of mobile structure, such as an automobile, an electrical vehicle, a hybrid electrical vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a vessel, or a robot. FIG.18is a block diagram schematically showing an example configuration of a vehicle control system that is an example of a mobile structure control system to which the technology according to the present disclosure may be applied. A vehicle control system12000includes a plurality of electronic control units connected via a communication network12001. In the example shown inFIG.18, the vehicle control system12000includes a drive system control unit12010, a body system control unit12020, an external information detection unit12030, an in-vehicle information detection unit12040, and an overall control unit12050. Further, a microcomputer12051, a sound/image output unit12052, and an in-vehicle network interface (I/F)12053are also shown as the functional components of the overall control unit12050. The drive system control unit12010controls operations of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit12010functions as control devices such as a driving force generation device for generating a driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle. The body system control unit12020controls operations of the various devices mounted on the vehicle body according to various programs. For example, the body system control unit12020functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal lamp, a fog lamp, or the like. In this case, the body system control unit12020can receive radio waves transmitted from a portable device that substitutes for a key, or signals from various switches. The body system control unit12020receives inputs of these radio waves or signals, and controls the door lock device, the power window device, the lamps, and the like of the vehicle. The external information detection unit12030detects information outside the vehicle equipped with the vehicle control system12000. For example, an imaging unit12031is connected to the external information detection unit12030. The external information detection unit12030causes the imaging unit12031to capture an image of the outside of the vehicle, and receives the captured image. On the basis of the received image, the external information detection unit12030may perform an object detection process for detecting a person, a vehicle, an obstacle, a sign, characters on the road surface, or the like, or perform a distance detection process. The imaging unit12031is an optical sensor that receives light, and outputs an electrical signal corresponding to the amount of received light. The imaging unit12031can output an electrical signal as an image, or output an electrical signal as distance measurement information. Further, the light to be received by the imaging unit12031may be visible light, or may be invisible light such as infrared rays. The in-vehicle information detection unit12040detects information about the inside of the vehicle. For example, a driver state detector12041that detects the state of the driver is connected to the in-vehicle information detection unit12040. The driver state detector12041includes a camera that captures an image of the driver, for example, and, on the basis of detected information input from the driver state detector12041, the in-vehicle information detection unit12040may calculate the degree of fatigue or the degree of concentration of the driver, or determine whether the driver is dozing off. On the basis of the external/internal information acquired by the external information detection unit12030or the in-vehicle information detection unit12040, the microcomputer12051can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit12010. For example, the microcomputer12051can perform cooperative control to achieve the functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance or impact mitigation, follow-up running based on the distance between vehicles, vehicle speed maintenance running, vehicle collision warning, vehicle lane deviation warning, or the like. Further, the microcomputer12051can also perform cooperative control to conduct automatic driving or the like for autonomously running not depending on the operation of the driver, by controlling the driving force generation device, the steering mechanism, the braking device, or the like on the basis of information about the surroundings of the vehicle, the information having being acquired by the external information detection unit12030or the in-vehicle information detection unit12040. Further, the microcomputer12051can also output a control command to the body system control unit12020, on the basis of the external information acquired by the external information detection unit12030. For example, the microcomputer12051controls the headlamp in accordance with the position of the leading vehicle or the oncoming vehicle detected by the external information detection unit12030, and performs cooperative control to achieve an anti-glare effect by switching from a high beam to a low beam, or the like. The sound/image output unit12052transmits an audio output signal and/or an image output signal to an output device that is capable of visually or audibly notifying the passenger(s) of the vehicle or the outside of the vehicle of information. In the example shown inFIG.18, an audio speaker12061, a display unit12062, and an instrument panel12063are shown as output devices. The display unit12062may include an on-board display and/or a head-up display, for example. FIG.19is a diagram showing an example of installation positions of imaging units12031. InFIG.19, a vehicle12100includes imaging units12101,12102,12103,12104, and12105as the imaging units12031. Imaging units12101,12102,12103,12104, and12105are provided at the following positions: the front end edge of a vehicle12100, a side mirror, the rear bumper, a rear door, an upper portion, and the like of the front windshield inside the vehicle, for example. The imaging unit12101provided on the front end edge and the imaging unit12105provided on the upper portion of the front windshield inside the vehicle mainly capture images ahead of the vehicle12100. The imaging units12102and12103provided on the side mirrors mainly capture images on the sides of the vehicle12100. The imaging unit12104provided on the rear bumper or a rear door mainly captures images behind the vehicle12100. The front images acquired by the imaging units12101and12105are mainly used for detection of a vehicle running in front of the vehicle12100, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like. Note thatFIG.19shows an example of the imaging ranges of the imaging units12101through12104. An imaging range12111indicates the imaging range of the imaging unit12101provided on the front end edge, imaging ranges12112and12113indicate the imaging ranges of the imaging units12102and12103provided on the respective side mirrors, and an imaging range12114indicates the imaging range of the imaging unit12104provided on the rear bumper or a rear door. For example, image data captured by the imaging units12101through12104are superimposed on one another, so that an overhead image of the vehicle12100viewed from above is obtained. At least one of the imaging units12101through12104may have a function of acquiring distance information. For example, at least one of the imaging units12101through12104may be a stereo camera including a plurality of imaging devices, or may be an imaging device having pixels for phase difference detection. For example, in accordance with distance information obtained from the imaging units12101through12104, the microcomputer12051calculates the distances to the respective three-dimensional objects within the imaging ranges12111through12114, and temporal changes in the distances (the speeds relative to the vehicle12100). In this manner, the three-dimensional object that is the closest three-dimensional object on the traveling path of the vehicle12100and is traveling at a predetermined speed (0 km/h or higher, for example) in substantially the same direction as the vehicle12100can be extracted as the vehicle running in front of the vehicle12100. Further, the microcomputer12051can set beforehand an inter-vehicle distance to be maintained in front of the vehicle running in front of the vehicle12100, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this manner, it is possible to perform cooperative control to conduct automatic driving or the like to autonomously travel not depending on the operation of the driver. For example, in accordance with the distance information obtained from the imaging units12101through12104, the microcomputer12051can extract three-dimensional object data concerning three-dimensional objects under the categories of two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, utility poles, and the like, and use the three-dimensional object data in automatically avoiding obstacles. For example, the microcomputer12051classifies the obstacles in the vicinity of the vehicle12100into obstacles visible to the driver of the vehicle12100and obstacles difficult to visually recognize. Then, the microcomputer12051then determines collision risks indicating the risks of collision with the respective obstacles. If a collision risk is equal to or higher than a set value, and there is a possibility of collision, the microcomputer12051can output a warning to the driver via the audio speaker12061and the display unit12062, or can perform driving support for avoiding collision by performing forced deceleration or avoiding steering via the drive system control unit12010. At least one of the imaging units12101through12104may be an infrared camera that detects infrared rays. For example, the microcomputer12051can recognize a pedestrian by determining whether or not a pedestrian exists in images captured by the imaging units12101through12104. Such pedestrian recognition is carried out through a process of extracting feature points from the images captured by the imaging units12101through12104serving as infrared cameras, and a process of performing a pattern matching on the series of feature points indicating the outlines of objects and determining whether or not there is a pedestrian, for example. If the microcomputer12051determines that a pedestrian exists in the images captured by the imaging units12101through12104, and recognizes a pedestrian, the sound/image output unit12052controls the display unit12062to display a rectangular contour line for emphasizing the recognized pedestrian in a superimposed manner. Further, the sound/image output unit12052may also control the display unit12062to display an icon or the like indicating the pedestrian at a desired position. An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit12031in the above described configuration. Specifically, the solid-state imaging device1described above can be applied as the imaging unit12031. As the technology according to the present disclosure is applied to the imaging unit12031, it is possible to obtain a more easier-to-view captured image and obtain distance information, while reducing the size. It is also possible to reduce the driver's fatigue and increase the degree of safety of the driver and the vehicle, using the obtained captured image and distance information. In the solid-state imaging devices in the above described examples, the first conductivity type is the p-type, the second conductivity type is the n-type, and electrons are used as signal charges. However, the present technology can also be applied to solid-state imaging devices in which holes are used as signal charges. That is, the first conductivity type can be the n-type, the second conductivity type can be the p-type, and the conductivity types of the above described respective semiconductor regions can be reversed. The present technology can also be applied not only to solid-state imaging devices that sense an incident light quantity distribution of visible light and form an image in accordance with the distribution, but also to solid-state imaging devices (physical quantity distribution sensors) in general, such as a solid-state imaging device that senses an incident quantity distribution of infrared rays, X-rays, particles, or the like, and forms an image in accordance with the distribution, or a fingerprint sensor that senses a distribution of some other physical quantity in a broad sense, such as pressure or capacitance, and forms an image in accordance with the distribution. Embodiments of the present technology are not limited to the above described embodiments, and various modifications may be made to them without departing from the scope of the present technology. For example, it is possible to adopt a combination of all or some of the embodiments described above. Note that the advantageous effects described in this specification are merely examples, and the advantageous effects of the present technology are not limited to them and may include effects other than those described in this specification. Note that the present technology may also be embodied in the configurations described below. (1) A solid-state imaging device including:a first semiconductor substrate and a second semiconductor substrate, a front surface side as a wiring layer formation surface of the first semiconductor substrate being joined to a back surface side of the second semiconductor substrate on the opposite side from a wiring layer formation surface of the second semiconductor substrate,the first semiconductor substrate including:a photoelectric conversion portion that photoelectrically converts incident light; anda transfer transistor that transfers an electric charge of the photoelectric conversion portion,the second semiconductor substrate includinga charge/voltage retention portion that retains the electric charge transferred by the transfer transistor or a voltage corresponding to the electric charge; anda through electrode that penetrates the second semiconductor substrate, and transmits the electric charge transferred from the transfer transistor or the voltage to the charge/voltage retention portion. (2) The solid-state imaging device according to (1), in whichthe first semiconductor substrate further includesa light blocking film formed with a metallic wiring line that is part of a wiring layer. (3) The solid-state imaging device according to (1) or (2), in whichthe first semiconductor substrate further includesa charge-voltage conversion portion that generates the voltage corresponding to the electric charge, andthe charge/voltage retention portion of the second semiconductor substrate holds the voltage converted by the charge-voltage conversion portion. (4) The solid-state imaging device according to any one of (1) to (3), in whicha cross-sectional diameter of the through electrode at a junction plane between the first semiconductor substrate and the second semiconductor substrate is smaller than or the same as a cross-sectional diameter of a portion penetrating the second semiconductor substrate. (5) The solid-state imaging device according to any one of (1) to (4), in which,in a pixel region, the first semiconductor substrate and the second semiconductor substrate are electrically connected only by a plurality of through electrodes. (6) The solid-state imaging device according to any one of (1) to (5), in whicha metallic wiring line of a wiring layer of the first semiconductor substrate includes tungsten. (7) A method for manufacturing a solid-state imaging device, the method including:forming a photoelectric conversion portion and a transfer transistor in a first semiconductor substrate, the photoelectric conversion portion photoelectrically converting incident light, the transfer transistor transferring an electric charge of the photoelectric conversion portion;bonding a front surface side as a wiring layer formation surface of the first semiconductor substrate to a back surface side of the second semiconductor substrate on the opposite side from a wiring layer formation surface of the second semiconductor substrate;forming a charge/voltage retention portion in the second semiconductor substrate after the bonding, the charge/voltage retention portion retaining the electric charge transferred by the transfer transistor or a voltage corresponding to the electric charge; andforming a through electrode that penetrates the second semiconductor substrate, and transmits the electric charge transferred from the transfer transistor or the voltage to the charge/voltage retention portion. (8) An electronic apparatus includinga solid-state imaging device including:a first semiconductor substrate and a second semiconductor substrate, a front surface side as a wiring layer formation surface of the first semiconductor substrate being joined to a back surface side of the second semiconductor substrate on the opposite side from a wiring layer formation surface of the second semiconductor substrate,the first semiconductor substrate including:a photoelectric conversion portion that photoelectrically converts incident light; anda transfer transistor that transfers an electric charge of the photoelectric conversion portion,the second semiconductor substrate including:a charge/voltage retention portion that retains the electric charge transferred by the transfer transistor or a voltage corresponding to the electric charge; anda through electrode that penetrates the second semiconductor substrate, and transmits the electric charge transferred from the transfer transistor or the voltage to the charge/voltage retention portion. REFERENCE SIGNS LIST 1Solid-state imaging device2Pixel3Pixel array unit41First semiconductor substrate43Wiring layer71Second semiconductor substrate73Multilayer wiring layer91,92,98,99Through electrodeTr1First transfer transistorM4Metallic wiring lineMEM Memory unitPD PhotodiodeTr11Transfer transistorTr13First amplification transistor300Imaging apparatus302Solid-state imaging device | 99,938 |
11942503 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are not limited to the particular methodology, uses, and applications described herein, as these may vary. It is also to be understood that the terminology used herein is used for the purpose of describing particular embodiments only, and is not intended to limit the scope of all embodiments of the present invention. It must be noted that as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include the plural reference unless the context clearly dictates otherwise. Thus, for example, a reference to “an element” is a reference to one or more elements, and includes equivalents thereof known to those skilled in the art. Similarly, for another example, a reference to “a step” or “a means” is a reference to one or more steps or means and may include sub-steps or subservient means. All conjunctions used are to be understood in the most inclusive sense possible. Thus, the word “or” should be understood as having the definition of a logical “or” rather than that of a logical “exclusive or” unless the context clearly necessitates otherwise. Structures described herein are to be understood also to refer to functional equivalents of such structures. Language that may be construed to express approximation should be so understood unless the context clearly dictates otherwise. Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which this invention belongs. Preferred methods, techniques, devices and materials are described although any methods, techniques, devices, or materials similar or equivalent to those described may be used in the practice or testing of the present invention. All patents and other publications discussed are incorporated herein by reference for the purpose of describing and disclosing, for example, the methodologies described in such publications that might be useful in connection with the present invention. These publications are provided solely for their disclosure prior to the filing date of the present application. Nothing in this regard should be construed as an admission that the inventors are not entitled to antedate or otherwise remove any such publication or patent as prior art for any reason. Image sensor units are individual, modular units of sensor arrays that may be integrated with certain electronics, for example, one or more of control logic, analog multiplexer, analog amplifiers, and similar option hardware. Referring now toFIG.1, an implementation of an image sensor unit100is shown. Image sensor unit100includes sensor pixel array102, unit controller104, memory106, row control circuitry108(or more simply, row control108), and column control circuitry110(or more simply, column control110). An analog amplifier112may also be included, and may be located either on the same chip as the image sensor unit or off-chip. The image sensor unit100includes a two-dimensional addressing scheme using the row control108and row addressing lines A-H and column control110and column addressing lines 1-8. Instead of the conventional sequential row-by-row readout, the pixels in the sensor pixel array102can be selectively read out in any order, whether predefined or selected on the fly. Pixels can be read out individually, or in any combination with any other pixel(s) (or “binning”) to put more than one pixel on the data line(s)114,114a-hto the amplifier112. Any binning pattern (for example, no binning, 2×1, 2×2, 2×3, etc.) can be predefined or programmed to the unit on demand Sensor pixel array102includes individual pixels that can be passive or active, for example, amorphous silicon pixels, 3T CMOS active pixels, and may be arranged in any suitable pattern. In the example ofFIG.1, the pixels are arranged in an 8×8 array, but implementations of an image sensor unit are not limited in this regard. Unit controller104communicates, for example, with external devices and/or control logic at different hierarchy level on the chip, access memory106, and control the row control108and column control110. In an implementation, unit controller104communicates with a field-programmable gate array, an application specific integrated circuit, and/or imager control logic. For example, those external devices send readout patterns to the unit controller, synchronize the operation of all the image sensor units100in the imager. In an implementation, unit controller104communicates with chip level control logic, a layer of the logic control hierarchy in the imager, for further configuration of operating the pixels in the unit, for example, binning modes, readout pattern and sequencing, etc. Row control108may be configured to selectively assert any single row or group of rows concurrently. For example, Row control108may assert a row alone or may assert any number of rows. Concurrently asserted rows may or may not be contiguous. For example, row control108may assert row A and B concurrently. Alternatively, row control108may assert rows A and C but not row B Similarly, column control110may be configured to assert a single column alone or any number of columns. For example, column control110may assert column 2 alone, or may assert columns 2 and 3 concurrently. Alternatively, column control110may assert columns 1 and 3 or 1 and 4 concurrently, for example. To select an individual pixel, a single row and a single column are asserted. For example, asserting row C and column 5 sends the value of pixel C5 to the data line114cto data line114to the amplifier112. Binned patterns can be asserted by asserting row and column combinations that define the particular pattern desired. For example, asserting rows A and B and columns 2 and 3 yields a 2×2 pattern with pixels A2, A3, B2, and B3. One of ordinary skill will understand how other patterns can be asserted. Memory106is used to store pre-defined readout patterns, for example. Additionally, the locations of pixels for repair or to skip read out (e.g. bad pixels) may be stored in memory106. In an example readout scheme, each pixel is read out one by one through the amplifier112. The amplifier112outputs an analog signal for further processing off the chip, for example, time stamping and/or digitization. Referring now toFIG.2, another implementation of an image sensor unit200is shown that outputs a digital signal. Image sensor unit200includes sensor pixel array202, unit controller204, memory206, row control208, and column control210. An analog amplifier212and a digitizer216may also be included, and may be located either on the same chip as the image sensor unit or off-chip Similar to image sensor unit100ofFIG.1, image sensor unit200includes a two-dimensional addressing scheme using the row control208and row addressing lines A-H and column control210and column addressing lines 1-8. Instead of the conventional sequential row-by-row readout, the pixels in the sensor pixel array202can be read out in any order, whether predefined or selected on the fly. Pixels can be selectively read out individually, or in any combination with any other pixel(s) (or “binning”) to put more than one pixel on the data line(s)214,214a-hto the amplifier212and digitizer216. Any binning pattern (for example, no binning, 2×1, 2×2, 2×3, etc.) can be predefined or programmed to the unit on demand Sensor pixel array202includes individual pixels that can be passive or active and may be arranged in any suitable pattern. In the example ofFIG.2, the pixels are arranged in an 8×8 array, but implementations of an image sensor unit are not limited in this regard. Unit controller204communicates, for example, with external devices and/or control logic at different hierarchy level on the chip, access memory206, and control the row control208and column control210. In an implementation, Unit controller204communicates with a field-programmable gate array, an application specific integrated circuit, and/or imager control logic. For example, those external devices send readout patterns to the unit controller and synchronize the operation of all the image sensor units200in the imager. In an implementation, unit controller204communicates with chip level control logic, a layer of the logic control hierarchy in the imager, for further configuration of the operation of the pixels in the unit, for example, binning modes, readout pattern and sequencing, etc. Row control208may be configured to assert any single row or group of rows concurrently. For example, Row control208may assert a row alone or may assert any number of rows. Concurrently asserted rows may or may not be contiguous. For example, row control208may assert row A and B concurrently. Alternatively, row control208may assert rows A and C but not row B. Similarly, column control210may be configured to assert a single column alone or any number of columns. For example, column control210may assert column 2 alone, or may assert columns 2 and 3 concurrently. Alternatively, column control210may assert columns 1 and 3 or 1 and 4 concurrently, for example. To select an individual pixel, a single row and a single column are asserted. For example, asserting row C and column 5 sends the value of pixel C5 to the data line214cto data line214to the amplifier212. Binned patterns can be asserted by asserting row and column combinations that define the particular pattern desired. For example, asserting rows A and B and columns 2 and 3 yields a 2×2 pattern with pixels A2, A3, B2, and B3. One of ordinary skill will understand how other patterns can be asserted. Memory206is used to store pre-defined readout patterns, for example. Additionally, the locations of pixels for repair or to skip read out (e.g. bad pixels) may be stored in memory206. In an example readout scheme, each pixel is read out one by one through the amplifier212. The amplifier212outputs an analog signal for further processing and digitization in digitizer216, for example. Referring now toFIG.3, another implementation of an image sensor unit300is shown that outputs a digital signal. Image sensor unit300includes sensor pixel array302, unit controller304, memory306, row control308, and column control310. Analog amplifiers312and313may also be included, and may be located either on the same chip as the image sensor unit or off-chip Similar to image sensor unit100ofFIG.1, image sensor unit300includes a two-dimensional addressing scheme using the row control308and row addressing lines A-H and column control310and column addressing lines 1-8. Instead of the conventional sequential row-by-row readout, the pixels in the sensor pixel array302can be read out in any order, whether predefined or selected on the fly. Pixels can be selectively read out individually, or in any combination with any other pixel(s) (or “binning”) to put more than one pixel on the data line(s)314a-hand processed through analog multiplexer316to two or more amplifiers, for example amplifier312and amplifier313. Any binning pattern (for example, no binning, 2×1, 2×2, 2×3, etc.) can be predefined or programmed to the unit on demand Sensor pixel array302includes individual pixels that can be passive or active and may be arranged in any suitable pattern. In the example ofFIG.3, the pixels are arranged in an 8×8 array, but implementations of an image sensor unit are not limited in this regard. Unit controller304communicates, for example, with external devices and/or control logic at different hierarchy level on the chip, access memory306, and control the row control308and column control310. In an implementation, Unit controller304communicates with a field-programmable gate array, an application specific integrated circuit, and/or imager control logic. For example, those external devices send readout patterns to the unit controller and synchronize the operation of all the image sensor units300in the imager. In an implementation, unit controller304communicates with chip level control logic, a layer of the logic control hierarchy in the imager, for further configuration of the operation of the pixels in the unit, for example, binning modes, readout pattern and sequencing, etc. Row control308may be configured to assert any single row or group of rows concurrently. For example, Row control308may assert a row alone or may assert any number of rows. Concurrently asserted rows may or may not be contiguous. For example, row control308may assert row A and B concurrently. Alternatively, row control308may assert rows A and C but not row B. Similarly, column control310may be configured to assert a single column alone or any number of columns. For example, column control310may assert column 2 alone, or may assert columns 2 and 3 concurrently. Alternatively, column control310may assert columns 1 and 3 or 1 and 4 concurrently, for example. To select an individual pixel, a single row and a single column are asserted. For example, asserting row C and column 5 sends the value of pixel C5 to the data line314cto data line314to the analog multiplexer316and one or both of amplifier312and amplifier313. Binned patterns can be asserted by asserting row and column combinations that define the particular pattern desired. For example, asserting rows A and B and columns 2 and 3 yields a 2×2 pattern with pixels A2, A3, B2, and B3. One of ordinary skill will understand how other patterns can be asserted. Analog multiplexer316can also be used to send different signals to each amplifier. For example, row control308and column control310may assert pixels B2, B3, C2, and C3 to read out through data line315ato amplifier312and pixels C5, C6, D5, and D6 to read out through data line315bto amplifier313. Memory306is used to store pre-defined readout patterns, for example. Additionally, the locations of pixels for repair or to skip read out (e.g. bad pixels) may be stored in memory306. In an example readout scheme using one amplifier each pixel is read out one by one to one of amplifier312and amplifier313. Once the pixels are read out, amplifiers312,313output an analog signal, for example, for further processing and digitization in a digitizer (not shown inFIG.3) or other processing and/or output circuitry. In another example readout scheme using both amplifiers, unit controller304asserts pixels A1 and H1 simultaneously, assign pixel A1 to amplifier312, and pixel H1 to amplifier313, respectively, using analog multiplexer316. In another example readout scheme for binned pixels, for example 2×2 binning: A1, A2, B1 and B2; G1, G2, H1 and H2. Using one amplifier, the unit controller304asserts row A and B, column 1 and 2, simultaneously, and the binned pixels (A1, A2, B1, and B2) are read out to the assigned amplifier through the analog multiplexer316. Using both amplifiers, the unit controller304asserts row A, B, G, and H, column 1 and 2, simultaneously, assign a first binned pixel range (for example, A1, A2, B1, and B2) to amplifier312, and a second binned pixel range (G1, G2, H1, and H2) Amplifier313, respectively, through the analog multiplexer316. Although not shown inFIG.3, a digitizer may be integrated on the same chip to digitize the output signals of the amplifiers. Referring now toFIG.4, a block diagram of a large area flat panel imager400is shown. Imager400includes an image sensor array402comprising image senor units on chips with the same or different chip sizes, detector control logic404, memory406, and analog and/or digital readout electronics408. Computer410may be connected to detector control logic404for provision of control commands and receipt of digital image signals and the like. The image sensor array may include any number of individual image sensor units, for example, one or more of image sensor units100,200,300as shown inFIGS.1-3. A number of image sensor units are fabricated on a same die to form an image sensor chip. An image sensor chip may have chip level control logic for internal/external communication and control. Detector control logic404, for example, may dynamically address and control any individual sensor unit at any time. Detector control logic404may also specify the readout pattern for the sensor unit, for example pixel binning modes and/or pixel readout sequence, and the readout sequence for the units in the array402at detector level, for example, read out one unit a time, or multi units simultaneously to achieve high frame rate. Memory406is used to store specific readout patterns for execution by the detector control logic404. Analog/digital readout electronics408provides digitized signal from the image sensor units to the detector to complete the acquisition of an image. To form an X-ray detector, a person of ordinary skill would understand how to deposit conversion materials (e.g. scintillators) on a fiber optic plate (“FOP”) which is then placed on top of or directly onto the active side of the imager. In one embodiment, the conversion materials are deposited directly on the active side of the imager, without the fiber optic plate in between. Referring now toFIG.5, an implementation of a large area flat panel imager500is shown. Flat panel imager500includes similar components to those shown inFIG.4. For clarity, imager control logic and memory506have been combined into one block component. A person of ordinary skill will recognize that these may be separate components. Image sensor array502includes multiple image sensor units512,514,516,522,524,526,532,534,536which can be on one or more chips. Each image sensor unit may, for example, have its own analog and/or digital readout electronics, which makes the modular units expandable for making different sizes of flat panel imagers. Each sensor unit has readout electronics513,515,517,523,525,527,533,535,537, on or off the chips. In the example ofFIG.5, image sensor units512,514,516may be connected in parallel to imager control logic and memory506via data bus510. Similarly, image sensor units522,524,526may be connected in parallel to imager control logic and memory506via data bus520, for example Image sensor units532,534,536may be connected in parallel to imager control logic and memory506via data bus530. If the image sensor unit has built-in digitizer, its readout electronics may perform the function of digital readout. If the image sensor unit outputs analog signals, its readout may perform both digitization, using a digitizer off chip, and then digital read out to the imager control logic and memory506to computer508. The imager control logic506controls every single image sensor unit in the panel directly or through the logic built in the image sensor chip. It is shown inFIG.5, each image sensor unit has its own readout electronics, either on or off the chip. In one embodiment, two or more image sensor units may share one set of the readout electronics. In effect, each image sensor unit (or set of readout electronics) may be independently selected, accessed, and configured. Referring now toFIG.6, an implementation of a large area flat panel imager600is shown. Flat panel imager600includes similar components to those described in reference toFIG.5. For clarity, imager control logic and memory606have been combined into one block component. A person of ordinary skill will recognize that these may be separate components. Image sensor array602includes multiple image sensor units612,614,616,622,624,626,632,634,636. Each image sensor unit may, for example, have its own analog and/or digital readout electronics, which makes the modular units expandable for making different sizes of flat panel imagers. Each sensor unit includes readout electronics613,615,617,623,625,627,633,635,637. In the example ofFIG.6, image sensor units612,614,616form a series daisy chain connected to imager control logic and memory606via line610and to each other via lines611, connecting image sensor units612and614, and lines618and619, connecting image sensor units614and616to intermediate image sensor units omitted fromFIG.6. Similarly, image sensor units622,624,626form a series daisy chain connected to imager control logic and memory606via line620and to each other via lines621, connecting image sensor units622and624, and lines628and629, connecting image sensor units624and626to intermediate image sensor units omitted fromFIG.6. Image sensor units632,634,636form a series daisy chain connected to imager control logic and memory606via line630and to each other via lines631, connecting image sensor units632and634, and lines638and639, connecting image sensor units634and636to intermediate image sensor units omitted fromFIG.6. If the image sensor unit has built-in digitizer, its readout electronics may perform the function of digital readout. If the image sensor unit outputs analog signals, its readout may perform both digitization, using a digitizer off chip and then digital read out to the imager control logic and memory606to computer608. The imager control logic606controls every single image sensor unit in the panel directly or through the logic built in the image sensor chip. It is shown inFIG.6, each image sensor unit has its own readout electronics, either on or off the chip. In one embodiment, two or more image sensor units share one set of readout electronics. In effect, each image sensor unit (or set of readout electronics) may be independently selected, accessed, and configured. Referring now toFIGS.7-10, various example patterns of modular image sensor units to be placed on a single die to form an image sensor chip are shown. The chip can have any number of the image sensor units, arranged in any possible pattern, on a same die. In one implementation, chip level control logic may be built in with the image sensor units to further facilitating the communication and the control of the operations of the image sensor units on the chip. These chips may then be arranged into a large area flat panel.FIG.7(a)shows a single image sensor unit per chip in a 1×1 configuration.FIG.7(b)shows a two-unit chip arranged in a 1×2 configuration or a 2×1 configuration, depending on the placement orientation.FIG.7(c)shows a three-unit chip arranged in a 1×3 configuration or a 3×1 configuration depending on the placement orientation.FIG.7(d)shows a four-unit chip arranged in a 2×2 configuration. One of ordinary skill will understand that patterns may include other dimensions, including 2×3, 3×4, 3×3, and so on and that one or more of these chip patterns could be arranged into a large area flat panel detector. For example,FIG.8shows a large area flat panel comprising a number of different sized chips. In the example shown inFIG.8, there are three 1×2 unit chips802, one 1×3 unit chip804, two 2×2 unit chips806, five 2×3 unit chips, one 2×4 unit chip810and one 3×3 unit chip806. In another example,FIG.9shows a single chip 5×6 unit flat panel image sensor array, and it may be at wafer size. In another example,FIG.10shows a large-scale single chip21-unit staircase pattern. If identical rectangular or square chips are used for an entire flat panel detector, seams formed across the imager in any direction due to the gap between the active region of chips, for example, the gap between the edges of adjacent chips, distance from the edge of the active region to the edge of the chip, may exhibit itself as a line defect in the image. If the gap is larger than the sensor pixel pitch, at least one line is lost. The lost line caused by the seam may be treated as a defect in the image. Conventionally, one may use the information obtained from the neighboring lines of pixels to recover partial information for the lost line. However, if there are too many “lost lines”, or the gap is too large, the conventional method does not work well, and defects caused by those “lost lines” will show up in the image even after post processing. One method for dealing with this problem is to randomize the seam pattern and take advantage of the image sensor unit's ability to compensate for the lost image information in an adjacent chip. An example is shown inFIG.8, described above, where the arrangement of different sized chips randomizes the location of the seams between chips. FIG.11shows another example of a randomized seam using a geometric pattern1100to ease manufacture.FIG.11(a)shows a single pattern1100with four 2×2 unit chips1102surrounding a 1×1 unit chip1104.FIG.11(b)shows an example large area flat panel detector constructed using pattern1100and additional smaller chip arrays. FIG.12shows a chip die arranged in a cross shape.FIG.12(a)shows a single width cross pattern including a total of five image sensor units, one at the center and four units surrounding the center, one on each of the right, left, top, and bottom of the center unit.FIG.12(b)is a double width cross pattern including a total of 20 image sensor units, in the same configuration as the single width described above replacing the single image sensor units with 2×2 image sensor arrays. One of ordinary skill will understand that the cross pattern chips may have any number of image sensor units. The cross pattern chips array may be arranged into a large area flat panel detector that would also solve the “lost line” problem. For example,FIG.13(a)shows an example pattern using the cross pattern chip starting at the center of the panel and adding chips to fill out the desired size of the flat panel detector.FIG.13(b)shows the full detector with all chips placed.FIG.14, for example, shows a finished flat panel detector using cross pattern chips. Referring now toFIGS.15and16, an alternative hexagonal shape for use in image sensor arrays.FIG.15(a)shows a single hexagonal unit chip.FIG.15(b)shows a hexagonal unit chip having rectangle and triangle shaped image sensor pixels.FIG.16(a)shows an example arrangement pattern of hexagonal pattern image sensor chip array that can be used to assemble a large area flat panel detector, an example of which is shown inFIG.16(b), to solve the “lost line” problem also. Referring now toFIGS.17-21, a process for manufacturing a large area imager assembly is described. Individual image sensor chips, regardless of the number of image sensor units it has on the die, are provided. For example,FIG.17shows a large-scale 8×8 array1700of image sensor units1702. The array1700may be composed of a number of different chips in different size. Alternatively, array1700may also be composed of an 8×8 array of single unit image sensor chips1702, and may be at wafer size. In any case, each square in the array1700is a single image sensor unit.FIG.18shows a structured substrate1800on which the array1700is to be mounted. The structured substrate includes openings1804for each image sensor unit. In the example shown inFIGS.17and18, there is a one to one mapping between an image sensor unit1702, regardless of the chip type or size, and each opening1804on the substrate. The pitches or footprints1802of the openings1804and that of the sensor units may match, for example. The image sensor unit sits on top of the opening and all the bumps/balls on the chip are exposed through the opening. The substrate1800can be any type of material whose coefficient of thermal expansion (“CTE”) is similar to that of the material the image sensor chip is built on, for example ceramic, glass, silicon wafer, and the like. The openings1804may be large enough to allow access to all or a desired number of the bumps/pads of the corresponding image sensor unit, and enable connections to the solder paste domes or the electronically conductive adhesive balls dispensed on a printed circuit board (“PCB”) for the assembly. The openings1804may also be small enough to hold the corresponding image sensor unit/chip on the substrate. The image sensor chip can be attached to the substrate by using ultraviolet (“UV”) curable adhesives. The openings1804may be of any shape provided the above requirements regarding size are met, for example oval, circle, rectangle, square, octagon, or any other regular or irregular shape. The thickness of the substrate1800may be sufficient to mechanically support the image sensor chips on it while guaranteeing the electrical connectivity between the chips and the PCB or the like. A person of ordinary skill will recognize that the one-to-one configuration of substrate openings1804and sensor units1702is only an example, and implementations of the present invention are not limited in this regard. For example, a substrate may have multiple openings per sensor unit or per chip. In another example, a substrate may have a single opening correspond with multiple sensor units and/or chips. Referring now toFIG.19, the packaging of an image sensor unit1900is described. In the example ofFIG.19, dummy bumps/balls1904surround the bumps/balls array1902along all the sides. The dummy bumps/balls1904are used to strengthen and reinforce the structural connection between chip and the PCB. Each image sensor chip may be, for example, packaged using any appropriate packaging method, for example ball grid array, flip chip, chip-scale packaging. Wafer/panel level packaging technology enables connecting the die with other external components, for example, using through silicon via (“TSV”) if a frontside illuminated (“FSI”) image sensor is used. TSV technology is used to increase the fill factor and is packaged with bumps/balls on the non-photosensitive side of the die for power/bias/signal connections. With a backside illuminated (“BSI”) image sensor, TSV is unnecessary for that purpose, and wafer/panel level packaging and bumping technology may be used to provide connection. In either case, the solder bumps/connections are located underneath the die. A UV curable epoxy or similar material may be used to attach the chips on the structured substrate. All the external electronics needed for the detector are mounted on a printed circuit board (“PCB”) with dispensed solder paste domes, or anisotropic conductive film (“ACF”), or electronically conductive adhesive balls on the pads for interconnecting the chips. If ACF is not used, the gap/space between the chips/substrate/PCB is filled with underfill having a coefficient of thermal expansion (“CTE”) similar to that of silicon, through through-holes on the PCB board. If ACF is used, the ACF itself can be used as underfill. The underfill provides structural and mechanical reinforcement along the all edges. Preferably, the chips of the image sensor array are assembled starting in the center of the structured substrate, fanning out to all sides to finish the rest of the assembly. Referring now toFIGS.20, the bottom side view of a panel2000which includes a structured substrate with image sensor chips attached. The footprint of each image sensor unit is indicated by the dashed lines. Openings2004, indicated by the square with solid edges, in the substrate1800, enable access to pads or bumps2006of the image sensor chips for connection to the PCB2100, shown inFIG.21.FIG.21is a top side view of PCB2100, which includes soldering pad arrays2106coupling to the corresponding image sensor units mounted on the substrate2002. Area2102of the PCB2100is the portion that is in contact with substrate2002. Each array of the soldering pads2106is located in an area2104(indicated by the square with solid edges) which matches the openings2004in the substrate. Multiple through-holes2108enable underfill to be injected into a cavity (e.g., cavity2504shown inFIG.25below) between the PCB2100and the panel2000. Pad arrays2106on the PCB2100contact bumps2006of the image sensor units/chips through the openings2004to relay the signal from the detector array to appropriate processing hardware. There are several ways to mount the panel2000to the PCB2100. A first method is to form a solder paste dome on a solder pad on the PCB2100and heating the assembly to approximately 250° C. or any other desired temperature to reflow the solder and create a permanent joint. After the reflow, underfill is injected through the through-holes2108into the cavity between the image sensor chips2002and the PCB2100. During underfilling, at least one of the through-holes is reserved for air flowing out of the closed space. A second method forms an electronically conducting adhesive epoxy ball on pad array2106and connecting the epoxy ball to contact bumps2006and cure the assembly at temperatures around 120° C., depending on the time it allows to cure. Underfill is injected through the through-holes2108into the cavity between the image sensor chips2002and the PCB2100. A third method covers the pad arrays2106with ACF and applies appropriate pressure at a temperature in the range of approximately 150-170° C., to bond the panel2000to the PCB. The third method does not require reflow soldering or underfill injection, as the ACF provides the added structural reinforcement that would otherwise be provided by the underfill. The process of mounting the finished structured panel2000onto the PCB may be aided by alignment markings on both the substrate and the PCB. Referring now toFIG.22(a), a top view of an assembled imager array2200is described. In the example ofFIG.22, the imager array2200is a 4×4 array of single unit chips for clarity. The imager array2200may be of any size and may be constructed from any number of chips of different sizes. As noted above, the substrate always has a one to one relationship between openings and image sensor units, regardless of chip size.FIG.22(b)is a cross-sectional view along the line X-X shown inFIG.22(a)and described in greater detail below in reference toFIGS.23-25. Referring now toFIG.23, a detail view of a partial cross-sectional view of the assembled imager array2300is described. Image sensor chips2302are attached to substrate2304and, through electrical contacts2308and2310, to printed circuit board (“PCB”)2306. In the case of FSI sensor technology, through-silicon vias (“TSV”)2312provide an electrical connection through the silicon die on which the image sensor unit is disposed. The electrical contacts2308and2310may be bumps/solder balls or electrical conductive adhesive paste, or any other suitable conductive material. Region2314is shown in detail inFIG.24to show the structure of the connection between the image sensor unit2402and the PCB2406. As noted above, TSV2412cuts directly through the die on which the image sensor unit2402is disposed. Electrical contact2408is formed on pad2414, while on pad2404electrical contact2410is formed. Electrical contacts2408and2414form a complete connection through which an analog or digital signal that is generated or required by the image sensor unit propagates. Referring now toFIG.25, through-holes2502are shown for the injection of underfill into cavity2504. For each cavity2504at least one through-hole on the PCB is used to inject the underfill, and at least one through-hole is reserved for letting the air out while underfilling the cavity. In one embodiment, instead of having aforementioned large openings exposing an array of electrical contacts2308, the structured substrate can have array of through-holes to expose electrical contacts of the image sensor unit and connect to the PCB. Each through-hole, for example, may correspond to an electrical contact from the image sensor array attached to the substrate. All the aforementioned assembly methods may be applied to complete the assembly of image sensor chips on the substrate and the PCB. In one embodiment, the openings in the substrate may be array of through vias conducting electrical signal from one layer to the other, as a panel size interposer between the image sensor chip array and the PCB. The imager assembly may have a single panel size interposer, or an array of interposers. All the aforementioned assembly methods may be applied to complete the assembly of image sensor chips on the interposer and the PCB. There are many advantages of the presently disclosed implementations over those of the prior art. Instead of fabricating a whole large panel or tiling several (for example, six) pieces of wafer size imagers to form a large panel, the disclosed methods and devices use small units/chips. Although a unit or chip may be at wafer size, a person of ordinary skill will recognize that cost and manufacturability considerations may indicate that smaller units are preferable. A person of ordinary skill would understand how to apply the assembly methodologies disclosed in this invention to make silicon photomultiplier (SiPM) based gamma ray detectors. While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. | 37,336 |
11942504 | An appendix is included herewith to preserve detail shown in theFIGS.9A-9B. DETAILED DESCRIPTION Examples directed to stacked chip architecture are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics of embodiments may be combined in any suitable manner in one or more examples. Throughout this specification, several terms of art are used. These terms are to take on their ordinary meaning in the art from which they come, unless specifically defined herein or the context of their use would clearly suggest otherwise. It should be noted that element names and symbols may be used interchangeably through this document (e.g., Si vs. silicon); however, both have identical meaning. To facilitate understanding, the present disclosure describes the invention in the context of complementary metal-oxide-semiconductor (“CMOS”) image sensors (CIS). However, it shall be appreciated that the invention shall not be limited to CIS, but may be applied to non-CMOS image sensors having stacked chip architecture and other semiconductor devices having stacked chip architecture. FIG.1is a functional block diagram illustrating an embodiment of a CIS100, in accordance with an embodiment of the present disclosure. CIS100may be one implementation of a semiconductor device, such as an integrated circuit having stacked device wafers, as described below. CIS100includes a pixel array104, readout circuitry108, function logic112, and control circuitry116. Pixel array104is a two-dimensional (“2D”) array of backside illuminated imaging sensors or pixels (e.g., pixels P1, P2. . . , Pn). In one embodiment, each pixel is an active pixel sensor (“APS”), such as a CMOS imaging pixel. As illustrated, each pixel is arranged into a row (e.g., rows R1to Ry) and a column (e.g., columns C1to Cx) to acquire image data of a subject (e.g., person, place, or object), which can then be used to render a 2D image of the person, place, or object. After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry108and transferred to function logic112. Readout circuitry108can include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, and/or other circuitry. Function logic112can store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or other post image effects). Such function logic112may be implemented by one or more logic elements, such as application specific integrated circuits (ASICs). Control circuitry116is coupled to pixel array104to control operational characteristics of pixel array104. In one non-limiting example, control circuitry116may be coupled to generate a global shutter signal for controlling image acquisition for each pixel (e.g., P1, P2, P3, . . . Pn). In the example, the global shutter signal simultaneously enables all pixels within pixel array104to simultaneously transfer the image charge from each respective photodetector during a single acquisition window. The control circuitry116may control other operational characteristics of pixel array104. Semiconductor devices such as CIS100ofFIG.1may be implemented in a stacked chip architecture, whereby a first semiconductor die is stacked on top of, and bonded to, a second semiconductor die. The first and second semiconductor dies may be bonded together by, for example, oxide surface level micro-bonds in the active pixel array. The first and second semiconductor dies may be bonded by hybrid bonds that achieve simultaneous metal-metal contact and dielectric-dielectric contact in the outer frame. Stacked chip architecture may advantageously reduce the form factor of the semiconductor device and enable additional features, such as permitting use of a greater photodiode-die area for photodiodes, and optimizing processing and materials of the first die for photodiodes, while optimizing processing of the second die for the supporting circuitry. FIGS.2A-2Billustrate a CIS200having stacked chip architecture in accordance with the teachings of the present disclosure. The CIS200includes a pixel die204that is stacked on top of a logic die208. In one example, the pixel die204includes a CIS pixel array similar to pixel array104ofFIG.1, and may also include other circuitry. In one example, the logic die208includes readout circuitry similar to readout circuitry108ofFIG.1, as well as a plurality of logic elements having function logic similar to function logic112ofFIG.1. In some embodiments, the logic die208may also embody control circuitry such as control circuitry116ofFIG.1. To facilitate understanding of the inventive aspects of the CIS200,FIGS.2A-2Bdo not show the pixel array, readout circuitry, function logic, and control circuitry to avoid obscuring the teachings of the present invention. However, it shall be understood that the pixel die204and logic die208may include these elements. In some embodiments, each of the pixel die and the logic die may each include additional circuitry. FIG.2Bshows a partially exploded view of the CIS200ofFIG.2A, in which the pixel die204is exploded from the logic die208for clarity. The pixel die204has a light receiving side212that, in use, faces a subject to be captured by the pixel array (e.g., a person, place, or object). The pixel die204also has a pixel bond side216that is opposite of the light receiving side212. The logic die208has a logic bond side220that faces the pixel bond side216of the pixel die204. A plurality of outer bonds224(e.g.,224a) bond the pixel die204to the logic die208around an outer region226of CIS200, which includes an outer region of the pixel die204and an outer region of the logic die208such that the outer bonds224surround an inner region228of the CIS200, which includes an inner region of the pixel die204and an inner region of the logic die208. In an embodiment, the inner region228encompasses a pixel array on the pixel die204. In the illustrated embodiment, each outer bond224is a hybrid bond that achieves simultaneous metal-metal contact and dielectric-dielectric contact between the pixel die204and the logic die208. In other embodiments, the outer bonds224may include one or more different bond types. CIS having a hybrid outer bond224may be referred to as a hybrid bond image sensor, or a hybrid bond CIS. FIG.2Cshows a partial schematic section view of the CIS200ofFIG.2Aalong section line2C through outer bonds224including outer bond224ain order to show other aspects of the CIS200. Each outer bond224has a bond height HBof at least about 1 μm, e.g., at least about 2 μm, or about 1 μm to about 3 μm. In an embodiment, the bond height H is about 1 μm. In another embodiment, the bond height HBis about 2 μm. To clarify, bond height HBis the distance between the pixel die204and the logic die208. As can be seen, adjacent outer bonds224(e.g.,224b) are separated by an air channel232. As shown inFIG.4, the air channel232(e.g.,232band232c) is fluidly connected to an air gap248between the pixel die204and the logic die208. The air gaps will be described in detail below. Returning toFIG.3, each air channel232has a width of about 150 μm to about 2000 μm. In use, each air channel232enables the exchange of air (or other gas) with the inner region228of CIS200, thereby removing thermal energy from the inner region228. In some embodiments, every air channel232is fluidly connected to an air gap. Returning toFIGS.2A-2B, the pixel die204includes a pixel oxide array236disposed on the pixel bond side216of the pixel die204. Similarly, the logic die208includes a logic oxide array240disposed on the logic bond side220of the logic die208. The pixel oxide array236and the logic oxide array240are configured to interface with each other at a plurality of inner bonds244(e.g.,244a,244b,244c) between the pixel die204and the logic die208. Together, the plurality of inner bonds244supports the pixel die204atop the logic die208and secures the x-, y-, and z-direction positions of the pixel die204relative to the logic die208. Further, the location and size of the inner bonds244impact the thermal characteristics of the pixel oxide array236and the logic oxide array240. The pixel oxide array236and the logic oxide array240facilitate the evacuation of thermal energy from between the pixel die204and the logic die208by separating the pixel die204from the logic die208. In particular, the pixel oxide array236and the logic oxide array240partially define a plurality of fluidly connected air gaps248(e.g.,248a,248b,and248cshown inFIG.2A) between the pixel die204and the logic die208. Advantageously, these fluidly connected air gaps248limit heat transfer from the logic die204to the pixel die208, and are described in detail below. Referring toFIG.3, the pixel oxide array236is at least partially formed from a plurality of raised pixel oxide features252(e.g.,252aand252b) that extend away from the pixel die204. In the illustrated embodiment, the raised pixel oxide features252form a grid having a plurality of pixel oxide vertices, although in other embodiments, the raised pixel oxide features form non-grid shapes (e.g., “islands” or “stripes,” as described below with respect toFIGS.6-7, respectively). In all embodiments, the raised pixel oxide features252may be formed by an etching process, a deposition process, or another process. An exemplary process for forming the raised pixel oxide features252is described below. Each raised pixel oxide feature extends away from the pixel die204by a height Hp of about 0.25 μm to about 1.75 μm. In an embodiment, each raised pixel oxide feature252has a height Hp of about 0.5 μm, which has been discovered to provide an advantageous level of spacing between the pixel die204and the oxide die208, when bonded with a logic oxide die as described below. Each raised pixel oxide feature252has a width Wp of about 2.0 μm to about 5.0 μm. In an embodiment, each raised pixel oxide feature252has a width Wp of about 3.0 μm, which provides an effective level of mechanical strength and stress without creating an overly-detrimental effect on insulation between the pixel die204and the logic die208. In some embodiments, different raised pixel oxide features252may have different heights Hp, widths Wp, and/or other dimension across the pixel die204, and/or relative to features of the logic oxide array240, described below. Adjacent raised pixel oxide features252are spaced apart by pitch Pp, which can range from about 10 μm to about 50 μm. In one embodiment, adjacent raised pixel oxide features252have a 33 μm pitch in both x- and y-directions, which creates air gaps (described below) that effectively insulate the pixel die204from the logic die208. In some embodiments, the x-direction pitch Ppmay vary from the y-direction pitch Pp. In some embodiments, the pitch Ppmay vary across the pixel die204. Similar to the pixel oxide array236, the logic oxide array240is formed from a plurality of raised logic oxide features256(e.g.,256aand256b) that extend away from the logic die208(hidden inFIG.3) by a height H1of about 0.25 μm to about 1.75 μm. In the illustrated embodiment, the raised logic oxide features256form a grid having a plurality of logic oxide vertices, although in other embodiments, the raised logic oxide features form non-grid shapes. In the illustrated embodiment, the raised logic oxide features256also form an outer frame (where240points inFIG.2A) that surrounds the grid and provides a foundation for the pixel oxide array. Some embodiments may not include an outer frame. The raised logic oxide features256may be formed by an etching process, a deposition process, or another process. An exemplary process for forming the raised logic oxide features256is described below. In an embodiment, each raised logic oxide feature256has a height H1of about 0.5 μm. Each raised logic oxide feature256has a width Wlof about 2.0 μm to about 5.0 μm. In an embodiment, each raised logic oxide feature256has a width Wlof about 3.0 μm. In some embodiments, different raised logic oxide features256may have different heights Hl, widths Wl, and/or other dimension across the logic die208, and/or relative to features of the pixel oxide array236. Adjacent raised logic oxide features256are spaced apart by pitch P1, which can range from about 10 μm to about 50 μm. In one embodiment, adjacent raised logic oxide features256have a 33 μm pitch in both x- and y-directions. In some embodiments, the x-direction pitch P1may vary from the y-direction pitch P1. In some embodiments, the pitch P1may vary across the logic die208. Any of the advantages described above with respect to specific dimensions of the raised pixel oxide features also apply to raised logic oxide features having those dimensions. Referring still toFIG.3, the pixel die204, logic die208, pixel oxide array236, and logic oxide array240at least partially define a plurality of fluidly connected air gaps248(e.g.,248dand248e). Each air gap248is a void between the pixel die204and the logic die208. Adjacent air gaps248are separated in the x- and y-directions by the raised pixel oxide features252and the raised logic oxide features256. In one sense, each air gap248extends in the z-direction from the pixel die204to the logic die208, and thus has a depth G=Hp+Hl. In another sense, each air gap248may be thought of as specific to the pixel die204or to the logic die208, and thus has a z-direction depth of Hp; or Hl. Considered in the first way (i.e., G=Hp+Hl), each air gap has a depth G of at least about 1 μm, about 1 μm, about 2 μm, at least about 2 μm, or about 1 μm to about 3 μm. In some embodiments, the air gap248does not have a consistent depth G. In some embodiments, the plurality of air gaps includes two or more air gaps having a different depth G. To clarify, the present disclosure refers to a plurality of air gaps248to facilitate understanding. Because each air gap248is fluidly connected, the plurality of air gaps248may be considered a single air gap having a plurality of distinct areas that are at least partially demarcated by the raised pixel oxide features252and the raised logic oxide features256. Each air gap248is a thermal insulator between the pixel die204and the logic die208. In particular, because air has a relatively low thermal conductivity (e.g., about 33.5 mW/m K at 400 K and atmospheric pressure) as compared to oxides, metals, and other solids, the space within each air gap248limits conduction of thermal energy from logic die208to pixel die204. Although the term “air gap” is utilized throughout this disclosure, the inventive structures described herein are not limited to air gaps filled with air, per se. In some embodiments, a vacuum may exist within one or more air gaps248. In some embodiments, non-air gases (e.g., inert gases) may occupy one or more air gaps248. Referring toFIG.4, each air gap248(e.g.,248f-248j) allows convection to remove thermal energy from CIS200because it is fluidly connected to an external heat sink S (e.g., ambient air) via one or more other fluidly connected air gaps248and/or air channels232. Whereas air gaps248are located within the pixel oxide array236and the logic oxide array240, air channels232are located between adjacent outer bonds224. In the illustrated embodiment, the air channels232are located in the outer region226of CIS200, whereas air gaps248are located in the inner region228of CIS200. In the illustrated embodiment, fluidly connected air gaps248are fluidly connected to heat sink S via air channels232band232c.Line F represents the fluid flow path through the air gaps248to the heat sink S. In the illustrated embodiment, fluid connections extend through the pixel oxide array236and through the logic oxide array240in at least two dimensions: across the page (i.e., fluid flow path F) and into the page. Thus, the stacked chip architecture of the present disclosure utilizes both conduction and convection to limit heat transfer from the logic chip208to the pixel chip204. FIG.5shows a top schematic view of a CIS200having stacked chip architecture in accordance with the present disclosure. The CIS200has pixel oxide array236and logic oxide array240, and a plurality of air gaps248(e.g., air gap248k). In the illustrated embodiment, air gap248k(which is formed within the pixel oxide array236) is fluidly connected to at least four separate and immediately adjacent air gaps248formed within the logic oxide array240. As discussed above, the advantages of the air gaps248relate to the lower thermal conductivity of air (or other gaseous matter/vacuum between the pixel die204and the logic die208) as compared to oxide and other solids. For this reason, the ability of the inventive structures to limit heat transfer between the logic die208and the pixel die204is inversely related to the inner bond overlap area, i.e., the sum of the areas of inner bonds244. The inner bond overlap area is the area through which thermal energy can be conducted from the logic die208to the pixel die204via the solid inner bonds244. To limit thermal conduction from the logic die208to the pixel204, the inner bond overlap area can be reduced. To reduce the inner bond overlap area, one or more of the following variables may be decreased: the raised pixel oxide feature width Wp and the raised logic oxide feature width Wl. Additionally or alternatively, to reduce the inner bond overlap area, one or more of the following variables may be increased: the raised pixel oxide feature pitch Pp and the raised logic oxide feature pitch Pl. For example, increasing the raised pixel oxide feature pitch Pp may result in fewer raised pixel oxide features252in the pixel oxide array, thereby reducing the inner bond overlap area. Likewise, increasing the raised logic oxide feature pitch Plmay result in fewer raised logic oxide features256in the pixel oxide array. In an embodiment, Ppand Plare each 33 um, and each of Wpand Wlare about 3 μm. The inner bond overlap area can also be reduced by offsetting the pixel oxide array236relative to the logic oxide array240. Specifically, the pixel oxide array236can be offset relative to the logic oxide array240along an offset vector O, which has an offset length L and an offset angle α. The offset length L can be represented by a x-component (Vx) and a y-component (Vy). Thus, L=√{square root over (Vx2+Vy2)}. Vxand Vycan each range from about 0.1 Pp(or 0.1 Pl) to about 0.9 Pp(or 0.9 Pl). Similarly, the offset length L can range from about 0.1 Pp(or 0.1 Pl) to about 0.9 Pp(or 0.9 Pl). For example, the offset length L can range from about 0.25 Pp(or 0.25 Pl) to about 0.75 Pp(or 0.75 Pl), e.g., about 0.5 Pp(or 0.5 Pl). The offset angle α can range from about 15° to about 75°. In the non-limiting embodiment ofFIG.5, the offset vector V has a half-pitch shift, i.e., Vx=0.5 Ppand Vy=0.5 Pp. Therefore, offset angle α=45°. This arrangement advantageously reduces the inner bond overlap area to those areas where the pixel oxide array236intersects the logic oxide array240(e.g., at inner bond244). The foregoing example is non-limiting, and other embodiments may have different attributes, including different Vx, Vy, and/or α. In any embodiment with a given Wp, Wl, Pp, and Pl, the pixel oxide array236may be offset relative to the bond oxide array240to reduce or minimize the inner bond overlap area. FIG.6shows a top schematic view of another image sensor600having stacked chip architecture in accordance with the teachings of the present invention. The image sensor600has a pixel oxide array604and a logic oxide array608, which are similar to the pixel oxide array236and logic oxide array240described above, respectively. The pixel oxide array604includes a plurality of raised pixel oxide features612. The logic oxide array608includes a plurality of raised logic oxide features616. As noted above, the raised pixel oxide features and the raised logic oxide features may form non-grid shapes. In this embodiment, the raised pixel oxide features612form a plurality of vertical “stripes.” Likewise, the raised logic oxide features616form a plurality of horizontal “stripes.” This configuration reduces the number of inner bonds620, which advantageously reduces the inner bond overlap area for improved insulation between the pixel die and the logic die. FIG.7shows a top schematic view of another image sensor700having stacked chip architecture in accordance with the teachings of the present invention. The image sensor700has a pixel oxide array704, which is similar to the pixel oxide array236described above. Image sensor700also has a logic oxide array, which is located behind the pixel oxide array704. As with the other embodiments, the pixel oxide array704and the logic oxide array include a plurality of raised pixel oxide features712and a plurality of raised logic oxide features, respectively. In this embodiment, the raised pixel oxide features712and the raised logic oxide features form a plurality of “islands” having a rounded shape that facilitate fluid flow. Each pixel oxide island (e.g., formed by raised pixel oxide feature712) forms an inner bond720with a logic oxide island. Each island has a diameter δ of about 2 μm to about 5 μm and is spaced apart from adjacent islands by pitch P of about about 10 μm to about 50 μm. This configuration facilitates convection heat transfer from the image sensor700because the pixel oxide array704and logic oxide array present a reduced barrier to fluid flow (e.g., as shown by arrow F). Thus, it is easier for air to flow through the air gaps724and air channels728. In some embodiments, the plurality of islands includes islands having two or more different diameters δ. In some embodiments, the plurality of islands includes islands having two or more different shapes (e.g., square, ovular, circular, or other shape). In some embodiments, the plurality of islands includes islands that are spaced apart by two or more different pitches P. Thus, the size and location of islands can be optimized based upon the location of one or more heat sources in the image sensor700. FIG.8shows one non-limiting method for preparing a pixel die having a pixel oxide array as described above, and a logic die having a logic oxide array as described above, wherein the pixel oxide array and the logic oxide array form a plurality of inner bonds between the pixel die and the logic die. The pixel die may be prepared before, simultaneously with, or after preparing the logic die. To prepare the pixel oxide array, a pixel die having an oxide layer on the bond side is provided. At step800, a mask is then applied to an inner region of the pixel die on the bond side, the mask having the negative profile of the pixel oxide array to be formed. In other words, the mask covers parts of the oxide that will form the raised pixel oxide features. Accordingly, the mask may define the characteristics of the raised pixel oxide features, including size, location, and spacing. In an embodiment, the mask defines Wp and Pp. In an embodiment, the mask defines δpand PIsland. At step804, one or more etchants and etching steps are then utilized to etch a plurality of recesses in the oxide layer of the pixel die, the recesses corresponding to the areas not covered by the mask. The recesses may be etched to a depth Hp. At step808, after etching, the mask is removed from the pixel die. Similarly, preparing the logic oxide array entails a similar process to the pixel oxide array. A logic die having an oxide layer on the bond side is provided. At step812, a mask is then applied to an inner region of the logic die on the bond side, the mask having the negative profile of the logic oxide array to be formed. Accordingly, the mask may define the characteristics of the raised logic oxide features, including size, location, and spacing. In an embodiment, the mask defines Wland Pl. In an embodiment, the mask defines δl. At step816, one or more etchants and etching steps are then utilized to etch a plurality of recesses in the oxide layer of the logic die, the recesses corresponding to the areas not covered by the mask. The recesses may be etched to a depth Hl. At step820, after etching, the mask is removed from the logic die. At step824, the pixel oxide array and the logic oxide array are then bonded together to form a plurality of inner bonds as described above, such that each recess etched into the oxide layer of the pixel die is fluidly connected to at least one recess etched into the oxide layer of the logic die, and vice versa. Thus, the method produces a semiconductor device having stacked architecture, with a plurality of fluidly-connected air gaps separating the logic die from the pixel die. In an embodiment, bonding the pixel oxide array to the logic oxide array creates a fluid connection between a) an air channel between a plurality of adjacent outer bonds and b) the plurality of air gaps. In an embodiment, the method includes utilizing a mask that masks both the logic oxide array (or the pixel oxide array) and an air channel between a plurality of adjacent outer bonds. The foregoing process describes the steps necessary to prepare the plurality of inner bonds between the pixel oxide array and the logic oxide array in order to create a plurality of fluidly-connected air gaps. The foregoing process is not intended to limit semiconductor formation processes to only those steps. Rather, one or more additional and optional processing steps may precede or follow any of the steps described above. As compared to known stacked chip architectures—including those having uniform oxide contact between and across the dies, and those that include a metallic layer between dies—the inventive stacked chip architectures of the present disclosure significantly reduce heat transfer between the logic die (heat source) and the pixel die. This reduced heat transfer advantageously reduces Dark Image Non-Uniformity (DINU). FIG.9Aillustrates a thermal simulation for an image sensor constructed without the plurality of fluidly connected air gaps taught by the present disclosure. For reference, Appendix A-1showsFIG.9Ain color. The simulation shows the temperature variation between (and across) a logic die900and a pixel die904bonded together by a uniform oxide layer908. A heat source912is located on the logic chip900in the middle-left side of the simulation. Accordingly, temperatures are highest at the heat source912, i.e., ˜380 K. Due to conduction of thermal energy from the heat source912to the pixel die904, temperatures in the pixel die904vary from ˜345 K (12 K above ambient temperature 333 K) nearest the heat source912to about ˜343 K. The temperature 100 μm away from heat source is 337.5 K; in other words, ΔT=7.5 K. FIG.9Billustrates a thermal simulation for an image sensor constructed with an air gap916between the logic die900and the pixel die904, as taught by the present disclosure. For reference, Appendix A-2 showsFIG.9Bin color. In this embodiment, the oxide layer is not uniform across the pixel die904. Rather, the oxide layer includes two raised oxide features908a,908bthat are separated by the air gap916. As can be seen from the darker coloration of the pixel die904as compared toFIG.9A, temperatures across the pixel die904are significantly lower than in the simulation ofFIG.9A. In particular, temperatures in the pixel die904generally do not exceed ˜337 K (4 K above ambient temperature 333 K) except in a very isolated location next to the heat source912—a 67% improvement. In other words, ΔT=2.1 K—a 70% reduction. Dark Image Non-Uniformity (DINU) is a function of dark current (DC), which decreases in a non-linear (exponential) relationship as temperature decreases. Therefore, relatively small temperature reductions on the pixel die904cause exponential reductions in DC and DINU. For this reason, the image sensor simulated inFIG.9Breduces DINU across the pixel die904by approximately 70% as compared to the image sensor simulated byFIG.9A. This impressive reduction in DINU results from the air gap916, which insulates the pixel die904from the heat source912. Accordingly, image sensors of the present disclosure perform significantly better than known image sensors. The above description of illustrated examples of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. | 30,018 |
11942505 | DETAILED DESCRIPTION Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosure as recited in the appended claims. It is to be understood that “first”, “second” and similar terms used in the specification and claims are not to represent any sequence, number or importance but only to distinguish different parts. Likewise, similar terms such as “a” or “an” also do not represent a number limit but represent “at least one”. It is also to be understood that term “and/or” used in the present disclosure refers to and includes one or any or all possible combinations of multiple associated items that are listed. As shown inFIG.1, a pixel structure of a stacked image sensor of the present invention is set on a first silicon wafer, a second silicon wafer, and a third silicon wafer (Si) stacked up and down and bonded together. Wherein, the second silicon wafer is located above, the first silicon wafer is located in middle, and the third silicon wafer is located below, so as to form a three-layer wafer structure stacked up and down and bonded together. The first silicon wafer to the third silicon wafer can be formed by a bulk silicon wafer. Please refer toFIG.1. A first photodiode array and control transistors are set on the first silicon wafer. The first photodiode array is composed of a plurality of first photodiodes arranged regularly. A first isolation layer is set around each the first photodiode; that is, each the first photodiode is surrounded by a first isolation layer. Any two adjacent the first isolation layers can be arranged separately. The first isolation layer can be formed by materials such as an oxide layer, SiN and so on. The first photodiode is set around by the control transistors, which are a polysilicon (POLY) gate structure of the control transistors located surrounding the first photodiode as shown inFIG.1. The first photodiode array and the control transistors are located above on the first silicon wafer; a metal interconnect layer located below is provided on the first silicon wafer, which is below the first photodiode array and the control transistors. The metal interconnect layer can be set in one to multiple layers. For example, the metal interconnect layer illustrated comprises a three-layer structure of the metal interconnect layers M1, M2, M3set in a dielectric layer. The metal interconnect layers M1, M2, M3can be formed by interconnecting metals such as copper. Surrounding circuits are mainly used for IO, signal extraction and circuits with higher noise. Wherein, the polysilicon (POLY) and the metal interconnection layers M1, M2, M3are interconnected with the first photodiodes, which are subsequent used for electrical signal extraction of the first photodiodes and connection of a control signal. The size (width) of the first photodiodes can be 1.0˜9.0 microns, preferably 2.0 microns. Please refer toFIG.1. a second photodiode array is set on the second silicon wafer. The second photodiode array is composed of a plurality of second photodiodes arranged regularly, and number, size, position, etc. of the second photodiodes are correspondingly to the first photodiodes. The size (width) of the second photodiode can be 1.0˜9.0 microns, preferably 2.0 microns. The first photodiodes and the second photodiodes can be a cubic shape. A second isolation layer is set around each the second photodiode; that is, each the second photodiode is surrounded by the second isolation layer. Any two adjacent the second isolation layers can be arranged separately. The second isolation layer can be formed by materials such as an oxide layer, SiN and so on. Please refer toFIG.1. The second silicon wafer and the first silicon wafer are stacked up and down and bonded together. Wherein, The upper surface of each the first photodiode in the first photodiode array is exposed and flush with the upper surface of the first silicon wafer. The upper surface of each the second photodiode in the second photodiode array is exposed and flush with the upper surface of the second silicon wafer; the lower surface of each the second photodiode is exposed and flush with the lower surface of the second silicon wafer. The upper surface of each the first photodiode is aligned with and bonded to the lower surface of the correspondingly second photodiode. Simultaneously, The upper surface of the first isolation layer is flush with the upper surface of the first photodiode, that is, the upper surface of the first isolation layer is flush with the upper surface of the first silicon wafer; the upper surface of the second isolation layer is flush with the second photosensitive, and the lower surface of the second isolation layer is flush with the lower surface of the second photodiode, that is, the upper and lower surfaces of the second isolation layer are respectively flush with the upper and lower surfaces of the second silicon wafer. The upper surface of the first isolation layer around each the first photodiode is aligned with and bonded to the correspondingly lower surface of the second isolation layer around each the second photodiode. Simultaneously, The upper surface of the silicon layer of the first silicon wafer other than the surfaces occupied by the first photodiodes and the first isolation layer on the first silicon wafer are aligned with and bonded to the correspondingly lower surface of the silicon layer of the second silicon wafer other than the surfaces occupied by the second photodiodes and the second isolation layer on the second silicon wafer. Please refer toFIG.1. The first photodiodes and the second photodiodes are bonded to form third photodiodes, that is, the third photodiodes are formed by bonding the second photodiodes and the first photodiodes up and down, which makes sizes of photodiodes of the pixel structure of the stacked image sensor of the present invention increase exponentially, so as to form the junction depths of the third photodiodes are greater than that photosensitive depth of required near-infrared sensitivity. TSVs are also set in the second silicon wafer and the first silicon wafer. The TSVs pass from the upper surface of the second silicon wafer through the second silicon wafer into the first silicon wafer and contact the polysilicon (POLY) of the control transistors on the first silicon wafer. Meanwhile, a PAD layer is set on the upper surface of the second silicon wafer, the upper ends of the TSVs are connected to the PAD layer, and the lower ends are connected to the polysilicon (POLY) of the control transistors. TSVs are used to lead out a chip signal of the stacked image sensor from the PAD layer to off-chip by vertically metal interconnection. Please refer toFIG.1. The third silicon wafer is arranged below the first silicon wafer; the lower surface of the first silicon wafer and the upper surface of the third silicon wafer are stacked up and down and bonded together. Wherein, an oxide layer and a metal interconnect layer can also be provided on the upper surface of the third silicon wafer, when bonding with the first silicon wafer, both of the oxide layers are aligned and bonded, and both of the metal interconnection layers are aligned and bonded, so as to bond the lower surface of the first silicon wafer with the upper surface of the third silicon wafer. The following describes in detail a preparation method for a pixel structure of a stacked image sensor according to the present invention through specific embodiments and accompanying drawings. Please refer toFIG.2-8. The preparation method for a pixel structure of a stacked image sensor of the present invention can be used to preparing the pixel structure of the stacked image sensor described above, and comprises following steps: Please refer toFIG.2. Step S01: providing a first silicon wafer, for example, a bulk silicon wafer (wafer), performing a CMOS standard process to form a first photodiode array on the front side of the first silicon wafer (corresponding to the direction of the lower surface of the first silicon wafer inFIG.1, same applies below); and a first isolation layer is formed around and on the bottom of each the first photodiode in the first photodiode array, which wraps the first photodiodes completely from sides and bottom. A control transistor is formed correspondingly around the first photodiode, which including a polysilicon (POLY) gate structure to form the control transistor. Metal interconnect layers M1˜M3are formed on the front surfaces of the first photodiode array and the control transistor. Please refer toFIG.3. Step S02: providing a second silicon wafer, performing a CMOS standard process to form a second photodiode array on the front surface of the second silicon wafer (corresponding to the direction of the lower surface of the second silicon wafer inFIG.1, same applies below); and a second isolation layer is formed around and on the bottom of each the second photodiode in the second photodiode array, which wraps the second photodiode completely from sides and bottom. Please refer toFIG.4. Step S03: flipping (turning down) the first silicon wafer to turn the front side of the first silicon wafer face down, that is, the first photodiode array and the poly-silicon of the control transistor on the first silicon wafer are located above and the metal interconnect layers M1˜M3are located below. Please refer toFIG.5. Step S04: aligning the front surface of the first silicon wafer with the front surface of the third silicon wafer (corresponding to the direction of the upper surface of the third silicon wafer inFIG.1, same applies below) and performing a bonding process. The bonding process comprises aligning and bonding the surface of the oxide layer (or SiN) exposed on the front surface of the first silicon wafer with the surface of the oxide layer (or SiN) exposed on the front surface of the third silicon wafer, aligning and bonding the surface of the connecting layer M3with the surface of the metal interconnect layer (not shown) exposed on the front surface of the third silicon wafer, and aligning and bonding other surface exposed of the bulk silicon wafer on the front surface of the first silicon wafer with other surface exposed of the bulk silicon wafer on the front surface of the third silicon wafer. The bonding process between the first silicon wafer and the third silicon wafer can be performed by a through-silicon vias (TSV) bonding or a hybrid bonding (hybrid-bonding). Please refer toFIG.6. Step S05: performing a thinning process on the bonded silicon wafer, that is, performing the thinning process on the back surface of the first silicon wafer (corresponding to the direction of the upper surface of the first silicon wafer inFIG.1, same applied below), for example, performing a CMP process, polishing to a depth to reach the first photodiodes and removing the first isolation layer at the bottoms of the first photodiodes (the upper side inFIG.6) completely, so as to expose the bottoms of the first photodiodes completely. Please refer toFIG.7. Step S06: aligning the front surface of the second silicon wafer with the back surface of the first silicon wafer and then performing a bonding process. The bonding process comprises aligning and bonding the surface of the oxide layer (or SiN) exposed on the front surface of the first silicon wafer with the surface of the oxide layer (or SiN) exposed on the front surface of the third silicon wafer, aligning and bonding the surfaces of the second photodiodes exposed on the front surface of the second silicon wafer with the surfaces of the first photodiodes exposed on the back surface of the first silicon wafer, aligning and bonding the surface of the second isolation layer exposed on the front surface of the second silicon wafer with the surface of the first isolation layer exposed on the back surface of the first silicon wafer, and aligning and bonding other surfaces exposed of the bulk silicon wafer on the front surface of the second silicon wafer with other surfaces exposed of the bulk silicon wafer on the front surface of the first silicon wafer. The bonding process between the first silicon wafer and the second silicon wafer can be performed by a through-silicon vias (TSV) bonding or a hybrid bonding (hybrid-bonding). Please refer toFIG.8. Step S08: performing a thinning process on the bonded silicon wafer, that is, performing the thinning process on the back surface of the second silicon wafer (corresponding to the direction of the upper surface of the second silicon wafer inFIG.1, same applied below), for example, performing a CMP process, polishing to a depth to reach the second photodiodes and removing the second isolation layer at the bottom of the second photodiodes (the upper side inFIG.8) completely, so as to expose the bottom of the first photodiode completely, and near-infrared lights incident from above can penetrate from the second photodiodes to the first photodiodes. Step S09: then, forming through silicon vias (TSV) in the second silicon wafer and the first silicon wafer, and metal filling of the through silicon vias is performed, so as to connect the lower ends of the TSVs with the poly-silicon (POLY) gate structure of the control transistor on the first silicon wafer, and expose the upper ends of the TSVs to the back surface of the second silicon wafer. Step S10: finally, a PAD layer is formed on the back surface of the second silicon wafer, the PAD layer is connected to the upper ends of the TSVs, all process steps are completed, and the pixel structure of the stacked image sensor of the present invention are formed as shown in FIG. Please refer toFIG.9, which shows a comparison graph of quantum efficiency in a R (red) light region between pixel structures of the present invention and the existing image sensor. As shown inFIG.9, an abscissa is wavelength (nm), and an ordinate is quantum efficiency (%). A curve 1 represents a quantum efficiency response curve of a pixel structure of a stacked image sensor of the present invention, and a curve 2 represents a quantum efficiency response curve of a pixel structure of the existing image sensor. It can be seen from the figure that in red bands, especially near-infrared bands (above 850 nm), the pixel structure of the stacked image sensor proposed by the present invention have better near-infrared response characteristics. In summary, the present invention adopts the bonding processes to stack the first silicon wafer to the third silicon wafer up and down; wherein, the first photodiode array is provided on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting the backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, which has very good photosensitive performance, so as to balance the near-infrared quantum efficiency and the small pixel size. Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure here. This application is intended to cover any variations, uses, or adaptations of the disclosure following the general principles thereof and including such departures from the disclosure as come within known or customary practice in the art. It is intended that the specification and embodiments be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims. It will be appreciated that the disclosure is not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. It is intended that the scope of the disclosure only be limited by the appended claims. | 16,957 |
11942506 | DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference signs will be used for the same elements or elements having the same functions in the description, and redundant descriptions will be omitted. First, a configuration of a solid state imaging device1according to the present embodiment will be described with reference toFIGS.1to4.FIG.1is a view illustrating a planar configuration of the solid state imaging device.FIG.2is a view illustrating a cross-sectional configuration of the solid state imaging device.FIG.2illustrates the cross-sectional configuration of the solid state imaging device taken along line II-II inFIG.1.FIG.3is a schematic view illustrating a photosensitive region.FIG.4is a view illustrating a change in electrical potential formed in the solid state imaging device. As illustrated inFIG.1, the solid state imaging device1includes a light receiving section3, a plurality of input gate sections4, a plurality of transfer sections7, and a shift register9. The shift register9is a charge output section. The solid state imaging device1is, for example, an implanted CCD linear image sensor. The light receiving section3includes a plurality of photoelectric conversion sections5. The plurality of photoelectric conversion sections5is distributed in a first direction D1. The photoelectric conversion section5is positioned between the input gate section4and the transfer section7. The photoelectric conversion section5has a long rectangular shape in which a length in a second direction D2is about 1 to 500 times a length in the first direction D1. In the present embodiment, the first direction D1is a direction along an opposing direction of two long sides of the photoelectric conversion section5. The first direction D1includes both a positive direction and a negative direction along the Y axis. The second direction D2is a direction along an opposing direction of two short sides of the photoelectric conversion section5. The second direction D2includes both a positive direction and a negative direction along the X axis. The second direction D2intersects with the first direction D1. The first direction D1and the second direction D2are orthogonal to each other. Each of the photoelectric conversion sections5includes one photosensitive region6. The photosensitive region6generates a charge in response to incident light. The photosensitive region6has a rectangular shape defined by two long sides and two short sides in plan view. The plurality of photosensitive regions6is distributed in the first direction D1. The plurality of photosensitive regions6is disposed in an array in a one-dimensional direction with the first direction D1as the one-dimensional direction. One photosensitive region6constitutes one pixel in the light receiving section3. The photosensitive region6includes a plurality of impurity regions having different impurity concentrations. As illustrated inFIG.3, the photosensitive region6includes a pair of first impurity regions11and one second impurity region12. The impurity concentration of the second impurity region12is higher than the impurity concentration of the first impurity region11. The photosensitive region6includes a pair of short sides6aand6band a pair of long sides6cand6d. The photosensitive region6is defined by the pair of short sides6aand6band the pair of long sides6cand6d. In the photosensitive region6, the second impurity region12is provided from the short side6ato the short side6bin the second direction D2. In the present embodiment, the second impurity region12is continuously provided from the short side6ato the short side6b. The short side6ais one end positioned away from the transfer section7in the second direction D2. The short side6bis another end positioned closer to the transfer section7in the second direction D2. The second impurity region12includes one end and the other end. The second impurity region12is positioned between the pair of first impurity regions11in the first direction D1. The pair of short sides6aand6boppose each other in the second direction D2. The second direction D2is a direction in which the pair of short sides6aand6boppose each other. The pair of long sides6cand6doppose each other in the first direction D1. The first direction D1is a direction in which the pair of long sides6cand6doppose each other. The second impurity region12has a shape that is line-symmetric with respect to a center line G1of the photosensitive region6along the second direction D2in plan view. A planar shape of the second impurity region12is line-symmetric with respect to the center line G1. The center line G1is parallel to the pair of long sides6cand6dof the photosensitive region6and is positioned such that distances from the long sides6cand6dare equivalent. In the present embodiment, “equivalent” not only means that values are exactly the same, but also means that a difference in values is included in the range of a measurement error or a preset minute difference. The expression that the planar shape of the second impurity region12is line-symmetric with respect to the center line G1represents that regions, obtained by dividing the second impurity region12by the center line G1and positioned with the center line G1therebetween, are mirror-symmetric and the regions has the same area and number. The center line G1is a mirror symmetry axis. A width W of the second impurity region12in the first direction D1increases in the direction from the short side6atoward the short side6b. Hereinafter, the width W in the first direction D1is referred to as the “width W”. The width W increases monotonously in a narrow sense from the short side6atoward the short side6b. A detailed description of the shape of the second impurity region12will be described later with reference toFIG.5. The second impurity region12forms an electrical potential gradient that increases in the positive X-axis direction inFIG.1in the photosensitive region6. The electrical potential gradient increases in the direction from the short side6atoward the short side6b. This electrical potential gradient allows transfer of the charge generated in the photosensitive region6in the direction from the short side6ato the short side6bin the photosensitive region6. The charge that has reached the short side6bis discharged from the photosensitive region6. Hereinafter, the direction from the short side6ato the short side6bis referred to as a “transfer direction TD”. As illustrated inFIG.1, one input gate section4corresponds to one photosensitive region6(one photoelectric conversion section5). The input gate section4is disposed closer to the short side6aof the corresponding photosensitive region6. The input gate section4is distributed with the corresponding photosensitive region6(photoelectric conversion section5) in the second direction D2in such a manner as to be adjacent to the short side6aof the corresponding photosensitive region6. The input gate section4applies a predetermined electrical potential to a region of the photosensitive region6closer to the short side6a. One transfer section7corresponds to one photosensitive region6(one photoelectric conversion section5). The transfer section7is disposed closer to the short side6bof the corresponding photosensitive region6. The transfer section7is distributed with the corresponding photosensitive region6(photoelectric conversion section5) in the second direction D2n such a manner as to be adjacent to the short side6bof the corresponding photosensitive region6. The transfer section7is positioned between the photosensitive region6and the shift register9. The transfer section7acquires the charge discharged from the photosensitive region6, and transfers the acquired charge to the shift register9. The shift register9is disposed such that each of the transfer sections7is positioned between each of the photosensitive regions6and the shift register9. The shift register9is disposed closer to the short side6bof the photosensitive region6. The shift register9is adjacent to the plurality of transfer sections7in the second direction D2. The shift register9acquires the charge transferred from each of the transfer sections7, transfers the charge in the negative Y-axis direction, and sequentially outputs the charge to an amplifier A. The amplifier A converts the charge output from the shift register9into a voltage, and outputs the converted voltage to the outside of the solid state imaging device1as an output of the photosensitive region6. Isolation regions are disposed between the adjacent photosensitive regions6and between the adjacent transfer sections7. The isolation region disposed between the photosensitive regions6electrically isolates the adjacent photosensitive regions6from each other. The isolation region disposed between the transfer sections7electrically isolates the adjacent transfer sections7. The solid state imaging device1includes a semiconductor substrate10. The light receiving section3, the plurality of input gate sections4, the plurality of transfer sections7, and the shift register9are formed on the semiconductor substrate10. In the present embodiment, the semiconductor substrate10is a silicon substrate. As illustrated inFIG.2, the semiconductor substrate10includes a main part layer10A serving as a base of the semiconductor substrate10and surface layers22to27. The surface layers22to27are disposed on one side of the main part layer10A. The main part layer10A is a p type semiconductor layer. The surface layer22is an n++type semiconductor layer. The surface layer23is an n−type semiconductor layer. As illustrated inFIG.3, the surface layer24includes a pair of n type semiconductor layers24aand one n+type semiconductor layer24b. The surface layer24includes one p+type conductor layer24c. The n type semiconductor layer24aand the n+type semiconductor layer24bare formed on the main part layer10A. The p+type conductor layer24cis formed on the n type semiconductor layer24aand the n+type semiconductor layer24b. As illustrated inFIG.3, the n+type semiconductor layer24bis positioned between the pair of n type semiconductor layers24ain the first direction D1. The surface layer25is an n−type semiconductor layer. The surface layer26is an n type semiconductor layer. The surface layer27is a p+type semiconductor layer. The respective conductivity types of the p type and the n type may be switched so as to be opposite to the above-described conductivity types. A high impurity concentration is indicated by “+” attached to a conductivity type. A low impurity concentration indicated by “−” attached to a conductivity type. The low impurity concentration also includes an aspect in which some impurities of a conductivity type attached with “−” are compensated with impurities of a conductivity type opposite to the conductivity type attached with “−” so that a low impurity concentration is obtained in appearance. The number of “+” indicates the degree of concentration of impurities of a conductivity type attached with “+”, and the larger number of “+” means a higher concentration of impurities of the conductivity type attached with “+”. The n type impurity is, for example, N, P, or As. The p type impurity is, for example, B or Al. A pn junction is formed at an interface between the main part layer10A, and the n type semiconductor layer24aand the n+type semiconductor layer24b. The n type semiconductor layer24aand the n+type semiconductor layer24bconstitute the photosensitive region6that generates the charge with incident light. The n type semiconductor layer24aconstitutes the first impurity region11in the photosensitive region6. A shape of the first impurity region11corresponds to a shape of the n type semiconductor layer24a. The n+type semiconductor layer24bconstitutes the second impurity region12. A shape of the second impurity region12corresponds to a shape of the n+type semiconductor layer24b. A concentration of n type impurities in the n+type semiconductor layer24bis higher than a concentration of n type impurities in the n type semiconductor layer24a. As illustrated inFIG.3, the width W of the n+type semiconductor layer24bgradually increases in the transfer direction TD. The width of the n+type semiconductor layer24bis small in the region near the short side6ain the transfer direction TD. In a case in which the width of the n+type semiconductor layer24bis small, an influence of the fringing electric field from the n type semiconductor layer24apositioned on both sides of the n+type semiconductor layer24bis large. Therefore, a potential of the surface layer24is shallow in the region near the short side6ain the transfer direction TD. The width of the n+type semiconductor layer24bis large in the region near the short side6bin the transfer direction TD. In a case in which the width of the n+type semiconductor layer24bis large, the influence of the fringing electric field from the n type semiconductor layer24apositioned on both sides of the n+type semiconductor layer24bis small. Therefore, a potential of the surface layer24is deep in the region near the short side6bin the transfer direction TD. Consequently, the surface layer24is formed with an inclination of a potential that gradually becomes deeper in the transfer direction TD as illustrated inFIG.4. The surface layer24is formed with an electrical potential gradient that gradually increases in the transfer direction TD. A plurality of electrodes41,42, and43is disposed on an insulating layer20. The electrode41is formed on a region of the insulating layer20corresponding to the surface layer23. The electrode41is disposed on the surface layer23such that the insulating layer20is positioned between the electrode41and the surface layer23. The electrode41and the surface layer23constitute the input gate section4. A drive circuit101gives a signal IG to the electrode41. The electrical potential of the surface layer23is determined in response to the signal1G. The electrical potential of the surface layer23is determined to be lower than the electrical potential of the surface layer24. Therefore, the potential of the surface layer23is shallower than the potential of the surface layer24, that is, the potential of the photosensitive region6as illustrated inFIG.4. The drive circuit101is controlled by a control device102. The electrode42is formed on a region of the insulating layer20corresponding to the surface layer25. The electrode42is disposed on the surface layer25such that the insulating layer20is positioned between the electrode42and the surface layer25. The electrode42and the surface layer25constitute the transfer section7. The drive circuit101gives a signal TG to the electrode42. The electrical potential of the surface layer25changes in response to the signal TG. The potential of the surface layer25becomes shallower than the potential of the surface layer24as illustrated in (a) ofFIG.4or becomes deeper than the potential of the surface layer24as illustrated in (b) ofFIG.4. Due to the change of the potential of the surface layer25, the transfer section7acquires a charge from the photosensitive region6, and sends the acquired charge to the shift register9. The electrode43is formed on a region of the insulating layer20corresponding to the surface layer26. The electrode43is disposed on the surface layer26such that the insulating layer20is positioned between the electrode43and the surface layer26. The electrode43and the surface layer26constitute the shift register9. The drive circuit101gives a signal PH to the electrode43. The electrical potential of the surface layer26changes in response to the signal PH. The potential of the surface layer26becomes shallower than the potential of the surface layer24and deeper than the potential of the surface layer25as illustrated in (a) ofFIG.4, or becomes deeper than the potential of the surface layer24and deeper than the potential of the surface layer25as illustrated in (b) ofFIG.4. The shift register9acquires a charge from the transfer section7based on the change of the potential of the surface layer26. The shift register9sends the acquired charge to the amplifier A. The surface layer27electrically isolates the surface layers22to26from other portions of the semiconductor substrate10. The above-described isolation region can be formed by the surface layer27. The electrodes41to43are, for example, polysilicon films. The insulating layer20is, for example, a silicon oxide film. Next, the shape of the second impurity region12will be described with reference toFIG.5.FIG.5is a view used for describing the width of the second impurity region. Here, (a) ofFIG.5is a schematic view illustrating the photosensitive region. In (a) ofFIG.5, the photosensitive region6having a length L in the second direction D2is divided into n sections in the second direction D2. Here, n is an integer of two or more. Here, (a) ofFIG.5illustrates widths W0, . . . , Wk, . . . , and Wnof the second impurity region12in sections L1, . . . , Lk, . . . , and Lnobtained by dividing the photosensitive region6into n sections. Here, k is an integer of two or more and n−1 or less. Each of the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12is, for example, a width at a position closest to the short side6bin each of the sections L1, Lk, . . . , and Ln. In this case, the widths W1, . . . , Wk, . . . , and Wnare the maximum widths in the respective sections L1, . . . , Lk, . . . , and Ln. The width W0is the minimum width in the section L1. The width W0is the width of the second impurity region12at the most upstream end (short side6a) in the transfer direction TD in the photosensitive region6. The widths W1, . . . , Wk, . . . , and Wnare not limited to the maximum widths in the respective sections L1, . . . , Lk, . . . , and Ln. For example, each of the widths W1, . . . , Wk, . . . , and Wnmay be an average value of widths in each of the sections L1, . . . , Lk, . . . , and Ln. Further, (b) ofFIG.5is a graph illustrating the electrical potential gradient of the photosensitive region6in each of the sections L1, . . . , Lk, . . . , and Ln. The horizontal axis in (b) ofFIG.5indicates a position [μm] along the transfer direction TD in the photosensitive region6. The vertical axis in (b) ofFIG.5indicates the maximum electrical potential [V] at each position. In the present embodiment, each of the sections L1, . . . , Lk, . . . , and Lnis each of sections obtained by equally dividing the photosensitive region6into n sections in the second direction D2. Although the equal division means division into equal amounts, each of the sections L1, . . . , Lk, . . . , and Lnis not necessarily divided to have the completely equal amount. For example, the width of each of the sections L1, . . . , Lk, . . . , and Lnin the second direction D2may include a measurement error or a minute difference within a preset range of ±several μm. As illustrated in (a) ofFIG.5, increase rates ΔW1, . . . , ΔWk, . . . , and ΔWnof the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12(ΔWk=Wk−Wk−1) gradually increase in the transfer direction TD. Within each of the sections L1, . . . , Lk, . . . , and Ln, the width W of the second impurity region12gradually increases from the upstream side to the downstream side in the transfer direction TD. Within each of the sections L1, . . . , Lk, . . . , and Ln, the width W of the second impurity region12monotonously increases in the transfer direction TD from the upstream end to the downstream end in the transfer direction TD. As illustrated in (b) ofFIG.5, the widths W1, . . . , Wk, . . . , and Wnof the second impurity regions12are set such that each of electrical potential differences ΔV1, . . . , ΔVk, . . . , and ΔVn(ΔVk=Vk−Vk−1) between adjacent sections among the sections L1, . . . , Lk, . . . , and Ln. becomes constant; provided, however, that ΔV1=V1−V0. Here, V0is an electrical potential of the photosensitive region6at the position of the width W0. Next, a process of determining the shape of the second impurity region12will be described. First, procedures for obtaining the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12will be described. In a first procedure, an electrical potential of the photosensitive region6for each predetermined notch width is calculated. At this electrical potential calculation, a model of a solid state imaging device including the second impurity region12with a constant notch width in the transfer direction TD is used. The maximum electrical potential of the photosensitive region6is calculated for each predetermined notch width. The notch width is, for example, a value within the range of 0.8 μm to 6.1 μm. Calculation results are illustrated inFIG.6.FIG.6is a graph illustrating the electrical potential of the photosensitive region for each notch width. The horizontal axis inFIG.6indicates the notch width [μm]. The vertical axis inFIG.6indicates the maximum electrical potential [V] of the photosensitive region6corresponding to the notch width. The vertical axis inFIG.6indicates that the maximum electrical potential increases in the upward direction, and the maximum electrical potential decreases in the downward direction. In a second procedure, the electrical potential in the range corresponding to the range where the notch width is 0.8 μm to 6.1 μm is equally divided into n sections in the graph ofFIG.6. In the example illustrated inFIG.6, for example, the electrical potential is equally divided into twelve sections. The notch widths at the respective equally dividing points (1, . . . , k, . . . and n) of the electrical potential are read from the graph ofFIG.6. The read notch widths at the respective equally dividing points are defined as the respective widths W1, . . . , Wk, . . . , and Wnof the second impurity region12corresponding to the respective equally dividing points. In the example illustrated inFIG.6, the width W1is 0.9 μm, the width W2is 1.0 μm, the width W3is 1.1 μm, the width W4is 1.2 μm, the width W5is 1.35 μm, and the width W6is 1.5 μm. The width W7is 1.7 μm, the width W8is 2.0 μm, the width W9is 2.4 μm, the width W10is 2.9 μm, the width W11is 3.9 μm, and the width W12is 6.1 μm. With the above procedure, the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12in which the electrical potential difference in the photosensitive region6between adjacent sections is constant are obtained. The width W0is set to the minimum value of the notch width. In the example illustrated inFIG.6, the width W0is 0.8 μm. Next, the shape of the second impurity region12is determined based on the obtained widths W0, W1, . . . , Wk, . . . , and Wn. As illustrated in the graph ofFIG.7, the respective widths W0, W1, . . . , Wk, . . . , and Wnof the second impurity region12are plotted so as to correspond to the respective equally dividing points of n=0,1, . . . , k, . . . , and n.FIG.7is a graph illustrating a width of the second impurity region at each equally dividing point.FIG.7is a graph illustrating the widths W0, W1, . . . , Wk, . . . , and Wnof the second impurity region12corresponding to the respective equally dividing points. The horizontal axis inFIG.7indicates the equally dividing points of n=0,1, . . . , k, . . . , and n. The vertical axis inFIG.7indicates a position [μm] with respect to the center of each of the widths W0, W1, . . . , Wk, . . . , and Wn. The vertical axis inFIG.7is also a boundary position between the second impurity region12and the first impurity region11. The shape of the second impurity region12is determined by the above procedure. The shape of the second impurity region12is a shape similar to the shape illustrated in the graph ofFIG.7regardless of the length of the photoelectric conversion section5in the transfer direction TD. Next, a simulation was performed to illustrate that the shape of the second impurity region12is suitable for improvement of charge transfer efficiency. Simulation results are illustrated inFIGS.8to10.FIG.8is a view illustrating a simulation model of the photosensitive region including the second impurity region in the present embodiment.FIG.9is a graph illustrating a potential of the photosensitive region in a three-dimensional space. The potential illustrated inFIG.9is a simulation result of the potential of the photosensitive region6using the model illustrated inFIG.8. InFIG.9, the positive x-axis direction corresponds to the transfer direction TD. InFIG.9, the y-axis direction corresponds to a width direction of the second impurity region12. The vertical axis inFIG.9indicates the maximum electrical potential. The vertical axis inFIG.9indicates that the maximum electrical potential decreases in the upward direction, and the maximum electrical potential increases in the downward direction. The vertical axis inFIG.9indicates that the potential is shallower in the upward direction and the potential is deeper in the downward direction.FIG.10is a graph illustrating an electrical potential gradient in the transfer direction.FIG.10is a graph obtained by plotting a value of the electrical potential corresponding to a position of the photosensitive region6in the transfer direction TD based on the simulation result illustrated inFIG.9. The horizontal axis ofFIG.10indicates the position [μm] of the photosensitive region6in the transfer direction TD. InFIG.10, the positive x-axis direction is the transfer direction TD. The vertical axis inFIG.10indicates the maximum electrical potential [V] of the photosensitive region6at each position. The vertical axis inFIG.10indicates that the maximum electrical potential decreases in the upward direction, and the maximum electrical potential increases in the downward direction. As illustrated inFIG.10, the electrical potential gradient in the photosensitive region6is approximately constant over approximately the entire region along the transfer direction TD of the photosensitive region6. The charge generated in the photosensitive region6is transferred along the electrical potential gradient having an approximately constant slope. Therefore, the charge generated in the photosensitive region6is transferred efficiently. Next, it is illustrated with reference toFIGS.11and12that the shape of the second impurity region12of the present embodiment is suitable for improvement of charge transfer efficiency as compared with reference examples.FIG.11is a schematic view illustrating second impurity regions in the reference examples. In a reference example illustrated in (a) ofFIG.11, an increase rate of a width W of a second impurity region50A is constant from a short side6ato a terminal region EA near a short side6b. The increase rate of the width W in the terminal region EA is larger than the increase rate of the width W from the short side6ato the terminal region EA. In a reference example illustrated in (b) ofFIG.11, an increase rate of a width W of a second impurity region50B is constant from a short side6ato a short side6b. FIG.12is a graph of the electrical potential gradient in the photosensitive region compared between the present embodiment and the reference examples. A characteristic60ainFIG.12illustrates an electrical potential gradient in the photosensitive region6including the second impurity region12of the above-described embodiment, and corresponds to a characteristic illustrated inFIG.10. A characteristic60binFIG.12indicates an electrical potential gradient in the photosensitive region6including the second impurity region50A. The characteristic60bindicates the electrical potential gradient obtained from simulation results of the potential of the photosensitive region6using a simulation model of the photosensitive region6including the second impurity region50A. A characteristic60cinFIG.12indicates an electrical potential gradient in the photosensitive region6including the second impurity region50B. The characteristic60cindicates the electrical potential gradient obtained from simulation results of the potential of the photosensitive region6using a simulation model of the photosensitive region6including the second impurity region50B. In a case in which the photosensitive region6includes the second impurity region50A or the second impurity region50B as illustrated inFIG.12, the electrical potential gradient decreases from the center to a terminal end of the photosensitive region6in the transfer direction TD. Specifically, a portion where the electrical potential gradient decreases is generated at a position of 100 μm to 200 μm. In contrast, in a case in which the photosensitive region6includes the second impurity region12of the above-described embodiment, the electrical potential gradient is approximately constant without generating a portion where the electrical potential gradient decreases. In the present embodiment, the photosensitive region6tends not to generate the portion where the electrical potential gradient decreases, and efficiently transfers the charge, as compared with the reference examples. From the above, it is understood that the shape of the second impurity region12of the present embodiment is suitable for improvement of the charge transfer efficiency. FIG.13is a graph of an actually measured value of an image lag corresponding to transfer time compared between the present embodiment and the reference examples. The horizontal axis inFIG.13represents charge transfer time [μs] in the photosensitive region6. The vertical axis inFIG.13represents an image lag [%]. The image lag is an afterimage that is generated when a charge remains in the photosensitive region6since the charge is not completely transferred from the photosensitive region6. InFIG.13, each of characteristics61a,61b,61cindicates an actual measurement result of the image lag. The characteristic61aindicates the actual measurement result of the image lag in the configuration in which the photosensitive region6includes the second impurity region12. The characteristic61billustrates the actual measurement result of the image lag in the configuration in which the photosensitive region6includes the second impurity region50A. The characteristic61cillustrates the actual measurement result of the image lag in the configuration in which the photosensitive region6includes the second impurity region50B. As illustrated inFIG.13, the image lag is greatly reduced in the photosensitive region6including the second impurity region12of the present embodiment as compared with the photosensitive region6including the second impurity region50A or50B. Therefore, the actually measured values also indicate that the present embodiment improves the charge transfer efficiency of the photosensitive region6as compared with the reference examples. As described above, the width W of the second impurity region12increases in the transfer direction TD in the present embodiment. Therefore, the photosensitive region6is formed with the electrical potential gradient in which the electrical potential increases from the short side6atoward the short side6b. The second impurity region12has the shape that is line-symmetric with respect to the center line G1of the photosensitive region6in plan view. Therefore, charges are transferred with the same efficiency in the photosensitive region6regardless of positions where the charges are generated. The increase rate ΔW1, . . . , ΔWk, . . . , and ΔWnof the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12in the respective sections L1, . . . , Lk, . . . , and Ln, obtained by dividing the photosensitive region6into n sections in the second direction D2, gradually increase in the transfer direction TD. In this case, a shape of the second impurity region12is a shape in which a portion having a small electrical potential gradient tends not to be generated in the photosensitive region6. Each of the photoelectric conversion sections5efficiently transfers the charge. Therefore, the solid state imaging device1improves charge transfer efficiency. In the present embodiment, the widths W1, . . . , Wk, . . . , and Wnof the second impurity region12in the respective sections L1, . . . , Lk, . . . , and Lnare set such that the electrical potential difference of the photosensitive region6between the adjacent sections among the sections L1, . . . , Lk, . . . , and Lnis constant. In this case, the electrical potential gradient in the photosensitive region6is approximately constant. Therefore, each of the photoelectric conversion sections5transfers the charge more efficiently. In a case in which the photoelectric conversion section5has a long shape and a transfer distance in the photosensitive region6becomes long, it is advantageous that the electrical potential gradient in the photosensitive region6is approximately constant. Although the embodiment of the present invention has been described as above, the present invention is not necessarily limited to the above-described embodiment, and various modifications can be made in a range without departing from a gist thereof. For example, the shape of the second impurity region12is not limited to the shape illustrated in the above embodiment. The second impurity region12can have various shapes as illustrated inFIG.14.FIG.14illustrates a plurality of second impurity regions12A to12E, which are modifications of the second impurity region12.FIG.14is a schematic view illustrating the modifications of the second impurity region. InFIG.14, a boundary position of each of sections obtained by dividing the photosensitive region6into a plurality of sections is indicated by a two-dot chain line. In the above embodiment, the second impurity region12is provided from the short side6ato the short side6bin the photosensitive region6. The second impurity region12is not necessarily provided from the short side6ain the photosensitive region6. For example, as illustrated in (a) ofFIG.14, the second impurity region12A is provided from a vicinity of the short side6ato the short side6b. The vicinity of the short side6ameans, for example, a position away from the short side6ato such an extent that movement of a charge is not hindered. In this case, the vicinity of the short side6ais a position separated by about several μm from the short side6a. In (a) ofFIG.14, the vicinity of the short side6ais a position closer to the short side6bthan the short side6ain the section L1, which is the closest to the short side6aamong the sections L1, . . . , Lk, . . . , and Ln. In the above embodiment, each of the sections L1, . . . , Lk, . . . , and Lnis each of the sections obtained by equally dividing the photosensitive region6into n sections, and the widths of the respective sections L1, . . . , Lk, . . . , and Lnin the second direction D2are equivalent. The widths of the respective sections L1, . . . , Lk, . . . , and Lnin the second direction D2are not necessarily equivalent. As illustrated in (b) ofFIG.14, each of the sections is, for example, each of sections obtained by dividing the photosensitive region6such that a width in the second direction D2becomes gradually narrower in the transfer direction TD. Even in this case, an increase rate of a width of a second impurity region12B in each of the sections becomes gradually larger in the transfer direction TD. In the above embodiment, the width W of the second impurity region12increases within each of the sections L1, . . . , Lk, . . . , and Ln. The width W of the second impurity region12does not necessarily increase within each of the sections L1, . . . , Lk, . . . , and Ln. For example, as illustrated in (c) ofFIG.14, a width W of a second impurity region12C does not increase within each section, but increases at a boundary position of each of the sections. An outer shape of the second impurity region12C within each of the sections is a rectangle. In the above embodiment, the second impurity region12is constituted by one region. The second impurity region12may be constituted by a plurality of minute regions. For example, as illustrated in (d) ofFIG.14, the second impurity region12D is constituted by a plurality of minute regions12din each section. In (d) ofFIG.14, an outline of a region corresponding to the second impurity region12D is indicated by a broken line. In the section Ln, which is the closest to the short side6bamong the sections L1, . . . , Lk, . . . , and Ln, an increase rate of the width Wnof the second impurity region12may change so as to increase near the short side6b. For example, in (e) ofFIG.14, the photosensitive region6is equally divided into three sections. In a section which is the closest to the short side6bamong sections obtained by equally dividing the photosensitive region6into three sections, an increase rate of a width of the second impurity region12E is not constant but changes so as to become larger near the short side6b. The photosensitive region6may be equally divided into two sections or may be equally divided into four or more sections. The expression, “near the short side6b” means, for example, to be closer to the short side6bthan the center line CL in the second direction D2in the section that is the closest to the short side6b. Each of the photoelectric conversion sections5does not necessarily have the long shape. Each of the photoelectric conversion sections5may include a plurality of the photosensitive regions6. Each of the photoelectric conversion sections5may include a plurality of pixels. Even in a case in which the photoelectric conversion section5includes the plurality of photosensitive regions6, an electrical potential gradient of each of the photosensitive regions6becomes approximately constant, and thus, the solid state imaging device1improves the charge transfer efficiency. INDUSTRIAL APPLICABILITY The present invention can be used for a CCD linear image sensor. REFERENCE SIGNS LIST 1solid state imaging device5photoelectric conversion section6photosensitive region6ashort side6bshort side7transfer section11first impurity region12second impurity regionD1first directionD2second directionTD transfer directionG1center lineW width | 38,300 |
11942507 | To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale. For example, the heights and widths of the mesas are not drawn to scale. DETAILED DESCRIPTION Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways. The term “substrate” as used herein according to one or more embodiments refers to a structure, intermediate or final, having a surface, or portion of a surface, upon which a process acts. In addition, reference to a substrate in some embodiments also refers to only a portion of the substrate, unless the context clearly indicates otherwise. Further, reference to depositing on a substrate according to some embodiments includes depositing on a bare substrate, or on a substrate with one or more films or features or materials deposited or formed thereon. In one or more embodiments, the “substrate” means any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. In exemplary embodiments, a substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon doped silicon oxides, germanium, gallium arsenide, glass, sapphire, and any other suitable materials such as metals, metal nitrides, III-nitrides (e.g., GaN, AN, InN and alloys), metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, light emitting diode (LED) devices. Substrates in some embodiments are exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the film processing steps disclosed are also performed on an underlayer formed on the substrate, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface. The term “wafer” and “substrate” will be used interchangeably in the instant disclosure. Thus, as used herein, a wafer serves as the substrate for the formation of the LED devices described herein. Reference to a micro-LED (uLED) means a light emitting diode having one or more characteristic dimensions (e.g., height, width, depth, thickness, etc. dimensions) of less than 100 micrometers. In one or embodiments, one or more dimensions of height, width, depth, thickness have values in a range of 2 to 25 micrometers. FIG.1Ais a cross-sectional view of a stack of semiconductor layers, a metal layer (e.g., a p-contact layer), and a dielectric layer (e.g., a hard mask layer) deposited on a substrate during a step in the manufacture of a LED device according to one or more embodiments. With reference toFIG.1A, semiconductor layers104are grown on a substrate102. The semiconductor layers104according to one or more embodiments comprise epitaxial layers, III-nitride layers or epitaxial III-nitride layers. The substrate may be any substrate known to one of skill in the art. In one or more embodiments, the substrate comprises one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more embodiments, the substrate is not patterned prior to the growth of the epitaxial layer(s). Thus, in some embodiments, the substrate is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate is patterned, e.g. patterned sapphire substrate (PSS). In one or more embodiments, the semiconductor layers104comprise a III-nitride material, and in specific embodiments epitaxial III-nitride material. In some embodiments, the III-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layers104comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN) and the like. In one or more specific embodiments, the semiconductor layers104comprises a p-type layer, an active region, and an n-type layer. In one or more embodiments, the semiconductor layers104comprise a III-nitride material, and in specific embodiments epitaxial III-nitride material. In some embodiments, the III-nitride material comprises one or more of gallium (Ga), aluminum (Al), and indium (In). Thus, in some embodiments, the semiconductor layers104comprises one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), aluminum indium gallium nitride (AlInGaN) and the like. In one or more specific embodiments, the semiconductor layers104comprises a p-type layer, an active region, and an n-type layer. In one or more embodiments, the substrate102is placed in a metalorganic vapor-phase epitaxy (MOVPE) reactor for epitaxy of LED device layers to grow the semiconductor layers104. In one or more embodiments, the semiconductor layers104comprise a stack of undoped III-nitride material and doped III-nitride material. The III-nitride materials may be doped with one or more of silicon (Si), oxygen (O), boron (B), phosphorus (P), germanium (Ge), manganese (Mn), or magnesium (Mg) depending upon whether p-type or n-type III-nitride material is needed. In specific embodiments, the semiconductor layers104comprise an n-type layer104n, an active region106and a p-type layer104p. In one or more embodiments, the semiconductor layers104have a combined thickness in a range of from about 2 μm to about 10 μm, including a range of from about 2 μm to about 9 μm, 2 μm to about 8 μm, 2 μm to about 7 μm, 2 μm to about 6 μm, 2 μm to about 5 μm, 2 μm to about 4 μm, 2 μm to about 3 μm, 3 μm to about 10 μm, 3 μm to about 9 μm, 3 μm to about 8 μm, 3 μm to about 7 μm, 3 μm to about 6 μm, 3 μm to about 5 μm, 3 μm to about 4 μm, 4 μm to about 10 μm, 4 μm to about 9 μm, 4 μm to about 8 μm, 4 μm to about 7 μm, 4 μm to about 6 μm, 4 μm to about 5 μm, 5 μm to about 10 μm, 5 μm to about 9 μm, 5 μm to about 8 μm, 5 μm to about 7 μm, 5 μm to about 6 μm, 6 μm to about 10 μm, 6 μm to about 9 μm, 6 μm to about 8 μm, 6 μm to about 7 μm, 7 μm to about 10 μm, 7 μm to about 9 μm, or 7 μm to about 8 μm. In one or more embodiments, an active region106is formed between the n-type layer104nand the p-type layer104p. The active region106may comprise any appropriate materials known to one of skill in the art. In one or more embodiments, the active region106is comprised of a III-nitride material multiple quantum wells (MQW), and a III-nitride electron blocking layer. In one or more embodiments, a P-contact layer105and a hard mask layer108are deposited on the p-type layer104p. As shown, the P-contact layer is deposited on the p-type layer104pand the hard mask layer108is on the P-contact layer. In some embodiments, the P-contact layer105is deposited directly on the p-type layer104p. In other embodiments, not illustrated, there may be one or more additional layer between the p-type layer104pand the P-contact layer105. In some embodiments, the hard mask layer108is deposited directly on the P-contact layer105. In other embodiments, not illustrated, there may be one or more additional layers between the hard mask layer108and the P-contact layer105. The hard mask layer108and the P-contact layer105may be deposited by any appropriate technique known to the skilled artisan. In one or more embodiments, the hard mask layer108and P-contact layer105are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD). “Sputter deposition” as used herein refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, e.g. a metal, is ejected from a target that is a source onto a substrate. The technique is based on ion bombardment of a source material, the target. Ion bombardment results in a vapor due to a purely physical process, i.e., the sputtering of the target material. As used according to some embodiments herein, “atomic layer deposition” (ALD) or “cyclical deposition” refers to a vapor phase technique used to deposit thin films on a substrate surface. The process of ALD involves the surface of a substrate, or a portion of substrate, being exposed to alternating precursors, i.e. two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to the alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a processing chamber, and the substrate, or portion of the substrate, is exposed separately to the precursors. As used herein according to some embodiments, “chemical vapor deposition (CVD)” refers to a process in which films of materials are deposited from the vapor phase by decomposition of chemicals on a substrate surface. In CVD, a substrate surface is exposed to precursors and/or co-reagents simultaneous or substantially simultaneously. As used herein, “substantially simultaneously” refers to either co-flow or where there is overlap for a majority of exposures of the precursors. As used herein according to some embodiments, “plasma enhanced atomic layer deposition (PEALD)” refers to a technique for depositing thin films on a substrate. In some examples of PEALD processes relative to thermal ALD processes, a material may be formed from the same chemical precursors, but at a higher deposition rate and a lower temperature. A PEALD process, in general, a reactant gas and a reactant plasma are sequentially introduced into a process chamber having a substrate in the chamber. The first reactant gas is pulsed in the process chamber and is adsorbed onto the substrate surface. Thereafter, the reactant plasma is pulsed into the process chamber and reacts with the first reactant gas to form a deposition material, e.g. a thin film on a substrate. Similarly to a thermal ALD process, a purge step maybe conducted between the delivery of each of the reactants. As used herein according to one or more embodiments, “plasma enhanced chemical vapor deposition (PECVD)” refers to a technique for depositing thin films on a substrate. In a PECVD process, a source material, which is in gas or liquid phase, such as a gas-phase III-nitride material or a vapor of a liquid-phase III-nitride material that have been entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiated gas is also introduced into the chamber. The creation of plasma in the chamber creates excited radicals. The excited radicals are chemically bound to the surface of a substrate positioned in the chamber, forming the desired film thereon. In one or more embodiments, the hard mask layer108may be fabricated using materials and patterning techniques which are known in the art. In some embodiments, the hard mask layer108comprises a metallic or dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN) and combinations thereof. The skilled artisan will recognize that the use of formulas like SiO, to represent silicon oxide, does not imply any particular stoichiometric relationship between the elements. The formula merely identifies the primary elements of the film. In one or more embodiments, the P-contact layer105may comprise any suitable metal known to one of skill in the art. In one or more embodiments, the P-contact layer105comprises silver (Ag). FIG.1Bis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1B, the hard mask layer108and P-contact layer105are patterned to form at least one opening110in the hard mask layer108and P-contact layer105, exposing a top surface104tof the semiconductor layers104and sidewalls108s,105sof the hard mask layer108and P-contact layer105, respectively. In one or more embodiments, the hard mask layer108and P-contact layer105is patterned according to any appropriate patterning technique known to one of skill in the art. In one or more embodiments, the hard mask layer108and P-contact layer105are patterned by etching. According to one or more embodiments, conventional masking, wet etching and/or dry etching processes can be used to pattern the hard mask layer108and the P-contact layer105. In other embodiments, a pattern is transferred to the hard mask layer108and P-contact layer105using nanoimprint lithography. In one or more embodiments, the substrate102is etched in a reactive ion etching (RIE) tool using conditions that etch the hard mask layer108and P-contact layer105efficiently but etch the p-type layer104pvery slowly or not at all. In other words, the etching is selective to the hard mask layer108and P-contact layer105over the p-type layer104p. In a patterning step, it is understood that masking techniques may be used to achieve a desired pattern. FIG.1Cis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1C, inner spacers112are deposited on top surface104tof the semiconductor layers104and the sidewalls108s,105sof the hard mask layer108and P-contact layer105. The inner spacers112may comprise any appropriate material known to one of skill in the art. In one or more embodiments, the inner spacers112comprise a dielectric material. Deposition of the material that forms the inner spacers is typically done conformally to the substrate surface, followed by etching to achieve inner spacers on the sidewalls108s,105s, but not on the top surface104bof the semiconductor layers104. As used herein, the term “dielectric” refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the inner spacers112include, but are not limited to, oxides, e.g., silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides, e.g., silicon nitride (Si3N4). In one or more embodiments, the dielectric inner spacers112comprise silicon nitride (Si3N4). In other embodiments, the inner spacers112comprise silicon oxide (SiO2). In some embodiments, the inner spacers112composition is non-stoichiometric relative to the ideal molecular formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxycarbides (e.g. silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g. silicon oxycarbonitride (SiNCO)). In some embodiments, the inner spacers112may be a distributed Bragg reflector (DBR). As used herein, a “distributed Bragg reflector” refers to a structure (e.g. a mirror) formed from a multilayer stack of alternating thin film materials with varying refractive index, for example high-index and low-index films. In one or more embodiments, the inner spacers112are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, the inner spacers112have a thickness in a range of from about 200 nm to about 1 μm, for example, about 300 nm to about 1 μm, about 400 nm to about 1 μm, about 500 nm to about 1 μm, about 600 nm to about 1 μm, about 700 nm to about 1 μm, about 800 nm to about 1 μm, about 500 nm to about 1 μm, about 200 nm to about 900 nm, 300 nm to about 900 nm, about 400 nm to about 900 nm, about 500 nm to about 900 nm, about 600 nm to about 900 nm, about 700 nm to about 900 nm, about 800 nm to about 900 nm, about 200 nm to about 800 nm, 300 nm to about 800 nm, about 400 nm to about 800 nm, about 500 nm to about 800 nm, about 600 nm to about 800 nm, about 700 nm to about 800 nm, about 200 nm to about 700 nm, about 300 nm to about 700 nm, about 400 nm to about 700 nm, about 500 nm to about 700 nm, about 600 nm to about 700 nm, about 200 nm to about 600 nm, about 300 nm to about 600 nm, about 400 nm to about 600 nm, about 500 nm to about 600 nm, about 200 nm to about 500 nm, about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm. FIG.1Dis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1D, the semiconductor layers104are etched to form at least one mesa, for example a first mesa150aand a second mesa150b. In the embodiment illustrated inFIG.1D, the first mesa150aand the second mesa150bare separated by a trench111, which will be referred to as a trench111. Each trench111has sidewalls113. FIG.1Eis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1E, outer spacers114are deposited on the sidewalls113of the trenches111. The outer spacers114may comprise any appropriate material known to one of skill in the art. In one or more embodiments, the outer spacers114comprise a dielectric material. The dielectric material insulates the sidewalls of the P-type layer104p(sidewall104s) and the active region106(sidewall106s) from metal that is deposited in the trenches111, as described below with respect toFIG.1I. Deposition of the material that forms the outer spacers is typically done conformally to the substrate surface, followed by etching to achieve outer spacers on the side walls of the trenches but not the bottom of the trench or top of the hard mask layer. In one or more embodiments, the outer spacers114may be oxides, e.g., silicon oxide (SiO2), aluminum oxide (Al2O3), nitrides, e.g., silicon nitride (Si3N4). In one or more embodiments, the outer spacer114comprises silicon nitride (Si3N4). In other embodiments, the outer spacer114comprises silicon oxide (SiO2). In some embodiments, the outer spacers114may be a distributed Bragg reflector (DBR). In one or more embodiments, the outer spacers114are deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD). FIG.1Nis an enlarged view of a portion of the stack ofFIG.1Eindicated by the dotted line circle1N inFIG.1E. In one or more embodiments, a dark space or dark space gap117is formed between adjacent edges105eof P-contact layers105on the first mesa150aand the second mesa150bas shown inFIG.1B,FIG.1E, andFIG.1N. In one or more embodiments, the dark space gap117formed between the adjacent edges105eof P-contact layers105on the first mesa150aand the second mesa150bis in a range from 10 μm to 0.5 μm, or in a range from 9 μm to 0.5 μm, or in a range of from 8 μm to 0.5 μm, or in a range of from 7 μm to 0.5 μm, or in a range of from 6 μm to 0.5 μm, or in a range of from 5 μm to 0.5 μm, or in a range of from 4 μm to 0.5 μm, or in a range of from 3 μm to 0.5 μm. In other embodiments, the dark space gap117formed between the adjacent edges105eof P-contact layer105on the first mesa150aand the second mesa150bis in a range of from 10 μm to 4 μm, for example, in a range of from 8 μm to 4 μm. In embodiments of the LED device100each of the plurality of spaced mesas150a,150bcomprise a P-contact layer105that is both conductive and reflective extending across a portion of each of the plurality of the mesas150a,150band including an edge105e, and the trench111between each of the plurality of spaced mesas results in a pixel pitch in a range of from 1 μm to 100 μm, including from 40 μm to 100 μm, 41 μm to 100 μm, and all values and subranges therebetween, and a dark space gap117between adjacent edges of the P-contact layer of less than 20% of the pixel pitch. In some embodiments, the pixel pitches is in a range of from 5 μm to 100 μm, 10 μm to 100 μm or 15 μm to 100 μm. In some embodiments, the dark space gap117between adjacent edges of the P-contact layer is greater than 1% of the pixel pitch, and less than 20%, 19%, 18%, 17%, 16%, 15%, 14%, 13%, 12%, 11%, 10%, 9%, 8%, 7%, 6% or 5% of the pixel pitch, when the pixel pitch is in a range of from 10 μm to 100 μm. In one or more embodiments, each of the spaced mesas150a,150bincludes sidewalls104s, each having a first segment104s1and a second segment104s2(shown inFIG.1M). The first segment104s1defines an angle “a” (as shown inFIG.1N) in a range of from 60 degrees to 90 degrees from a horizontal plane129that is parallel with the N-type layer104nand the P-type layer104p. In some embodiments, the angle “a” is in a range of from 60 to 85 degrees, 60 to 80 degrees, 60 to 75 degrees, 60 to 70 degrees, 65 to 90 degrees 65 to 85 degrees, 65 to 80 degrees, 65 to 75 degrees, 65 to 70 degrees, 70 to 90 degrees, 70 to 85 degrees, 70 to 80 degrees, 70 to 75 degrees, 75 to 90 degrees, 75 to 85 degrees, 75 to 80 degrees, 80 to 90 degrees or 80 to 85 degrees. In one or more embodiments, the second segments104s2of the sidewalls form an angle with a top surface of a substrate upon which the mesas are formed in a range of from 75 to less than 90 degrees. FIG.1Fis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1F, the semiconductor layers104are etched and the trenches111are expanded (i.e. the depth of the trenches is increased) to expose a top surface102tof the substrate102. In one or more embodiments, the etching is selective such that the outer spacers114remain on the sidewalls of the trenches111. In one or more embodiments, the trench111has a bottom111band sidewalls113. In one or more embodiments, the trench111having a depth from a top surface104tof the semiconductor layer forming the mesas in a range of from about 0.5 μm to about 2 μm. FIG.1Gis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1G, the first mesa150aand second mesa150bare patterned to form a via opening116on the top surface of the mesa, exposing a top surface of the semiconductor layers104and/or a top surface of the P-contact layer105. In one or more embodiments, the first mesa150aand second mesa150bcan be patterned according to any appropriate technique known one of skill in the art, such as a masking and etching process used in semiconductor processing. FIG.1His a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1H, a reflective liner130is deposited on the substrate on: the sidewalls113and bottom111bof the trenches111, the sidewalls of the outer spacer114, and along the hard mask layer108surface, and the top surface of the semiconductor layers104and/or the top surface of the P-contact layer105. The reflective liner130may comprise any appropriate material known to one of skill in the art. In one or more embodiments, the reflective liner130comprises aluminum (Al). In one or more embodiments, the reflective liner130is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, the deposition of the reflective liner130is selective deposition such that the reflective liner130is only deposited on the sidewalls113of the trench111and the sidewalls of the outer spacer114. FIG.1Iis a cross-sectional view of the stack after a step in the manufacture of a LED device according to one or more embodiments. With reference toFIG.1I, an electrode metal118, e.g., to yield an N-contact material118nand/or a P-metal material plug118pand/or a conducting metal118cin a final product, is deposited on the substrate, including on top of the mesas150a,150b, in the via opening116, and in the trenches111. The electrode metal118can comprise any appropriate material known to the skilled artisan. In one or more embodiments, the electrode metal118comprises copper and the electrode metal material118is deposited by electrochemical deposition (ECD) of the copper. FIG.1Jis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1J, the electrode metal118is planarized, etched, or polished. Electrode metal118yields N-contact material118nand a P-metal material plug118p. As used herein, the term “planarized” refers to a process of smoothing surfaces and includes, but is not limited to, chemical mechanical polishing/planarization (CMP), etching, and the like. FIG.1Kis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1K, a passivation layer120is deposited on the substrate. In some embodiments, the passivation layer120is deposited directly on the planarized N-contact material118n, the planarized P-metal material plug118p, the top surface of the inner spacer112, the top surface of the outer spacer114, and the top surface of the hard mask layer108. In other embodiments, there may be one or more additional layers between the passivation layer120and the planarized N-contact material118n, the planarized P-metal material plug118p, the top surface of the inner spacer112, the top surface of the outer spacer114, and the top surface of the hard mask layer108. In some embodiments, the passivation material comprises the same material as the hard mask layer108. In other embodiments, the passivation layer120comprises a material distinct from the hard mask layer108. In one or more embodiments, the passivation layer120may be deposited by any suitable technique known to one of skill in the art. In one or more embodiments, the passivation layer120is deposited by one or more of sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, the passivation layer120may be comprises by any suitable material known to one of skill in the art. In one or more embodiments, the passivation layer120comprises a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN) and combinations thereof. FIG.1Lis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1L, the passivation layer120is patterned to form at least one opening122, exposing a top surface of the P-metal material plug118p. Two openings122are shown. The passivation layer120may be patterned using any suitable technique known to one of skill in the art including, but not limited to, lithography, wet etching, or dry etching. FIG.1Mis a cross-sectional view of the stack after a step in the manufacture of a LED device100according to one or more embodiments. With reference toFIG.1M, under bump metallization (UBM) material forms an under bump metallization (UBM) layer124a, which is deposited in the openings122. As used herein, “under bump metallization (UBM)” refers to the metal layer which is required for connecting a die to a substrate with solder bumps for flip-chip packages. In one or more embodiments, the UBM layer124amay be a patterned, thin-film stack of material that provides an electrical connection from the die to a solder bump, provides a barrier function to limit unwanted diffusion from the bump to the die, and provides a mechanical interconnection of the solder bump to the die through adhesion to the die passivation and attachment to a solder bump pad. The UBM layer124amay comprise any suitable metal known to the skilled artisan. In one or more embodiments, the UBM layer124amay comprise gold (Au). In one or more embodiments, under bump metallization (UBM) may be achieved by any technique known to one of skill in the art including, but not limited to, a dry vacuum sputter method combined with electroplating. In one or more embodiments, a dry vacuum sputter method combined with electroplating consists of multi-metal layers being sputtered in a high temperature evaporation system. InFIG.1M, the UBM layer124ais patterned (e.g. by masking and etching). The UBM layer124amay be patterned using any suitable technique known to one of skill in the art including, but not limited to, lithography, wet etching, or dry etching. The patterning of the UBM layer124aprovides anode pads in contact with the P-metal material plug118pover the P-contact layer105at the first mesa150aand the second mesa150b. FIG.1Ois a cross-sectional view of a finished LED device according to one or more embodiments. With reference toFIG.1O, the finished LED device100comprises the features shown inFIG.1M, and further includes a common electrode (common cathode)140formed at an end of the device100as viewed in cross-section. UBM material has been patterned to provide anode pads124ain contact with the P-metal material plug118pover the P-contact layer105at the first mesa150aand the second mesa150b. Common cathode140comprises a conducting metal118c. Under bump metallization (UBM) material also provides cathode pads124cin contact with the common cathode140, patterned analogously to the UBM layers124a. In one or more embodiments, the plurality of spaced mesas150a,150bdefines a matrix of pixels, and the matrix of pixels are surrounded by the common electrode140. In one or more embodiments, the common electrode140is a pixelated common cathode comprising a plurality of semiconductor stacks surrounded by a conducting metal. In one or more embodiments, the semiconductor stacks comprise semiconductor layers104, which according to one or more embodiments comprise epitaxial layers, III-nitride layers or epitaxial III-nitride layers. In a specific embodiment, one or more semiconductor layers comprise GaN. To fabricate a pixelated common electrode, processing proceeds in accordance withFIGS.1A to1F, at which point rather than preparing via openings116as shown inFIG.1G, a portion of the mesas are etched to expose the top surface of the semiconductor layers. Turning toFIG.5A, third mesa150cand fourth mesa150dare etched to expose the top surface104tof the semiconductor layers104, thereby forming semiconductor stacks151cand151d, respectively. That is, the inner spacers112, the hard mask layer108, and the P-contact layer105on the third mesa150cand the fourth mesa150dare removed. Sidewalls of the third mesa150cand the fourth mesa150dare exposed upon etching of the outer spacers114. Thereafter, processing of the third mesa150cand the fourth mesa150dproceeds in accordance with:FIG.1Hto add the reflective liner layer130,FIG.1Ito deposit the electrode materials118, andFIGS.1J-1M, to form a pixelated common cathode as shown inFIG.5B. In the embodiment ofFIG.5B, a finished LED device101comprises the features shown inFIG.5A, thereafter processed according toFIGS.1H-1M, andFIG.1M, including a common electrode (common cathode)141formed at an end of the device101as viewed in cross-section. UBM material has been patterned to provide anode pads124ain contact with the P-metal material plug118pover the P-contact layer105at the first mesa150aand the second mesa150b. The third mesa150cand fourth mesa150ddefines or forms semiconductor stacks151cand151d, respectively, surrounded by conducting metal118c. The semiconductor stacks151cand151dare inactive in that they do not generate light. Under bump metallization (UBM) material also provides cathode pads124cin contact with the common cathode141, patterned analogously to the UBM layers124a. FIG.2shows a top plan view of an LED monolithic array200comprising a plurality of pixels155(of which155aand155bare examples) which are defined or formed by a plurality of spaced mesas as described herein with respect toFIGS.1A-10. For example, the first mesa150adefines or forms a first pixel155aand the second mesa150bdefines or forms a second pixel155b. The third mesa150cand fourth mesa150dforms or provides a inactive pixels, or semiconductor stacks151cand151d. The pixels155are arranged in grid and connected by a common cathode140. In one or more embodiments, an array of spaced mesas comprises an arrangement of mesas in two directions. For example, the array can comprise an arrangement of 2×2 mesas, 4×4 mesas, 20×20 mesas, 50×50 mesas, 100×100 mesas, or n1×n2 mesas, where each of n1 and n2 is a number in a range of from 2 to 1000, and n1 and n2 can be equal or not equal. One or more embodiments provide light emitting diode (LED) device100comprising a plurality of spaced mesas150a,150bdefining pixels155a,155b, each of the plurality of spaced mesas150a,150bcomprising semiconductor layers104, the semiconductor layers including an N-type layer104n, an active region106, and a P-type layer104p, each of the spaced mesas150a,150bhaving a height H and a width W, where the height H is less than or equal to the width W. The LED device100further comprises a metal118in a trench111in the form of a trench111between each of the plurality of spaced mesas150a,150b, the metal118providing optical isolation between each of the spaced mesas150a,150b, and electrically contacting the N-type layer104nof each of the spaced mesas150a,150balong sidewalls of the N-type layers104n. In one or more embodiments, the LED device100comprises a first dielectric material114which insulates sidewalls of the P-type layer104p(sidewall104s) and the active region106(sidewall106s) from the N-contact material118n. A P-metal material plug118pis in electrical communication with the p-contact layer105. In embodiments of the LED device100each of the plurality of spaced mesas150a,150bcomprise a conductive p-contact layer105extending across a portion of each of the plurality of the mesas150a,150band including an edge105e, and the trench111between each of the plurality of spaced mesas results in a pixel pitch in a range of from 1 μm to 100 μm, including 51 μm to 100 μm, and all values and subranges therebetween, and a dark space gap117between adjacent edges of the p-contact layer of less than 20% of the pixel pitch. In some embodiments, the pixel pitches is in a range of from 5 μm to 100 μm, 10 μm to 100 μm or 15 μm to 100 μm. In other embodiments, the dark space gap117is in a range of from 10 μm to 0.5 μm, in a range of from 10 μm to 4 μm, for example, in a range of from 8 μm to 4 μm. As used herein according to one or more embodiments and as shown inFIG.1O, “pixel pitch” means a distance or spacing119between a center “C” of adjacent pixels provided or formed by mesas150a,150b. In other words, pixel pitch refers to a center-to-center spacing119of adjacent pixels. In one or more embodiments, the center-to-center spacing for an array of LEDs as shown inFIG.2is the same for adjacent pixels155a,155band all adjacent pixels of the array200. In one or more embodiments, the pixel pitch is in a range of from 5 μm to 100 μm, for example in a range of from 5 μm to 90 μm, 5 μm to 80 μm, 5 μm to 70 μm, 5 μm to 60 μm, 5 μm to 50 μm, 5 μm to 40 μm, 5 μm to 30 μm, 10 μm to 90 μm, 10 μm to 80 μm, 10 μm to 70 μm, 10 μm to 60 μm, 10 μm to 50 μm, 10 μm to 40 μm, 10 μm to 30 μm, 20 μm to 90 μm, 20 μm to 80 μm, 20 μm to 70 μm, 20 μm to 60 μm, 20 μm to 50 μm, 20 μm to 40 μm, 20 μm to 30 μm, 30 μm to 90 μm, 30 μm to 80 μm, 30 μm to 70 μm, 30 μm to 60 μm, 30 μm to 50 μm, 30 μm to 40 μm, 40 μm to 90 μm, 40 μm to 80 μm, 40 μm to 70 μm, 40 μm to 60 μm, 40 μm to 50 μm, 50 μm to 90 μm, 50 μm to 80 μm, 50 μm to 70 μm, or 50 μm to 60 μm. In one or more embodiments, a light emitting diode (LED) device comprises: a plurality of mesas defining pixels, each of the plurality of mesas comprising semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer, each of the mesas having a height less than or equal to their width; an N-contact material in a space between each of the plurality of mesas, the N-contact material providing optical isolation between each of the mesas, and electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layers; a dielectric material which insulates sidewalls of the P-type layer and the active region from the N-contact material; and each of the plurality of mesas comprising a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and the space between each of the plurality of mesas results in a pixel pitch in a range of from 10 μm to 100 μm and a dark space gap between adjacent edges of the p-contact layer of less than 20% of the pixel pitch. In one or more embodiments, the p-contact layer comprises a reflective metal. The LED device of claim1, wherein the pixel pitch is in a range of from 40 μm to 100 μm. In one or more embodiments, the dark space gap between adjacent edges of the p-contact layer of less than 10% of the pixel pitch. The LED device of claim1, wherein the semiconductor layers are epitaxial semiconductor layers having a thickness in a range of from 2 μm to 10 μm. In one or more embodiments, the dielectric material is in a form of outer spacers comprising a material selected from the group consisting of SiO2, AlOx, and SiN, having a thickness in a range of from 200 nm to 1 μm. In one or more embodiments, the N-contact material has a depth from a top surface of the mesa in a range of from 0.5 μm to 2 μm. In one or more embodiments, each of the mesas includes sidewalls, each having a first segment and a second segment, wherein the first segments of the sidewalls define an angle in a range of from 60 degrees to 90 degrees from a horizontal plane that is parallel with the N-type layer and the P-type layer, the second segments of the sidewalls form an angle with a top surface of a substrate upon which the mesas are formed in a range of from 75 to less than 90 degrees. In one or more embodiments, a light emitting diode (LED) device comprises: a plurality of mesas defining pixels, each of the plurality of mesas comprising semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer, each of the mesas having a height less than or equal to their width; a metal in a space between each of the plurality of mesas, the metal providing optical isolation between each of the mesas, and electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layers; a dielectric material which insulates sidewalls of the P-type layer and the active layer from the metal; and each of the plurality of mesas comprising a p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and the space between each of the plurality of mesas results in a pixel pitch in a range of from 10 μm to 100 μm and a dark space gap between adjacent edges of the p-contact layer in a range of from 4 μm to 10 μm. the plurality of mesas comprises an array of mesas. In one or more embodiments, the dark space gap is in a range of from 4 μm and to 8 μm. In one or more embodiments, the pixel pitch is in a range of from 40 μm to 100 μm. One or more embodiments of the disclosure provide a method of manufacturing an LED device.FIGS.3A-3Fillustrate process flow diagrams according to various embodiments. With reference toFIG.3A, the method200comprises at operation202fabrication of a substrate. Substrate fabrication can include depositing a plurality of semiconductor layers including, but not limited to an N-type layer, an active region, and a P-type layer on a substrate. Once the semiconductor layers are deposited on the substrate, a portion of the semiconductor layers are etched to form trenches and a plurality of spaces mesas. At operation204, a die is fabricated. Die fabrication includes depositing a (first) dielectric material to insulate sidewalls of the epitaxial layers (e.g., N-type layer, active region, and P-type layer), which is followed by deposition of an electrode metal in the trenches, e.g., spaces between each of the plurality of spaced mesas. In some embodiments, the die fabrication further includes depositing a P-contact layer and a hard mask, forming a current spreading film, plating a p-metal material plug, followed by under bump metallization (UBM). At operation204, a die is fabricated. At operation206, optional microbumping may occur on a complementary metal oxide semiconductor (CMOS) backplane. At operation208, optionally, backend processing occurs such that the die is connected to the CMOS backplane, underfill is provided, laser lift off occurs, followed by optional phosphor integration. With reference toFIG.3B, in one embodiment, the method210comprises at212depositing a plurality of semiconductor layers including an N-type layer, an active region, and a P-type layer on a substrate. At214, the method further comprises etching a portion of the semiconductor layers to form trenches and a plurality of spaced mesas defining pixels, each of the plurality of spaced mesas comprising the semiconductor layers and each of the spaced mesas having a height less than or equal to their width. At216, the method comprises depositing a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. At218, the method comprises depositing an electrode metal in a space between each of the plurality of spaced mesas, the metal providing optical isolation between each of the spaced mesas, and electrically contacting the N-type layer of each of the spaced mesas along sidewalls of the N-type layers. In one or more embodiments, each of the plurality of spaced mesas comprising a conductive p-contact layer extending across a portion of each of the plurality of mesas and including an edge, and the space between each of the plurality of spaced mesas results in a pixel pitch in a range of from 1 μm to 100 μm and dark space gap between adjacent edges of the p-contact layer of less than 20% of the pixel pitch. In some embodiments, the pixel pitches is in a range of from 5 μm to 100 μm, 10 μm to 100 μm or 15 μm to 100 μm. In other embodiments, the dark space gap is in a range of from 10 μm to 0.5 μm, or in a range of from 10 μm to 4 μm, for example, in a range of 8 μm to 4 μm. As used herein, according to one or more embodiments, the term “dark space gap” refers to the space between adjacent edges of the p-contact layer where no light is reflected. In some embodiments, the method comprises forming an array of spaced mesas. In some embodiments, the metal comprises a reflective metal. In some embodiments, the dark space gap is in a range of from to 10 μm to 0.5 μm or in a range of from 10 μm to 4 μm. In some embodiments, the plurality of spaced mesas is arranged into pixels, and the pixel pitch in a range of from 5 μm to 100 μm or from 30 μm to 50 μm. In some embodiments, the semiconductor layers104have a thickness in a range of from 2 μm to 10 μm. With reference toFIG.3C, further to operations212to218ofFIG.3B, a method220comprises at operation222forming a common electrode. In one or more embodiments, the common electrode comprises a plurality of semiconductor stacks surrounded by a conducting metal. In one or more embodiments, the semiconductor stacks comprise one or more layers of GaN. With reference toFIG.3D, further to operations212to218ofFIG.3B, a method224comprises at operation226deposition of a current spreading layer. Some method embodiments comprise forming a multilayer composite film on the P-type layer, the multilayer composite film comprising the current spreading layer, a P-contact layer on a first portion of the current spreading layer, and a (second) dielectric layer on a second portion of the current spreading layer below a hard mask layer. In one or more embodiments, the multilayer composite film comprises a current spreading layer on the P-type layer, the current spreading layer having a first portion and a section portion; a dielectric layer on the second portion of the current spreading layer; a via opening defined by sidewalls in the dielectric layer and the first portion of the current spreading layer; and a P-contact layer in the via opening on: the first portion of the current spreading layer, the sidewalls of the dielectric layer, and at least a portion of a surface of the dielectric layer. In one or more embodiments, the multilayer composite film is formed directly on the P-type layer. In other embodiments, there may be one or more additional layers formed between the multilayer composite film and the P-type layer. In one or more embodiments, the multilayer composite layer includes a guard layer on the P-contact layer. Some method embodiments comprising depositing a current spreading layer over the P-type layer. Other method embodiments comprise depositing a current spreading layer over the P-type layer; depositing a dielectric layer on the current spreading layer; forming a via opening in the dielectric layer; conformally depositing a P-contact layer in the via opening and on a top surface of the dielectric layer; depositing a guard layer on the P-contact layer; depositing a hard mask layer on the guard layer; forming an opening in the hard mask layer; depositing a liner layer in the opening in the hard mask layer; and depositing a P-metal material plug on the liner layer, the P-metal material plug having a width; and forming a passivation layer on the P-metal material plug, the passivation layer having an opening therein defining a width, the width of the opening in the passivation layer is less than the width of a combination of the P-metal material plug and the liner layer in the opening. With reference toFIG.3E, some method embodiments comprise a method230including at operation232, depositing a hard mask layer above or over the P-type layer. At operation234, an opening is formed in the hard mask layer. At operation236, in one or more embodiments, a liner layer is deposited in the opening in the hard mask layer. At operation238, in one or more embodiments, a P-metal material plug is deposited on the liner layer, the P-metal material plug having a width, and, at operation240, a passivation layer is formed on the P-metal material plug, the passivation layer having an opening therein defining a width, the width of the opening in the passivation layer less than the width of the P-metal material plug. In one or more embodiments, a method of manufacturing a light emitting diode (LED) device comprising: depositing a plurality of semiconductor layers including an N-type layer, an active region, and a P-type layer on a substrate; depositing a hard mask layer over the P-type layer; etching a portion of the semiconductor layers and the hard mask layer to form trenches and plurality of mesas defining pixels, each of the plurality of mesas comprising the semiconductor layers and each of the mesas having a height less than or equal to their width; depositing a dielectric material in the trenches; forming an opening in the hard mask layer, and etching the semiconductor layers to expose a surface of the substrate and a sidewall of the N-type layer; depositing a liner layer on the substrate, including on surfaces of the opening in the hard mask layer, the dielectric material, the N-type layer, and substrate; depositing an electrode metal on the liner layer; planarizing the substrate to form an N-contact material electrically contacting the N-type layer of each of the mesas along sidewalls of the N-type layers, and a P-metal material plug on the liner layer in the opening of the hard mask layer, a combination of the P-metal material plug and the liner layer in the opening of the hard mask layer having a width; and forming a passivation layer on the substrate and forming openings in the passivation layer defining a width. In one or more embodiments, the width of each opening in the passivation layer is less than the width of the combination of the P-metal material plug and the liner layer. With reference to3F, some method embodiments comprise a method240, which includes at operation212, depositing semiconductor layers, for example, as described with respect toFIG.1A. Method240further comprises at operation213deposing a current spreading film or layer and/or a P-contact layer, for example, as described with respect toFIG.1A. Method240further includes at operation231, depositing and patterning a hard mask layer, for example, as described with respect toFIGS.1A-C. At operation233, trenches are formed in the semiconductor layers and dielectric material is deposited, for example, as described with respect toFIGS.1D-G. At operation234, an opening is formed in the hard mask layer, for example, as described with respect toFIG.1H. At operation236, in one or more embodiments, a liner layer is deposited in the opening in the hard mask layer, for example, as described with respect toFIG.1H. At operation237, metal is deposited in the trenches and a P-metal material plug is deposited, for example, as described with respect toFIG.1I. At operation239, planarization is performed, for example, as described with respect toFIG.1J. At operation241, a passivation layer is formed and patterned, for example, as described with respect toFIGS.1K and1L. At operation243, the under bump metallization layer is formed and patterned, for example, as described with respect toFIG.1M. The operations of method240can be utilized according to one or more embodiments to form the device as shown inFIG.1OorFIG.4. Another aspect of the disclosure pertains to an electronics system. In one or more embodiments, an electronic system comprises the LED monolithic devices and arrays described herein and driver circuitry configured to provide independent voltages to one or more of p-contact layers. In one or more embodiments, the electronic system is selected from the group consisting of a LED-based luminaire, a light emitting strip, a light emitting sheet, an optical display, and a microLED display. FIG.4is a cross sectional view of an LED device300showing a single mesa350of an LED device according to one or more embodiments. The device300is similar to the first mesa150aor the second mesa150bof the device100shown inFIG.1O. The device300comprises a semiconductor layer304including an n-type layer304n, a p-type layer304pand an active region306between the n-type layer304nand the p-type layer304p. In the embodiment shown, there is a multilayer composite film317on the P-type layer304p. As shown, the multilayer composite film317comprises a current spreading layer311on the P-type layer304p. The multilayer composite film further comprises a dielectric layer307on the current spreading layer311. In one or more embodiments, the current spreading layer311has a first portion311yand a second portion311z. The first portion311yand the second portion311zare lateral portions of the current spreading layer311. A P-contact layer305is on the first portion311yof the current spreading layer311and in a via opening319. The dielectric layer307is on the second portion311zof the current spreading layer311. In one or more embodiments, the dielectric layer307is separated by the via opening319. The via opening319has at least one sidewall319sand a bottom319b, the bottom319bexposing the current spreading layer311. In the embodiment shown, the via opening319is defined by opposing sidewalls319sof the dielectric layer307and a bottom319bdefined by the current spreading layer311. In the embodiment illustrated inFIG.4, the via opening319is filled with a P-contact layer305and a guard layer309. As shown inFIG.4, the P-contact layer305is directly on the top surface of the dielectric layer307, on the sidewalls319sand the bottom319bof the via opening319, and on the first portion311yof the current spreading layer311. As shown in the embodiment ofFIG.4, the P-contact layer305is substantially conformal to the via opening319. As used herein, a layer which is “substantially conformal” refers to a layer where the thickness is about the same throughout (e.g., on the hard mask layer308, on the sidewalls319sand on the bottom319bof the via opening319). A layer which is substantially conformal varies in thickness by less than or equal to about 5%, 2%, 1% or 0.5%. In one or more embodiments, a guard layer309is on the P-contact layer305. Without intending to be bound by theory, according to one or more embodiments, the guard layer309may prevent metal ions from the P-contact layer305from migrating and shorting the device300. In one or more embodiments, the guard layer309covers P-contact layer305in its entirety. In one or more embodiments, the guard layer309directly covers P-contact layer305in its entirety. In one or more embodiments, the current spreading layer comprises a transparent material. The current spreading layer is separate from a reflecting layer. In this way, the function of current spreading is achieved in a different layer from the function of reflection. In one or more embodiments, the current spreading layer311comprises indium tin oxide (ITO) or other suitable conducting, transparent materials, e.g., transparent conductive oxides (TCO), such as indium zinc oxide (IZO), the current spreading layer311having a thickness in a range of from 5 nm to 100 nm. In some embodiments, the dielectric layer307comprises any suitable dielectric material, for example, silicon dioxide (SiO2) or silicon oxynitride (SiON). The guard layer309, in some embodiments, comprises titanium-platinum (TiPt), titanium-tungsten (TiW), or titanium-tungsten nitride (TiWN). In one or more embodiments, the P-contact layer305comprises a reflective metal. In one or more embodiments, the P-contact layer305comprises any suitable reflective material such as, but not limited to, nickel (Ni) or silver (Ag). Without intending to be bound by theory, according to some embodiments, the multilayer composite film317on the P-type layer304pmay balance absorption, reflection, and conductivity. In some embodiments, the P-contact layer305is a highly reflective layer. At angles close to and larger than the critical angle, the dielectric layer307is a better reflector than P-contact layer305and may not be particularly conductive. In some embodiments, the dielectric layer307may be composed of multiple dielectric layers to form a DBR (distributed Bragg reflector). In one or more embodiments, the current spreading layer311is optimized to minimize absorption and increase conductivity. In one or more embodiments, the P-contact layer305spans a width of the mesa that is smaller than a width that the current spreading layer311spans. In the embodiment shown, there is a hard mask layer308on a first section of the guard layer309, which is above the second portion311zof the current spreading layer311, the hard mask layer308having a hard mask opening347defined therein. The hard mask layer308may comprise any suitable material, including a dielectric material. The hard mask layer308has been masked and etched as described with respect toFIGS.1A-Nabove. The hard mask opening347is partially filled with a liner layer325and partially filled with a P-metal material plug318p, the P-metal material plug318phaving a width339. As shown in the embodiment ofFIG.4, the liner layer325is substantially conformal to the hard mask opening347. As used herein, a layer which is “substantially conformal” refers to a layer where the thickness is about the same throughout (e.g., on the sidewalls347sand on the bottom347bof the hard mask opening347). A layer which is substantially conformal varies in thickness by less than or equal to about 5%, 2%, 1% or 0.5%. In one or more embodiments, the hard mask opening347has at least one sidewall347sand a bottom surface347b. In some embodiments, the bottom surface347bexposes the guard layer309. In one or more embodiments, the liner layer325is on the at least the one sidewall347sand the bottom347bof the hard mask opening347. In specific embodiments, the liner layer325is substantially conformal to the at last one sidewall347sand the bottom347bof the hard mask opening347. In the embodiment shown, there are two sidewalls347s, which are opposed sidewalls347sdefining the hard mask opening347. In one or more embodiments, the liner layer325has a thickness in a range of from about 5 nm to about 2 um. In one or more embodiments, the liner layer325may comprise a seed material and the liner layer325can comprise any suitable material including, but not limited, to aluminum (Al), titanium nitride, Ag, indium tin oxide (ITO), titanium tungsten (TiW) and/or titanium platinum (TiP). The seed material of the liner layer325according to some embodiments may promote plating of the P-metal material plug318p. In one or more embodiments, the liner layer325serves as an electrical bridge. The liner layer325may be formed by any means known to one of skill in the art such as sputtering deposition. As illustrated inFIG.4, there is a passivation film321on the hard mask layer308. In one or more embodiments, the passivation film321comprises a first passivation layer320and a second passivation layer322. The first passivation layer320and the second passivation layer322can comprise any suitable material. In one or more embodiments, the first passivation layer320comprises silicon oxide (SiO2), and the second passivation layer comprises silicon nitride (SiN). In one or more embodiments, the passivation film321has a passivation film opening348therein defining a width349, the width349of the passivation film opening348being less than the width339of a combination of the P-metal material plug318pand the liner layer325. In one or more embodiments, the passivation film321is sized to cover a surface325fof the liner layer325and a portion of the P-metal material plug318p. In this way, the passivation film opening348being less than the width339of the P-metal material plug318pand liner layer325is effective to protect the liner layer325while allowing access to the P-metal material plug318p. In one or more embodiments, each the passivation film opening348is centered to the P-metal material plug318p. As shown inFIG.4, a layer of P-metal material, which may also be referred to as a P-metal material plug318p, is formed on the liner layer325. The P-metal material plug318pcan comprise any suitable material. In one or more embodiments, the P-metal material plug318pcomprises copper (Cu). In one or more embodiments, the inner spacers312contact the outer edges of the P-contact layer305, the guard layer309, and the hard mask layer308. Outer spacers314are formed adjacent the inner spacers312. In one or more embodiments, a reflective liner330is formed at the ends of the semiconductor layers304n,306, and304p, separating them from N-contact material318n. A difference between the LED device300inFIG.4and that shown inFIG.1Ois the first passivation layer320corresponding to the passivation layer120shown inFIG.1M, and a second passivation layer322, which may comprise silicon nitride (SiN) in some embodiments. In some embodiments, there is only the first passivation layer320, but in other embodiments, there is the first passivation layer320and the second passivation layer322. The first passivation layer320and the second passivation layer322have a passivation film opening348therein. InFIG.4, there is also an anode pad comprising under bump metallization324a, the composition of which is described with respect toFIG.1M. The P-metal material plug318phas a width339defined by the distance from the outer edges of liner layer325, and the passivation film opening348in the passivation layers is filled with the under bump metallization324a, which forms the anode pad. In one or more embodiments, the opening348has a width349that is less than the width339of the P-metal material plug318p. In some embodiments, the width of the P-metal material plug318pis in a range of from 2 μm to 30 for example from 10 μm to 20 Applications LED devices disclosed herein may be monolithic arrays or matrixes. An LED device may be affixed to a backplane for use in a final application. Illumination arrays and lens systems may incorporate LED devices disclosed herein. Applications include but are not limited to beam steering or other applications that benefit from fine-grained intensity, spatial, and temporal control of light distribution. These applications may include, but are not limited to, precise spatial patterning of emitted light from pixel blocks or individual pixels. Depending on the application, emitted light may be spectrally distinct, adaptive over time, and/or environmentally responsive. Light emitting pixel arrays may provide pre-programmed light distribution in various intensity, spatial, or temporal patterns. Associated optics may be distinct at a pixel, pixel block, or device level. An example light emitting pixel array may include a device having a commonly controlled central block of high intensity pixels with an associated common optic, whereas edge pixels may have individual optics. In addition to flashlights, common applications supported by light emitting pixel arrays include video lighting, automotive headlights, architectural and area illumination, and street lighting. The use of the terms “a” and “an” and “the” and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods. Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner. Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents. | 65,118 |
11942508 | DETAILED DESCRIPTION OF THE EMBODIMENTS The embodiments may be modified in various ways and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail herein. In the following description, the singular forms also include the plural forms unless the context clearly includes the singular. The embodiments are not limited to the embodiments disclosed below, and may be modified in various forms and may be implemented. Each of the embodiments disclosed below may be implemented alone or in combination with at least one of other embodiments. In the drawings, some components which are not directly related to a characteristic of the embodiments may be omitted to clearly represent the embodiments. Some components in the drawings may be shown to be exaggerated in size or proportion. Throughout the drawings, the same or similar components will be given by the same reference numerals and symbols as much as possible even though they are shown in different drawings, and repetitive descriptions will be omitted. FIG.1is a schematic perspective view illustrating a light emitting element LD according to an embodiment,FIG.2is a cross-sectional view illustrating the light emitting element LD according to an embodiment. For example,FIG.1illustrates an example of the light emitting element LD that may be used as a light source of a pixel according to an embodiment, andFIG.2illustrates an example of a cross-section of the light emitting element LD taken along line I˜I′ ofFIG.1. Referring toFIGS.1and2, the light emitting element LD includes a first semiconductor layer SCL1, an active layer ACT, and a second semiconductor layer SCL2, which are sequentially disposed along one direction, and an insulating film INF surrounding an outer circumferential surface (for example, a side surface) of the first semiconductor layer SCL1, the active layer ACT, and the second semiconductor layer SCL2. The light emitting element LD may also include an electrode layer ETL disposed on the second semiconductor layer SCL2. The insulating film INF may or may not at least partially surround an outer circumferential surface of the electrode layer ETL. According to an embodiment, the light emitting element LD may further include another electrode layer disposed on a surface (for example, a lower surface) of the first semiconductor layer SCL1. In an embodiment, the light emitting element LD may be provided in a stick (or rod) shape extending along one direction, and may have a first end portion EP1and a second end portion EP2at the ends of a length L direction (or a thickness direction). The first end portion EP1may be a first bottom surface (or an upper surface) of the light emitting element LD, and the second end portion EP2may be a second bottom surface (or a lower surface) of the light emitting element LD. In an embodiment, the term “rod shape” includes rod-like shapes and bar-like shapes that are long (have an aspect ratio greater than 1) in the length L direction, and may include circular columns or polygonal columns without limitation to the shape of the cross section thereof. For example, the length L of the light emitting element LD may be greater than the diameter D (or the width of the cross section). The first semiconductor layer SCL1, the active layer ACT, the second semiconductor layer SCL2, and the electrode layer ETL may be sequentially disposed in a direction from the second end portion EP2to the first end portion EP1of the light emitting element LD. For example, the first semiconductor layer SCL1may be disposed on the second end portion EP2of the light emitting element LD, and the electrode layer ETL may be disposed on the first end portion EP1of the light emitting element LD. In an embodiment, at least one electrode layer may be disposed on the second end portion EP2of the light emitting element LD. The first semiconductor layer SCL1may be a semiconductor layer of a first conductivity type. For example, the first semiconductor layer SCL1may be an N-type semiconductor layer including an N-type dopant. For example, the first semiconductor layer SCL1may include any one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an N-type semiconductor layer doped with a dopant such as Si, Ge, or Sn. However, the material comprising the first semiconductor layer SCL1is not limited thereto, and other materials may also comprise the first semiconductor layer SCL1. The active layer ACT may be disposed on the first semiconductor layer SCL1and may be formed in a single-quantum well or multi-quantum well structure. A position of the active layer ACT may be changed according to a type of the light emitting element LD. The active layer ACT may emit light having a wavelength of about 400 nm to about 900 nm, and may use a double hetero-structure. A clad layer (not shown) doped with a conductive dopant may be selectively formed on and/or under the active layer ACT. For example, the clad layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer ACT, and other materials may also comprise the active layer ACT. When a voltage equal to or greater than a threshold voltage is applied to both ends of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are combined in the active layer ACT. By controlling light emission of the light emitting element LD using such a principle, the light emitting element LD may be used as a light source of light emitting devices including a pixel of a display device. The second semiconductor layer SCL2may be disposed on the active layer ACT and may be a semiconductor layer of a second conductive type different from that of the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2may include a P-type semiconductor layer including a P-type dopant. For example, the second semiconductor layer SCL2may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be a P-type semiconductor layer doped with a dopant such as Mg. However, the material comprising the second semiconductor layer SCL2is not limited thereto, and other materials may also comprise the second semiconductor layer SCL2. In an embodiment, the first semiconductor layer SCL1and the second semiconductor layer SCL2may have different lengths (or thicknesses) in the length L direction of the light emitting element LD. For example, the first semiconductor layer SCL1may have a length (or a thickness) longer (or thicker) than that of the second semiconductor layer SCL2along the length L direction of the light emitting element LD. Accordingly, the active layer ACT of the light emitting element LD may be positioned closer to the first end portion EP1than the second end portion EP2. The electrode layer ETL may be disposed on the second semiconductor layer SCL2. The electrode layer ETL may protect the second semiconductor layer SCL2, and may be a contact electrode for smoothly connecting the second semiconductor layer SCL2to a predetermined electrode, line, or the like. For example, the electrode layer ETL may be an ohmic contact electrode or a Schottky contact electrode. In describing embodiments, the term “connection (or access)” may mean a physical and/or electrical connection (or access) generically. This may mean a direct or indirect connection (or access) and an integral or non-integral connection (or access) generically. The electrode layer ETL may be substantially transparent or translucent. Accordingly, light generated by the light emitting element LD may pass through the electrode layer ETL and may be emitted to the outside of the light emitting element LD. In other embodiments, the electrode layer ETL may be opaque when the light generated by the light emitting element LD does not pass through the electrode layer ETL and the light is emitted to the outside through a region other than the end portion of the light emitting element LD on which the electrode layer ETL is disposed. In an embodiment, the electrode layer ETL may include metal or metal oxide. For example, the electrode layer ETL may be formed using a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), an oxide or alloy of these metals, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or indium oxide (In2O3), and the like, either alone or in a combination. The insulating film INF may expose the electrode layer ETL and the first semiconductor layer SCL1at the first and second end portions EP1and EP2of the light emitting element LD, respectively. When the insulating film INF is provided to cover the surface of the light emitting element LD, particularly the outer circumferential surface of the first semiconductor layer SCL1, the active layer ACT, the second semiconductor layer SCL2, and/or the electrode layer ETL, short circuit defects through the light emitting element LD may be prevented. Accordingly, electrical stability of the light emitting element LD may be assured. When the insulating film INF is provided on the surface of the light emitting element LD, surface defects of the light emitting element LD may be minimized, and thus life and efficiency may be improved. When the insulating film INF is formed on each light emitting element LD, even though the light emitting elements LD are disposed close to each other, occurrence of unwanted short circuits between the light emitting elements LD may be prevented. In an embodiment, the light emitting element LD may be manufactured through a surface treatment process. For example, the surface treatment may be performed on each light emitting element LD such that when the light emitting elements LD are mixed in a fluid solution (or solvent) and supplied to the light emitting areas of each pixel, the light emitting elements LD may be uniformly dispersed in the solution and avoid aggregating together. In an embodiment, the insulating film INF itself may be a hydrophobic film formed of a hydrophobic material, or a hydrophobic film may be additionally formed on the insulating film INF. The insulating film INF may include a transparent insulating material. Accordingly, light generated in the active layer ACT may pass through the insulating film INF and may be emitted outside of the light emitting element LD. For example, the insulating film INF may include at least one insulating material of SiO2or other silicon oxide (SiOx), Si3N4or other silicon nitride (SiNx), Al2O3or other aluminum oxide (AlxOy), and TiO2or other titanium oxide (TixOy), but the embodiments are not limited thereto. The insulating film INF may be formed of a single layer or multiple layers. For example, the insulating film INF may be formed of a double film. The insulating film INF may be partially etched in at least one of the upper or lower region. The insulating film INF may have a rounded shape in the partially etched region, but the embodiments are not limited by the shape of the insulating film INF. For example, in at least one of the upper or the lower regions, the insulating film INF may be partially or entirely removed. Accordingly, some of the first semiconductor layer SCL1, the second semiconductor layer SCL2, the electrode layer ETL, or another electrode layers (for example, another electrode layer disposed at the second end portion EP2of the light emitting element LD) may be exposed. In an embodiment, the light emitting element LD may have a nanometer scale to micrometer scale size. For example, each light emitting element LD may have a diameter D (or a width of a cross section) and/or length L in the nanometer scale to micrometer scale range. For example, the light emitting element LD may have a diameter D in a range of several hundred nanometers and a length L in a range of several micrometers. However, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed according to the design conditions of the light emitting devices using the light emitting element LD as a light source. The structure, shape, and/or type of the light emitting element LD may be modified according to an embodiment. For example, the light emitting element LD may not include the electrode layer ETL. In other embodiments, the light emitting element LD may further include another electrode layer disposed at an end portion of the first semiconductor layer SCL1. For example, the light emitting element LD may further include at least one other electrode layer disposed on the second end portion EP2. The light emitting element LD may also be formed in a core-shell structure. A light emitting device including the light emitting element LD may be used in a variety of devices that require a light source, including a display device. For example, multiple light emitting elements LD may be arranged in each pixel of a display panel, and the light emitting elements LD may be used as a light source of each pixel. However, the application field of the light emitting element LD is not limited to this example. For example, the light emitting element LD may also be used in other types of devices that require a light source, such as a lighting device. FIG.3is a schematic plan view illustrating the display device according to an embodiment. For example,FIG.3shows a display panel PNL comprising a screen or the like of the display device. According to an embodiment, the display panel PNL ofFIG.3may use the light emitting element LD described in the embodiment ofFIGS.1and2as a light source of the pixel PXL. For example, each pixel PXL of the display panel PNL may include at least one light emitting element LD. InFIG.3, a structure of the display panel PNL is briefly shown centering on a display area DA. However, according to an embodiment, at least one driving circuit unit, lines and/or pads, which are not shown, may be further disposed in the display panel PNL. Referring toFIG.3, the display panel PNL may include a base layer BSL and pixels PXL provided on the base layer BSL. The display panel PNL and the base layer BSL for forming the display panel PNL may include the display area DA for displaying an image, and a non-display area NDA excluding the display area DA. The display area DA may comprise a screen on which the image is displayed, and the non-display area NA may be the remaining area excluding for the display area DA. The display panel PNL may be provided in various shapes. For example, the display panel PNL may be provided in a rectangular plate shape, but is not limited thereto. For example, the display panel PNL may have a shape such as a circle or an ellipse. InFIG.3, the display panel PNL has angled corners, but the embodiments are not limited thereto. For example, the display panel PNL may have curved corners. InFIG.3, the display panel PNL has a pair of short sides and a pair of long sides. The extension direction of the short side is indicated as the first direction DR1, the extension direction of the long side is indicated as the second direction DR2, and a direction (for example, a thickness or height direction of the display panel PNL) perpendicular to both the long side and the short side is indicated as the third direction DR3. However, this may be changed according to the shape of the display panel PNL. The display area DA may have various shapes. For example, the display area DA may have various shapes including a rectangle, a circle, or an ellipse. In an embodiment, the display area DA may have a shape matching the shape of the display panel PNL, but is not limited thereto. The pixels PXL may be disposed in the display area DA on the base layer BSL. For example, the display area DA may include multiple pixel areas in which the pixels PXL are disposed. The non-display area NA may be disposed around the display area DA, and various lines, pads, and/or an embedded circuit unit connected to the pixels PXL of the display area DA may be disposed in the non-display area NA. According to an embodiment, at least two types of pixels PXL emitting light of different colors may be disposed in the display area DA. Multiple pixels PXL, for example, a red pixel, a green pixel, and a blue pixel, that are disposed adjacent to each other and emit light of different colors may comprise each pixel unit. In an embodiment, each pixel PXL may be set as a pixel of a predetermined color, and may include a light emitting element LD that generates light of the predetermined color. In another embodiment, at least some of the pixels PXL may include light emitting elements LD that generate light of a first color, and may also include a light conversion layer LCL comprised of color conversion particles, such as quantum dots of a predetermined color, for converting light of a first color into a second color. Accordingly, the light of the second color may be generated by some of the pixels PXL. The pixel PXL may include at least one light source driven by a predetermined control signal (for example, a scan signal and a data signal) and/or predetermined power (for example, first power and second power). In an embodiment, the light source may include at least one light emitting element LD according to the embodiment ofFIGS.1and2, for example, at least one stick-shaped light emitting element LD having a nanometer to micrometer scale size. Various types of light emitting elements may be used as the light source of the pixel PXL. For example, in another embodiment, the light source of each pixel PXL may be comprised of a light emitting element of a core-shell structure or a flip chip structure. In the embodiments, the pixel PXL may have a structure according to one of the examples described below. Each pixel PXL may have these structures applied alone, or in a combination. In an embodiment, the pixel PXL may be configured as an active pixel, but the embodiments are not limited thereto. For example, the pixel PXL may be configured to be a pixel for a passive or active light emitting display devices having a variety of structures and/or driving methods. FIG.4is a circuit diagram illustrating the pixel PXL according to an embodiment. For example,FIG.4is a circuit diagram illustrating an embodiment of the pixel PXL that may be disposed in the display area DA ofFIG.3. Referring toFIG.4, the pixel PXL includes a light emitting unit EMU for generating light of a luminance corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC for driving the light emitting unit EMU. The light emitting unit EMU may include at least one light emitting element LD connected between first power VDD and second power VSS. For example, the light emitting unit EMU may include a multiple light emitting elements LD. For example, the light emitting unit EMU may include a first electrode ELT1(also referred to as a “first alignment electrode”) connected to the first power VDD via the pixel circuit PXC and a first power line PL1, a second electrode ELT2(also referred to as a “second alignment electrode”) connected to the second power VSS via a second power line PL2, and the light emitting elements LD connected in parallel in the same direction between the first and second electrodes ELT1and ELT2. In an embodiment, the first electrode ELT1may be an anode electrode of the light emitting unit EMU, and the second electrode ELT2may be a cathode electrode of the light emitting unit EMU, but the embodiments are not limited thereto. Each of the light emitting elements LD may include the first end portion EP1(for example, a P-type end portion) connected to the first power VDD through the first electrode ELT1and/or the pixel circuit PXC, and the second end portion EP2(for example, an N-type end portion) connected to the second power VSS through the second electrode ELT2. The light emitting elements LD may be connected in parallel in a forward direction between the first and second electrodes ELT1and ELT2. Each light emitting element LD connected in the forward direction between the first power VDD and the second power VSS may comprise each effective light source. The effective light sources may be gathered to comprise the light emitting unit EMU of the pixel PXL. The first power VDD and the second power VSS may have different potentials so that the light emitting elements LD emit light. For example, the first power VDD may be set as a high potential power, and the second power VSS may be set as a low potential power. The potential difference between the first power VDD and the second power VSS may be set to be equal to or greater than the threshold voltage of the light emitting elements LD during the light emission period of the pixel PXL. The first end portions EP1of the light emitting elements LD comprising each light emitting unit EMU may be connected to the pixel circuit PXC through the first electrode ELT1, and may be connected to the first power VDD through the pixel circuit PXC and the first power line PL1. The second end portions EP2of the light emitting elements LD may be connected to the second power VSS through the second electrode ELT2and the second power line PL2. The light emitting elements LD may emit light at a luminance corresponding to a driving current supplied through a corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply a driving current corresponding to a grayscale value to be expressed in a corresponding frame to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may be divided and flow to the light emitting elements LD connected in the forward direction. Accordingly, while each light emitting element LD emits light at a luminance corresponding to the current flowing therein, the light emitting unit EMU may emit light of a luminance corresponding to the driving current. In an embodiment, the light emitting unit EMU may further include at least one ineffective light source in addition to the light emitting elements LD. For example, at least one ineffective light emitting element, which is arranged in a reverse direction or which has at least one end portion floated, may be further included in at least one series stage. The ineffective light emitting element maintains a deactivated state even though the driving voltage (for example, a driving voltage of a forward direction) is applied between the first and second electrodes ELT1and ELT2, and thus may substantially maintain a non-light emitting state. Although inFIG.4the pixel PXL includes a light emitting unit EMU of a parallel structure, the embodiments are not limited thereto. For example, the pixel PXL may include a light emitting unit EMU of a series structure or of a series and parallel structure. For example, the light emitting unit EMU may include multiple light emitting elements LD connected in the series structure or the series and parallel structure between the first electrode ELT1and the second electrode ELT2. The pixel circuit PXC may be connected between the first power VDD and the first electrode ELT1. The pixel circuit PXC may be connected to a scan line SL and a data line DL of a corresponding pixel PXL. The pixel circuit PXC may be connected to a sensing signal line SSL and a sensing line SENL. The pixel circuit PXC may include a first transistor M1, a second transistor M2, a third transistor M3, and a storage capacitor Cst. The first transistor M1may be connected between the first power VDD and the first electrode ELT1of the light emitting unit EMU. The gate electrode of the first transistor M1may be connected to a first node N1. The first transistor M1may control the driving current supplied to the light emitting unit in correspondence with a voltage of the first node N1. The first transistor M1may be a driving transistor that controls the driving current of the pixel PXL. In an embodiment, the first transistor M1may include a bottom metal layer BML (also referred to as a “lower metal electrode”, a “lower electrode”, or a “lower light blocking layer”). For example, when driving the pixel PXL, a back-biasing technology (or sync technology) of moving the threshold voltage of the first transistor M1in a negative direction or a positive direction by applying a back-biasing voltage to the lower metal layer BML of the first transistor M1may be applied. The threshold voltage of the first transistor M1may be changed by applying a source-sink technology by connecting the lower metal layer BML to an electrode, for example, a source electrode, of the first transistor M1. When the lower metal layer BML is disposed under a semiconductor layer comprising a channel of the first transistor M1, the lower metal layer BML may serve as a light blocking pattern and stabilize the operation characteristic of the first transistor M1. In the embodiments, the function and utilization methods of the lower metal layer BML are not limited to these examples. The second transistor M2may be connected between the data line DL and the first node N1. The gate electrode of the second transistor M2may be connected to the scan line SL. The second transistor M2may be turned on when a scan signal of a gate-on voltage (for example, a high-level voltage) is supplied from the scan line SL, to electrically connect the data line DL and the first node N1. For each frame period, a data signal of a corresponding frame is supplied to the data line DL, and the data signal is transferred to the first node N1through the turned on second transistor M2during a period in which the scan signal of the gate-on voltage is supplied. The second transistor M2may be a switching transistor for transferring each data signal to the inside of the pixel PXL. One electrode of the storage capacitor Cst is electrically connected to the first node N1, and another electrode is electrically connected to the first electrode ELT1(or a second electrode of the transistor M1). The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1during each frame period. The third transistor M3may be connected between the first electrode ELT1of the light emitting unit EMU and the sensing line SENL. The gate electrode of the third transistor M3may be connected to the sensing signal line SSL. The third transistor M3may transfer a voltage value applied to the first electrode ELT1of the light emitting unit EMU to the sensing line SENL according to a sensing signal supplied to the sensing signal line SSL during a predetermined sensing period. The voltage value transferred through the sensing line SENL may be provided to an external circuit (for example, a timing controller), and the external circuit may extract characteristic information (for example, the threshold voltage or the like of the first transistor M1) of each pixel PXL based on the provided voltage value. The extracted characteristic information may be used to convert image data so that a characteristic deviation between the pixels PXL is compensated. InFIG.4, all transistors included in the pixel circuit PXC, for example, the first, second, and third transistors M1, M2, and M3may be N-type transistors, but the embodiments are not limited thereto. For example, the first, second, and third transistors M1, M2, and M3may be changed to P-type transistors. In another embodiment, the pixel circuit PXC may include both of P-type and N-type transistors. For example, some of the transistors (for example, the first, second, and third transistors M1, M2, M3) included in the pixel circuit PXC may be P-type transistors, and the others may be N-type transistors. The voltage level of control signals (for example, the scan signal, the data signal, and/or the sensing signal) for driving each transistor may be adjusted according to the type of the transistors. The structure and a driving method of the pixel PXL may be changed according to the embodiments. For example, the pixel circuit PXC may also be comprised of a pixel circuit of other structures and/or driving methods, in addition to the embodiment shown inFIG.3. For example, the pixel circuit PXC may not include the third transistor M3. The pixel circuit PXC may additionally include at least one or more other circuit elements such as a transistor for compensating for the threshold voltage of the first transistor M1, a transistor for initializing the voltage of the first node N1or the first electrode ELT1of the light emitting unit EMU, a transistor for controlling a period in which the driving current is supplied to the light emitting unit EMU, and/or a boosting capacitor for boosting the voltage of the first node N1. In another embodiment, when the pixel PXL is configured for a passive light emitting display device or the like, the pixel circuit PXC may be omitted. Each of the first and second electrodes ELT1and ELT2of the light emitting unit EMU may be directly connected to the scan line SL, the data line DL, the first power line PL1, the second power line PL2, other signal lines or power lines, or the like. FIG.5is a schematic plan view illustrating the pixel PXL according to an embodiment. InFIG.5, a structure of the pixel PXL is shown centering on the light emitting unit EMU of the pixel PXL. For example,FIG.5illustrates a structure of the light emitting unit EMU including the first and second electrodes ELT1and ELT2, and the light emitting elements LD connected in parallel between the first and second electrodes ELT1and ELT2, as in the embodiment ofFIG.4. However, the structure of the light emitting unit EMU, including the number and a connection structure of the light emitting elements LD, may be variously changed. FIG.5shows an embodiment in which each light emitting unit EMU is connected to a predetermined power line (for example, the first power line PL1and/or the second power line PL2), a circuit element (for example, at least one circuit element comprising the pixel circuit PXC) and/or a signal line (for example, the scan line SL and/or the data line DL) through first and second contact holes CH1and CH2. However, the embodiments are not limited thereto. For example, in another embodiment, at least one of the first and second electrodes ELT1and ELT2of each pixel PXL may be directly connected to the predetermined power line and/or the signal line without passing through a contact hole, an intermediate line, and/or the like. Referring toFIG.5, the pixel PXL is provided in each pixel area PXA. The pixel area PXA may comprehensively mean a pixel circuit area in which circuit elements for comprising a corresponding pixel PXL are disposed and a light emitting area EMA in which the light emitting unit EMU of the pixel PXL is disposed. The light emitting area EMA may be an area in which the light emitting elements LD connected in the forward direction between the first and second electrodes ELT1and ELT2comprising the light emitting unit EMU of each pixel PXL may be disposed. Hereinafter, each of the embodiments are described where the light emitting elements LD may be disposed in the light emitting areas EMA. In the light emitting area EMA, predetermined electrodes (for example, the first and second electrodes ELT1and ELT2, and/or first and second contact electrodes CNE1and CNE2) electrically connected to the light emitting elements LD, or a region of the electrodes may be disposed. In an embodiment, the light emitting area EMA may be surrounded by a bank BNK. The pixel PXL may include the first electrode ELT1and the second electrode ELT2disposed in the light emitting area EMA, and the light emitting elements LD disposed and/or arranged between the first and second electrodes ELT1and ELT2. The light emitting elements LD are disposed and/or arranged between the first and second electrodes ELT1and ELT2such that at least one region of each of the light emitting elements LD is positioned in a region between the first and second electrodes ELT1and ELT2on a plan view. The pixel PXL may further include the first contact electrode CNE1and the second contact electrode CNE2disposed on the first end portions EP1and the second end portions EP2of the light emitting elements LD, and a bank pattern BNP disposed under the first and second electrodes ELT1and ELT2. When at least one region of the bank BNK is positioned in each pixel area PXA, the pixel PXL may further include the bank BNK (or one region of the bank BNK). The bank pattern BNP may be disposed to overlap a region of the first and second electrodes ELT1and ELT2. For example, the bank pattern BNP may be disposed under the first and second electrodes ELT1and ELT2and may overlap a region of each of the first and second electrodes ELT1and ELT2in a plan view. The bank pattern BNP may form a reflective wall structure around the light emitting elements LD, and may be formed as a separate or integral pattern. For example, the bank pattern BNP may include a first bank pattern portion BNP1and a second bank pattern portion BNP2separated from each other. The first bank pattern portion BNP1may be disposed under the first electrode ELT1and overlap a region of the first electrode ELT1, and the second bank pattern portion BNP2may be disposed under the second electrode ELT2and overlap a region of the second electrode ELT2. In another embodiment, the bank pattern BNP may be configured as an integral pattern of a shape surrounding a region where the light emitting elements LD are disposed while having an opening or a groove corresponding to the region where the light emitting elements LD are disposed. When the bank pattern BNP is disposed under a region of each of the first and second electrodes ELT1and ELT2, the first and second electrodes ELT1and ELT2may protrude in an upward direction in the region where the bank pattern BNP is formed. The bank pattern BNP may comprise reflective wall structure together with the first and second electrodes ELT1and ELT2. For example, the first and second electrodes ELT1and ELT2and/or the bank pattern BNP may be formed of a reflective material, or a reflective layer may be formed on a protruded sidewall SDW (refer toFIG.6) of the first and second electrodes ELT1and ELT2and/or the bank pattern BNP. Accordingly, the light emitted from the first and second end portions EP1and EP2of the light emitting elements LD facing the first and second electrodes ELT1and ELT2may be guided to be more directed to the front direction of the display panel PNL. Here, the front direction of the display panel PNL may include a direction (for example, the third direction DR3) perpendicular to the display panel PNL, and may comprehensively mean a direction belonging to a predetermined viewing angle range. As described above, when a region of the first and second electrodes ELT1and ELT2is protruded in the upward direction using the bank pattern BNP, light efficiency of the pixel PXL may be improved. In another embodiment, the pixel PXL may not include the bank pattern BNP. In this case, the first and second electrodes ELT1and ELT2may have a substantially flat surface or may have an uneven surface by being formed in different thicknesses for each region. The first electrode ELT1and the second electrode ELT2may be disposed to be spaced apart from each other in each pixel area PXA. For example, the first and second electrodes ELT1and ELT2may be disposed to be spaced apart from each other in the first direction DR1in the light emitting area EMA of each pixel PXL. The first and second electrodes ELT1and ELT2may have various shapes. For example, each of the first and second electrodes ELT1and ELT2may have a bar shape extending along one direction. Each of the first and second electrodes ELT1and ELT2may have a bar shape extending in the second direction DR2crossing or intersecting (for example, orthogonal to) the first direction DR1. In an embodiment, the first direction DR1may be a row direction (or a horizontal direction) of the display area DA, and the second direction DR2may be a column direction (or a vertical direction) of the display area DA, but the embodiments are not limited thereto. The shape and/or a structure of the first and second electrodes ELT1and ELT2may be modified. In each pixel area PXA, the first and second electrodes ELT1and ELT2may have a uniform width or a non-uniform width, and may or may not include a bent portion. The shapes, structure, and other features of the first and second electrodes ELT1and ELT2may be changed based on the embodiments. AlthoughFIG.5discloses an embodiment in which one first electrode ELT1and one second electrode ELT2are disposed in each light emitting area EMA, the number of first and second electrodes ELT1and ELT2disposed in each pixel PXL may be modified. When multiple first electrodes ELT1are disposed in one pixel PXL, the first electrodes ELT1may be integrally or non-integrally connected to each other. For example, the first electrodes ELT1may be integrally connected or may be connected to each other by a bridge pattern positioned on a layer (for example, a circuit layer on which the pixel circuit PXC is disposed) different from that of the first electrodes ELT1. Similarly, when multiple second electrodes ELT2are disposed in one pixel PXL, the second electrodes ELT2may be integrally or non-integrally connected to each other. The first electrode ELT1and/or the second electrode ELT2may have a pattern separated for each pixel PXL or a pattern commonly connected across several of the pixels PXL. For example, as shown inFIG.5, the first and second electrodes ELT1and ELT2may be disconnected in a separation area SPA positioned outside a corresponding light emitting area EMA. In another embodiment, at least one of the first and second electrodes ELT1and ELT2may have an independent pattern disconnected in the light emitting area EMA. For example, the first electrode ELT1may be disconnected inside the light emitting area EMA, or both of the first and second electrodes ELT1and ELT2may be disconnected inside the light emitting area EMA. In another embodiment, the first electrode ELT1may be disconnected in the separation area SPA, or both of the first and second electrodes ELT1and ELT2may be disconnected in the separation area SPA. In other embodiments, the first electrode ELT1may have an independent pattern disconnected inside the separation area SPA or the light emitting area EMA, and an end portion of the second electrode ELT2may extend in the first direction DR1or the second direction DR2and may be integrally connected to the second electrode ELT2of another pixel PXL adjacent in the first direction DR1or the second direction DR2. At least one of the first and second electrodes ELT1and ELT2may be disconnected in the separation area SPA or the light emitting area EMA. Before the process of forming the pixel PXL is complete, (especially before the alignment of the light emitting elements LD is completed), the first electrodes ELT1of the pixels PXL disposed in the display area DA may be connected to each other, and the second electrodes ELT2of the pixels PXL may be connected to each other. For example, before the alignment of the light emitting elements LD is completed, the first electrodes ELT1of the pixels PXL may be integrally or non-integrally connected to each other to configure a first alignment line, and the second electrodes ELT2of the pixels PXL may be integrally or non-integrally connected to each other to configure a second alignment line. When the first electrodes ELT1or the second electrodes ELT2of the pixels PXL are non-integrally connected to each other, the first electrodes ELT1or the second electrodes ELT2may be electrically connected to each other by at least one contact hole, a bridge pattern, and/or the like. The first alignment line and the second alignment line may receive a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage) in aligning the light emitting elements LD, respectively. For example, any one of the first and second alignment lines may receive an alignment signal of an alternating current type, and the other of the first and second alignment lines may receive an alignment voltage (for example, a ground voltage) having a constant voltage level. In aligning the light emitting elements LD, a predetermined alignment signal may be applied to the first and second alignment electrodes. Accordingly, an electric field may be formed between the first and second alignment lines, and thus each of the light emitting elements LD supplied to the light emitting area EMA may be self-aligned in a predetermined direction. After the alignment of the light emitting elements LD is completed, at least the first alignment line may be disconnected in the separation area SPA or the like to be separated into each of the first electrodes ELT1of each pixel PXL, and thus the pixels PXL may be individually driven. The first electrode ELT1may be electrically connected to a predetermined circuit element (for example, at least one transistor of the pixel circuit PXC), a power line (for example, the first power line PL1), and/or the signal line (for example, the scan line SL, the data line DL, or a predetermined control line) through the first contact hole CH1. In another embodiment, the first electrode ELT1may be directly connected to a predetermined power line or signal line. In an embodiment, the first electrode ELT1may be electrically connected to the predetermined circuit element disposed under the first electrode ELT1through the first contact hole CH1and may be electrically connected to a first line through the circuit element. The first line may be the first power line PL1for supplying the first power VDD, but is not limited thereto. The second electrode ELT2may be electrically connected to a predetermined circuit element (for example, at least one transistor of the pixel circuit PXC), a power line (for example, the second power line PL2), and/or a signal line (for example, the scan line SL, the data line DL, or a predetermined control line) through the second contact hole CH2. In another embodiment, the second electrode ELT2may be directly connected to a predetermined power line or signal line. In an embodiment, the second electrode ELT2may be electrically connected to a second line disposed under the second electrode ELT2through the second contact hole CH2. The second line may be the second power line PL2for supplying the second power VSS, but is not limited thereto. Each of the first and second contact holes CH1and CH2may or may not overlap the bank BNK. For example, as shown inFIG.5, the first and second contact holes CH1and CH2may be disposed between the light emitting area EMA and the separation area SPA, and may overlap the bank BNK. In another embodiment, at least one of the first and second contact holes CH1and CH2may be disposed in the light emitting area EMA or the separation area SPA. Each of the first and second electrodes ELT1and ELT2may be comprised of a single layer or of multiple layers. For example, the first electrode ELT1may include a reflective electrode layer of at least one layer including a reflective conductive material, and may further include at least one transparent electrode layer and/or a conductive capping layer. Similarly, the second electrode ELT2may include a reflective electrode layer of at least one layer including a reflective conductive material, and may further include at least one transparent electrode layer and/or a conductive capping layer. The reflective conductive material may include at least one of a variety of metal materials such as a metal having high reflectance in the visible light wavelength band, for example, aluminum (Al), gold (Au), and silver (Ag), but the embodiments are not limited thereto. The light emitting elements LD may be disposed between the first electrode ELT1and the second electrode ELT2. For example, the light emitting elements LD may be positioned between the first electrode ELT1and the second electrode ELT2and may be arranged in parallel to each other. For example, each light emitting element LD may be aligned in the first direction DR1between the first electrode ELT1and the second electrode ELT2, and may be electrically connected between the first and second electrodes ELT1and ELT2. InFIG.5, all light emitting elements LD are uniformly aligned in the first direction DR1, but the embodiments are not limited thereto. For example, at least one of the light emitting elements LD may be aligned in a diagonal direction or the like inclined with respect to the first and second directions DR1and DR2between the first and second electrodes ELT1and ELT2. According to an embodiment, each light emitting element LD may be an ultra-small light emitting element of a size in the nanometer to micrometer scale ranges, using a material of an inorganic crystal structure, but the embodiments are not limited thereto. Each light emitting element LD may be a rod-shaped light emitting element LD as shown inFIGS.1and2, but the embodiments are not limited thereto. Each light emitting element LD may include the first end portion EP1and the second end portion EP2. The first end portion EP1may be disposed adjacent to the first electrode ELT1, and the second end portion EP2may be disposed adjacent to the second electrode ELT2. For example, the first end portion EP1may be disposed to face the first electrode ELT1and the second end portion EP2may be disposed to face the second electrode ELT2. The first end portion EP1may or may not overlap the first electrode ELT1. The second end portion EP2may or may not overlap the second electrode ELT2. In an embodiment, the first end portion EP1of each of the light emitting elements LD may be electrically connected to the first electrode ELT1, and the second end portion EP2of each of the light emitting elements LD may be electrically connected to the second electrode ELT2. In another embodiment, the first end portion EP1of each of the light emitting elements LD may be connected to the first electrode ELT1by directly contacting the first electrode ELT1, and the second end portion EP2of each of the light emitting elements LD may be connected to the second electrode ELT2by directly contacting the second electrode ELT2. Each light emitting element LD connected in the forward direction between the first and second electrodes ELT1and ELT2may configure an effective light source of the corresponding pixel PXL. The effective light sources may be gathered to form the light emitting unit EMU of the pixel PXL. The light emitting elements LD may be dispersed in a predetermined solution, and may be supplied to each pixel area through various methods such as an inkjet method or a slit coating method. For example, the light emitting elements LD may be mixed with a volatile solvent and supplied to the light emitting area EMA of each pixel PXL. When a predetermined alignment voltage (or an alignment signal) is applied to the first and second electrodes ELT1and ELT2of the pixels PXL, an electric field may be formed between the first and second electrodes ELT1and ELT2, and thus the light emitting elements LD may be aligned between the first and second electrodes ELT1and ELT2. After the light emitting elements LD are aligned, the light emitting elements LD may be stably arranged between the first and second electrodes ELT1and ELT2by performing a drying process or the like to remove the solvent. In an embodiment, the light emitting elements LD may be biased and aligned so that the light emitting elements LD may be aligned in a more specific direction. For example, the light emitting elements LD may be aligned using electromagnetic force so that a larger number and/or ratio of the light emitting elements LD supplied to each light emitting area EMA are connected between the first and second electrodes ELT1and ELT2in the forward direction. For example, the light emitting elements LD may be biased and aligned so that more of the first end portions EP1of the light emitting elements LD face the first electrode ELT1(or the first alignment line before being separated into the first electrode ELT1), and more of the second end portions EP2of the light emitting elements LD face the second electrode ELT2(or the second alignment line before being separated into the second electrode ELT2). Thereafter, the drying process or the like for removing the solvent may be performed when the light emitting elements LD in an aligned state. When the light emitting elements LD are biased and aligned in a desired direction as described above, the utilization rate of the light emitting elements LD supplied to each light emitting area EMA may be increased, and the luminance of the pixel PXL may be improved. However, an eccentric alignment in which the light emitting elements LD are more biased and aligned toward a specific electrode (or a specific alignment line) may occur during a bias alignment process or the like using an electromagnetic force or the like. For example, the light emitting elements LD may be arranged to be closer to the sidewall SDW (refer toFIG.6) of the first bank pattern portion BNP1or closer to the second bank pattern portion BNP2. For example, when the light emitting elements LD are biased in a direction of the first electrode ELT1(or the first alignment line) and arranged, the first end portions EP1of the light emitting elements LD may be close or in contact with the sidewall SDW (refer toFIG.6) of the first bank pattern portion BNP1. In case that an eccentric alignment occurs, a contact defect may occur in a subsequent contact process (for example, the process of forming the first and second contact electrodes CNE1and CNE2on the first and second end portions EP1and EP2of the light emitting elements LD, respectively). For example, when the first end portions EP1of the light emitting elements LD are close to the first bank pattern portion BNP1, or the insulating layer formed on the sidewall SDW (refer toFIG.6) of the first bank pattern portion BNP1, the deposition space for forming the first contact electrode CNE1between the first end portions EP1and the first bank pattern portion BNP1may not be sufficient. Accordingly, the risk of a disconnection between the first contact electrode CNE1and first end portion EP1of the light emitting element LD may increase. When a disconnection of the first contact electrode CNE1or the like occurs, even though the light emitting element LD is connected in the forward direction between the first and second electrodes ELT1and ELT2, the light emitting element LD may not operate as an effective light source due to the contact defect. The utilization rate of the light emitting elements LD may be reduced, and uniformity of light emission may be reduced. In an embodiment, a trench TRC may be formed between the first and second electrodes ELT1and ELT2to control the alignment position of the light emitting elements LD. For example, the trench TRC may be disposed at a position capable of preventing eccentric alignment of the light emitting elements LD, and may be formed to have a size capable of accommodating the light emitting elements LD. In an embodiment, the light emitting elements LD may be arranged (or disposed) inside the trench TRC. For example, the pixel PXL may include the trench TRC positioned between the first and second electrodes ELT1and ELT2in a plan view. Here, positioning the trench TRC between the first and second electrodes ELT1and ELT2means that at least one region (for example, at least a central region) of the trench TRC is positioned between the first and second electrodes ELT1and ELT2. In an embodiment, the trench TRC may be formed in an insulating layer (for example, a first insulating layer INS1ofFIGS.6to8) covering the first and second electrodes ELT1and ELT2, and may be formed at a position including a region between the first and second electrodes ELT1and ELT2. The position of the trench TRC is not limited thereto. For example, the trench TRC may be formed on at least one or more other insulating layers, a substrate, or the like, at a position where the light emitting elements LD may be mounted. The trench TRC may or may not partially overlap the first electrode ELT1and/or the second electrode ELT2. In an embodiment, the trench TRC may be positioned in a region between the first and second bank pattern portions BNP1and BNP2and may not overlap the first and second bank pattern portions BNP1and BNP2. For example, the trench TRC may be formed to be spaced apart from each of the first and second bank pattern portions BNP1and BNP2by a predetermined distance or more in a plan view. The predetermined distance may be a sufficient distance to insure there is sufficient space for stably forming the first and second contact electrodes CNE1and CNE2on and/or around the first and second end portions EP1and EP2of the light emitting elements LD in a subsequent contact process, and the predetermined distance may vary according to a design structure or the like of each pixel PXL. According to an embodiment, the trench TRC may be a double trench, but the embodiments are not limited thereto. For example, the trench TRC may be a triple or more multiple trenches. The trench TRC may be at least a double trench. The trench TRC may include a first trench TRC1positioned between the first and second electrodes ELT1and ELT2to accommodate the light emitting elements LD and multiple second trenches TRC2having a size less than that of the first trench TRC1and provided (or disposed) inside the first trench TRC1. For example, the second trenches TRC2may be provided (or disposed) on the bottom surface of the first trench TRC1to form an uneven surface on the bottom surface of the first trench TRC1. The trench TRC may have a width (for example, a width Wt1of the first trench TRC1) capable of accommodating the light emitting elements LD as a whole within the first and second trenches TRC1and TRC2. The trench TRC may have a depth DTH (refer toFIG.6) capable of at least partially accommodating the light emitting elements LD. Accordingly, the light emitting elements LD may be stably arranged (or disposed) in the trench TRC. The first trench TRC1may be positioned between the first and second electrodes ELT1and ELT2in the first direction DR1. For example, in each light emitting area EMA, the first electrode ELT1, the first trench TRC1, and the second electrode ELT2may be sequentially arranged along, or disposed in, the first direction DR1. The first trench TRC1may or may not overlap the first electrode ELT1and/or the second electrode ELT2. In an embodiment, the first trench TRC1may extend in the second direction DR2and may have a size capable of accommodating the light emitting elements LD. Each of the first electrode ELT1, the first trench TRC1, and the second electrode ELT2extend in the second direction DR2which intersects the first direction DR1. For example, the first trench TRC1may have the width Wt1equal to or greater than the length L of each of the light emitting elements LD in the first direction DR1, and may have a length Lt1corresponding to a length of a light emitting element array region defined between the electrodes ELT1and ELT2in the second direction DR2. The first trench TRC1may be formed in correspondence with a region in which the light emitting elements LD are to be arranged (or disposed) in each light emitting area EMA. According to an embodiment, when the light emitting elements LD have a size of a nano scale to micro scale range, the first trench TRC1may have a size in the nanometer scale to micrometer scale range (for example, the width Wt1and/or the length Lt1may be in the nanometer scale to micrometer scale range). The first trench TRC1may also be referred to as a nano or micro trench. In an embodiment, each of the second trenches TRC2may be regularly arranged along (or disposed in) a direction inside the first trench TRC1. For example, the second trenches TRC2may be sequentially arranged along (or disposed in) an extension direction (for example, the second direction DR2) of the first trench TRC1, and each of the second trenches TRC2may extend in a direction (for example, the first direction DR1) crossing (or intersecting) the extension direction of the trench TRC1. In an embodiment, the second trenches TRC2may have a size capable of partially accommodating at least one light emitting element LD. For example, the second trenches TRC2may have a length Lt2equal to or greater than the length L of the light emitting elements LD in the first direction DR1, and may have a width equal to or less than the diameter D (or the width of the cross section) of the light emitting elements LD in the second direction DR2. At least one light emitting element LD may be partially accommodated in at least one second trench TRC2. For example, a light emitting element LD may be partially inserted into any one of the second trenches TRC2. According to an embodiment, when the light emitting elements LD have a size in the nanometer to micrometer scale range, the second trench TRC2may have a size of a nanometer scale to a micrometer scale range (for example, the width Wt2and/or the length Lt2of a second trench TRC2may be in the nanometer scale to micrometer scale range). The second trench TRC2may also be referred to as a nano or micro ripple. When the trench TRC is formed in at least a double structure as described above, an alignment characteristic of the light emitting elements LD may be improved. For example, even though the light emitting elements LD are aligned under an influence of the electromagnetic field, the eccentric alignment of the light emitting elements LD may be prevented by controlling an alignment region of the light emitting elements LD by the first trench TRC1. For example, the light emitting elements LD may be mounted in the first trench TRC1, and thus the light emitting elements LD may be prevented from being arranged close to the first bank pattern portion BNP1or the second bank pattern portion BNP2. Accordingly, contact defects of the light emitting elements LD may be prevented or reduced, the utilization rate of the light emitting elements LD may be increased, and the light efficiency of the pixel PXL may be improved. The light emitting elements LD may also be prevented from rotating in an aligned position or being concentrated in one region by the second trenches TRC2forming an uneven surface on the bottom surface or the like of the first trench TRC1. For example, the light emitting elements LD may be arranged at a predetermined distance or more by the second trenches TRC2, and/or may be aligned in a direction intersecting (for example, an orthogonal direction to) the extension direction (for example, the second direction DR2) of the first and second electrodes ELT1and ELT2(or the first and second bank pattern portions BNP1and BNP2). In an embodiment, when each of at least one or more light emitting elements LD are partially inserted into any one second trench TRC2, the light emitting elements LD may be more effectively prevented from deviating from the aligned position. When the second trenches TRC2are arranged at a distance so that the light emitting elements LD are not in contact with each other in consideration of the size (for example, the diameter D or the like) of the light emitting elements LD, the light emitting elements LD may be more effectively prevented from being concentrated. However, the embodiments are not limited thereto. For example, in another embodiment, each of the second trenches TRC2may have a size and/or a shape that is difficult to accommodate the light emitting element LD. However, even in this case, the light emitting elements LD may be prevented from rotating in the aligned position or being concentrated. The first contact electrode CNE1and the second contact electrode CNE2may be formed on the first and second end portions EP1and EP2of the light emitting elements LD, respectively. Accordingly, the light emitting elements LD may be stably connected between the first and second electrodes ELT1and ELT2. The first contact electrode CNE1may be disposed on the first end portion EP1of each of the light emitting elements LD arranged in the forward direction and the first electrode ELT1. The first contact electrode CNE1may be connected to at least the first end portions EP1of the light emitting elements LD. For example, the first contact electrode CNE1may be connected to the first end portions EP1of the light emitting elements LD and the first electrode ELT1, to electrically connect the first end portions EP1to the first electrode ELT1. The first contact electrode CNE1may also stably fix the first end portions EP1of the light emitting elements LD. The second contact electrode CNE2may be disposed on the second end portion EP2of each of the light emitting elements LD arranged in the forward direction and the second electrode ELT2. The second contact electrode CNE2may be connected to at least the second end portions EP2of the light emitting elements LD. For example, the second contact electrode CNE2may be connected to the second end portions EP2of the light emitting elements LD and the second electrode ELT2, to electrically connect the second end portions EP2to the second electrode ELT2. The second contact electrode CNE2may also stably fix the second end portions EP2of the light emitting elements LD. AlthoughFIG.5illustrates the light emitting elements LD connected in parallel, the embodiments are not limited thereto. For example, the pixel PXL may include a light emitting unit EMU having a series or series and parallel structure including light emitting elements LD connected to at least two series stages. The light emitting unit EMU may further include at least one intermediate electrode connected between the first and second electrodes ELT1and ELT2through the light emitting elements LD, and/or at least one contact electrode for connecting the intermediate electrode to adjacent light emitting elements LD. The bank BNK may be disposed around the light emitting area EMA to surround the light emitting area EMA of each pixel PXL. For example, the bank BNK may be disposed in a boundary area of each pixel area PXA and/or in an area between adjacent pixels PXL to surround each light emitting area EMA. For example, the bank BNK may include an opening corresponding to the light emitting area EMA of each pixel PXL, and may have a mesh shape in the entire display area DA. In an embodiment, the bank BNK may further include an opening corresponding to the separation area SPA between adjacent pixels PXL in the first direction DR1and/or the second direction DR2. Accordingly, alignment lines may be easily disconnected in the separation area SPA to separate the alignment lines into the individual electrodes of each pixel PXL. The bank BNK may or may not partially overlap the first electrode ELT1and/or the second electrode ELT2. For example, the first electrode ELT1and/or the second electrode ELT2may extend to an outer portion of the light emitting area EMA to overlap the bank BNK, or may be disconnected in the light emitting area EMA so as not to overlap the bank BNK. The bank BNK may or may not overlap the first contact hole CH1and/or the second contact hole CH2. For example, the first contact hole CH1and/or the second contact hole CH2may be formed to overlap the bank BNK, or may be formed in each light emitting area EMA and not overlap the bank BNK. The bank BNK may include at least one light blocking and/or reflective material to prevent light leakage between adjacent pixels PXL. The bank BNK may include at least one black matrix material (for example, at least one light blocking material), a color filter material of a specific color, and/or the like. For example, the bank BNK may be formed of a black opaque pattern to block light transmission. In supplying the light emitting elements LD to each pixel PXL, the bank BNK may function as a dam structure defining each light emitting area EMA to which the light emitting elements LD are supplied. For example, each light emitting area EMA may be partitioned by the bank BNK, and thus a light emitting element ink of a desired type and/or amount may be supplied to the light emitting area EMA. In an embodiment, the bank BNK may be simultaneously formed on the same layer as the bank pattern BNP in a process of forming the bank pattern BNP of the pixels PXL. In another embodiment, the bank BNK may be formed on a layer the same as or different from that of the bank pattern BNP through a process separate from the process of forming the bank pattern BNP. In an embodiment, at least double trenches TRC may be formed corresponding to a predetermined light emitting element array region, and thus the alignment characteristics of the light emitting elements LD may be improved. For example, the alignment position of the light emitting elements LD may be controlled by the trench TRC so that the light emitting elements LD are not eccentrically aligned. The second trenches TRC2may control the light emitting elements LD to be more evenly arranged in each light emitting element array region where the first trench TRC1is formed. Accordingly, the utilization rate of the light emitting elements LD supplied to each light emitting area EMA of each pixel area PXA may be increased, and light emission characteristics of the pixel PXL such as light emission luminance and uniformity may be improved. FIGS.6to8are schematic cross-sectional views illustrating the pixel PXL according to an embodiment. For example,FIGS.6and7illustrate different embodiments of a cross section of the pixel PXL taken along line II˜II′ ofFIG.5. In comparison withFIG.6, the embodiment ofFIG.7further includes a fourth insulating layer INS4disposed on the first contact electrode CNE1.FIG.8illustrates an embodiment of a cross section of the pixel PXL taken along line III˜III′ ofFIG.5. FIGS.6to8, illustrate as an example of circuit elements that may be disposed on a circuit layer PCL, a transistor TR (for example, a transistor connected to the first electrode ELT1through the first contact hole CH1and the bridge pattern BRP). As an example of a line that may be disposed on the circuit layer PCL, the second power line PL2connected to the second electrode ELT2through the second contact hole CH2is shown. Referring toFIGS.3to8, the pixel PXL and the display device including the same according to an embodiment may include the circuit layer PCL and a display layer DPL disposed to overlap each other on a surface of the base layer BSL. For example, the display area DA may include the circuit layer PCL disposed on a surface of the base layer BSL, and the display layer DPL disposed on the circuit layer PCL. However, the positions of the circuit layer PCL and the display layer DPL on the base layer BSL may vary according to the embodiments. The circuit elements (for example, the transistors TR and the storage capacitors Cst) comprising the pixel circuit PXC of the corresponding pixel PXL and various lines connected to the circuit elements may be disposed in each pixel area PXA of the circuit layer PCL. The first and second electrodes ELT1and ELT2, the light emitting elements LD, and/or the first and second contact electrodes CNE1and CNE2comprising the light emitting unit EMU of a corresponding pixel PXL may be disposed in each pixel area PXA of the display layer DPL. The circuit layer PCL may include insulating layers in addition to the circuit elements and the lines. For example, the circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and/or a passivation layer PSV sequentially stacked on a surface of the base layer BSL. The circuit layer PCL may further include a first conductive layer including at least one light blocking layer (or the bottom metal layer BML of the transistor TR) or the like disposed under at least a portion of the transistor TR. For example, the first conductive layer may be disposed between the base layer BSL and the buffer layer BFL and may include the bottom metal layer BML that overlaps a gate electrode GE and/or a semiconductor pattern SCP of at least one transistor TR. In an embodiment, the bottom metal layer BML may be connected to one electrode of a corresponding transistor TR. For example, as illustrated inFIG.4, when the first transistor M1includes the bottom metal layer BML, the bottom metal layer BML may be connected to a source electrode (or a drain electrode) of the first transistor M1. The buffer layer BFL may be disposed on one surface of the base layer BSL including the first conductive layer. The buffer layer BFL may prevent an impurity from diffusing into each circuit element. A semiconductor layer may be disposed on the buffer layer BFL. The semiconductor layer may include the semiconductor pattern SCP of each transistor TR. The semiconductor pattern SCP may include a channel region overlapping the gate electrode GE, and first and second conductive regions (for example, a source region and a drain region) disposed on both sides of the channel region. The semiconductor pattern SCP may be formed of polysilicon, amorphous silicon, oxide semiconductor, or the like. The channel region of the semiconductor pattern SCP may be a semiconductor pattern that is not doped with an impurity, and may be an intrinsic semiconductor, and each of the first and second conductive regions of the semiconductor pattern SCP may be a semiconductor pattern doped with a predetermined impurity. In an embodiment, the semiconductor patterns SCP of the transistors TR comprising each pixel circuit PXC may be formed of substantially the same or similar material. For example, the semiconductor pattern SCP of the transistors TR may be formed of the same material among polysilicon, amorphous silicon, and oxide semiconductor. In another embodiment, some of the transistors TR and the other of the transistors TR may include semiconductor patterns SCP formed of different materials. For example, the semiconductor pattern SCP of some of the transistors TR may be formed of polysilicon or amorphous silicon, and the semiconductor pattern SCP of the other of the transistors TR may be formed of oxide semiconductor. The gate insulating layer GI may be disposed on the semiconductor layer. A second conductive layer may be disposed on the gate insulating layer GI. The second conductive layer may include the gate electrode GE of each transistor TR. The second conductive layer may further include one electrode of the storage capacitor Cst and/or a predetermined line (for example, the scan line SL). The first interlayer insulating layer ILD1may be disposed on the second conductive layer. A third conductive layer may be disposed on the first interlayer insulating layer ILD1. The third conductive layer may include first and second transistor electrodes TE1and TE2of each transistor TR. Here, the first and second transistor electrodes TE1and TE2may be source and drain electrodes. The third conductive layer may further include one electrode of the storage capacitor Cst and/or a predetermined line (for example, the data line DL). The second interlayer insulating layer ILD2may be disposed on the third conductive layer. A fourth conductive layer may be disposed on the second interlayer insulating layer ILD2. Each of the buffer layer BFL, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, each of the buffer layer BFL, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2may include various types organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. The fourth conductive layer may include the bridge pattern BRP connecting the circuit layer PCL and the display layer DPL and/or a predetermined line (for example, the first power line PL1and/or the second power line PL2). The bridge pattern BRP may be connected to the first electrode ELT1of the light emitting unit EMU through the first contact hole CH1or the like. The second power line PL2may be connected to the second electrode ELT2of the light emitting unit EMU through the second contact hole CH2or the like. Each of conductive patterns, electrodes and/or lines forming the first to fourth conductive layers may have conductivity by including at least one conductive material, and the embodiments are not particularly limited by the conductive material. For example, each of the conductive patterns, electrodes, and/or lines forming the first to fourth conductive layers may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but the embodiments are not limited thereto. The passivation layer PSV may be disposed on the fourth conductive layer. According to an embodiment, the passivation layer PSV may include at least an organic insulating layer and may substantially planarize a surface of the circuit layer PCL. The display layer DPL may be disposed on the passivation layer PSV. The passivation layer PSV may be comprised of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the passivation layer PSV may include at least one layer of an organic insulating layer and may substantially planarize the surface of the pixel circuit layer PCL. In an embodiment, the organic insulating layer may include at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a poly-phenylene ethers resin, a poly-phenylene sulfides resin, and a benzocyclobutene resin. The display layer DPL may include the light emitting unit EMU of each pixel PXL. For example, the display layer DPL may include the first and second electrodes ELT1and ELT2disposed in the light emitting area EMA of each pixel PXL, the light emitting elements LD arranged between the first and second electrodes ELT1and ELT2, and the first and second contact electrodes CNE1and CNE2connecting the first and second electrodes ELT1and ELT2and the light emitting elements LD. The display layer DPL may further include the bank pattern BNP for protruding one region of the first and second electrodes ELT1and ELT2in the upward direction, and the bank BNK surrounding each light emitting area EMA. The display layer DPL may further include at least one conductive layer, insulating layer, and/or the like. For example, the display layer DPL may include the bank pattern BNP, the first and second electrodes ELT1, ELT2, the first insulating layer INS1, the light emitting elements LD, the second insulating layer INS2, the first and second contact electrodes CNE1and CNE2, and a third insulating layer INS3sequentially disposed and/or formed on the circuit layer PCL. In an embodiment, the first and second contact electrodes CNE1and CNE2may be disposed on the same layer as shown inFIG.6. In another embodiment, the first and second contact electrodes CNE1and CNE2may be disposed separately on different layers as shown inFIG.7. In this case, the display layer DPL may further include the fourth insulating layer INS4interposed between the first and second contact electrodes CNE1and CNE2. For example, the fourth insulating layer INS4may cover the first contact electrode CNE1, and an end of the fourth insulating layer INS4may be interposed between the first contact electrode CNE1and the second contact electrode CNE2. The position of the bank BNK on the cross section may vary according to the embodiments. In an embodiment, the bank BNK may be formed on the first insulating layer INS1. In other embodiments, the bank BNK may be disposed on the same layer as the bank pattern BNP. The bank BNK may or may not overlap the bank pattern BNP. The bank pattern BNP may be disposed on a surface of the base layer BSL on which the circuit layer PCL is selectively formed. The bank pattern BNP may be formed as a separate or integral pattern. The bank pattern BNP may protrude in a height direction (for example, the third direction DR3) of the base layer BSL on the surface of the base layer BSL on which the circuit layer PCL is formed. Accordingly, a region of the first and second electrodes ELT1and ELT2disposed on the bank pattern BNP may protrude in the upward direction. The bank pattern BNP may include an insulating material including at least one inorganic material and/or organic material. For example, the bank pattern BNP may include at least one layer of inorganic layer including various inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or the like. Alternatively, the bank pattern BNP may include at least one layer of an organic layer including various types of organic insulating materials, or may be formed of a single layer or multiple layer of insulators including organic/inorganic materials in combination. A reflective wall may be formed around the light emitting elements LD by the bank pattern BNP and the first and second electrodes ELT1and ELT2disposed thereon. For example, when the first and second electrodes ELT1and ELT2include a reflective electrode layer, light emitted from both end portions of the light emitting elements LD may be reflected from the reflective electrode layer, and may be emitted in an upward direction of each pixel PXL. The bank pattern BNP may have various shapes. In an embodiment, the bank pattern BNP may be formed to have the side wall SDW inclined at a predetermined range of angle with respect to the base layer BSL as shown inFIGS.6and7. In another embodiment, the side wall SDW of the bank pattern BNP may have a curved surface or a stepped shape. For example, the bank pattern BNP may have a cross section of a semicircle or semi-ellipse shape, and the like. The first and second electrodes ELT1and ELT2may be disposed on the bank pattern BNP. According to an embodiment, the first and second electrodes ELT1and ELT2may protrude in the height direction of the base layer BSL while having a shape corresponding to the bank pattern BNP in a region overlapping the bank pattern BNP. Each of the first and second electrodes ELT1and ELT2may include at least one conductive material. For example, the first and second electrodes ELT1and ELT2may include at least one metal among various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), and the like, an alloy thereof, a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine doped tin oxide (FTO), and a conductive polymer such as PEDOT, but is not limited thereto. For example, the first and second electrodes ELT1and ELT2may include other conductive materials such as carbon nanotubes or graphene. The first and second electrodes ELT1and ELT2may have conductivity by including at least one of various conductive materials, and the embodiments are not limited by the materials. The first and second electrodes ELT1and ELT2may include the same conductive material or may include different conductive materials. Each of the first and second electrodes ELT1and ELT2may comprise a single layer or multiple layers. For example, the first and second electrodes ELT1and ELT2may include a reflective electrode layer including a reflective conductive material (for example, metal). The first and second electrodes ELT1and ELT2may selectively further include at least one of a transparent electrode layer of at least one layer disposed on and/or under the reflective electrode layer, and a conductive capping layer of at least one layer covering an upper portion of the reflective electrode layer and/or the transparent electrode layer. The first insulating layer INS1may be disposed on a region of the first and second electrodes ELT1and ELT2. For example, the first insulating layer INS1may be formed to cover a region of each of the first and second electrodes ELT1and ELT2, and may include an opening exposing another region of each of the first and second electrodes ELT1and ELT2. For example, the first insulating layer INS1may include openings formed on an upper surface of the bank pattern BNP. In another embodiment, the first insulating layer INS1may also include contact holes for connecting the first and second electrodes ELT1and ELT2to the first and second contact electrodes CNE1and CNE2, respectively. The first insulating layer INS1may be comprised of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. In an embodiment, the first insulating layer INS1may include at least one layer of inorganic insulating layer including at least one type of inorganic insulating material including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). In a region where the first insulating layer INS1is opened, the first and second electrodes ELT1and ELT2may be electrically connected to the first and second contact electrodes CNE1and CNE2, respectively. In an embodiment, the first insulating layer INS1may be formed to entirely cover the first and second electrodes ELT1and ELT2. After the light emitting elements LD are supplied and aligned on the first insulating layer INS1, the first insulating layer INS1may be partially opened to expose one region of the first and second electrodes ELT1and ELT2. Since the first and second electrodes ELT1and ELT2are formed and then covered by the first insulating layer INS1or the like, the first and second electrodes ELT1and ELT2may be prevented from being damaged in a subsequent process. In an embodiment, the first insulating layer INS1may include the trench TRC corresponding to the light emitting element arrangement region between the first and second electrodes ELT1and ELT2. The trench TRC may accommodate the light emitting elements, and have a shape and an area capable of accommodating the light emitting elements LD. For example, the first trench TRC1may have the width Wt1and the length Lt such that it may accommodate the light emitting elements LD. In the embodiments, the trench TRC may be formed in a shape and a size that ensures sufficient connection space between the light emitting elements LD and the first and second contact electrodes CNE1and CNE2. For example, the trench TRC may have a depth DTH capable of partially accommodating the light emitting elements LD in a thickness or depth direction (for example, the third direction DR3). For example, a depth DTH1of the first trench DTH1, a depth DTH2of the second trench DTH2, and/or the total depth DTH of the trench TRC including the first trench TRC1and the second trench TRC2may be equal to or less than the diameter D (or the width of the cross section) of each of the light emitting elements LD. For example, when the second trenches DTH2have the depth DTH2less than the diameter D (or the width of the cross section) of the light emitting elements LD, the light emitting elements LD may protrude above the second trenches TRC2. Accordingly, a sufficient contact area between the first and second end portions EP1and EP2of the light emitting elements LD and the first and second contact electrodes CNE1and CNE2may be stably insured. The trench TRC (or the first insulating layer INS1including the region in which the trench TRC is formed) may cover the first and second electrodes ELT1and ELT2. Accordingly, the first and second electrodes ELT1and ELT2may not be directly exposed in a region where the light emitting elements LD are arranged. For example, when aligning the light emitting elements LD, the first and second electrodes ELT1and ELT2may be entirely covered by the first insulating layer INS1. In aligning the light emitting elements LD between the first and second electrodes ELT1and ELT2, the light emitting elements LD may be prevented from being in direct contact with the first and second electrodes ELT1and ELT2. Accordingly, a current (for example, a large current due to an alignment signal) may be prevented from flowing through the light emitting elements LD in aligning the light emitting elements LD, thereby preventing damage to the light emitting elements LD. In an embodiment, the trench TRC may not be formed in the first insulating layer INS1. The trench TRC may be formed on another insulating layer, substrate, and/or the like positioned under the light emitting elements LD. For example, when the first insulating layer INS1is omitted or integrated with the passivation layer PSV, the first and second electrodes ELT1and ELT2may be spaced apart at a distance equal to or greater than the length L of each of the light emitting elements LD, and a trench for accommodating the light emitting elements LD may be formed in the passivation layer PSV in correspondence with a region between the first and second electrodes ELT1and ELT2. The light emitting elements LD may be supplied and aligned in the light emitting area EMA in which the first insulating layer INS1or the like is formed. Before the light emitting elements LD are supplied, the bank BNK may be formed around the light emitting area EMA. For example, the bank BNK may be formed in the display area DA to surround each light emitting area EMA. In an embodiment, at least some of the light emitting elements LD may be disposed in a horizontal direction, a diagonal direction, or the like between a pair of first and second electrodes ELT1and ELT2so that both end portions (the first and second end portions EP1and EP2) overlap the first and second electrodes ELT1and ELT2. In another embodiment, at least some of the light emitting elements LD may be disposed between the adjacent pair of first and second electrodes ELT1and ELT2and may not overlap the first and second electrodes ELT1and ELT2. The second insulating layer INS2may be disposed on a region of the light emitting elements LD. For example, the second insulating layer INS2may be disposed on a region of the light emitting elements LD while exposing the first and second end portions EP1and EP2of each of the light emitting elements LD. For example, the second insulating layer INS2may be disposed only on the center region of each of the light emitting elements LD. The second insulating layer INS2may be formed in an independent pattern in the light emitting area EMA of each pixel PXL, but the embodiments are not limited thereto. The second insulating layer INS2may be comprised of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the second insulating layer INS2may include various types of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), a photoresist (PR) material, and the like. When the second insulating layer INS2is formed on the light emitting elements LD after the alignment of the light emitting elements LD is completed, the light emitting elements LD may be prevented from deviating from the aligned position. In an embodiment, when a separation space between the first insulating layer INS1and the light emitting elements LD is present by a step and/or the trench TRC formed by the first and second electrodes ELT1and ELT2, at least a portion of the separation space may be filled by the insulating material forming the second insulating layer INS2. According to an embodiment, the separation space may not be completely filled. Both end portions of the light emitting elements LD, which are not covered by the second insulating layer INS2(the first and second end portions EP1and EP2), may be covered by the first and second contact electrodes CNE1and CNE2, respectively. The first and second contact electrodes CNE2and CNE2may be formed to be spaced apart from each other. For example, the first and second contact electrodes CNE1and CNE2may be disposed with the second insulating layer INS2interposed between them, and may be disposed to be spaced apart from each other on the first and second end portions EP1and EP2of at least one light emitting element LD. The first and second contact electrodes CNE1and CNE2may also be disposed on the first and second electrodes ELT1and ELT2to cover exposed regions of each of the first and second electrodes ELT1and ELT2. For example, the first and second contact electrodes CNE1and CNE2may be disposed at least one region of each of the first and second electrodes ELT1and ELT2to be directly/indirectly in contact with each of the first and second electrodes ELT1and ELT2on the bank pattern BNP or around the bank pattern BNP. Accordingly, the first and second contact electrodes CNE1and CNE2may be electrically connected to the first and second electrodes ELT1and ELT2, respectively. Each of the first and second electrodes ELT1and ELT2may be electrically connected to the first end portion EP1or the second end portion EP2of at least one adjacent light emitting element LD through the first and second contact electrodes CNE1and CNE2. When the first and second contact electrodes CNE1and CNE2are formed on the same layer as in the embodiment ofFIG.6, the first and second contact electrodes CNE1and CNE2may be formed simultaneously in the same process, or may be sequentially formed, and the fourth insulating layer INS4may be omitted. The manufacturing process of the pixel PXL and a display device including the pixel PXL may be simplified. As illustrated inFIG.7, when the first and second contact electrodes CNE1and CNE2are formed on different layers with the fourth insulating layer INS4interposed between them, the first and second contact electrodes CNE1and CNE2may be more stably separated. For example, the fourth insulating layer INS4may be disposed to cover the first contact electrode CNE1. The fourth insulating layer INS4may be comprised of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. In an embodiment, the fourth insulating layer INS4may include at least one layer of inorganic insulating layer including at least one type of inorganic insulating material including silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). When the second insulating layer INS2and/or the fourth insulating layer INS4are/is formed on the light emitting elements LD, electrical stability between the first and second end portions EP1and EP2of the light emitting elements LD may be assured. Accordingly, a short circuit defect may be prevented from occurring between the first and second end portions EP1and EP2of the light emitting elements LD. The first and second contact electrodes CNE1and CNE2may be formed of various transparent conductive materials. For example, the first and second contact electrodes CNE1and CNE2may include at least one transparent conductive material including ITO, IZO, ITZO, ZnO, AZO, GZO, ZTO, GTO, and FTO, and may be implemented to be substantially transparent or translucent to satisfy a predetermined transmittance. Accordingly, the light emitted from the light emitting elements LD through each of the first and second end portions EP1and EP2may pass through the first and second contact electrodes CNE1and CNE2and may be emitted to the outside of the display panel PNL. The third insulating layer INS3may be disposed on the first and second contact electrodes CNE1and CNE2. For example, the third insulating layer INS3may be entirely formed and/or disposed on the display area DA to cover the bank pattern BNP, the first and second electrodes ELT1and ELT2, the first insulating layer INS1, the bank BNK, the light emitting elements LD, the second insulating layer INS2, the first and second contact electrodes CNE1and CNE2, the third insulating layer INS3and/or the fourth insulating layer INS4. The third insulating layer INS3may include at least one layer of an inorganic layer and/or organic layer. For example, the third insulating layer INS3may be comprised of a single layer or multiple layers, and may include at least one inorganic insulating material and/or organic insulating material. For example, the third insulating layer INS3may include organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), or aluminum oxide (Al2O3). In an embodiment, the third insulating layer INS3may include a thin film encapsulation layer of a multilayer structure. For example, the third insulating layer INS3may be comprised of a thin film encapsulation layer of a multilayer structure including at least two layers of inorganic insulating layers and at least one layer of organic insulating layer interposed between the at least two layers of inorganic insulating layers. However, the embodiments are not limited to these materials and/or structures of the third insulating layer INS3. In an embodiment, at least one of an overcoat layer, a filler layer, an upper substrate, and/or the like may be further disposed on the third insulating layer INS3. FIG.9is a schematic plan view illustrating the pixel PXL according to an embodiment.FIG.9illustrates a modification toFIG.5.FIGS.10to12are schematic cross-sectional views illustrating the pixel PXL according to an embodiment, respectively. For example,FIGS.10and11illustrate different embodiments of the cross section of the pixel PXL taken along lines IV˜IV′ ofFIG.9. Compared toFIG.10,FIG.11further includes a fourth insulating layer INS4disposed on the first contact electrode CNE1.FIG.12illustrates an embodiment of the cross section of the pixel PXL taken along line V˜V′ ofFIG.9. In describing the embodiments ofFIGS.9to12, the same reference numerals are assigned to configurations similar to or identical to those ofFIGS.5to8. Referring toFIGS.9to12, each of the second trenches TRC2may have a shape and an area capable of accommodating at least one light emitting element LD in a plan view. For example, the second trenches TRC2may have a width Wt2′ equal to or greater than the diameter D (or the width of the cross section) of the light emitting elements LD, and may have a length Lt2′ equal to or greater than the length L of the light emitting elements LD. At least one of light emitting elements LD may be mounted and/or accommodated in at least one of the second trenches TRC2. The trench TRC may have a width (for example, the width Wt1of the first trench TRC1) capable of accommodating the light emitting elements LD as a whole by including the first and second trenches TRC1and TRC2. The trench TRC may have a depth DTH capable of at least partially accommodating the light emitting elements LD. Accordingly, the light emitting elements LD may be stably arranged in the trench TRC. FIG.13is a schematic perspective view schematically illustrating the trench TRC and a method of forming the trench TRC according to an embodiment. For example,FIG.13schematically illustrates a method of forming the trench TRC shown inFIGS.5and9. Referring toFIGS.5to13, the trench TRC may be formed in the first insulating layer INS1through an etching method using a laser beam. For example, the trench TRC of a desired size and/or shape may be formed at a desired position by adjusting a size, movement path and distance, intensity (power), a wavelength, a polarization direction, and/or the like of the laser beam. The first trench TRC1may have a shape and an area corresponding to the size, a movement direction DRm, and a movement distance of the laser beam. For example, the first trench TRC1may have the width Wt1corresponding to a length of the laser beam along the first direction DR1, and may have the shape and the length Lt1corresponding to the movement path of the laser beam. The first trench TRC1may have the depth DTH1corresponding to the intensity of the laser beam. Therefore, the first trench TRC1of a desired size and/or shape may be formed at a desired position by adjusting the size, the movement path and/or distance, the intensity, and/or the like of the laser beam. The second trenches TRC2may have a shape, a direction, a period (or interval), and a size corresponding to the polarization direction DRp, the wavelength, and the intensity of the laser beam. For example, each of the second trenches TRC2may be generated and/or extended in a direction orthogonal to the polarization direction DRp of the laser beam, and may have a period corresponding to the wavelength of the laser beam. For example, when the polarization direction DRp of the laser beam is identical to (or is parallel to) the movement direction DRm, each of the second trenches TRC2may be generated to be extended in the direction orthogonal to the movement direction DRm of the laser beam, and may be generated and/or arranged in a period corresponding to ¼ of the wavelength of the laser beam (or λ/4) along the movement direction DRm of the laser beam. The second trenches TRC2may have the depth DTH2corresponding to the intensity of the laser beam. Therefore, the second trenches TRC2may be formed in the desired shape, direction, period, and/or size at the desired positions by adjusting the polarization direction DRp, wavelength, intensity, and the like of the laser beam. In an embodiment, in order to form a double trench TRC of a nanometer scale to a micrometer scale size, an ultra-short wave laser such as a femtosecond laser (for example, a 290 fs laser) may be used. For example, the first and second trenches TRC1and TRC2may be formed using an ultra-short wave laser beam or an extremely ultra-short wave laser beam obtained by splitting the ultra-short wave laser beam. According to an embodiment, when the second trenches TRC2are formed at a distance in the range of about 200 nm to about 300 nm (for example, approximately 250 nm), a laser beam of a wavelength of approximately 1030 nm may be used. In consideration of the shape, direction, size, and/or period of the trench TRC to be formed, the laser beam to be used to form the trench TRC may change. FIGS.14and15are schematic plan views illustrating pixels PXL according to the embodiments.FIGS.14and15illustrate modifications toFIG.5. Referring toFIGS.14and15, the shape, position, size, structure, and/or the like of the first and second electrodes ELT1and ELT2may be changed in the embodiments. The shape, position, size, and/or the like of the bank pattern BNP, the trench TRC, the first and second contact electrodes CNE1and CNE2, and/or the bank BNK may also be changed according to the shape, position, size, structure, and/or the like of the first and second electrodes ELT1and ELT2. For example, in the embodiment ofFIG.14, the first electrode ELT1may have a circular (or elliptical) shape, and the second electrode ELT2may have a circular (or elliptical) ring shape concentric with the first electrode ELT1and surrounding the first electrode ELT1. The trench TRC may have a circular (or elliptical) ring shape concentric with the first and second electrodes ELT1and ELT2, and may or may not partially overlap the first electrode ELT1and/or the second electrode ELT2. Similarly, the bank pattern BNP and the first and second contact electrodes CNE1and CNE2may have a circular (or elliptical) shape conforming to the shape of the first and second electrodes ELT1and ELT2, or may have a ring shape corresponding thereto. In the embodiment ofFIG.15, the first electrode ELT1may have a polygonal shape (for example, a triangle), and the second electrode ELT2may have a polygonal (for example, a triangular) ring shape concentric with the first electrode ELT1and surrounding the first electrode ELT1. The trench TRC may have a polygonal (for example, triangular) ring shape concentric with the first and second electrodes ELT1and ELT2, and may or may not partially overlap the first electrode ELT1and/or the second electrode ELT2. Similarly, the bank pattern BNP and the first and second contact electrodes CNE1and CNE2may also have a polygonal shape (for example, a triangle) conforming to the shape of the first and second electrodes ELT1and ELT2, or may have a ring shape corresponding thereto. The bank BNK may have a shape conforming to the shape of the first and second electrodes ELT1and ELT2, or may have an opening corresponding to a predetermined light emitting area EMA regardless of the shape of the first and second electrodes ELT1and ELT2. For example, the bank BNK may have a circular (or elliptical) or polygonal (for example, triangular) opening conforming to the shape of the first and second electrodes ELT1and ELT2, but the embodiments are not limited thereto. FIG.16is a schematic plan view illustrating the pixel PXL according to an embodiment.FIG.16illustrates a modification toFIG.5.FIG.17is a schematic perspective view illustrating the trench TRC and a method of forming the trench TRC according to an embodiment.FIG.17schematically illustrates a method of forming the trench TRC shown inFIG.16. Referring toFIGS.16and17, each of the second trenches TRC2may extend vertically in the second direction DR2and may be sequentially arranged along, or disposed in, the first direction DR1. For example, a formation direction of the second trenches TRC2may be changed by changing the polarization direction DRp of the laser beam to the first direction DR1crossing, or intersecting, the movement direction DRm of the laser beam, for example, in an orthogonal direction to the movement direction DRm. For example, each of the second trenches TRC2may extend in a direction substantially parallel to the extension direction of the first trench TRC1. However, the embodiments are not limited by the formation direction of the second trenches TRC2. For example, the second trenches TRC2may be formed in a diagonal direction or the like crossing, or intersecting, the first and second directions DR1and DR2. In the above-described embodiment, the uneven surface may be formed in the first trench TRC1by the second trenches TRC2. Accordingly, the alignment of the light emitting elements LD may be improved. FIG.18is a schematic plan view illustrating a pixel PXL according to an embodiment. For example,FIG.18illustrates modifications toFIGS.5and16.FIG.19is a schematic perspective view illustrating the trench TRC and a method of forming the trench TRC according to an embodiment.FIG.19schematically illustrates a method of forming the trench TRC shown inFIG.18. Referring toFIGS.18and19, each of the second trenches TRC2may have a dot shape (for example, a circular or elliptical shape) and may be dispersed in the first trench TRC1. The second trenches TRC2of the dot shape may be formed on the bottom surface of the first trench TRC1by changing the polarization direction DRp of the laser beam to a circular shape. In an embodiment, the second trenches TRC2may be distributed in a matrix form on the bottom surface of the first trench TRC1along the first and second directions DR1and DR2. However, the embodiments are not limited thereto. For example, in another embodiment, the second trenches TRC2may be irregularly distributed inside the first trench TRC1. In the embodiments, the uneven surface may be formed in the first trench TRC1by the second trenches TRC2. Accordingly, the alignment degree of the light emitting elements LD may be improved. FIGS.20to25are schematic plan views illustrating the pixel PXL according to the embodiments. For example,FIGS.20to23illustrate modifications of FIGS.5,9,16, and18, respectively, andFIGS.24and25illustrate different modifications ofFIG.5. Referring toFIGS.20to23, the trench TRC may not include the first trench TRC1and may only include the second trenches TRC2. Referring toFIGS.24and25, at least some of the second trenches TRC2disclosed in the above-described embodiments may be integrally connected to form one second trench TRC2. For example, a second trench TRC2of a zigzag shape may be formed by periodically changing the movement direction of the laser beam while moving the laser beam in a diagonal direction with respect to at least one of the first direction DR1and the second direction DR2. Continuous laser processing may be possible, and thus process efficiency may be improved. In the embodiments ofFIGS.24and25, the first trench TRC1may be selectively formed. For example, the trench TRC may include the first and second trenches TRC1and TRC2shown inFIGS.24and25. In other embodiments, the trench TRC may not include the first trench TRC1and may include only the second trench TRC2. As described above, the structure and/or shape of the trench TRC may be changed according to an embodiment. Although the technical spirit has been described in detail in accordance with the above-described embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. Those skilled in the art may understand that various modifications are possible within the scope of the technical spirit of the embodiments. The scope of the embodiments are not limited to the details described in the detailed description of the specification, but should be defined by the claims. It is to be construed that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope. | 106,797 |
11942509 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number. FIG.1illustrates a top view showing a trench and a via formed in a semiconductor stack in accordance with an embodiment of the present application.FIG.2illustrates a cross-sectional view taken along line A-A′ ofFIG.1. The semiconductor stack comprises a first semiconductor layer201, an active layer202and a second semiconductor layer203sequentially formed on a surface of a substrate10. One or a plurality of trenches21penetrates the second semiconductor layer203, the active layer202, and the first semiconductor layer201to expose a surface21sof the substrate10, and divides the semiconductor stack into a plurality of light-emitting units20, wherein the plurality of light-emitting units20is separated from each other by the trench21. In an embodiment of the present application, as shown inFIG.1andFIG.2, the light-emitting device1comprises a first light-emitting unit20aand a second light-emitting unit20b, wherein the first light-emitting unit20aand the second light-emitting unit20bare separated by the trench21, and the surface21sof the substrate10is exposed. In an embodiment of the present application (not shown), the light-emitting device1comprises a plurality of light-emitting units20arranged in an array having a rectangular shape, the plurality of light-emitting units20is separated from each other by a plurality of trenches21, wherein the plurality of light-emitting units20comprises same area and/or same shape, or different areas and/or different shapes, and the trenches21are connected to each other and continuously expose the surface21sof the substrate10. In an embodiment of the present application, in the top view of the light-emitting device1, the light-emitting device1comprises a polygonal shape such as a triangular shape, a hexagonal shape, a rectangular shape or a square shape. As shown inFIG.1, the light-emitting device1having the square shape is illustrated in the embodiment. The light-emitting device1comprises a substrate10having a plurality of outer sidewalls S located around the light-emitting device1to form a polygonal shape such as a triangular shape, a hexagonal shape, a rectangular shape or a square shape. The size of the light-emitting device1may be, for example, a square shape of 1000 μm*1000 μm or 700 μm*700 μm, or a rectangular shape of a similar size, but is not particularly limited thereto. The substrate10can be a growth substrate, comprising gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al2O3) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). In another embodiment, the substrate10can be a support substrate, the semiconductor stack which was originally epitaxially grown on the growth substrate can be transferred to the support substrate, and the growth substrate originally used for epitaxial growth is optionally removed according to the requirements of the application. The support substrate comprises a conductive material such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or an alloy of the above materials, or a thermally conductive material such as diamond, graphite or aluminum nitride. Although the feature is omitted in the figures, the side of the substrate10that is in contact with the semiconductor stack comprises a rough surface, and the rough surface comprises a surface having an irregular morphology or a surface having a regular morphology, for example, the surface having a plurality of hemispheres, the surface having a plurality of cones, or the surface having a plurality of pyramids. In an embodiment of the present application, a plurality of semiconductor layers comprising optical characteristics and semiconductor materials is formed on the substrate10by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating, wherein physical vapor deposition (PVD) comprises sputtering or evaporation. In an embodiment of the present application, the semiconductor stack comprises a buffer layer (not shown) formed between the first semiconductor layer201and the substrate10which can release the stress caused by lattice mismatch between the materials of the substrate10and the first semiconductor layer201so the lattice dislocation and the lattice defect are reduced and the epitaxial quality of the semiconductor stack is improved. The buffer layer comprises a single layer or a structure comprising a plurality of layers. In an embodiment, an aluminum nitride (AlN) layer formed by using PVD method can be the buffer layer formed between the first semiconductor layer201and the substrate10to improve the epitaxial quality of the semiconductor stack. In an embodiment, the method for forming aluminum nitride (AlN) is PVD, and the target is made of aluminum nitride. In another embodiment, a target made of aluminum reacts with a nitrogen source to form the aluminum nitride. The wavelength of the light emitted from the light-emitting device1is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack comprises a group III-V semiconductor material, such as AlxInyGa(1−x−y)N or AlxInyGa(1−x−y)P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer202, when the material of the semiconductor stack comprises AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack comprises InGaN series material, blue or deep blue light having a wavelength between 400 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack comprises AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted. The first semiconductor layer201and the second semiconductor layer203can be cladding layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer201is an n-type semiconductor and the second semiconductor layer203is a p-type semiconductor. The active layer202is formed between the first semiconductor layer201and the second semiconductor layer203. The electrons and holes combine in the active layer202under a current driving to convert electric energy into light energy and then light is emitted from the active layer202. The active layer202can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer123can be i-type, p-type, or n-type semiconductor. The first semiconductor layer201, the active layer202, or the second semiconductor layer203can be a single layer or a structure comprising a plurality of layers. As shown inFIG.2, each of the light-emitting units20is selectively etched to form one or a plurality of vias200, one or a plurality of surrounding parts204, and one or a plurality of semiconductor mesas205on each of the light-emitting units20. The semiconductor mesa205of each of the light-emitting units20is surrounded by one or the plurality of surrounding parts204. For example, after coating a photoresist and removing a portion of the photoresist, a photoresist pattern of the via200, the surrounding part204and the semiconductor mesa205is formed through a lithography process. Then, an etching process is provided to form the via200, the surrounding part204and the semiconductor mesa205by using the photoresist pattern as an etching mask. Specifically, each semiconductor mesa205is formed by removing a portion of the second semiconductor layer203and the active layer202to form a structure comprising the first semiconductor layer201, the active layer202and the second semiconductor layer203. Each of the vias200and the surrounding parts204is formed by removing a portion of the second semiconductor layer203and the active layer202to expose the first semiconductor layer201. The remaining photoresist pattern is removed after the etching process. In other words, the semiconductor mesa205comprises the first semiconductor layer201, the active layer202, and the second semiconductor layer203. The via200and the surrounding part204expose the first semiconductor layer201. The via200and the surrounding part204do not comprise the second semiconductor layer203and the active layer202formed thereon, As shown inFIG.2, each of the semiconductor mesas205comprises an upper surface t1and a lower surface b1. The active layer202comprises a first upper surface202tand a second lower surface202b, wherein the first upper surface202tof the active layer202is closer to the upper surface t1of the semiconductor mesa205than the second lower surface202bof the active layer202to the upper surface t1of the semiconductor mesa205. A first distance is between the upper surface t1of the semiconductor mesa205and the first upper surface202tof the active layer202, a second distance is between the lower surface b1of the semiconductor mesa205and the second lower surface202bof the active layer202, and the second distance is greater than the first distance. In an embodiment of the present application, when the growth substrate is removed from the semiconductor stack and the semiconductor stack is flipped to be mounted to the support substrate, each semiconductor mesa205comprises an upper surface t1and a lower surface b1. The active layer202comprises a first upper surface202tand a second lower surface202b, wherein the upper surface t1of the semiconductor mesa205and the first upper surface202tof the active layer202are respectively away from the support substrate than the lower surface b1of the semiconductor mesa205and the second lower surface202bof the active layer202to the support substrate. A first distance is between the upper surface t1of the semiconductor mesa205and the first upper surface202tof the active layer202, a second distance is between the lower surface b1of the semiconductor mesa205and the second lower surface202bof the active layer202, and the first distance is greater than the second distance. In a top view of the light-emitting device1, as shown inFIG.1, the shape(s) of one or the plurality of the vias200can be an ellipse, a circle, a rectangle, or any other shape. In an embodiment of the present application, as shown inFIG.1, each of the light-emitting units20comprises only one surrounding part204. In an embodiment, the surrounding part204is located at an outermost side of each of the light-emitting units20and continuously surrounds the light-emitting unit20. The outermost side of the light-emitting unit20comprises the surround part204circumferentially surrounding the light-emitting unit20. In a top view of the light-emitting device1, the shape of the surrounding part204comprises a polygon, such as a triangle, a hexagon, a rectangle, or any other shape. In other words, the shape of the surrounding part204corresponds to the shape of each of the light-emitting units20. The shape of each surrounding part204is similar to the shape of each of the light-emitting units20. In an embodiment, the shape of the surrounding part204comprises a rectangle, the shape of each of the light-emitting units20comprises a rectangle, and the surrounding part204is located at the outermost side of each of the light-emitting units20, wherein the corners of the rectangular light-emitting unit20can be rounded to avoid current crowding at the corners of each of the light-emitting units20. The surrounding part204continuously surrounds the second semiconductor layer203and the active layer202of each of the light-emitting units20by exposing the surface of the first semiconductor layer201at the outermost side of each of the light-emitting unit20. In another embodiment (not shown), in the top view of the light-emitting device1, the semiconductor mesa205comprises a wave shape, a zigzag shape or a square wave shape. Each of the light-emitting units20respectively comprises a plurality of surrounding parts204. The top view shape of each of the plurality of surrounding parts204comprises a rectangle, an ellipse or a circle, and the plurality of surrounding parts204is located at the outermost sides of each of the light-emitting units20to discontinuously surround the second semiconductor layer203and the active layer202of the semiconductor mesa205. The position of the plurality of surrounding parts204ais formed close to the concave part of the wave shape, the zigzag shape or the square wave shape. In order to avoid the electrical current locally crowding at the corner of the light-emitting unit20, the semiconductor stack comprising the second semiconductor layer203and the active layer202located at the corner of the light-emitting unit20are remained without being removed. The plurality of surrounding parts204are formed on the plurality of sides of each of the light-emitting units20by removing the second semiconductor layer203and the active layer202on the plurality of sides of each of the light-emitting units20. One or more surrounding parts204are located on one of the plurality of sides of each of the light-emitting units20. The number of surrounding parts204formed on one side of the plurality of sides may be the same or different from the number of surrounding parts204formed on the other side of the plurality of sides of each of the light-emitting units20. Taking one of the light-emitting units20as an example, the light-emitting unit20comprises one or more surrounding parts204formed on one side, and one or more surrounding parts204formed on the adjacent side or the opposite side, the number of surrounding parts204on the one side and the adjacent side may be the same or different, or the number of surrounding parts204on the one side and the opposite side may be the same or different. As shown inFIG.1, one or more vias200are located inside each of the light-emitting units20and are surrounded by one or the plurality of surrounding parts204. In other words, one or more vias200are respectively surrounded by the second semiconductor layer203and the active layer202of each of the light-emitting units20. The number and arrangement positions of the plurality of vias200are not limited, and that may be regularly arranged at a certain interval to uniformly spread the current in the horizontal direction. The plurality of vias200may be arranged in a plurality of columns, and the vias200of any adjacent two columns may be aligned or staggered from each other. The position of the contact layer and the electrode subsequently formed can be determined according to the arrangement position of the plurality of vias200. In an embodiment of the present application, the vias200on the adjacent two columns are staggered from each other, and a distance between the vias200of the adjacent two columns is the same as a distance between the vias200of the same column so that the plurality of vias200is closely arranged to uniformly spread the current. In an embodiment of the present application, considering the position of the contact layer and the electrode subsequently formed, the vias200of the adjacent two columns are staggered from each other, and a shortest distance between two vias200respectively in the adjacent two columns is smaller than a shortest distance between two vias200in the same column. In an embodiment of the present application, considering the position of the contact layer and the electrode subsequently formed, the vias200of the adjacent two columns are staggered from each other, and a shortest distance between the vias200of the adjacent two columns is larger than a shortest distance between the vias200of the same column. As shown inFIG.1andFIG.2, the first light-emitting unit20acomprises a first semiconductor mesa205a. An inner surface200asof the first semiconductor layer201is formed after removing a portion of the second semiconductor layer203and the active layer202. The inner surface200asof the first semiconductor layer201is formed on the one or the plurality of first vias200a. In the top view of the light-emitting device1, the plurality of first vias200ais not connected to each other. A first surrounding part204ais formed by removing a portion of the second semiconductor layer203and the active layer202around a plurality of sides of the first semiconductor mesa205a. An outer surface204asof the first semiconductor layer201is formed after removing the portion of the second semiconductor layer203and the active layer202. The first surrounding part204acomprises the outer surface204asof the first semiconductor layer201. In the top view of the light-emitting device1, as shown inFIG.1, the first surrounding part204acomprises a first inner recess2041aand a plurality of first outer recesses2042a. The first inner recess2041aand the plurality of first outer recesses2042aare connected to continuously surround the first semiconductor mesa205a. The first via200ais formed on the first semiconductor mesa205a, and the first surrounding part204asurrounds the first semiconductor mesa205a. As shown inFIG.1andFIG.2, the second light-emitting unit20bcomprises a second semiconductor mesa205b. An inner surface200bsof the first semiconductor layer201is formed after removing a portion of the second semiconductor layer203and the active layer202. The inner surface200bsof the first semiconductor layer201is formed on the one or the plurality of second vias200b. In the top view of the light-emitting device1, the plurality of second vias200bis not connected to each other. A second surrounding part204bis formed by removing a portion of the second semiconductor layer203and the active layer202to around a plurality of sides of the second semiconductor mesa205b. An outer surface204bsof the first semiconductor layer201is formed after removing the portion of the second semiconductor layer203and the active layer202. The second surrounding part204bcomprises the outer surface204bsof the first semiconductor layer201. In the top view of the light-emitting device1, as shown inFIG.1, the second surrounding part204bcomprises a second inner recess2041band a plurality of second outer recesses2042b. The first inner recess2041band the plurality of first outer recesses2042bare connected to continuously surround the first semiconductor mesa205b. The second via200bis formed on the second semiconductor mesa205b, and the second surrounding part204bsurrounds the second semiconductor mesa205b. As shown inFIG.1andFIG.2, the first light-emitting unit20aand the second light-emitting unit20bis separated by the trench21. The trench21is between the first inner recess2041aof the first light-emitting unit20aand the second inner recess2041bof the second light-emitting unit20b. As shown inFIG.2, from cross-sectional view, the first via200ais formed in the first semiconductor mesa205a, and the first inner recess2041aand the first outer recess2042aare respectively formed at two sides of the first semiconductor mesa205a. The second via200bis formed in the second semiconductor mesa205b, and the second inner recess2041band the second outer recess2042bare respectively formed at two sides of the second semiconductor mesa205b. The first via200aand the second via200beach comprises a first inclined surface S1having a first angle with respect to a horizontal extension surface of the inner surface200asor the inner surface200bsof the first semiconductor layer201, wherein the first angle is between 10 degrees and 80 degrees. The first surrounding part204aand the second surrounding part204beach comprises a second inclined surface S2having a second angle with respect to a horizontally extension surface of the outer surface204asor the outer surface204bsof the first semiconductor layer201, wherein the second angle is between 10 degrees and 80 degrees. If the first angle or the second angle is less than 10 degrees, an excessively low slope reduces the area of the active layer202, and a decreased area of the active layer202decreases luminance of the light-emitting device. If the first angle or the second angle is greater than 80 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the sidewalls of the first semiconductor layer201, the second semiconductor layer203, and/or the active layer202, thereby causing cracking of the film. In an embodiment, in order to maintain the symmetry of the structure to reduce the lithography misalignment, the angle difference between the first angle and the second angle is less than 20 degrees, preferably less than 10 degrees, more preferably less than 5 degrees. In an embodiment, the first semiconductor layer201of each of the light-emitting units20comprises a third surface S3having an angle between 10 degrees and 80 degrees with respect to the outer surface204asor the outer surface204bsof the first semiconductor layer201. In another embodiment, the first semiconductor layer201of each of the light-emitting units20comprises a third surface S3having an angle close to 90 degrees with respect to the outer surface204asor the outer surface204bsof the first semiconductor layer201, preferably between 60 degrees and 120 degrees, more preferably between 80 degrees and 110 degrees. In an embodiment, there is no other surface separating the third surface S3of the first semiconductor layer201and the outer sidewall S of the substrate10. The outer sidewall S of the substrate10may be flush with the third surface S3of the first semiconductor layer201, or have an oblique angle with respect to the third surface S3of the first semiconductor layer201, preferably an angle between 60 and 120 degrees, more preferably an angle between 80 to 110 degrees. In another embodiment, as shown inFIG.2, by removing the first semiconductor layer201, the second semiconductor layer202and the active layer203, the light-emitting device1comprises a dicing street10dexposing an upper surface10sof the substrate10, wherein the first surrounding part204ais formed between the dicing street10dand the first semiconductor mesa205a, and a second surrounding part204bis formed between the dicing street10dand the second semiconductor mesa205b. The third surface S3has a third angle with respect to the horizontal extension surface of the upper surface10sof the substrate10, wherein the third angle is between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably less than 40 degrees. The outer sidewall S of the substrate10may be perpendicular to the upper surface10sexposed by the dicing street10d, or may have a fourth angle with respect to the upper surface10sexposed by the dicing street10d, preferably, the fourth angle is between 60 degrees and 120 degrees, more preferably between 80 degrees and 110 degrees. In another embodiment, in order to completely cover the third surface S3with the insulating layer and the metal layer subsequently formed, the difference between the third angle and the second angle is greater than 15 degrees, preferably greater than 25 degrees, more preferably greater than 35 degrees. In the top view of the light-emitting device1, a plurality of light-emitting units20each comprises a polygon or a rectangle shape, and the plurality of light-emitting units20are arranged to form a rectangular array having a plurality of sides. The dicing street10dsurrounds the plurality of sides of the rectangular array formed by the plurality of light-emitting units20, and continuously exposes the upper surface10sof the substrate10. The dicing street10dis located at the outermost side of the light-emitting device1. The top view shape of the dicing street10dis the same as the shape of the rectangular array arranged by the plurality of light-emitting units20, for example, a rectangular or polygonal ring shape surrounds the outermost side of the rectangular array arranged by the plurality of light emitting units20. In an embodiment, the exposed upper surface10sof the dicing street10dis a rough surface. The rough surface may be a surface having an irregular shape or a surface having a regular shape, for example, a surface having a plurality of hemispherical shapes, a surface having a plurality of cones, or a surface having a plurality of pyramids. FIG.3illustrates a top view showing a contact electrode and a reflective layer formed on the semiconductor stack in accordance with an embodiment of the present application.FIG.4illustrates a cross-sectional view taken along line A-A′ ofFIG.3.FIG.5illustrates a top view of a first insulating layer, a contact electrode, a reflective layer and a second insulating layer in accordance with an embodiment of the present application.FIG.6illustrates a cross-sectional view taken along line A-A′ ofFIG.5. As shown inFIG.5, a first insulating layer50is formed on the substrate10and each of the light-emitting units20. One or a plurality of openings500of the first insulating layer50are formed on the first light-emitting unit20a, the second light-emitting unit20b, and the trench21by selective etching to expose the substrate10, the first semiconductor layer201of the first light-emitting unit20aand the first semiconductor layer201of the second light-emitting unit20b. In an embodiment, the one or the plurality of openings500of the first insulating layer50formed on the trench21exposes the first semiconductor layer201of the first inner recess2041aand the first semiconductor layer201of the second inner recess2041b. As shown inFIG.5andFIG.6, one or a plurality of first openings501aof the first insulating layer50is formed on the first inner recess2041aof the first light-emitting unit20aadjacent to a side of the trench21to expose the first semiconductor layer201of the first light-emitting unit20a. As shown inFIG.5, one or a plurality of second openings502aand502bof the first insulating layer50are respectively formed on the second semiconductor layer203of the first light-emitting unit20aand the second semiconductor layer203of the second light-emitting unit20bto expose the second semiconductor layer203, the contact electrode30, and/or the reflective layer40. As shown inFIG.5, one or a plurality of third openings503aof the first insulating layer50are formed on the plurality of first outer recesses2042aof the first light-emitting unit20ato expose the first semiconductor layer201of the first light-emitting unit20a. Another one or an another plurality of third openings503bof the first insulating layer50are formed on the plurality of second outer recesses2042bof the second light-emitting unit20bto expose the first semiconductor layer201of the second light-emitting unit20b. As shown inFIG.5, the fourth openings504a,504bof the first insulating layer50are respectively formed on the first via200aof the first light-emitting unit20aand the second via200bof the second light-emitting unit20bto expose the first semiconductor layer201. The remaining area shown inFIG.5is covered by the first insulating layer50. In an embodiment, the first insulating layer50comprises an insulating material having light transparency. For example, the material of the first insulating layer50comprises SiOx. In an embodiment, the first insulating layer50comprises two or more materials of different refractive indices alternately stacked to form a Distributed Bragg Reflector (DBR). In an embodiment, the first insulating layer50is laminated with sub-layers of SiO2/TiO2or SiO2/Nb2O5to selectively reflect light of a specific wavelength, thereby increasing the light extraction efficiency of the light-emitting device. When the peak emission wavelength of the light-emitting device1is λ, the optical thickness of the first insulating layer50can an integral multiple of λ/4. The peak emission wavelength refers to the wavelength having a strongest intensity in the emission spectrum of the light-emitting device1. The thickness of the first insulating layer50may have a deviation of ±30% on the basis of an integral multiple of the optical thickness λ/4. In an embodiment of the present application, the first insulating layer50comprises a non-conductive material comprising organic material, inorganic material or dielectric material. The organic material comprises Sub, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material comprises silicone or glass. The dielectric material comprises aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In an embodiment of the present application, the first insulating layer50comprises a thickness between 1000 angstrom (Å) and 20,000 angstrom (Å). In an embodiment of the present application, the material of the first insulating layer50comprises SiO2, TiO2, or SiNx. If the thickness of the first insulating layer50is less than 1000 angstrom (Å), the thinner thickness may make the insulating property of the first insulating layer50weak. Specifically, the first insulating layer50is formed on the etched first inclined surface S1and the etched second inclined surface S2. The first insulating layer50conformally formed on the inclined surface comprises an inclined slope. If the first insulating layer50comprises a thickness less than 1000 angstrom (Å), it may cause cracking of the film. In an embodiment of the present application, the material of the first insulating layer50comprises SiO2, TiO2or SiNx. If the thickness of the first insulating layer50is thicker than 20000 angstrom (Å), it is getting difficult to perform selective etching on the first insulating layer50. However, the above embodiments do not exclude other materials having a good covering extensibility or a high etch selectivity to avoid the problem caused by the thin thickness or the thick thickness of the first insulating layer50. The first insulating layer50comprises a side surface which is an inclined surface having an angle with respect to a horizontally extending surface of the inner surface200asor the outer surface204asof the first semiconductor layer201exposed through selective etching. The inclined surface comprises the angle between 10 and 70 degrees with respect to the horizontally extending surface of the inner surface200asor the outer surface204asof the first semiconductor layer201exposed through selective etching. If the angle of the side surface of the first insulating layer50is less than 10 degrees, the thickness of the first insulating layer50is substantially reduced. Therefore, it may be difficult to ensure the insulation properties. If the angle of the side surface of the first insulating layer50is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not be completely covered, thereby causing the film cracking. As shown inFIG.4andFIG.6, a contact electrode30is formed on the second semiconductor layer203of each of the light-emitting units20. Specifically, the contact electrode30is formed in one or the plurality of second openings502aand502bof the first insulating layer50. In other words, the contact electrode30is exposed by one or the plurality of second openings502aand502bof the first insulating layer50of the light-emitting units20. The contact electrode30comprises a transparent electrode. The material of the transparent electrode comprises a light-transmitting conductive oxide or a light-transmitting metal. The light-transmitting conductive oxide comprises indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (GITO), gallium indium oxide (GIO) or gallium zinc oxide (GZO). The light-transmitting conductive oxide comprises various dopants such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The light-transmitting metal comprises nickel (Ni) or gold (Au). The thickness of the contact electrode30is not limited, but may have a thickness between 0.1 nm and 100 nm. In an embodiment, the material of the contact electrode30comprises a light-transmitting conductive oxide. If the thickness of the contact electrode30is less than 0.1 nm, the thickness of the contact electrode30is too thin to ohmic contact with the second semiconductor layer203. If the thickness of the contact electrode30is larger than 100 nm, the contact electrode30having the thick thickness may partially absorb the light emitted from the active layer202, and the luminance of the light-emitting device1is reduced. Since the contact electrode30has a thickness in the range described above, the current can be uniformly spread in the horizontal direction to improve the electrical performance of the light-emitting device1. However, the above embodiments do not exclude other materials being capable of lateral current spreading. The contact electrode30is formed on substantially the entire surface of the second semiconductor layer203of each of the light-emitting units20, and forms a low-resistance contact with the second semiconductor layer203of each of the light-emitting units20, such as an ohmic contact. The electrical current uniformly spread through the second semiconductor layer203by the contact electrode30. In an embodiment, in a cross-sectional view of the light-emitting device1, the contact electrode30comprises an outermost side30swhich is separated from the second inclined surface S2of the light-emitting unit20by a horizontal distance less than 20 μm, preferably less than 10 μm, and more preferably less than 5 μm. A reflective layer40is formed on the contact electrode30of each of the light-emitting units20. The material of the reflective layer40comprises a metal such as aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt) or an alloy of the above materials. The reflective layer40reflects light and the reflected light emits outward in a direction toward the substrate10, wherein the light is formed in the active layer202of each of the light-emitting units20. In another embodiment, the step of forming the contact electrode30may be omitted. A reflective layer40is formed in one or the plurality of second openings502aand502bof the first insulating layer50of the light-emitting units20, and the reflective layer40forms an ohmic contact with the second semiconductor layer203. In an embodiment, in a cross-sectional view of the light-emitting device, as shown inFIG.4andFIG.6, the reflective layer40comprises an outermost side40sthat is separated from the second inclined surface S2of the light-emitting unit20by a horizontal distance less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm. In an embodiment, the reflective layer40can be a structure comprising one or more layers, such as a Distributed Bragg reflector. In one embodiment, a surface of the reflective layer40is an inclined surface with respect to the upper surface of the second semiconductor layer203, and the inclined surface comprises an angle between 10 and 60 degrees with respect to the surface of the second semiconductor layer203. The material of the reflective layer40can be silver (Ag). If the angle of the reflective layer40is less than 10 degrees, a gentle slope can lower the reflection efficiency of the light. In addition, an angle less than 10 degrees is also difficult to achieve a uniform thickness. If the angle of the reflective layer40is greater than 60 degrees, it may cause cracking of the film subsequently formed. However, the above embodiments do not exclude other materials having high reflectance. The adjustment of the angle of the reflective layer40can be achieved by changing the configuration of the substrate and the deposition direction of the metal atoms in the thermal deposition process. For example, the position of the substrate is adjusted such that the surface of the substrate is an inclined surface with respect to the deposition direction in the evaporation or sputtering. In an embodiment, a barrier layer (not shown) is formed on the reflective layer40of each of the light-emitting units20to cover the upper surface and the side surface of the reflective layer40to avoid surface oxidation of the reflective layer40which deteriorated the reflectivity of the reflective layer40. The material of the barrier layer comprises a metal material such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) or an alloy of the above materials. The barrier layer comprises one or more layers, such as titanium (Ti)/aluminum (Al), and/or nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW). In an embodiment of the present application, the barrier layer comprises a laminated structure comprising titanium (Ti)/aluminum (Al) and a laminated structure comprises nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW), wherein laminated structure comprising titanium (Ti)/aluminum (Al) is formed on one side away from the reflective layer40, and the laminated structure comprises nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW) is adjacent to one side adjacent to the reflective layer40. In an embodiment of the invention, the material of the reflective layer40and the barrier layer preferably comprises a metal material other than gold (Au) or copper (Cu). The laminated structure of the barrier layer comprises nickel titanium alloy (NiTO/titanium tungsten alloy (TiW)/platinum (PO/titanium (Ti)/aluminum (Al)/titanium (Ti)/aluminum (Al)/Chromium (Cr)/platinum (Pt), the barrier layer comprises an angle between 10 and 60 degrees with respect to the upper surface of the second semiconductor layer203. In an embodiment, if the angle of the barrier layer is less than 10 degrees, the gentle slope cannot completely cover the reflective layer40and is also difficult to achieve a uniform thickness. If the angle of the barrier layer is greater than 60 degrees, it may cause cracking of the film subsequently formed. In an embodiment, the thickness of the reflective layer40or the barrier layer is preferably between 100 nm and 1 μm. If the thickness of the reflective layer40or the barrier layer is less than 100 nm, the light emitted from the active layer203cannot be effectively reflected. If the thickness of the reflective layer40or the barrier layer is larger than 1 μm, the manufacturing loss is caused by excessive production time. In order to cover the upper surface and the side surface of the reflective layer40, the barrier layer comprises a bottom surface contacting the second semiconductor layer203and/or the contact electrode30. As shown inFIG.5, a second insulating layer60is formed on the substrate10and each of the light-emitting units20. One or a plurality of openings600of the second insulating layer60is formed on the first light-emitting unit20a, the second light-emitting unit20band the trench21by selectively etching to expose the substrate10, the first semiconductor layer201of the first light-emitting unit20aand the first semiconductor layer201of the second light-emitting unit20b. In an embodiment, the one or the plurality of openings600of the second insulating layer60formed adjacent to the trench21exposes the first semiconductor layer201of the first recess2041aand the first semiconductor layer201of the second recess2041b. As shown inFIG.5andFIG.6, one or the plurality of first openings601aof the second insulating layer60is formed on the first recess2041aof the first light-emitting unit20aadjacent to the trench21to expose the first semiconductor layer201. As shown inFIG.5, one or a plurality of second openings602aand602bof the second insulating layer60are respectively formed on the second semiconductor layer203of the first light-emitting unit20aand the second semiconductor layer203of the second light-emitting unit20bto expose the second semiconductor layer203, the contact electrode30and/or the reflective layer40. As shown inFIG.5, in the top view of the light-emitting device1, the positions of the plurality of first openings601aof the second insulating layer60and the plurality of second openings602bof the second insulating layer60are aligned with each other. As shown inFIG.5, one or a plurality of third openings603aof the second insulating layer60are respectively formed on the plurality of first outer recesses2042aof the first light-emitting unit20ato expose the first semiconductor layer201of the first light-emitting unit20a. Another one or an another plurality of third openings603bof the second insulating layer60are formed on the plurality of second outer recesses2042bof the second light-emitting unit20bto expose the first semiconductor layer201of the second light-emitting unit20b. As shown inFIG.5, the fourth openings604aand604bof the second insulating layer60are respectively formed on the first via200aof the first light-emitting unit20aand the second via200bof the second light-emitting unit20bto expose the first semiconductor layer201. The remaining area shown inFIG.5is shielded by the second insulating layer60. The number and/or the position of the first opening601aof the second insulating layer60corresponds to that of the first opening501aof the first insulating layer50. The number and/or the position of the third openings603a,603bof the second insulating layer60respectively corresponds to that of the third openings503a,503bof the first insulating layer50. The number and/or the position of the fourth openings604a,604bof the second insulating layer60respectively corresponds to that of the fourth openings504a,504bof the first insulating layer50. The positions of the second openings602a,602bof the second insulating layer60partially overlap with the positions of the second openings502a,502bof the first insulating layer50. The opening number of the second openings602a,602bof the second insulating layer60is different from the opening number of the second openings502a,502bof the first insulating layer50. In an embodiment, the plurality of second openings602a,602bof the second insulating layer60are respectively formed on the second openings502a,502bof the first insulating layer50. The first opening502a,502bof the first insulating layer50has a size larger than that of any of the plurality of second openings602a,602bof the second insulating layer60. In an embodiment, the second insulating layer60comprises an insulating material having light transparency. For example, the second insulating layer60comprises SiOx. In an embodiment, the second insulating layer60comprises two or more materials having different refractive indices alternately stacked to form a Distributed Bragg Reflector (DBR). In an embodiment, the second insulating layer60is laminated with sub-layers of SiO2/TiO2or SiO2/Nb2O5to selectively reflect light of a specific wavelength, thereby increasing the light extraction efficiency of the light-emitting device1. When the peak emission wavelength of the light-emitting device1is λ, the optical thickness of the second insulating layer60can an integral multiple of λ/4. The peak emission wavelength refers to the wavelength having a strongest intensity in the emission spectrum of the light-emitting device1. The thickness of the second insulating layer60may have a deviation of ±30% on the basis of an integral multiple of the optical thickness λ/4. The second insulating layer60comprises a non-conductive material comprising organic material, inorganic material or dielectric material. The organic material comprises Sub, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material comprises silicone or glass. The dielectric material comprises aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In an embodiment of the present application, the second insulating layer60comprises a thickness between 1000 angstrom (Å) and 20,000 angstrom (Å). In an embodiment of the present application, the material of the second insulating layer60comprises SiO2, TiO2or SiNx. If the thickness of the second insulating layer60is less than 1000 angstrom (Å), the thinner thickness may make the insulating property of the second insulating layer60weak. Specifically, the second insulating layer60is formed on the etched first inclined surface S1and the etched second inclined surface S2. The second insulating layer60conformally formed on the inclined surface comprises an inclined slope. If the second insulating layer60comprises a thickness less than 1000 Å, it may cause cracking of the film. In an embodiment of the present application, the material of the second insulating layer60comprises SiO2, TiO2or SiNx. If the thickness of the second insulating layer60is thicker than 20000 angstrom (Å), it is getting difficult to perform selective etching on the second insulating layer60. However, the above embodiments do not exclude other materials having a good covering extensibility or a high etch selectivity to avoid the problem caused by the thin thickness or the thick thickness of the second insulating layer60. The second insulating layer60comprises a surface which is an inclined surface with respect to a horizontally extending surface of the inner surface200asor the outer surface204asof the first semiconductor layer201exposed through selective etching. The inclined surface comprises an angle ranged between 10 degrees and 70 degrees with respect to a horizontally extending surface of the inner surface200asor the outer surface204asof the first semiconductor layer201exposed through selective etching. If the angle of the surface of the first insulating layer50is less than 10 degrees, the thickness of the second insulating layer60can be substantially reduced. Therefore, it may be difficult to ensure the insulation properties. If the angle of the surface of the second insulating layer60is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the second insulating layer60, thereby causing the film cracking thereof FIG.7illustrates a top view showing a top electrode, a bottom electrode and a connecting electrode formed on the semiconductor stack in accordance with an embodiment of the present application.FIG.7AandFIG.7Billustrate partial enlarged views ofFIG.7.FIG.8illustrates a cross-sectional view taken along line A-A′ ofFIG.7. One or a plurality of connecting electrodes70is formed between the first light-emitting unit20aand the second light-emitting unit20b. One or the plurality of connecting electrodes70comprises a first connecting part701on the first inner recess2041aof the first light-emitting unit20a, which covers the first opening601aof the second insulating layer60and electrically connected to the first semiconductor layer201of the first light-emitting unit20athrough the first opening601aof the second insulating layer60and the first opening501aof the first insulating layer50; a second connecting part702formed on the second semiconductor layer203of the second light-emitting unit20band electrically connected to the second semiconductor layer203of the second light-emitting unit20bthrough the second opening602bof the second insulating layer60and the second opening502bof the first insulating layer50, and a third connecting part703formed in the trench21and between the first connecting part701and the second connecting part702. In an embodiment of the present application, as shown inFIG.7A, the first connecting part701of the connecting electrodes70comprises a first connecting segment7011formed in the first opening601aof the second insulating layer60of the first light-emitting unit20a. The second connecting part702of the connecting electrodes70comprises a second connecting segment7022formed in the second opening602bof the second insulating layer60of the second light-emitting unit20b. In an embodiment, as shown inFIG.7A, the first connecting segment7011of the first connecting part701formed in the first opening601aof the second insulating layer60directly contacts the first semiconductor layer201of the first light-emitting unit20a. The second connecting segment7022of the second connecting part702formed in the second insulating layer second opening602bcontacts the barrier layer, the reflective layer40or the contact electrode30. In an embodiment of the present application, as shown inFIG.7A, in the top view of the light-emitting device1, the third connecting part703comprises a first segment7031formed on the third surface S3of the first light-emitting unit20a, and a second segment7032formed on the third surface S3of the second light-emitting unit20b. The first connecting segment7031and/or the second segment7032comprises a width larger than 15 μm, preferably larger than 30 μm, more preferably larger than 50 μm. In an embodiment, in order to uniformly inject the electrical current from the first light-emitting unit20ainto the second light-emitting unit20b, a total area of the second light-emitting unit20bprovided for the injected current is increased, and the electrical current density in the cross-sectional area of the second connecting part702is reduced. As shown inFIG.7andFIG.7A, in the top view of the light-emitting device1, the second opening602bof the second insulating layer60of the second light-emitting unit20bcomprises a first opening area larger than a second opening area of the first opening601aof the second insulating layer60of the first light-emitting unit20a. The first connecting segment7011of the first connecting part701comprises a first width W1smaller than a second width W2of the second connecting segment7022of the second connecting part702. The second segment7032of the third connection part703comprises a third width W3smaller than a width of the first segment7031of the third connection part703, and a width between the first segment7031of the third connection part703and the second segment7032of the third connection part703is gradually changed. In another embodiment (not shown), in order to uniformly inject the electrical current from the first light-emitting unit20ainto the second light-emitting unit20b, a total area of the second light-emitting unit20bprovided for the injected current is increased, and the electrical current density in the cross-sectional area of the second connecting part702is reduced. The first connecting segment7011of the first connecting part701comprises a first width W1smaller than a second width W2of the second connecting segment7022of the second connecting part702. The second segment7032of the third connection part703comprises a third width W3same as a width of the first segment7031of the third connection part703. In another embodiment (not shown), in order to uniformly spread the electrical current on the first connecting part701and the first surrounding part204a, the first width W1of the first connecting segment7011of the first connecting part701is larger than the second width W2of the second connecting segment7022of the second connecting part702, and the third width W3of the third connection part703is larger than the second width W2of the second connecting segment7022of the second connecting part702. In another embodiment (not shown), in order to avoid uneven current density flowing through the connection electrode70, the first width W1of the first connecting segment7011of the first connecting part701is same as the second width W2of the second connecting segment7022of the second connecting part702. The third width W3of the third connection part703is larger than the first width W1of the first connecting segment7011and/or the second width W2of the second connecting segment7022. In an embodiment, one or a plurality of first top electrodes71ais respectively formed in the one or the plurality of second openings602aof the second insulating layer60of the first light-emitting unit20a, and electrically connected to the second semiconductor layer203of the first light-emitting unit20a. A first bottom electrode72acovers the first inner recess2041aand the plurality of first outer recesses2042aof the first light-emitting unit20a. The first bottom electrode72adirectly contacts the first semiconductor layer201of the first inner recess2041aof the first light-emitting unit20athrough the one or the plurality of openings600of the second insulating layer60and the one or the plurality of first openings601aof the second insulating layer60. The first bottom electrode72adirectly contacts the first semiconductor layer201on the plurality of first outer recesses2042athrough the one or the plurality of third openings603aof the second insulating layer60, and electrically connected to the first semiconductor layer201of the first light-emitting unit20a. The first bottom electrode72adirectly contacts the first semiconductor layer201on the first via200athrough the fourth opening604aof the second insulating layer60, and electrically connected to the first semiconductor layer201of the first light-emitting unit20a. In the top view of the light-emitting device1, the plurality of openings600of the second insulating layer60and the plurality of connecting electrodes70are alternately arranged. The first bottom electrode72aextends along the second inclined surface S2of the first light-emitting unit20ato cover the first semiconductor mesa205ato reflect the light emitted from the active layer202of the first light-emitting unit20a. The second insulating layer openings600, the first openings601aof the second insulating layer60and the third openings603aof the second insulating layer60expose the first semiconductor layer201of the first surrounding part204aof the first light-emitting unit20a. In the top view of the light-emitting device1, the opening600of the second insulating layer60, the first opening601aof the second insulating layer60and the third opening603aof the second insulating layer60comprise different sizes. The size comprises an area, a width, or a depth. The second insulating layer60is formed between the first top electrodes71aand the first bottom electrode72ato avoid a short circuit caused by the contacting of the first top electrodes71aand the first bottom electrode72a. A portion of the second insulating layer60is located below the first bottom electrode72awhich extends over the first semiconductor mesa205ato prevent the first bottom electrode72afrom contacting the barrier layer, the reflective layer40, and/or the contact electrode30. The first surrounding part204aof the first light-emitting unit20acomprises the first inner recess2041aand the plurality of first outer recesses2042ato form a rectangle shape, and is located around the first light-emitting unit20a, wherein the first inner recess2041ais adjacent to one side of the trench21with respect to the plurality of first outer recesses2042a. In the top view of the light-emitting device1, as shown inFIG.7, the plurality of openings600of the second insulating layer60and the plurality of first openings601aof the second insulating layer60are alternately arranged to expose the first semiconductor layer201of the first light-emitting unit20a. In a direction parallel to a side of the first inner recess2041a, the opening600of the second insulating layer60comprises a width larger than or less than a width of the first opening601aof the second insulating layer60to uniformly spread electrical current adjacent to the connecting electrode70. As shown inFIG.7, the first bottom electrode72ais formed in the openings600of the second insulating layer60, extends over the second insulating layer60, and connects to the first connecting segment7011of the first connecting part701formed in the first opening601aof the second insulating layer60. In the top view of the light-emitting device1, as shown inFIG.7, the one or the plurality of first top electrodes71aformed on the first light-emitting unit20ais respectively surrounded by the first bottom electrode72a. In an embodiment, in the top view of the light-emitting device1, as shown inFIG.7, the one or the plurality of first top electrodes71aformed on the first light-emitting unit20acomprises a first top surface area larger than a first bottom surface area of the first bottom electrode72a. In another embodiment (not shown), in the top view of the light-emitting device1, the one or the plurality of first top electrodes71aformed on the first light-emitting unit20acomprises a first top surface area smaller than a first bottom surface area of the first bottom electrode72a. In another embodiment (not shown), the one or the plurality of first top electrodes71aformed on the first light-emitting unit20acomprises a first top surface area same as a first bottom surface area of the first bottom electrode72a. A second bottom electrode72bcovers the second inner recess2041bof the second light-emitting unit20band the plurality of second outer recesses2042b. The second bottom electrode72bdirectly contacts with the first semiconductor layer201on the second inner recess2041bthrough the one or the plurality of openings600of the second insulating layer60. The second bottom electrode72bdirectly contacts the first semiconductor layer201of the plurality of second outer recesses2042bthrough the one or the plurality of third openings603bof the second insulating layer, and is electrically connected to the first semiconductor layer201of the second light-emitting unit20b. The second bottom electrode72bdirectly contacts the first semiconductor layer201located in the second via200bthrough the fourth opening604bof the second insulating layer60, and is electrically connected to the first semiconductor layer201of the second light-emitting unit20b. In the top view of the light-emitting device1, the plurality of openings600of the second insulating layer60and the plurality of connecting electrodes70are alternately arranged. The second bottom electrode72bextends along the second inclined surface S2of the second light-emitting unit20bto cover the second semiconductor mesa205bto reflect the light emitted from the active layer202. As shown inFIG.8, the second insulating layer60is located under the second bottom electrode72bto prevent the second bottom electrode72bfrom contacting the barrier layer, the reflective layer40, and/or the contact electrode30. In an embodiment, as shown inFIG.7, in the top view of the light-emitting device1, the second bottom electrode72blocated on the second light-emitting unit20bcomprises a second bottom surface area larger than a first bottom surface area of the first bottom electrode72aon the first light-emitting unit20a. In another embodiment, as shown inFIG.7, in the top view of the light-emitting device1, the second bottom electrode72blocated on the second light-emitting unit20bcomprises a second bottom surface area larger than a first top surface area each of the first top electrodes71aon the first light-emitting unit20a. In another embodiment, as shown inFIG.7, in the top view of the light-emitting device1, the second bottom electrode72blocated on the second light-emitting unit20bcomprises a second bottom surface area larger than a sum of the first top surface areas of the plurality of first top electrode71aon the first light-emitting unit20a. As shown inFIG.7, the trench21is located between the first inner recess2041aof the first light-emitting unit20aand the second inner recess2041bof the second light-emitting unit20b. The opening500of the first insulating layer50and the opening600of the second insulating layer60expose the surface21sof the substrate10, the first semiconductor layer201on the first inner recess2041a, and the first semiconductor layer201on the second inner recess2041b. In other words, the opening500of the first insulating layer50and the opening600of the second insulating layer60formed adjacent to the trench21expose the first semiconductor layer201of the first inner recess2041aand the second inner recess2041bat same positions. The first bottom electrode72acomprises a portion formed in the opening500of the first insulating layer50and the opening600of the second insulating layer60and directly contacting the first semiconductor layer201on the first inner recess2041a. The second bottom electrode72bcomprises a portion formed in the opening500of the first insulating layer50and the opening600of the second insulating layer60and directly contacting the first semiconductor layer201on the second inner recess2041b. The first bottom electrode72aand the second bottom electrode72bare separated from each other by the trench21. As shown inFIG.7B, the second bottom electrode72bcomprises one or a plurality of second bottom electrode recesses721baccommodating one or a plurality of second connection parts702; and one or a plurality of second bottom electrode protrusions722bformed between two adjacent of the second connecting parts702. The second bottom electrode protrusion722bcomprises a width W4larger or smaller than the width of the second connection part702. In order to uniformly inject the electrical current from the second bottom electrode72binto the first semiconductor layer201of the second light-emitting unit20b, the second bottom electrode protrusions722bfurther comprises one or a plurality of second bottom electrode extending portions724bin the second inner recess2041b. The second bottom electrode extending portion724bextends into the opening600of the second insulating layer60to directly contact the first semiconductor layer201of the second inner recess2041b. In order to increase the area for current injection, the second bottom electrode extending portion724bcomprises a width W5larger than a width W4of the second bottom electrode protrusion722b. In an embodiment, as shown inFIG.7, in the top view of the light-emitting device1, the second bottom electrode protrusion722bcomprises a width smaller than that of the second connection part702. In another embodiment (not shown), in the top view of the light-emitting device1, the second bottom electrode protrusion722bcomprises a width larger than that of the second connection part702. As shown inFIG.7, in the top view of the light-emitting device1, the plurality of second bottom electrode protrusions722band the plurality of second connecting part702are alternately arranged to uniformly inject the electrical current into the first semiconductor layer201and the second semiconductor layer203of the second light-emitting unit20b. The plurality of second bottom electrode protrusions722bcomprises a number different from a number of the plurality of second connecting part702. For example, the number of the second bottom electrode protrusions722bis greater than or less than the number of the plurality of second connecting parts702. The first bottom electrode72alocated on the first light-emitting unit20adirectly contacts the outer surface204asof the first semiconductor layer201of the first light-emitting unit20a. The second bottom electrode72blocated on the second light-emitting unit20bdirectly contacts the outer surface204bsof the first semiconductor layer201of the second light-emitting unit20b. As shown inFIG.8, when the first bottom electrode72aor the second bottom electrode72bcompletely covers the outer surface204asor the outer surface204bsof the first semiconductor layer201, the first bottom electrode72aor the second bottom electrode72brespectively comprises a first bottom electrode outer sidewall72asand a second bottom electrode outer sidewall72bsdirectly connecting the third surface S3of the first semiconductor layer201. In an embodiment, when the first bottom electrode72aor the second bottom electrode72bpartially covers the outer surface204asor the outer surface204bsof the first semiconductor layer201, the first bottom electrode outer sidewall72asof the first bottom electrode72aor the second bottom electrode outer side-wall72bsof the second bottom electrode72bis spaced apart from the third surface S3of the first semiconductor layer201by a distance to partially expose the outer surface204asor the outer surface204bsof the first semiconductor layer201(not shown). In an embodiment, the first top electrode71alocated at the first light-emitting unit20acomprises an inclined side surface to reduce the risk of the films peeling off from the reflective layer40or the barrier layer, and to increase the coverage of the films subsequently formed. The first bottom electrode72alocated on the first light-emitting unit20aand the second bottom electrode72blocated on the second light-emitting unit20brespectively comprises an inclined side surface to reduce the risk of the films peeling from the first semiconductor layer201and increase the coverage of the films subsequently formed. The inclined side surface of the first top electrode71acomprises an angle between 30 degrees and 75 degrees with respect to the surface of the reflective layer40or the barrier layer. The inclined side surface of the first bottom electrode72aand/or the second bottom electrode72bcomprises an angle between 30 degrees and 75 degrees with respect to the surface of the first semiconductor layer201. The first top electrode71a, the first bottom electrode72a, and/or the second bottom electrode72bcomprises a metal material comprising chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first top electrode71a, the first bottom electrode72a, and/or the second bottom electrode72bcomprises single layer or multilayers. For example, the first top electrode71a, the first bottom electrode72a, and/or the second bottom electrode72bcomprises Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack. The first top electrode71a, the first bottom electrode72a, and/or the second bottom electrode72bcomprises a thickness preferably between 0.5 μm and 3.5 μm. In an embodiment, the first top electrode71acomprises a top surface lower than a top surface of the first bottom electrode72a. In other words, a step height is formed between the top surface of the first top electrode71aand the top surface of the first bottom electrode72a, wherein the step height comprises a height between 2000 angstrom (Å) and 20,000 angstrom (Å). In an embodiment, the step height is formed between the top surface of the first bottom electrode72aand the top surface of the second bottom electrode72b, wherein the step height comprises a height less than 2000 angstrom (Å), preferably less than 1000 angstrom (Å), more preferably less than 500 angstrom (Å). In an embodiment, the top surface of the first bottom electrode72ais substantially flush to the top surface of the second bottom electrode72b. FIG.9illustrates a top view showing a formation of a third insulating layer in accordance with an embodiment of the present application.FIG.10illustrates a cross-sectional view taken along line A-A′ ofFIG.9. A third insulating layer80is formed on the substrate10and each of the light-emitting units20. One or a plurality of first openings801of the third insulating layer80and one or a plurality of second openings802of the third insulating layers80are formed on each of the light-emitting units20by selective etching. The one or the plurality of first openings801of the third insulating layer80exposes the one or the plurality of first top electrodes71aon the first light-emitting units20a. The one or the plurality of second openings802of the third insulating layer80exposes the second bottom electrodes72bon the second light-emitting unit20b. The remaining area is covered by the third insulating layer80. In an embodiment, as shown inFIG.9, in the top view of the light-emitting device1, the one or the plurality of first openings801of the third insulating layer80formed on the first light-emitting unit20acomprises a width smaller than a width of the one or the plurality of second openings802of the third insulating layer80formed on the second light-emitting unit20b, wherein the plurality of first openings801of the third insulating layer80comprises same width or different widths, and/or the plurality of second openings802of the third insulating layers80comprises same or different widths. In another embodiment (not shown), the one or the plurality of first openings801of the third insulating layer80formed on the first light-emitting unit20acomprises a width larger than a width of the one or the plurality of second openings802of the third insulating layer80formed on the second light-emitting unit20b, wherein the plurality of first openings801of the third insulating layer80comprises same width or different widths, and/or the plurality of second openings802of the third insulating layers80comprises same or different widths. In an embodiment, the light-emitting device1comprises the dicing street10dlocated at the outermost side of the light-emitting device1. The third insulating layer80covers the exposed upper surface10sof the substrate10. The third insulating layer80comprises a third insulating sidewall80sthat is directly connected to the outer sidewall S of the substrate10or separated from the outer sidewall S of the substrate10by a distance to expose the portion of the upper surface10sof the substrate10. In another embodiment, the third surface S3of the first semiconductor layer201is directly connected to the outer sidewall S of the substrate10. The third insulating layer80covers the outer surface204asor the outer surface204bsof the first semiconductor layer201, wherein the third insulating sidewall80sof the third insulating layer80directly contacts the third surface S3of the first semiconductor layer201or is separated from the third surface S3of the first semiconductor layer201by a distance to partially expose the outer surface204asor the outer surface204bsof the first semiconductor layer201. In an embodiment, the third insulating layer80comprises an insulating material having light transparency. For example, the material of the third insulating layer80comprises SiOx. In an embodiment, the third insulating layer80may comprise two or more materials of different refractive indices alternately stacked to form a Distributed Bragg Reflector (DBR). In an embodiment, the third insulating layer80is laminated with sub-layers of SiO2/TiO2or SiO2/Nb2O5to selectively reflect light of a specific wavelength, thereby increasing the light extraction efficiency of the light-emitting device. When the peak emission wavelength of the light-emitting device1is λ, the optical thickness of the third insulating layer80can an integral multiple of λ/4. The peak emission wavelength refers to the wavelength having a strongest intensity in the emission spectrum of the light-emitting device1. The thickness of the third insulating layer80may have a deviation of ±30% on the basis of an integral multiple of the optical thickness λ/4. In an embodiment of the present application, the third insulating layer80comprises a non-conductive material comprising organic material, inorganic material or dielectric material. The organic material comprises Sub, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material comprises silicone or glass. The dielectric material comprises aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). In an embodiment of the present application, the third insulating layer80comprises a thickness ranged between 2000 angstrom (Å) and 60,000 angstrom (Å). In an embodiment of the present application, the material of the third insulating layer80comprises SiO2, TiO2or SiNx. If the thickness of the third insulating layer80is less than 2000 angstrom (Å), the thinner thickness may weaken the insulating property of the third insulating layer80. Specifically, the third insulating layer80is formed on the etched first inclined surface S1and the etched second inclined surface S2, and the conformally formed third insulating layer80comprises an inclined surface. If the third insulating layer80comprises a thickness less than 2000 angstrom (Å), the film may be easily cracked. In an embodiment of the present application, the material of the third insulating layer80comprises SiO2, TiO2or SiNx. If the thickness of the third insulating layer80is thicker than 60000 angstrom (Å), it is getting difficult to perform selective etching on the third insulating layer80. However, the above embodiments do not exclude other materials having a good covering extensibility material or a high etch selectivity to avoid the problem caused by the thin thickness or the thick thickness of the third insulating layer80. The third insulating layer80comprises a third insulating side surface80swhich is an inclined surface with respect to a horizontally extending surface of the inner surface200as,200bs, the outer surface204as,204bsof the first semiconductor layer201, or the exposed upper surface10sof the substrate10exposed through selective etching. The inclined surface comprises an angle between 10 degrees and 70 degrees with respect to a horizontally extending surface of the inner surface200as,200bs, the outer surface204as,204bsof the first semiconductor layer201, or the exposed upper surface10sof the substrate10exposed through selective etching. If the angle of the third insulating sidewall80sof the third insulating layer80is less than 10 degrees, the thickness of the third insulating layer80can be substantially reduced. Therefore, it may be difficult to ensure the insulation properties. If the angle of the third insulating sidewall80sof the third insulating layer80is greater than 70 degrees, the insulating layer and the metal layer subsequently formed may not completely cover the third insulating layer80, thereby causing the film cracking. As shown inFIG.9andFIG.10, the one or the plurality of third insulating layer first openings801on the first light-emitting unit20ais formed corresponding to the one or the plurality of second insulating layer second openings602a, and overlaps the position of the first insulating layer second opening502a. As shown inFIG.9andFIG.10, the one or the plurality of third insulating layer second openings802on the second light-emitting unit20boverlaps with the second opening502bof the first insulating layer50formed below, and the one or the plurality of second openings802of the third insulating layer80do not overlap with the second opening602bof the second insulating layer60. FIG.11illustrates a top view of a first electrode pad and a second electrode pad in accordance with an embodiment of the present application.FIG.12illustrates a cross-sectional view taken along line A-A′ ofFIG.11.FIG.13illustrates a cross-sectional view taken along line B-B′ ofFIG.11.FIG.14illustrates a cross-sectional view taken along line C-C′ ofFIG.11. The light-emitting device1comprises one or a plurality of first electrode pads901covering the one or the plurality of third insulating layer first openings801and contacting the one or the plurality of first top electrodes71a. The first electrode pad901is electrically connected to the second semiconductor layer203on the first light-emitting unit20aby the reflective layer40and/or the contact electrode30. The light-emitting device1comprises one or a plurality of second electrode pads902covering the one or the plurality of second openings802of the third insulating layer80and contacting the second bottom electrode72b. The second electrode pad902is electrically connected to the first semiconductor layer201on the second light-emitting unit20bby the second bottom electrode72bformed on the second via200band the second surrounding part204b. The electrical current injected through the first electrode pad901and the second electrode pad902electrically connects the first light-emitting unit20aand the second light-emitting unit20bin series by the first connecting part701and the second connecting part702of the connecting electrode70. The upper surface of the first electrode pad901or the second electrode pad902may be planar or non-planar. When the upper surface of the first electrode pad901or the second electrode pad902is non-planar, the upper surface of the first electrode pad901or the second electrode pad902comprises a surface topography corresponding to that of the first opening801of the third insulating layer80and that of the first opening802of the third insulating layer80, such as an elongated profile, a circular or a stepped profile. As shown inFIG.11, the upper surface of the first electrode pad901or the second electrode pad902comprises a recess and a protrusion surrounding the recess. A position of the recess corresponds to a position of the first opening801of the third insulating layer80or the second opening802of the third insulating layer80, and the recess is formed in the first opening801of the third insulating layer80and the second opening802of the third insulating layer80. The position of the protrusion is formed at a position other than that of the first opening801of the third insulating layer80and the second opening802of the third insulating layer80, and the protrusion is formed on the upper surface of the third insulating layer80. A stepped surface is formed between the protrusion and the recess, wherein the stepped surface comprises a step height between 200 angstrom (Å) and 60,000 angstrom (Å), preferably between 1000 angstrom (Å) and 30,000 angstrom (Å), more preferably between 2000 angstrom (Å) and 20,000 angstrom (Å). The recess and the protrusion comprise a circular shape or a rectangular shape as shown inFIG.1. In another embodiment of the present application (not shown), the first electrode pad901and the second electrode pad902comprises a thin pad structure comprising a thickness smaller than a thickness of the third insulating structure80. The first electrode pad901and the second electrode pad902comprise a metal material comprising chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode pad901and the second electrode pad902comprise single layer or multilayers. For example, the first electrode pad901and the second electrode pad902comprise Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack. In an embodiment of the present application, the first electrode pad901comprises a size that is the same as or different from that of the second electrode pad902, and the size comprises a width or an area. For example, the upper surface area of the first electrode pad901or the second electrode pad902may be 0.8 times or more and less than 1 time the sum of the upper surface areas of the first electrode pad901and the second electrode pad902. In an embodiment of the present application (not shown), the first electrode pad901or the second electrode pad902respectively comprises an inclined sidewall, and cross-sectional area of the first electrode pad901or the second electrode pad902varies along the thickness direction. For example, a side of the first electrode pad901or the second electrode pad902away from the semiconductor stack comprises a cross-sectional area smaller than that of a side of the first electrode pad901or the second electrode pad902near the semiconductor stack. In an embodiment of the present application (not shown), when the light-emitting device1is flipped to be mounted onto the package substrate, in order to increase the contact area between the first electrode pad901, the second electrode pad902and the package substrate, a side of the first electrode pad901or the second electrode pad902away from the semiconductor stack comprises a cross-sectional area larger than that of a side of the first electrode pad901or the second electrode pad902near the semiconductor stack. The first electrode pad901or the second electrode pad902comprises a thickness between 1 and 100 μm, preferably between 1.5 and 6 μm. The first electrode pad901and the second electrode pad902comprise a space formed there between. The space comprises a shortest distance larger than 10 μm and a longest distance less than 250 μm. In the above range, the upper surface areas of the first electrode pad901and the second electrode pad902is increased by reducing the space between the first electrode pad901and the second electrode pad902, so that the heat dissipation efficiency of the light-emitting device1can be improved, and a short circuit between the first electrode pad901and the second electrode pad902is avoided. As mentioned above, the light-emitting device1comprises the first light-emitting unit20aand the second light-emitting unit20b, wherein the first light-emitting unit20aand the second light-emitting unit20bare separated by the trench21. The first surrounding part204acomprises the first inner recess2041aand the plurality of first outer recesses2042aformed on the first light-emitting unit20a. The second surrounding part204bcomprises the second inner recess2041band the plurality of second outer recesses2042b. The connecting electrode70is formed between the first light-emitting unit20aand the second light-emitting unit20b. The connecting electrodes70comprises the first connecting part701on the first inner recess2041aof the first light-emitting unit20a, the second connecting part702formed on the second semiconductor layer203of the second light-emitting unit20b, and the third connecting part703formed in the trench21and between the first connecting part701and the second connecting part702. The first connecting part701comprises the first width W1smaller than second width W2of the second connecting part702. The first top electrodes71ais formed on the second semiconductor layer203on the first light-emitting unit20a. The first bottom electrode72acovers the first inner recess2041aand the plurality of first outer recesses2042aof the first light-emitting unit20a. The second bottom electrode72bcovers the second inner recess2041bof the second light-emitting unit20band the plurality of second outer recesses2042b. The first electrode pad901contacts the first top electrodes71aand is electrically connected to the second semiconductor layer203on the first light-emitting unit20a. The second electrode pad902contacts the second bottom electrode72band is electrically connected to the first semiconductor layer201on the second light-emitting unit20b. FIG.15is a schematic view of a light-emitting apparatus2in accordance with an embodiment of the present application. The light-emitting device1in the foregoing embodiment is mounted on the first spacer511and the second spacer512of the package substrate51in the form of flip chip. The first spacer511and the second spacer512are electrically insulated from each other by an insulating portion53comprising an insulating material. The main light-extraction surface of the flip chip is one side of the growth substrate opposite to the electrode-forming surface where the electrodes are formed on. A reflective structure54can be provided around the light-emitting device1to increase the light extraction efficiency of the light-emitting apparatus2. FIG.16illustrates a structure diagram of a light-emitting apparatus3in accordance with an embodiment of the present application. A light bulb comprises an envelope602, a lens604, a light-emitting module610, a base612, a heat sink614, a connector616and an electrical connecting device618. The light-emitting module610comprises a submount606and a plurality of light-emitting devices608on the submount606, wherein the plurality of light-emitting devices608can be the light-emitting device1or the light-emitting apparatus2described in above embodiments. The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims. | 85,208 |
11942510 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number. FIG.1illustrates a top view of a light-emitting device1in accordance with an embodiment of the present application.FIG.2illustrates a cross-sectional view taken along line A-A′ ofFIG.1.FIG.3illustrates a cross-sectional view taken along line B-B′ ofFIG.1.FIG.4illustrates a cross-sectional view taken along line C-C1-C2-C′ ofFIG.1.FIG.5illustrates a cross-sectional view taken along line D-D1-D2-D′ ofFIG.1. As shown inFIG.1,FIG.2,FIG.3,FIG.4andFIG.5, the light-emitting device1comprises a substrate10comprising a top surface100; a plurality of light-emitting units C1˜C6formed on the top surface100of the substrate10comprising a first light-emitting unit C1, a second light-emitting unit C6, and one or a plurality of third light-emitting units C2, C3, C4and C5wherein the plurality of light-emitting units C1˜C6each comprises a first semiconductor layer201, an active layer202and a second semiconductor layer203; an insulating layer60comprising a first insulating layer opening601and a second insulating layer opening602formed on each of light-emitting units C1˜C6; a first extension electrode7100covering the first light-emitting unit C1wherein the first extension electrode7100covers the first insulating layer opening601on the first light-emitting unit C1without covering the second insulating layer opening602on the first light-emitting unit C1; a second extension electrode7200covering the second light-emitting unit C6wherein the second extension electrode7200covers the second insulating layer opening602on the second light-emitting unit C6without covering the first insulating layer opening601on the second light-emitting unit C6; a first electrode pad91covering a first part of the plurality of the light-emitting units C1˜C6; and a second electrode pad92covering a second part of the plurality of light-emitting units C1˜C6. The substrate10comprises a top surface100. The substrate10can be a growth substrate for the epitaxial growth of a semiconductor stack20, comprising gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al2O3) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). In another embodiment, the substrate10can be a support substrate for supporting the semiconductor stack20which was originally epitaxially grown on the growth substrate and then being transferred to the support substrate. The growth substrate originally used for epitaxial growth is optionally removed according to the requirements of the application. The support substrate comprises a conductive material such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or an alloy of the above materials, or a thermally conductive material such as diamond, graphite or aluminum nitride. Although the feature is omitted in the figures, the side of the substrate10that is in contact with the semiconductor stack20comprises a rough surface, and the rough surface comprises a surface having an irregular morphology or a surface having a regular morphology, for example, the surface having a plurality of hemispheres, the surface having a plurality of cones, or the surface having a plurality of pyramids protruding or recessed from the top surface100. In an embodiment of the present application, the semiconductor stack20with optical characteristics, such as a light-emitting stack, is formed on the substrate10by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating, wherein physical vapor deposition (PVD) comprises sputtering or evaporation. In an embodiment of the present application, the semiconductor stack20comprises the first semiconductor layer201, the active layer202and the second semiconductor layer203. The semiconductor stack20further comprises a buffer layer (not shown) formed between the first semiconductor layer201and the substrate10which can release the stress caused by lattice mismatch between the materials of the substrate10and the first semiconductor layer201so the lattice dislocation and the lattice defect are reduced and the epitaxial quality of the semiconductor stack is improved. The buffer layer comprises a single layer or a plurality of layers. In an embodiment, an aluminum nitride (AlN) layer formed by using PVD method can be the buffer layer formed between the semiconductor stack20and the substrate10to improve the epitaxial quality of the semiconductor stack20. In an embodiment, the method for forming aluminum nitride (AlN) is PVD, and the target is made of aluminum nitride. In another embodiment, a target made of aluminum reacts with a nitrogen source to form the aluminum nitride. The wavelength of the light emitted from the light-emitting device1is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack20. The material of the semiconductor stack20comprises a group III-V semiconductor material, such as AlxInyGa(1−x−y)N or AlxInyGa(1−x−y)P, wherein 0≤x, y≤1; (x+y)≤1. When the material of the semiconductor stack20comprises AlInGaP series material, the red light having a wavelength between 610 nm and 650 nm or the green light having a wavelength between 530 nm and 570 nm can be emitted. When the material of the semiconductor stack20comprises InGaN series material, the blue light having a wavelength between 400 nm and 490 nm can be emitted. When the material of the semiconductor stack20comprises AlGaN or AlInGaN series material, the UV light having a wavelength between 400 nm and 250 nm can be emitted. The first semiconductor layer201and the second semiconductor layer203can be cladding layers or confinement layers having different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer201is an n-type semiconductor and the second semiconductor layer203is a p-type semiconductor. The active layer202is formed between the first semiconductor layer201and the second semiconductor layer203. The electrons and holes combine in the active layer202under a current driving to convert the electric energy into the light energy and then the light is emitted from the active layer202. The active layer202can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer123can be i-type, p-type, or n-type semiconductor. The first semiconductor layer201, the active layer202, or the second semiconductor layer203can be a single layer or a structure comprising a plurality of layers. As shown inFIG.2,FIG.3,FIG.4andFIG.5, the semiconductor stack20is selectively etched to form a recess200and a semiconductor mesa204. Specifically, by removing a part of the second semiconductor layer203and the active layer202, the semiconductor mesa204comprises the first semiconductor layer201, the second semiconductor layer203, and the active layer202. The recess200exposes the first semiconductor layer201by removing a part of the second semiconductor layer203and the active layer202. The light-emitting device1comprises a trench T12, T23, T34, T45and T56respectively formed between two adjacent light-emitting units C1˜C6, and the trenches T12, T23, T34, T45and T56expose the top surface100of the substrate10. As shown inFIG.1, the light-emitting device1comprises a first trench T12formed between the first light-emitting unit C1and the third light-emitting unit C2; a second trench T23formed between two adjacent third light-emitting units C2and C3; a third trench T34formed between two adjacent third light-emitting units C3and C4; a fourth trench T45formed between two adjacent third light-emitting units C4and C5; and a fifth trench T56formed between the third light-emitting unit C5and the second light-emitting unit C6, wherein each of the trenches T12, T23, T34, T45and T56exposes the top surface100of the substrate10. The light-emitting device1comprises one or a plurality of current blocking layers30formed on the second semiconductor layer203. The current blocking layer30comprises a non-conductive material, comprising aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). The current blocking layer30comprises a distributed Bragg reflector (DBR), wherein the distributed Bragg reflector (DBR) comprises insulating materials with different refractive indexes stacked on each other. The current blocking layer30comprises a light transmittance of more than 80% or a light reflectance of more than 80% for the light emitted from the active layer202. The light-emitting device1comprises a conductive layer40formed on the second semiconductor layer203and/or the current blocking layer30, and the conductive layer40covers a sidewall of the current blocking layer30. The conductive layer40covering the current blocking layer30comprises a surface profile corresponding to that of the current blocking layer30. The material of the conductive layer40comprises a material that is transparent to the light emitted from the active layer202, such as a metal material with a thickness thinner than 100 Å or a transparent conductive oxide. The transparent conductive oxide comprises indium tin oxide (ITO) or indium zinc oxide (IZO). The light-emitting device1comprises one or a plurality of first contact electrodes51respectively formed on the one or the plurality of recesses200of the plurality of light-emitting units C1˜C6to contact the first semiconductor layer201, and one or a plurality of second contact electrodes52respectively formed on the second semiconductor layer203of the plurality of light-emitting units C1˜C6. The first contact electrode51directly contacts the first semiconductor layer201of each of light-emitting units C1˜C6, and the second contact electrode52directly contacts the conductive layer40, the current blocking layer30or the second semiconductor layer203of each of light-emitting units C1˜C6. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the position of the second contact electrode52is substantially the same as the position of the current blocking layer30. The shape of the second contact electrode52and the shape of the current blocking layer30may be the same or different. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first contact electrode51is formed between the plurality of second contact electrodes52. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the plurality of second contact electrodes52comprises a second amount greater than a first amount of the plurality of first contact electrodes51. The light-emitting device1comprises an insulating layer60covering the semiconductor stack20, wherein the insulating layer60comprises one or a plurality of first insulating layer openings601exposing the one or the plurality of first contact electrodes51, and one or a plurality of second insulating layer openings602exposing the one or the plurality of second contact electrodes52. As shown inFIG.1andFIG.3, the light-emitting device1comprises a first extension electrode7100covering the first light-emitting unit C1and the plurality of third light-emitting units C2and C3, wherein the first extension electrode7100covers the first insulating layer opening601of the first light-emitting unit C1without covering the second insulating layer opening602of the first light-emitting unit C1, and the first insulating layer openings601and the second insulating layer openings602of the plurality of third light-emitting units C2and C3. The first extension electrode7100contacts the first contact electrode51of the first light-emitting unit C1through the first insulating layer opening601of the first light-emitting unit C1and is electrically connected to the first semiconductor layer201of the first light-emitting unit C1. As shown inFIG.1andFIG.2, the light-emitting device1further comprises a second extension electrode7200covering the second light-emitting unit C6and the plurality of third light-emitting units C4and C5, wherein the second extension electrode7200covers the second insulating layer opening602of the second light-emitting unit C6without covering the first insulating layer opening601of the second light-emitting unit C6and the first insulating layer openings601and the second insulating layer openings602of the plurality of third light-emitting units C4and C5. The second extension electrode7200contacts the second contact electrode52of the second light-emitting unit C6through the second insulating layer opening602of the second light-emitting unit C6and is electrically connected to the second semiconductor layer203of the second light-emitting unit C6. The light-emitting device1comprises one or a plurality of connecting electrodes71˜75formed between two adjacent light-emitting units C1˜C6. As shown inFIG.1, the connecting electrodes71˜75comprises a first connecting electrode71, a second connecting electrode72, a third connecting electrode73, a fourth connecting electrode74, and a fifth connecting electrode75. The first connecting electrode71is formed between the first light-emitting unit C1and the third light-emitting unit C2, the second connecting electrode72is formed between two adjacent third light-emitting units C2and C3, and the third connecting electrode73is formed between two adjacent third light-emitting units C3and C4, the fourth connecting electrode74is formed between two adjacent third light-emitting units C4and C5, and the fifth connecting electrode75is formed between the third light-emitting unit C5and the second light-emitting unit C6. The first connecting electrode71, the second connecting electrode72, the third connecting electrode73, the fourth connecting electrode74, and the fifth connecting electrode75each comprises a first electrical connecting portion712,713,714,715and716, a bridge connecting portion701,702,703,704and705, and a second electrical connecting portion721,722,723,724and725. The first electrical connecting portions712,713,714,715and716of the connecting electrodes71˜75are used to contact the one or the plurality of first contact electrodes51and are electrically connected to the first semiconductor layer201of the plurality of light-emitting units C1˜C6through the first contact electrodes51. The second electrical connecting portions721,722,723,724and725of the connecting electrodes71˜75are used to contact the one or the plurality of second contact electrodes52and are electrically connected to the second semiconductor layer203of the light-emitting units C1˜C6through the second contact electrodes52. The bridge connecting portions701,702,702,704and705of the connecting electrodes71˜75are respectively formed on the trenches T12, T23, T34, T45and T56and electrically connects two adjacent light-emitting units C1˜C6. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the plurality of connecting electrodes71˜75is formed on two sides of the first extension electrode7100and/or formed on two sides of the second extension electrode7200. The first contact electrodes51, the second contact electrodes52, the first extension electrode7100, the second extension electrode7200and the connecting electrodes71˜75comprise a metal material comprising chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first contact electrodes51, the second contact electrodes52, the first extension electrode7100, the second extension electrode7200and/or the connecting electrodes71˜75comprise a single layer or multilayers. For example, the first contact electrodes51, the second contact electrodes52, the first extension electrode7100, the second extension electrode7200and/or the connecting electrodes71˜75comprise Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Cr/Ti/Al/Au stack, Ti/Al/Ti/Au stack, Cr/Al/Pt/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack. The light-emitting device1comprises a protective layer80covering the plurality of light-emitting units C1˜C6, wherein the protective layer80comprises one or a plurality of first protective layer openings801to expose the first extension electrode7100and one or a plurality of second protective layer openings802to expose the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the plurality of first protective layer openings801is formed on the first extension electrode7100of the first light-emitting unit C1and the plurality of third light-emitting units C2˜C3, and the plurality of second protective layer openings802is formed on the second extension electrode7200of the second light-emitting unit C6and the plurality of third light-emitting units C4˜C5. In an embodiment of the present application, when viewing from the top of the light-emitting device1, one or the plurality of first protective layer openings801is only formed on the first extension electrode7100of the first light-emitting unit C1, and one or the plurality of second protective layer openings802is only formed on the second extension electrode7200of the second light-emitting unit C6. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the position of the first protective layer opening801does not overlap with that of the first insulating layer opening601. The position of the second protective layer opening802does not overlap with that of the second insulating layer opening602. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first protective layer opening801and/or the second protective layer opening802comprises a non-linear pattern, such as a curve. In an embodiment of the present application, in the top view of the light-emitting device1, the first insulating layer opening601and/or the second insulating layer opening602comprises a circle, an ellipse, or a polygon. The insulating layer60and the protective layer80comprise a non-conductive material comprising organic material, inorganic material or dielectric material. The organic material comprises Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material comprises silicone or glass. The dielectric material comprises aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). The insulating layer60and/or the protective layer80comprises two or more materials of different refractive indices alternately stacked to form a Distributed Bragg Reflector (DBR), which selectively reflects light of a certain wavelength. For example, the Distributed Bragg Reflector (DBR) with high reflectivity can be formed by laminating SiO2/TiO2or SiO2/Nb2O5layers. When the wavelength of the light emitted from the light-emitting device1is λ, the optical thickness of the Distributed Bragg Reflector (DBR) can be an integral multiple of λ/4. The optical thickness of the Distributed Bragg Reflector (DBR) can have a deviation of ±30% on the basis of the integral multiple of λ/4. As shown inFIG.1,FIG.4andFIG.5, the light-emitting device1comprises a first electrode pad91covering the first protective layer opening801to contact the first extension electrode7100and a second electrode pad92covering the second protective layer opening802to contact the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first electrode pad91and the second electrode pad92do not cover the one or the plurality of connecting electrodes71˜75. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first electrode pad91and the second electrode pad92do not cover the first insulating layer opening601and/or the second insulating layer opening602. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the plurality of connecting electrodes71˜72is formed on two sides of the first electrode pad91and/or the plurality of connecting electrodes74˜75is formed on two sides of the second electrode pad92. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first electrode pad91is surrounded by the plurality of connecting electrodes71˜72, and/or the second electrode pad92is surrounded by the plurality of connecting electrodes74˜75. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first electrode pad91comprises a first electrode pad area smaller than a first surface area of the first extension electrode7100, or the second electrode pad92comprises a second electrode pad area smaller than a second surface area of the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device1shown inFIG.1, the first electrode pad91covers a first amount of the plurality of light-emitting units C1˜C6, the second electrode pad92covers a second amount of the plurality of light-emitting cells C1˜C6, and the first amount and the second amount is the same or different. The first electrode pad91and the second electrode pad92comprise a metal material comprising chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode pad91and the second electrode pad92comprise a single layer or multilayers. For example, the first electrode pad91or the second electrode pad92comprises Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack, Cr/Al/Ti/Al/Ni//Pt/Au stack or Cr/Al/Cr/Ni/Au stack. The first electrode pad91and the second electrode pad92can be used as an electrical path for an external power source to supply current to the first semiconductor layer201and the second semiconductor layer203. The first electrode pad91and the second electrode pad92each comprises a thickness between 1˜100 μm, preferably between 1.2˜60 μm, and more preferably between 1.5˜6 μm. FIG.6is a top view of a light-emitting device2in accordance with an embodiment of the present application.FIG.7illustrates a cross-sectional view taken along line E-E1-E2-E′ ofFIG.6.FIG.8illustrates a cross-sectional view taken along line F-F1-F2-F′ ofFIG.6.FIG.9illustrates a cross-sectional view taken along line G-G′ ofFIG.6.FIG.10illustrates a cross-sectional view taken along line H-H′ ofFIG.6. The light-emitting device2and the light-emitting device1have substantially the same structure. Therefore, the same names and the same reference numbers of the light-emitting device2shown inFIG.6˜FIG.10and the light-emitting device1shown inFIG.1˜FIG.5have the same structures, which will be omitted or not repeated here. As shown inFIG.6˜FIG.10, the light-emitting device2comprises a substrate10comprising a top surface100; a plurality of light-emitting units C1˜C6formed on the substrate10comprising a first light-emitting unit C1, a second light-emitting unit C6, and one or a plurality of third light-emitting units C2˜C5wherein each of light-emitting units C1˜C6comprises a first semiconductor layer201, an active layer202, and a second semiconductor layer203; an insulating layer60comprising a first insulating layer opening601and a second insulating layer opening602formed on each of light-emitting units C1˜C6; a first extension electrode7100covering the first light-emitting unit C1wherein the first extension electrode7100covers the first insulating layer opening601on the first light-emitting unit C1without covering the second insulating layer opening602on the first light-emitting unit C1; the second extension electrode7200covering the second light-emitting unit C6wherein the second extension electrode7200covers the second insulating layer opening602on the second light-emitting unit C6without covering the first insulating layer opening601on the second light-emitting unit C6; a first electrode pad91covering a first part of the plurality of the light-emitting units C1˜C6; and a second electrode pad92covering a second part of the plurality of light-emitting units C1˜C6. The light-emitting device2comprises a trench T12, T23, T34, T45or T56formed between two adjacent light-emitting units C1˜C6, and the trenches T12, T23, T34, T45and T56expose the top surface100of the substrate10. One or a plurality of current blocking layers30is formed on the second semiconductor layer203. The light-emitting device2comprises a conductive layer40formed on the second semiconductor layer203and/or the current blocking layer30, and the conductive layer40covers a sidewall of the current blocking layer30. The light-emitting device2comprises one or a plurality of first contact electrodes51respectively formed on one or a plurality of recesses200of the plurality of light-emitting units C1˜C6to contact the first semiconductor layer201and one or a plurality of second contact electrodes52respectively formed on the second semiconductor layers203of the plurality of light-emitting units C1˜C6. The light-emitting device2comprises an insulating layer60to cover the semiconductor stack20, wherein the insulating layer60comprises one or a plurality of first insulating layer openings601to expose the one or the plurality of first contact electrodes51and one or a plurality of second insulating layer openings602to expose the one or the plurality of second contact electrodes52. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the light-emitting device2comprises a first extension electrode7100covering the first light-emitting unit C1, wherein the first extension electrode7100covers the first insulating layer opening601of the first light-emitting unit C1without covering the second insulating layer opening602of the first light-emitting unit C1. The first extension electrode7100contacts the first contact electrode51of the first light-emitting unit C1through the first insulating layer opening601of the first light-emitting unit C1and is electrically connected to the first semiconductor layer201of the first light-emitting unit C1. The light-emitting device2further comprises a second extension electrode7200covering the second light-emitting unit C6, wherein the second extension electrode7200covers the second insulating layer opening602of the second light-emitting unit C6without covering the first insulating layer opens601of the second light-emitting unit C6. The second extension electrode7200contacts the second contact electrode52of the second light-emitting unit C6through the second insulating layer opening602of the second light emitting unit C6and is electrically connected to the second semiconductor layer203of the second light-emitting unit C6. The light-emitting device2comprises one or a plurality of connecting electrodes71˜75formed between two adjacent light-emitting units C1˜C6. The connecting electrodes71˜75comprise a first connecting electrode71, a second connecting electrode72, a third connecting electrode73, a fourth connecting electrode74, and a fifth connecting electrode75. The first connecting electrode71, the second connecting electrode72, the third connecting electrode73, the fourth connecting electrode74, and the fifth connecting electrode75each comprises a first electrical connecting portion712,713,714,715and716, a bridge connecting portion701,702,703,704and705, and a second electrical connecting portion721,722,723,724and725. In an embodiment of the present application, as shown inFIG.6,FIG.9andFIG.10, the light-emitting device2further comprises a first metal layer7001covering the first light-emitting unit C1and the plurality of third light-emitting units C2˜C3and a second metal layer7002covering the second light-emitting unit C6and the plurality of third light-emitting units C4˜C5, wherein the first metal layer7001and the second metal layer7002are electrically insulated from the plurality of light-emitting units C1˜C6. In an embodiment of the present application, as shown inFIG.6,FIG.9andFIG.10, the first metal layer7001and the second metal layer7002cover a part of the first contact electrode51and the second contact electrode52, but the positions of the first metal layer7001and the second metal layer7002are misaligned with the positions of the first insulating layer opening601and the second insulating layer opening602. In other words, the first metal layer7001and the second metal layer7002do not overlap with the first insulating layer opening601and the second insulating layer opening602. In an embodiment of the present application, as shown inFIG.6, the first metal layer7001covers the first trench T12formed between the first light-emitting unit C1and the third light-emitting unit C2, and/or the second trench T23formed between the two adjacent third light-emitting units C2and C3. The second metal layer7002covers the fourth trench T45formed between the two adjacent third light-emitting units C4and C5, and/or the fifth trench T56formed between the third light-emitting unit C5and the second light-emitting unit C6. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first metal layer7001comprises a first metal surface area larger than a first extension surface area of the first extension electrode7100, and/or the second metal layer7002comprises a second metal surface area larger than a second extension surface area of the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device2, a plurality of connecting electrodes71˜72are formed on two sides of the first extension electrode7100and the first metal layer7001and/or the plurality of connecting electrodes74˜75are formed on two sides of the second extension electrode7200and the second metal layer7002. The light-emitting device2comprises a protective layer80covering the plurality of light-emitting units C1˜C6, wherein the protective layer80comprises one or a plurality of first protective layer openings801to expose the first extension electrode7100and one or a plurality of second protective layer openings802to expose the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the one or the plurality of first protective layer openings801is only formed on the first extension electrode7100of the first light-emitting unit C1and the one or the plurality of second protective layer openings802is only formed on the second extension electrode7200of the second light-emitting unit C6. As shown inFIG.6,FIG.7andFIG.8, the light-emitting device2comprises a first electrode pad91covering the first protective layer opening801to contact the first extension electrode7100and a second electrode pad92covering the second protective layer opening802to contact the second extension electrode7200. In an embodiment of the present application, viewing from the top of the light-emitting device2, the light-emitting device2comprises the plurality of first protective layer openings801respectively formed on the first extension electrode7100of the first light-emitting unit C1and the first metal layer7001of the plurality of third light-emitting units C2˜C3. The light-emitting device2comprises the plurality of second protective layer openings802respectively formed on the second extension electrode7200of the second light-emitting unit C6and the second metal layer7002of the plurality of third light-emitting units C4˜C5. The first electrode pad91covers the first protective layer openings801to contact the first extension electrode7100and the first metal layer7001, and the second electrode pad92covers the second protective layer openings802to contact the second extension electrode7200and the second metal layer7002. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first electrode pad91and the second electrode pad92do not cover the one or the plurality of connecting electrodes71˜75. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first electrode pad91and the second electrode pad92do not cover the first insulating layer opening601and/or the second insulating layer opening602. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first electrode pad91comprises a first electrode pad area larger than a first surface area of the first extension electrode7100, or the second electrode pad92comprises a second electrode pad area larger than a second surface area of the second extension electrode7200. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first electrode pad91comprises a first electrode pad area larger than a first metal surface area of the first metal layer7001, or the second electrode pad92comprises a second electrode pad area larger than a second metal surface area of the second metal layer7002. In an embodiment of the present application, in the top view of the light-emitting device2shown inFIG.6, the first electrode pad91covers the first metal layer7001and the first extension electrode7100, and the second electrode pad92covers the second metal layer7002and the second extension electrode7200. FIG.11illustrates a top view of a light-emitting device3in accordance with an embodiment of the present application.FIG.12illustrates a cross-sectional view taken along line I-I1-I2-I3-14-I′ ofFIG.11.FIG.13illustrates a cross-sectional view taken along line J-J5-J4-J3-J2-J1-J′ ofFIG.11.FIG.14illustrates a cross-sectional view taken along line K-K1-K2-K′ ofFIG.11. The light-emitting device3and the light-emitting device1have substantially the same structure. Therefore, the same names and the same reference numbers of the light-emitting device3shown inFIG.11˜FIG.14and the light-emitting device1shown inFIG.1˜FIG.5have the same structures, which will be omitted or not repeated here. The light-emitting device3comprises a substrate10comprising a top surface100; a plurality of light-emitting units C1˜C8formed on the top surface100of the substrate10comprising a first light-emitting unit C1, a second light-emitting unit C8, and one or a plurality of third light-emitting units C2˜C7wherein the light-emitting units C1˜C8each comprises a first semiconductor layer201, an active layer202, and a second semiconductor layer203; a first metal layer7001acovering the first light-emitting unit C1and a first part of the plurality of third light-emitting units C2˜C4; a second metal layer7002acovering the second light-emitting unit C8and a second part of the plurality of third light-emitting units C5˜C7wherein the first metal layer7001aand the second metal layer7002aare electrically insulated from the plurality of light-emitting units C1˜C8; a first electrode pad91acovering the first light-emitting unit C1and the first part of the plurality of third light-emitting units C2˜C4; and a second electrode pad92acovering the second light-emitting unit C8and the second part of the plurality of third light-emitting units C5˜C7wherein the first part of the plurality of third light-emitting units C2˜C4and the second part of the plurality of third light-emitting units C5˜C7comprise the same amount of the light-emitting units. In an embodiment, the first light-emitting unit C1, the second light-emitting unit C8, and the one or the plurality of third light-emitting units C2˜C7is electrically connected in series. As shown inFIG.11˜FIG.14, the plurality of light-emitting units C1˜C8of the light-emitting device3each comprises one or a plurality of recesses200aand a semiconductor mesa204a, and the semiconductor mesa204ais surrounded by the plurality of recesses200a. Specifically, the semiconductor mesa204acomprises the first semiconductor layer201, the second semiconductor layer203, and the active layer202. The recess200aexposes a surface of the first semiconductor layer201. The light-emitting device3comprises a trench T12, T23, T34, T45, T56, T67and T78formed between two adjacent light-emitting units C1˜C8, and the trenches T12, T23, T34, T45, T56, T67and T78expose the top surface100of the substrate10. As shown inFIG.11, the light-emitting device3comprises a first trench T12formed between the first light-emitting unit C1and the third light-emitting unit C2; a second trench T23formed between two adjacent third light-emitting units C2and C3; a third trench T34formed between two adjacent third light-emitting units C3and C4; a fourth trench T45formed between two adjacent third light-emitting units C4and C5; a fifth trench T56formed between two adjacent third light-emitting units C5and C6; a sixth trench T67formed between two adjacent third light-emitting units C6and C7; and a seventh trench T78formed between the third light-emitting unit C7and the second light-emitting unit C8. The light-emitting device3comprises a blocking layer62acovering the semiconductor stack20of each of the light-emitting units C1˜C8, wherein the blocking layer62acomprises one or a plurality of first blocking layer openings621ato expose the first semiconductor layer201of each of the light-emitting units C1˜C8and one or a plurality of second blocking layer openings622ato expose the second semiconductor layer203of each of the light-emitting unit C1˜C8. As shown inFIG.12˜FIG.14, the light-emitting device3comprises a conductive layer40formed in the one or the plurality of second blocking layer openings622aof each of light-emitting units C1˜C8to contact the second semiconductor layer203and a metal reflective layer42aformed in the one or the plurality of second blocking layer openings622ato contact the second semiconductor layer203and/or the conductive layer40. The metal reflective layer42ais formed on the conductive layer40and covers a sidewall of the conductive layer40. The conductive layer40comprises a material that is transparent to the light emitted from the active layer202, such as a metal material with a thickness thinner than 100 Å or a transparent conductive oxide. The transparent conductive oxide comprises indium tin oxide (ITO) or indium zinc oxide (IZO). The material of the metal reflective layer42acomprises a metal comprising aluminum (Al), silver (Ag), rhodium (Rh), platinum (Pt), or an alloy of the above materials. The metal reflective layer42acan reflect a light so the light exits in a direction toward the substrate10, wherein the reflected light is from the active layer202of each of the light-emitting units C1˜C8. In an embodiment, a barrier layer (not shown) is formed on the metal reflective layer42aof each of the light-emitting units C1˜C8to cover a top surface and a side surface of the metal reflective layer42ato avoid the surface oxidation of the metal reflective layer42a, thereby deteriorating the reflectivity of the metal reflective layer42a. The material of the barrier layer comprises metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt), or an alloy of the above materials. The barrier layer comprises a structure having one or more layers, such as titanium (Ti)/aluminum (Al), and/or nickel titanium alloy (NiTi)/titanium tungsten alloy (TiW). In an embodiment, the metal reflective layer42aof each of the light-emitting units C1˜C8is directly formed on the second semiconductor layer203, and the conductive layer40is formed on the metal reflective layer42a(not shown) to reduce the light from the active layer202of each of the light-emitting units C1˜C8being absorbed by the conductive layer40. In an embodiment, the blocking layer62acovers a periphery of the metal reflective layer42aand the conductive layer40to protect the metal reflective layer42aand the conductive layer40from being affected by the subsequent processes. The light-emitting device3comprises an insulating layer60acovering the semiconductor stack20of each of the light-emitting units C1˜C8, wherein the insulating layer60acomprises one or a plurality of first insulating layer openings601ato expose the first semiconductor layer201of each of the light-emitting units C1˜C8and one or a plurality of second insulating layer openings602ato expose the second semiconductor layer203, the conductive layer40or the metal reflective layer42aof each of the light-emitting units C1˜C8. In an embodiment, the one or the plurality of first insulating layer openings601ais formed on an outer periphery of the light-emitting units C1˜C8. Specifically, the semiconductor mesa204aof each of the light-emitting units C1˜C8is surrounded by the one or the plurality of recesses200a, and the one or the plurality of first insulating layer openings601ais formed on the one or the plurality of recesses200ato expose the surface of the first semiconductor layer201. As shown inFIG.11˜FIG.14, the light-emitting device3comprises a first extension electrode7100acovering the first light-emitting unit C1, wherein the first extension electrode7100acovers the one or the plurality of first insulating layer opening601aof the first light-emitting unit C1, and the first extension electrode7100acontacts the first semiconductor layer201of the first light-emitting unit C1through the one or the plurality of first insulating layer openings601a. The light-emitting device3further comprises a second extension electrode7200acovering the second light-emitting unit C8, wherein the second extension electrode7200acovers the one or the plurality of second insulating layer openings602aof the second light-emitting unit C8, and the second extension electrode7200ais electrically connected to the second semiconductor layer203of the second light-emitting unit C8through the one or the plurality of second insulating layer openings602a. The light-emitting device3comprises one or a plurality of connecting electrodes71a˜77aformed between two adjacent light-emitting units C1˜C8. As shown inFIG.11, the connecting electrodes71a˜77acomprise a first connecting electrode71a, a second connecting electrode72a, a third connecting electrode73a, a fourth connecting electrode74a, a fifth connecting electrode75a, a sixth connecting electrode76a, and a seventh connecting electrode77a. The first connecting electrode71ais formed between the first light-emitting unit C1and the third light-emitting unit C2, the second connecting electrode72ais formed between two adjacent third light-emitting units C2and C3, the third connecting electrode73ais formed between two adjacent third light-emitting units C3and C4, the fourth connecting electrode74ais formed between two adjacent third light-emitting units C4and C5, the fifth connecting electrode75ais formed between two adjacent third light-emitting units C5and C6, the sixth connecting electrode76ais formed between two adjacent third light-emitting units C6and C7, and the seventh connecting electrode77ais formed between the third light-emitting unit C7and the second light-emitting unit C8. The first connecting electrode71a, the second connecting electrode72a, the third connecting electrode73a, the fourth connecting electrode74a, the fifth connecting electrode75a, the sixth connecting electrode76a, and the seventh connecting electrode77aeach comprises a first electrical connecting portion712a,713a,714a,715a,716a,717aand718a, a bridge connecting portion701a,702a,703a,704a,705a,706aand707a, and a second electrical connecting portion721a,722a,723a,724a,725a,726aand727a. The first electrical connecting portions712a,713a,714a,715a,716a,717aand718aof the connecting electrodes71a˜77aeach contacts the first semiconductor layer201of each of light-emitting units C2˜C8. The second electrical connecting portions721a,722a,723a,724a,725a,726aand727aof the connecting electrodes71a˜77aeach contacts the metal reflective layer42aand/or the barrier layer of each of light-emitting units C1˜C7(not shown) and/or the conductive layer40, and are electrically connected to the second semiconductor layers203of the plurality of light-emitting units C1˜C7through the metal reflective layer42a, the barrier layer (not shown) and/or the conductive layer40. The bridge connecting portions701a,702a,703a,704a,705a,706aand707aof the connecting electrodes71a˜77aare respectively formed on the trenches T12, T23, T34, T45, T56, T67and T78to electrically connect two adjacent light-emitting units C1˜C8. The light-emitting device3comprises a protective layer80acovering the plurality of light-emitting units C1˜C8, wherein the protective layer80acomprises one or a plurality of first protective layer openings801ato expose the first extension electrode7100aof the first light-emitting unit C1and one or a plurality of second protective layer openings802ato expose the second extension electrode7200aof the second light-emitting unit C8. In an embodiment of the present application, viewing from the top of the light-emitting device3, the plurality of first protective layer openings801ais formed on the first extension electrode7100aof the first light-emitting unit C1and the plurality of first metal layer7001aof the plurality of third light-emitting unit C2˜C4, and/or the plurality of second protective layer openings802ais formed on the second extension electrode7200aof the second light-emitting unit C8and/or on the second metal layer7002aof the plurality of third light-emitting units C5˜C7. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the position of the first protective layer opening801ais misaligned with the first insulating layer opening601a. The position of the second protective layer opening802ais misaligned with that of the second insulating layer opening602a. The light-emitting device3comprises a first electrode pad91acovering the first protective layer opening801ato contact the first extension electrode7100aformed on the first light-emitting unit C1and a second electrode pad92acovering the second protective layer opening802ato contact the second extension electrode7200aformed on the second light-emitting unit C8. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91aand the second electrode pad92ado not cover the one or the plurality of connecting electrodes71a˜77a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91aand the second electrode pad92ado not cover the first insulating layer opening601aand/or the second insulating layer opening602a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91acovers the first metal layer7001a, and/or the second electrode pad92acovers the second metal layer7002a. As shown inFIG.12andFIG.14, the protective layer80ais formed between the first electrode pad91aand the first metal layer7001a, and the protective layer80ais located between the second electrode pad92aand the second metal layer7002a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the plurality of connecting electrodes71a˜74ais formed on two sides of the first electrode pad91aand/or the plurality of connecting electrodes74a-77ais formed on two sides of the second electrode pad92a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91ais surrounded by the plurality of connecting electrodes71a˜74a, and/or the second electrode pad92ais surrounded by the plurality of connecting electrodes74a˜77a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91acomprises a first electrode pad area larger than a first metal surface area of the first metal layer7001a, or the second electrode pad92acomprises a second electrode pad area larger than a second metal surface area of the second metal layer7002a. In an embodiment of the present application, in the top view of the light-emitting device3shown inFIG.11, the first electrode pad91acovers a first amount of the plurality of light-emitting units C1˜C8, the second electrode pad92acovers a second amount of the plurality of light-emitting units C1˜C8, and the first amount and the second amount are the same or different. FIG.15illustrates a top view of a light-emitting device4in accordance with an embodiment of the present application.FIG.16illustrates a cross-sectional view taken along line L-L′ ofFIG.15. The light-emitting device4, the light-emitting device1, and the light-emitting device3have substantially the same structure. Therefore, the same names and the same reference numbers of the light-emitting device4shown inFIG.15˜FIG.16, the light-emitting device1shown inFIG.1˜FIG.5and the light-emitting device3shown inFIG.11˜FIG.14have the same structures, which will be omitted or not repeated here. The light-emitting device4comprises a substrate10comprising a top surface100; a plurality of light-emitting units C1˜C7formed on the top surface100of the substrate10comprising a first light-emitting unit C1, a second light-emitting unit C7, and one or a plurality of third light-emitting units C2˜C6wherein the plurality of light-emitting units C1˜C7each comprises a first semiconductor layer201, an active layer202and a second semiconductor layer203; a first metal layer7001bcovering the first light-emitting unit C1and a first part of the plurality of third light-emitting units C2˜C4; a second metal layer7002bcovering the second light-emitting unit C7and a second part of the plurality of third light-emitting units C4˜C6wherein the first metal layer7001band the second metal layer7002bare electrically insulated from the plurality of light-emitting units C1˜C7; a first electrode pad91bcovering the first light-emitting unit C1and the first part of the plurality of third light-emitting units C2˜C4; and a second electrode pad92bcovering the second light-emitting unit C7and the second part of the plurality of third light-emitting units C4˜C6. In an embodiment, the first light-emitting unit C1, the second light-emitting unit C7, and the one or the plurality of third light-emitting units C2˜C6is electrically connected in series. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first light-emitting unit C1, the second light-emitting unit C7, and the plurality of third light-emitting units C2˜C6is arranged as a rectangle comprising a plurality of rows. The first light-emitting unit C1and the third light-emitting unit C2are arranged in a first row, the third light-emitting units C3˜C5are arranged in a second row, and the second light-emitting unit C7and the third light-emitting unit C6are arranged in a third row. The second row is located between the first row and the third row. The plurality of rows comprises different amount of light-emitting units from each other, for example, the amount of the light-emitting units located in the first row is different from the amount of the light-emitting units located in the second row. As shown inFIG.15˜FIG.16, the plurality of light-emitting units C1˜C7of the light-emitting device4each comprises one or a plurality of recesses200band a semiconductor mesa204b. Specifically, the semiconductor mesa204bcomprises a first semiconductor layer201, a second semiconductor layer203, and an active layer202. The recess200bexposes a surface of the first semiconductor layer201. The light-emitting device4comprises a trench T12, T23, T34, T45, T56and T67formed between two adjacent light-emitting units C1˜C7, and the trenches T12, T23, T34, T45, T56, T67and T78expose the top surface100of the substrate10, wherein the trenches T34and T45are located on the same side of the third light-emitting unit C4, and the trenches T34and T45are directly connected. As shown inFIG.15, the light-emitting device4comprises a first trench T12formed between the first light-emitting unit C1and the third light-emitting unit C2; a second trench T23formed between two adjacent third light-emitting units C2and C3; a third trench T34formed between two adjacent third light-emitting units C3and C4; a fourth trench T45formed between two adjacent third light-emitting units C4and C5, wherein the third light-emitting units C3and C5are located on the same side of the third light-emitting unit C4; a fifth trench T56formed between the third light-emitting units C5and C6; and a sixth trench T67formed between the third light-emitting unit C6and the second light-emitting unit C7. The light-emitting device4comprises a blocking layer62bcovering the semiconductor stack20of each of the light-emitting units C1˜C7, wherein the blocking layer62bcomprises one or a plurality of first blocking layer openings621bexposing the first semiconductor layer201of each of the light-emitting units C1˜C7, and one or plurality of second blocking layer openings622bexposing the second semiconductor layer203of each of the light-emitting unit C1˜C7. As shown inFIGS.15˜16, the light-emitting device4comprises a conductive layer40formed in the one or the plurality of second blocking layer openings622bof the plurality of light-emitting units C1˜C7to contact the second semiconductor layer203; and a metal reflective layer42bformed in the one or the plurality of second blocking layer openings622bto contact the second semiconductor layer203and/or the conductive layer40, wherein the metal reflective layer42bis formed on the conductive layer40and covers the sidewall of the conductive layer40. The light-emitting device4comprises an insulating layer60bto cover the semiconductor stack20of each of the light-emitting units C1˜C7, wherein the insulating layer60bcomprises one or a plurality of first insulating layer openings601bto expose the first semiconductor layer201, and one or a plurality of second insulating layer openings602bto expose the second semiconductor layer203, the conductive layer40or the metal reflective layer42bof each of the light-emitting units C1˜C7. In an embodiment, the one or the plurality of first insulating layer openings601bis formed on an outer periphery of the light-emitting units C1˜C7. Specifically, the semiconductor mesa204bof each of the light-emitting units C1˜C7is surrounded by the one or the plurality of recesses200b, and the one or the plurality of first insulating layer openings601bis formed on the one or the plurality of recesses200bto expose the surface of the first semiconductor layer201. As shown inFIGS.15˜16, the light-emitting device4comprises a first extension electrode7100bcovering the one or the plurality of first insulating layer openings601bof the first light-emitting unit C1, and the first extension electrode7100bcontacts the first semiconductor layer201of the first light-emitting unit C1through the one or the plurality of first insulating layer openings601b. The light-emitting device4further comprises a second extension electrode7200bcovering the one or the plurality of second insulating layer openings602bof the second light-emitting unit C7, and the second extension electrode7200bis electrically connected to the second semiconductor layer203of the second light-emitting unit C7through the one or the plurality of second insulating layer openings602b. The light-emitting device4comprises one or a plurality of connecting electrodes71b˜76bformed between two adjacent light-emitting units C1˜C7. As shown inFIG.15, the connecting electrodes71b˜76bcomprise a first connecting electrode71b, a second connecting electrode72b, a third connecting electrode73b, a fourth connecting electrode74b, a fifth connecting electrode75b, and a sixth connecting electrode76b. The first connecting electrode71bis formed between the first light-emitting unit C1and the third light-emitting unit C2, the second connecting electrode72bis formed between two adjacent third light-emitting units C2˜C3, the third connecting electrode73bis formed between two adjacent third light-emitting units C3˜C4, the fourth connecting electrode74bis formed between two adjacent third light-emitting units C4˜C5, and the fifth connecting electrode75bis formed between two adjacent third light-emitting units C5˜C6, and the sixth connecting electrode76bis formed between the third light-emitting unit C6and the second light-emitting unit C7. The first connecting electrode71b, the second connecting electrode72b, the third connecting electrode73b, the fourth connecting electrode74b, the fifth connecting electrode75b, and the sixth connecting electrode76beach comprises a first electrical connecting portion712b,713b,714b,715b,716band717b, a bridge connecting portion701b,702b,703b,704b,705band706b, and a second electrical connecting portion721b,722b,723b,724b,725band726b. The first electrical connecting portions712b,713b,714b,715b,716band717bof the connecting electrodes71b˜76beach contacts the first semiconductor layer201of each of light-emitting units C2˜C7. The second electrical connecting portions721b,722b,723b,724b,725band726bof the connecting electrodes71b˜77beach contacts the metal reflective layer42band/or the barrier layer of each of light-emitting units C1˜C6(not shown), and are electrically connected to the second semiconductor layer203of each of light-emitting units C1˜C7through the metal reflective layer42band/or the barrier layer (not shown). The bridge connecting portions701b,702b,703b,704b,705band706bof the connecting electrodes71b˜76bare respectively formed on the trenches T12, T23, T34, T45, T56and T67and electrically connects two adjacent light-emitting units C1˜C7. The first metal layers7001,7001a,7001b, the first extension electrodes7100a,7100b, the second metal layers7002,7002a,7002b, the second extension electrodes7200a,7200b, and the connecting electrodes71a˜77a,71b˜76bcomprise a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first metal layers7001,7001a,7001b, the first extension electrodes7100a,7100b, the second metal layers7002,7002a,7002b, the second extension electrodes7200a,7200band the connecting electrodes71a˜77a,71b˜76bcan compose of a single layer or multiple layers. For example, the first metal layers7001,7001a,7001b, the first extension electrodes7100a,7100b, the second metal layers7002,7002a,7002b, the second extension electrodes7200a,7200band/or the connecting electrodes71a˜77a,71b˜76bcomprise Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack. The light-emitting device4comprises a protective layer80bcovering the plurality of light-emitting units C1˜C7, wherein the protective layer80bcomprises one or a plurality of first protective layer openings801bto expose the first extension electrode7100bon the first light-emitting unit C1, and one or a plurality of second protective layer openings802bto expose the second extension electrode7200bon the second light-emitting unit C2. In an embodiment of the present application, viewing from the top of the light-emitting device4, the plurality of first protective layer openings801bis formed on the first extension electrode7100aof the first light-emitting unit C1and the first metal layer7001bof the plurality of third light-emitting unit C2˜C4, and/or the plurality of second protective layer openings802bis located on the second extension electrode7200bof the second light-emitting unit C7and the second metal layer7002bof the plurality of light-emitting units C4˜C6. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the position of the first protective layer opening801bis misaligned with the first insulating layer opening601b. The position of the second protective layer opening802bis misaligned with the second insulating layer opening602b. The blocking layers62a,62b, the insulating layers60a,60b, and the protective layers80a,80bcomprise non-conductive materials comprising the organic materials, the inorganic materials, or the dielectric materials. The organic materials comprise Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide or fluorocarbon polymer. The inorganic materials comprise silicone or glass. The dielectric materials comprise aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). The blocking layers62a,62b, the insulating layers60a,60b, and/or the protective layers80a,80bcomprise two or more materials with different refractive indexes alternately stacked to form a distributed Bragg reflector (DBR) structure to selectively reflect the light of a certain wavelength. For example, the distributed Bragg reflector (DBR) with high reflectivity can be formed by laminating SiO2/TiO2or SiO2/Nb2O5layers. The light-emitting device4comprises a first electrode pad91bcovering the first protective layer opening801bto contact the first extension electrode7100bon the first light-emitting unit C1and a second electrode pad92bcovering the second protective layer opening802bto contact the second extension electrode7200bon the second light-emitting unit C7. In an embodiment of the present application, in the top view of the light-emitting device4, as shown inFIG.15, the first electrode pad91band the second electrode pad92bdo not cover the one or the plurality of connecting electrodes71b˜76b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first electrode pad91band the second electrode pad92bdo not cover the first insulating layer opening601band/or the second insulating layer opening602b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first electrode pad91bcovers the first metal layer7001b, and/or the second electrode pad92bcovers the second metal layer7002b. As shown inFIGS.15˜16, the protective layer80bis formed between the first electrode pad91band the first metal layer7001b, and the protective layer80bis formed between the second electrode pad92band the second metal layer7002b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first metal layer7001band the second metal layer7002bcover the same third light-emitting unit C4. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the plurality of connecting electrodes71b˜73bis located on two sides of the first electrode pad91band/or the plurality of connecting electrodes74b˜76bis located on two sides of the second electrode pad92b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first electrode pad91bis surrounded by the plurality of connecting electrodes71b˜73b, and/or the second electrode pad92bis surrounded by the plurality of connecting electrodes74b˜76b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the first electrode pad91bcomprises a first electrode pad area larger than a first metal surface area of the first metal layer7001b, or the second electrode pad92bcomprises a second electrode pad area larger than a second metal surface area of the second metal layer7002b. In an embodiment of the present application, in the top view of the light-emitting device4shown inFIG.15, the light-emitting device4comprises an odd amount of light-emitting units C1˜C7. The first electrode pad91bcovers a first amount of the plurality of light-emitting units C1˜C7and the second electrode pad92bcovers a second amount of the plurality of light-emitting units C1˜C7, wherein the first electrode pad91band the second electrode pad92bcover the same light-emitting unit, such as the third light-emitting unit C4. The first electrode pads91a,91band the second electrode pads92a,92bcomprise metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode pads91a,91band the second electrode pads92a,92bcomprise a single layer or multiple layers. For example, the first electrode pad91a,91bor the second electrode pad92a,92bcomprises Ti/Au stack, Ti/Pt/Au stack, Cr/Au stack, Cr/Pt/Au stack, Ni/Au stack, Ni/Pt/Au stack or Cr/Al/Cr/Ni/Au stack. The first electrode pads91a,91band the second electrode pads92a,92bare provided as a current path for external power supply connecting to the first semiconductor layer201and the second semiconductor layer203. The first electrode pads91a,91band the second electrode pads92a,92bcomprise a thickness between 1 and 100 μm, preferably between 1.2 and 60 μm, more preferably between 1.5 and 6 μm. FIG.17is a schematic view of a light-emitting apparatus5in accordance with an embodiment of the present application. The light-emitting device1,2,3or4in the foregoing embodiment is mounted on the first spacer511and the second spacer512of the package substrate51in the form of flip chip. The first spacer511and the second spacer512are electrically insulated from each other by an insulating portion53comprising an insulating material. The main light-extraction surface of the flip chip is one side of the growth substrate opposite to the electrode-forming surface where the electrodes are formed on. A reflective structure54can be provided around the light-emitting device1,2,3or4to increase the light extraction efficiency of the light-emitting apparatus5. FIG.18illustrates a structure diagram of a light-emitting apparatus6in accordance with an embodiment of the present application. A light bulb comprises an envelope602, a lens604, a light-emitting module610, a base612, a heat sink614, a connector616and an electrical connecting device618. The light-emitting module610comprises a submount606and a plurality of light-emitting devices608on the submount606, wherein the plurality of light-emitting devices608can be the light-emitting device1,2,3or4or the light-emitting apparatus5described in above embodiments. The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims. | 68,082 |
11942512 | DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the invention will be described in detail with reference to the drawings. In the drawings, those having the same reference numerals indicate the same constituent elements or constituent elements having similar functions. In addition, p−, p, p+ indicate that a conductive type of a semiconductor layer is a p type, and relative impurity concentrations increase in this order. Similarly, n−, n, n+ indicate that a conductive type of the semiconductor layer is an n type, and relative impurity concentrations increase in this order. Embodiment 1 A semiconductor device according to Embodiment 1 of the invention and a manufacturing method thereof will be described with reference toFIGS.1to7. FIG.1is a top view of an IGBT semiconductor chip101, which is the semiconductor device according to Embodiment 1. An active region103of an IGBT is provided at a center of the chip. In addition, a gate electrode PAD104for applying a gate voltage of the IGBT is provided. A chip termination guard ring region102is provided on an outer periphery of the IGBT semiconductor chip101. FIG.2is a cross-sectional view of the active region103and the chip termination guard ring region102of the IGBT semiconductor chip101. In the active region103, trench gates207are periodically arranged, and contacts203are provided between adjacent trench gates207. The contact203penetrates an insulating layer (interlayer insulating film202) and is connected to an emitter electrode201which is a first metal layer. The trench gate207includes a gate insulating film208and polysilicon (Poly-Si) embedded in the trench, and forms a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a p base layer206and an n+ source layer204formed on a front surface of an n-semiconductor substrate209so as to have a function of turning on/off the IGBT semiconductor chip101. In addition, the p base layer206is provided with a p+ layer205in order to reduce contact resistance with the contact203. The trench gate207is connected to a polysilicon gate wiring214on a field oxide film222by the polysilicon (Poly-Si) embedded in the trench, and is connected to a gate electrode213via the contact203through an insulating layer (interlayer insulating film202). In the chip termination guard ring region102, a plurality of second conductive type (p type) guard rings215are arranged on the front surface of the n-semiconductor substrate209, and at the chip termination, a first conductive type (n type) channel stopper216is disposed on the front surface of the n-semiconductor substrate209. Each of the plurality of second conductive type (p type) guard rings215is connected to a corresponding second metal layer217by a corresponding contact203through the field oxide film222and the insulating layer (interlayer insulating film202). The first conductive type (n type) channel stopper216is connected to a third metal layer218by the contact203through the insulating layer (interlayer insulating film202). The second metal layer217covers a surface of the corresponding second conductive type (p type) guard ring215and has a laminated structure of at least two or more kinds of dissimilar metals, and this laminated structure of dissimilar metals is formed such that a first metal219is in contact with the corresponding second conductive type (p type) guard ring215, and a second metal220having a lower standard potential than the first metal219is in contact with the first metal219. In addition, the second metal layer217connected to the second conductive type (p type) guard ring215and the third metal layer218connected to the first conductive type (n type) channel stopper216are covered with an organic passivation film (protective film)221. Here, the laminated structure of the first metal219and the second metal220is formed such that a ratio of a contact area of the first metal219with the organic passivation film (protective film)221to a contact area of the second metal220with the organic passivation film (protective film)221is 0.05 or less. An n type buffer layer210, a p type collector layer211, and a collector electrode212are formed in this order on a back surface of the n-semiconductor substrate209, that is, on a main surface (back surface) of the n-semiconductor substrate209opposite to a main surface (front surface) on a side where the trench gates207are formed. A relation between the first metal219and the second metal220will be described in detail with reference toFIGS.3to6. For ease of explanation,FIGS.3and5show a state before the second metal layer217is covered with the organic passivation film (protective film)221, that is, a state in which an upper surface and a side surface of the second metal220and an upper surface and a side surface of the first metal219that are not covered with the second metal220are exposed. FIGS.3A and3Bare schematic views showing a relation between an exposed surface area A of the first metal219and an exposed surface area B of the second metal220in a cross-section of a main part of a guard ring portion. FIG.3A shows a case where the ratio of the exposed surface area A of the first metal219to the exposed surface area B of the second metal220is large, andFIG.3Bshows a case where the ratio of the exposed surface area A of the first metal219to the exposed surface area B of the second metal220is small. FIG.4is a characteristic diagram showing a relation between a corrosion amount of the first metal219and the ratio of the exposed surface area A of the first metal219to the exposed surface area B of the second metal220. According to the examination of the inventors of the present application, it was found that since the above-mentioned galvanic reaction satisfies Formula (1), corrosion of the first metal219can be prevented when the ratio of the exposed surface area A of the first metal219to the exposed surface area B of the second metal220is 0.05 or less as shown inFIG.4. FIGS.5A and5Bare schematic views showing a percentage of an area Ts1of an upper surface of the first metal219that is covered with an area Bs1of the second metal220in a cross-section of a main part of a guard ring portion.FIG.5Ashows a case where the percentage of the upper surface of the first metal219(area Ts1) that is covered with the second metal220(area Bs1) is small, andFIG.5Bshows a case where the percentage of the upper surface of the first metal219(area Ts1) that is covered with the second metal220(area Bs1) is large. FIG.6is a characteristic diagram showing a relation between a corrosion amount of the first metal219and the percentage of the upper surface of the first metal219(area Ts1) that is covered with the second metal220(area Bs1). Under a hot and humid condition, bromine ions (Br−), chlorine ions (Cl−), fluorine ions (F−) or the like remaining in a package or in a wafer processing step dissolve in moisture, and these halogen components move to a + potential side of the chip termination guard ring region102, which may cause a leak path or corrosion. In addition, the dissimilar metals become local batteries, thereby accelerating the corrosion. According to the examination of the inventors of the present application, it was found that the corrosion of the first metal219can be prevented when the percentage of the upper surface of the first metal219(area Ts1) that is covered with the second metal220(area Bs1) is 90% or more, as shown inFIG.6. InFIG.5, Bs1is defined in a part excluding the contact203, but inFIG.5, the contact203is continuously formed in a depth direction of a page surface, even if a broken portion exists in the contact203, the portion is about 1% of the whole, and thus a calculation result shown inFIG.6is within an error range. FIGS.7A to7Fare diagrams showing a manufacturing process of the IGBT semiconductor chip101according to Embodiment 1 (FIG.2). FIG.7AFormation of P-Well First, an n-semiconductor substrate209(for example, a semiconductor wafer such as a Si wafer) is prepared. Next, an insulating film (for example, a SiO2film) is formed on the main surface (front surface) of the n-semiconductor substrate209, a photoresist is applied on the insulating film, and then the photoresist is patterned for forming a P-well301by photolithography. Next, the patterned photoresist is used as a mask, p type impurities (for example, boron) are implanted into the n-semiconductor substrate209by ion implantation, the photoresist is removed, and then the p type impurities are diffused by annealing to form the P-well301. The P-well301configures the second conductive type (p type) guard ring215in the chip termination guard ring region102, and constitutes a p type layer for potential stabilization under the polysilicon gate wiring214in the active region103. FIG.7BFormation of Trench Gate Next, an insulating film (for example, a SiO2film) is formed on the main surface (front surface) of the n-semiconductor substrate209, a photoresist is applied on the insulating film, and then the photoresist is patterned for forming the field oxide film222by photolithography. After the photoresist is removed, the patterned insulating film is used as a mask, and a thermal oxidation treatment is performed on the main surface (surface) of the n-semiconductor substrate209to selectively form the field oxide film222on the main surface (surface) of the n-semiconductor substrate209. After the patterned insulating film is removed, an insulating film (for example, a SiO2film) is formed on the main surface (front surface) of the n-semiconductor substrate209, a photoresist is applied on the insulating film, and then the photoresist and the insulating film are patterned for forming a trench by photolithography. After the photoresist is removed, a trench is formed by anisotropic etching using the patterned insulating film as a mask. Next, the gate insulating film208is formed in the trench, then a polysilicon film is deposited so as to be embedded in the trench, and the trench gate207and the polysilicon gate wiring214are processed and formed by photolithography. FIG.7CFormation of P Base Layer, N+ Source Layer, Channel Stopper Next, a photoresist patterned for forming the p base layer206is used as a mask, p type impurities are ion-implanted and further a heat treatment is performed so as to form the p base layer206. Subsequently, a photoresist patterned for forming the n+ source layer204and the first conductive type (n type) channel stopper216is used as a mask, n type impurities are ion-implanted so as to form the n+ source layer204and the first conductive type (n type) channel stopper216. FIG.7DFormation of Contact Next, the interlayer insulating film202is deposited on the main surface (front surface) of the n-semiconductor substrate209, and the interlayer insulating film202is flattened. For flattening, for example, reflow of Boron-Phosphors Silicate Glass (BPSG) film or flattening methods such as Chemical Mechanical Polishing (CMP) is applied. Contact holes are formed by photolithography and anisotropic etching after the interlayer insulating film202is flattened. At this time, the contact holes penetrate the interlayer insulating film202and further reach the p base layer206, the P-well301, the polysilicon gate wiring214, and the first conductive type (n type) channel stopper216. As a result, when the p base layer206is viewed in cross-section, a pair of n+ source layers204are formed, and a groove portion in contact with a contact metal layer formed in the subsequent process is formed. Subsequently, the interlayer insulating film202in which the contact holes are formed is used as a mask, and p type impurities are ion-implanted so as to form the p+ layer205at a bottom of the contact holes. Next, a metal, such as Mo, TiW, TiN, Ti, Co, Ni, that serves as a barrier layer of the Al electrode and can react with Si to reduce resistance of a Si contact surface is formed into a film by, for example, sputtering, and annealed so as to form a silicide layer. Next, a metal film made of a high hardness and high melting point metal such as W is embedded in the contact holes, and further the metal film is etched or flattened by CMP so as to form the contact metal layer (contact203). At this time, a portion other than the contact holes is not removed even after the flattening of W, and remains on the interlayer insulating film202. Here, the metal serving as the barrier layer of the Al electrode is preferably a metal having a small potential difference with the standard potential of Al (−1.66 V) in order to prevent the galvanic reaction. For example, a standard potential of Ti is −1.63 V, a standard potential of Co is −0.277 V, a standard potential of Ni is −0.23 V, and a standard potential of Mo is −0.2 V. FIG.7EFormation of Electrode and Organic Passivation Film on Front Surface Thereafter, a metal layer containing aluminum (Al) as a main component is deposited, and the emitter electrode201which is the first metal layer, the second metal layer217, and the gate electrode213are formed by photolithography and etching. The aluminum is etched by anisotropic dry etching, and at the same time, the barrier layer is also processed and formed. As a result, the percentage of the area Ts1on the upper surface of the first metal219(for example, Ti), which is the barrier layer, that is covered with the area Bs1of the second metal220(Al) is large, the galvanic reaction can be prevented, and the corrosion of the barrier layer (first metal219) can be prevented. In addition, the ratio of the exposed surface area A of the first metal219(barrier layer: for example, Ti) to the exposed surface area B of the second metal220(Al) is decreased, and similarly, the galvanic reaction can be prevented, and the corrosion of the barrier layer (first metal219) can be prevented. Moreover, since the second metal layer217covers the surface of the second conductive type (p type) guard ring215, and the shielding effect against moisture or external electric charges such as ionic substances, and movable ions can be enhanced, a potential of the n-semiconductor substrate209during application of a high voltage is stabilized, the electric field is less likely to fluctuate, and a blocking voltage is stabilized. Thereafter, the organic passivation film221made of polyimide or the like is formed, and patterned so as to expose the emitter electrode201. The above stepsFIGS.7A to7Eare a front surface-side process of the n-semiconductor substrate209. FIG.7FFormation of N Buffer, P Collector Layer, Collector Electrode on Back Surface Next, the n-semiconductor substrate209is ground to a desired thickness from the back surface side thereof by back grinding. Thereafter, n type and p type impurities are ion-implanted into the n-semiconductor substrate209from the back surface side of the n-semiconductor substrate209, and laser annealing is further performed so as to form the n type buffer layer210and the p type collector layer211. By appropriately adjusting acceleration energy at the time of ion implantation, the n type buffer layer210and the p type collector layer211having different depths from the back surface of the n semiconductor substrate209can be formed. Thereafter, a laminated metal layer, for example, Al—Ti—Ni—Au is formed by sputtering on the back surface side of the n-semiconductor substrate209so as to form the collector electrode212. In the semiconductor device of the present embodiment, the second metal layer217covers the surface of the second conductive type (p type) guard ring215, and the shielding effect against moisture or external electric charges such as ionic substances, and movable ions can be enhanced. Therefore, the potential of the n-semiconductor substrate209during the application of the high voltage is stabilized, the electric field is less likely to fluctuate, and the blocking voltage can be stabilized. In addition, the second metal layer217has a laminated structure of dissimilar metals, the laminated structure of dissimilar metals is formed such that the first metal219is in contact with the second conductive type (p type) guard ring215, and the second metal220having a lower standard potential than the first metal219is in contact with the first metal219, 90% or more of the area of the upper portion of the first metal219is covered with the second metal220, and the percentage of the area Ts1on the upper surface of the first metal219(barrier Layer, for example, Ti) that is covered with the area Bs1of the second metal220(Al) is large, so that the galvanic reaction can be prevented, and the corrosion of the barrier layer (first metal219) can be prevented. In addition, the ratio of the exposed surface area A of the first metal219(barrier layer: for example, Ti) to the exposed surface area B of the second metal220(Al) is decreased, and similarly, the galvanic reaction can be prevented, and the corrosion of the barrier layer (first metal219) can be prevented. In addition, the chip termination guard ring region102is covered with the organic passivation film221, and the surface is mechanically protected and is protected against moisture or external electric charges such as ionic substances, and movable ions. As described above, the semiconductor device according to the present embodiment includes the active region103formed on the main surface of the n-semiconductor substrate209and the chip termination guard ring region102formed on the main surface of the n-semiconductor substrate209so as to surround the active region103. The chip termination guard ring region102includes the second conductive type (p type) guard rings215formed on the n-semiconductor substrate209, the interlayer insulating film202formed on the n-semiconductor substrate209so as to cover the second conductive type (p type) guard rings215, the field plates (second metal layers217) disposed on the interlayer insulating film202and electrically connected to the second conductive type (p type) guard rings215via the contacts203penetrating the interlayer insulating film202, and an organic passivation film (protective film)221covering the field plates (second metal layers217). The field plate (second metal layer217) has a laminated structure including the first metal219in contact with the second conductive type (p type) guard ring215and the second metal220which is disposed in contact with the first metal219and has a lower standard potential than the first metal219. The ratio of the contact area of the first metal219with the organic passivation film (protective film)221to the contact area of the second metal220with the organic passivation film (protective film)221is 0.05 or less. In addition, 90% or more of the area of the upper surface of the first metal219is covered with the second metal220. In addition, the chip termination guard ring region102includes the first conductive type (n type) channel stopper216formed on the n-semiconductor substrate209so as to surround the second conductive type (p type) guard rings215. Therefore, it is possible to provide a highly reliable semiconductor device that prevents the corrosion of the metal layer connected to the guard ring under a hot and humid environment, and prevents the withstand voltage deterioration and the leakage current increase during a long-term operation under a hot and humid environment and a power conversion device using the semiconductor device. It is more desirable that almost all (about 100%) of the upper surface of the first metal219is covered with the second metal220, and the ends of the first metal219and the ends of the second metal220are aligned when the field plate (second metal layer217) is viewed in cross section. Accordingly, galvanic corrosion of the field plate (second metal layer217) can be prevented. In addition, it is preferable that both ends of the field plate (second metal layer217) protrude from both ends of the second conductive type (p type) guard ring215when the IGBT semiconductor chip101is viewed in cross-section. This is because the electric field relaxation effect of the field plate (second metal layer217) at the end of the chip can be enhanced. Moreover, in the present embodiment (FIG.2), an example is shown in which a plurality of second conductive type (p type) guard rings215are formed on the n-semiconductor substrate209, and the plurality of second conductive type (p type) guard rings215are respectively connected to a plurality of field plates (second metal layer217) via a plurality of contacts203, but the number of combinations of the second conductive type (p type) guard ring215and the field plate (second metal layer217) is not limited thereto. For example, a case may be configured such that the second conductive type (p type) guard ring215and the field plate (second metal layer217) are formed in a one-to-one manner in the chip termination guard ring region102, or a case may be configured such that a plurality of second conductive type (p type) guard rings215are formed on the n-semiconductor substrate209, and are connected, via a plurality of contacts203, to one field plate (second metal layer217) having an area large enough to cover all of the plurality of second conductive type (p type) guard rings215. In either case, galvanic corrosion of the field plate (second metal layer217) can be prevented by configuring the area of the first metal219and the area of the second metal220constituting the field plate (second metal layer217) as described above. Embodiment 2 A semiconductor device according to Embodiment 2 of the invention will be described with reference toFIG.8.FIG.8is a cross-sectional view of the IGBT semiconductor chip101according to Embodiment 2, and corresponds to a modification of Embodiment 1 (FIG.2). The present embodiment is different from Embodiment 1 in that the chip termination guard ring region102according to Embodiment 1 (FIG.2) is covered with the organic passivation film221which is a protective film, whereas the chip termination guard ring region102according to the present embodiment (FIG.8) is covered with an inorganic passivation film801. Other configurations are the same as those in Embodiment 1 (FIG.2). Since the organic passivation film221is hygroscopic and has a small effect of preventing the diffusion of moisture or ionic substances, the inorganic passivation film801such as SiN, SiON, SiO2is used as the protective film of the chip termination guard ring region102, and thus the invasion of moisture and the diffusion of ionic substances can be prevented. Since the semiconductor device according to the present embodiment can further prevent the invasion of moisture or ionic substances as compared with Embodiment 1, it is possible to provide a more highly reliable semiconductor device that prevents the corrosion of the metal layer connected to the guard ring under a hot and humid environment, and prevents the withstand voltage deterioration and the leakage current increase during a long-term operation under a hot and humid environment and a power conversion device using the semiconductor device. Embodiment 3 A semiconductor device according to Embodiment 3 of the invention will be described with reference toFIG.9.FIG.9is a cross-sectional view of the IGBT semiconductor chip101according to the present embodiment, and corresponds to a modification of Embodiment 1 (FIG.2) or Embodiment 2 (FIG.8). The chip termination guard ring region102according to the present embodiment is covered with a laminated film of the inorganic passivation film801and the organic passivation film221, which is different from Embodiments 1 and 2. Other configurations are the same as in those Embodiment 1 and Embodiment 2. The inorganic passivation film801is formed on the second metal layer217. The passivation film has a function of protecting the surface mechanically and protecting the surface against moisture or external electric charges such as ionic substances, and movable ions. Thickening the passivation film is effective for mechanical surface protection. However, the surface of the second metal layer217is uneven, and when the film is thickened, cracks may occur due to stress during film formation in a case where, for example, SiN is adopted as the inorganic passivation film801. Since the cracks serve as an intrusion route of the moisture or ionic substances, the withstand voltage against external electric charges deteriorates and the leakage current increases, leading to corrosion of the barrier layer (first metal219). Therefore, in the present embodiment, it is possible to provide a highly reliable semiconductor device in which the second metal layer217is covered with a laminated film of the inorganic passivation film801and the organic passivation film221, the occurrence of cracks is prevented by thinning the inorganic passivation film801, the invasion of moisture or ionic substances can be prevented while showing a mechanical surface protection effect, further the corrosion of the metal layer connected to the guard ring under a hot and humid environment is prevented, and the withstand voltage deterioration and the leakage current increase during a long-term operation in a hot and humid environment is prevented, and a power conversion device using the semiconductor device. Embodiment 4 An example of an embodiment in which the semiconductor device of the invention is applied to a power conversion device will be described with reference toFIG.10.FIG.10is a circuit block diagram showing a power conversion device600that employs the semiconductor device according to any one of Embodiments 1 to 3 of the invention as components.FIG.10shows a circuit configuration of the power conversion device600according to the present embodiment, and a relation of connection between the DC power supply and a three-phase AC motor (AC load). In the power conversion device600according to the present embodiment, the semiconductor device according to any one of Embodiments 1 to 3 is used for power switching elements601to606. The power switching elements601to606are, for example, IGBTs. As shown inFIG.10, the power conversion device600according to the present embodiment includes a P terminal631and an N terminal632which are a pair of DC terminals, and a U terminal633, a V terminal634, and a W terminal635which are AC terminals of the same number as the number of phases of AC output. In addition, a switching leg is provided in which a pair of power switching elements601and602are connected in series and the U terminal633connected to a series connection point of the power switching elements601and602is set as an output. A switching leg having a similar configuration is provided in which the power switching elements603and604are connected in series and the V terminal634connected to a series connection point of the power switching elements603and604is set as an output. A switching leg having a similar configuration is provided in which the power switching elements605and606are connected in series and the W terminal635connected to a series connection point of the power switching elements605and606is set as an output. The three-phase switching legs including the power switching elements601to606are connected between the DC terminals of the P terminal631and the N terminal632, and is supplied with DC power from a DC power supply (not shown). The U terminal633, V terminal634, and W terminal635, which are three-phase AC terminals of the power conversion device600, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply. Diodes621to626are connected in antiparallel to the power switching elements601to606respectively. Gate input terminals of the power switching elements601to606implemented by the IGBTs are respectively connected to gate drive circuits611to616, and are respectively driven and controlled by the gate drive circuits611to616. That is, the power conversion device600according to the present embodiment is a power conversion device that receives DC power from the outside, converts the received DC power into AC power, and outputs the AC power. The power conversion device600includes a pair of DC terminals631,632for receiving DC power, and the AC terminals633to635that are AC terminals for outputting AC power and that have the same number as the number of AC phases of the AC power. For each of the AC terminals633to635of the number corresponding to the number of phases, between one terminal (p terminal631) and the other terminal (n terminal632) of the pair of DC terminals631,632, a series circuit (for example, a series circuit of a parallel circuit of the power switching element601and the diode621and a parallel circuit of the power switching element602and the diode622) is connected which is configured by connecting, in series, two parallel circuits (for example, a parallel circuit of the power switching element601and the diode621) in each of which a switching element (for example, power switching element601) and a diode (for example, diode621) having polarity reverse to that of the switching element are connected in parallel, and an interconnection point of the two parallel circuits configuring the series circuit is configured to be connected to the AC terminal (for example, U terminal633) of the phase (for example, U phase) corresponding to the series circuit. As in the present embodiment, the reliability of the power conversion device can be improved and the service life of the power conversion device can be elongated by applying the IGBT semiconductor chip101described in any one of Embodiments 1 to 3 to the power switching element of the power conversion device. The invention is not limited to the embodiments described above and includes various modifications. For example, the above embodiments have been described in detail for easy understanding of the invention, and are not necessarily limited to those including all the configurations described above. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of one embodiment can also be added to the configuration of another embodiment. In addition, other configurations may be added to, deleted from, or replaced with a part of the configuration of each embodiment. | 30,343 |
11942513 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately,” or “about” generally means within a value or range which can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately,” or “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately,” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. Referring toFIG.1AandFIG.1B,FIG.1Ais a schematic drawing illustrating a cross sectional view of a semiconductor structure, germanium concentration distribution thereof, and an inter-diffusion area of a silicon layer,FIG.1Bis a schematic drawing illustrating a cross sectional view of a semiconductor structure, germanium concentration distribution thereof, and an inter-diffusion area of a silicon layer, according to some comparative embodiments. In fabricating a gate-all-around transistor structure composed of Si and SiGe stacks, germanium concentration in the SiGe layer is pivotal to the etching selectivity between the SiGe layer and Si layer in the stack. In some embodiments, the etching operation imposes a greater etching rate to the silicon germanium layer with higher germanium concentration comparing to the silicon germanium layer with lower germanium concentration. One of the etching operation to the Si and SiGe stacks is associated with a lateral etch of the SiGe layer in order to form a side recess to accommodate an inner spacer. However, as shown inFIG.1A, when depositing a SiGe layer2H* with a high germanium concentration between two adjacent Si layers1*, Si layer undesirably suffers from greater loss due to high inter-diffusion between Si layer1* and the SiGe layer2H* contacts thereto. On the other hand, as shown inFIG.1B, when depositing a SiGe layer2L* with a lower germanium concentration between two adjacent Si layers1*, the SiGe layer2L* may not be effectively removed during etching operation due to low etching selectivity. In some cases, it is observed that the SiGe layer2L* is barely etched due to low etching selectivity. The present disclosure provides a semiconductor structure and a method for forming semiconductor structure. Specifically, in order to effectively remove at least a portion of a SiGe layer between two Si layers (so the entire SiGe layer can be effectively removed in subsequent operations before forming gate material) while alleviating material loss to the Si layer under such etching operation, as will be subsequently discussed inFIG.2AtoFIG.2B, a SiGe stack2is utilized to control the etching rate distribution thereof. Referring toFIG.2AandFIG.2B,FIG.2Ais a schematic drawing illustrating a cross sectional view of a semiconductor structure,FIG.2Bis a schematic drawing illustrating a cross sectional view of a semiconductor structure, according to some embodiments of the present disclosure. A SiGe stack2is disposed between a first silicon layer1aand a second silicon layer1b, wherein the SiGe stack2includes a silicon germanium layer2H having a higher germanium concentration, and a silicon germanium layer2L having a lower germanium concentration. Specifically, the SiGe stack2includes a first silicon germanium layer2LA over the first silicon layer1a, a second silicon germanium layer2H over the first silicon germanium layer2LA, and a third silicon germanium layer2LB over the second silicon germanium layer2H, wherein the second silicon layer1bis above the third silicon germanium layer2LB. Herein the first silicon germanium layer2LA has a first germanium concentration, the second silicon germanium layer2H has a second germanium concentration, and the third silicon germanium layer2LB has a third germanium concentration, wherein the second germanium concentration is greater than the first germanium concentration, and the third germanium concentration is less than the second germanium concentration. Alternatively stated, the portion having greater germanium concentration among the SiGe stack2is proximal to the middle of the SiGe stack2, and silicon germanium layers2L having lower germanium concentration proximal to the silicon layers1. In some embodiments, the first germanium concentration is in a range from about 15% to about 25%. In some embodiments, the second germanium concentration (atomic concentration) is in a range from about 30% to about 45%. In some embodiments, the third germanium concentration is in a range from about 15% to about 25%. As previously discussed inFIG.1AandFIG.1B, germanium concentration in the SiGe layer is pivotal to the etching selectivity between the SiGe layer and Si layer in the stack. In some embodiments, the etching operation imposes a greater etching rate to the silicon germanium layer with higher germanium concentration comparing to the silicon germanium layer with lower germanium concentration. That is, under the etching operation, the etching rate to the second silicon germanium layer2H is greater than either the first silicon germanium layer2LA or the third silicon germanium layer2LB. When laterally removing a portion of the SiGe stack2, a lateral depth LD2of removed portion in the second silicon germanium layer2H is greater than a lateral depth LD1of removed portion in the first silicon germanium layer2LA and the third silicon germanium layer2LB. Thereby, it is relative easier to remove the remaining second silicon germanium layer2H in subsequent operation (which will subsequently be discussed inFIG.17AandFIG.17B), while alleviating the material loss of the silicon layer1. Furthermore, in order to further facilitate the etching performance, the thickness and/or the germanium concentration of each of the first silicon germanium layer2LA, the second silicon germanium layer2H, and the third silicon germanium layer2LB can be adjusted. In some embodiments, a thickness T2of the second silicon germanium layer2H is greater than either a thickness T1of the first silicon germanium layer2LA or a thickness T3of the third silicon germanium layer2LB. For example, the thickness T2of the second silicon germanium layer2H may be in a range from about 2.5 nm to about 6.0 nm, and the thickness T1of the first silicon germanium layer2LA and the thickness T3of the third silicon germanium layer2LB may be in a range from about 1.0 nm to about 2.0 nm. For another example, a germanium concentration (atomic percentage) of the second silicon germanium layer2H may be in a range from about 30% to about 45%, a germanium concentration of the first silicon germanium layer2LA and a germanium concentration (atomic percentage) of the third silicon germanium layer2LB may be in a range from about 15% to about 25%. It is appreciated, however, that the values recited throughout the description are examples, and may be changed to different values. The above SiGe stack2can be used in the semiconductor fabrication operations as subsequently discussed inFIG.3AtoFIG.18E. It should be noted that similar fabrication operations may also be applied to semiconductor structures having different materials (e.g. other than Si—SiGe stack), wherein etching rate is found to be related to inter-diffusion between two different materials. For example, a sacrificial layer is disposed between a first semiconductor layer and a second semiconductor layer, wherein the sacrificial layer may include a stack having an etch rate profile under a certain etching operation similar toFIG.2B. Referring toFIG.3A,FIG.3Ashows a flow chart representing a method for fabricating a semiconductor structure, in accordance with some embodiments of the present disclosure. The method1000for fabricating a semiconductor structure includes forming a first silicon layer over a substrate (operation1004, which can be referred toFIG.5), forming a first silicon germanium layer over the first silicon layer (operation1007, which can be referred toFIG.5), forming a second silicon germanium layer over the first silicon germanium layer (operation1013, which can be referred toFIG.5), forming a third silicon germanium layer over the second silicon germanium layer (operation1018, which can be referred toFIG.5), forming a second silicon layer over the third silicon germanium layer (operation1022, which can be referred toFIG.5), and partially removing the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer from a lateral side by an etching operation (operation1026, which can be referred toFIG.11AandFIG.11B). Referring toFIG.3B,FIG.3Bshows a flow chart representing a method for fabricating a semiconductor structure, in accordance with some embodiments of the present disclosure. The method2000for fabricating a semiconductor structure includes forming a first silicon layer over a substrate (operation2004, which can be referred toFIG.5), forming a first silicon germanium layer over the first silicon layer (operation2007, which can be referred toFIG.5), forming a second silicon germanium layer over the first silicon germanium layer (operation2013, which can be referred toFIG.5), forming a third silicon germanium layer over the second silicon germanium layer (operation2018, which can be referred toFIG.5), forming a second silicon layer over the third silicon germanium layer (operation2022, which can be referred toFIG.5), partially removing the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer from a lateral side by an etching operation (operation2026, which can be referred toFIG.11AandFIG.11B), forming a spacer over a sidewall of first silicon germanium layer, a sidewall of the second silicon germanium layer, a sidewall of the first silicon germanium layer, a sidewall of the second silicon germanium layer, and a sidewall of the third silicon germanium layer (operation2030, which can be referred toFIG.12), removing a portion of the spacer to expose the sidewall of the first silicon layer and the sidewall of the second silicon layer (operation2034, which can be referred toFIG.13), forming a source/drain region laterally surrounding the first silicon layer, the second silicon layer, the first silicon germanium layer, the second silicon germanium layer, the third silicon germanium layer, and the spacer (operation2042, which can be referred toFIG.14), removing the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer (operation2058, which can be referred toFIG.17AandFIG.17B), and forming metal gate material between the first silicon layer and the second silicon layer (operation2062, which can be referred toFIG.18AandFIG.18B). Referring toFIG.4,FIG.4is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A substrate1′ is provided. The substrate1′ may be a semiconductor substrate, such as a silicon substrate, a silicon-on-insulator substrate, or other suitable substrate. The substrate1′ may optionally be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation can optionally be performed. In some embodiments, well regions can be formed in the substrate1′ by implantation operation. Referring toFIG.5,FIG.5is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A semiconductor stack1S is formed above a front side FS of the substrate1′. The semiconductor stack1S includes silicon layers1and SiGe stacks2, wherein the silicon layers1and SiGe stacks2can be stacked alternatively. Specifically, a first SiGe stack2ais formed above the front side FS of the substrate1′, a first silicon layer1ais formed above the first SiGe stack2a, a second SiGe stack2bis formed above the first silicon layer1a, a second silicon layer1bis formed above the second SiGe stack2b. In some embodiments, the stack can further be repeated. For example, a third SiGe stack2cis formed above the second silicon layer1b, a third silicon layer1cis formed above the third SiGe stack2c, and so on. The numbers of the silicon layer1and the SiGe stack2in the semiconductor stack1S are not limited in the present disclosure. As previously discussed inFIG.2AtoFIG.2B, the SiGe stack2(herein using the second SiGe stack2bas an example) includes a first silicon germanium layer2LA formed over the first silicon layer1a, a second silicon germanium layer2H formed over the first silicon germanium layer2LA, and a third silicon germanium layer2LB formed over the second silicon germanium layer2H, wherein the second silicon layer1bis above the third silicon germanium layer2LB. Herein the first silicon germanium layer2LA has a first germanium concentration, the second silicon germanium layer2H has a second germanium concentration, and the third silicon germanium layer2LB has a third germanium concentration, wherein the second germanium concentration is greater than the first germanium concentration, and the third germanium concentration is less than the second germanium concentration. Herein each of the SiGe stack2can be formed through epitaxial formation operation, or other suitable operations. Furthermore, in some embodiments, the thickness T2of the second silicon germanium layer2H may be in a range from about 2.5 nm to about 6.0 nm, and the thickness T1of the first silicon germanium layer2LA and the thickness T3of the third silicon germanium layer2LB may be in a range from about 1.0 nm to about 2.0 nm. In some embodiments, a germanium concentration (atomic percentage) of the second silicon germanium layer2H may be in a range from about 30% to about 45%, a germanium concentration of the first silicon germanium layer2LA and a germanium concentration (atomic percentage) of the third silicon germanium layer2LB may be in a range from about 15% to about 25%. It is appreciated, however, that the values recited throughout the description are examples, and may be changed to different values. Referring toFIG.6,FIG.6is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A mask12is formed over the semiconductor stack1S. The mask12can be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbo-nitride, or the like. Subsequently, the semiconductor stack1S, including the silicon layer1and the SiGe stack2, and a portion of the substrate1′ is patterned, thereby trenches19extending into the substrate1′ are formed. The mask12is subsequently removed. Optionally, an oxide layer11can be formed between the mask12and the semiconductor stack1S. The remaining portions of the semiconductor stack1S over the substrate1′ are hereinafter referred to as semiconductor strip1S′. Referring toFIG.7,FIG.7is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. Isolation regions21, which can be shallow trench isolation regions, can be formed in the trenches19. The formation of the isolation regions21may include filling the trenches19with a dielectric layer using Flowable Chemical Vapor Deposition (FCVD, or other suitable deposition operations), and performing a chemical mechanical planarization (CMP) operation to level at a top surface of the mask12. Subsequently the isolation regions21can be recessed, thereby a sidewall of the semiconductor strip1S′ is exposed from the material of the isolation regions21. It should be noted that the isolation regions21may also be formed with other suitable operations. A dummy oxide layer22is subsequently formed over the top surface and the sidewall of the semiconductor strip1S′. The dummy oxide layer22may optionally extend over the top surface of the isolation regions21. In some embodiments, the dummy oxide layer22may include silicon oxide. In some embodiments, a material of the dummy oxide layer22may be identical with a material of the isolation regions21and/or the oxide layer11over the semiconductor strip1S′. Therefore in some of the embodiments, the interfaces between the dummy oxide layer22, the isolation regions21and/or the oxide layer11may not be distinguishable. In some alternative embodiments, those interfaces may be distinguishable. Referring toFIG.8,FIG.8is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. In some embodiments, a dummy gate stack30is formed over the semiconductor strip1S′ and the dummy oxide layer22. In some embodiments, the dummy gate stack30may have a lengthwise direction orthogonal to a lengthwise direction of the semiconductor strip1S′. The dummy gate stack30includes a dummy gate electrode31over the dummy oxide layer22, wherein the dummy gate electrode31may include polysilicon or other suitable material that can be used as a sacrificial layer. The dummy gate stack30may further include a hard mask layer30*. In some of the embodiments, the hard mask layer30* may be a single layer (such as silicon nitride layer or silicon oxide layer), or alternatively, a composition of plurality of layers. For example, the hard mask layer30* includes a silicon nitride layer32and a silicon oxide layer33over the silicon nitride layer32. Referring toFIG.9,FIG.9is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A gate spacer40is formed over the top surface and on the sidewall of the dummy gate stack30. In some embodiments, the gate spacer40has a single layer structure, which may include silicon nitride, silicon oxide, or other similar materials which can be used as a protection spacer. Alternatively in some embodiments, as shown in the example provided inFIG.9, the gate spacer40has a composite structure including a plurality of layers. For example, the gate spacer40may include a silicon oxide layer41, and a silicon nitride layer42over the silicon oxide layer41. Referring toFIG.10,FIG.10is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. An etching operation is performed to remove a portion of the gate spacer40, a portion of the semiconductor strip1S′ and/or a portion of the substrate1′. As a result, the etching stops at the hard mask layer30* (for example, the silicon oxide layer33is exposed from the gate spacer40), and a recess5R is formed between adjacent semiconductor strips1S′. Referring toFIG.11A,FIG.11Ais a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. The SiGe stacks2are partially and laterally removed. Specifically, the first silicon germanium layer2LA, the second silicon germanium layer2H, and the third silicon germanium layer2LB are partially removed from a lateral side by the etching operation, thereby a lateral recess6LR recessed from a sidewall of the SiGe stacks2is formed. A lower surface and a top surface of each of the silicon layers1is exposed after the etching operation. A portion of the substrate1′ may further be exposed from the SiGe stack2after the etching operation. As previously discussed inFIG.1AtoFIG.2B, germanium concentration in the SiGe layer is pivotal to the etching selectivity between the SiGe layer and Si layer in the stack. Under such etching operation, the etching rate to the second silicon germanium layer2H is greater than either the first silicon germanium layer2LA or the third silicon germanium layer2LB. As a result, a profile of the lateral recess6LR as well as a profile of a surface of the silicon layer1reflects the distribution of the etching rate. The profiles will be subsequently discussed inFIG.11AtoFIG.11D. Referring toFIG.11A,FIG.11B,FIG.11C, andFIG.11D,FIG.11Bis an enlarged cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations,FIG.11Cis a schematic diagram showing a profile of a surface of a semiconductor layer,FIG.11Dis a schematic diagram showing a relationship between a position on a surface of a semiconductor layer and an absolute value of a derivative thereat, according to some embodiments of the present disclosure. As a result of the distribution of the etching rate at the exposed lateral sidewall of the SiGe stack2, a top surface of the substrate1′, a bottom surface of the silicon layer1(which may include the first silicon layer1a, the second silicon layer1b, and/or the third silicon layer1c) of the semiconductor strip1S′, and/or a top surface of the silicon layer1may have a unique profile. Specifically, since the inter-diffusion of germanium proximal to the interface at the surfaces of the silicon layer1are alleviated with the configuration of the first silicon germanium layer2LA as well as the third silicon germanium layer2LB, instead of having the silicon layer1being in direct contact with the second silicon germanium layer2H having a higher germanium concentration, an etching rate at a position proximal to the interface between the silicon layer1and the SiGe stack2is relatively lower than an etching rate at a position at an exposed surface of the second silicon germanium layer2H. Therefore, it can be observed that the lateral recess6LR has a necking structure, that is, having an intermediate section between a wider portion proximal to the sidewall of the silicon layer1and a narrower portion distal to the sidewall of the silicon layer1. Alternatively stated, herein using a lower surface1bL of the second silicon layer1bas an example (same surface profile may be observed on other silicon layers1as well), the lower surface1bL of the second silicon layer1bhas a first section P1proximal to an outer sidewall of the second silicon layer1b(after forming an S/D region81, as will be discussed inFIG.14, the first section P1is proximal to the S/D region81), a second section P2proximal to the remaining SiGe stack2(after forming a gate material93between the first silicon layer1aand the second silicon layer1b, as will be discussed inFIG.18AtoFIG.18B, the second section P2is proximal to the gate material93), and a third section P3between the first section P1and the second section P2. The profile of the lower surface1bL of the second silicon layer1band the position of the first section P1, the second section P2, and the third section P3can be referred toFIG.11BandFIG.11C. As shown inFIG.11D, the feature of the profile of the lower surface1bL of the second silicon layer1bcan further be represented by an absolute value of a first derivative derived from the surface profile in theFIG.11C, that is, each value in the diagram of theFIG.11Drepresents a local slope value of the correspond position at the lower surface1bL of the second silicon layer1b. It should be noted that a necking portion can be identified as having a greater local slope value comparing with other section. In some embodiments, the third section P3is at the necking portion, thus the absolute value of a derivative (absolute value of local slope value) at the third section P3is greater than either the absolute value of a derivative (absolute value of local slope value) at the first section P1or at the second section P2. Specifically, an absolute value of a derivative at the third section P3is in a range from about 0.3 to about 2.0, and the absolute values of a derivative at the first section P1and at the second section P2are both less than the absolute value of a derivative at the third section P3. In some embodiments, the absolute value of a derivative at the first section P1is less than 0.3. In some embodiments, the absolute value of a derivative at the second section P2is less than 0.3. It should be noted that similar profile can also be found on other lower surfaces of the silicon layers1, such as (hut not limited to) the first silicon layer1aand/or the third silicon layer1c, or the like. It should also be noted that in the present disclosure, the absolute value of a derivative (or an absolute value of a local slope value) can be represented as |dy/dx|, wherein the direction x and y are shown inFIG.11AandFIG.11B. In some embodiments, a similar profile can also be observed on an upper surface1aU of the first silicon layer1a, wherein the upper surface1aU of the first silicon layer1ahas a fourth section P4proximal to an outer sidewall of the first silicon layer1b(after forming an S/D region81, as will be discussed inFIG.14, the fourth section P4is proximal to the S/D region81), a fifth section P5proximal to the remaining SiGe stack2(after forming a gate material93between the first silicon layer1aand the second silicon layer1b, as will be discussed inFIG.18AtoFIG.18B, the fifth section P5is proximal to the gate material93), and a sixth section P6between the fourth section P4and the fifth section P5. The profile of the upper surface1aU of the first silicon layer1aand the position of the fourth section P4, the fifth section P5, and the sixth section P6can be referred toFIG.11BandFIG.11C. Similarly, the sixth section P6is at the necking section, thus the absolute value of a derivative (absolute value of local slope value) at the sixth section P6is greater than either the absolute value of a derivative (absolute value of local slope value) at the fourth section P4or at the fifth section P5. Specifically, an absolute value of a derivative at the sixth section P6is in a range from about 0.3 to about 2.0, and the absolute values of a derivative at the fourth section P4and at the fifth section P5are both less than the absolute value of a derivative at the sixth section P6. In some embodiments, the absolute value of a derivative at the fourth section P4is less than 0.3. In some embodiments, the absolute value of a derivative at the fifth section P5is less than 0.3. It should be noted that similar profile can also be found on other upper surfaces of the silicon layers1or the substrate1′, such as (but not limited to) the second silicon layer1band/or the third silicon layer1c, or the like. Referring toFIG.12,FIG.12is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A spacer71is formed to cover a sidewall of the silicon layers1(including sidewalls of the first silicon layer1a, the second silicon layer1b, and/or the third silicon layer1c, or the like), a sidewall of the SiGe stack2(including sidewalls of the first silicon germanium layer2LA, the second silicon germanium layer2H, and/or the third silicon germanium layer2LB, or the like), a sidewall of the gate spacer40and a top surface of the substrate1′, and may further cover the exposed surface of the dummy gate stack30(such as a top surface of the hard mask layer30*). Furthermore, the spacer71is filled in the lateral recesses6LR and conforms to the profile of the lateral recesses6LR. Referring toFIG.13,FIG.13is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A portion of the spacer71is removed by etching operation to expose the sidewall of the silicon layers1(including sidewalls of the first silicon layer1a, the second silicon layer1b, and/or the third silicon layer1c, or the like). A recess13R is thereby formed. Furthermore, an outer sidewall of the spacer71is recessed from the sidewall of the silicon layers1for enhancing the formation of S/D region81, as will be introduced inFIG.14. Referring toFIG.14,FIG.14is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. A source/drain (S/D) region81can be formed by growing a semiconductor material in the recess13R (shown inFIG.13), which may include performing epitaxial growth operations. After forming the S/D region81, the S/D region81is in direct contact with the outer sidewall of the spacer71and the outer sidewall of the silicon layers1. The S/D region81surrounds the silicon layers1(including the first silicon layer1a, the second silicon layer1b, and/or the third silicon layer1c, or the like), and the SiGe stack2(including the first silicon germanium layer2LA, the second silicon germanium layer2H, and/or the third silicon germanium layer2LB, or the like). As previously discussed inFIG.13, since the outer sidewall of the spacer71is recessed from the sidewall of the silicon layers1, a portion of the S/D region81extrudes toward the spacer71and is in direct contact with a portion of the upper surface and/or a portion of the lower surface of the silicon layers1(similar to the enlarged cross sectional view shown inFIG.18C). In some embodiments, a thickness TB (shown inFIG.18C) of the extrusion of the S/D region81is in a range from about 0.5 nm to about 2.0 nm to enhance the formation by providing additional spacing during epitaxial growth operation. Referring toFIG.15,FIG.15is a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. An inter-layer dielectric (ILD)80is formed over the S/D region81. A CMP operation is then performed to remove a portion of the ILD80, a portion of the gate spacer40, and a portion of the dummy gate stack30. Thereby a top surface of the gate spacer40, a top surface of ILD80and a top surface of the dummy gate electrode31are leveled. Referring toFIG.16AandFIG.16B,FIG.16AandFIG.16Bare cross sectional views of a semiconductor structure during intermediate stages of manufacturing operations, according to some embodiments of the present disclosure. HereinFIG.16Bis a schematic drawing illustrating a cross sectional view taken along line A-A′ ofFIG.16A. The dummy gate electrode31is then removed to expose the dummy oxide layer22. Herein the remaining dummy oxide layer22can be referred to as interfacial oxide layer. Referring toFIG.17AandFIG.17B,FIG.17Ais a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations,FIG.17Bis a schematic drawing illustrating a cross sectional view taken along line B-B′ ofFIG.17A, according to some embodiments of the present disclosure. The remaining SiGe stack2between the silicon layers1are removed by etching operation, thereby forming gaps between silicon layers1and a recess17R between the gate spacer40. Furthermore, the dummy oxide layer22is also removed. Referring toFIG.18AandFIG.18B,FIG.18Ais a cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations,FIG.18Bis a schematic drawing illustrating a cross sectional view taken along line C-C′ ofFIG.18A, according to some embodiments of the present disclosure. An interfacial layer91is formed on the exposed surfaces of the silicon layers1and an inner sidewall of the spacer71, a high-k dielectric layer92is formed on the interfacial layer91, an inner sidewall of the spacer71and/or on the inner sidewall of the recess17R, and a gate material93is filled into the gaps between the silicon layers1and/or in the recess17R. The gate material93may be a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, Cu, W, combination thereof, or the like. Thereby, a fin99protruding from the front surface of the substrate1′ is formed. From the cross section view as shown inFIG.18A, the gate material93is surrounded by the high-k dielectric layer92, and the high-k dielectric layer92is surrounded by the interfacial layer91. The spacer71may be in direct contact with the high-k dielectric layer92and/or the interfacial layer91, wherein the gate material93and the spacer71may be separated by the high-k dielectric layer92. From the cross section view as shown inFIG.18B, the silicon layer1is surrounded by the interfacial layer91, the interfacial layer91is surrounded by the high-k dielectric layer92, and the gate material93is formed between adjacent high-k dielectric layers92and above the silicon layers1. Hereinafter the interfacial layer91, the high-k dielectric layers92and the gate material93are collectively referred to as a gate90. Referring toFIG.18C,FIG.18D, andFIG.18E,FIG.18Cis an enlarged cross sectional view of a semiconductor structure during intermediate stages of manufacturing operations,FIG.18Dis a schematic diagram showing a profile of a surface of a spacer,FIG.18Eis a schematic diagram showing a relationship between a position on a surface of a spacer and an absolute value of a derivative thereat, according to some embodiments of the present disclosure. Since a surface of the spacer71conforms to the lateral recess6LR as shown inFIG.11AtoFIG.11B, the spacer71also has a necking portion between a wider portion proximal to the sidewall of the silicon layer1and a narrower portion proximal to the gate material93. The spacer71has an upper surface71U and a lower surface71L opposite to the upper surface71U. Using a spacer71between the first silicon layer1aand the second silicon layer1bas an example, the upper surface71U of the spacer71conforms to the lower surface1bL of the second silicon layer1b, and the lower surface71L of the spacer71conforms to the upper surface1aU of the first silicon layer1a. Herein the upper surface71U of the spacer71has a first section J1proximal to the S/D region81, a second section J2proximal to the gate material93of the gate90, and a third section J3between the first section J1and the second section J2. The profile of the l upper surface71U and the position of the first section J1, the second section J2, and the third section J3can be referred toFIG.18CandFIG.18D. As shown inFIG.18E, the feature of the profile of the upper surface71U of the spacer71can further be represented by an absolute value of a first derivative derived from the surface profile in theFIG.18D, that is, each value in the diagram of theFIG.18Erepresents a local slope value of the correspond position at the upper surface71U of the spacer71. In some embodiments, the third section J3is at the necking portion, thus the absolute value of a derivative (absolute value of local slope value) at the third section J3is greater than either the absolute value of a derivative (absolute value of local slope value) at the first section J1or at the second section J2. Specifically, an absolute value of a derivative at the third section J3is in a range from about 0.3 to about 2.0, and the absolute values of a derivative at the first section J1and at the second section J2are both less than the absolute value of a derivative at the third section J3. In some embodiments, the absolute value of a derivative at the first section J1is less than 0.3. In some embodiments, the absolute value of a derivative at the second section J2is less than 0.3. It should be noted that similar profile can also be found on other spacers71. In some embodiments, a similar profile can also be observed on the lower surface71L of the spacer71, wherein the lower surface71L of the spacer71has a fourth section J4proximal to the S/D region81, a fifth section J5proximal to the gate material93of the gate90, and a sixth section J6between the fourth section J4and the fifth section J5. The profile of the lower surface71L of the spacer71and the position of the fourth section J4, the fifth section J5, and the sixth section J6can be referred toFIG.18CandFIG.18D. Similarly, the sixth section P6is at the necking portion, thus the absolute value of a derivative (absolute value of local slope value) at the sixth section J6is greater than either the absolute value of a derivative (absolute value of local slope value) at the fourth section P4or at the fifth section J5. Specifically, an absolute value of a derivative at the sixth section J6is in a range from about 0.3 to about 2.0, and the absolute values of a derivative at the fourth section J4and at the fifth section J5are both less than the absolute value of a derivative at the sixth section J6. In some embodiments, the absolute value of a derivative at the fourth section J4is less than 0.3. In some embodiments, the absolute value of a derivative at the fifth section J5is less than 0.3. It should be noted that similar profile can also be found on other spacers71. The present disclosure provides a semiconductor structure and a method for forming semiconductor structure. Specifically, in order to effectively remove a SiGe layer between two silicon layers (in some embodiments the removal may include two or more etching operation, firstly partially remove at least a portion of the SiGe stack2, and subsequently remove the entire SiGe stack2) while alleviating material loss to the Si layer under etching operation, a SiGe stack2is utilized. In order to control the etching rate at an exposed surface of the SiGe stack2and a position proximal to an interface between the SiGe stack2and the silicon layer1, the SiGe stack2has the first silicon germanium layer2LA as well as the third silicon germanium layer2LB in direct contact with silicon layers1, instead of having the silicon layer1being in direct contact with the second silicon germanium layer2H having a higher germanium concentration, Thereby an etching rate at a position proximal to the interface between the silicon layer1and the SiGe stack2is relatively lower than an etching rate at a position at an exposed surface of the second silicon germanium layer2H. Furthermore, in order to support the structures of the silicon layers1after removing the remaining SiGe stack2, the spacer71is formed between the silicon layers1. Since the spacer71conforms to a profile of the lateral recess6LR as discussed inFIG.11AandFIG.11B, it can be observed that the spacer71as a unique profile that reflects the distribution of etching rate of the exposed surface of the SiGe stack2as well as a position proximal to an interface between the SiGe stack2and the silicon layer1. Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a front surface, a fin protruding from the front surface, the fin including: a first semiconductor layer in proximal to the front surface, a second semiconductor layer stacked over the first semiconductor layer, a gate between the first semiconductor layer and the second semiconductor layer, and a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region laterally surrounding the fin, wherein the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including: a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section, wherein an absolute value of a derivative at the third section is greater than an absolute value of a derivative at the second section. Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a front surface, a fin protruding from the front surface, the fin including: a first semiconductor layer in proximal to the front surface, a second semiconductor layer stacked over the first semiconductor layer, and a gate between the first semiconductor layer and the second semiconductor layer, and an source/drain (S/D) region laterally surrounding the fin, wherein a lower surface of the second semiconductor layer includes: a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section, wherein an absolute value of a derivative at the third section is in a range of from about 0.3 to about 2. Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, including forming a first silicon layer over a substrate, forming a first silicon germanium layer over the first silicon layer, wherein the first silicon germanium layer has a first germanium concentration, forming a second silicon germanium layer over the first silicon germanium layer, wherein the second silicon germanium layer has a second germanium concentration greater than the first germanium concentration, forming a third silicon germanium layer over the second silicon germanium layer, wherein the third silicon germanium layer has a third germanium concentration less than the second germanium concentration, forming a second silicon layer over the third silicon germanium layer, and partially removing the first silicon germanium layer, the second silicon germanium layer and the third silicon germanium layer from a lateral side by an etching operation. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other operations and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. | 45,590 |
11942514 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element or layer is referred to as being “connected to,” or “coupled to” another element or layer, it can be directly connected to or coupled to another element or layer or intervening elements or layers may be present. It should be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless indicated otherwise, these terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Unless the context indicates otherwise, terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to reflect this meaning. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes. In the present disclosure, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device. A semiconductor stack with a lower threshold voltage may have a faster switching speed and may be suitable for providing computational logic functions. In contrast, a semiconductor stack with a high threshold voltage may decrease power consumption of the semiconductor stack and may be suitable to implement in storage functions. Therefore, a semiconductor device with semiconductor stacks with multiple threshold voltages may have broader applicability than a semiconductor device with only a single threshold voltage. It should be noted that, in the description of the present disclosure, above (or up) corresponds to the direction of the arrow of the direction Z, and below (or down) corresponds to the opposite direction of the arrow of the direction Z. FIG.1illustrates, in a schematic cross-sectional view diagram, a semiconductor device100A in accordance with one embodiment of the present disclosure.FIG.2illustrates, in a schematic top-view diagram, the semiconductor device100A in accordance with one embodiment of the present disclosure. With reference toFIGS.1and2, in the embodiment depicted, the semiconductor device100A may include a substrate101, an isolation layer103, a plurality of doped regions, a plurality of spacers, a first semiconductor stack301, a second semiconductor stack401, and a third semiconductor stack501. With reference toFIGS.1and2, in the embodiment depicted, the substrate101may include an array area10and a peripheral area20. The array area10may be in the center of the substrate101. The peripheral area20may surround the array area10. The substrate101may be formed of, for example, silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenic, indium arsenic, indium phosphorus or other IV-IV, III-V or II-VI semiconductor materials. The substrate101may have a first lattice constant and a crystal orientation <100>. Alternatively, in another embodiment, the substrate101may include an organic semiconductor or a layered semiconductor such as silicon/silicon germanium, silicon-on-insulator or silicon germanium-on-insulator. When the substrate101is formed of silicon-on-insulator, the substrate101may include a top semiconductor layer and a bottom semiconductor layer formed of silicon, and a buried insulating layer that may separate the top semiconductor layer from the bottom semiconductor layer. The buried insulating layer may include, for example, a crystalline or non-crystalline oxide, nitride or any combination thereof. With reference toFIGS.1and2, in the embodiment depicted, the isolation layer103may be disposed in the substrate101. Specifically, the isolation layer103may be disposed in an upper portion of the substrate101. The isolation layer103may define a first active region105-1, a second active region105-2, and a third active region105-3separated from each other. The first active region105-1may be located at the array area10of the substrate101. The second active region105-2and the third active region105-3may be located at the peripheral area20of the substrate101. Alternatively, in another embodiment, the first active region105-1, the second active region105-2, and the third active region105-3may be all located at the array area10or all located at the peripheral area20, but are not limited thereto. Alternatively, in another embodiment, the first active region105-1, the second active region105-2, and the third active region105-3may be connected to each other. The isolation layer103may be formed of, for example, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. It should be noted that, in the present disclosure, silicon oxynitride refers to a substance which contains silicon, nitrogen, and oxygen and in which a proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance which contains silicon, oxygen, and nitrogen and in which a proportion of nitrogen is greater than that of oxygen. With reference toFIGS.1and2, in the embodiment depicted, the plurality of doped regions may be disposed in the substrate101and may include two first lightly-doped regions201-1, two second lightly-doped regions201-2, two third lightly-doped regions201-3, two first heavily-doped regions203-1, two second heavily-doped regions203-2, and two third heavily-doped regions203-3. The plurality of spacers may include a first pair of inner spacers207-1, a second pair of inner spacers207-2, and a third pair of inner spacers207-3. The plurality of spacers may be formed of, for example, silicon oxide, silicon nitride, polysilicon, or the like. With reference toFIGS.1and2, in the embodiment depicted, the first semiconductor stack301may be disposed on the first active region105-1. The first semiconductor stack301may have a first threshold voltage and may include a first insulating stack, a first bottom conductive layer309, a first filler layer313, and a first capping layer315. With reference toFIGS.1and2, in the embodiment depicted, the first insulating stack may be disposed on the first active region105-1and may include a first bottom insulating layer303. In other words, the first bottom insulating layer303may be disposed on the substrate101. The first bottom insulating layer303may have a thickness between about 0.5 nm and about 5.0 nm. Preferably, the thickness of the first bottom insulating layer303may be between about 0.5 nm and about 2.5 nm. It should be noted that the thickness of the first bottom insulating layer303may be set to an arbitrary range depending on the circumstances. The two first lightly-doped regions201-1may be respectively correspondingly disposed adjacent to two sides of the first bottom insulating layer303and in the substrate101. The two first lightly-doped regions201-1may be doped with a dopant such as phosphorus, arsenic, or antimony and have a first electrical type. The two first lightly-doped regions201-1may have a dopant concentration between about 1E14 atoms/cm{circumflex over ( )}3 and about 1E16 atoms/cm{circumflex over ( )}3. The first bottom insulating layer303may be formed of, for example, an insulating material having a dielectric constant of about 4.0 or greater. All dielectric constants mentioned herein are relative to a vacuum unless otherwise noted. The insulating material having a dielectric constant of about 4.0 or greater may be hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, aluminum oxide, aluminum silicon oxide, titanium oxide, tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium (III) trioxide, gadolinium gallium oxide, lead zirconium titanate, barium titanate, barium strontium titanate, barium zirconate, or a mixture thereof. Alternatively, in another embodiment, the insulating material may be silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. With reference toFIGS.1and2, in the embodiment depicted, the first bottom conductive layer309may be disposed on the first bottom insulating layer303. The first bottom conductive layer309may have a thickness between about 10 angstroms and about 200 angstroms. Preferably, the thickness of the first bottom conductive layer309may be between about 10 angstroms and about 100 angstroms. The first bottom conductive layer309may be formed of, for example, aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium, or tungsten nitride. The first filler layer313may be disposed on the first bottom conductive layer309. The first filler layer313may be formed of, for example, tungsten or aluminum. The first capping layer315may be disposed on the first filler layer313and may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. With reference toFIGS.1and2, in the embodiment depicted, the first pair of inner spacers207-1may be respectively correspondingly attached to two sides of the first semiconductor stack301. Specifically, the first pair of inner spacers207-1may be respectively correspondingly attached to sidewalls of the first capping layer315, sidewalls of the first filler layer313, sidewalls of the first bottom conductive layer309, and sidewalls of the first bottom insulating layer303. Bottoms of the first pair of inner spacers207-1may be respectively correspondingly disposed on portions of the two first lightly-doped regions201-1. With reference toFIGS.1and2, in the embodiment depicted, the two first heavily-doped regions203-1may be respectively correspondingly disposed adjacent to the two first lightly-doped regions201-1. The two first heavily-doped regions203-1may be respectively correspondingly disposed adjacent to the first pair of inner spacers207-1and in the substrate101. The two first heavily-doped regions203-1may be doped with a same dopant as the two first lightly-doped regions201-1and may have a same electrical type as the two first lightly-doped regions201-1. The two first heavily-doped regions203-1may have a dopant concentration greater than the dopant concentration of the two first lightly-doped regions201-1. With reference toFIGS.1and2, in the embodiment depicted, the second semiconductor stack401may be disposed on the second active region105-2and may include a second insulating stack, a second bottom conductive layer409, a second filler layer413, and a second capping layer415. The second insulating stack may include a second bottom insulating layer403, a second middle insulating layer405, and a second top insulating layer407. The second semiconductor stack401may have a second threshold voltage. The second threshold voltage may be greater than the first threshold voltage. With reference toFIGS.1and2, in the embodiment depicted, the second bottom insulating layer403may be disposed on the second active region105-2. The second bottom insulating layer403may have a thickness between about 0.1 nm and about 3.0 nm. Preferably, the thickness of the second bottom insulating layer403may be between about 0.5 nm and about 2.5 nm. It should be noted that the thickness of the second bottom insulating layer403may be set to an arbitrary range depending on the circumstances. The second bottom insulating layer403may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. Alternatively, in another embodiment, the second bottom insulating layer403may be formed of an insulating material having a dielectric constant of about 4.0 or greater. The two second lightly-doped regions201-2may be respectively correspondingly disposed adjacent to two sides of the second bottom insulating layer403and in the substrate101. The two second lightly-doped regions201-2may be doped with a same dopant as the two first lightly-doped regions201-1, and may have a same electrical type and a same dopant concentration as the two first lightly-doped regions201-1, but are not limited thereto. With reference toFIGS.1and2, in the embodiment depicted, the second middle insulating layer405may be disposed on the second bottom insulating layer403. The second middle insulating layer405may have a thickness between about 0.1 nm and about 2.0 nm. Preferably, the thickness of the second middle insulating layer405may be between about 0.5 nm and about 1.5 nm. It should be noted that the thickness of the second middle insulating layer405may be set to an arbitrary range depending on the circumstances. The second middle insulating layer405may be formed of, for example, an insulating material having a dielectric constant of about 4.0 or greater. Alternatively, in another embodiment, the second middle insulating layer405may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. With reference toFIGS.1and2, in the embodiment depicted, the second top insulating layer407may be disposed on the second middle insulating layer405. The second top insulating layer407may have a same thickness as the first bottom insulating layer303, but is not limited thereto. The second top insulating layer407may be formed of a same material as the first bottom insulating layer303, but is not limited thereto. The second bottom conductive layer409may be disposed on the second top insulating layer407and may have a same thickness as the first bottom conductive layer309, but is not limited thereto. The second bottom conductive layer409may be formed of a same material as the first bottom conductive layer309, but is not limited thereto. With reference toFIGS.1and2, in the embodiment depicted, the second filler layer413may be disposed on the second bottom conductive layer409. The second filler layer413may be formed of a same material as the first filler layer313, but is not limited thereto. The second capping layer415may be disposed on the second filler layer413. The second capping layer415may be formed of a same material as the first capping layer315, but is not limited thereto. The second pair of inner spacers207-2may be respectively correspondingly attached to two sides of the second semiconductor stack401. Specifically, the second pair of inner spacers207-2may be respectively correspondingly attached to sidewalls of the second capping layer415, sidewalls of the second filler layer413, sidewalls of the second bottom conductive layer409, sidewalls of the second top insulating layer407, sidewalls of the second middle insulating layer405, and sidewalls of the second bottom insulating layer403. Bottoms of the second pair of inner spacers207-2may be respectively correspondingly disposed on portions of the two second lightly-doped regions201-2. With reference toFIGS.1and2, in the embodiment depicted, the two second heavily-doped regions203-2may be respectively correspondingly disposed adjacent to the two second lightly-doped regions201-2. The two second heavily-doped regions203-2may be respectively correspondingly disposed adjacent to the second pair of inner spacers207-2and in the substrate101. The two second heavily-doped regions203-2may be doped with a same dopant as the two second lightly-doped regions201-2and may have a same electrical type as the two second lightly-doped regions201-2. The two second heavily-doped regions203-2may have a dopant concentration greater than the dopant concentration of the two second lightly-doped regions201-2. With reference toFIGS.1and2, in the embodiment depicted, the third semiconductor stack501may be disposed on the third active region105-3and may include a third insulating stack, a third bottom conductive layer509, a third top conductive layer511, a third filler layer513, and third capping layer515. The third insulating stack may include a third bottom insulating layer503and a third top insulating layer507. The third semiconductor stack501may have a third threshold voltage. The third threshold voltage may be greater than the first threshold voltage and less than the second threshold voltage. With reference toFIGS.1and2, in the embodiment depicted, the third bottom insulating layer503may be disposed on the third active region105-3. The third bottom insulating layer503may have a same thickness as the second middle insulating layer405, but is not limited thereto. It should be noted that the thickness of the third bottom insulating layer503may be set to an arbitrary range depending on the circumstances. The third bottom insulating layer503may be formed of a same material as the second middle insulating layer405, but is not limited thereto. The two third lightly-doped regions201-3may be respectively correspondingly disposed adjacent to two sides of the third bottom insulating layer503and in the substrate101. The two third lightly-doped regions201-3may be doped with a dopant such as boron and may have a second electrical type which may be different from the first electrical type. The two third lightly-doped regions201-3may have a dopant concentration between about 1E14 atoms/cm{circumflex over ( )}3 and about 1E16 atoms/cm{circumflex over ( )}3. With reference toFIGS.1and2, in the embodiment depicted, the third top insulating layer507may be disposed on the third bottom insulating layer503. The third top insulating layer507may have a same thickness as the second top insulating layer407, but is not limited thereto. The third top insulating layer507may be formed of a same material as the second top insulating layer407, but is not limited thereto. The third bottom conductive layer509may be disposed on the third top insulating layer507. The third bottom conductive layer509may have a thickness between about 10 angstroms and about 100 angstroms. The third bottom conductive layer509may be formed of, for example, titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium. With reference toFIGS.1and2, in the embodiment depicted, the third top conductive layer511may be disposed on the third bottom conductive layer507. The third top conductive layer511may have a same thickness as the second bottom conductive layer409, but is not limited thereto. The third top conductive layer511may be formed of a same material as the second bottom conductive layer409, but is not limited thereto. The third filler layer513may be disposed on the third top conductive layer511. The third filler layer513may be formed of a same material as the second filler layer413, but is not limited thereto. The third capping layer515may be disposed on the third filler layer513and may be formed of a same material as the second capping layer415, but is not limited thereto. With reference toFIGS.1and2, in the embodiment depicted, the third pair of inner spacers207-3may be respectively correspondingly attached to two sides of the third semiconductor stack501. Specifically, the third pair of inner spacers207-3may be respectively correspondingly attached to sidewalls of the third capping layer515, sidewalls of the third filler layer513, sidewalls of the third top conductive layer511, sidewalls of the third bottom conductive layer509, sidewalls of the third top insulating layer507, and sidewalls of the third bottom insulating layer503. Bottoms of the third pair of inner spacers207-3may be respectively correspondingly disposed on portions of the two third lightly-doped regions201-3. With reference toFIGS.1and2, in the embodiment depicted, the two second heavily-doped regions203-3may be respectively correspondingly disposed adjacent to the two third lightly-doped regions201-3. The two second heavily-doped regions203-3may be respectively correspondingly disposed adjacent to the third pair of inner spacers207-3and in the substrate101. The two second heavily-doped regions203-3may be doped with a same dopant as the two third lightly-doped regions201-3and may have a same electrical type as the two third lightly-doped regions201-3. The two second heavily-doped regions203-3may have a dopant concentration greater than the dopant concentration of the two third lightly-doped regions201-3. With reference toFIGS.1and2, in the embodiment depicted, the first insulating stack may have a thickness T1, which may be equal to the thickness of the first bottom insulating layer303. The second insulating stack may have a thickness T2, which may be equal to a sum of the thicknesses of the second top insulating layer407, the second middle insulating layer405, and the second bottom insulating layer403. The third insulating stack may have a thickness T3, which may be equal to a sum of the thicknesses of the third top insulating layer507and the third bottom insulating layer503. The thickness T2may be greater than the thickness T3and the thickness T1. The thickness T2may be greater than the thickness T1. The threshold voltage may be proportional to the thickness of the insulating stack; hence, the second threshold voltage of the second semiconductor stack401including the second insulating stack may be greater than the third threshold voltage of the third semiconductor stack501including the third insulating stack and the first threshold voltage of the first semiconductor stack301including the first insulating stack. Accordingly, the third threshold voltage of the third semiconductor stack501including the third insulating stack may be greater than the first threshold voltage of the first semiconductor stack301including the first insulating stack. FIG.3illustrates, in a schematic cross-sectional view diagram, a semiconductor device100B in accordance with another embodiment of the present disclosure. With reference toFIG.3and in comparison toFIG.1, the two third lightly-doped regions201B-3and the two second heavily-doped regions203B-3may be doped with a dopant such as phosphorus, arsenic, or antimony and may have the first electrical type, which is the same as the electrical type of the two first lightly-doped regions201-1. The third bottom conductive layer509B may be disposed on the third top insulating layer507. The third bottom conductive layer509B may have a same thickness as the second bottom conductive layer409, but is not limited thereto. The third bottom conductive layer509B may be formed of a same material as the second bottom conductive layer409, but is not limited thereto. The third filler layer513may be disposed on the third bottom conductive layer509B. FIG.4illustrates, in a schematic cross-sectional view diagram, a semiconductor device100C in accordance with another embodiment of the present disclosure. With reference toFIG.4and in comparison toFIG.1, the two second lightly-doped regions201C-2and the two second heavily-doped regions203C-2may be doped with a dopant such as boron and may have the second electrical type, which is the same as the electrical type of the two third lightly-doped regions201-3. The second semiconductor stack401may include a second top conductive layer411. The second bottom conductive layer409C may be disposed on the second top insulating layer407. The second bottom conductive layer409C may have a thickness between about 10 angstroms and about 100 angstroms. The second bottom conductive layer409C may be formed of, for example, titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium. The second top conductive layer411may be disposed on the second bottom conductive layer409C and may have a same thickness as the first bottom conductive layer309, but is not limited thereto. The second top conductive layer411may be formed of a same material as the first bottom conductive layer309, but is not limited thereto. The second filler layer413may be disposed on the second top conductive layer411. FIG.5illustrates, in a schematic cross-sectional view diagram, a semiconductor device100D in accordance with another embodiment of the present disclosure. With reference toFIG.5and in comparison toFIG.1, the two first lightly-doped regions201D-1and the two first heavily-doped regions203D-1may be doped with a dopant such as boron and may have the second electrical type, which is the same as the electrical type of the two third lightly-doped regions201-3. The first semiconductor stack301may include a first top conductive layer311. The first bottom conductive layer309D may be disposed on the first bottom insulating layer303. The first bottom conductive layer309D may have a thickness between about 10 angstroms and about 100 angstroms. The first bottom conductive layer309D may be formed of, for example, titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium. The first top conductive layer311may be disposed on the first bottom conductive layer309D and may have a thickness between about 10 angstroms and about 200 angstroms. Preferably, the thickness of the first top conductive layer311may be between about 10 angstroms and about 100 angstroms. The first top conductive layer311may be formed of, for example, aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium, or tungsten nitride. The first filler layer313may be disposed on the first top conductive layer311. FIG.6illustrates, in a schematic cross-sectional view diagram, a semiconductor device100E in accordance with another embodiment of the present disclosure. With reference toFIG.6and in comparison toFIG.5, the two third lightly-doped regions201E-3and the two second heavily-doped regions203E-3may be doped with a dopant such as phosphorus, arsenic, or antimony and may have the first electrical type, which is the same as the electrical type of the two second lightly-doped regions201-2. The third bottom conductive layer509E may be disposed on the third top insulating layer507. The third bottom conductive layer509E may have a same thickness as the second bottom conductive layer409, but is not limited thereto. The third bottom conductive layer509E may be formed of a same material as the second bottom conductive layer409, but is not limited thereto. The third filler layer513may be disposed on the third bottom conductive layer509E. FIG.7illustrates, in a schematic cross-sectional view diagram, a semiconductor device100F in accordance with another embodiment of the present disclosure. With reference toFIG.7and in comparison toFIG.5, the two second lightly-doped regions201F-2and the two second heavily-doped regions203F-2may be doped with a dopant such as boron and may have the second electrical type, which is the same as the electrical type of the two third lightly-doped regions201-3. The second semiconductor stack401may include a second top conductive layer411. The second bottom conductive layer409F may be disposed on the second top insulating layer407. The second bottom conductive layer409F may have a thickness between about 10 angstroms and about 100 angstroms. The second bottom conductive layer409F may be formed of, for example, titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium. The second top conductive layer411may be disposed on the second bottom conductive layer409F and may have a same thickness as the third top conductive layer511, but is not limited thereto. The second top conductive layer411may be formed of a same material as the third top conductive layer511, but is not limited thereto. The second filler layer413may be disposed on the second top conductive layer411. FIG.8illustrates, in a schematic cross-sectional view diagram, a semiconductor device100G in accordance with another embodiment of the present disclosure. With reference toFIG.8, the semiconductor device100G may include a first pair of outer spacers209-1, a second pair of outer spacers209-2, and a third pair of outer spacers209-3. The first pair of outer spacers209-1, the second pair of outer spacers209-2, and the third pair of outer spacers209-3may be formed of, for example, silicon oxide, silicon nitride, or the like. The first pair of outer spacers209-1, the second pair of outer spacers209-2, and the third pair of outer spacers209-3may be formed of a same material, but are not limited thereto. The first pair of outer spacers209-1may be respectively correspondingly attached to outer surfaces of the first pair of inner spacers207-1. The second pair of outer spacers209-2may be respectively correspondingly attached to outer surfaces of the second pair of inner spacers207-2. The third pair of outer spacers209-3may be respectively correspondingly attached to outer surfaces of the third pair of inner spacers207-3. Due to the presence of the first pair of outer spacers209-1, the second pair of outer spacers209-2, and the third pair of outer spacers209-3, thicknesses of the first pair of inner spacers207-1, the second pair of inner spacers207-2, and the third pair of inner spacers207-3may be minimized, thereby reducing overlap capacitance occurring between the plurality of doped regions and the first semiconductor stack301, the second semiconductor stack401, and the third semiconductor stack501. As a result, performance of the semiconductor device100G may be improved. FIG.9illustrates, in a schematic cross-sectional view diagram, a semiconductor device100H in accordance with another embodiment of the present disclosure. With reference toFIG.9, the semiconductor device100H may include a third pair of stress regions205-3. The third pair of stress regions205-3may be disposed at the third active region105-3. Specifically, lower portions of the third pair of stress regions205-3may be disposed in the substrate101and may be respectively correspondingly disposed adjacent to the two third lightly-doped regions201-3. Upper portions of the third pair of stress regions205-3may protrude from a top surface of the substrate101and may be respectively correspondingly disposed adjacent to the third pair of inner spacers207-3. The third pair of stress regions205-3may be formed of a material having a second lattice constant which may be different from the first lattice constant of the substrate101. Specifically, the third pair of stress regions205-3may be formed of, for example, silicon germanium. Due to the lattice mismatch between the substrate101and the third pair of stress regions205-3, the carrier mobility may be increased; therefore, the performance of the semiconductor device100H may be improved. FIG.10illustrates, in a schematic cross-sectional view diagram, a semiconductor device100I in accordance with another embodiment of the present disclosure. With reference toFIG.10and in comparison toFIG.9, the semiconductor device100I may include a first pair of stress regions205-1and a second pair of stress regions205-2. The first pair of stress regions205-1and the second pair of stress regions205-2may be respectively correspondingly disposed at the first active region105-1and the second active region105-2in a manner similar to that of the third pair of stress regions205-3illustrated inFIG.9. The first pair of stress regions205-1and the second pair of stress regions205-2may be formed of a material having a third lattice constant which may be different from the first lattice constant of the substrate101. Specifically, the first pair of stress regions205-1and the second pair of stress regions205-2may be formed of, for example, silicon carbide. FIG.11illustrates, in a schematic cross-sectional view diagram, a semiconductor device100J in accordance with another embodiment of the present disclosure. With reference toFIG.11, the first semiconductor stack301may include a first interfacial layer317, a first dipole layer319, a first functional layer321, a first adjustment layer323, a first protection layer325, and a first encapsulation layer327. The first interfacial layer317may be disposed between the substrate101and the first bottom insulating layer303. The first interfacial layer317may facilitate formation of the first bottom insulating layer303. The first interfacial layer317may have a thickness between about 5 angstroms and about angstroms. The first interfacial layer317may be formed of a chemical oxide of the underlying substrate101such as silicon oxide. With reference toFIG.11, the first dipole layer319may be disposed between the first bottom insulating layer303and the first interfacial layer317. The first dipole layer319may have a thickness less than 2 nm. The first dipole layer319may displace defects in the first bottom insulating layer303and may improve the mobility and reliability of the first semiconductor stack301. The first dipole layer319may be formed of a material including one or more of lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide, lanthanum oxide, lanthanum silicon oxide, barium oxide, barium silicon oxide, strontium oxide, strontium silicon oxide, aluminum oxide, aluminum silicon oxide, titanium oxide, titanium silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, scandium oxide, scandium silicon oxide, magnesium oxide, and magnesium silicon oxide. With reference toFIG.11, the first functional layer321may be disposed on the first bottom insulating layer303. The first functional layer321may have a thickness between about 10 angstroms and about angstroms and may be formed of, for example, titanium nitride or tantalum nitride. The first functional layer321may protect the first bottom insulating layer303from damage during subsequent semiconductor processes. The first adjustment layer323may be disposed on the first functional layer321and may include a material or an alloy including lanthanide nitride. The first adjustment layer323may be used to fine-tune the first threshold voltage. The first protection layer325may be disposed on the first adjustment layer323and may protect the first adjustment layer323from damage during subsequent semiconductor processes. The first protection layer325may be formed of, for example, titanium nitride. With reference toFIG.11, the first encapsulation layer327may be disposed between the first bottom conductive layer309and the first filler layer313. The first encapsulation layer327may have a thickness between about 15 angstroms and about 25 angstroms. The first encapsulation layer327may be formed of, for example, titanium nitride. The first encapsulation layer327may protect layers below the first encapsulation layer327from mechanical damage or diffusion of the first filler layer313. With reference toFIG.11, the second semiconductor stack401may include a second interfacial layer417, a second dipole layer419, a second functional layer421, a second adjustment layer423, a second protection layer425, and a second encapsulation layer427. The third semiconductor stack501may include a third interfacial layer517, a third dipole layer519, a third functional layer521, a third adjustment layer523, a third protection layer525, and a third encapsulation layer527. The aforementioned layers of the second semiconductor stack401and the third semiconductor stack501may be disposed in a manner similar to that of the first semiconductor stack301. FIG.12illustrates, in a flowchart diagram form, a method30for fabricating a semiconductor device100A in accordance with one embodiment of the present disclosure.FIGS.13to36illustrate, in schematic cross-sectional diagrams, a flow of fabricating the semiconductor device100A in accordance with one embodiment of the present disclosure. With reference toFIGS.12and13, at step S11, in the embodiment depicted, a substrate101may be provided and an isolation layer103may be formed in the substrate101and may define a first active region105-1, a second active region105-2, and a third active region105-3. With reference toFIGS.12and14to19, at step S13, in the embodiment depicted, a first insulating stack, a second insulating stack, and a third insulating stack may be respectively correspondingly formed on the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.14, a bottom insulating film601may be deposited on the substrate101. The bottom insulating film601may have a thickness between about 0.1 nm and about 3.0 nm. The bottom insulating film601may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like. Alternatively, in another embodiment, the bottom insulating film601may be formed of an insulating material having a dielectric constant of about 4.0 or greater. A mask layer may be formed on the bottom insulating film601. After development, the mask layer may be turned into a first mask segment701on the bottom insulating film601at the second active region105-2. With reference toFIG.15, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the bottom insulating film601and turn the bottom insulating film601into a second bottom insulating layer403. After the etch process, the first mask segment701may be removed. With reference toFIG.16, a middle insulating film603may be deposited on the substrate101and on the second bottom insulating layer403. The middle insulating film603may have a thickness between about 0.1 nm and about 2.0 nm. The middle insulating film603may be formed of a same material as the bottom insulating film601, but is not limited thereto. A mask layer may be formed on the middle insulating film603. After development, the mask layer may be turned into a plurality of second mask segments703on the middle insulating film603at the second active region105-2and the third active region105-3. With reference toFIG.17, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the middle insulating film603and turn the middle insulating film603into a second middle insulating layer405and a third bottom insulating layer503. After the etch process, the plurality of second mask segments703may be removed. With reference toFIG.18, a top insulating film605may be deposited on the substrate101, the second middle insulating layer405, and the third bottom insulating layer503. The top insulating film605may have a thickness between about 0.5 nm and about 5.0 nm. The top insulating film605may be formed of a same material as the bottom insulating film601, but is not limited thereto. A mask layer may be formed on the top insulating film605. After development, the mask layer may be turned into a plurality of third mask segments705on the top insulating film605at the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.19, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the top insulating film605and turn the top insulating film605into a first bottom insulating layer303, a second top insulating layer407, and a third top insulating layer507. After the etch process, the plurality of third mask segments705may be removed. The first bottom insulating layer303alone may be regarded as the first insulating stack. The second bottom insulating layer403, the second middle insulating layer405, and the second top insulating layer407may be regarded as the second insulating stack. The third bottom insulating layer503and the third top insulating layer507may be regarded as the third insulating stack. With reference toFIGS.12and20to22, at step S15, in the embodiment depicted, two first lightly-doped regions201-1, two second lightly-doped regions201-2, and two third lightly-doped regions201-3may be respectively correspondingly formed in the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.20, a mask layer may be formed over the substrate101. After development, the mask layer may be turned into a fourth mask segment707covering the third active region105-3. With reference toFIG.21, an implantation process using a dopant such as phosphorus, arsenic, or antimony may be performed to respectively correspondingly form the two first lightly-doped regions201-1and the two second lightly-doped regions201-2in the first active region105-1and the second active region105-2. The fourth mask segment707may be removed after the implantation process. With reference toFIG.22, the two third lightly-doped regions201-3may be formed in the third active region105-3with another implantation process similar to that of the two first lightly-doped regions201-1illustrated inFIGS.20and21. The dopant used in the implantation process of the third active region105-3may be boron. With reference toFIGS.12and23to30, at step S17, in the embodiment depicted, a first semiconductor stack301, a second semiconductor stack401, and a third semiconductor stack501may be respectively correspondingly formed on the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.23, a bottom conductive film607may be deposited to cover the substrate101, the first insulating stack, the second insulating stack, and the third insulating stack. The bottom conductive film607may have a thickness between about 10 angstroms and about 100 angstroms. The bottom conductive film607may be formed of, for example, titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium. A mask layer may be formed on the bottom conductive film607. After development, the mask layer may be turned into a fifth mask segment709on the bottom conductive film607at the third active region105-3. With reference toFIG.24, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the bottom conductive film607and turn the bottom conductive film607into a third bottom conductive layer509. After the etch process, the fifth mask segment709may be removed. With reference toFIG.25, a top conductive film609may be deposited to cover the substrate101, the first insulating stack, the second insulating stack, and the third bottom conductive layer509. The top conductive film609may have a thickness between about 10 angstroms and about 200 angstroms. The top conductive film609may be formed of, for example, aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium, or tungsten nitride. A mask layer may be formed on the top conductive film609. After development, the mask layer may be turned into a plurality of sixth mask segments711on the top conductive film609at the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.26, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the top conductive film609and turn the top conductive film609into a first bottom conductive layer309, a second bottom conductive layer409, and a third top conductive layer511. After the etch process, the plurality of sixth mask segments711may be removed. With reference toFIG.27, a filler film611may be deposited to cover the substrate101, the first bottom conductive layer309, the second bottom conductive layer409, and the third top conductive layer511. The filler film611may be formed of, for example, tungsten or aluminum. A mask layer may be formed on the filler film611. After development, the mask layer may be turned into a plurality of seventh mask segments713on the filler film611at the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.28, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the filler film611and turn the filler film611into a first filler layer313, a second filler layer413, and a third filler layer513. After the etch process, the plurality of seventh mask segments713may be removed. With reference toFIG.29, a capping film613may be deposited to cover the substrate101, the first filler layer313, the second filler layer413, and the third filler layer513. The capping film613may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluoride-doped silicate. A mask layer may be formed on the capping film613. After development, the mask layer may be turned into a plurality of eighth mask segments715on the capping film613at the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.30, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the capping film613and turn the capping film613into a first capping layer315, a second capping layer415, and a third capping layer515. After the etch process, the plurality of eighth mask segments715may be removed. The first bottom insulating layer303, the first bottom conductive layer309, the first filler layer313, and the first capping layer315together form the first semiconductor stack301. The second bottom insulating layer403, the second middle insulating layer405, the second top insulating layer407, the second bottom conductive layer409, the second filler layer413, and the second capping layer415together form the second semiconductor stack401. The third bottom insulating layer503, the third top insulating layer507, the third bottom conductive layer509, the third top conductive layer511, the third filler layer513, and the third capping layer515together form the third semiconductor stack501. With reference toFIGS.12and31to33, at step S19, in the embodiment depicted, a first pair of inner spacers207-1, a second pair of inner spacers207-2, and a third pair of inner spacers207-3may be respectively correspondingly formed on the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.31, a mask layer may be formed over the substrate101. After development, the mask layer may be turned into a ninth mask segment717cover the second active region105-2and the third active region105-3. Subsequently, a spacer film615may be deposited on the first active region105-1and may cover the first semiconductor stack301. The spacer film615may be formed of, for example, polysilicon, silicon oxide, or silicon nitride. With reference toFIG.32, an etch process, such as an anisotropic dry etch process, may be performed to remove portions of the spacer film615and turn the spacer film615into the first pair of inner spacers207-1attached to two sides of the first semiconductor stack301. With reference toFIG.33, the second pair of inner spacers207-2and the third pair of inner spacers207-3may be respectively correspondingly formed on the second active region105-2and the third active region105-3with a procedure similar to that of the first pair of inner spacers207-1illustrated inFIGS.30and31. Subsequently, the ninth mask segment717may be removed. With reference toFIGS.12and34to36, at step S21, in the embodiment depicted, two first heavily-doped regions203-1, two second heavily-doped regions203-2, and two third heavily-doped regions203-3may be respectively correspondingly formed in the first active region105-1, the second active region105-2, and the third active region105-3. With reference toFIG.34, a mask layer may be formed over the substrate101. After development, the mask layer may be turned into a tenth mask segment719covering the second active region105-2and the third active region105-3. With reference toFIG.35, an implantation process using a dopant such as phosphorus, arsenic, or antimony may be performed to respectively correspondingly form the two first heavily-doped regions203-1in the first active region105-1. The tenth mask segment719may be removed after the implantation process. With reference toFIG.36, the two second heavily-doped regions203-2and the two third heavily-doped regions203-3may be sequentially formed in the second active region105-2and the third active region105-3with other implantation processes similar to that of the two first heavily-doped regions203-1illustrated inFIGS.34and35. Due to the design of the semiconductor device of the present disclosure, the first semiconductor stack301, the second semiconductor stack401, and the third semiconductor stack501may have different threshold voltages and may provide different functions; therefore, the applicability of the semiconductor device may be increased. In addition, the carrier mobility of the semiconductor device may be improved due to presence of the pairs of stress regions. Furthermore, the threshold voltages of the semiconductor device may be fine-tuned using the adjustment layers. Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps. | 52,932 |
11942515 | DETAILED DESCRIPTION Advantages and features of the inventive concept and methods of accomplishing them will be made apparent with reference to the accompanying drawings and some embodiments to be described below. These inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the inventive concept to those skilled in the art. Accordingly, all such modifications are intended to be included within the scope of this inventive concept as defined in the claims. The terminology used herein to describe embodiments of the invention is not intended to limit the scope of the invention. The use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements of the invention referred to in the singular form may number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated elements, components, steps, operations, and/or devices, but do not preclude the presence or addition of one or more other elements, components, steps, operations, and/or devices. Embodiments are described herein with reference to cross-sectional and/or planar illustrations that are schematic illustrations of idealized embodiments and intermediate structures. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present inventive concept. Like numerals refer to like elements throughout the specification. Accordingly, the same numerals and similar numerals can be described with reference to other drawings, even if not specifically described in a corresponding drawing. Further, when a numeral is not marked in a drawing, the numeral can be described with reference to other drawings. As semiconductor devices sizes are further reduced, conventional contact areas of source drain regions are decreased and on-current characteristics of semiconductor devices are degraded. The present inventive concept arises from the recognition that the contact area of a crystal growth source/drain needs to be increased for improved on-current characteristics. This may be achieved by use of a left-right asymmetric diamond shaped source/drain, as will be described now in further detail. FIG.1Ais a perspective view illustrating a semiconductor device in accordance with an embodiment of the inventive concept.FIG.1Ais an enlarged view of E1ofFIG.1A.FIG.1Bis a cross-sectional view taken along line I-I′ ofFIG.1A.FIG.1Cis a cross-sectional view taken along line II-II′ ofFIG.1A.FIG.1Dis a cross-sectional view taken along line III-III′ ofFIG.1A, andFIG.1Dis an enlarged view of E1aofFIG.1D. Referring toFIGS.1A,1B, and1C, a semiconductor device100ain accordance with an embodiment of the inventive concept may include a substrate102a,active fins102bprotruding from a surface of the substrate102a,a device isolation layer104, gate stacks118, spacers108, crystal growth source/drains114ahaving an asymmetrical shape, and an interlayer insulating layer116. The substrate102amay include the protruding active fins102b,first trenches TR1, second trenches TR2, and third trenches TR3. The first trenches TR1and the second trenches TR2may be formed when the substrate102ais recessed to form the active fins102b.Side surfaces of the first trenches TR1and the second trenches TR2may be side surfaces of the active fins102b.Widths TRW1of the first trenches TR1and widths TRW2of the second trenches TR2may be interpreted as distances between adjacent active fins102b.The widths TRW1of the first trenches TR1may be smaller than the widths TRW2of the second trenches TR2. Accordingly, distances between the active fins102bsharing the first trenches TR1may be smaller than distances between the active fins102bsharing the second trenches TR2. The third trenches TR3may be formed by recessing bottom surfaces TRB2of the second trenches TR2. Bottom surfaces TRB1of the first trenches TR1may be disposed at the same level as the bottom surfaces TRB2of the second trenches TR2. Bottom surfaces TRB3of the third trenches TR3may be disposed at a lower level (i.e. deeper into the substrate102a) than the bottom surfaces TRB1of the first trenches TR1and the bottom surfaces TRB2of the second trenches TR2. Active blocks ABL may be separated by the second trenches TR2and/or third trenches TR3. Each active block ABL may include the active fins102bsharing the first trench TR1. For example, an SRAM may include the active blocks ABL having different-type impurities. The third trenches TR3may electrically insulate the active blocks ABL. The active fins102bmay be spaced apart from each other and may extend in a direction away from the substrate102a. The active fins102b,referring toFIG.1C, may include first fin areas A and second fin areas B. The second fin areas B may be recessed areas and may include recessed upper surfaces102baand recessed side surfaces102bb.The recessed upper surfaces102baof the second fin areas B may be disposed at a lower level than upper surfaces102ba′of the first fin areas A. Accordingly, the active fins102bmay have a concave-convex shape including concave portions and convex portions. The substrate102amay include a silicon (Si) substrate and a silicon-germanium (SiGe) substrate. The device isolation layer104, referring toFIG.1A, may fill the first trenches TR1, the second trenches TR2, and the third trenches TR3. An upper surface of the device isolation layer104may be disposed at a lower level than the recessed upper surfaces102baof the active fins102b.The upper surface of the device isolation layer104filling the first trenches TR1may be disposed at a higher level than the upper surface of the device isolation layer104filling the second trenches TR2. The device isolation layer104may include silicon oxide (SiO2). First residues108amay remain on first side surfaces102bcof the active fins102bsharing the first trenches TR1, and second residues108bmay remain on second side surfaces102bdof the active fins102bsharing the second trenches TR2and parallel to the first side surfaces102bc.The first residues108aand the second residues108bmay be in contact with upper surfaces of the device isolation layer104filling the first trenches TR1and the second trenches TR2. The upper surfaces of the device isolation layer104contacting the first residues108aand the second residues108bmay be disposed at the same level. The second residues108bmay be smaller in volume than the first residues108a.Upper surfaces of the first residues108amay be disposed at a higher level than upper surfaces of the second residues108b.The second side surfaces102bdof the active fins102bmay include exposed portions K1. The exposed portions K1may be portions exposed by level differences between the recessed upper surfaces102baof the active fins102band the upper surfaces of the second residues108b. The gate stacks118may have a bar shape extending in a direction. The gate stacks118may be spaced apart from each other and cross the active fins102b.The gate stacks118may perpendicularly cross the second fin areas B of the active fins102b.The gate stacks118may include gate dielectric layers118aand gate electrodes118b.The gate dielectric layers118amay include lower surfaces118aaconformally formed on the upper surfaces of the device isolation layer104and the upper and side surfaces of the active fins102bof the second fin areas B, and side surfaces118abperpendicular to the lower surfaces118aa.The gate electrodes118bmay be in contact with the lower surfaces118aaand the side surfaces118abof the gate dielectric layers118aand may fill spaces formed by the gate dielectric layers118a.The gate dielectric layers118amay include a high-k dielectric material. More specifically, the high-k dielectric material may include hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), or tantalum oxide (Ta2O5). The gate electrodes118bmay include tungsten (W) or aluminum (Al). In some embodiments, the gate electrodes118bmay have a stacked structure including barrier layers. The spacers108may be in contact with the side surfaces118abof the gate dielectric layers118a.The spacers108may be formed in a multilayer. The spacers108may include stacked silicon nitride (SiNx) and silicon carbide (SiC) layers. In some embodiments, the spacers108may include stacked silicon nitride (SiNx) and silicon carbonitride (SiCN) layers. The first residues108aand the second residues108bmay include the same material as the spacers108. More specifically, the first residues108aand the second residues108bmay be residues of the spacers108that remain without being removed. The source/drains114amay have a left-right asymmetric diamond shape. Each source/drain114amay include a first crystal growth portion114aaand a second crystal growth portion114ab.For convenience of description, the first crystal growth portion114aamay be referred to as “a main growth portion,” and the second crystal growth portion114abmay be referred to as “an additional growth portion.” The main growth portion114aamay be a portion grown from the recessed upper surface102baand the recessed side surface102bbof the active fin102b.The additional growth portion114abmay be a portion grown from the exposed portion K1of the second side surface102bdof the active fin102b.The main growth portion114aamay have a left-right symmetric diamond shape, and the additional growth portion114abmay have a rectangular shape. The additional growth portion114aband the main growth portion114aamay share a plane. A lower surface of the main growth portion114aamay be in contact with the recessed upper surface102baof the active fin102band the upper surface of the first residue108a,and a lower surface of the additional growth portion114abmay be in contact with the exposed portion K1of the second side surface102bdof the active fin102band the upper surface of the second residue108b.The lower surface of the additional growth portion114abmay be disposed at a lower level than the lower surface of the main growth portion114aa. The source/drains114amay be grown in an epitaxial growth process. The source/drains114amay include Si, SiGe, or SiC. The source/drains114amay include impurities. When the semiconductor device100ais an N-type transistor, it may include N-type impurities. When the semiconductor device100ais a P-type transistor, it may include P-type impurities. The impurities may be included throughout the source/drains114aand the active fins102bthereunder. The impurities may be distributed differently in the source/drains114a.For example, the dopant concentration may gradually increase toward upper ends of the source/drains114a. The interlayer insulating layer116may cover the source/drains114a.An upper surface of the interlayer insulating layer116may be disposed at the same level as upper surfaces of the gate stacks118. FIG.2is a cross-sectional view for describing a semiconductor device in accordance with embodiments of the inventive concept.FIG.2is an enlarged view of E2ainFIG.2. The configuration described with reference toFIG.2may be understood as an embodiment of the configuration described with reference toFIG.1D. Referring toFIG.2, a semiconductor device100bmay include a substrate102a,active fins102b,crystal growth source/drains114ahaving a left-right asymmetric diamond shape, and a device isolation layer104. The device isolation layer104may fill the first trenches TR1, the second trenches TR2, and the third trenches TR3described above with reference toFIGS.1A to1D. An upper surface of the device isolation layer104filling the first and second trenches TR1and TR2may be disposed at a high level and a low level. The high level may have the highest value among levels of the upper surface of device isolation layer104, and the low level may have the lowest value among the levels of the upper surface of device isolation layer104. The upper surface at the high level may be located adjacent to side surfaces of the active fins102b.Such a level difference in the upper surface of the device isolation layer104may be determined by widths TRW1and TRW2of the first and second trenches TR1and TR2shared by the active fins102b,that is, distances between the active fins102b.As the widths TRW1and TRW2of the first and second trenches TR1and TR2decrease, the level difference in the upper surface of the device isolation layer104may significantly increase. Here, since a portion disposed at the high level protrudes than a portion disposed at the low level, it is referred to as a “protrusion” hereinafter. Accordingly, the device isolation layer104filling the first trenches TR1may include first protrusions104aprotruding from side surfaces of the first trenches TR1. The device isolation layer104filling the second trenches TR2may include second protrusions104bprotruding from side surfaces of the second trenches TR2. Upper surfaces of the first protrusions104amay be disposed at a higher level than upper surfaces of the second protrusions104b.The upper surfaces of the first protrusions104amay be disposed at the same level as or a higher level than the upper surfaces of the active fins102b.Second side surfaces102bdof the active fins102bmay include exposed portions K2. The exposed portions K2may be portions exposed by level differences between recessed upper surfaces102baof the active fins102band the upper surfaces of the second protrusions104b. The crystal growth source/drains114amay include main growth portions114aaand additional growth portions114ab.Lower surfaces of the main growth portions114aamay be in contact with the upper surfaces of the active fins102band the upper surfaces of the first protrusions104a.Lower surfaces of the additional growth portions114abmay be in contact with the exposed portions K2of the second side surfaces102bdof the active fins102band the upper surfaces of the second protrusions104b.The lower surfaces of the additional growth portions114abmay be disposed at a lower level than the lower surfaces of the main growth portions114aa. FIG.3Ais a perspective view illustrating a semiconductor device in accordance with embodiments of the inventive concept.FIG.3Bis a cross-sectional view taken along line IV-IV′ ofFIG.3A. In the configuration ofFIG.3A, the same reference numerals as those inFIG.1may denote the same components as those inFIG.1, and detailed descriptions thereof will be omitted. Since E1ofFIG.3Aand E1aofFIG.3Bhave the same configurations asFIG.1AandFIG.1D, respectively, these figures may be referred to. Referring toFIGS.3A,3B,1A,1C, and1D, a semiconductor device100cin accordance with embodiments of the inventive concept may include a substrate102a,active fins102bprotruding from a surface of the substrate102a,a device isolation layer104, gate stacks118, spacers108, merged crystal growth source/drains114b,and an interlayer insulating layer116. The substrate102amay include the protruding active fins102b,first trenches TR1, second trenches TR2, and third trenches TR3. Side surfaces of the first trenches TR1may be first side surfaces102bcof adjacent active fins102b,and side surfaces of the second trenches TR2may be second side surfaces102bdparallel to the first side surfaces102bcof the active fins102b. First residues108amay remain on the first side surfaces102bcof the active fins102b,and second residues108bmay remain on the second side surfaces102bdof the active fins102b.Upper surfaces of the first residues108amay be disposed at the same level as or a higher level than upper surfaces of the active fins102b.Upper surfaces of the second residues108bmay be disposed at a lower level than the upper surfaces of the first residues108a.The second side surfaces102bdof the active fins102bmay include exposed portions K1. The exposed portions K1may be portions exposed by level differences between recessed upper surfaces102baof the active fins102band the upper surfaces of the second residues108b.The first residues108aand the second residues108bmay include the same material as the spacers108. The merged source/drains114bmay be in contact with a plurality of active fins102b,and may include first crystal growth portions114ba,second crystal growth portions114bb,and third crystal growth portions114bc.For convenience of description, the first crystal growth portion114bamay be referred to as “a main growth portion,” the second crystal growth portion114bbmay be referred to as “an additional growth portion,” and the third crystal growth portions114bcmay be referred to as “a merged growth portion.” A first region of the isolation layer104may be between and in contact with the plurality of active fins102band may overlap the merged crystal growth portion114bcin a direction perpendicular to the substrate102a. The main growth portions114bamay be portions grown from the recessed upper surfaces102baand recessed side surfaces102bbof the active fins102b.The additional growth portions114bbmay be portions grown from the exposed portions K1of the second side surfaces102bdof the active fins102b.The additional growth portions114bbmay be respectively located at one side and the other side of the merged source/drains114b.Each main growth portion114aamay share a plane with each additional growth portion114bb.The main growth portions114bamay have a diamond shape, the additional growth portions114bbmay have a rectangular shape, and the merged growth portions114bcmay be understood as having a shape in which edges of the main growth portions114baare merged. More specifically, the merged growth portions114bcmay be portions in which adjacent edges of the main growth portions114baare merged and the merged portions are extended upwardly and downwardly during a crystal growth process. Lower surfaces of the main growth portions114bamay be in contact with the upper surfaces of the active fins102band the upper surfaces of the first residues108a,and lower surfaces of the additional growth portions114bbmay be in contact with the side surfaces of the active fins102band the upper surfaces of the second residues108b.The lower surfaces of the additional growth portions114bbmay be disposed at a lower level than the lower surfaces of the main growth portions114ba.Lower surfaces of the merged growth portions114bcmay be disposed at a higher level than the lower surfaces of the main growth portions114ba.The second region of the isolation layer104overlaps upper end portions of the second crystal growth portions114bbthat are spaced apart from the plurality of active fins102b.A lowest portion of an upper surface of the second region of the isolation layer104that overlaps the upper end portions of the second crystal growth portions114bbthat are spaced apart from the plurality of active fins102bis at lower level than a lowest portion of an upper surface of the first region of the isolation layer104. The second region overlaps upper end portions of the second crystal growth portions114bbthat are spaced apart from the active fins102b.A lowest portion of an upper surface of the second region of the isolation layer104that overlaps the upper end portions of the second crystal growth portions114bbthat are spaced apart from the active fins102bis at a lower level than a lowest portion of an upper surface of the first region of the isolation layer104. FIG.4is a cross-sectional view for describing a semiconductor device in accordance with embodiments of the inventive concept.FIG.4may be understood as an embodiment of the configuration described with reference toFIG.3B. Since E2aofFIG.4has the same configuration asFIG.2, this figure may be referred to. Referring toFIGS.4and2, a semiconductor device100din accordance with the embodiment of the inventive concept may include a substrate102a,active fins102b,merged crystal growth source/drains114b,and a device isolation layer104. The device isolation layer104may fill the above-described first trenches TR1, second trenches TR2, and third trenches TR3. An upper surface of the device isolation layer104filling the first trenches TR1may be disposed at a higher level than an upper surface of the device isolation layer104filling the second trenches TR2. The upper surface of the device isolation layer104filling the first trenches TR1may be disposed at a high level and a low level. Since a portion disposed at the high level protrudes more than a portion disposed at the low level, it is referred to as a “protrusion” hereinafter. Accordingly, the device isolation layer104filling the first trenches TR1may include first protrusions104aprotruding from side surfaces of the first trenches TR1. The device isolation layer104filling the second trenches TR2may include second protrusions104bprotruding from side surfaces of the second trenches TR2. Upper surfaces of the first protrusions104amay be disposed at a higher level than upper surfaces of the second protrusions104b.Second side surfaces102bdof the active fins102bmay include exposed portions K2. The exposed portions K2may be portions exposed by level differences between recessed upper surfaces of the active fins102band the upper surfaces of the second protrusions104b. The merged crystal growth source/drains114bmay have a shape in which edges of crystal growth portions having an asymmetric diamond shape are merged, as described above. The merged source/drains114bmay include main growth portions114ba,additional growth portions114bb,and merged growth portions114bc. Lower surfaces of the main growth portions114bamay be in contact with the upper surfaces of the active fins102band upper surfaces of the first protrusions104a,and lower surfaces of the additional growth portions114bbmay be in contact with the exposed portions K2of the second side surfaces102bdof the active fins102band the upper surfaces of the second protrusions104b.The lower surfaces of the additional growth portions114bbmay be disposed at a lower level than the lower surfaces of the main growth portions114ba.Lower surfaces of the merged growth portions114bcmay be disposed at a higher level than the lower surfaces of the main growth portions114ba. FIGS.5A,6A,7A,8A,9A,10A,11A,12, and13Aare process perspective views illustrating a method of fabricating a semiconductor device in accordance with an embodiment of the inventive concept according to a process sequence.FIGS.5B,6B,7B,8B,9B,10B,11B,12B, and13Bare cross-sectional views taken along lines V-V′ of the perspective views, respectively (here, the line V-V′ will be omitted inFIG.6A,7A,8A, andFIGS.9A,10A,11A,12, and13A). Referring toFIGS.5A and5B, a method of fabricating a semiconductor device100ain accordance with an embodiment of the inventive concept may include forming active fins102bprotruding from a single substrate102a,a device isolation layer104covering side surfaces of the active fins102b,and sacrificial gate stacks106crossing the active fins102b. The formation of the active fins102bmay include forming first trenches TR1and second trenches TR2by recessing the substrate102a.Bottom surfaces TRB1of the first trenches TR1may be disposed at the same level as bottom surfaces TRB2of the second trenches TR2. Widths TRW1of the first trenches TR1and widths TRW2of the second trenches TR2may be understood as distances between adjacent active fins102b.The widths TRW1of the first trenches TR1may be smaller than the widths TRW2of the second trenches TR2. Accordingly, a distance between the active fins102bsharing the first trenches TR1may be smaller than a distance between the active fins102bsharing the second trenches TR2. The active fins102bmay include first fin areas A and second fin areas B. The first fin areas A may be areas perpendicularly crossed by the sacrificial gate stacks106, and the second fin areas B may be exposed areas. The method may further include forming third trenches TR3. The third trenches TR3may be formed by recessing the bottom surfaces TRB2of the second trenches TR2. Bottom surfaces TRB3of the third trenches TR3may be disposed at a lower level than the bottom surfaces TRB1of the first trenches TR1and the bottom surfaces TRB2of the second trenches TR2. Active blocks ABL may be separated by the second trenches TR2and/or third trenches TR3. The active blocks ABL may include the active fins102bsharing the first trenches TR1. For example, the SRAM may include active blocks ABL having different-type impurities. The third trenches TR3may electrically insulate the above-described active blocks ABL. The substrate102amay be a crystal growth substrate. For example, the substrate102amay include a Si substrate or a SiGe substrate. The device isolation layer104may fill the first trenches TR1, the second trenches TR2, and the third trenches TR3. Upper surfaces of the device isolation layer104may be disposed at a lower level than upper surfaces of the active fins102b.The upper surfaces of the device isolation layer104may be in contact with lower surfaces of the sacrificial gate stacks106. For example, the device isolation layer104may include SiO2. The sacrificial gate stacks106may cross the second fin areas B of the active fins102band be spaced apart from each other. The sacrificial gate stacks106may include sacrificial dielectric layers106a,sacrificial gates106b,and hard masks106cstacked on upper surfaces of the sacrificial gates106b.The sacrificial dielectric layers106amay be formed between the sacrificial gates106band the first fin areas A of the active fins102b.The sacrificial dielectric layers106amay be silicon oxide layers formed by thermally oxidizing surfaces of the active fins102b.The sacrificial gates106bmay be in contact with surfaces of the sacrificial dielectric layers106aand the upper surfaces of the device isolation layer104. The sacrificial gates106bmay include polysilicon. The hard masks106cmay be used as etch masks for forming the sacrificial gates106b.The hard masks106cmay include SiNx. Referring toFIGS.6A and6B, the method may include forming a spacer layer108A. The spacer layer108A may conformally cover the sacrificial gate stacks106, the second fin areas B of the active fins102b,and the upper surfaces of the device isolation layer104. The spacer layer108A may include stacked SiNxand SiC layers. In some embodiments, the spacer layer108A may include stacked SiNxand SiCN layers. FIG.7Ais a process perspective view, andFIG.7Ais an enlarged view of E3inFIG.7A. Referring toFIGS.7A and7B, the method may include forming spacers108on side surfaces of the sacrificial gate stacks106. When forming the spacers108, first residues108amay remain on first side surfaces102bcof the active fins102bsharing the first trenches TR1. Second residues108bmay remain on second side surfaces102bdsharing the second trenches TR2and parallel to the first side surfaces102bc.The second residues108bmay be smaller in volume than the first residues108a.Upper surfaces of the first residues108amay be disposed at a higher level than upper surfaces of the second residues108b.Upper surfaces of the spacers108covering side surfaces of the sacrificial gate stacks106may be disposed at a lower level than upper surfaces of the hard masks106cof the sacrificial gate stacks106. The second side surfaces102bdof the active fins102bmay be exposed by level differences LD1between the upper surfaces of the first residues108aand the upper surfaces of the second residues108b. For example, the spacers108may be formed in an etch-back process. The first residues108aand the second residues108bmay be residues of the spacer layer108A remaining after the etch-back process is finished. Due to differences between the widths TRW1of the first trenches TR1and the widths TRW2of the second trenches TR2, differences in volume between the first residues108aand the second residues108bmay be generated. This is because a rate at which the spacer layer108A formed in the second trenches TR2having a large width is removed is faster than a rate at which the spacer layer108A formed in the first trenches TR1having a small width is removed. During the etch-back process, the upper surfaces of the device isolation layer104may be recessed. The device isolation layer104may include upper surfaces covered by the first residues108aand the second residues108b,and exposed upper surfaces. Level differences may exist between the upper surfaces of the device isolation layer104. For example, in the device isolation layer104, the upper surfaces covered by the first residues108aand the second residues108bmay be disposed at a higher level than the exposed upper surfaces. FIG.8Ais a process perspective view, andFIG.8Ais an enlarged view of E4inFIG.8A. Referring toFIGS.8A and8B, the method may include recessing the second fin areas B of the active fins102b. The recessing process of the second fin areas B may include removing portions of the active fins102bwhich are not covered by the device isolation layer104. The recessed second fin areas B may include recessed upper surfaces102baand recessed side surfaces102bb.The recessed upper surfaces102baof the second fin areas B may be disposed at a lower level than upper surfaces102ba′of the first fin areas A. For example, the active fins102bmay have a concave-convex shape including concave portions and convex portions. The recessed upper surfaces102baof the second fin areas B may be disposed at the same level as or a lower level than the upper surfaces of the first residues108a,and disposed at a higher level than the upper surfaces of the second residues108b.The second side surfaces102bdof the second fin areas B may include exposed portions K1. The exposed portions K1may be portions exposed by level differences between the upper surfaces of the second residues108band the recessed upper surfaces102baof the second fin areas B. Hereinafter, since E1ofFIG.9Ahas the same configuration as that ofFIG.1A, this figure may be referred to. Referring toFIGS.9A and9Btogether withFIG.1A, the method may include performing a crystal growth process to grow source/drains114afrom the recessed upper surfaces102baand recessed side surfaces102bbof the active fins102b. The source/drains114amay be grown to have a left-right asymmetric diamond shape. The source/drains114ahaving the left-right asymmetric diamond shape may include main growth portions114aaand additional growth portions114ab. The main growth portions114aamay be portions grown from the recessed upper surfaces102baand recessed side surfaces102bbof the active fins102b,and the additional growth portions114abmay be portions grown from the exposed portions K1of the second side surfaces102bdof the active fins102b.The main growth portions114aamay have a diamond shape, and the additional growth portions114abmay have a rectangular shape. The main growth portions114aaand the additional growth portions114abmay share a plane. Lower surfaces of the main growth portions114aamay be in contact with the upper surfaces of the active fins102band the upper surfaces of the first residues108a.Lower surfaces of the additional growth portions114abmay be in contact with the exposed portions K1of the second side surfaces102bdof the active fins102b,and the upper surfaces of the second residues108b.The lower surfaces of the additional growth portions114abmay be disposed at a lower level than the lower surfaces of the main growth portions114aa. For example, the source/drains114amay be formed in an epitaxial growth process. The source/drains114amay include Si, SiGe, or SiC. The source/drains114amay include impurities. The source/drains114amay include N-type impurities or P-type impurities. The impurities may be distributed differently in the source/drains114a.For example, while the crystal growth process is performed, the dopant concentration may be increased based on the active fins102b. Referring toFIGS.10A and10B, the method may include forming an interlayer insulating layer116covering the source/drains114a,and removing the hard masks106c. Upper surfaces of the interlayer insulating layer116, the spacers108, and the sacrificial gate106bmay be disposed at the same level. The interlayer insulating layer116may include SiO2. Referring toFIGS.11A and11B, the method may include forming gate trenches GT. The formation of the gate trenches GT may include removing the sacrificial gates106b.Here, the sacrificial dielectric layers106amay serve to prevent the active fins102bfrom being damaged while the sacrificial gates106bare removed. The sacrificial dielectric layer106amay be removed together with the sacrificial gates106bor may remain. Side surfaces the gate trenches GT may be side surfaces of the spacers108. Lower surfaces of the gate trenches GT may be the surfaces of the device isolation layer104and the surfaces of the active fins102bexposed by the gate trenches GT. When the sacrificial dielectric layers106aremain, the bottom surfaces of the gate trenches GT may be the surfaces of the device isolation layer104and surfaces of the sacrificial dielectric layers106asurrounding the active fins102b. Referring toFIGS.12A and12B, the method may include forming gate stacks118in the gate trenches GT. The gate stacks118may include gate dielectric layers118aand gate electrodes118b.The gate dielectric layers118amay include lower surfaces118aaand side surfaces118abperpendicular to the lower surfaces118aa.The lower surfaces118aaof the gate dielectric layers118amay be conformally formed on the surfaces of the device isolation layer104, and the side and upper surfaces of the active fins102bexposed in the gate trenches GT. The side surfaces118abof the gate dielectric layers118amay be in contact with the side surfaces of the gate trenches GT. The gate electrodes118bmay be in contact with the lower surfaces118aaand the side surfaces118abof the gate dielectric layers118aand may fill the gate trenches GT. Upper surfaces of the gate dielectric layers118a,gate electrodes118b,and interlayer insulating layer116may be disposed at the same level. The gate dielectric layers118amay include a high-k material. When the gate dielectric layers118aare formed of the high-k material, it is advantageous for reducing leakage current even when the gate dielectric layers118aare thin. The high-k material may include HfO2, Al2O3, ZrO2, or Ta2O5. The gate electrodes118bmay include W or Al. In some embodiments, the gate electrodes118bmay have a stacked structure including buffer layers. The buffer layers may include titanium nitride (TiN) or tantalum nitride (TaN). Referring toFIGS.13A and13B, the method may include forming a protection layer120, via holes122, and contact electrodes126. The protection layer120may cover the upper surfaces of the gate electrodes118band the upper surface of the interlayer insulating layer116. The protection layer120may include SiOx. The via holes122may pass through the interlayer insulating layer116and the protection layer120. Upper surfaces of the via holes122may have a bar shape extending in a direction. Due to the via holes122, surfaces of the main growth portions114aaof the source/drains114aand surfaces of the additional growth portions114abmay be exposed. The contact electrodes126may fill the via holes122and contact the source/drains114aa.The contact electrodes126may be referred to as plugs. The contact electrodes126may include W. In some embodiments, the contact electrodes126may be used in conjunction with the device ofFIG.17including a merging crystal growth between adjacent source/drains. The contact electrodes126may be in direct contact with the first diamond-shaped source/drain, the second diamond-shaped source/drain, and the merging crystal growth. The method may further include forming silicide layers124on the surfaces of the source/drains114aexposed through the via holes122. The formation of the silicide layers124may include injecting a conductive metal on the exposed source/drains114ain the via holes122, and performing a thermal treatment process. The silicide layers124may be formed between the source/drains114aand the contact electrodes126. Through the above-described processes, a semiconductor device in accordance with the embodiment of the inventive concept may be fabricated. FIGS.14to16are process perspective views illustrating a method of fabricating a semiconductor device in accordance with embodiments of the inventive concept.FIG.14may be understood as illustrating a process to be performed after the process described with reference toFIGS.5A and5Bamong the above-described processes. FIG.14is a process perspective view, andFIG.14is an enlarged view of E5inFIG.14. Referring toFIGS.14,6A, and6B, the method of fabricating the semiconductor device100cin accordance with the other embodiment of the inventive concept may include forming spacers108on side surfaces of the sacrificial gate stacks106. The formation of the spacers108may include partially removing the spacer layer108A through an etching process. During the etching process, in the spacer layer108A, portions covering the second fin areas B of the active fins102band portions covering the hard masks116cmay be removed. Subsequently, the upper surface of the device isolation layer104may be over-etched. The upper surface of the device isolation layer104filling the first trenches TR1and the second trenches TR2may be disposed at a high level and a low level. The high level may be understood as the highest level of the upper surface of the device isolation layer104, and the low level may be understood as the lowest level of the upper surface of the device isolation layer104. Since the portion disposed at the high level protrudes relative to the portion disposed at the low level, it is referred to as a “protrusion” hereinafter. Accordingly, the device isolation layer104filling the first trenches TR1may include first protrusions104aprotruding from side surfaces of the first trenches TR1. The device isolation layer104filling the second trenches TR2may include second protrusions104bprotruding from side surfaces of the second trenches TR2. Upper surfaces of the first protrusions104amay be disposed at a higher level than upper surfaces of the second protrusions104b.Accordingly, first side surfaces102bcof the active fins102b,that is, side surfaces of the first trenches TR1may include the first protrusions104a,and second side surfaces102bdparallel to the first side surfaces102bcof the active fins102b,that is, side surfaces of the second trenches TR2may include the second protrusions104b.Accordingly, the second side surfaces102bdof the active fins102bmay be more exposed by level differences LD2between the upper surfaces of the first protrusions104aand the upper surface of the second protrusions10b. More specifically, the first protrusions104aand the second protrusions104bmay be formed since upper surfaces of the device isolation layer104corresponding to center portions of trenches TR1and TR2are recessed at a faster rate than upper surfaces of the device isolation layer104adjacent to the side surfaces of the first trenches TR1and second trenches TR2. In addition, the first protrusions104aand the second protrusions104bmay have a level difference since the device isolation layer104formed in the second trenches TR2having a large widths is removed faster than the device isolation layer104formed in the first trenches TR1having a small widths. Hereafter,FIG.15is a process perspective view, andFIG.15is an enlarged view of E6inFIG.15. Referring toFIGS.15and8B, the method may include recessing the second fin areas B of the active fins102b. The recess of the second fin areas B may include removing portions of the active fins102bwhich are exposed without being covered by the device isolation layer104. The recessed second fin areas B may include recessed upper surfaces102baand recessed side surfaces102bb.The recessed upper surfaces102baof the second fin areas B may be disposed at a lower level than upper surfaces102ba′of the first fin areas A. For example, the active fins102bmay have a concave-convex shape including concave portions and convex portions. The recessed upper surfaces102baof the second fin areas B may be disposed at the same level as or a lower level than the upper surfaces of the first protrusions104a,and at a lower level than the upper surfaces of the second protrusions104b.The second side surfaces102bdof the second fin areas B may include exposed portions K2. The exposed portions K2may be portions exposed as by level differences between the recessed upper surfaces102baof the second fin areas B and the upper surfaces of the second protrusions10b. Hereinafter,FIG.16is a process perspective view, andFIG.16is an enlarged view of E2inFIG.16. Referring toFIG.16, the method may include performing a crystal growth process to grow source/drains114ain the recessed second fin areas B. The source/drains114amay have an asymmetric diamond shape. The source/drains114amay include main growth portions114aaand additional growth portions114ab.The main growth portions114aamay be portions grown in a diamond shape from the recessed upper surfaces102baand the recessed side surfaces102bbof the active fins102b.The additional growth portions114abmay be portions grown from the exposed portions K2of the second side surfaces102bdof the active fins102b.The additional growth portions114abmay have a rectangular shape. The main growth portions114aaand the additional growth portions114abmay share a plane. Lower surfaces of the main growth portions114aamay be in contact with the upper surfaces of the active fins102band the upper surfaces of the first protrusions104a.Lower surfaces of the additional growth portions114abmay be in contact with the exposed portions K2of the second side surfaces102bdof the active fins102b,and the upper surfaces of the second protrusions104b.The lower surfaces of the additional growth portions114abmay be disposed at a lower level than the lower surfaces of the main growth portions114aa. For example, the source/drains114amay be crystallized through an epitaxial process. Subsequent processes may be the same as the processes described above with reference toFIGS.10A,11A,12, and13A. FIG.17is a process perspective view illustrating a method of fabricating a semiconductor device in accordance with embodiments of the inventive concept. Processes performed before a process to be described with reference toFIG.17may be the same as the processes described with reference toFIGS.5A to8Ain the above-described embodiment. Since E1ofFIG.17has the same configuration as those ofFIG.1A, this figure may be referred to. Referring toFIGS.15,17, and1A, the method of fabricating a semiconductor device in accordance with the other embodiment of the inventive concept may include forming merged source/drains114b. The merged source/drains114bmay be in contact with a plurality of active fins102b,and may include main growth portions114ba,additional growth portions114bb,and merged growth portions114bc.The main growth portions114bamay be portions grown from recessed upper surfaces102baand recessed side surfaces102bbof the active fins102b.The additional growth portions114bbmay be portions grown from exposed portions K1of second side surfaces102bdof the active fins102b.The additional growth portions114bbmay be disposed at one side and the other side of the merged source/drains114b.The main growth portions114bamay share a plane with the additional growth portions114bb.The main growth portions114bamay have a diamond shape, the additional growth portions114bbmay have a rectangular shape, and the merged growth portions114bcmay be understood as a shape in which edges of the main growth portions114baare merged. More specifically, the merged growth portions114bcmay be portions in which adjacent edges of the main growth portions114baare merged and the merged portions are extended upwardly and downwardly during a crystal growth process. In the above-described configuration, first residues108amay remain on first side surfaces102bcof the active fins102b,that is, side surfaces of first trenches TR1, and upper surfaces of a device isolation layer104. Second residues108bmay remain on the second side surfaces102bdparallel to the first side surfaces102bc,and lower surfaces of the additional growth portions114bb.Lower surfaces of the main growth portions114bamay be in contact with upper surfaces of the active fins102band upper surfaces of the first residues108a,and the lower surfaces of the additional growth portions114bbmay be in contact with the side surfaces of the active fins102band upper surfaces of the second residues108b.The lower surfaces of the additional growth portions114bbmay be disposed at a lower level than the lower surfaces of the main growth portions114ba.Lower surfaces of the merged growth portions114bcmay be disposed at a higher level than the lower surfaces of the main growth portions114ba. In some embodiments, referring toFIG.4, the first and second residues108aand108bmay be fully removed, first protrusions104aextending from the device isolation layer104may exist on the first side surfaces102bcof the active fins102b,and second protrusions104bextending from the device isolation layer104may exist on the second side surfaces102bdparallel to the first side surfaces102bc. Subsequent processes may be the same as the processes described above with reference toFIGS.13A and13BandFIGS.14A and14B. FIG.18is a view conceptually illustrating a semiconductor module including a semiconductor device100a,100b,100c,or100dfabricated in accordance with various embodiments of the inventive concept. Referring toFIG.18, a semiconductor module500in accordance with an embodiment of the inventive concept may include a semiconductor device100a,100b,100c,or100dfabricated in accordance with various embodiments of the inventive concept. The semiconductor module500may further include a microprocessor520mounted on a module substrate510. Input/output terminals540may be disposed on at least one side of the module substrate. The semiconductor module500may include a memory card or a solid state drive (SSD). FIG.19is a block diagram conceptually illustrating an electronic system including the semiconductor device100a,100b,100c,or100dfabricated in accordance with various embodiments of the inventive concept. Referring toFIG.19, the semiconductor device100a,100b,100c,or100dmay be applied to an electronic system600. The electronic system600may include a body610, a microprocessor unit620, a power supply630, a function unit640, and/or a display controller unit650. The body610may be a system board or motherboard including a printed circuit board (PCB). The microprocessor unit620, the power supply630, the function unit640, and the display controller unit650may be installed or mounted on the body610. A display unit660may be disposed on a surface of the body610or outside of the body610. For example, the display unit660may be disposed on the surface of the body610and display an image processed by the display controller unit650. The power supply630may receive a constant voltage from an external power source, etc., divide the voltage into various levels of required voltages, and supply those voltages to the microprocessor unit620, the function unit640, and the display controller unit650, etc. The microprocessor unit620may receive a voltage from the power supply630to control the function unit640and the display unit660. The function unit640may perform various functions of the electronic system600. For example, when the electronic system600is a mobile electronic apparatus, such as a mobile phone, the function unit640may have several components which perform wireless communication functions, such as output of an image to the display unit660or output of a voice to a speaker, by dialing or communication with an external apparatus670. When a camera is installed, the function unit640may function as an image processor. In the embodiment to which the inventive concept is applied, when the electronic system600is connected to a memory card, etc. in order to expand a capacity thereof, the function unit640may be a memory card controller. The function unit640may exchange signals with the external apparatus670through a wired or wireless communication unit680. Further, when the electronic system600needs a Universal Serial Bus (USB), etc. in order to expand functionality, the function unit640may function as an interface controller. The semiconductor device100a,100b,100c,or100dfabricated in accordance with the embodiments of the inventive concept may be included in the function unit640. FIG.20is a block diagram conceptually illustrating an electronic system including the semiconductor device100a,100b,100c,or100dfabricated in accordance with various embodiments of the inventive concept. Referring toFIG.20, an electronic system700may include the semiconductor device100a,100b,100c,or100dfabricated in accordance with the embodiments of the inventive concept. The electronic system700may be applied to a mobile electronic apparatus or a computer. For example, the electronic system700may include a memory system712, a microprocessor714, a random access memory (RAM)716, and a user interface718which performs data communication using a bus720. The microprocessor714may program and control the electronic system700. The RAM716may be used as an operational memory of the microprocessor714. For example, the microprocessor714or the RAM716may include one of the semiconductor devices100a,100b,100c,and100dfabricated in accordance with the embodiments of the inventive concept. The microprocessor714, the RAM716, and/or other components may be assembled in a single package. The user interface718may be used to input data to or output data from the electronic system700. The memory system712may store codes for operating the microprocessor714, data processed by the microprocessor714, or external input data. The memory system712may include a controller and a memory device. As set forth above, a semiconductor device according to various embodiments of the inventive concept may include a crystal growth source/drain having a left-right asymmetric shape. Due to the asymmetric shape of the source/drain, a contact area of the source/drain can be further secured, and thus on-current characteristics of the semiconductor device can be improved. Other devices, methods, and/or systems according to embodiments of present inventive concepts will be or become apparent to one with skill in the art upon review of the drawings and detailed description. It is intended that all such additional devices and/or systems be included within this description, be within the scope of present inventive concepts, and be protected by the accompanying claims. Moreover, it is intended that all embodiments disclosed herein can be implemented separately or combined in any way and/or combination. In the drawings and specification, there have been disclosed typical embodiments and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. The foregoing was for illustration of the embodiments only and is not to be construed as limiting thereof Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings, advantages and scope of the inventive concept as defined by the following claims. | 52,391 |
11942516 | DETAILED DESCRIPTION Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and an adjacent second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack. The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits (“qubits”) in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices. In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C). The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “under,” “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. As used herein, a “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide. As used herein, a “magnet line” refers to a magnetic field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots. One example of a magnet line, as discussed herein, is a conductive pathway that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area. FIGS.1-3are cross-sectional views of a quantum dot device100, in accordance with various embodiments. In particular,FIG.2illustrates the quantum dot device100taken along the section A-A ofFIG.1(whileFIG.1illustrates the quantum dot device100taken along the section C-C ofFIG.2), andFIG.3illustrates the quantum dot device100taken along the section B-B ofFIG.1with a number of components not shown to more readily illustrate how the gates106/108and the magnet line121may be patterned (whileFIG.1illustrates a quantum dot device100taken along the section D-D ofFIG.3). AlthoughFIG.1indicates that the cross-section illustrated inFIG.2is taken through the fin104-1, an analogous cross-section taken through the fin104-2may be identical, and thus the discussion ofFIG.2refers generally to the “fin104.” The quantum dot device100may include a base102and multiple fins104extending away from the base102. The base102and the fins104may include a substrate and a quantum well stack (not shown inFIGS.1-3, but discussed below with reference to the substrate144and the quantum well stack146), distributed in any of a number of ways between the base102and the fins104. The base102may include at least some of the substrate, and the fins104may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer152). Examples of base/fin arrangements are discussed below with reference to the base fin arrangements158ofFIGS.49-55. Although only two fins,104-1and104-2, are shown inFIGS.1-3, this is simply for ease of illustration, and more than two fins104may be included in the quantum dot device100. In some embodiments, the total number of fins104included in the quantum dot device100is an even number, with the fins104organized into pairs including one active fin104and one read fin104, as discussed in detail below. When the quantum dot device100includes more than two fins104, the fins104may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a 1×2N line, or a 2×N line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4×N/2 array, a 6×N/3 array, etc.). The discussion herein will largely focus on a single pair of fins104for ease of illustration, but all the teachings of the present disclosure apply to quantum dot devices100with more fins104. As noted above, each of the fins104may include a quantum well layer (not shown inFIGS.1-3, but discussed below with reference to the quantum well layer152). The quantum well layer included in the fins104may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device100, as discussed in further detail below. The quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins104, and the limited extent of the fins104(and therefore the quantum well layer) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins104. To control the x-location of quantum dots in the fins104, voltages may be applied to gates disposed on the fins104to adjust the energy profile along the fins104in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates106/108). The dimensions of the fins104may take any suitable values. For example, in some embodiments, the fins104may each have a width162between 10 nanometers and 30 nanometers. In some embodiments, the fins104may each have a vertical dimension164between 200 nanometers and 400 nanometers (e.g., between 250 nanometers and 350 nanometers, or equal to 300 nanometers). The fins104may be arranged in parallel, as illustrated inFIGS.1and3, and may be spaced apart by an insulating material128, which may be disposed on opposite faces of the fins104. The insulating material128may be a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. For example, in some embodiments, the fins104may be spaced apart by a distance160between 100 nanometers and 250 nanometers. Multiple gates may be disposed on each of the fins104. In the embodiment illustrated inFIG.2, three gates106and two gates108are shown as distributed on the top of the fin104. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, as discussed below with reference toFIG.82, multiple groups of gates (like the gates illustrated inFIG.2) may be disposed on the fin104. As shown inFIG.2, the gate108-1may be disposed between the gates106-1and106-2, and the gate108-2may be disposed between the gates106-2and106-3. A gate106may be spaced apart from an adjacent gate108at least partially by a gate wall138. The gate walls138may include two different dielectric materials. For example, a gate wall138may include a barrier layer113and a spacer134. The barrier layer113may have an L-shape in cross-section, with a vertical portion adjacent to the gate dielectric114-1of an adjacent gate106, and a horizontal portion under the associated spacer134. The vertical portion of the barrier layer113of a gate wall138may be disposed between the gate dielectric114-1of an adjacent gate106and the spacer134of that gate wall138. The horizontal portion of the barrier layer113of a gate wall138may be disposed between the fin104and the spacer134of that gate wall138. The spacer134of a gate wall138may be disposed between the vertical portion of the associated barrier layer113and the gate dielectric114-2of a gate108. As illustrated inFIG.2, the spacers134may be thicker closer to the fin104and thinner farther away from the fin104. In some embodiments, the spacers134may have a convex shape. The spacers134may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). The barrier layer113may be formed of any suitable material (different from the spacers134), such as aluminum oxide, silicon carbide, silicon nitride, an interlayer dielectric material, or any suitable etch stop material. In some embodiments, the barrier layer113may only be present at the bottom of the spacers134(between the spacers134and the fin104), and not at the sidewalls of the spacers134(e.g., not between the spacers134and the adjacent gate dielectric114). Each of the gates106/108may include a gate dielectric114(e.g., the gate dielectric114-1of the gates106, and the gate dielectric114-2of the gates108, as illustrated inFIG.2). In some embodiments, the gate dielectric114-1of the gates106disclosed herein may have a different material composition or material structure than the gate dielectric114-2of the gates108disclosed herein. In some embodiments, the gate dielectric114-1of the gates106disclosed herein may have a same material composition or material structure as the gate dielectric114-2of the gates108disclosed herein. In some embodiments, a gate dielectric114may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin104and the corresponding gate metal). The gate dielectric114may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric114may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric114may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric114to improve the quality of the gate dielectric114. Although the gate dielectrics114-1and114-2for the gates106and108, respectively, are shown in various ones of the accompanying figures as distinct, non-materially continuous portions of gate dielectric114, in other embodiments of the quantum dot devices100disclosed herein, the gate dielectrics114-1and114-2may be provided by a single, common layer of gate dielectric114on the fin104(between the fin104and the gate metals110/112, discussed further below). Each of the gates106may also include a gate metal110. The gate dielectric114-1for each gate106may extend at least partially up the sides of the adjacent barrier layer113of a gate wall138(forming a “U” shape), and the gate metal110may extend between the portions of gate dielectric114-1on the adjacent barrier layer113, as shown. In some embodiments, the gate metal110may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. Each of the gates108may include a gate metal112and a gate dielectric114-2. The gate dielectric114-2for each gate108may have a bottom portion that extends at least partially up the sides of the adjacent gate walls138(contacting the spacer134and the barrier layer113under the spacer134of a gate wall138), forming a “U” shape in cross-section. The gate dielectric114-1for each gate108may also have a top portion that contacts insulating material130adjacent to the gate108, and extends over the adjacent gates106; thus, the gates108may have a “T”-shape. The gate metal112may extend between the portions of gate dielectric114-2on the adjacent gate walls138and different adjacent portions of the insulating material130, as shown. The gates108may be “taller” than the adjacent gates106and may extend at least partially over the adjacent gates106so as to “overlap” them. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate dielectric114-1of the gate106is at least partially disposed between the fin104and the gate dielectric114-2of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate metal110of the gate106is at least partially disposed between the fin104and the gate dielectric114-2of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate dielectric114-1of the gate106is at least partially disposed between the fin104and the gate metal112of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate metal110of the gate106is at least partially disposed between the fin104and the gate metal112of the adjacent gate108. The gate108may extend over, and may be in contact with, a top surface of a cap118-1on the gate metal110of an adjacent gate106. A cap118-1may extend over the gate metal110of the gates106; the bottom surface of the cap118-1may contact the gate metal110, while side faces of the cap118-1may contact the gate dielectric114-1. Similarly, a cap118-2may extend over the gate metal112of the gates108; the bottom surface of the cap118-2may contact the gate metal112, while side faces of the cap118-2may contact the gate dielectric114-2. In some embodiments, no caps118-2may be present in a quantum dot device100. The caps118may be formed of silicon nitride, silicon carbide, or another suitable material. The caps118-1may help insulate the gate metal110of a gate106from the gate metal112of an adjacent gate108, reducing the likelihood of an undesirable short or leak. In some embodiments, the gate metal112and the gate metal110may have the same material structure; in other embodiments, the gate metal112may have a different material structure from the gate metal110. In particular, in some embodiments, the material structures of the gate metals110and112may be different and may be selected so as to induce strain in the underlying material layers (including the quantum well layer152). As used herein, two materials may have a same “material structure” when their chemical composition and internal strain are approximately the same; two materials may have a different “material structure” when their chemical composition and/or their internal strain differ. As used herein, a “relaxed” material may be a material that is substantially free from compressive or tensile strain, while a “strained” material may be a material exhibiting compressive or tensile strain. Strain in the quantum well layer152may improve the mobility of the carriers that flow therein, which may improve performance. In particular, tensile strain may improve electron mobility (and thus may be useful for quantum dot devices100in which electrons are the carriers of interest, as discussed above) and compressive strain may improve hole mobility (and thus may be useful for quantum dot devices100in which holes are the carriers of interest, as discussed above). Strain may also increase valley splitting, and may also be used to define the location of quantum dots142by improved electric field control, both of which may be advantageous for the operation of a quantum dot device100. The strain induced in the underlying material layers by the gate metal110/112may not be uniform through these underlying material layers, but may vary along the material layers depending upon the relative location below the gate metal110/112. For example, the region of a quantum well layer152below the gate metal110may be tensilely strained, while the region below the gate metal112may be compressively strained (or vice versa). In some embodiments, the region of a quantum well layer152below the gate metal110may be tensilely (compressively) strained, and the region below the gate metal112may be tensilely (compressively) strained as well, but by a different amount. The gate metals110and112may be selected to achieve a particular differential strain landscape in the underlying material layers (e.g., in the quantum well layer152) that may improve the electric field control of the potential energies in these material layers (e.g., the “barrier” and “plunger” potentials, as discussed below). In some embodiments, the gate metal110and or the gate metal112itself may be strained (e.g., with strain induced during deposition, as known in the art). In other embodiments, the differential strain induced in the quantum well layer152may be a function of the interaction between the gate metals110/112and the adjacent materials (e.g., the gate dielectric114, a barrier layer156(discussed below), etc.). Differential strain may be induced in the quantum well layer152by the gate metal110/112in a number of ways. For example, differential strain may be induced in the quantum well layer152when the gate metal110is formed of different metal than the gate metal112. For example, in some embodiments, the gate metal110may be a superconductor while the gate metal112is a non-superconductor (or vice versa). In some embodiments, the gate metal110may be titanium nitride while the gate metal112is a metal different than titanium nitride (e.g., aluminum or niobium titanium nitride) (or vice versa). In some embodiments, the gate metal110and the gate metal112may be different non-magnetic metals. Even when the gate metal110and the gate metal112include the same metal, differential strain may be induced in the quantum well layer152(and other intervening material layers) when the gate metal110and the gate metal112are deposited under different conditions (e.g., precursors, time, temperature, pressure, deposition technique, etc.). For example, the gate metal110and the gate metal112may be deposited using the same technique (e.g., atomic layer deposition, electroless deposition, electroplating, or sputtering), but the parameters and/or materials of these deposition processes may be different, resulting in different structures of the gate metals110/112and therefore differential strain in the underlying material layers. In some embodiments, the thin film deposition of the gate metals110/112may induce strain in the underlying quantum well layer152. Although various ones of the accompanying figures illustrate “alternating” gate metals110and112, a quantum dot device may include more than two different gate metals that have different material structures, and these different gate metals may be arranged in any desired manner to achieve a desired strain landscape in the underlying material layers. For example, in some embodiments, three or more gate metals with different material structures may be used in place of the gate metals110/112to achieve a desired strain landscape in a quantum well layer152. The gate108-1may extend between the proximate gate walls138on the sides of the gate106-1and the gate106-2, as shown inFIG.2. In some embodiments, the gate metal112and the bottom portion of the gate dielectric114-2of the gate108-1may together extend between the gate walls138on the sides of the gate106-1and the gate106-2. Thus, the gate metal112and the bottom portion of the gate dielectric114-2of the gate108-1together may have a shape that is substantially complementary to the shape of the gate walls138, as shown. Similarly, the gate108-2may extend between the proximate gate walls138on the sides of the gate106-2and the gate106-3. The dimensions of the gates106/108may take any suitable values. For example, in some embodiments, the z-height166of the gates106may be between 30 nanometers and 120 nanometers (e.g., approximately 50 nanometers); the z-height175of the gates108may be in the same range, and may be greater than the z-height166of the gates106. In some embodiments, the length168of the gate metal110(i.e., in the x-direction) at its base may be between 20 nanometers and 60 nanometers (e.g., 40 nanometers). In some embodiments, the length170of the gate metal112at its base may be between 20 nanometers and 60 nanometers (e.g., 40 nanometers). The pitch of adjacent ones of the gates106may be between 50 nanometers and 150 nanometers (e.g., 100 nanometers). In some embodiments, the thickness172of the gate walls138may be between 1 nanometer and 15 nanometers (e.g., between 3 nanometers and 5 nanometers, between 4 nanometers and 6 nanometers, or between 4 nanometers and 7 nanometers). In some embodiments, the thickness174of the vertical portion of the barrier layer113may be between 5 Angstroms and 20 Angstroms (e.g., between 8 Angstroms and 15 Angstroms); the thickness of the horizontal portion of the barrier layer113(i.e., the thickness between the fin104and the associated spacer134) may also be between 5 Angstroms and 20 Angstroms (e.g., between 8 Angstroms and 15 Angstroms). The length170of the gate metal112(i.e., in the x-direction) may depend on the dimensions of the gates106and the gate walls138, as illustrated inFIG.2. As indicated inFIG.1, the gates106/108on one fin104may extend over the insulating material128beyond their respective fins104and towards the other fin104, but may be isolated from their counterpart gates by the intervening insulating material130(and gate walls138for the gates106). Although all of the gates106are illustrated in the accompanying drawings as having the same length168of the gate metal110, in some embodiments, the “outermost” gates106(e.g., the gates106-1and106-3of the embodiment illustrated inFIG.2) may have a greater length168than the “inner” gates106(e.g., the gate106-2in the embodiment illustrated inFIG.2). For example, in some embodiments, the outermost gates106may have a length168between 100 nanometers and 500 nanometers. Such longer “outside” gates106may provide spatial separation between the doped regions140and the areas under the gates108and the inner gates106in which quantum dots142may form, and thus may reduce the perturbations to the potential energy landscape under the gates108and the inner gates106caused by the doped regions140. In some embodiments, during operation of the quantum dot device100, a 2DEG may form under the outermost gates106; this 2DEG may separate the “active” device region (under the gates106/108) from the doped region140(which has a large density of implanted charge carriers). As shown inFIG.2, the gates106and108may be alternatingly arranged along the fin104in the x-direction. During operation of the quantum dot device100, voltages may be applied to the gates106/108to adjust the potential energy in the quantum well layer (not shown) in the fin104to create quantum wells of varying depths in which quantum dots142may form. Only one quantum dot142is labeled with a reference numeral inFIGS.2and3for ease of illustration, but five are indicated as dotted circles in each fin104. The location of the quantum dots142inFIG.2is not intended to indicate a particular geometric positioning of the quantum dots142. The gate walls138may themselves provide “passive” barriers between quantum wells under the gates106/108in the quantum well layer, and the voltages applied to different ones of the gates106/108may adjust the potential energy under the gates106/108in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers. The fins104may include doped regions140that may serve as a reservoir of charge carriers for the quantum dot device100. For example, an n-type doped region140may supply electrons for electron-type quantum dots142, and a p-type doped region140may supply holes for hole-type quantum dots142. In some embodiments, an interface material141may be disposed at a surface of a doped region140, as shown. The interface material141may facilitate electrical coupling between a conductive contact (e.g., a conductive via136, as discussed below) and the doped region140. The interface material141may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region140includes silicon, the interface material141may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference toFIGS.31-32). In some embodiments, the interface material141may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material141may be a metal (e.g., aluminum, tungsten, or indium). The quantum dot devices100disclosed herein may be used to form electron-type or hole-type quantum dots142. Note that the polarity of the voltages applied to the gates106/108to form quantum wells/barriers depend on the charge carriers used in the quantum dot device100. In embodiments in which the charge carriers are electrons (and thus the quantum dots142are electron-type quantum dots), amply negative voltages applied to a gate106/108may increase the potential barrier under the gate106/108, and amply positive voltages applied to a gate106/108may decrease the potential barrier under the gate106/108(thereby forming a potential well in which an electron-type quantum dot142may form). In embodiments in which the charge carriers are holes (and thus the quantum dots142are hole-type quantum dots), amply positive voltages applied to a gate106/108may increase the potential barrier under the gate106/108, and amply negative voltages applied to a gate106and108may decrease the potential barrier under the gate106/108(thereby forming a potential well in which a hole-type quantum dot142may form). The quantum dot devices100disclosed herein may be used to form electron-type or hole-type quantum dots. Voltages may be applied to each of the gates106and108separately to adjust the potential energy in the quantum well layer under the gates106and108, and thereby control the formation of quantum dots142under each of the gates106and108. Additionally, the relative potential energy profiles under different ones of the gates106and108allow the quantum dot device100to tune the potential interaction between quantum dots142under adjacent gates. For example, if two adjacent quantum dots142(e.g., one quantum dot142under a gate106and another quantum dot142under a gate108) are separated by only a short potential barrier, the two quantum dots142may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate106/108may be adjusted by adjusting the voltages on the respective gates106/108, the differences in potential between adjacent gates106/108may be adjusted, and thus the interaction tuned. In some applications, the gates108may be used as plunger gates to enable the formation of quantum dots142under the gates108, while the gates106may be used as barrier gates to adjust the potential barrier between quantum dots142formed under adjacent gates108. In other applications, the gates108may be used as barrier gates, while the gates106are used as plunger gates. In other applications, quantum dots142may be formed under all of the gates106and108, or under any desired subset of the gates106and108. Conductive vias and lines may contact the gates106/108, and to the doped regions140, to enable electrical connection to the gates106/108and the doped regions140to be made in desired locations. As shown inFIGS.1-3, the gates106may extend away from the fins104, and conductive vias120may contact the gates106(and are drawn in dashed lines inFIG.2to indicate their location behind the plane of the drawing). The conductive vias120may extend through the caps118-1to contact the gate metal110of the gates106. The gates108may extend away from the fins104, and conductive vias122may contact the gates108(also drawn in dashed lines inFIG.2to indicate their location behind the plane of the drawing). The conductive vias122may extend through the caps118-2to contact the gate metal112of the gates108. Conductive vias136may contact the interface material141and may thereby make electrical contact with the doped regions140. The quantum dot device100may include further conductive vias and/or lines (not shown) to make electrical contact to the gates106/108and/or the doped regions140, as desired. The conductive vias and lines included in a quantum dot device100may include any suitable materials, such as copper, tungsten (deposited, e.g., by chemical vapor deposition (CVD)), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium). During operation, a bias voltage may be applied to the doped regions140(e.g., via the conductive vias136and the interface material141) to cause current to flow through the doped regions140. When the doped regions140are doped with an n-type material, this voltage may be positive; when the doped regions140are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts). The quantum dot device100may include one or more magnet lines121. For example, a single magnet line121is illustrated inFIGS.1-3proximate to the fin104-1. The magnet line121may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots142that may form in the fins104. In some embodiments, the magnet line121may conduct a pulse to reset (or “scramble”) nuclear and/or quantum dot spins. In some embodiments, the magnet line121may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, the magnet line121may conduct current to provide a continuous, oscillating magnetic field to which the spin of a qubit may couple. The magnet line121may provide any suitable combination of these embodiments, or any other appropriate functionality. In some embodiments, the magnet line121may be formed of copper. In some embodiments, the magnet line121may be formed of a superconductor, such as aluminum. The magnet line121illustrated inFIGS.1-3is non-coplanar with the fins104, and is also non-coplanar with the gates106/108. In some embodiments, the magnet line121may be spaced apart from the gates106/108by a distance167. The distance167may take any suitable value (e.g., based on the desired strength of magnetic field interaction with the quantum dots142); in some embodiments, the distance167may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers). In some embodiments, the magnet line121may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material130to provide a permanent magnetic field in the quantum dot device100. The magnet line121may have any suitable dimensions. For example, the magnet line121may have a thickness169between 25 nanometers and 100 nanometers. The magnet line121may have a width171between 25 nanometers and 100 nanometers. In some embodiments, the width171and thickness169of a magnet line121may be equal to the width and thickness, respectively, of other conductive lines in the quantum dot device100(not shown) used to provide electrical interconnects, as known in the art. The magnet line121may have a length173that may depend on the number and dimensions of the gates106/108that are to form quantum dots142with which the magnet line121is to interact. The magnet line121illustrated inFIGS.1-3(and the magnet lines121illustrated inFIGS.43-45below) are substantially linear, but this need not be the case; the magnet lines121disclosed herein may take any suitable shape. Conductive vias123may contact the magnet line121. The conductive vias120,122,136, and123may be electrically isolated from each other by an insulating material130. The insulating material130may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material130may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias120/122/136/123may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, conductive lines (not shown) included in the quantum dot device100may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias shown inFIGS.1-3is simply illustrative, and any electrical routing arrangement may be implemented. As discussed above, the structure of the fin104-1may be the same as the structure of the fin104-2; similarly, the construction of gates106/108on the fin104-1may be the same as the construction of gates106/108on the fin104-2. The gates106/108on the fin104-1may be mirrored by corresponding gates106/108on the parallel fin104-2, and the insulating material130may separate the gates106/108on the different fins104-1and104-2. In particular, quantum dots142formed in the fin104-1(under the gates106/108) may have counterpart quantum dots142in the fin104-2(under the corresponding gates106/108). In some embodiments, the quantum dots142in the fin104-1may be used as “active” quantum dots in the sense that these quantum dots142act as qubits and are controlled (e.g., by voltages applied to the gates106/108of the fin104-1) to perform quantum computations. The quantum dots142in the fin104-2may be used as “read” quantum dots in the sense that these quantum dots142may sense the quantum state of the quantum dots142in the fin104-1by detecting the electric field generated by the charge in the quantum dots142in the fin104-1, and may convert the quantum state of the quantum dots142in the fin104-1into electrical signals that may be detected by the gates106/108on the fin104-2. Each quantum dot142in the fin104-1may be read by its corresponding quantum dot142in the fin104-2. Thus, the quantum dot device100enables both quantum computation and the ability to read the results of a quantum computation. The quantum dot devices100disclosed herein may be manufactured using any suitable techniques.FIGS.4-42illustrate various example stages in the manufacture of the quantum dot device100ofFIGS.1-3, in accordance with various embodiments. Although the particular manufacturing operations discussed below with reference toFIGS.4-42are illustrated as manufacturing a particular embodiment of the quantum dot device100, these operations may be applied to manufacture many different embodiments of the quantum dot device100, as discussed herein. Any of the elements discussed below with reference toFIGS.4-42may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). FIG.4illustrates a cross-sectional view of an assembly200including a substrate144. The substrate144may include any suitable semiconductor material or materials. In some embodiments, the substrate144may include a semiconductor material. For example, the substrate144may include silicon (e.g., may be formed from a silicon wafer). Various embodiments of the substrate144are discussed below with reference toFIGS.46-48. FIG.5illustrates a cross-sectional view of an assembly202subsequent to providing a quantum well stack146on the substrate144of the assembly200(FIG.4). The quantum well stack146may include a quantum well layer (not shown) in which a 2DEG may form during operation of the quantum dot device100. Various embodiments of the quantum well stack146are discussed below with reference toFIGS.46-48. FIG.6illustrates a cross-sectional view of an assembly204subsequent to forming fins104in the assembly202(FIG.5). The fins104may extend from a base102, and may be formed in the assembly202by patterning and then etching the assembly202, as known in the art. For example, a combination of dry and wet etch chemistry may be used to form the fins104, and the appropriate chemistry may depend on the materials included in the assembly202, as known in the art. At least some of the substrate144may be included in the base102, and at least some of the quantum well stack146may be included in the fins104. In particular, the quantum well layer (not shown) of the quantum well stack146may be included in the fins104. Example arrangements in which the quantum well stack146and the substrate144are differently included in the base102and the fins104are discussed below with reference toFIGS.49-55. FIG.7illustrates a cross-sectional view of an assembly206subsequent to providing an insulating material128to the assembly204(FIG.6). Any suitable material may be used as the insulating material128to electrically insulate the fins104from each other. As noted above, in some embodiments, the insulating material128may be a dielectric material, such as silicon oxide. FIG.8illustrates a cross-sectional view of an assembly208subsequent to planarizing the assembly206(FIG.7) to remove the insulating material128above the fins104. In some embodiments, the assembly206may be planarized using a chemical mechanical polishing (CMP) technique. FIG.9is a perspective view of at least a portion of the assembly208, showing the fins104extending from the base102and separated by the insulating material128. The cross-sectional views ofFIGS.4-8are taken parallel to the plane of the page of the perspective view ofFIG.9.FIG.10is another cross-sectional view of the assembly208, taken along the dashed line along the fin104-1inFIG.9. The cross-sectional views illustrated inFIGS.11-33,35,37,39, and41are taken along the same cross-section asFIG.10. The cross-sectional views illustrated inFIGS.34,36,38,40, and42are taken along the same cross-section asFIG.8. FIG.11is a cross-sectional view of an assembly210subsequent to depositing a dummy material111on the fins104of the assembly208(FIGS.8-10). The dummy material111may include any material that may be selectively etched without etching the barrier layer113, the spacers134, or the dummy material109(discussed below). In some embodiments, the dummy material111may include polysilicon. FIG.12is a cross-sectional view of an assembly211subsequent to patterning the dummy material111of the assembly210(FIG.11). The pattern applied to the dummy material111may correspond to the locations for the gates106, as discussed below. The dummy material111may be patterned by applying a resist, patterning the resist using lithography, and then etching the dummy material111(using dry etching or any appropriate technique). FIG.13is a cross-sectional view of an assembly212subsequent to depositing a conformal layer of the barrier layer113on the dummy material111and the exposed fin104of the assembly211(FIG.12). Any suitable technique may be used to deposit the barrier layer113, such as atomic layer deposition (ALD). In some embodiments, the barrier layer113may be deposited to a thickness between 5 Angstroms and 20 Angstroms (e.g., between 8 Angstroms and 15 Angstroms). The barrier layer113may help protect the fin104(and in particular, the quantum well stack146) from damage during subsequent manufacturing operations. FIG.14is a cross-sectional view of an assembly213subsequent to providing spacer material132on the assembly212(FIG.13). The spacer material132may include any of the materials discussed above with reference to the spacers134, for example, and may be deposited using any suitable technique. For example, the spacer material132may be a nitride material (e.g., silicon nitride) deposited by sputtering. FIG.15is a cross-sectional view of an assembly214subsequent to etching the spacer material132of the assembly213(FIG.14), leaving spacers134formed of the spacer material132on the barrier layer113on the side faces of the dummy material111. The etching of the spacer material132may be an anisotropic etch, etching the spacer material132“downward” to remove the spacer material132on top of the barrier layer113/dummy material111structures and in some of the area between these structures, while leaving the spacers134on the barrier layer113on the side faces of the dummy material111. In some embodiments, the anisotropic etch may be a dry etch, and may be selective to the spacer material132so as to not significantly etch the barrier layer113. In some embodiments, the etch of the spacer material132may be controlled so as to “overetch” into the barrier layer113, causing recesses in the barrier layer113, to help ensure that the spacer material132has been fully removed as desired. FIG.16is a cross-sectional view of an assembly215subsequent to providing another dummy material109on the assembly214(FIG.15). The dummy material109may include any material that may be selectively etched without etching the barrier layer113, the spacers134, the gate metal110, or the gate dielectric114-1. In some embodiments, the dummy material109may include silicon oxide. The dummy material109may fill the areas between adjacent ones of the barrier layer113/dummy material111structures, and may extend over the tops of these structures, as shown. In some embodiments, the dummy material109may be an insulating material, and may remain in the quantum dot device100as an insulating material in an area away from the gates106/108. FIG.17is a cross-sectional view of an assembly216subsequent to planarizing the assembly215(FIG.16) to remove the barrier layer113and the dummy material109above the dummy material111. In some embodiments, the assembly215may be planarized using a CMP technique. Some of the remaining dummy material109may fill the areas between adjacent ones of the barrier layer113/dummy material111structures, while other portions of the remaining dummy material109may be located “outside” of the barrier layer113/dummy material111structures. FIG.18is a cross-sectional view of an assembly217subsequent to removing the dummy material111from the assembly216(FIG.17) to form cavities103. Any suitable technique may be used to remove the dummy material111, such as an etch technique that is selective to the dummy material111while leaving the barrier layer113, the spacers134, and the dummy material109in place. As illustrated inFIG.18, the barrier layer113may provide the sidewalls of the cavities103, and the fin104may provide the bottom of the cavities103. FIG.19is a cross-sectional view of an assembly218subsequent to conformally depositing a layer of the gate dielectric114-1on the assembly217(FIG.18). The gate dielectric114may cover the sidewalls of the cavities103(on the barrier layer113) and the bottom of the cavities103(on the fin104). Any suitable technique may be used to deposit the gate dielectric114-1, such as ALD. FIG.20is a cross-sectional view of an assembly219subsequent to depositing the gate metal110on the assembly218(FIG.19). The gate metal110may fill the cavities103of the assembly218, and may extend over the dummy material109, as shown. FIG.21is a cross-sectional view of an assembly220subsequent to planarizing the assembly219(FIG.20) to remove the gate dielectric114-1and the gate metal110above the dummy material109. In some embodiments, the assembly219may be planarized using a CMP technique. In the assembly220, the dummy material109may be exposed, as shown. The gate metal110along with the adjacent gate dielectric114-1may provide the gates106, as discussed above with reference toFIGS.1-3. FIG.22is a cross-sectional view of an assembly221subsequent to recessing the gate metal110of the assembly220(FIG.21), forming caps118-1on the recessed gate metal110, and then removing the dummy material109. Any suitable technique may be used to recess the gate metal110to a desired depth (e.g., a metal etch), and any suitable technique may be used to form the caps118-1(e.g., a deposition followed by a polish operation). Any suitable technique may be used to remove the dummy material109, such as an etch technique that is selective to the dummy material109while leaving the barrier layer113, the spacers134, the gate dielectric114-1, and the caps118-1in place. FIG.23is a cross-sectional view of an assembly222subsequent to removing the barrier layer113that is exposed on the fin104from the assembly221(FIG.22). The barrier layer113that is part of the gate walls138(i.e., the vertical portion of the barrier layer113between the gate dielectric114-1and a spacer134, and the horizontal portion of the barrier layer113between the spacers134and the fin104) remains in the assembly222. In some embodiments, the barrier layer113that is exposed on the fin104may be removed by a short wet etch. FIG.24is a cross-sectional view of an assembly224subsequent to providing an insulating material130on the assembly222(FIG.23). The insulating material130may take any of the forms discussed above. For example, the insulating material130may be a dielectric material, such as silicon oxide. The insulating material130may be provided on the assembly234using any suitable technique, such as spin coating, CVD, or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material130may be polished back after deposition, and before further processing. FIG.25is a cross-sectional view of an assembly225subsequent to forming openings119in the insulating material130of the assembly224(FIG.24). The openings119may be formed between adjacent ones of the gates106, and may expose portions of the fins104and the adjacent gate walls138. Portions of the insulating material130may be left on top of “interior” ones of the gates106, as illustrated inFIG.25. The openings119may be formed using any suitable technique (e.g., a lithography operation). For example, the openings119may be formed using a single- or double-pass lithography operation, followed by an etch of the insulating material130. This etch may be performed in a single stage in embodiments in which the insulating material130between the gates106has a same material composition as the insulating material130above the gates106, or may be performed in two stages in embodiments in which the insulating material130between the gates has a different material composition as the insulating material130above the gates106. FIG.26is a cross-sectional view of an assembly226subsequent to conformally depositing a layer of the gate dielectric114-2on the assembly225(FIG.25). This gate dielectric114-2may cover the “walls” of the openings119, covering the exposed portions of the fin104and extending over the gate walls138and the gates106. The gate dielectric114-2may have “shoulders” where the gate dielectric goes over the tops of the gate walls138, as shown. Any suitable technique may be used to deposit the gate dielectric114-2, such as ALD. FIG.27is a cross-sectional view of an assembly227subsequent to depositing the gate metal112on the assembly226(FIG.26). The gate metal112may fill the remainder of the openings119, filling the spaces between the gates106, and may extend “outside” of the area between the gates106. FIG.28is a cross-sectional view of an assembly228subsequent to planarizing the assembly227(FIG.27) to remove the gate dielectric114-2and the gate metal112above the gates106. In some embodiments, the assembly227may be planarized using a CMP technique. FIG.29is a cross-sectional view of an assembly229subsequent to recessing the gate metal112of the assembly228(FIG.28), and forming caps118-2on the recessed gate metal112. Any suitable technique may be used to recess the gate metal112to a desired depth (e.g., a metal etch), and any suitable technique may be used to form the caps118-2(e.g., a deposition followed by a polish operation). In embodiments in which no caps118-2are present in a quantum computing device100, the operations ofFIG.29may not be performed. FIG.30is a cross-sectional view of an assembly230subsequent to patterning the insulating material130of the assembly229(FIG.29) to remove the insulating material “outside” of the footprint of the gates106/108, and doping the fins104to form doped regions140in the portions of the fins104“outside” of the gates106/108. The insulating material130may be patterned using any suitable technique (e.g., applying a resist, patterning the resist using lithography, etching the insulating material130using dry etching or any appropriate technique, and then removing the resist). The type of dopant used to form the doped regions140may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when the quantum dot142is to be an electron-type quantum dot142, the doped regions140may be formed by ion implantation of phosphorous, arsenic, or another n-type material. When the quantum dot142is to be a hole-type quantum dot142, the doped regions140may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the fins104may follow the ion implantation process. The depth of the doped regions140may take any suitable value; for example, in some embodiments, the doped regions140may extend into the fin104to a depth115between 500 Angstroms and 1000 Angstroms. The “outermost” gate walls138may provide a doping boundary, limiting diffusion of the dopant from the doped regions140into the area under the gates106/108. As shown, the doped regions140may extend under the adjacent outer gate walls138. In some embodiments, the doped regions140may extend past the outer gate walls138and under the gate dielectric114-1of the outer gates106, may extend only to the boundary between the outer spacers134and the adjacent gate metal110, or may terminate under the outer gate walls138and not reach the boundary between the outer gate walls138and the adjacent gate dielectric114-1. The doping concentration of the doped regions140may, in some embodiments, be between 1017/cm3and 1020/cm3. In other embodiments, the doped regions140may be formed before the gates106/108are formed, instead of after the gates106/108are formed. In such embodiments, a patterned implant mask may be disposed on the fins104, the doped regions140may be formed in accordance with the pattern of the patterned implant mask, and the patterned implant mask may be removed before forming the gates106/108. Such embodiments may advantageously allow the annealing of the doped regions140(e.g., to activate the dopants therein) before the gates106/108are formed, and may improve the controllability of the overlap between the outermost gates106/108and the doped regions140. In some other embodiments, the doped regions140may be formed after the gates106/108are formed, and a patterned implant mask may also be used. In some such embodiments, after the gates106/108are formed, a patterned hardmask would be applied, the gate dielectric114-2not protected by the patterned hardmask would be removed, the implant would be performed to form the doped regions140, the patterned hardmask would be stripped, an insulating material (e.g., an oxide) would be deposited and planarized, and then a new hardmask would be applied to proceed with the process of forming conductive contacts (as discussed below). FIG.31is a cross-sectional side view of an assembly232subsequent to providing a layer of nickel or other material143over the assembly230(FIG.30). The nickel or other material143may be deposited on the assembly230using any suitable technique (e.g., a plating technique, CVD, or ALD). FIG.32is a cross-sectional side view of an assembly234subsequent to annealing the assembly232(FIG.31) to cause the material143to interact with the doped regions140to form the interface material141, then removing the unreacted material143. When the doped regions140include silicon and the material143includes nickel, for example, the interface material141may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference toFIG.31in order to form other interface materials141, including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example. More generally, the interface material141of the assembly234may include any of the materials discussed herein with reference to the interface material141. FIG.33is a cross-sectional view of an assembly236subsequent to providing an insulating material130on the assembly234(FIG.32). The insulating material130may take any of the forms discussed above. For example, the insulating material130may be a dielectric material, such as silicon oxide. The insulating material130may be provided on the assembly234using any suitable technique, such as spin coating, CVD, or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material130may be polished back after deposition, and before further processing. In some embodiments, the thickness131of the insulating material130provided on the assembly236(as measured from the cap118-1, as indicated inFIG.34) may be between 50 nanometers and 1.2 microns (e.g., between 50 nanometers and 300 nanometers).FIG.34is another cross-sectional view of the assembly236, taken along the section C-C ofFIG.33. FIG.35is a cross-sectional view of an assembly238subsequent to forming a trench125in the insulating material130of the assembly236(FIGS.33and34). The trench125may be formed using any desired techniques (e.g., resist patterning followed by etching), and may have a depth127and a width129that may take the form of any of the embodiments of the thickness169and the width171, respectively, discussed above with reference to the magnet line121.FIG.36is another cross-sectional view of the assembly238, taken along the section C-C ofFIG.35. FIG.37is a cross-sectional view of an assembly240subsequent to filling the trench125of the assembly238(FIGS.35and36) with a conductive material to form the magnet line121. The magnet line121may be formed using any desired techniques (e.g., plating followed by planarization, or a semi-additive process), and may take the form of any of the embodiments disclosed herein.FIG.38is another cross-sectional view of the assembly240, taken along the section C-C ofFIG.37. FIG.39is a cross-sectional view of an assembly242subsequent to providing additional insulating material130on the assembly240(FIGS.37and38). The insulating material130provided on the assembly240may take any of the forms of the insulating material130discussed above.FIG.40is another cross-sectional view of the assembly242, taken along the section C-C ofFIG.39. FIG.41is a cross-sectional view of an assembly244subsequent to forming, in the assembly242(FIGS.39and40), conductive vias120through the insulating material130(and the caps118-1) to contact the gate metal110of the gates106, conductive vias122through the insulating material130(and the caps118-2) to contact the gate metal112of the gates108, conductive vias136through the insulating material130to contact the interface material141of the doped regions140, and conductive vias123through the insulating material130to contact the magnet line121.FIG.42is another cross-sectional view of the assembly244, taken along the section C-C ofFIG.41. Further conductive vias and/or lines may be formed in the assembly244using conventional interconnect techniques, if desired. The resulting assembly244may take the form of the quantum dot device100discussed above with reference toFIGS.1-3. In the embodiment of the quantum dot device100illustrated inFIGS.1-3, the magnet line121is oriented parallel to the longitudinal axes of the fins104. In other embodiments, the magnet line121may not be oriented parallel to the longitudinal axes of the fins104. For example,FIGS.43-45are various cross-sectional views of an embodiment of a quantum dot device100having multiple magnet lines121, each proximate to the fins104and oriented perpendicular to the longitudinal axes of the fins104. Other than orientation, the magnet lines121of the embodiment ofFIGS.43-45may take the form of any of the embodiments of the magnet line121discussed above. The other elements of the quantum dot devices100ofFIGS.43-45may take the form of any of those elements discussed herein. The manufacturing operations discussed above with reference toFIGS.4-42may be used to manufacture the quantum dot device100ofFIGS.43-45. Although a single magnet line121is illustrated inFIGS.1-3, multiple magnet lines121may be included in that embodiment of the quantum dot device100(e.g., multiple magnet lines121parallel to the longitudinal axes of the fins104). For example, the quantum dot device100ofFIGS.1-3may include a second magnet line121proximate to the fin104-2in a symmetric manner to the magnet line121illustrated proximate to the fin104-1. In some embodiments, multiple magnet lines121may be included in a quantum dot device100, and these magnet lines121may or may not be parallel to one another. For example, in some embodiments, a quantum dot device100may include two (or more) magnet lines121that are oriented perpendicular to each other (e.g., one or more magnet lines121oriented like those illustrated inFIGS.1-3, and one or more magnet lines121oriented like those illustrated inFIGS.43-45). As discussed above, the base102and the fin104of a quantum dot device100may be formed from a substrate144and a quantum well stack146disposed on the substrate144. The quantum well stack146may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device100. The quantum well stack146may take any of a number of forms, several of which are discussed below with reference toFIGS.46-48. The various layers in the quantum well stacks146discussed below may be grown on the substrate144(e.g., using epitaxial processes). Although the singular term “layer” may be used to refer to various components of the quantum well stack146ofFIGS.46-48, any of the layers discussed below may include multiple materials arranged in any suitable manner. Layers other than the quantum well layer152in a quantum well stack146may have higher threshold voltages for conduction than the quantum well layer152so that when the quantum well layer152are biased at their threshold voltages, the quantum well layer152conducts and the other layers of the quantum well stack146do not. This may avoid parallel conduction in both the quantum well layer152and the other layers, and thus avoid compromising the strong mobility of the quantum well layer152with conduction in layers having inferior mobility. In some embodiments, silicon used in a quantum well stack146(e.g., in a quantum well layer152) may be grown from precursors enriched with the 28Si isotope. In some embodiments, germanium used in a quantum well stack146(e.g., in a quantum well layer152) may be grown from precursors enriched with the 70Ge, 72Ge, or 74Ge isotope. As noted above, different regions of a quantum well layer152of a quantum dot device100may be relaxed or strained (e.g., depending upon the differential material structure of the gate metals110and112proximate to those regions of the quantum well layer152). Further, when additional material layers in a quantum well stack are disposed between the quantum well layer152and the gate metal110/112(e.g., a barrier layer156, as discussed below), different regions of those material layers may be relaxed or strained depending upon the differential material structure of the gate metals110and112proximate to those regions of the material layers. FIG.46is a cross-sectional view of a quantum well stack146on a substrate144. The quantum well stack146may include a buffer layer154on the substrate144, and a quantum well layer152on the buffer layer154. In some embodiments of the quantum dot device100including the arrangement ofFIG.46, the gate dielectric114(not shown) of the gates106and/or the gates108may be directly on the quantum well layer152. The quantum well layer152may be formed of a material such that, during operation of the quantum dot device100, a 2DEG may form in the quantum well layer152proximate to the upper surface of the quantum well layer152. In some embodiments, the quantum well layer152ofFIG.46may be formed of intrinsic silicon, and the gate dielectric114(of the gates106and/or the gates108) may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. Embodiments in which the quantum well layer152ofFIG.46is formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices100. In some embodiments, the quantum well layer152ofFIG.46may be formed of intrinsic germanium, and the gate dielectric114may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device100, a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices100. The quantum well layers152disclosed herein may be differentially strained, with its strain induced by the gate metal110/112, as discussed above. The buffer layer154may be formed of the same material as the quantum well layer152(e.g., silicon or germanium), and may be present to trap defects that form in this material as it is grown on the substrate144. In some embodiments, the buffer layer154may be grown under different conditions (e.g., deposition temperature or growth rate) from the quantum well layer152. In particular, the quantum well layer152may be grown under conditions that achieve fewer defects than in the buffer layer154. FIG.47is a cross-sectional view of an arrangement including a quantum well stack146that includes a buffer layer154, a barrier layer156-1, a quantum well layer152, and an additional barrier layer156-2. The barrier layer156-1(156-2) may provide a potential barrier between the quantum well layer152and the buffer layer154(gate dielectric114, not shown). In some embodiments in which the quantum well layer152includes silicon or germanium, the barrier layers156may include silicon germanium. The germanium content of this silicon germanium may be between 20 atomic-percent and 80 atomic-percent (e.g., between 30 atomic-percent and 70 atomic-percent). In some embodiments of the arrangement ofFIG.47, the buffer layer154and the barrier layer156-1may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer154may have a germanium content that varies (e.g., continuously or in a stepwise manner) from the substrate144to the barrier layer156-1; for example, the silicon germanium of the buffer layer154may have a germanium content that varies from zero percent at the substrate to a nonzero percent (e.g., between 30 atomic-percent and 70 atomic-percent) at the barrier layer156-1. The barrier layer156-1may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer154may have a germanium content equal to the germanium content of the barrier layer156-1but may be thicker than the barrier layer156-1to absorb the defects that arise during growth. In some embodiments of the quantum well stack146ofFIG.47, the barrier layer156-2may be omitted. FIG.48is a cross-sectional view of another example quantum well stack146on an example substrate144. The quantum well stack146ofFIG.48may include an insulating layer155on the substrate144, a quantum well layer152on the insulating layer155, and a barrier layer156on the quantum well layer152. The presence of the insulating layer155may help confine carriers to the quantum well layer152, providing high valley splitting during operation. In some embodiments, the substrate144ofFIG.48may include silicon. The insulating layer155may include any suitable electrically insulating material. For example, in some embodiments, the insulating layer155may be an oxide (e.g., silicon oxide or hafnium oxide). The substrate144, the quantum well layer152, and/or the barrier layer156ofFIG.48may take the form of any of the embodiments disclosed herein. In some embodiments, the quantum well layer152may be formed on the insulating layer155by a layer transfer technique. In some embodiments, the barrier layer156may be omitted from the quantum well stack146ofFIG.48. The thicknesses (i.e., z-heights) of the layers in the quantum well stacks146ofFIGS.46-48may take any suitable values. For example, in some embodiments, the thickness of the quantum well layer152may be between 5 nanometers and 15 nanometers (e.g., approximately equal to 10 nanometers). In some embodiments, the thickness of a buffer layer154may be between 0.3 microns and 4 microns (e.g., between 0.3 microns and 2 microns, or approximately 0.5 microns). In some embodiments, the thickness of the barrier layers156may be between 0 nanometers and 300 nanometers. In some embodiments, the thickness of the insulating layer155in the quantum well stack146ofFIG.48may be between 5 nanometers and 200 nanometers. The substrate144and the quantum well stack146may be distributed between the base102and the fins104of the quantum dot device100, as discussed above. This distribution may occur in any of a number of ways. For example,FIGS.49-55illustrate example base/fin arrangements158that may be used in a quantum dot device100, in accordance with various embodiments. In the base/fin arrangement158ofFIG.49, the quantum well stack146may be included in the fins104, but not in the base102. The substrate144may be included in the base102, but not in the fins104. When the base/fin arrangement158ofFIG.49is used in the manufacturing operations discussed with reference toFIGS.5-6, the fin etching may etch through the quantum well stack146, and stop when the substrate144is reached. In the base/fin arrangement158ofFIG.50, the quantum well stack146may be included in the fins104, as well as in a portion of the base102. A substrate144may be included in the base102as well, but not in the fins104. When the base/fin arrangement158ofFIG.50is used in the manufacturing operations discussed with reference toFIGS.5-6, the fin etching may etch partially through the quantum well stack146, and stop before the substrate144is reached.FIG.51illustrates a particular embodiment of the base/fin arrangement158ofFIG.50. In the embodiment ofFIG.51, the quantum well stack146ofFIG.46is used; the base102includes the substrate144and a portion of the buffer layer154of the quantum well stack146, while the fins104include the remainder of the quantum well stack146. In the base/fin arrangement158ofFIG.52, the quantum well stack146may be included in the fins104, but not the base102. The substrate144may be partially included in the fins104, as well as in the base102. When the base/fin arrangement158ofFIG.52is used in the manufacturing operations discussed with reference toFIGS.5-6, the fin etching may etch through the quantum well stack146and into the substrate144before stopping.FIG.53illustrates a particular embodiment of the base/fin arrangement158ofFIG.52. In the embodiment ofFIG.53, the quantum well stack146ofFIG.48is used; the fins104include the quantum well stack146and a portion of the substrate144, while the base102includes the remainder of the substrate144. Although the fins104have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins104may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins104). For example, as illustrated in the base/fin arrangement158ofFIG.54, in some embodiments, the fins104may be tapered. In some embodiments, the fins104may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height). When the fins104are tapered, the wider end of the fins104may be the end closer to the base102, as illustrated inFIG.54.FIG.55illustrates a particular embodiment of the base/fin arrangement158ofFIG.54. InFIG.55, the quantum well stack146is included in the tapered fins104while a portion of the substrate144is included in the tapered fins and a portion of the substrate144provides the base102. FIGS.56-58are cross-sectional views of another embodiment of a quantum dot device100, in accordance with various embodiments. In particular,FIG.57illustrates the quantum dot device100taken along the section A-A ofFIG.56(whileFIG.56illustrates the quantum dot device100taken along the section C-C ofFIG.57), andFIG.58illustrates the quantum dot device100taken along the section D-D ofFIG.57(whileFIG.57illustrates the quantum dot device100taken along the section A-A ofFIG.58). The quantum dot device100ofFIGS.56-58, taken along the section B-B ofFIG.56, may be the same as illustrated inFIG.3. AlthoughFIG.56indicates that the cross-section illustrated inFIG.57is taken through the trench107-1, an analogous cross-section taken through the trench107-2may be identical, and thus the discussion ofFIG.57refers generally to the “trench107.” The quantum dot device100may include a quantum well stack146disposed on a substrate144. An insulating material128may be disposed above the quantum well stack146, and multiple trenches107in the insulating material128may extend towards the quantum well stack146. In the embodiment illustrated inFIGS.56-58, a gate dielectric114(for the gates106and108) may be disposed at the “bottom” of the trenches107and may extend up the “side walls” of the trenches107and over adjacent portions of insulating material. In the trenches107, the gate dielectric114of the gates106and108may have a U-shaped cross-section, as shown. The quantum well stack146of the quantum dot device100ofFIGS.56-58may take the form of any of the quantum well stacks disclosed herein (e.g., as discussed above with reference toFIGS.46-48). The various layers in the quantum well stack146ofFIGS.56-58may be grown on the substrate144(e.g., using epitaxial processes). Although only two trenches,107-1and107-2, are shown inFIGS.56-58, this is simply for ease of illustration, and more than two trenches107may be included in the quantum dot device100. In some embodiments, the total number of trenches107included in the quantum dot device100is an even number, with the trenches107organized into pairs including one active trench107and one read trench107, as discussed in detail below. When the quantum dot device100includes more than two trenches107, the trenches107may be arranged in pairs in a line (e.g., 2N trenches total may be arranged in a 1×2N line, or a 2×N line) or in pairs in a larger array (e.g., 2N trenches total may be arranged as a 4×N/2 array, a 6×N/3 array, etc.). For example,FIG.81illustrates a quantum dot device100including an example two-dimensional array of trenches107. As illustrated inFIGS.56and58, in some embodiments, multiple trenches107may be oriented in parallel. The discussion herein will largely focus on a single pair of trenches107for ease of illustration, but all the teachings of the present disclosure apply to quantum dot devices100with more trenches107. As discussed above with reference toFIGS.1-3, in the quantum dot device100ofFIGS.56-58, a quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the quantum well stack146. To control the x- and y-location of quantum dots in the quantum well stack146, voltages may be applied to gates disposed at least partially in the trenches107above the quantum well stack146to adjust the energy profile along the trenches107in the x- and y-direction and thereby constrain the x- and y-location of quantum dots within quantum wells (discussed in detail below with reference to the gates106/108). The dimensions of the trenches107may take any suitable values. For example, in some embodiments, the trenches107may each have a width162between 10 nanometers and 30 nanometers. In some embodiments, the trenches107may each have a vertical dimension164between 5 nanometers and 400 nanometers (e.g., between 250 nanometers and 350 nanometers, or equal to 300 nanometers). The insulating material128may be a dielectric material (e.g., an interlayer dielectric), such as silicon oxide. In some embodiments, the insulating material128may be a CVD oxide or a flowable CVD oxide. In some embodiments, the trenches107may be spaced apart by a distance160between 50 nanometers and 500 nanometers. Multiple gates may be disposed at least partially in each of the trenches107. In the embodiment illustrated inFIG.57, three gates106and two gates108are shown as distributed at least partially in a single trench107. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, as discussed below with reference toFIG.82, multiple groups of gates (like the gates illustrated inFIG.57) may be disposed at least partially in the trench107. As shown inFIG.57, the gate108-1may be disposed between the gates106-1and106-2, and the gate108-2may be disposed between the gates106-2and106-3. As discussed above with reference to the quantum dot device100ofFIGS.1-3, a gate106may be spaced apart from an adjacent gate108by a gate wall138. The gate wall138may include a barrier layer113and a spacer134. The barrier layer113may have an L-shape in cross-section, with a vertical portion adjacent to the gate dielectric114-1of an adjacent gate106, and a horizontal portion under the associated spacer134. The vertical portion of the barrier layer113of a gate wall138may be disposed between the gate dielectric114-1of an adjacent gate106and the spacer134of that gate wall138. In some embodiments, the vertical portion of the barrier material113of gate wall138may not be present. The horizontal portion of the barrier layer113of a gate wall138may be disposed between the fin104and the spacer134of that gate wall138. The spacer134of a gate wall138may be disposed between the vertical portion of the associated barrier layer113and the gate dielectric114-2of a gate108. As illustrated inFIG.2, the spacers134may be thicker closer to the fin104and thinner farther away from the fin104. In some embodiments, the spacers134may have a convex shape. The spacers134may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). Each of the gates106/108may include a gate dielectric114; in the embodiment illustrated inFIG.57, the gate dielectric114-1for the gates106and the gate dielectric114-2for the gates108are provided by separate portions of gate dielectric114, as shown. The gate dielectrics114for the gates106and the gates108may have the same material composition or structure, or different material compositions or structures, as discussed above. In some embodiments, a gate dielectric114may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the trench107and the corresponding gate metal). A gate dielectric114may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric114may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric114may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric114to improve the quality of the gate dielectric114. As noted above, although the gate dielectrics114-1and114-2for the gates106and108, respectively, are shown in various ones of the accompanying figures as distinct, non-materially continuous portions of gate dielectric114, in other embodiments of the quantum dot devices100disclosed herein, the gate dielectrics114-1and114-2may be provided by a single, common layer of gate dielectric114on the fin104(between the fin104and the gate metals110/112). Each of the gates106may also include a gate metal110. The gate dielectric114-1for each gate106may extend at least partially up the sides of the adjacent barrier layer113of a gate wall138, and the gate metal110may extend between the portions of gate dielectric114-1on the adjacent barrier layer113, as shown. The gate dielectric114-1may be at least partially disposed between the gate metal110and the quantum well stack146. As shown inFIG.56, in some embodiments, the gate metal110of a gate106may extend over the insulating material128and into a trench107in the insulating material128. In some embodiments, the gate metal110may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via ALD), or niobium titanium nitride. As illustrated inFIG.58, in some embodiments, no spacer material or barrier layer113may be disposed between the gate metal112and the sidewalls of the trench107in the y-direction (while in other embodiments, spacer material and barrier layer113may be present, as discussed below with reference toFIGS.77-78). Each of the gates108may include a gate metal112and a gate dielectric114-2. The gate dielectric114-2for each gate108may have a bottom portion that extends at least partially up the sides of the adjacent gate walls138(contacting the spacer134and the barrier layer113under the spacer134of a gate wall138), forming a “U” shape in cross-section. The gate dielectric114-1for each gate108may also have a top portion that contacts insulating material130adjacent to the gate108, and extends over the adjacent gates106; thus, the gates108may have a “T”-shape. The gate metal112may extend between the portions of gate dielectric114-2on the adjacent gate walls138and different adjacent portions of the insulating material130, as shown. As shown inFIG.58, in some embodiments, the gate metal112of a gate108may extend over the insulating material128and into a trench107in the insulating material128. The gate metal110and the gate metal112may take any of the forms discussed above. For example, in some embodiments, the gate metal110and the gate metal112may have different material structures so as to induce differential strain in the underlying quantum well layer152, while in other embodiments, the gate metal110and the gate metal112may have the same material structure. As discussed above with reference toFIGS.1-3, the gates108may be “taller” than the adjacent gates106and may extend at least partially over the adjacent gates106so as to “overlap” them. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate dielectric114-1of the gate106is at least partially disposed between the fin104and the gate dielectric114-2of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate metal110of the gate106is at least partially disposed between the fin104and the gate dielectric114-2of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate dielectric114-1of the gate106is at least partially disposed between the fin104and the gate metal112of the adjacent gate108. In some embodiments, a gate108may overlap an adjacent gate106to such a degree that the gate metal110of the gate106is at least partially disposed between the fin104and the gate metal112of the adjacent gate108. The gate108may extend over, and may be in contact with, a top surface of a cap118-1on the gate metal110of an adjacent gate106. As discussed above with reference toFIGS.1-3, a cap118-1may extend over the gate metal110of the gates106; the bottom surface of the cap118-1may contact the gate metal110, while side faces of the cap118-1may contact the gate dielectric114-1. Similarly, a cap118-2may extend over the gate metal112of the gates108; the bottom surface of the cap118-2may contact the gate metal112, while side faces of the cap118-2may contact the gate dielectric114-2. The caps118may take any of the forms disclosed herein The gate108-1may extend between the proximate gate walls138on the sides of the gate106-1and the gate106-2along the longitudinal axis of the trench107, as shown inFIG.57. In some embodiments, the gate metal112and the bottom portion of the gate dielectric114-2of the gate108-1may together extend between the gate walls138on the sides of the gate106-1and the gate106-2along the longitudinal axis of the trench107. Thus, the gate metal112and the bottom portion of the gate dielectric114-2of the gate108-1may together have a shape that is substantially complementary to the shape of the gate walls138, as shown. Similarly, the gate108-2may extend between the proximate gate walls138on the sides of the gate106-2and the gate106-3along the longitudinal axis of the trench107. The gate dielectric114-2may extend at least partially up the sides of the gate walls138(and up the proximate sidewalls of the trench107), as shown, and the gate metal112may extend between the portions of gate dielectric114-2on the spacers134(and the proximate sidewalls of the trench107). The gate metal112, like the gate metal110, may be any suitable metal, such as titanium nitride. As illustrated inFIG.58, in some embodiments, no spacer material or barrier layer113may be disposed between the gate metal112and the sidewalls of the trench107in the y-direction; in other embodiments (e.g., as discussed below with reference toFIGS.77and78), spacers134and barrier layer113may also be disposed between the gate metal112and the sidewalls of the trench107in the y-direction. The dimensions of the gates106/108may take any suitable values. For example, in some embodiments, the z-height166of the gates106in the trench107may be between 50 nanometers and 400 nanometers (e.g., approximately 300 nanometers); the z-height175of the gates108may be in the same range and may be greater than the z-height166. In some embodiments, the length168of the gate metal110(i.e., in the x-direction) may be between 20 nanometers and 60 nanometers (e.g., 40 nanometers). Although all of the gates106are illustrated in the accompanying drawings as having the same length168of the gate metal110, in some embodiments, the “outermost” gates106(e.g., the gates106-1and106-3of the embodiment illustrated inFIG.57) may have a greater length168than the “inner” gates106(e.g., the gate106-2in the embodiment illustrated inFIG.57). For example, in some embodiments, the outermost gates106may have a length168between 100 nanometers and 500 nanometers. Such longer “outside” gates106may provide spatial separation between the doped regions140and the areas under the gates108and the inner gates106in which quantum dots142may form, and thus may reduce the perturbations to the potential energy landscape under the gates108and the inner gates106caused by the doped regions140. In some embodiments, during operation of the quantum dot device100, a 2DEG may form under the outermost gates106; this 2DEG may separate the “active” device region (under the gates106/108) from the doped region140(which has a large density of implanted charge carriers). In some embodiments, the distance170between adjacent ones of the gates106(e.g., as measured from the gate metal110of one gate106to the gate metal110of an adjacent gate106in the x-direction, as illustrated inFIG.57) may be between 40 nanometers and 100 nanometers (e.g., 50 nanometers). In some embodiments, the thickness172of the gate walls138may be between 1 nanometer and 10 nanometers (e.g., between 3 nanometers and 5 nanometers, between 4 nanometers and 6 nanometers, or between 4 nanometers and 7 nanometers). In some embodiments, the thickness174of the vertical portion of the barrier layer113may be between 5 Angstroms and 20 Angstroms (e.g., between 8 Angstroms and 15 Angstroms); the thickness of the horizontal portion of the barrier layer113(i.e., the thickness between the fin104and the associated spacer134) may also be between 5 Angstroms and 20 Angstroms (e.g., between 8 Angstroms and 15 Angstroms). The length of the gate metal112(i.e., in the x-direction) may depend on the dimensions of the gates106and the gate walls138, as illustrated inFIG.57. As indicated inFIGS.56and58, the gates106/108in one trench107may extend over the insulating material128between that trench107and an adjacent trench107, but may be isolated from their counterpart gates by the intervening insulating material130(and gate walls138for the gates106). As shown inFIG.57, the gates106and108may be alternatingly arranged in the x-direction. During operation of the quantum dot device100, voltages may be applied to the gates106/108to adjust the potential energy in the quantum well stack146to create quantum wells of varying depths in which quantum dots142may form, as discussed above with reference to the quantum dot device100ofFIGS.1-3. Only one quantum dot142is labeled with a reference numeral inFIG.57for ease of illustration, but five are indicated as dotted circles below each trench107. The quantum well stack146of the quantum dot device100ofFIGS.56-58may include doped regions140that may serve as a reservoir of charge carriers for the quantum dot device100, in accordance with any of the embodiments discussed above. The quantum dot devices100discussed with reference toFIGS.56-58may be used to form electron-type or hole-type quantum dots142, as discussed above with reference toFIGS.1-3. Conductive vias and lines may contact the gates106/108of the quantum dot device100ofFIGS.56-58, and to the doped regions140, to enable electrical connection to the gates106/108and the doped regions140to be made in desired locations. As shown inFIGS.56-58, the gates106may extend both “vertically” and “horizontally” away from the quantum well stack146, and conductive vias120may contact the gates106(and are drawn in dashed lines inFIG.57to indicate their location behind the plane of the drawing). The conductive vias120may extend through the caps118-1to contact the gate metal110of the gates106. The gates108may similarly extend away from the quantum well stack146, and conductive vias122may contact the gates108(also drawn in dashed lines inFIG.57to indicate their location behind the plane of the drawing). The conductive vias122may extend through the caps118-2to contact the gate metal112of the gates108. Conductive vias136may contact the interface material141and may thereby make electrical contact with the doped regions140. The quantum dot device100ofFIGS.56-58may include further conductive vias and/or lines (not shown) to make electrical contact to the gates106/108and/or the doped regions140, as desired. The conductive vias and lines included in a quantum dot device100may include any suitable materials, such as copper, tungsten (deposited, e.g., by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium). In some embodiments, the quantum dot device100ofFIGS.56-58may include one or more magnet lines121. For example, a single magnet line121is illustrated inFIGS.56-58, proximate to the trench107-1. The magnet line(s)121of the quantum dot device ofFIGS.56-58may take the form of any of the embodiments of the magnet lines121discussed herein. For example, the magnet line121may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots142that may form in the quantum well stack146. In some embodiments, the magnet line121may conduct a pulse to reset (or “scramble”) nuclear and/or quantum dot spins. In some embodiments, the magnet line121may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, the magnet line121may conduct current to provide a continuous, oscillating magnetic field to which the spin of a qubit may couple. The magnet line121may provide any suitable combination of these embodiments, or any other appropriate functionality. In some embodiments, the magnet line121ofFIGS.56-58may be formed of copper. In some embodiments, the magnet line121may be formed of a superconductor, such as aluminum. The magnet line121illustrated inFIGS.56-58is non-coplanar with the trenches107, and is also non-coplanar with the gates106/108. In some embodiments, the magnet line121may be spaced apart from the gates106/108by a distance167. The distance167may take any suitable value (e.g., based on the desired strength of magnetic field interaction with particular quantum dots142); in some embodiments, the distance167may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers). In some embodiments, the magnet line121ofFIGS.56-58may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material130to provide a permanent magnetic field in the quantum dot device100. The magnet line121ofFIGS.56-58may have any suitable dimensions. For example, the magnet line121may have a thickness169between 25 nanometers and 100 nanometers. The magnet line121may have a width171between 25 nanometers and 100 nanometers. In some embodiments, the width171and thickness169of a magnet line121may be equal to the width and thickness, respectively, of other conductive lines in the quantum dot device100(not shown) used to provide electrical interconnects, as known in the art. The magnet line121may have a length173that may depend on the number and dimensions of the gates106/108that are to form quantum dots142with which the magnet line121is to interact. The magnet line121illustrated inFIGS.56-58are substantially linear, but this need not be the case; the magnet lines121disclosed herein may take any suitable shape. Conductive vias123may contact the magnet line121. The conductive vias120,122,136, and123may be electrically isolated from each other by an insulating material130, all of which may take any of the forms discussed above with reference toFIGS.1-3. The particular arrangement of conductive vias shown inFIGS.56-58is simply illustrative, and any electrical routing arrangement may be implemented. As discussed above, the structure of the trench107-1may be the same as the structure of the trench107-2; similarly, the construction of gates106/108in and around the trench107-1may be the same as the construction of gates106/108in and around the trench107-2. The gates106/108associated with the trench107-1may be mirrored by corresponding gates106/108associated with the parallel trench107-2, and the insulating material130may separate the gates106/108associated with the different trenches107-1and107-2. In particular, quantum dots142formed in the quantum well stack146under the trench107-1(under the gates106/108) may have counterpart quantum dots142in the quantum well stack146under the trench107-2(under the corresponding gates106/108). In some embodiments, the quantum dots142under the trench107-1may be used as “active” quantum dots in the sense that these quantum dots142act as qubits and are controlled (e.g., by voltages applied to the gates106/108associated with the trench107-1) to perform quantum computations. The quantum dots142associated with the trench107-2may be used as “read” quantum dots in the sense that these quantum dots142may sense the quantum state of the quantum dots142under the trench107-1by detecting the electric field generated by the charge in the quantum dots142under the trench107-1, and may convert the quantum state of the quantum dots142under the trench107-1into electrical signals that may be detected by the gates106/108associated with the trench107-2. Each quantum dot142under the trench107-1may be read by its corresponding quantum dot142under the trench107-2. Thus, the quantum dot device100enables both quantum computation and the ability to read the results of a quantum computation. The quantum dot devices100disclosed herein may be manufactured using any suitable techniques. In some embodiments, the manufacture of the quantum dot device100ofFIGS.56-58may begin as described above with reference toFIGS.4-5; however, instead of forming fins104in the quantum well stack146of the assembly202, manufacturing may proceed as illustrated inFIGS.59-76(and described below). Although the particular manufacturing operations discussed below with reference toFIGS.59-76are illustrated as manufacturing a particular embodiment of the quantum dot device100, these operations may be applied to manufacture many different embodiments of the quantum dot device100, as discussed herein. Any of the elements discussed below with reference toFIGS.59-76may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). FIG.59is a cross-sectional view of an assembly1204including a quantum well stack146on a substrate144. The assembly1204may be formed as described above with reference toFIGS.4-5, and may have the same form as the assembly202(FIG.5). FIG.60is a cross-sectional view of an assembly1206subsequent to providing an insulating material128on the assembly1204(FIG.59). Any suitable material may be used as the insulating material128to electrically insulate the trenches107from each other, as discussed above. As noted above, in some embodiments, the insulating material128may be a dielectric material, such as silicon oxide. FIG.61is a cross-sectional view of an assembly1208subsequent to forming trenches107in the insulating material128of the assembly1206(FIG.60). The trenches107may extend down to the quantum well stack146, and may be formed in the assembly1206by patterning and then etching the assembly1206using any suitable conventional lithographic process known in the art. For example, a hardmask may be provided on the insulating material128, and a photoresist may be provided on the hardmask; the photoresist may be patterned to identify the areas in which the trenches107are to be formed, the hardmask may be etched in accordance with the patterned photoresist, and the insulating material128may be etched in accordance with the etched hardmask (after which the remaining hardmask and photoresist may be removed). In some embodiments, a combination of dry and wet etch chemistry may be used to form the trenches107in the insulating material128, and the appropriate chemistry may depend on the materials included in the assembly1208, as known in the art. Although the trenches107illustrated inFIG.61(and other accompanying drawings) are shown as having substantially parallel sidewalls, in some embodiments, the trenches107may be tapered, narrowing towards the quantum well stack146.FIG.62is a view of the assembly1208taken along the section A-A ofFIG.61, through a trench107(whileFIG.61illustrates the assembly1208taken along the section D-D ofFIG.62). FIG.63is a cross-sectional view of an assembly1216subsequent to performing the operations discussed above with reference toFIGS.11-14, including depositing and patterning a dummy material111, conformally depositing a layer of barrier layer113, and providing spacer material132on the assembly1208(FIGS.61and62).FIG.64is a view of the assembly1216taken along the section D-D ofFIG.63(whileFIG.63illustrates the assembly1216taken along the section A-A ofFIG.64, along a trench107). The operations discussed above with reference toFIGS.11-14may be performed in accordance with any of the embodiments disclosed herein. FIG.65is a cross-sectional view of an assembly1218subsequent to providing capping material133on the assembly1216(FIGS.63and64).FIG.66is a view of the assembly1218taken along the section D-D ofFIG.65(whileFIG.65illustrates the assembly1218taken along the section A-A ofFIG.66, along a trench107). The capping material133may be any suitable material; for example, the capping material133may be silicon oxide deposited by CVD or ALD. As illustrated inFIGS.65and66, the capping material133may be conformally deposited on the assembly1216. FIG.67is a cross-sectional view of an assembly1220subsequent to providing a sacrificial material135on the assembly1218(FIGS.65and66).FIG.68is a view of the assembly1220taken along the section D-D ofFIG.67(whileFIG.67illustrates the assembly1220taken along the section A-A ofFIG.68, through a trench107). The sacrificial material135may be deposited on the assembly1218to completely cover the capping material133, then the sacrificial material135may be recessed to expose portions137of the capping material133. In particular, the portions137of capping material133disposed near the “top” of the dummy material111may not be covered by the sacrificial material135. As illustrated inFIG.68, all of the capping material133disposed in the region between adjacent portions of the dummy material111may be covered by the sacrificial material135. The recessing of the sacrificial material135may be achieved by any etching technique, such as a dry etch. The sacrificial material135may be any suitable material, such as a bottom anti-reflective coating (BARC). FIG.69is a cross-sectional view of an assembly1222subsequent to treating the exposed portions137of the capping material133of the assembly1220(FIGS.67and68) to change the etching characteristics of the exposed portions137relative to the rest of the capping material133.FIG.70is a view of the assembly1222taken along the section D-D ofFIG.69(whileFIG.69illustrates the assembly1222taken along the section A-A ofFIG.70, through a trench107). In some embodiments, this treatment may include performing a high-dose ion implant in which the implant dose is high enough to cause a compositional change in the portions137and achieve a desired change in etching characteristics. FIG.71is a cross-sectional view of an assembly1224subsequent to removing the sacrificial material135and the unexposed capping material133of the assembly1222(FIGS.69and70).FIG.72is a view of the assembly1224taken along the section D-D ofFIG.71(whileFIG.71illustrates the assembly1224taken along the section A-A ofFIG.72, through a trench107). The sacrificial material135may be removed using any suitable technique (e.g., by ashing, followed by a cleaning step), and the untreated capping material133may be removed using any suitable technique (e.g., by etching). In embodiments in which the capping material133is treated by ion implantation (e.g., as discussed above with reference toFIGS.69and70), a high temperature anneal may be performed to incorporate the implanted ions in the portions137of the capping material133before removing the untreated capping material133. The remaining treated capping material133in the assembly1224may provide capping structures145disposed proximate to the “tops” of the portions of the dummy material111and extending over the spacer material132disposed proximate to the “sides” of the portions of the dummy material111. FIG.73is a cross-sectional view of an assembly1226subsequent to directionally etching the spacer material132of the assembly1224(FIGS.71and72) that isn't protected by a capping structure145, leaving spacer material132on the sides and top of dummy material111/barrier layer113structures.FIG.74is a view of the assembly1226taken along the section D-D ofFIG.73(whileFIG.73illustrates the assembly1226taken along the section A-A ofFIG.74, through a trench107). The etching of the spacer material132may be an anisotropic etch, etching the spacer material132“downward” to remove the spacer material132in some of the area between the portions of the dummy material111(as illustrated inFIGS.73and74), while leaving the spacer material132on the sides and tops of the dummy material111/barrier layer113structures. In some embodiments, the anisotropic etch may be a dry etch.FIGS.75-76maintain the cross-sectional perspective ofFIG.73. FIG.75is a cross-sectional view of an assembly1228subsequent to removing the capping structures145from the assembly1226(FIGS.73and74). The capping structures145may be removed using any suitable technique (e.g., a wet etch). The spacer material132that remains in the assembly1228may include spacers134disposed on the sides of the dummy material111/barrier layer113structures, and portions139disposed on the top of the dummy material111/barrier layer113structures. FIG.76is a cross-sectional view of an assembly1230subsequent to providing a dummy material109on the assembly1228(FIG.75). The dummy material109may fill the areas between adjacent ones of the dummy material111/barrier layer113structures, and may extend over the tops of the structures and over the spacer material portions139. The dummy material109of the assembly1230may fill the trenches107and extend over the insulating material128. The assembly1230may then be processed substantially as discussed above with reference toFIGS.17-42to form the quantum dot device100ofFIGS.56-58. In the embodiment of the quantum dot device100illustrated inFIGS.56-58, the magnet line121is oriented parallel to the longitudinal axes of the trenches107. In other embodiments, the magnet line121of the quantum dot device100ofFIGS.56-58may not be oriented parallel to the longitudinal axes of the trenches107; for example, any of the magnet line arrangements discussed above with reference toFIGS.43-45may be used. Although a single magnet line121is illustrated inFIGS.56-58, multiple magnet lines121may be included in that embodiment of the quantum dot device100(e.g., multiple magnet lines121parallel to the longitudinal axes of the trenches107). For example, the quantum dot device100ofFIGS.56-58may include a second magnet line121proximate to the trench107-2in a symmetric manner to the magnet line121illustrated proximate to the trench107-1. In some embodiments, multiple magnet lines121may be included in a quantum dot device100, and these magnet lines121may or may not be parallel to one another. For example, in some embodiments, a quantum dot device100may include two (or more) magnet lines121that are oriented perpendicular to each other. As discussed above, in the embodiment illustrated inFIGS.56-58(andFIGS.59-71), there may not be any substantial spacer material132or barrier layer113between the gate metal112and the proximate sidewalls of the trench107in the y-direction. In other embodiments, gate walls138(including spacers134and barrier layer113) may also be disposed between the gate metal112and the sidewalls of the trench107in the y-direction. A cross-sectional view of such an embodiment is shown inFIG.77(analogous to the cross-sectional view ofFIG.58). To manufacture such a quantum dot device100, the operations discussed above with reference toFIGS.65-74may not be performed; instead, the spacer material132and the barrier layer113of the assembly1216ofFIGS.63and64may be anisotropically etched (as discussed with reference toFIGS.73and74) to form the gate walls138on the sides of the dummy material111and on the sidewalls of the trench107.FIG.78is a cross-sectional view of an assembly1256that may be formed by such a process (taking the place of the assembly1226ofFIG.74); the view along the section A-A of the assembly1256may be similar toFIG.75, but may not include the spacer material portions139. The assembly1256may be further processed as discussed above to form a quantum dot device100. As noted above, a quantum dot device100may include multiple trenches107arranged in an array of any desired size. For example,FIG.81is a top cross-sectional view, like the view ofFIG.3, of a quantum dot device100having multiple trenches107arranged in a two-dimensional array. Magnet lines121are not depicted inFIG.81, although they may be included in any desired arrangements. In the particular example illustrated inFIG.81, the trenches107may be arranged in pairs, each pair including an “active” trench107and a “read” trench107, as discussed above. The particular number and arrangement of trenches107inFIG.81is simply illustrative, and any desired arrangement may be used. Similarly, a quantum dot device100may include multiple sets of fins104(and accompanying gates, as discussed above with reference toFIGS.1-3) arranged in a two-dimensional array. As noted above, a single trench107may include multiple groups of gates106/108, spaced apart along the trench by a doped region140.FIG.82is a cross-sectional view of an example of such a quantum dot device100having multiple groups of gates180at least partially disposed in a single trench107above a quantum well stack146, in accordance with various embodiments. Each of the groups180may include gates106/108(not labeled inFIG.82for ease of illustration) that may take the form of any of the embodiments of the gates106/108discussed herein. A doped region140(and its interface material141) may be disposed between two adjacent groups180(labeled inFIG.82as groups180-1and180-2), and may provide a common reservoir for both groups180. In some embodiments, this “common” doped region140may be electrically contacted by a single conductive via136. The particular number of gates106/108illustrated inFIG.82, and the particular number of groups180, is simply illustrative, and a trench107may include any suitable number of gates106/108arranged in any suitable number of groups180. The quantum dot device100ofFIG.82may also include one or more magnet lines121, arranged as desired. Similarly, in embodiments of the quantum dot device100that include fins, a single fin104may include multiple groups of gates106/108, spaced apart along the fin. In some embodiments, spacers may be disposed on top of the gates106, and may provide side “walls” for the adjacent gates108. For example,FIG.79illustrates a view of such a quantum dot device100; the view ofFIG.79is analogous to the view ofFIG.2. One or two spacers117may be disposed at the top of each gate106, and the gate dielectric114-2of a gate108may contact the proximate ones of these spacers117on the adjacent gates106. Two spacers117may be disposed at the top of “interior” gates106, and one spacer117may be disposed at the top of “exterior” gates106, as shown. The spacers117may curve convexly toward the proximate gates108, as shown, and the gate dielectric114-2may be disposed on these convex surfaces. The spacers117may be formed after the patterning of the insulating material130(discussed above with reference toFIG.29) and before the deposition of the gate dielectric114-2. Any of the spacer formation techniques disclosed herein may be used to form the spacers117, and the spacers117may have any of the material structures disclosed herein. The spacers117may further insulate the gate metal110of a gate106from the gate metal112of an adjacent gate108, reducing the likelihood of an undesirable short or leak. In some embodiments, the caps118-1and118-2may have the same thickness, while in other embodiments, the caps118-1may have a different thickness than the caps118-2. For example,FIG.80illustrates a view of a quantum dot device100in which the caps118-1and118-2have different thicknesses; the view ofFIG.80is analogous to the view ofFIG.2. InFIG.80, the caps118-1are thicker than the caps118-2, but in other embodiments, the caps118-2may be thicker than the caps118-1. In other embodiments, no caps118-2may be present, as noted above. In some embodiments, the quantum dot device100may be included in a die and coupled to a package substrate to form a quantum dot device package. For example,FIG.83is a side cross-sectional view of a die302including the quantum dot device100ofFIG.57and conductive pathway layers303disposed thereon, whileFIG.84is a side cross-sectional view of a quantum dot device package300in which the die302and another die350are coupled to a package substrate304(e.g., in a system-on-a-chip (SoC) arrangement). Details of the quantum dot device100are omitted fromFIG.84for economy of illustration. As noted above, the particular quantum dot device100illustrated inFIGS.83and84may take a form similar to the embodiments illustrated inFIGS.2and57, but any of the quantum dot devices100disclosed herein may be included in a die (e.g., the die302) and coupled to a package substrate (e.g., the package substrate304). In particular, any number of fins104or trenches107, gates106/108, doped regions140, magnet lines121, and other components discussed herein with reference to various embodiments of the quantum dot device100may be included in the die302. The die302may include a first face320and an opposing second face322. The base102may be proximate to the second face322, and conductive pathways315from various components of the quantum dot device100may extend to conductive contacts365disposed at the first face320. The conductive pathways315may include conductive vias, conductive lines, and/or any combination of conductive vias and lines. For example,FIG.83illustrates an embodiment in which one conductive pathway315(extending between a magnet line121and associated conductive contact365) includes a conductive via123, a conductive line393, a conductive via398, and a conductive line396. More or fewer structures may be included in the conductive pathways315, and analogous conductive pathways315may be provided between ones of the conductive contacts365and the gates106/108, doped regions140, or other components of the quantum dot device100. In some embodiments, conductive lines of the die302(and the package substrate304, discussed below) may extend into and out of the plane of the drawing, providing conductive pathways to route electrical signals to and/or from various elements in the die302. The conductive vias and/or lines that provide the conductive pathways315in the die302may be formed using any suitable techniques. Examples of such techniques may include subtractive fabrication techniques, additive or semi-additive fabrication techniques, single Damascene fabrication techniques, dual Damascene fabrication techniques, or any other suitable technique. In some embodiments, layers of oxide material390and layers of nitride material391may insulate various structures in the conductive pathways315from proximate structures, and/or may serve as etch stops during fabrication. In some embodiments, an adhesion layer (not shown) may be disposed between conductive material and proximate insulating material of the die302to improve mechanical adhesion between the conductive material and the insulating material. The gates106/108, the doped regions140, and the quantum well stack146(as well as the proximate conductive vias/lines) may be referred to as part of the “device layer” of the quantum dot device100. The conductive lines393may be referred to as a Metal 1 or “M1” interconnect layer, and may couple the structures in the device layer to other interconnect structures. The conductive vias398and the conductive lines396may be referred to as a Metal 2 or “M2” interconnect layer, and may be formed directly on the M1 interconnect layer. A solder resist material367may be disposed around the conductive contacts365, and, in some embodiments, may extend onto the conductive contacts365. The solder resist material367may be a polyimide or similar material, or may be any appropriate type of packaging solder resist material. In some embodiments, the solder resist material367may be a liquid or dry film material including photoimageable polymers. In some embodiments, the solder resist material367may be non-photoimageable (and openings therein may be formed using laser drilling or masked etch techniques). The conductive contacts365may provide the contacts to couple other components (e.g., a package substrate304, as discussed below, or another component) to the conductive pathways315in the quantum dot device100, and may be formed of any suitable conductive material (e.g., a superconducting material). For example, solder bonds may be formed on the one or more conductive contacts365to mechanically and/or electrically couple the die302with another component (e.g., a circuit board), as discussed below. The conductive contacts365illustrated inFIG.83take the form of bond pads, but other first-level interconnect structures may be used (e.g., posts) to route electrical signals to/from the die302, as discussed below. The combination of the conductive pathways and the proximate insulating material (e.g., the insulating material130, the oxide material390, and the nitride material391) in the die302may provide an ILD stack of the die302. As noted above, interconnect structures may be arranged within the quantum dot device100to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures depicted inFIG.83or any of the other accompanying figures, and may include more or fewer interconnect structures). During operation of the quantum dot device100, electrical signals (such as power and/or input/output (I/O) signals) may be routed to and/or from the gates106/108, the magnet line(s)121, and/or the doped regions140(and/or other components) of the quantum dot device100through the interconnects provided by conductive vias and/or lines, and through the conductive pathways of the package substrate304(discussed below). Example superconducting materials that may be used for the structures in the conductive pathways313,317,319(discussed below), and315, and/or conductive contacts of the die302and/or the package substrate304, may include aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium titanium, niobium aluminum, or niobium tin). In some embodiments, the conductive contacts365,379, and/or399may include aluminum, and the first-level interconnects306and/or the second-level interconnects308may include an indium-based solder. As noted above, the quantum dot device package300ofFIG.84may include a die302(including one or more quantum dot devices100) and a die350. As discussed in detail below, the quantum dot device package300may include electrical pathways between the die302and the die350so that the dies302and350may communicate during operation. In some embodiments, the die350may be a non-quantum logic device that may provide support or control functionality for the quantum dot device(s)100of the die302. For example, as discussed further below, in some embodiments, the die350may include a switching matrix to control the writing and reading of data from the die302(e.g., using any known word line/bit line or other addressing architecture). In some embodiments, the die350may control the voltages (e.g., microwave pulses) applied to the gates106/108, and/or the doped regions140, of the quantum dot device(s)100included in the die302. In some embodiments, the die350may include magnet line control logic to provide microwave pulses to the magnet line(s)121of the quantum dot device(s)100in the die302. The die350may include any desired control circuitry to support operation of the die302. By including this control circuitry in a separate die, the manufacture of the die302may be simplified and focused on the needs of the quantum computations performed by the quantum dot device(s)100, and conventional manufacturing and design processes for control logic (e.g., switching array logic) may be used to form the die350. Although a singular “die350” is illustrated inFIG.84and discussed herein, the functionality provided by the die350may, in some embodiments, be distributed across multiple dies350(e.g., multiple dies coupled to the package substrate304, or otherwise sharing a common support with the die302). Similarly, one or more dies providing the functionality of the die350may support one or more dies providing the functionality of the die302; for example, the quantum dot device package300may include multiple dies having one or more quantum dot devices100, and a die350may communicate with one or more such “quantum dot device dies.” The die350may take any of the forms discussed below with reference to the non-quantum processing device2028ofFIG.88. Mechanisms by which the control logic of the die350may control operation of the die302may be take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects. For example, the die350may implement an algorithm executed by one or more processing units, e.g. one or more microprocessors. In various embodiments, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s), preferably non-transitory, having computer readable program code embodied (e.g., stored) in or coupled to the die350. In various embodiments, such a computer program may, for example, be downloaded (updated) to the die350(or attendant memory) or be stored upon manufacturing of the die350. In some embodiments, the die350may include at least one processor and at least one memory element, along with any other suitable hardware and/or software to enable its intended functionality of controlling operation of the die302as described herein. A processor of the die350may execute software or an algorithm to perform the activities discussed herein. A processor of the die350may be communicatively coupled to other system elements via one or more interconnects or buses (e.g., through one or more conductive pathways319). Such a processor may include any combination of hardware, software, or firmware providing programmable logic, including by way of non-limiting example, a microprocessor, a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA), an application-specific integrated circuit (ASIC), or a virtual machine processor. The processor of the die350may be communicatively coupled to the memory element of the die350, for example, in a direct-memory access (DMA) configuration. A memory element of the die350may include any suitable volatile or nonvolatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory regions, magnetic or tape memory, or any other suitable technology. In some embodiments, the memory element and the processor of the “die350” may themselves be provided by separate physical dies that are in electrical communication. The information being tracked or sent to the die350could be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable timeframe. The die350can further include suitable interfaces for receiving, transmitting, and/or otherwise communicating data or information in a network environment (e.g., via the conductive pathways319). In some embodiments, the die350may be configured to apply appropriate voltages to any one of the gates106/108(acting as, e.g., plunger gates, barrier gates, and/or accumulation gates) in order to initialize and manipulate the quantum dots142, as discussed above. For example, by controlling the voltage applied to a gate106/108acting as a plunger gate, the die350may modulate the electric field underneath that gate to create an energy valley between the tunnel barriers created by adjacent barrier gates. In another example, by controlling the voltage applied to a gate106/108acting as a barrier gate, the die350may change the height of the tunnel barrier. When a barrier gate is used to set a tunnel barrier between two plunger gates, the barrier gate may be used to transfer charge carriers between quantum dots142that may be formed under these plunger gates. When a barrier gate is used to set a tunnel barrier between a plunger gate and an accumulation gate, the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate. The term “accumulation gate” may refer to a gate used to form a 2DEG in an area that is between the area where the quantum dots142may be formed and a charge carrier reservoir (e.g., the doped regions140). Changing the voltage applied to the accumulation gate may allow the die350to control the number of charge carriers in the area under the accumulation gate. For example, changing the voltage applied to the accumulation gate may reduce the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum well layer152, and vice versa. In some embodiments, the “outermost” gates106in a quantum dot device100may serve as accumulation gates. In some embodiments, these outermost gates106may have a greater length168than “inner” gates106. As noted above, the die350may provide electrical signals to control spins of charge carriers in quantum dots142of the quantum dot device(s)100of the die302by controlling a magnetic field generated by one or more magnet line(s)121. In this manner, the die350may initialize and manipulate spins of the charge carriers in the quantum dots142to implement qubit operations. If the magnetic field for a die302is generated by a microwave transmission line, then the die350may set/manipulate the spins of the charge carriers by applying appropriate pulse sequences to manipulate spin precession. Alternatively, the magnetic field for a quantum dot device100of the die302may be generated by a magnet with one or more pulsed gates; the die350may apply the pulses to these gates. In some embodiments, the die350may be configured to determine the values of the control signals applied to the elements of the die302(e.g. determine the voltages to be applied to the various gates106/108) to achieve desired quantum operations (communicated to the die350through the package substrate304via the conductive pathways319). In other embodiments, the die350may be preprogrammed with at least some of the control parameters (e.g. with the values for the voltages to be applied to the various gates106/108) during the initialization of the die350. In the quantum dot device package300(FIG.84), first-level interconnects306may be disposed between the first face320of the die302and the second face326of a package substrate304. Having first-level interconnects306disposed between the first face320of the die302and the second face326of the package substrate304(e.g., using solder bumps as part of flip chip packaging techniques) may enable the quantum dot device package300to achieve a smaller footprint and higher die-to-package-substrate connection density than could be achieved using conventional wirebond techniques (in which conductive contacts between the die302and the package substrate304are constrained to be located on the periphery of the die302). For example, a die302having a square first face320with side length N may be able to form only 4N wirebond interconnects to the package substrate304, versus N2flip chip interconnects (utilizing the entire “full field” surface area of the first face320). Additionally, in some applications, wirebond interconnects may generate unacceptable amounts of heat that may damage or otherwise interfere with the performance of the quantum dot device100. Using solder bumps as the first-level interconnects306may enable the quantum dot device package300to have much lower parasitic inductance relative to using wirebonds to couple the die302and the package substrate304, which may result in an improvement in signal integrity for high speed signals communicated between the die302and the package substrate304. Similarly, first-level interconnects309may be disposed between conductive contacts371of the die350and conductive contacts379at the second face326of the package substrate304, as shown, to couple electronic components (not shown) in the die350to conductive pathways in the package substrate304. The package substrate304may include a first face324and an opposing second face326. Conductive contacts399may be disposed at the first face324, and conductive contacts379may be disposed at the second face326. Solder resist material314may be disposed around the conductive contacts379, and solder resist material312may be disposed around the conductive contacts399; the solder resist materials314and312may take any of the forms discussed above with reference to the solder resist material367. In some embodiments, the solder resist material312and/or the solder resist material314may be omitted. Conductive pathways may extend through the insulating material310between the first face324and the second face326of the package substrate304, electrically coupling various ones of the conductive contacts399to various ones of the conductive contacts379, in any desired manner. The insulating material310may be a dielectric material (e.g., an ILD), and may take the form of any of the embodiments of the insulating material130disclosed herein, for example. The conductive pathways may include one or more conductive vias395and/or one or more conductive lines397, for example. For example, the package substrate304may include one or more conductive pathways313to electrically couple the die302to conductive contacts399on the first face324of the package substrate304; these conductive pathways313may be used to allow the die302to electrically communicate with a circuit component to which the quantum dot device package300is coupled (e.g., a circuit board or interposer, as discussed below). The package substrate304may include one or more conductive pathways319to electrically couple the die350to conductive contacts399on the first face324of the package substrate304; these conductive pathways319may be used to allow the die350to electrically communicate with a circuit component to which the quantum dot device package300is coupled (e.g., a circuit board or interposer, as discussed below). The package substrate304may include one or more conductive pathways317to electrically couple the die302to the die350through the package substrate304. In particular, the package substrate304may include conductive pathways317that couple different ones of the conductive contacts379on the second face326of the package substrate304so that, when the die302and the die350are coupled to these different conductive contacts379, the die302and the die350may communicate through the package substrate304. Although the die302and the die350are illustrated inFIG.84as being disposed on the same second face326of the package substrate304, in some embodiments, the die302and the die350may be disposed on different faces of the package substrate304(e.g., one on the first face324and one on the second face326), and may communicate via one or more conductive pathways317. In some embodiments, the conductive pathways317may be microwave transmission lines. Microwave transmission lines may be structured for the effective transmission of microwave signals, and may take the form of any microwave transmission lines known in the art. For example, a conductive pathway317may be a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. The die350may provide microwave pulses along the conductive pathways317to the die302to provide electron spin resonance (ESR) pulses to the quantum dot device(s)100to manipulate the spin states of the quantum dots142that form therein. In some embodiments, the die350may generate a microwave pulse that is transmitted over a conductive pathway317and induces a magnetic field in the magnet line(s)121of a quantum dot device100and causes a transition between the spin-up and spin-down states of a quantum dot142. In some embodiments, the die350may generate a microwave pulse that is transmitted over a conductive pathway317and induces a magnetic field in a gate106/108to cause a transition between the spin-up and spin-down states of a quantum dot142. The die350may enable any such embodiments, or any combination of such embodiments. The die350may provide any suitable control signals to the die302to enable operation of the quantum dot device(s)100included in the die302. For example, the die350may provide voltages (through the conductive pathways317) to the gates106/108, and thereby tune the energy profile in the quantum well stack146. In some embodiments, the quantum dot device package300may be a cored package, one in which the package substrate304is built on a carrier material (not shown) that remains in the package substrate304. In such embodiments, the carrier material may be a dielectric material that is part of the insulating material310; laser vias or other through-holes may be made through the carrier material to allow conductive pathways313and/or319to extend between the first face324and the second face326. In some embodiments, the package substrate304may be or may otherwise include a silicon interposer, and the conductive pathways313and/or319may be through-silicon vias. Silicon may have a desirably low coefficient of thermal expansion compared with other dielectric materials that may be used for the insulating material310, and thus may limit the degree to which the package substrate304expands and contracts during temperature changes relative to such other materials (e.g., polymers having higher coefficients of thermal expansion). A silicon interposer may also help the package substrate304achieve a desirably small line width and maintain high connection density to the die302and/or the die350. Limiting differential expansion and contraction may help preserve the mechanical and electrical integrity of the quantum dot device package300as the quantum dot device package300is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower temperatures). In some embodiments, thermal expansion and contraction in the package substrate304may be managed by maintaining an approximately uniform density of the conductive material in the package substrate304(so that different portions of the package substrate304expand and contract uniformly), using reinforced dielectric materials as the insulating material310(e.g., dielectric materials with silicon dioxide fillers), or utilizing stiffer materials as the insulating material310(e.g., a prepreg material including glass cloth fibers). In some embodiments, the die350may be formed of semiconductor materials or compound semiconductor materials (e.g., group III-group V compounds) to enable higher efficiency amplification and signal generation to minimize the heat generated during operation and reduce the impact on the quantum operations of the die302. In some embodiments, the metallization in the die350may use superconducting materials (e.g., titanium nitride, niobium, niobium nitride, and niobium titanium nitride) to minimize heating. The conductive contacts365of the die302may be electrically coupled to the conductive contacts379of the package substrate304via the first-level interconnects306, and the conductive contacts371of the die350may be electrically coupled to the conductive contacts379of the package substrate304via the first-level interconnects309. In some embodiments, the first-level interconnects306/309may include solder bumps or balls (as illustrated inFIG.84); for example, the first-level interconnects306/309may be flip chip (or controlled collapse chip connection, “C4”) bumps disposed initially on the die302/die350or on the package substrate304. Second-level interconnects308(e.g., solder balls or other types of interconnects) may couple the conductive contacts399on the first face324of the package substrate304to another component, such as a circuit board (not shown). Examples of arrangements of electronics packages that may include an embodiment of the quantum dot device package300as discussed below with reference toFIG.86. The die302and/or the die350may be brought in contact with the package substrate304using a pick-and-place apparatus, for example, and a reflow or thermal compression bonding operation may be used to couple the die302and/or the die350to the package substrate304via the first-level interconnects306and/or the first-level interconnects309, respectively. The conductive contacts365,371,379, and/or399may include multiple layers of material that may be selected to serve different purposes. In some embodiments, the conductive contacts365,371,379, and/or399may be formed of aluminum, and may include a layer of gold (e.g., with a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit the oxidation of the surface of the contacts and improve the adhesion with adjacent solder. In some embodiments, the conductive contacts365,371,379, and/or399may be formed of aluminum, and may include a layer of a barrier metal such as nickel, as well as a layer of gold, wherein the layer of barrier metal is disposed between the aluminum and the layer of gold, and the layer of gold is disposed between the barrier metal and the adjacent interconnect. In such embodiments, the gold may protect the barrier metal surface from oxidation before assembly, and the barrier metal may limit the diffusion of solder from the adjacent interconnects into the aluminum. In some embodiments, the structures and materials in the quantum dot device100may be damaged if the quantum dot device100is exposed to the high temperatures that are common in conventional integrated circuit processing (e.g., greater than 100 degrees Celsius, or greater than 200 degrees Celsius). In particular, in embodiments in which the first-level interconnects306/309include solder, the solder may be a low temperature solder (e.g., a solder having a melting point below 100 degrees Celsius) so that it can be melted to couple the conductive contacts365/371and the conductive contacts379without having to expose the die302to higher temperatures and risk damaging the quantum dot device100. Examples of solders that may be suitable include indium-based solders (e.g., solders including indium alloys). When low temperature solders are used, however, these solders may not be fully solid during handling of the quantum dot device package300(e.g., at room temperature or temperatures between room temperature and 100 degrees Celsius), and thus the solder of the first-level interconnects306/309alone may not reliably mechanically couple the die302/die350and the package substrate304(and thus may not reliably electrically couple the die302/die350and the package substrate304). In some such embodiments, the quantum dot device package300may further include a mechanical stabilizer to maintain mechanical coupling between the die302/die350and the package substrate304, even when solder of the first-level interconnects306/309is not solid. Examples of mechanical stabilizers may include an underfill material disposed between the die302/die350and the package substrate304, a corner glue disposed between the die302/die350and the package substrate304, an overmold material disposed around the die302/die350on the package substrate304, and/or a mechanical frame to secure the die302/die350and the package substrate304. In some embodiments of the quantum dot device package300, the die350may not be included in the package300; instead, the die350may be electrically coupled to the die302through another type of common physical support. For example, the die350may be separately packaged from the die302(e.g., the die350may be mounted to its own package substrate), and the two packages may be coupled together through an interposer, a printed circuit board, a bridge, a package-on-package arrangement, or in any other manner. Examples of device assemblies that may include the die302and the die350in various arrangements are discussed below with reference toFIG.86. FIGS.85A-Bare top views of a wafer450and dies452that may be formed from the wafer450; the dies452may be included in any of the quantum dot device packages (e.g., the quantum dot device package300) disclosed herein. The wafer450may include semiconductor material and may include one or more dies452having conventional and quantum dot device elements formed on a surface of the wafer450. Each of the dies452may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum dot device. After the fabrication of the semiconductor product is complete, the wafer450may undergo a singulation process in which each one of the dies452is separated from the others to provide discrete “chips” of the semiconductor product. A die452may include one or more quantum dot devices100and/or supporting circuitry to route electrical signals to the quantum dot devices100(e.g., interconnects including conductive vias and lines), as well as any other integrated circuit (IC) components. In some embodiments, the wafer450or the die452may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die452. For example, a memory array formed by multiple memory devices may be formed on a same die452as a processing device (e.g., the processing device2002ofFIG.88) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. FIG.86is a cross-sectional side view of a device assembly400that may include any of the embodiments of the quantum dot device packages300disclosed herein. The device assembly400includes a number of components disposed on a circuit board402. The device assembly400may include components disposed on a first face440of the circuit board402and an opposing second face442of the circuit board402; generally, components may be disposed on one or both faces440and442. In some embodiments, the circuit board402may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board402. In other embodiments, the circuit board402may be a package substrate or flexible board. In some embodiments, the die302and the die350(FIG.84) may be separately packaged and coupled together via the circuit board402(e.g., the conductive pathways317may run through the circuit board402). The device assembly400illustrated inFIG.86includes a package-on-interposer structure436coupled to the first face440of the circuit board402by coupling components416. The coupling components416may electrically and mechanically couple the package-on-interposer structure436to the circuit board402, and may include solder balls (as shown inFIG.84), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. The package-on-interposer structure436may include a package420coupled to an interposer404by coupling components418. The coupling components418may take any suitable form for the application, such as the forms discussed above with reference to the coupling components416. For example, the coupling components418may be the second-level interconnects308. Although a single package420is shown inFIG.86, multiple packages may be coupled to the interposer404; indeed, additional interposers may be coupled to the interposer404. The interposer404may provide an intervening substrate used to bridge the circuit board402and the package420. The package420may be a quantum dot device package300or may be a conventional IC package, for example. In some embodiments, the package420may take the form of any of the embodiments of the quantum dot device package300disclosed herein, and may include a quantum dot device die302coupled to a package substrate304(e.g., by flip chip connections). Generally, the interposer404may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer404may couple the package420(e.g., a die) to a ball grid array (BGA) of the coupling components416for coupling to the circuit board402. In the embodiment illustrated inFIG.86, the package420and the circuit board402are attached to opposing sides of the interposer404; in other embodiments, the package420and the circuit board402may be attached to a same side of the interposer404. In some embodiments, three or more components may be interconnected by way of the interposer404. In some embodiments, a quantum dot device package300including the die302and the die350(FIG.84) may be one of the packages disposed on an interposer like the interposer404. In some embodiments, the die302and the die350(FIG.84) may be separately packaged and coupled together via the interposer404(e.g., the conductive pathways317may run through the interposer404). The interposer404may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer404may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-group V compounds and group IV materials. The interposer404may include metal interconnects408and vias410, including but not limited to through-silicon vias (TSVs)406. The interposer404may further include embedded devices414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer404. The package-on-interposer structure436may take the form of any of the package-on-interposer structures known in the art. The device assembly400may include a package424coupled to the first face440of the circuit board402by coupling components422. The coupling components422may take the form of any of the embodiments discussed above with reference to the coupling components416, and the package424may take the form of any of the embodiments discussed above with reference to the package420. The package424may be a quantum dot device package300(e.g., including the die302and the die350, or just the die302) or may be a conventional IC package, for example. In some embodiments, the package424may take the form of any of the embodiments of the quantum dot device package300disclosed herein, and may include a quantum dot device die302coupled to a package substrate304(e.g., by flip chip connections). The device assembly400illustrated inFIG.86includes a package-on-package structure434coupled to the second face442of the circuit board402by coupling components428. The package-on-package structure434may include a package426and a package432coupled together by coupling components430such that the package426is disposed between the circuit board402and the package432. The coupling components428and430may take the form of any of the embodiments of the coupling components416discussed above, and the packages426and432may take the form of any of the embodiments of the package420discussed above. Each of the packages426and432may be a quantum dot device package300or may be a conventional IC package, for example. In some embodiments, one or both of the packages426and432may take the form of any of the embodiments of the quantum dot device package300disclosed herein, and may include a die302coupled to a package substrate304(e.g., by flip chip connections). In some embodiments, a quantum dot device package300including the die302and the die350(FIG.84) may be one of the packages in a package-on-package structure like the package-on-package structure434. In some embodiments, the die302and the die350(FIG.84) may be separately packaged and coupled together using a package-on-package structure like the package-on-package structure434(e.g., the conductive pathways317may run through a package substrate of one or both of the packages of the dies302and350). A number of techniques are disclosed herein for operating a quantum dot device100.FIG.87is a flow diagram of a particular illustrative method1020of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method1020are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method1020may be illustrated with reference to one or more of the embodiments discussed above, but the method1020may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein). At1022, electrical signals may be provided to one or more first gates disposed above a quantum well stack as part of causing a first quantum well to form in a quantum well layer in the quantum well stack. The quantum well stack may take the form of any of the embodiments disclosed herein (e.g., the quantum well stacks146discussed above with reference toFIGS.46-48), and may be included in any of the quantum dot devices100disclosed herein. For example, a voltage may be applied to a gate108-11as part of causing a first quantum well (for a first quantum dot142) to form in the quantum well stack146below the gate108-11. At1024, electrical signals may be provided to one or more second gates disposed above the quantum well stack as part of causing a second quantum well to form in the quantum well layer. For example, a voltage may be applied to the gate108-12as part of causing a second quantum well (for a second quantum dot142) to form in the quantum well stack146below the gate108-12. At1026, electrical signals may be provided to one or more third gates disposed above the quantum well stack as part of (1) causing a third quantum well to form in the quantum well layer or (2) providing a potential barrier between the first quantum well and the second quantum well. For example, a voltage may be applied to the gate106-12as part of (1) causing a third quantum well (for a third quantum dot142) to form in the quantum well stack146below the gate106-12(e.g., when the gate106-12acts as a “plunger” gate) or (2) providing a potential barrier between the first quantum well (under the gate108-11) and the second quantum well (under the gate108-12) (e.g., when the gate106-12acts as a “barrier” gate). FIG.88is a block diagram of an example quantum computing device2000that may include any of the quantum dot devices disclosed herein. A number of components are illustrated inFIG.88as included in the quantum computing device2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device2000may be attached to one or more PCBs (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single SoC die. Additionally, in various embodiments, the quantum computing device2000may not include one or more of the components illustrated inFIG.88, but the quantum computing device2000may include interface circuitry for coupling to the one or more components. For example, the quantum computing device2000may not include a display device2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2006may be coupled. In another set of examples, the quantum computing device2000may not include an audio input device2024or an audio output device2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2024or audio output device2008may be coupled. The quantum computing device2000may include a processing device2002(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device2002may include a quantum processing device2026(e.g., one or more quantum processing devices), and a non-quantum processing device2028(e.g., one or more non-quantum processing devices). The quantum processing device2026may include one or more of the quantum dot devices100disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices100, and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device2026may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device2026may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device2026may also include support circuitry to support the processing capability of the quantum processing device2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters. For example, the quantum processing device2026may include circuitry (e.g., a current source) to provide current pulses to one or more magnet lines121included in the quantum dot device100. As noted above, the processing device2002may include a non-quantum processing device2028. In some embodiments, the non-quantum processing device2028may provide peripheral logic to support the operation of the quantum processing device2026. For example, the non-quantum processing device2028may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device2028may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device2026. For example, the non-quantum processing device2028may interface with one or more of the other components of the quantum computing device2000(e.g., the communication chip2012discussed below, the display device2006discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device2026and conventional components. The non-quantum processing device2028may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The quantum computing device2000may include a memory2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., ROM), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device2026may be read and stored in the memory2004. In some embodiments, the memory2004may include memory that shares a die with the non-quantum processing device2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-M RAM). The quantum computing device2000may include a cooling apparatus2030. The cooling apparatus2030may maintain the quantum processing device2026at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 Kelvin or less. In some embodiments, the non-quantum processing device2028(and various other components of the quantum computing device2000) may not be cooled by the cooling apparatus2030, and may instead operate at room temperature. The cooling apparatus2030may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the quantum computing device2000may include a communication chip2012(e.g., one or more communication chips). For example, the communication chip2012may be configured for managing wireless communications for the transfer of data to and from the quantum computing device2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip2012may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip2012may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip2012may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip2012may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip2012may operate in accordance with other wireless protocols in other embodiments. The quantum computing device2000may include an antenna2022to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). In some embodiments, the communication chip2012may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2012may include multiple communication chips. For instance, a first communication chip2012may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2012may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2012may be dedicated to wireless communications, and a second communication chip2012may be dedicated to wired communications. The quantum computing device2000may include battery/power circuitry2014. The battery/power circuitry2014may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device2000to an energy source separate from the quantum computing device2000(e.g., AC line power). The quantum computing device2000may include a display device2006(or corresponding interface circuitry, as discussed above). The display device2006may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example. The quantum computing device2000may include an audio output device2008(or corresponding interface circuitry, as discussed above). The audio output device2008may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example. The quantum computing device2000may include an audio input device2024(or corresponding interface circuitry, as discussed above). The audio input device2024may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The quantum computing device2000may include a GPS device2018(or corresponding interface circuitry, as discussed above). The GPS device2018may be in communication with a satellite-based system and may receive a location of the quantum computing device2000, as known in the art. The quantum computing device2000may include an other output device2010(or corresponding interface circuitry, as discussed above). Examples of the other output device2010may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. The quantum computing device2000may include an other input device2020(or corresponding interface circuitry, as discussed above). Examples of the other input device2020may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. The quantum computing device2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. The following paragraphs provide various examples of the embodiments disclosed herein. Example 1 is a quantum dot device, including: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack. Example 2 includes the subject matter of Example 1, and further specifies that the first gate dielectric has a U-shaped cross-section. Example 3 includes the subject matter of any of Examples 1-2, and further specifies that the first gate is at least partially between a portion of the second gate dielectric and the quantum well stack. Example 4 includes the subject matter of any of Examples 1-3, and further specifies that the first gate is at least partially between a portion of the second gate metal and the quantum well stack. Example 5 includes the subject matter of any of Examples 1-4, and further specifies that the first gate dielectric is at least partially between a portion of the second gate metal and the quantum well stack. Example 6 includes the subject matter of any of Examples 1-5, and further specifies that the first gate metal is at least partially between a portion of the second gate dielectric and the quantum well stack. Example 7 includes the subject matter of any of Examples 1-6, and further specifies that the first gate metal is at least partially between a portion of the second gate metal and the quantum well stack. Example 8 includes the subject matter of any of Examples 1-7, and further specifies that the first gate dielectric and the second gate dielectric have different material structures. Example 9 includes the subject matter of any of Examples 1-8, and further specifies that the first gate dielectric and the second gate dielectric have a same material structure. Example 10 includes the subject matter of any of Examples 1-9, and further specifies that the first gate metal and the second gate metal have different material structures. Example 11 includes the subject matter of any of Examples 1-9, and further specifies that the first gate metal and the second gate metal have a same material structure. Example 12 includes the subject matter of any of Examples 1-11, and further includes: a dielectric cap at least partially between the first gate metal and the second gate. Example 13 includes the subject matter of Example 12, and further specifies that side surfaces of the dielectric cap contact the first gate dielectric. Example 14 includes the subject matter of any of Examples 12-13, and further specifies that the second gate dielectric contacts the dielectric cap. Example 15 includes the subject matter of any of Examples 1-14, and further includes: at least one dielectric spacer above the first gate. Example 16 includes the subject matter of Example 15, and further specifies that the second gate dielectric is in contact with at least one dielectric spacer. Example 17 includes the subject matter of any of Examples 1-16, and further includes: a gate wall between the first gate and the second gate, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material. Example 18 includes the subject matter of Example 17, and further specifies that the second dielectric material includes silicon nitride. Example 19 includes the subject matter of any of Examples 17-18, and further specifies that the first dielectric material includes aluminum oxide. Example 20 includes the subject matter of any of Examples 17-18, and further specifies that the first dielectric material includes silicon carbide. Example 21 includes the subject matter of any of Examples 17-18, and further specifies that the first dielectric material includes silicon nitride. Example 22 includes the subject matter of any of Examples 17-21, and further specifies that the second dielectric material is a spacer. Example 23 includes the subject matter of Example 22, and further specifies that the first dielectric material is at least partially between the second dielectric material and the quantum well stack. Example 24 includes the subject matter of any of Examples 17-23, and further specifies that the first dielectric material is at least partially between the second dielectric material and the quantum well stack. Example 25 includes the subject matter of any of Examples 17-24, and further specifies that the first dielectric material has an L-shaped cross-section. Example 26 includes the subject matter of any of Examples 1-25, and further specifies that first gate metal has a height that is different from a height of the second gate metal. Example 27 includes the subject matter of any of Examples 1-26, and further specifies that the quantum well stack is at least partially included in a fin. Example 28 includes the subject matter of any of Examples 1-26, and further specifies that the first gate and the second gate are at least partially disposed in a trench in an insulating material above the quantum well stack. Example 29 includes the subject matter of any of Examples 1-28, and further includes: doped regions in the quantum well stack. Example 30 is a method of operating a quantum dot device, including: providing electrical signals to a first gate above a quantum well stack as part of causing a first quantum well to form in a quantum well layer in the quantum well stack; providing electrical signals to a second gate above the quantum well stack as part of causing a second quantum well to form in the quantum well layer in the quantum well stack; and providing electrical signals to a third gate above the quantum well stack to (1) cause a third quantum well to form in the quantum well layer in the quantum well stack or (2) provide a potential barrier between the first quantum well and the second quantum well; wherein a gate dielectric of the third gate extends over the first gate and also extends over the second gate. Example 31 includes the subject matter of Example 30, and further specifies that at least two of the first, second, or third gate have a gate wall between them, the gate wall includes a first dielectric material and a second dielectric material, and the first dielectric material is at least partially between the second dielectric material and the quantum well stack. Example 32 includes the subject matter of Example 31, and further specifies that the first dielectric material is at least partially between the second dielectric material and a gate metal of at least one of the first, second, or third gates. Example 33 includes the subject matter of any of Examples 30-32, and further specifies that the third gate is adjacent to a first spacer above the first gate and a second spacer above the second gate. Example 34 includes the subject matter of Example 33, and further specifies that the first spacer and the second spacer have convex curvature towards the third gate. Example 35 is a method of manufacturing a quantum dot device, including: forming a quantum well stack; forming a first set of gates above the quantum well stack; forming a patterned insulating material over the first set of gates, wherein openings in the patterned insulating material expose the quantum well stack in regions between adjacent pairs of individual gates in the first set of gates; and forming a second set of gates in the openings in the patterned insulating material. Example 36 includes the subject matter of Example 35, and further specifies that the openings in the patterned insulating material expose top surfaces of gate walls at sides of individual gates in the first set of gates. Example 37 includes the subject matter of any of Examples 35-36, and further includes: after forming the patterned insulating material, forming spacers at side surfaces of the patterned insulating material, above individual gates in the first set of gates. Example 38 includes the subject matter of any of Examples 35-37, and further specifies that forming the second set of gates includes: forming a conformal gate dielectric on side surfaces of the openings; and depositing a gate metal on the conformal gate dielectric. Example 39 includes the subject matter of Example 38, and further includes: recessing the gate metal; and forming dielectric caps on the recessed gate metal. Example 40 includes the subject matter of any of Examples 35-39, and further specifies that forming the first set of gates includes: recessing a gate metal of the first set of gates; and forming dielectric caps on the recessed gate metal of the first set of gates. Example 41 includes the subject matter of any of Examples 35-40, and further specifies that forming the first set of gates includes: depositing a dummy material above the quantum well stack; patterning the dummy material into dummy gates; depositing a barrier layer conformally on the dummy gates; and forming spacers on the barrier layer on sidewalls of the dummy gates. Example 42 includes the subject matter of Example 41, and further specifies that the dummy material is a first dummy material, and forming the first set of gates further includes: depositing a second dummy material between the spacers; after depositing the second dummy material, removing the first dummy material; after removing the first dummy material, conformally depositing a gate dielectric; and after conformally depositing the gate dielectric, depositing a gate metal. Example 43 includes the subject matter of Example 42, and further specifies that the gate dielectric is a first gate dielectric, the gate metal is a first gate metal, and forming the second set of gates further includes: after depositing the first gate metal, removing the second dummy material; and removing at least some of the barrier layer on the quantum well stack. Example 44 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes at least one quantum well layer and a plurality of gates above the quantum well layer to control quantum dot formation in the quantum well layer, and wherein a gate dielectric of a first gate extends over a second gate adjacent to the first gate; and a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates. Example 45 includes the subject matter of Example 44, and further includes: a package substrate, wherein the quantum processing device is coupled to the package substrate. Example 46 includes the subject matter of any of Examples 44-45, and further specifies that the gate dielectric of the first gate is spaced apart from gate dielectric of the second gate by a gate wall, and the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material. Example 47 includes the subject matter of Example 46, and further specifies that the first dielectric material has an L-shaped cross-section. Example 48 includes the subject matter of any of Examples 46-47, and further specifies that the second dielectric material is a spacer. Example 49 includes the subject matter of any of Examples 44-48, and further includes: a refrigeration unit. Example 50 includes the subject matter of any of Examples 44-49, and further specifies that the plurality of gates is on a fin or in a trench. | 173,473 |
11942517 | DETAILED DESCRIPTION Problem to be Solved by the Present Disclosure It is an object of the present disclosure to provide: a silicon carbide semiconductor device in which a charge balance in a superjunction portion can be maintained excellently; and a method of manufacturing such a silicon carbide semiconductor device. Advantageous Effect of the Present Disclosure According to the present disclosure, there can be provided: a silicon carbide semiconductor device in which a charge balance in a superjunction portion can be maintained excellently; and a method of manufacturing such a silicon carbide semiconductor device. DESCRIPTION OF EMBODIMENTS First, embodiments of the present disclosure are listed and described. Regarding crystallographic indications in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, and an individual plane is represented by ( ) and a group plane is represented by { }. A crystallographically negative index is normally expressed by putting “-” (bar) above a numeral; however, in the present specification, the crystallographically negative index is expressed by putting a negative sign before the numeral. (1) A silicon carbide semiconductor device200according to the present disclosure includes a silicon carbide substrate100, a first insulator80, a first electrode60, and a second electrode70. Silicon carbide substrate100has a first main surface1and a second main surface2opposite to first main surface1. Silicon carbide substrate100includes: a first impurity region11located between first main surface1and second main surface2, first impurity region11having a first conductivity type; a second impurity region12located between first main surface1and second main surface2, second impurity region12being provided in contact with first impurity region11, second impurity region12having a second conductivity type different from the first conductivity type; a third impurity region13located between first main surface1and second main surface2, third impurity region13being provided in contact with second impurity region12so as to be separated from first impurity region11, third impurity region13having the first conductivity type; a first superjunction portion16having a first region31and a second region32, first region31being in contact with first impurity region11, first region31being located between first impurity region11and second main surface2, first region31having the first conductivity type, second region32being in contact with each of second impurity region12and first region31, second region32having the second conductivity type; a fourth impurity region21located between first main surface1and second main surface2, fourth impurity region21having the first conductivity type; a fifth impurity region22located between first main surface1and second main surface2, fifth impurity region22being provided in contact with fourth impurity region21, fifth impurity region22having the second conductivity type; a sixth impurity region23located between first main surface1and second main surface2, sixth impurity region23being provided in contact with fifth impurity region22so as to be separated from fourth impurity region21, sixth impurity region23having the first conductivity type; and a second superjunction portion26having a third region33and a fourth region34, third region33being in contact with fourth impurity region21, third region33being located between fourth impurity region21and second main surface2, third region33having the first conductivity type, fourth region34being in contact with each of fifth impurity region22and third region33, fourth region34having the second conductivity type. Second region32has a first end surface17in contact with second impurity region12, and a second end surface3opposite to first end surface17. Fourth region34has a third end surface27in contact with fifth impurity region22, and a fourth end surface4opposite to third end surface27. First region31, second region32, fourth region34, and third region33are provided side by side in a first direction101parallel to second main surface2. Second region32is located between first region31and fourth region34, and fourth region34is located between second region32and third region33. First main surface1is provided with a first trench8that separates second region32and fourth region34from each other. A first insulator80is provided inside first trench8. A bottom surface7of first trench8is located between second end surface3and second main surface2and is located between fourth end surface4and second main surface2in a direction perpendicular to second main surface2. (2) In silicon carbide semiconductor device200according to (1), an impurity concentration of each of first region31and third region33may be more than or equal to 3×1016cm−3and less than or equal to 3×1017cm−3. (3) In silicon carbide semiconductor device200according to (1) or (2), when it is assumed that a width of first region31is a first width W1and a width of second region32is a second width W2in first direction101and when it is assumed that an impurity concentration of first region31is a first concentration and an impurity concentration of second region32is a second concentration, a value obtained by dividing, by a value obtained by multiplying the second concentration by second width W2, a value obtained by multiplying the first concentration by first width W1may be more than or equal to 0.5 and less than or equal to 1.5, and when it is assumed that a width of third region33is a third width W3and a width of fourth region34is a fourth width W4in first direction101and when it is assumed that an impurity concentration of third region33is a third concentration and an impurity concentration of fourth region34is a fourth concentration, a value obtained by dividing, by a value obtained by multiplying the fourth concentration by fourth width W4, a value obtained by multiplying the third concentration by third width W3may be more than or equal to 0.5 and less than or equal to 1.5. (4) In silicon carbide semiconductor device200according to (3), each of second width W2and fourth width W4may be more than or equal to 0.1 μm and less than or equal to 2 μm. (5) In silicon carbide semiconductor device200according to any one of (1) to (4), a width of first trench8in first direction101may be more than or equal to 1 μm and less than or equal to 3 μm. (6) In silicon carbide semiconductor device200according to any one of (1) to (5), a depth of first trench8may be more than or equal to 3 μm and less than or equal to 30 μm. (7) In silicon carbide semiconductor device200according to any one of (1) to (6), a value obtained by dividing a depth of first trench8by a width of first trench8in first direction101may be more than or equal to 0.5 and less than or equal to 25. (8) In silicon carbide semiconductor device200according to any one of (1) to (7), first trench8may have a first side surface5and a second side surface6, first side surface5being in contact with second region32, first side surface5being recessed from second region32toward first region31, second side surface6being in contact with fourth region34, second side surface6being recessed from fourth region34toward third region33. (9) In silicon carbide semiconductor device200according to (8), a value obtained by subtracting a minimum width of first region31from a maximum width of first region31in first direction101may be more than or equal to 0.05 μm and less than or equal to 2.0 μm, and a value obtained by subtracting a minimum width of third region33from a maximum width of third region33in first direction101may be more than or equal to 0.05 μm and less than or equal to 2.0 μm. (10) In silicon carbide semiconductor device200according to any one of (1) to (9), first impurity region11and first region31may be in one piece and fourth impurity region21and third region33may be in one piece. (11) In silicon carbide semiconductor device200according to any one of (1) to (10), first main surface1may be provided with a second trench9that surrounds first trench8when viewed in the direction perpendicular to second main surface2, and silicon carbide semiconductor device200may further include a second insulator90provided inside second trench9. (12) A method of manufacturing a silicon carbide semiconductor device200according to the present disclosure includes the following steps. A silicon carbide epitaxial substrate100including a silicon carbide single crystal substrate50and a silicon carbide epitaxial layer40is prepared, silicon carbide epitaxial layer40being provided on silicon carbide single crystal substrate50, silicon carbide epitaxial layer40having impurity ions capable of imparting a first conductivity type. A trench8is formed in silicon carbide epitaxial layer40, trench8having a first side surface5and a second side surface6opposite to first side surface5. A second region32is formed by obliquely implanting, into first side surface5, impurity ions capable of imparting a second conductivity type. A fourth region34is formed by obliquely implanting, into second side surface6, the impurity ions capable of imparting the second conductivity type. Silicon carbide epitaxial layer40includes a first superjunction portion16and a second superjunction portion26, first superjunction portion16having a first region31and second region32, first region31having the first conductivity type, first region31being in contact with second region32, second superjunction portion26having a third region33and fourth region34, third region33having the first conductivity type, third region33being in contact with fourth region34. A bottom surface7of trench8is located between silicon carbide single crystal substrate50and each of second region32and fourth region34in a direction perpendicular to a boundary surface45between silicon carbide single crystal substrate50and silicon carbide epitaxial layer40. Trench8is filled with an insulator80. (13) In method of manufacturing silicon carbide semiconductor device200according to (12), in each of the forming of second region32and the forming of fourth region34, the impurity ions capable of imparting the second conductivity type may be implanted into bottom surface7. The impurity ions capable of imparting the second conductivity type and implanted in bottom surface7may be removed by etching. (14) In method of manufacturing a silicon carbide semiconductor device200according to (12), in each of the forming of second region32and the forming of fourth region34, oblique implantation is performed to avoid the impurity ions capable of imparting the second conductivity type from being implanted into bottom surface7. DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments of the present disclosure will be described in detail. In the description below, the same or corresponding elements are denoted by the same reference numerals, and will not be described repeatedly. First Embodiment First, a configuration of a silicon carbide semiconductor device200according to a first embodiment will be described.FIG.1is a schematic cross sectional view showing the configuration of silicon carbide semiconductor device200according to the first embodiment. As shown inFIG.1, silicon carbide semiconductor device200according to the first embodiment is, for example, a planar type MOSFET, and mainly includes a silicon carbide substrate100, gate electrodes52, gate insulating films51, separation insulating films53, a first electrode60, a second electrode70, and first insulators80. Silicon carbide substrate100has a first main surface1and a second main surface2opposite to first main surface1. Silicon carbide substrate100includes a silicon carbide single crystal substrate50and a silicon carbide epitaxial layer40provided on silicon carbide single crystal substrate50. Silicon carbide single crystal substrate50forms second main surface2. Silicon carbide epitaxial layer40forms first main surface1. Silicon carbide single crystal substrate50is composed of, for example, hexagonal silicon carbide having a polytype of4H. First main surface1corresponds to, for example, a {0001} plane or a plane angled off by less than or equal to 8° with respect to the {0001} plane. Specifically, first main surface1corresponds to, for example, a (0001) plane or a plane angled off by less than or equal to 8° with respect to the (0001) plane. First main surface1may correspond to, for example, a (000-1) plane or a plane angled off by less than or equal to 8° with respect to the (000-1) plane. Silicon carbide substrate100includes a first impurity region11, second impurity regions12, third impurity regions13, first contact regions14, and a first superjunction portion16. First impurity region11includes an n type impurity capable of imparting the n type, such as N (nitrogen). First impurity region11has, for example, the n type (first conductivity type). First impurity region11is, for example, a drift region. Second impurity regions12are provided in contact with first impurity region11. First impurity region11is located between first main surface1and second main surface2. Each of second impurity regions12includes a p type impurity capable of imparting the p type, such as Al (aluminum). Second impurity region12has p type (second conductivity type) different from the n type. Second impurity region12is, for example, a body region. The concentration of the p type impurity included in second impurity region12may be higher than the concentration of the n type impurity included in first impurity region11. Second impurity region12is located between first main surface1and second main surface2. Second impurity region12may have a fifth region41and a sixth region42. The concentration of the p type impurity included in fifth region41may be higher than the concentration of the p type impurity included in sixth region42. Fifth region41is in contact with second region32, third impurity region13, and first contact region14. Sixth region42is in contact with first region31, third impurity region13, and first impurity region11. Third impurity regions13are provided in contact with second impurity regions12so as to be separated from first impurity region11. Each of third impurity regions13includes an n type impurity capable of imparting the n type, such as P (phosphorus). Third impurity region13has, for example, the n type. Third impurity region13is, for example, a source region. Third impurity region13is located between first main surface1and second main surface2. The concentration of the n type impurity included in third impurity region13may be higher than the concentration of the p type impurity included in second impurity region12. Each of first contact regions14includes a p type impurity capable of imparting the p type, such as Al. First contact region14has the p type. The concentration of the p type impurity included in first contact region14may be higher than the concentration of the p type impurity included in second impurity region12. First superjunction portion16has a first region31and second regions32. First region31is in contact with first impurity region11. First region31is located between first impurity region11and second main surface2. First region31includes an n type impurity capable of imparting the n type, such as N. First region31has, for example, the n type. First region31may be in contact with second impurity regions12. Second regions32are in contact with second impurity regions12and first region31. Each of second regions32includes a p type impurity capable of imparting the p type, such as Al. Second region32has, for example, the p type. First region31is interposed between the pair of second regions32, for example. First region31and second regions32form first superjunction portion16. As shown inFIG.1, when viewed in a direction (second direction102) perpendicular to each of a first direction101and a third direction103, each of first region31and second regions32has a columnar shape. Silicon carbide substrate100includes a fourth impurity region21, fifth impurity regions22, sixth impurity regions23, second contact regions24, and a second superjunction portion26. Fourth impurity region21includes an n type impurity capable of imparting the n type, such as N. Fourth impurity region21has, for example, the n type (first conductivity type). Fourth impurity region21is, for example, a drift region. Fourth impurity region21is located between first main surface1and second main surface2. Fifth impurity regions22are provided in contact with fourth impurity region21. Each of fifth impurity region22includes a p type impurity capable of imparting the p type, such as Al. Fifth impurity region22has the p type (second conductivity type) different from the n type. Fifth impurity region22is, for example, a body region. The concentration of the p type impurity included in fifth impurity region22may be higher than the concentration of the n type impurity included in fourth impurity region21. Fifth impurity region22is located between first main surface1and second main surface2. Fifth impurity region22may have a seventh region43and an eighth region44. The concentration of the p type impurity included in seventh region43may be higher than the concentration of the p type impurity included in eighth region44. Seventh region43is in contact with fourth region34, sixth impurity region23, and second contact region24. Eighth region44is in contact with third region33, sixth impurity region23, and fourth impurity region21. Sixth impurity regions23are provided in contact with fifth impurity regions22so as to be separated from fourth impurity region21. Each of sixth impurity regions23includes an n type impurity capable of imparting the n type, such as P (phosphorus). Sixth impurity region23has, for example, the n type. Sixth impurity region23is, for example, a source region. Sixth impurity region23is located between first main surface1and second main surface2. The concentration of the n type impurity included in sixth impurity region23may be higher than the concentration of the p type impurity included in fifth impurity region22. Each of second contact regions24includes a p type impurity capable of imparting the p type, such as Al. Second contact region24has the p type. The concentration of the p type impurity included in second contact region24may be higher than the concentration of the p type impurity included in fifth impurity region22. Second superjunction portion26has a third region33and fourth regions34. Third region33is in contact with fourth impurity region21. Third region33is located between fourth impurity region21and second main surface2. Third region33includes an n type impurity capable of imparting the n type, such as N. Third region33has, for example, the n type. Third region33may be in contact with fifth impurity region22. Fourth regions34are in contact with fifth impurity regions22and third region33. Each of fourth regions34includes a p type impurity capable of imparting the p type, such as Al. Fourth region34has, for example, the p type. Third region33is interposed between fourth regions34, for example. Third region33and fourth regions34form second superjunction portion26. As shown inFIG.1, when viewed in the direction (second direction102) perpendicular to each of first direction101and third direction103, each of third region33and fourth regions34has a columnar shape. First superjunction portion16and second superjunction portion26are alternately disposed in the direction (first direction101) from third region33toward fourth region34. As shown inFIG.1, in the direction (first direction101) from first region31toward second region32, the width of first region31is a first width W1, and the width of second region32is a second width W2. In the direction (first direction101) from third region33toward fourth region34, the width of third region33is a third width W3, and the width of fourth region34is a fourth width W4. It should be noted that when second region32is separated into two regions as shown inFIG.1, the width of second region32refers to the total of the widths of these two second regions32. Similarly, when fourth region34is separated into two regions, the width of fourth region34refers to the total of the widths of these two fourth regions34. Each of second width W2and fourth width W4is, for example, more than or equal to 0.3 μm and less than or equal to 0.5 μm. The upper limit of each of second width W2and fourth width W4is not particularly limited, but may be less than or equal to 1 μm or may be less than or equal to 2 μm, for example. The lower limit of each of second width W2and fourth width W4is not particularly limited, but may be more than or equal to 0.2 μm or may be more than or equal to 0.1 μm, for example. The impurity concentration of each of first region31and third region33is, for example, more than or equal to 3×1016cm−3and less than or equal to 3×1017cm−3. The upper limit of the impurity concentration of each of first region31and third region33is not particularly limited, but may be less than or equal to 5×1017cm−3or may be less than or equal to 1×1018cm−3, for example. The lower limit of the impurity concentration of each of first region31and third region33is not particularly limited, but may be more than or equal to 2×1016cm−3or may be more than or equal to 1×1016cm−3, for example. When it is assumed that the impurity concentration of first region31is a first concentration and the impurity concentration of second region32is a second concentration, a value (first ratio) obtained by dividing, by a value obtained by multiplying the second concentration by second width W2, a value obtained by multiplying the first concentration by first width W1is more than or equal to 0.7 and less than or equal to 1.3. The upper limit of the first ratio is not particularly limited, but may be less than or equal to 1.4 or may be less than or equal to 1.5, for example. The lower limit of the first ratio is not particularly limited, but may be more than or equal to 0.6 or more than or equal to 0.5, for example. When it is assumed that the impurity concentration of third region33is a third concentration and the impurity concentration of fourth region34is a fourth concentration, a value (second ratio) obtained by dividing, by a value obtained by multiplying the fourth concentration by fourth width W4, a value obtained by multiplying the third concentration by third width W3is more than or equal to 0.7 and less than or equal to 1.3. The upper limit of the second ratio is not particularly limited, but may be less than or equal to 1.4 or may be less than or equal to 1.5, for example. The lower limit of the second ratio is not particularly limited, but may be more than or equal to 0.6 or may be more than or equal to 0.5, for example. Silicon carbide substrate100includes a first lower drift region15, a second lower drift region25, and a third lower drift region91. First lower drift region15includes an n type impurity capable of imparting the n type, such as N. First lower drift region15has the n type. First lower drift region15is in contact with each of first region31and second regions32. First lower drift region15is located between second main surface2and each of first region31and second regions32. Second lower drift region25has the n type. Second lower drift region25is in contact with each of third region33and fourth regions34. Second lower drift region25is located between second main surface2and each of third region33and fourth regions34. Third lower drift region91includes an n type impurity capable of imparting the n type, such as N. Third lower drift region91has the n type. Third lower drift region91is located between first lower drift region15and second lower drift region25. Third lower drift region91is contiguous to each of first lower drift region15and second lower drift region25. First lower drift region15is electrically connected to second lower drift region25via third lower drift region91. As shown inFIG.1, first region31, second region32, fourth region34, and third region33are provided side by side in first direction101parallel to second main surface2. Second region32is located between first region31and fourth region34, and fourth region34is located between second region32and third region33. As shown inFIG.1, first main surface1is provided with first trenches8. Each of first trenches8separates second region32and fourth region34from each other. First trench8is located between second region32and fourth region34. First trench8has a first side surface5, a first bottom surface7, and a second side surface6. Second side surface6is opposite to first side surface5. Each of first side surface5and second side surface6is contiguous to first main surface1. First bottom surface7is contiguous to each of first side surface5and second side surface6. Second region32has a first end surface17and a second end surface3. First end surface17is in contact with second impurity region12. Second end surface3is opposite to first end surface17. Fourth region34has a third end surface27and a fourth end surface4. Third end surface27is in contact with fifth impurity region22. Fourth end surface4is opposite to third end surface27. As shown inFIG.1, in the direction (third direction103) perpendicular to second main surface2, first bottom surface7of first trench8is located between second end surface3and second main surface2, and is located between fourth end surface4and second main surface2. From another point of view, it can be said that first bottom surface7of first trench8is located on the second main surface2side with respect to each of second end surface3and fourth end surface4. First contact region14, second impurity region12, second region32, and first lower drift region15are in contact with first side surface5. Second contact region24, fifth impurity region22, fourth region34, and second lower drift region25are in contact with second side surface6. Third lower drift region91is in contact with first bottom surface7. Each of second region32and fourth region34is separated from first bottom surface7. As shown inFIG.1, the width (fifth width W5) of first trench8in the direction (first direction101) from second region32toward fourth region34is, for example, more than or equal to 1 μm and less than or equal to 3 μm. The upper limit of the width of first trench8is not particularly limited, but may be less than or equal to 4 μm or may be less than or equal to 5 μm, for example. The lower limit of the width of first trench8is not particularly limited, but may be more than or equal to 0.75 μm or may be more than or equal to 0.5 μm, for example. As shown inFIG.1, the depth (first depth H1) of first trench8in the thickness direction (third direction103) of silicon carbide substrate100is, for example, more than or equal to 3 μm and less than or equal to 30 μm. The upper limit of the depth of first trench8is not particularly limited, but may be less than or equal to 50 μm or may be less than or equal to 100 μm, for example. The lower limit of the depth of first trench8is not particularly limited, but may be more than or equal to 2 μm or may be more than or equal to 1 μm, for example. A value (aspect ratio) obtained by dividing the depth (first depth H1) of first trench8by the width (fifth width W5) of first trench8in the direction (first direction101) from second region32toward fourth region34is, for example, more than or equal to 2 and less than or equal to 20. The upper limit of the aspect ratio is not particularly limited, but may be more than or equal to 1 or may be more than or equal to 0.5, for example. The lower limit of the aspect ratio is not particularly limited, but may be less than or equal to 25 or may be less than or equal to 50, for example. As shown inFIG.1, first impurity region11and first region31are preferably in one piece. First impurity region11and first region31are preferably in one piece. Specifically, in a boundary region (region of more than or equal to 3 μm) between first impurity region11and first region31, a concentration distribution of the n type impurity along third direction103(value obtained by dividing, by an average concentration, a value obtained by subtracting the minimum concentration from the maximum concentration) is less than or equal to 10. Preferably, first impurity region11, first region31, and first lower drift region15are seamlessly connected to one another. From another point of view, it can be said that first impurity region11, first region31, and first lower drift region15are formed in one epitaxial growth step. Similarly, fourth impurity region21and third region33are preferably in one piece. Specifically, in a boundary region (region of more than or equal to 3 μm) between fourth impurity region21and third region33, a concentration distribution of the n type impurity along third direction103(value obtained by dividing, by an average concentration, a value obtained by subtracting the minimum concentration from the maximum concentration) is less than or equal to 10. Preferably, fourth impurity region21, third region33, and second lower drift region25are seamlessly connected to one another. From another point of view, it can be said that fourth impurity region21, third region33, and second lower drift region25are formed in one epitaxial growth step. First insulator80is provided inside first trench8. From another point of view, it can be said that first trench8is filled with first insulator80. First insulator80is, for example, a BCB (BenzoCycloButene) resin. The BCB resin is excellent in heat resistance, chemical resistance, and filling property. First insulator80may be, for example, a SOG (Spin On Glass) film or a silicon dioxide film. As shown inFIG.1, first impurity region11, second impurity region12, third impurity region13, first contact region14, first region31, second region32, and first lower drift region15may form a first mesa region10. Fourth impurity region21, fifth impurity region22, sixth impurity region23, second contact region24, third region33, fourth region34, and second lower drift region25may form a second mesa region20. First mesa region10and second mesa region20are separated by first insulator80. Each of gate insulating films51is composed of, for example, silicon dioxide. Gate insulating film51is provided in contact with first main surface1. The gate insulating film is in contact with each of first impurity region11, second impurity region12, and third impurity region13at first main surface1. A channel can be formed in second impurity region12that is in contact with gate insulating film51. The gate insulating film is in contact with each of fourth impurity region21, fifth impurity region22, and sixth impurity region23at first main surface1. A channel can be formed in fifth impurity region22that is in contact with gate insulating film51. The thickness of each gate insulating film51is, for example, more than or equal to 40 nm and less than or equal to 150 nm. Gate electrodes52are provided on respective gate insulating films51. Gate electrodes52are disposed in contact with respective gate insulating films51. Each of gate electrodes52is composed of, for example, a conductor such as polysilicon doped with an impurity. Separation insulating films53are provided to cover respective gate electrodes52. Separation insulating films53are in contact with respective gate electrodes52and respective gate insulating films51. Each of separation insulating films53is composed of, for example, a NSG (None-doped Silicate Glass) film, a PSG (Phosphorus Silicate Glass) film, or the like. Separation insulating film53electrically insulates gate electrode52and first electrode60from each other. First electrode60is provided on first main surface1. First electrode60is, for example, a source electrode. First electrode60is electrically connected to each of third impurity regions13and sixth impurity regions23. First electrode60has electrode layers61and a source wiring62. Each of electrode layers61is composed of, for example, a Ni alloy. Electrode layer61is composed of, for example, a material including Ti (titanium), Al (aluminum), and Si (silicon). Source wiring62is composed of, for example, a material including Al. First electrode60may be in contact with each of third impurity regions13and sixth impurity regions23at first main surface1. First electrode60may be in contact with each of first contact regions14and second contact regions24at first main surface1. First electrode60extends over first trench8. First electrode60may be in contact with first insulator80. Second electrode70is provided on second main surface2. Second electrode70is, for example, a drain electrode. Second electrode70is electrically connected to each of first region31and third region33. Second electrode70is in contact with silicon carbide single crystal substrate50at second main surface2. Second electrode70is composed of a material capable of ohmic contact with silicon carbide single crystal substrate50having the n type, such as NiSi (nickel silicide). FIG.2is a schematic cross sectional view taken along a II-II line ofFIG.1. As shown inFIG.2, when viewed in the direction perpendicular to second main surface2, first trench8extends along second direction102. From another point of view, it can be said that the long side direction of first trench8is second direction102. The short side direction of first trench8is first direction101. Similarly, first insulator80extends along second direction102. From another point of view, it can be said that the long side direction of first insulator80is second direction102. The short side direction of first insulator80is first direction101. When viewed in the direction perpendicular to second main surface2, each of first trench8and first insulator80may have a substantially rectangular shape. As shown inFIG.2, each of first impurity region11, second impurity regions12, third impurity regions13, first contact regions14, fourth impurity region21, fifth impurity regions22, sixth impurity regions23, and second contact regions24extends along second direction102. From another point of view, it can be said that the long side direction of each of first impurity region11, second impurity regions12, third impurity regions13, first contact regions14, fourth impurity region21, fifth impurity regions22, sixth impurity regions23, and second contact regions24is second direction102. The short side direction of each of first impurity region11, second impurity regions12, third impurity regions13, first contact regions14, fourth impurity region21, fifth impurity regions22, sixth impurity regions23, and second contact regions24is first direction101. FIG.3is a schematic cross sectional view taken along a line inFIG.1. As shown inFIG.3, when viewed in the direction perpendicular to second main surface2, each of first region31and second regions32extends along second direction102. From another point of view, it can be said that the long side direction of each of first region31and second regions32is second direction102. The short side direction of each of first region31and second regions32is first direction101. In first direction101, second regions32are disposed on the both sides beside first region31. Similarly, when viewed in the direction perpendicular to second main surface2, each of third region33and fourth regions34extends along second direction102. From another point of view, it can be said that the long side direction of each of third region33and fourth regions34is second direction102. The short side direction of each of third region33and fourth regions34is first direction101. In first direction101, fourth regions34are disposed on the both sides beside third region33. It should be noted that in the above description, each of first direction101and second direction102is parallel to second main surface2. Third direction103is perpendicular to second main surface2. First direction101is, for example, a <11-20> direction. Second direction102is, for example, a <1-100> direction. Third direction103is, for example, the <0001> direction. First direction101may be, for example, a direction obtained by projecting the <11-20> direction onto first main surface1. Second direction102may be, for example, a direction obtained by projecting the <1-100> direction onto first main surface1. Third direction103may be, for example, a direction inclined with respect to the <0001> direction. FIG.4is a schematic plan view showing the configuration of silicon carbide semiconductor device200according to the first embodiment.FIG.4only shows first insulators80, a second insulator90, first trench8, a second trench9, and first main surface1, and does not show the other configurations. As shown inFIG.4, the plurality of first trenches8are provided in first main surface1of silicon carbide substrate100. Each of the plurality of first trenches8extends along second direction102. The plurality of first trenches8are disposed to be separated from one another along first direction101. Second trench9is provided in first main surface1. As shown inFIG.4, when viewed in the direction perpendicular to second main surface2, second trench9has an annular shape. When viewed in the direction perpendicular to second main surface2, second trench9surrounds first trench8. Silicon carbide semiconductor device200has second insulators90. Second insulator90is provided inside second trench9. When viewed in the direction perpendicular to second main surface2, second insulator90has an annular shape. When viewed in the direction perpendicular to second main surface2, second insulator90surrounds first insulator80. Second Embodiment Next, a configuration of a silicon carbide semiconductor device200according to a second embodiment will be described. Silicon carbide semiconductor device200according to the second embodiment is different from silicon carbide semiconductor device200according to the first embodiment mainly in terms of such a configuration that first region31and third region33are narrowed, and the other configurations are the same as those of silicon carbide semiconductor device200according to the first embodiment. Hereinafter, the configuration different from that of silicon carbide semiconductor device200according to the first embodiment will be mainly described. FIG.5is a schematic cross sectional view showing the configuration of silicon carbide semiconductor device200according to the second embodiment. As shown inFIG.5, first side surface5of first trench8is in contact with second region32. First side surface5is recessed from second region32toward first region31. Second side surface6of first trench8is in contact with fourth region34. Second side surface6is recessed from fourth region34toward third region33. Each of first side surface5and second side surface6is curved. As shown inFIG.5, in the direction from first main surface1toward second main surface2, the width of first region31at the central portion of first region31may be smaller than the width of first region31at the upper end portion of first region31and may be smaller than the width of first region31at the lower end portion of first region31. In the direction from first region31toward second region32, the maximum width (sixth width W6) of first region31is, for example, more than or equal to 0.5 μm and less than or equal to 5.0 μm. In the direction from first region31toward second region32, the minimum width (seventh width W7) of first region31is, for example, more than or equal to 0.3 μm and less than or equal to 3.0 μm. A value (first difference) obtained by subtracting the minimum width of first region31from the maximum width of first region31in the direction from first region31toward second region32may be, for example, more than or equal to 0.2 μm and less than or equal to 0.5 μm. The upper limit of the first difference is not particularly limited, but may be less than or equal to 1.0 μm or may be less than or equal to 2.0 μm, for example. The lower limit of the first difference is not particularly limited, but may be more than or equal to 0.1 μm or may be more than or equal to 0.05 μm, for example. As shown inFIG.5, in the direction from first main surface1toward second main surface2, the width of third region33at the central portion of third region33may be smaller than the width of third region33at the upper end portion of third region33and may be smaller than the width of third region33at the lower end portion of third region33. In the direction from third region33toward fourth region34, the maximum width (eighth width W8) of third region33is, for example, more than or equal to 0.5 μm and less than or equal to 5.0 μm. In the direction from third region33toward fourth region34, the minimum width (ninth width W9) of third region33is, for example, more than or equal to 0.3 μm and less than or equal to 3.0 μm. A value (second difference) obtained by subtracting the minimum width of third region33from the maximum width of third region33in the direction from third region33toward fourth region34may be, for example, more than or equal to 0.2 μm and less than or equal to 0.5 μm. The upper limit of the second difference is not particularly limited, but may be less than or equal to 1.0 μm or may be less than or equal to 2.0 μm, for example. The lower limit of the second difference is not particularly limited, but may be more than or equal to 0.1 μm or may be more than or equal to 0.05 μm, for example. Third Embodiment Next, a configuration of a silicon carbide semiconductor device200according to a third embodiment will be described. Silicon carbide semiconductor device200according to the third embodiment is different from silicon carbide semiconductor device200according to the first embodiment in terms of such a configuration that silicon carbide semiconductor device200according to the third embodiment is a gate trench type MOSFET, and the other configurations are the same as those of silicon carbide semiconductor device200according to the first embodiment. Hereinafter, the configuration different from that of silicon carbide semiconductor device200according to the first embodiment will be mainly described. FIG.6is a schematic cross sectional view showing the configuration of silicon carbide semiconductor device200according to the third embodiment. As shown inFIG.6, silicon carbide semiconductor device200according to the third embodiment is a gate trench type MOSFET. As shown inFIG.6, a first gate trench74is provided in first main surface1. First gate trench74has a third side surface71, a fourth side surface72, and a second bottom surface73. Fourth side surface72is opposite to third side surface71. Each of third side surface71and fourth side surface72is contiguous to first main surface1. Second bottom surface73is contiguous to each of third side surface71and fourth side surface72. Second bottom surface73of first gate trench74is located at a position shallower than first bottom surface7of first trench8. From another point of view, it can be said that a distance between second bottom surface73and first main surface1is shorter than a distance between first bottom surface7and first main surface1in the direction (third direction103) perpendicular to second main surface2. Each of first impurity region11, second impurity regions12, and third impurity regions13is in contact with gate insulating film51at third side surface71. Similarly, each of first impurity region11, second impurity regions12, and third impurity regions13is in contact with gate insulating film51at fourth side surface72. First impurity region11is in contact with gate insulating film51at second bottom surface73. Second regions32may face third side surface71and fourth side surface72. As shown inFIG.6, a second gate trench78is provided in first main surface1. Second gate trench78has a fifth side surface75, a sixth side surface76, and a third bottom surface77. Sixth side surface76is opposite to fifth side surface75. Each of fifth side surface75and sixth side surface76is contiguous to first main surface1. Third bottom surface77is contiguous to each of fifth side surface75and sixth side surface76. Third bottom surface77of second gate trench78is located at a position shallower than first bottom surface7of first trench8. From another point of view, it can be said that a distance between third bottom surface77and first main surface1is shorter than a distance between first bottom surface7and first main surface1in the direction (third direction103) perpendicular to second main surface2. Each of fourth impurity region21, fifth impurity regions22, and sixth impurity regions23is in contact with gate insulating film51at fifth side surface75. Similarly, each of fourth impurity region21, fifth impurity regions22, and sixth impurity regions23is in contact with gate insulating film51at sixth side surface76. Fourth impurity region21is in contact with gate insulating film51at third bottom surface77. Fourth regions34may face fifth side surface75and sixth side surface76. Next, the following describes a method of measuring the concentration of the p type impurity and the concentration of the n type impurity in the impurity regions. Each of the concentrations of the p type impurity and the n type impurity in the impurity regions can be measured using SIMS (Secondary Ion Mass Spectrometry). An exemplary measurement apparatus is a secondary ion mass spectrometer manufactured by Cameca. A measurement pitch is, for example, 0.01 μm. When the n type impurity to be detected is nitrogen, a primary ion beam is cesium (Cs). Primary ion energy is 14.5 keV. The polarity of the secondary ions is negative. When the p type impurity to be detected is aluminum or boron, the primary ion beam is oxygen (O2). Primary ion energy is 8 keV. The polarity of the secondary ions is positive. Next, the following describes a method of distinguishing the p type region and the n type region from each other. In the method of distinguishing the p type region and the n type region from each other, an SCM (Scanning Capacitance Microscope) is used. An exemplary measurement apparatus is NanoScope IV manufactured by Bruker AXS. With the SCM, a carrier concentration distribution in a semiconductor is visualized. Specifically, a surface of a sample is scanned using a metal-coated silicon probe. On this occasion, a high frequency voltage is applied to the sample. Majority carriers are excited to modulate the capacitance of the system. The frequency of the high frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V. Fourth Embodiment Next, a method of manufacturing a silicon carbide semiconductor device200according to a fourth embodiment will be described. First, a step (S10:FIG.7) of preparing a silicon carbide substrate is performed. For example, a silicon carbide single crystal ingot grown by a Modified-Lely method is sliced to obtain a substrate, and a surface of the substrate is mirror-polished, thereby preparing silicon carbide single crystal substrate50. Silicon carbide single crystal substrate50is, for example, hexagonal silicon carbide having a polytype of4H. The diameter of silicon carbide single crystal substrate50is, for example, 150 mm. Next, a step of forming silicon carbide epitaxial layer40is performed. For example, a carrier gas including hydrogen, a source material gas including silane and propane, and a dopant gas including nitrogen are supplied onto silicon carbide single crystal substrate50, and silicon carbide single crystal substrate50is heated to, for example, about 1550° C. under a pressure of 10 kPa. Thus, silicon carbide epitaxial layer40having the n type is formed on silicon carbide single crystal substrate50(seeFIG.8). In this way, silicon carbide substrate100is prepared which includes silicon carbide single crystal substrate50and silicon carbide epitaxial layer40provided on silicon carbide single crystal substrate50. Silicon carbide epitaxial layer40has impurity ions capable of imparting the n type (first conductivity type). First main surface1of silicon carbide epitaxial layer40corresponds to, for example, the {0001} plane or a plane angled off by less than or equal to about 8° with respect to the {0001} plane. Next, ion implantation is performed into silicon carbide epitaxial layer40. First, ions of a p type impurity are implanted into silicon carbide epitaxial layer40. Thus, first p type impurity regions92are formed. The p type impurity is, for example, aluminum. Next, ions of an n type impurity are implanted into each of first p type impurity regions92. Thus, a first n type impurity region93is formed. First n type impurity region93is formed in contact with first p type impurity region92. The n type impurity is, for example, phosphorus. Next, ions of a p type impurity are implanted into first n type impurity region93. Thus, a second p type impurity region94is formed. The p type impurity is, for example, aluminum. First p type impurity region92is to serve as second impurity region12and fifth impurity region22. First n type impurity region93is to serve as third impurity region13and sixth impurity region23. Second p type impurity region94is to serve as first contact region14and second contact region24. A step (S20:FIG.7) of forming a trench is performed. First, a mask layer54is formed on first main surface1. Mask layer54is composed of, for example, a material including a deposited oxide film. Mask layer54is provided with an opening formed in conformity with a region in which first trench8is to be formed. Next, silicon carbide epitaxial layer40is etched using mask layer54. In this way, first trench8is formed in silicon carbide epitaxial layer40(seeFIG.10). First trench8has first side surface5, second side surface6, and first bottom surface7. Second side surface6is opposite to first side surface5. First bottom surface7is contiguous to each of first side surface5and second side surface6. The depth (first depth H1) of first trench8is, for example, more than or equal to 3 μm and less than or equal to 30 μm. The width (fifth width W5) of first trench8is, for example, more than or equal to 1 μm and less than or equal to 3 μm. Next, etching conditions will be described. First trench8having first side surface5and second side surface6each in the form of a straight line is formed by using conditions to attain a sufficiently large amount of C deposit on each of the sidewalls of the trench as a protective film for the sidewall against the etching employing plasma in the trench (seeFIG.1). On the other hand, first trench8is formed to be expanded to both sides in the lateral direction by using conditions to attain an insufficient amount of C deposit on each of the sidewalls of the trench (seeFIG.5). Next, an oblique ion implantation step (S30:FIG.7) is performed. Specifically, impurity ions capable of imparting the p type (second conductivity type) such as aluminum are obliquely implanted into first side surface5of first trench8with mask layer54being disposed on first main surface1. Thus, second region32exposed at first side surface5is formed (seeFIG.11). Next, impurity ions capable of imparting the p type such as aluminum are obliquely implanted into second side surface6of first trench8. Thus, fourth region34exposed at second side surface6is formed (seeFIG.12). It should be noted that after the impurity ions capable of imparting the p type are implanted obliquely into second side surface6, the impurity ions capable of imparting the p type may be obliquely implanted into first side surface5. According to the method of manufacturing silicon carbide semiconductor device200according to the third embodiment, in each of the step of forming second region32and the step of forming fourth region34, oblique implantation is performed to avoid the impurity ions capable of imparting the second conductivity type from being implanted into bottom surface7. Specifically, when it is assumed that the width of first trench8is fifth width W5, the depth of first trench8is first depth H1, the thickness of mask layer54is first thickness H3, and the total of first thickness H3and first depth H1is second thickness H2, an angle (first angle θ1) at which the ion implantation can be performed to a boundary between first side surface5and first bottom surface7is an angle represented by an arc tangent of a value obtained by dividing second thickness H2by fifth width W5(seeFIG.11). Therefore, in order to perform ion implantation into first side surface5and avoid ion implantation into first bottom surface7, an angle formed between silicon carbide substrate100and the ion implantation direction is adjusted such that an angle with respect to a plane parallel to first bottom surface7is an angle (second angle θ2) smaller than first angle θ1. In this way, second regions32and fourth regions34are formed in silicon carbide epitaxial layer40. A portion of silicon carbide epitaxial layer40between the pair of second regions32serves as first region31. A portion of silicon carbide epitaxial layer40between the pair of fourth regions34serves as third region33. In a direction perpendicular to a boundary surface45between silicon carbide single crystal substrate50and silicon carbide epitaxial layer40, second bottom surface73of first trench8is located between silicon carbide single crystal substrate50and each of second regions32and fourth regions34. From another point of view, it can be said that second bottom surface73of first trench8is located on the second main surface2side with respect to each of second regions32and fourth regions34. Activation annealing may be performed after the oblique ion implantation step (S30:FIG.7). Silicon carbide epitaxial layer40includes first superjunction portion16having first region31and second regions32, first region31having the n type, second regions32having the p type. First region31is in contact with second regions32. First region31and second regions32form first superjunction portion16. Silicon carbide epitaxial layer40includes second superjunction portion26having third region33and fourth regions34, third region33having the n type, fourth regions34having the p type. Third region33is in contact with fourth regions34. Third region33and fourth regions34form second superjunction portion26. In first direction101, first superjunction portion16and second superjunction portion26are alternately disposed. It should be noted that as shown inFIGS.11and12, in the oblique ion implantation step (S30:FIG.7), part of the impurity ions capable of imparting the p type may be implanted into a portion of each of second impurity regions12, third impurity regions13, first contact regions14, fifth impurity regions22, sixth impurity regions23, and second contact regions24. Next, a step (S40:FIG.7) of filling the trench with an insulator is performed. For example, when first insulator80is a BCB resin or SOG, first insulator80is formed inside each first trench8by a spin coating method. In this way, first trench8is filled with first insulator80(seeFIG.13). Next, gate insulating films51are formed. Specifically, gate insulating films51are formed on first main surface1. Gate insulating film51is in contact with first impurity region11, second impurity regions12, and third impurity regions13at first main surface1. Similarly, gate insulating film51is in contact with fourth impurity region21, fifth impurity regions22, and sixth impurity regions23at first main surface1. The thickness of each gate insulating film51is, for example, more than or equal to 40 nm and less than or equal to 150 nm. Next, gate electrodes52are formed. Specifically, gate electrodes52are formed on respective gate insulating films51. Each of gate electrodes52is composed of, for example, a material including polysilicon including an impurity. Next, separation insulating films53are formed to cover respective gate electrodes52. Each of separation insulating films53is, for example, a silicon dioxide film (seeFIG.14). Next, first electrode60is formed. First electrode60is formed to extend over first trench8. Specifically, first electrode60is formed in contact with third impurity regions13, first contact regions14, first insulators80, second contact regions24, and sixth impurity regions23at first main surface1. First electrode60includes electrode layers61. Each of electrode layers61is formed by sputtering, for example. Electrode layer61is composed of a material including Ti, Al, and Si, for example. Next, silicon carbide substrate100having electrode layers61formed thereon is subjected to RTA (Rapid Thermal Anneal) for about 2 minutes at more than or equal to 900° C. and less than or equal to 1100° C., for example. Thus, at least a portion of each electrode layer61reacts with silicon included in silicon carbide substrate100, thus resulting in silicidation. Accordingly, electrode layer61is in ohmic contact with each of third impurity region13and sixth impurity region23. Preferably, electrode layer61is in ohmic contact with each of first contact region14and second contact region24. Next, source wiring62is formed. Source wiring62is formed to extend over first trench8. Specifically, source wiring62is formed in contact with electrode layers61to cover first insulators80. Source wiring62is preferably composed of a material including Al. Next, backside surface polishing is performed onto silicon carbide single crystal substrate50. Thus, the thickness of silicon carbide single crystal substrate50is reduced. Next, second electrode70is formed. Second electrode70is formed in contact with second main surface2of silicon carbide substrate100. Second electrode70is composed of a material including NiSi, for example. Second electrode70is preferably formed by the sputtering method, but may be formed by vapor deposition. After second electrode70is formed, second electrode70is heated by, for example, laser annealing. Thus, at least a portion of second electrode70is silicided. In this way, MOSFET200shown inFIG.1is manufactured. Fifth Embodiment Next, a method of manufacturing a silicon carbide semiconductor device200according to the fifth embodiment will be described. The method of manufacturing silicon carbide semiconductor device200according to the fifth embodiment is different from the method of manufacturing silicon carbide semiconductor device200according to the fourth embodiment mainly in terms of steps in which ion implantation is performed into first bottom surface7of first trench8, and the other steps are the same as those in the method of manufacturing silicon carbide semiconductor device200according to the fourth embodiment. Hereinafter, the steps different from those of the method of manufacturing silicon carbide semiconductor device200according to the fourth embodiment will be mainly described. As shown inFIG.15, the depth (second depth H4) of first trench8in the step (S20:FIG.7) of forming trench8of silicon carbide semiconductor device200according to the fifth embodiment is shallower than the depth (first depth H1) of first trench8in the step (S20:FIG.7) of forming trench8in the method of manufacturing silicon carbide semiconductor device200according to the fourth embodiment. Second depth H4is, for example, more than or equal to 2.5 μm and less than or equal to 29.5 μm. Next, the oblique ion implantation step (S30:FIG.7) is performed. Specifically, impurity ions capable of imparting the p type (second conductivity type) such as aluminum are obliquely implanted into first side surface5and first bottom surface7of first trench8with mask layer54being disposed on first main surface1. Thus, second region32exposed at first side surface5and first bottom surface7is formed (seeFIG.16). Next, impurity ions capable of imparting the p type such as aluminum are obliquely implanted into second side surface6and first bottom surface7of first trench8. Thus, fourth region34exposed at second side surface6and first bottom surface7is formed (seeFIG.17). Thus, according to the method of manufacturing silicon carbide semiconductor device200according to the fifth embodiment, the impurity ions capable of imparting the second conductivity type are implanted into bottom surface7in each of the step of forming second region32and the step of forming fourth region34. Next, additional etching is performed. Specifically, the impurity ions capable of imparting the p type and implanted in first bottom surface7of first trench8are removed by the additional etching. Thus, the depth of first trench8is changed from second depth H4to first depth H1(seeFIG.11). As a result, first bottom surface7of first trench8is exposed at third lower drift region91having the n type. As shown inFIG.11, in the direction perpendicular to boundary surface45between silicon carbide single crystal substrate50and silicon carbide epitaxial layer40, first bottom surface7of first trench8is located between silicon carbide single crystal substrate50and each of second regions32and fourth regions34. The subsequent steps are the same as those of the method of manufacturing silicon carbide semiconductor device200according to the fourth embodiment. In the above description, it has been illustrated that the first conductivity type is the n type and the second conductivity type is the p type; however, the first conductivity type may be the p type and the second conductivity type may be the n type. Further, in the above description, silicon carbide semiconductor device200according to the present disclosure has been described by illustrating the MOSFET; however, silicon carbide semiconductor device200according to the present disclosure is not limited to the MOSFET. Silicon carbide semiconductor device200according to the present disclosure may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like. Next, the following describes functions and effects of silicon carbide semiconductor devices200and the methods of manufacturing silicon carbide semiconductor devices200according to the above embodiments. As shown inFIG.17, when second region32is in contact with first bottom surface7of first trench8, the width of second region32located on the second main surface2side with respect to first bottom surface7is larger than the width of second region32located on the first main surface1side with respect to first bottom surface7. In this case, a charge balance between second region32and first region31on the second main surface2side with respect to first bottom surface7is different from a charge balance between second region32and first region31on the first main surface1side with respect to first bottom surface7. Similarly, a charge balance between fourth region34and third region33on the second main surface2side with respect to first bottom surface7is different from a charge balance between fourth region34and third region33on the first main surface1side with respect to first bottom surface7. Therefore, each of the charge balance between second region32and first region31and the charge balance between fourth region34and third region33is lost. In other words, it is difficult to excellently maintain a charge balance in each superjunction portion. On the other hand, according to each of silicon carbide semiconductor devices200and the methods of manufacturing silicon carbide semiconductor devices200according to the above embodiments, in the direction perpendicular to second main surface2, first bottom surface7of first trench8is located between the bottom surface (second end surface3) of second region32and second main surface2, and is located between the bottom surface (fourth end surface4) of fourth region34and second main surface2. In this case, second region32is separated from first bottom surface7of first trench8. Therefore, unlike the case where second region32is in contact with first bottom surface7of first trench8, the width of second region32is maintained to be substantially unchanged in the direction perpendicular to second main surface2. Similarly, fourth region34is separated from first bottom surface7of first trench8. Therefore, unlike the case where fourth region34is in contact with first bottom surface7of first trench8, the width of fourth region34is maintained to be substantially unchanged in the direction perpendicular to second main surface2. As a result, each of the charge balance between second region32and first region31and the charge balance between fourth region34and third region33can be suppressed from being lost. In other words, a charge balance in each superjunction portion can be maintained excellently. A deep superjunction portion is manufactured normally by repeating an epitaxial growth step and an ion implantation step. However, when this manufacturing method is used, the manufacturing process becomes significantly long, thus resulting in increased cost. Further, by repeating the epitaxial growth step and the ion implantation step, impurity concentrations in the respective epitaxial layers may greatly differ. On the other hand, according to the method of manufacturing silicon carbide semiconductor device200according to the present embodiment, trench8having first side surface5and second side surface6opposite to first side surface5is formed in silicon carbide epitaxial layer40. Second region32is formed by obliquely implanting, into to first side surface5, the impurity ions capable of imparting the second conductivity type. Fourth region34is formed by obliquely implanting, into second side surface6, the impurity ions capable of imparting the second conductivity type. Thus, a deep superjunction portion can be manufactured by such a simple method. Therefore, the manufacturing process can be significantly shortened. When the epitaxial growth process is performed once, variation in impurity concentration in the direction perpendicular to second main surface2can be reduced as compared with the case where the epitaxial growth step is repeated twice or more. Therefore, a charge balance in the superjunction portion can be excellently maintained. The embodiments disclosed herein are illustrative and non-restrictive in any respect. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. REFERENCE SIGNS LIST 1: first main surface;2: second main surface;3: second end surface;4: fourth end surface;5: first side surface;6: second side surface;7: first bottom surface (bottom surface);8: first trench (trench);9: second trench;10: first mesa region;11: first impurity region;12: second impurity region;13: third impurity region;14: first contact region;15: first lower drift region;16: first superjunction portion;17: first end surface;20: second mesa region;21: fourth impurity region;22: fifth impurity region;23: sixth impurity region;24: second contact region;25: second lower drift region;26: second superjunction portion;27: third end surface;31: first region;32: second region;33: third region;34: fourth region;40: silicon carbide epitaxial layer;41: fifth region;42: sixth region;43: seventh region;44: eighth region;45: boundary surface;50: silicon carbide single crystal substrate;51: gate insulating film;52: gate electrode;53: separation insulating film;54: mask layer;60: first electrode;61: electrode layer;62: source wiring;70: second electrode;71: third side surface;72: fourth side surface;73: second bottom surface;74: first gate trench;75: fifth side surface;76: sixth side surface;77: third bottom surface;78: second gate trench;80: insulator (first insulator);90: second insulator;91: third lower drift region;92: first p type impurity region;93: first n type impurity region;94: second p type impurity region;100: silicon carbide substrate;101: first direction;102: second direction;103: third direction;200: silicon carbide semiconductor device (MOSFET); H1: first depth; H2: second thickness; H3: first thickness; H4: second depth; W1: first width; W2: second width; W3: third width; W4: fourth width; W5: fifth width; W6: sixth width; W7: seventh width; W8: eighth width; W9: ninth width. | 68,467 |
11942518 | DETAILED DESCRIPTION III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and substrates (e.g., silicon-containing substrates). Certain embodiments are related to gallium nitride materials, and material structures comprising gallium nitride material regions and silicon-containing substrates. It has been discovered, in accordance with certain embodiments, that in certain cases, operation of semiconductor devices including III-nitride material regions over substrates generates heat, which decreases the electrical resistance of the substrate. The decrease in electrical resistance can lead to an increase in current transported across the substrate, which can lead to additional resistive heating. In this way, a positive feedback effect (in which further heating leads to further reductions in electrical conductivity and additional further heating) can be present that can degrade product performance characteristics, such as output power and efficiency of devices formed from such semiconductor structures. Certain of the embodiments described herein are related to structures and methods of operation that reduce this positive feedback effect, which in certain cases, enhances device performance. Certain embodiments are related to semiconductor structures comprising substrates having relatively high electronic conductivities. For example, in accordance with certain embodiments, the structures include substrates comprising silicon having a relatively high electronic conductivity. In certain embodiments, electronically conductive substrates can reduce issues arising from increased thermal resistance within the semiconductor structure. For example, without wishing to be bound by any particular theory, it is believed that the use of substrates having regions with relatively high electronic conductivity reduces the amount of heat that is generated via resistive heating during operation of the device. It is further believed that the reduction in the amount of heat generated by the device leads to enhanced device performance (e.g., an increase in power output and/or device efficiency). According to some embodiments, the semiconductor structures comprise relatively thick III-nitride layers. In certain embodiments, use of a relatively thick III-nitride layer (e.g., a relatively thick epitaxial GaN layer) reduces capacitive coupling between electrically conductive components of the semiconductor structure (e.g., conductive metal structures, such as electrodes, of transistors) and the substrate (e.g., a silicon-containing substrate which can be electronically conductive). The reduction in capacitive coupling can reduce RF current displacement in the semiconductor structures, which can ultimately result in higher operating temperatures of the semiconductor structures, enhanced operating efficiency, and/or other performance improvements. According to certain embodiments, the interfacial area between the III-nitride material surface and electronically conductive components in a semiconductor device is relatively small. This can be achieved, for example, by using small ohmic or Schottky contacts. In certain embodiments, reducing and/or minimizing the contact area between electrode structures (e.g., metal structures) and the III-nitride material surface results in the reduction of capacitive coupling between the electrode structures and the substrate (e.g., a silicon-containing substrate, which can be electronically conductive). Not wishing to be bound by any particular theory, the ohmic or Schottky contacts can, in certain cases, capacitively couple to the substrate, which can result in the loss of energy during operation of the semiconductor device. It is believed that when large ohmic or Schottky contacts are used, capacitive coupling increases, which can result in increased displacement current, resulting in dissipated power in the substrate. Conversely, as the contact area is decreased, capacitive coupling to the substrate and displacement current can be decreased, leading to enhanced performance. According to some embodiments, a dielectric region is located over the substrate and over the III-nitride material region. In certain embodiments, the dielectric region provides a surface on which large contact pads are formed. According to some embodiments when large contact pads are present on the thick dielectric region, the thick dielectric region separates the large contact pads from the III-nitride material region and underlying substrate, resulting in reduced capacitive coupling to the substrate (e.g., a silicon-containing substrate, which can be electronically conductive). In certain embodiments, a large contact pad present on a thick dielectric region reduces unwanted capacitance associated with the contact pad. In certain embodiments, the semiconductor structures described herein comprise a backside ground that couples an electronically conductive material (e.g., a contact pad and/or an electrode) of a device to the electronically conductive substrate through the thickness of the III-nitride material region. According to certain embodiments, the electronically conductive material that is coupled to the electronically conductive substrate is coupled to the source electrode and/or drain electrode. In some embodiments, the electronically conductive material reduces the capacitance to the silicon-containing substrate (e.g., to ground) by providing an alternate source of grounding. Some embodiments described herein are related to semiconductor structures and devices with improved performance. For example, in accordance with certain embodiments, the semiconductor structures exhibit increased efficiency at elevated temperatures. Furthermore, in certain embodiments, the semiconductor structures have small drops in efficiency upon increasing operating temperatures of the semiconductor structures. Certain embodiments are related to inventive semiconductor structures. Certain inventive semiconductor structures described herein can comprise a substrate and a III-nitride material region located over the substrate (e.g., at least one region comprising III-nitride material formed over a surface region of the substrate). In some cases, a substrate can have one or more semiconductor layers and may further include one or more thin-film dielectric layers. A substrate may be made of bulk silicon or may comprise silicon in various embodiments. In some implementations, the III-nitride material region can include one or more thin-film dielectric layers. FIG.1Ais a cross-sectional schematic illustration of a semiconductor structure100A, according to certain embodiments. Semiconductor structure100A comprises substrate110and a III-nitride material region120located over surface135of substrate110(and, thus, over surface region130of substrate110). According to certain embodiments, surface135of substrate110can be a silicon surface. For example, surface135may correspond to a surface of a silicon wafer, in some embodiments. In certain embodiments, the top surface (e.g., surface135in the figures) may correspond to a silicon surface of a composite substrate (e.g., comprising a silicon layer and one or more additional underlying layers). For example, in some embodiments, surface135may correspond to a surface of a silicon portion of a silicon-on-insulator substrate, surface135may correspond to a surface of a silicon-on-sapphire substrate. According to certain embodiments and as described above, the semiconductor structures described herein comprise a substrate. In certain embodiments, the substrate comprise silicon (i.e., a substrate containing the element silicon in any form). Some embodiments are related to substrates at least a portion of which is made of silicon. Certain embodiments are related to substrates at least a portion of which (or all of which) is made of bulk silicon. As used herein, bulk silicon refers to doped or undoped elemental Si in any form. Substrates that contain bulk silicon can include, for example, at least a layer of doped or undoped silicon, as opposed to silicon oxides, silicon carbides, silicon nitrides, etc. Examples of substrates comprising silicon that can be used in various embodiments include, but are not limited to, bulk silicon wafers, silicon-on-insulator substrates, and substrates made of or comprising alloys of silicon (e.g., silicon germanium and silicon carbide substrates). In some embodiments, the substrate comprises a silicon substrate. As used herein, a silicon substrate refers to any substrate that includes a silicon surface. Examples of suitable silicon substrates include substrates that are composed entirely of silicon (e.g., bulk silicon wafers), silicon-on-insulator (SOI) substrates, and silicon-on-sapphire (SOS) substrates. Suitable silicon substrates also include composite substrates that have a silicon wafer bonded to another material such as diamond or other crystallographic forms of carbon, aluminum nitride (AlN), silicon carbide (SiC), or other crystalline or polycrystalline materials. Silicon substrates having different crystallographic orientations may be used, though single crystal silicon substrates may be preferred in certain, but not necessarily all, embodiments. In some embodiments, silicon (111) substrates are used. In certain embodiments, silicon (100) or (110) substrates are used. As used herein, a silicon carbide substrate refers to any substrate that includes a silicon carbide surface. Examples of suitable silicon carbide substrates include substrates that are composed entirely of silicon carbide (e.g., bulk silicon carbide wafers), silicon carbide composite wafers (e.g., wafers comprising a silicon carbide layer and a second layer of a material that is not silicon carbide), and the like. In certain embodiments, at least a portion of the substrates described herein are electronically conductive. In some embodiments, the substrate comprises at least one layer that is electronically conductive. For example, in certain embodiments in which silicon substrates are used, the silicon substrate (or at least the silicon portion of the substrate for substrates that include a silicon portion formed on another material) is electronically conductive. As used herein, a material (e.g., a region, a layer, a substrate, etc.) is considered to be electronically conductive when it has an electronic resistivity of less than 0.10 Ω·cm when at 25° C. In certain embodiments, the region of the substrate underneath an active region of the semiconductor structure has a resistivity of about 0.01 Ω·cm to about 0.10 Ω·cm. For example, electronically conductive materials (e.g., regions, layers, substrates) have electronic resistivities of less than 0.10 Ω·cm in some embodiments, less than 0.05 Ω·cm in some embodiments, less than 0.03 Ω·cm in some embodiments, less than 0.01 Ω·cm in some embodiments, less than 0.001 Ω·cm in some embodiments, less than 0.0001 Ω·cm in some embodiments, less than 0.00001 Ω·cm in some embodiments, or yet less than 0.000001 Ω·cm in some embodiments, when the electronically conductive materials are at 25° C. According to certain embodiments, the electronic resistivity of the material (e.g., a layer, a substrate) when at 25° C. is greater than 0 Ω·cm in some embodiments, greater than 1×10−10Ω·cm in some embodiments, greater than 1×10−9Ω·cm in some embodiments, greater than 1×10−8Ω·cm in some embodiments, greater than 1×10−6Ω·cm in some embodiments, greater than 1×10−4Ω·cm in some embodiments, greater than 1×10−2Ω·cm in some embodiments, and yet greater than 0.01 Ω·cm in some embodiments. Combinations of these ranges are also possible, (e.g., greater than 1×10−10Ω·cm and less than 0.10 Ω·cm). The electronic resistivity of a material (e.g., a region, a layer, a substrate, etc.) is measured laterally across the material (i.e., in a direction perpendicular to the thickness of the substrate). Those of ordinary skill in the art are capable of determining the electronic resistivity of a material. For example, the electronic resistivity of a material (e.g., a region, a layer, a substrate, etc.) can be determined by first making a resistance measurement across a known geometry (e.g., by placing two electrodes across the material). The resistivity of the material can then be determined as follows: ρ=RAl (1) where R is the measured electrical resistance, A is the cross-sectional area over which the resistance measurement was taken, and l is the length of the area over which the resistance measurement was taken. The conductivity of the region (also sometimes referred to as the “conductance”) is the inverse of the resistivity of the region. In some embodiments, the substrate comprises at least one portion having a length of at least 1 micrometer, at least 10 micrometers, at least 100 micrometers, at least 1 mm, or at least 10 mm, wherein that portion also has an electronic resistivity of less than 0.10 Ω·cm (or within any of the ranges outlined above) when at 25° C. Electronically conductive substrates (e.g., comprising silicon, such as silicon substrates or other substrates comprising silicon) may be particularly useful in some (but not necessarily all) structures that are used to form devices that operate at high frequencies (e.g., RF devices). According to certain embodiments, the high conductivity can reduce so-called substrate losses which otherwise may arise and sacrifice performance. These substrate losses may render substrates with higher resistivities unsuitable in high frequency devices. In certain embodiments, a substrate having one or more integrated circuit components (such as devices and/or discrete components) may have various device layers, homojunctions, heterojunctions, or circuit layers embedded in the substrate, or formed on the front-side and/or back-side of the substrate. Such substrates may be semi-spec standard thickness, or thicker, or in some implementations thinner than semi-spec standards. In some cases, for example, an Si substrate may have a diameter of less than one hundred millimeters (100 mm), while in other implementations, the substrate may have a diameter in a range from approximately 100 mm to approximately 150 mm. In certain embodiments, the substrate diameter may be in a range from approximately 150 mm to approximately 200 mm, or larger. In still other embodiments, the substrate may include a textured surface or may have a non-planar surface. Embodiments include substrates of smaller size than a full wafer. The term “substrate” can also refer to a substrate having properties as described above and having a size of a chip, die, or discrete device. In certain implementations, a substrate of a chip, die, or discrete device is singulated from a larger wafer. In some embodiments, the substrate may also have any of a variety of suitable thicknesses. According to some embodiments, the substrate has a thickness of less than 150 micrometers. According to certain embodiments, the substrate has a thickness of less than 100 micrometers, less than 50 micrometers, or less. According to certain embodiments, the thickness of the substrate may be selected based on the final device and heteroepitaxial specifications (e.g., wafer warp and bow), for example, as needed for successful high yielding semiconductor fabrication. In some embodiments, the thickness of the substrate may be semi-spec thicknesses typical of the wafer diameter used in high volume wafer silicon manufacturing. As used herein, the term “III-nitride material” refers to any Group III element-nitride compound. Non-limiting examples of III-nitride materials include boron nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), and thallium nitride (TIN), as well as any alloys including Group III elements and Group V elements (e.g., AlxGa(1−x)N, AlxInyGa(1−x−y)N, InyGa(1−y)N, GaAsaPbN(1−a−b), AlxInyGa(1−x−y)AsaPbN(1−a−b), and the like). Typically, when present, arsenic and/or phosphorus are at low concentrations (e.g., less than 5 weight percent). III-nitride materials may be doped n-type or p-type, or may be intrinsic. III-nitride materials may have any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-nitride material may also include either the Wurtzite, Zincblende, or mixed polytypes, and may include monocrystalline, polycrystalline, or amorphous structures. In some embodiments, the III-nitride material region comprises a gallium nitride material. As used herein, the phrase “gallium nitride material” refers to gallium nitride (GaN) and any of its alloys, such as aluminum gallium nitride (AlxGa(1−x)N), indium gallium nitride (InyGa(1−y)N), aluminum indium gallium nitride (AlxInyGa(1−x−y)N), gallium arsenide phosphoride nitride (GaAsaPbN(1−a−b)), aluminum indium gallium arsenide phosphoride nitride (AlxInyGa(1−x−y)AsaPbN(1−a−b)), amongst others. In certain embodiments, the III-nitride material region comprises GaN. According to some embodiments, the III-nitride material region is an epitaxial III-nitride material region. In certain embodiments, the III-nitride material region comprises a heterojunction, a two-dimensional electron gas (2DEG) region, and/or two-dimensional hole gas (2DHG). In some embodiments, the III-Nitride material region comprises doped homojunctions and/or doped heterojunctions. Typically, when present, arsenic and/or phosphorus are at low concentrations (i.e., less than 5 weight percent). In certain embodiments, the gallium nitride material has a high concentration of gallium and includes little or no amounts of aluminum and/or indium. In high gallium concentration embodiments, the sum of (x+y) may be less than 0.4, less than 0.2, less than 0.1, or even less. In some cases, it is preferable for the gallium nitride material layer to have a composition of GaN (i.e., x+y=0). Gallium nitride materials may be doped n-type or p-type, or may be intrinsic. According to some embodiments, the thickness of the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) and the number of different layers within the III-nitride material device region are dictated, at least in part, on the application in which the semiconductor structure is used. In some embodiments, the III-nitride material region is thick. According to certain embodiments, at a minimum, the total thickness of the III-nitride material region (or any individual layer within the III-nitride material device region) is sufficient to permit formation of the desired semiconductor structure or device. Certain embodiments are related to a III-nitride material region having a thickness of at least 2.0 micrometers located over the substrate. In some embodiments, the thickness of the III-nitride material device region is greater than 2.0 micrometers, or greater than 3.0 micrometers, or greater than 4.0 micrometers, greater than 5.0 micrometers, greater than 6.0 micrometers, greater than 7.0 micrometers, greater than 8.0 micrometers, or greater than 9.0 micrometers. According to certain embodiments, the thickness the III-nitride material device region is less than 10.0 micrometers, less than 9.0 micrometers, less than 8.0 micrometers, less than 7.0 micrometers, less than 6.0 micrometers, less than 5.0 micrometers, less than 4.0 micrometers, less than 3.0 micrometers, or less than 2.0 micrometers. Combinations of these ranges are also possible (e.g., greater than 2.0 micrometers and less than 5.0 micrometers, greater than 3.0 micrometers and less than 4.0 micrometers). Some embodiments are related to a III-nitride material region having a thickness of 4.8 micrometers. In some embodiments, the III-nitride material region is located over the substrate. When a structure (e.g., layer and/or device) is referred to as being “on,” “over,” or “overlying” another structure (e.g., layer or substrate), it is over at least a portion of that structure. In some cases, a structure that is referred to as being “on,” “over,” or “overlying” another structure is over the entirety of that structure. When a structure (e.g., layer and/or device) is referred to as being “on,” “over,” or “overlying” another structure (e.g., layer or substrate), it can be directly on the structure, or an intervening structure (e.g., a layer, air gap) also may be present. A structure that is “directly on” or “in direct contact with” another structure means that no intervening structure is present. It should also be understood that when a structure is referred to as being “on” or “over” another structure, it may cover the entire structure, or a portion of the structure. In addition, when a structure is referred to as being “on” or “over” another structure, it may be embedded within that structure. According to some embodiments, the III-nitride material region comprises an optional III-nitride nucleation layer or intermediate layer. For example, referring to the exemplary embodiment ofFIG.1B, III-nitride material region120comprises III-nitride material transition layer170. It should be understood that transition layer170is optional, and in other embodiments, III-nitride material region120does not include transition layer170. InFIG.1B, transition layer170is formed directly on nucleation layer155. In other embodiments, one or more materials may be positioned between transition layer170and nucleation layer155. The nucleation layer can, according to certain embodiments, prepare a surface of the substrate for growth of III-nitride material over the substrate. In certain cases, III-nitride material (e.g., gallium nitride materials and/or other III-nitride materials) can be difficult to grow heteroepitaxially directly on the substrate (and/or another region that is over a surface of the substrate), for example, because the III-nitride material one wishes to grow may have a lattice structure and/or a lattice constant which is significantly different than the substrate or other underlying region. According to certain embodiments, the nucleation layer forms an appropriate template to transition from the lattice of the substrate (or other underlying layer) to a template more suitable for III-nitride growth. In certain embodiments, the nucleation layer can accommodate the difference in the lattice constants of an overlying layer in the III-nitride material region (e.g., the III-nitride material region portion in direct contact with the nucleation layer) and the region underneath the nucleation layer (e.g., the substrate and/or another underlying region, which in some cases, may be in direct contact with the nucleation layer). In some embodiments, the nucleation layer can accommodate the difference in the thermal expansion coefficients of an overlying layer in the III-nitride material region (e.g., the III-nitride material region portion in direct contact with the nucleation layer) and the region underneath the nucleation layer (e.g., the substrate and/or another underlying region, which in some cases, may be in direct contact with the nucleation layer). According to certain embodiments, the nucleation layer can accommodate both the difference in lattice constants and the difference in thermal expansion coefficients of an overlying layer in the III-nitride material region and the region underneath the nucleation layer. In some embodiments, the nucleation layer may also act as a reaction barrier between the III-nitride material region and the silicon substrate. For example, in organometallic vapor phase epitaxy (OMVPE) growth environments (e.g., metal-organic chemical vapor deposition (MOVCD)), the introduction of gallium species in direct proximity to the silicon surface can result in the formation and accumulation of free gallium atoms and deleterious formation of SiN preventing proper initiation of GaN heteroepitaxy. This can be prevented by first forming an AlN heteroepitaxy nucleation layer which acts to seal the silicon surface and reacting with subsequent growth of GaN or gallium containing III-Nitride material layers. According to certain embodiments, the nucleation layer comprises an aluminum nitride material. As used herein, the phrase “aluminum nitride material” refers to aluminum nitride (AlN) and any of its alloys, such as aluminum gallium nitride (Al(1−x)Ga(x)N), aluminum indium nitride (Al(1−x)In(x)N), aluminum indium gallium nitride (Al(1−x−y)In(x)Ga(y)N), aluminum indium gallium arsenide phosphoride nitride (Al(1−x−y)InxGayAsaPbN(1−a−b)), amongst others. In certain embodiments, the aluminum nitride material has a high concentration of aluminum and includes little or no amounts of gallium and/or indium. In high aluminum concentration embodiments, the sum of (x+y) may be less than 0.4, less than 0.2, less than 0.1, or even less. In some cases, it is preferable for the aluminum nitride material to have a composition of MN (i.e., x+y=0). Aluminum nitride materials may be doped n-type or p-type, or may be intrinsic. In certain embodiments, the use of an aluminum nitride material as the nucleation layer may be preferred in certain cases in which the III-nitride material is formed on the substrate without the use of a diffusion barrier region between the III-nitride material and the substrate. According to certain embodiments, the nucleation layer may comprise one or more layers. When multiple nucleation layers are present, the nucleation layers may be made of the same material or different materials. In addition, in certain embodiments in which multiple nucleation layers are present, the nucleation layers may be formed using different semiconductor growth conditions. For example, in some embodiments, the nucleation layers may comprise two or more aluminum nitride material layers formed at different growth temperatures (e.g., one at a relatively low temperature and another at a relatively high temperature). In some embodiments, other growth conditions (e.g., pressure, reactant flow rates, etc.) may be varied from the growth of one nucleation layer to another. Suitable materials from which the III-nitride material nucleation layer may be formed include, but are not limited to, aluminum nitride materials (e.g., aluminum nitride, aluminum nitride alloys). The III-nitride material nucleation layer typically has a constant composition. In some embodiments, the nucleation layer comprises a first aluminum nitride-based layer and a second aluminum nitride-based layer. The aluminum nitride-based nucleation layer can include aluminum nitride as well as other optional elements, such as silicon and/or oxygen. For example, in some embodiments, the aluminum nitride-based nucleation layer can be a thin (e.g., from about 10 Angstroms to about 20 Angstroms, or thinner) amorphous or non-crystalline (unordered) material comprising aluminum and nitrogen, and optionally silicon and/or oxygen. In some embodiments, the amorphous aluminum nitride-based layer may also act as a diffusion barrier region as discussed further below. In other embodiments, one or more separate diffusion barrier layers can be used in combination with the aluminum-nitride based layer. In certain embodiments, a III-nitride material nucleation layer has a single crystal structure. It may be advantageous, in some but not necessarily all embodiments, for a III-nitride material nucleation layer to have a single crystal structure because such structures can facilitate formation of one or more single crystal layers (e.g., gallium nitride material layers) above the III-nitride material nucleation layer. It should also be understood that a III-nitride material nucleation layer may not have a single crystal structure and may be amorphous or polycrystalline, though certain of the advantages associated with the single crystal nucleation layers may not be achieved in some such embodiments. The III-nitride material nucleation layer may have a number of suitable thicknesses. For example, the III-nitride material nucleation layer may have a thickness of between about 10 nanometers and about 5 micrometers, though other thicknesses are also possible. In certain embodiments in which more than one nucleation layer is employed, the combined thickness of the nucleation layers may be between about 10 nanometers and about 5 micrometers, though other thicknesses are also possible. According to certain embodiments, the III-nitride material region comprises an optional III-nitride transition layer. For example, referring to the exemplary embodiment ofFIG.1B, III-nitride material region120comprises III-nitride material transition layer170. It should be understood that transition layer170is optional, and in other embodiments, III-nitride material region120does not include transition layer170. InFIG.1B, transition layer170is formed directly on nucleation layer155. In other embodiments, one or more materials may be positioned between transition layer170and nucleation layer155. In some embodiments, the III-nitride transition layer is compositionally graded. In some embodiments, the III-nitride material transition layer comprises a compositionally graded III-nitride material. Examples of such materials are described, for example, in U.S. Pat. No. 6,649,287, issued Nov. 18, 2003, and entitled “Gallium Nitride Materials and Methods,” which is incorporated herein by reference in its entirety for all purposes. Compositionally-graded transition layers have a composition that is varied across at least a portion of the layer (e.g., across at least a portion of the thickness of the layer). For example, according to certain embodiments in which the transition layer comprises a III-nitride material layer, the concentration of at least one of the elements (e.g., Ga, Al, In) of the III-nitride material is varied across at least a portion of the thickness of the transition layer. Compositionally-graded transition layers are particularly effective, according to certain embodiments, in reducing crack formation in gallium nitride material regions formed on the transition layer, for example, by lowering thermal stresses that result from differences in thermal expansion rates between the gallium nitride material and the substrate (e.g., silicon). Compositionally-graded transition layers may also contribute to reducing generation of screw dislocations in the III-nitride material layer(s)/region(s) (e.g., gallium nitride material layer(s)). In some cases, the compositionally-graded transition layers may also contribute to reducing mixed and edge dislocation densities. The composition of a compositionally-graded III-nitride material layer can be graded, for example, discontinuously (e.g., step-wise) or continuously. The composition of the compositionally-graded layer can be graded across the entire thickness of the layer, or across only a portion of the thickness of the layer. According to one set of embodiments, the transition layer is compositionally-graded and formed of an alloy of gallium nitride such as AlxInyGa(1-31 x−y)N, AlxGa(1−x)N, and InyGa(1−y)N. In some such embodiments, the concentration of at least one of the elements (e.g., Ga, Al, In) of the alloy is varied across at least a portion of the thickness of the transition layer. In certain embodiments in which the transition layer has an AlxInyGa(1−y)N composition, x and/or y may be varied. In certain embodiments in which the transition layer has a AlxGa(1−x)N composition, x may be varied. In certain embodiments in which the transition layer has a InyGa(1−y)N composition, y may be varied. In certain embodiments, it is desirable for the transition layer to have a low gallium concentration at a back surface which is graded to a high gallium concentration at a front surface. It has been found that such transition layers can be particularly effective in relieving internal stresses within overlying gallium nitride material layers. For example, the transition layer may have a composition of AlxGa(1−x)N, where x is decreased from the back surface to the front surface of the transition layer (e.g., x is decreased from a value of 1 at the back surface of the transition layer to a value of 0 at the front surface of the transition layer). In some embodiments, the semiconductor structure includes an aluminum nitride nucleation layer and a compositionally-graded transition layer. In some embodiments, the compositionally-graded transition layer has a composition of AlxGa(1−x)N, where x is continuously graded from a value of 1 at the back surface of the transition layer to a value of 0 at the front surface of the transition layer. One discontinuous grade may include steps of AlN, Al0.6Ga0.4N, and Al0.3Ga0.7N (step grades) proceeding in a direction toward the gallium nitride material layer. In another example of a discontinuously graded III-nitride material transition layer, there may be periodic layers and/or intervening layers inserted between one or more of the step layers making up the step grade. The periodic layers and/or intervening layers, for example, may be layers of aluminum nitride material (e.g., AlN or AlGaN) formed at the same or different (e.g., lower) temperatures than are used to form the step grade layers. Another example of periodic layers or intervening layers include silicon nitride and/or aluminum silicon nitride layers, which can act as masking layers to pin the vertical threading and screw dislocations which may extend from one layer to the next. It should be understood that, in other cases, the transition layer may have a constant composition and may not be compositionally-graded. In some cases (e.g., in certain cases in which the substrate is not a silicon substrate), the transition layer may have a constant composition. Suitable compositions include, but are not limited to, aluminum nitride-based materials (e.g., aluminum nitride, aluminum nitride alloys) and gallium nitride materials. In these constant composition embodiments, the transition layer may be similar to the nucleation layer described above. According to certain embodiments, the transition layer may be made of, at least in part, one or more superlattices. In some cases, a superlattice of a transition layer can be formed as a strained layer superlattices (SLS). In some cases, a superlattic of a transition layer can be formed as a multiple quantum wells (MQW). In some cases, a superlattic of a transition layer can be formed as a compositionally-graded superlattice or compositionally graded MQW. Embodiments also include transition layers that have any combination of the foregoing superlattice types. Any of the foregoing superlattice types may include carbon doping. In some cases, a superlattice or combination of superlattices of the foregoing types can be present outside of a transition layer. In yet additional embodiments, a superlattice or combination of superlattices of the foregoing types can be present only and there may be no other transition layer. In certain embodiments, the III-nitride material region comprises an optional III-nitride buffer layer. For example, referring to the exemplary embodiment ofFIG.1B, III-nitride material region120comprises III-nitride material buffer layer180. It should be understood that buffer layer180is optional, and in other embodiments, III-nitride material region120does not include buffer layer180. The buffer layer can, according to certain embodiments, provide a surface for the growth of epitaxial III-nitride material above the buffer layer. According to certain embodiments, the buffer layer comprises an aluminum gallium nitride material. In some such embodiments, the buffer layer comprises AlxGa(1−x)N. In certain embodiments in which the buffer layer comprises AlxGa(1−x)N, x may be less than about 0.2, less than about 0.1, less than about 0.05, or less than about 0.01. In some embodiments, the buffer layer comprises GaN. The buffer layer may be formed over the transition layer, for example, using any of a number of known growth techniques. For example, according to certain embodiments, the buffer layer may be formed over the transition layer using molecular-beam epitaxy (MBE) or metalorganic vapor phase epitaxy (MOVPE). In certain embodiments (including certain embodiments in which the desired epitaxial material structure will be used in the fabrication of devices such as field effect transistors (FETs), Schottky diodes, and/or High Electron Mobility Transistors (HEMTs)), it may be desirable to form a channel layer above the buffer layer. Typically, in some such embodiments, it would then be desirable for the buffer layer bandgap to be greater than or equal to the bandgap of the channel layer. For example, in certain transistor designs using back barriers, the channel layer may comprise gallium nitride while the buffer layer may comprise aluminum gallium nitride. In some such cases, the buffer layer may comprise a substantially uniform composition of AlGaN with a bandgap larger than the channel layer but smaller than the underlying transition layer alloy composition. In other examples, the buffer layer may itself be a compositionally graded layer which has a larger aluminum composition formed near the transition layer, and a smaller aluminum concentration formed near the channel layer. In some embodiments, the composition of the channel layer and the buffer layer may be substantially the same. Although the intrinsic material properties of GaN materials can allow for the formation of high performance devices in theory, conventional growth environments of GaN nitride materials typically include impurity sources. For example, carbon impurities resulting from metalorganic precursors may be, in some cases, introduced into the GaN materials grown using MOCVD, also known more generically as organometallic vapor phase epitaxy (OMVPE). The presence of these impurities in the GaN growth environment can cause unintentional doping in or near critical device layers, for example the channel layer. In certain embodiments (e.g., including certain embodiments in which enhancing the standoff voltage is desired), it may be desirable to incorporate impurities into the buffer layer. For example, the addition of impurities such as carbon (C) and iron (Fe) into the buffer layers of gallium nitride based transistors may increase the vertical and lateral breakdown voltage capability and/or reduce the leakage levels of the device. However, addition of certain impurities within close proximity to the channel layer may result in dispersive device performance (e.g., exhibited by high levels of drain and gate lag). As such, in certain embodiments, it may be beneficial to form the buffer layer such that there is a substantially low impurity concentration throughout the thickness of the buffer layer. In certain other embodiments, there may be a graded (continuously or discontinuously) impurity level within the buffer layer, with a higher impurity concentration near the transition layer, and a lower impurity concentration formed nearer to the channel layer. In certain other embodiments, the transition layer(s) may also include one or more impurities. In some such embodiments, the concentration of impurities in the transition layer(s) may be higher than the concentration(s) of the impurities within the buffer layer and/or within the channel layer. In certain embodiments, the III-nitride material region comprises an optional III-nitride device region. For example, referring to the exemplary embodiment ofFIG.1B, III-nitride material region120comprises III-nitride material device region190. It should be understood that device region190is optional, and in other embodiments, III-nitride material region120does not include device region190. In some embodiments, the III-nitride material region includes at least one gallium nitride material layer. For example, in certain embodiments, the III-nitride material device region190comprises at least one gallium nitride material layer. Referring toFIG.1B, for example, in some embodiments, III-nitride material device region190can include at least one gallium nitride material layer. As described further below, oftentimes, the structure includes more than one gallium nitride material layer which form, in part, the active region of a device. As noted above, in some embodiments, the device region190comprises one or more III-nitride material layers.FIG.1Cis a cross-sectional schematic illustration of a III-nitride material device region190, according to certain embodiments. In some embodiments, the III-nitride material device region comprises an optional back barrier layer. According to certain embodiments, when present, the optional back barrier layer is the layer of the III-nitride material region that is the closest to the underlying substrate. For example, inFIG.1C, exemplary III-nitride material device region190comprises optional back barrier layer190A, which as shown inFIG.1C, is the closest of the layers within III-nitride material region to substrate110. When used, the optional back barrier can create a double heterostructure (e.g., due to the bandgap off sets with the buffer layer, such as a GaN buffer layer). This may be desirable, in certain cases, in devices which operate under higher drain bias as they can prevent injection of electrons from the channel layer into the buffer layer, thereby reducing drain leakage and punch through of the device. Additionally, in some cases, the buffer layer may contain higher levels of impurities, intentionally (e.g., iron and carbon used to increase breakdown voltage) or unintentionally (e.g., carbon impurities incorporated into the buffer layer as byproducts from the crystal growth methodologies employed). These impurities and/or other defects may, in certain cases, act as trapping centers and cause deleterious performance results (e.g., memory effects) for the device if electrons from the channel layer penetrate into the underlying buffer layer. Back barrier layers can, in certain cases, help confine the electrons in the channel layer and prevent spill over into the more defective buffer layer and/or other underlying III-nitride layers. In certain embodiments, one or more AlGaN back barrier layers may be used. In certain embodiments, one or more InGaN back barrier layers may be used. In some embodiments, one or more AlInN back barrier layers may be employed. According to certain embodiments, the thickness of the back-barrier (either in the form of a single layer or a combination of layers) is in the range of about 1-300 angstroms. In certain cases, the III-nitride material device region190(e.g., which may comprise at least one gallium nitride material layer) has a single crystal (i.e., monocrystalline) structure. In some cases, the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) includes one or more layers having a Wurtzite (hexagonal) structure. In some embodiments, the III-nitride material device region comprises an optional channel layer. The channel layer may be positioned, according to certain embodiments, over the back barrier layer when present. For example, inFIG.1C, exemplary III-nitride material device region190comprises optional channel layer190B, which as shown inFIG.1C, is positioned over optional back barrier layer190A. In other embodiments in which the back barrier layer is not present, the channel layer can be the layer within the III-nitride material device region that is closest to the underlying substrate. According to certain embodiments, the channel layer composition is selected with a smaller bandgap than either the spacer and or front-barrier layers (described in more detail below). Such arrangements can create a heterostructure forming a two-dimensional electron gas (2DEG) near the interface between the channel layer and an overlying layer (e.g., the spacer layer and/or the front barrier layer, described in more detail below). Such arrangements may be present, for example, in High Electron Mobility Transistors (HEMTs) and Schottky diodes. Electron flow through HEMTs and HFETs between the source and the drain of the device can, in some instances, be controlled by the gate of the device which acts to interrupt electron current flow between the source and drain. The channel layer can be formed, in certain cases, such that impurities or other point defects (which can act as trapping centers) are kept at a relatively low level, for example, to avoid impeding the mobility of the electrons and/or to avoid adding memory effects to the device. Trapping centers can adversely impact linearity in RF devices and turn-on and turn-off (switching) speeds in power management devices. The thickness of the channel layer can vary, for example, depending on the operational voltage desired for the device. As the drain voltage is increased, the depth of the depletion area between the gate and drain generally increases. In certain cases, if the channel is formed too thin, punch through into the buffer layer can occur, which can result in drain leakage and breakdown of the device. According to certain embodiments, the III-nitride material device region comprises an optional spacer layer (sometimes also referred to as an interlayer). The spacer layer may be positioned, according to certain embodiments, over the channel layer and/or the back barrier layer when present. For example, inFIG.1C, exemplary III-nitride material device region190comprises optional spacer layer190C, which as shown inFIG.1C, is positioned over optional back barrier layer190A and over optional channel layer190B. In some embodiments, the interface between the channel layer and the spacer layer can form a 2-dimensional electron gas region (i.e., a “2DEG region”). For example, inFIG.1C, 2DEG region191is located at the interface of spacer layer190C and channel layer190B. Typically the spacer layer, when used, is formed with a high aluminum content. In some embodiments, the spacer layer is configured to have a relatively high bandgap offset with the underlying channel layer (e.g., by using a relatively high aluminum content in the spacer layer), which can lead to enhancement of the 2DEG. In certain embodiments, the spacer layer comprises AlxGa(1−x)N. In certain such embodiments, (1−x)=0.5 or greater. In some embodiments, the spacer layer comprises AlN. According to certain embodiments, the spacer layer is relatively thin (for example, less than about 50 Angstroms, less than about 20 Angstroms, or less). The use of a relatively thin spacer layer can avoid, in some cases, adversely impacting the ohmic contact resistance of the source and drain to the 2DEG and channel layer of the device. The III-nitride material device region comprises, in some embodiments, an optional front barrier layer. The front barrier layer may be positioned, according to certain embodiments, over the spacer layer, the channel layer, and/or the back barrier layer when present. For example, inFIG.1C, exemplary III-nitride material device region190comprises optional front barrier layer190D, which as shown inFIG.1C, is positioned over optional back barrier layer190A, over optional channel layer190B, and over optional spacer layer190C. According to certain embodiments (and as described above), if the device structure is a HEMT and/or if a 2DEG is desired, the optional front-barrier190A can be formed over the channel layer190B (or spacer layer190C, if used) to form a heterojunction The composition of the front-barrier is selected, according to certain embodiments, such that the carrier density and/or sheet charge of the 2DEG is tailored (e.g., optimized) for the device desired. In certain embodiments, the front-barrier layer comprises AlGaN. According to certain embodiments in which an AlGaN-containing front-barrier layer is used, the aluminum concentration of the AlGaN front-barrier is less than about 30 atomic percent (at%), less than about 25 at%, or between about 15 at% and about 20 at%. In certain embodiments, it may be desirable to match or substantially match the lattice constant between the channel and the front-barrier, and to maintain a bandgap offset, for example, to create a 2DEG. In some such cases, an AlInN or InGaN front-barrier layer can be created to provide the bandgap offset and match or substantially match the lattice constants. According to some embodiments, the III-nitride material device region comprises an optional cap layer. The cap layer may be positioned, according to certain embodiments, over the front barrier layer, the spacer layer, the channel layer, and/or the back barrier layer when present. For example, inFIG.1C, exemplary III-nitride material device region190comprises optional cap layer190E, which as shown inFIG.1C, is positioned over optional back barrier layer190A, over optional channel layer190B, over optional spacer layer190C, and over optional front barrier layer190D. Cap layers have been found useful in optimizing the semiconductor surface of the device structure, according to certain embodiments. For example, in certain cases in which the cap layer(s) comprises GaN, the resulting surface morphology may be smoother and/or include fewer defects, relative to surfaces formed when the cap layer(s) is not present. In addition, in some cases, a more uniform source composition may also be provided (i.e., terminated with gallium atoms rather than a mixture of gallium and aluminum atoms), which may, in some instances, aid in surface chemistry processing of the semiconductor surface and/or reduce the number of surface defects under the gate of the HFET. Such surface defects may, for example, act as shallow trapping centers and compromise the performance of the device, for example, due to increased gate leakage or lateral breakdown of the device, increased dispersion, increased gate and drain lag of the device, amongst other reductions in performance. Additionally, in certain cases, by providing a more consistently terminated semiconductor surface, the repeatability and consistency of the contact resistance may be enhanced, which can lead to higher manufacturing yields. In some embodiments, it may be desired to dope the cap layer(s). In some instances in which the barrier is doped, it may be desirable to use a GaN cap layer which is n-type doped (e.g., using silicon). The use of an n-type doped cap layer may, according to certain embodiments, reduce Idss degradation of the device. In some embodiments, the cap layer(s) may comprise a conductive GaN material layer, for example, used as a conductive field plate. In certain embodiments, the cap layer(s)190E may be doped p-type, for example, with magnesium. Such doping may be desirable, for example, in certain cases in which a normally OFF or enhancement mode HFET is being fabricated. As one non-limiting example, by forming a localized p-type GaN region under the gate of the HFET, the 2DEG can be disrupted and the channel depleted such that under no bias, the device is normally off. In some such cases, a positive bias to the gate would then be needed to restore the 2DEG locally under the gate and allow current flow from the source to the drain. It should be noted that one or more layers may be used as the cap layer(s), and that whether a single cap layer or multiple cap layers are employed may depend, for example, on the specifics of the design device structure. In some embodiments, the cap layer may include an in-situ silicon nitride cap layer and/or passivation layer. Such layer(s) may be used to terminate the III-Nitride structure and/or stabilize the surface of the GaN material. In some embodiments, the III-nitride material device region190comprises at least two device layers. In some embodiments, the first device layer can be the closest of two or three layers to the substrate. If three layers are present, the second device layer can be an intermediate layer (i.e., between the first device layer and a third device layer), and the third device layer can be the farthest of the three layers from the substrate. In some such embodiments, the first layer can be a channel layer, the second device layer can be a front-barrier layer, and the third device layer can be a cap layer. In some embodiments, the cap layer may not be present. Referring toFIG.1C, for example, III-nitride material device region190can comprise channel layer190B, front-barrier layer190D, and cap layer190E. In some such embodiments, back-barrier layer190A and spacer layer190C are each optional, and one or both may be present or not present. According to some such embodiments, channel layer190B can be the closest of these three layers (i.e., channel layer190B, front barrier layer190D, and cap layer190E) to the underlying substrate. In certain embodiments, it may be preferable for the second device layer to have an aluminum concentration that is greater than the concentration of aluminum in the first layer and/or the third layer. For example, referring toFIG.1C, in some embodiments, front-barrier layer190D can have an aluminum concentration that is greater than the concentration of aluminum in channel layer190B and cap layer190E. In some embodiments, the first and second layers (e.g., channel layer190B and front-barrier layer190D inFIG.1C, respectively) can be gallium nitride material layers, and the value of x (as used elsewhere herein with reference to gallium nitride material layers, in subscripts to denote the relative amount of aluminum in a compound (e.g., the “x” in AlxGa(1−x)N)) in the second gallium nitride material layer may have a value that is between about 0.15 and about 0.3 greater, or between about 0.15 and about 0.75 greater than the value of x in the first gallium nitride material layer. For example, the second device layer may be formed of A10.26Ga0.74N, while the first device layer may be formed of GaN. This difference in aluminum concentration may lead to formation of a highly conductive region at the interface of the second and first device layer (i.e., a 2DEG region). In some embodiments, the first device layer may be formed of GaN. According to certain embodiments, the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) has a low crack level. As described above, the transition layer (particularly when compositionally-graded) and/or the nucleation layer may reduce crack formation. Gallium nitride materials and other III-nitride materials having low crack levels have been described, for example, in U.S. Pat. No. 6,649,287, which is incorporated herein by reference in its entirety for all purposes. In some cases, the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) has a crack level of less than 0.005 μm/μm2. In some embodiments, the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) has a very low crack level of less than 0.001 μm/μm2. In certain cases, it may be preferable for the III-nitride material device region (e.g., which may comprise at least one gallium nitride material layer) to be substantially crack-free as defined by a crack level of less than 0.0001 μm/μm2. The optional III-nitride material nucleation layer, the optional III-nitride material transition layer, and the optional III-nitride material buffer layer are not typically (though may be) part of the active region of devices formed from structures of the embodiments described herein. As described above, these layers may be formed to facilitate deposition of the layer(s) of the III-nitride material device region. Active regions of devices formed from certain of the structures described herein may be formed, in part, in one or more layers of the III-nitride material device region (e.g., gallium nitride material layers). Suitable gallium nitride material layer arrangements have been described, for example, in U.S. Pat. No. 7,071,498, entitled “Gallium Nitride Material Devices Including an Electrode-Defining Layer and Methods of Forming the Same,” issued on Jul. 4, 2006, which is incorporated herein by reference in its entirety for all purposes. Other commonly used III-nitride material device layers include channel layers, spacer layers, barrier layers, capping layers, and P-type layers used under the gate electrodes used for the design of enhancement mode (normally OFF) transistor designs. These III-nitride material device layers may also include, according to certain embodiments, intentionally doped layers in addition to various III-nitride layers exhibiting different alloy compositions. According to some embodiments, a semiconductor structure can comprise a second III-nitride material region120. In certain embodiments, the semiconductor structure comprises a second III-nitride material region over the III-nitride material region120(second III-nitride material region not shown inFIG.1A and1B). In certain embodiments, the second III-nitride material region is an epitaxial III-nitride material region. In some embodiments, the second III-nitride material region comprises a III-nitride device region. According to some embodiments, the second III-nitride material region comprises a 2DEG. The semiconductor structures described herein may, according to certain embodiments, form the basis of a variety of integrated semiconductor devices and/or discrete components (e.g., capacitors, resistors, thermistors, microstrip transmission lines, and inductors). Suitable devices include, but are not limited to, active devices like transistors (e.g., field effect transistors (FETs); either enhancement or depletion mode), Schottky diodes, junction diodes, PIN diodes, as well as light-emitting devices including light emitting diodes (LEDs) and laser diodes. Likewise, suitable devices also include integrated circuits (e.g., monolithic microwave integrated circuits (MMICs) having combinations of two or more active devices and/or discrete components, e.g., for assembly of front end modules (FEMs). It may be particularly advantageous, according to certain but not necessarily all embodiments, to use structures of the invention in devices that operate at high frequencies (e.g., at frequencies of 50 MHz or higher for certain power management applications, at frequencies of 1 GHz or higher (e.g., up to 20 GHz) for certain RF applications). Other non-limiting examples of RF applications include discretes and integrated circuits used for transmit and receive functions associated wireless and wireline communications, RF energy, RF plasma lighting, wireless charging, RF induction and microwave heating, RF spark-plugs, ISM, medical devices, RADAR, and electronic warfare and countermeasure devices. Additional applications using III-nitride devices operating at lower frequencies include power management discretes, devices, and integrated circuits used to switch, rectify, monitor, or control electric power from a source to a load (e.g., buck converters, boost converters, half bridges, H-bridges, full bridges, three-phase bridges and multi-phase bridges). Such power management devices can operate at frequencies down to 1 MHz or lower (e.g., down to about 50 kHz). In certain embodiments, there may be integrated circuits and/or multiple dice on a chip combining both RF devices and switching devices used to monitor, switch, or control the electric power delivery from a source to a load. According to certain embodiments, the devices have active regions that are typically, at least in part, formed within the III-nitride material region (e.g., in one or more layers of the III-nitride material device region, such as one or more gallium nitride material layers). According to some embodiments, the devices include a variety of other functional layers and/or features (e.g., electrodes, dielectric regions, field plate layers, etc.). According to certain embodiments, semiconductor devices can comprise the semiconductor structures described herein. Example devices include a transistor (e.g., a field effect transistor (FET)) or a diode. The transistor can comprise, according to certain embodiments, a source electrode and a drain electrode. The source electrode and the drain electrode can be electronically isolated from each other. For example, in some embodiments, the source electrode and the drain electrode are spatially separated. In some embodiments, the transistor further comprises a gate electrode. The gate electrode may be a Schottky gate or an insulated gate electrode. According to certain embodiments, during use, application of a voltage at the gate electrode can create and/or modify an electric field at least partially positioned between the source electrode and the drain electrode, such that electrons are transferred from the source electrode to the drain electrode. Suitable transistors (e.g., FETs) that may be used in association with certain of the embodiments described herein include depletion mode (normally-ON) transistors and enhancement mode (normally OFF) transistors. A transistor can be associated with any of the semiconductor structures described elsewhere herein, including but not limited to those described with respect toFIGS.1A-1C. FIG.2Ais a cross-sectional schematic illustration of a portion of an exemplary semiconductor device200A comprising a semiconductor structure, according to certain embodiments. In this example, the illustrated device200A includes elements of a transistor, though the invention is not limited to only transistors. The inventive embodiments of semiconductor structures described herein can be applied to diodes, PIN switches, integrated inductors, and integrated capacitors, for example. The structure shown inFIG.2Ais also not limited to transistors. Such structure can be used for a diode, as described in U.S. patent publication No. 2017/0301798, titled “High Voltage Lateral GaN-on-Silicon Schottky Diode,” filed Jul. 29, 2016, which is incorporated herein by reference. For example, the gate electrode260can be used as an anode electrode of a Schottky diode. The source electrode220and drain electrode230can be electrically connected together and serve as cathodes for the diode. FIGS.3A-3Hare top, perspective-view schematic illustrations of contacts and electrodes that can be patterned on the semiconductor device of which device200A shown inFIG.2Ais a part, with the cross-section shown inFIG.2Ataken along line “2A” illustrated inFIGS.3G and3H.FIGS.3A-3Hrepresent a schematic progression of the addition of various components to the semiconductor device. InFIG.3A, a plurality of electrode pairs215have been added over III-nitride material region120. According to certain embodiments, each of the electrode pairs (e.g., components of a transistor) has a source electrode and a drain electrode, each of which define ohmic contacts with an underlying III-nitride material region. As shown inFIG.3A, semiconductor device200A comprises six electrode pairs215A-215F, wherein each electrode pair215A-215F comprises source electrodes220A-220F and drain electrodes230A-230F. The source electrodes make ohmic contacts with the underlying III-nitride material region. For example, inFIG.2A, source electrode220makes ohmic contact302A with III nitride material120. The drain electrodes also make ohmic contacts with the underlying III-nitride material region. For example inFIG.2A, drain electrode230makes ohmic contact302B with III-nitride material region120. Electrode pairs215A-215F may be, in accordance with various embodiments, evenly and/or non-evenly spaced on III-nitride material region120. InFIG.3B, the electrode pairs have been removed to illustrate the interfacial areas between the electrode structures and the underlying semiconductor material (i.e., the ohmic contact interfacial areas), described in more detail below. FIG.3Cis a top, perspective-view schematic illustration of the semiconductor structure ofFIG.3A, but in which gate electrodes240A-240F have been added relative to the structure shown inFIG.3A. InFIG.3C, gate electrodes240A-240F have been added between each of electrode pairs215A-215F (each electrode pair including a source electrode220and a drain electrode230), creating transistors210A-210F. InFIG.3D, gate contact pad244, which establishes electrical connections to gate contacts240, has been added. InFIG.3E, drain contact pad234, which establishes electrical connections to drain contacts230, has been added. InFIG.3F, source contact pads224A-224D, which establish electrical connections to source contacts220, have been added. FIG.3Gis a top, perspective-view schematic illustration of the completed device, withFIG.3Hshowing a magnified view of portion350. In certain embodiments, as shown inFIG.3C-3H, the semiconductor structure comprises multiple transistors. In other embodiments, the semiconductor structure includes only a single transistor. When multiple transistors are present, any suitable number of transistors (e.g. one, two, three, four, or more) can be present. Referring back toFIG.2A, transistor210comprises source electrode220and drain electrode230. Transistor210also comprises gate electrode240. Source electrode220, drain electrode230, and gate electrode240are positioned on III-nitride material region120. The device also includes dielectric region250. The dielectric region can be a passivating layer that protects and passivates the surface of the III-nitride material region. Via260is formed within the dielectric region250in which gate electrode240is, in part, formed. InFIG.2A, as described above, III-nitride material region120is formed directly on substrate110. It is also noted that the configuration of gate electrode240in direct contact with the III-nitride material device region120forms a Schottky-gated FET. In other embodiments (not shown inFIG.2A) there may be an insulator layer formed between gate electrode240and III-nitride material device region120configured as a Metal Insulated Field Effect Transistor (MISFET) or more generically an insulated gate transistor. It should also be noted that, althoughFIG.2Ashows via260formed within dielectric region250, in certain other embodiments, via260could extend down and terminate within III-nitride material region120. The transistor structures illustrated inFIGS.2A-2D(andFIGS.3A-3H) are exemplary, and other structures could also be used. For example, according to some embodiments, a single transistor comprising a semiconductor structure described herein may be located over the surface region of the substrate. In some embodiments, at least one second transistor or at least one diode comprising a semiconductor structure described herein can be located over the substrate and laterally spaced apart from the first transistor. As noted above, certain embodiments are related to systems and methods for mitigating the impact of temperature increases on device performance. The maximum junction temperature in III-nitride materials on silicon substrates is typically fundamentally limited by junction reliabilities within the semiconductor device, and more specifically, by the substrate (e.g., silicon-containing substrate) resistivity at elevated temperatures. In certain cases, a resistive silicon-containing substrate at the epitaxial interface heats up under RF operation and elevated temperatures, and conducts RF current that degrades product performance such as output power and efficiency. In some cases, “high resistivity” silicon does not retain its high resistivity properties above 50° C. For example, 10 kΩ·cm high resistivity silicon at 25° C. becomes 100 Ω·cm at 177° C. As a result, in certain cases, current through the transistor (i.e., dissipated power) generates heat that spreads into the substrate from the III-nitride material. In certain cases, the substrate is capacitively coupled with conductive structures (e.g., source, drain, or gate electrodes, associated contact pads, etc.), for example, at the III-nitride material interface. In some such cases, application of an RF voltage across the drain electrode to the source electrode generates heat in the substrate, leading to thermal runaway by increasing the heat source temperature and reducing the substrate resistance even further. Effectively, in certain instances, as the temperature of the package flange and/or supply voltage of the semiconductor device is increased, the substrate resistance is decreased, and as a result the semiconductor structure has both lower output power and lower efficiency. RF induced substrate power dissipation is a strong function of supply voltage, and the power dissipated in the silicon-containing substrate is proportional to the square of the peak RF voltage, leading to significant performance degradation for semiconductor structures containing highly resistive silicon-containing substrates. In some cases, when a voltage is applied to a semiconductor device, current is generated within the semiconductor structure between at least two electrodes (e.g., between a source electrode and a drain electrode). The flow of current within the semiconductor structure is generally dictated by Ohm's law, which dictates that the current is inversely proportional to the resistance. In some cases, the passage of electrical current through the semiconductor structure produces heat (also referred to as Joule heating or resistive heating); in this process, electric current energy is converted to heat through resistive losses (e.g., dissipated power) in the substrate of the semiconductor structure. As discussed above, certain of the devices and semiconductor structures described herein comprise electronically conductive substrates (e.g., electronically conductive substrates comprising bulk silicon). The electrical resistance in the substrate can be reduced by the use of electronically conductive substrates (e.g., as the conductivity of the substrate increases, the resistance of the substrate decreases). As a result, the resistive heating of the semiconductor structure is lowered, resulting in semiconductor devices and semiconductor structures with less performance degradation and better efficiencies at higher operating temperatures, which is explained in more detail herein. In certain embodiments, semiconductor structures comprising thick III-nitride material regions are described. The use of thick III-nitride materials can reduce leakage current between the substrate and components of a device that is formed using a semiconductor structure described herein. As a result, in some embodiments, the use of thick III-nitride layers can reduce the degree to which electrons are transported, undesirably, between the substrate and electronically conductive structures on the III-nitride material surface. In some cases, ohmic contacts are present between electrode structures (e.g., metal structures) and the III-nitride material region, and in certain cases, the ohmic contact areas capacitively couple RF current to the electronically conductive substrate. In some cases, capacitive coupling results from the transfer of energy within the electrical network of the semiconductor structure by means of displacement current between transistor components incorporated in the semiconductor structure (e.g., a source electrode and/or a drain electrode) and the substrate. According to certain embodiments, the capacitive coupling and displacement current generated during operation of the semiconductor structure can be decreased by the use of small ohmic contacts over the III-nitride material surface. Reduced ohmic contact interfacial areas on the III-nitride material surface have the effect, in accordance with certain embodiments, of lowering the amount of dissipated current transported through the substrate of the semiconductor structure. Some embodiments described herein are related to the use of small ohmic contacts with large contact pads. In certain embodiments, the contact pads are present above and electrically connect to the electrode structures (e.g., metal structures) that make ohmic contacts with the III-nitride material surface. According to certain embodiments, large contact pads are useful for making external electrical connections to the semiconductor device. In certain embodiments, the contact pads described above are present on a thick dielectric region that separates the large contact pads from the III-nitride material region. According to some embodiments, the use of a thick dielectric region between the large contact pads and the III-nitride material region can reduce the capacitance to the electronically conductive substrate, resulting in higher operating temperatures and better efficiencies at said temperatures. Certain of the semiconductor structures described herein can be “self-grounding,” for example, by including an electrical coupling between an electronically conductive component (e.g., on the top side of the device, such as an electrode or a contact pad) and the electronically conductive substrate (or an electronically conductive portion of the substrate). For example, in some embodiments, the semiconductor structures include a cavity formed in the top portion of the device. The cavity can be, in accordance with certain embodiments, a front-side via (also referred to as a top-side via). The cavity can be configured to expose the electronically conductive substrate (or an electronically conductive portion thereof), for example by extending through the III-nitride material region. In some embodiments, an electronically conductive material (e.g., a metal) can be disposed such that it establishes an electronically conductive grounding pathway between an electronically conductive component on the top side of the device to the electronically conductive substrate (or an electronically conductive portion of the substrate). The electronically conductive pathway between the electronically conductive component and the substrate can ensure that charge does not accumulate in an unwanted location, and can help limit the amount of power dissipated during operation. This arrangement can result in a “self-grounding” structure where no external electrical connection, such as a wire, is required to ground the device. Certain embodiments are related to semiconductor structures comprising a substrate, at least a portion of which is electronically conductive. Referring back toFIGS.2A, substrate110can be an electronically conductive substrate (e.g., a bulk silicon substrate) and/or may include a portion that is electronically conductive. In some embodiments, the use of substrates having electronically conductive regions can reduce the amount of heat that is generated during device operation. For example, in some cases, as a voltage is applied to the semiconductor structure, an electrical current is generated between at least two electrode structures, such as a source electrode and a gate electrode. Additionally, current can also be (undesirably) transported through the substrate. As current is transported through the substrate, heat can be generated (for example, due to Joule heating). In the case of highly resistive substrates, the generation of heat can result in a decrease in resistivity, which can result in an increase in the current transported through the substrate (which still remains relatively highly resistive), increased Joule heating, and increased substrate temperatures. In certain embodiments described herein, however, the use of substrates having electronically conductive regions can allow for current to be transferred through the substrate relatively efficiently, with little or no Joule heating. The relatively efficient transport of electrical current through the substrate can improve the efficiency of devices and components formed from the semiconductor structure, for example, even at relatively high operating temperatures. In certain embodiments, the devices having semiconductor structures described herein comprise at least one ohmic contact located over the III-nitride material region. Certain devices (e.g., Schottky diodes and HEMTs) can also include Schottky contacts at the anode and gate, respectively. Referring toFIGS.2A and3A-3B, semiconductor device200A comprises ohmic contacts302A and302B located over III-nitride material region120. In certain embodiments, the ohmic contacts are an electrical junction between an electrode structure (e.g., a source electrode and/or a drain electrode of a transistor) and an underlying portion of the semiconductor structure (e.g., the III-nitride material region). In some cases, capacitive coupling occurs between the ohmic contact(s) and the substrate. The capacitive coupling between the ohmic contact(s) and the substrate can lead to the displacement current flowing through the substrate, resulting in dissipated power. In some embodiments, as the ohmic contact area of the at least one ohmic contact decreases, the capacitive coupling between the ohmic contact(s) and the substrate decreases. In some such cases, less displacement current is transported through the substrate. Accordingly, in accordance with certain embodiments, the semiconductor devices described herein comprise ohmic contacts that are relatively small, which can help reduce capacitive coupling losses. It should be understood that an ohmic contact that is “over” a III-nitride material region can sit on top of the III-nitride material region or be at least partially embedded in the III-nitride material region. For example, referring toFIGS.2A, ohmic contact302A and ohmic contact302B are embedded in III-nitride material region120.FIG.2Cis, in accordance with certain embodiments, a side-view schematic illustration of a semiconductor device with ohmic contacts on top of the III-nitride material region. In some embodiments, such as those illustrated inFIG.2C, ohmic contact302A and ohmic contact302B sit on top of III-nitride material region120. According to certain embodiments, at least one ohmic contact defines an ohmic contact interfacial area with the III-nitride material region. The ohmic contact interfacial area of a given ohmic contact type (e.g., drain ohmic contact) refers to the area of the interface between the ohmic contact or contacts of the same type in a device and the III-nitride material. The ohmic contact interfacial area of a device (also referred to herein as the “device ohmic interfacial area”) refers to the sum of all of the interfacial areas of the ohmic contacts of that device. For example, in the case of a transistor having a source electrode and a drain electrode, the device ohmic contact interfacial area for that device would correspond to the sum of the ohmic contact interfacial areas of all ohmic contacts for the source electrode and the drain electrode. The ohmic contact interfacial area of that transistor device would not include the interfacial area of the gate electrode, since in some cases the gate electrode may form a Schottky contact or a capacitive contact, rather than an ohmic contact. Referring toFIGS.2A, for example, ohmic contact302A of source electrode220has interfacial area308, and ohmic contact302B of drain electrode230has interfacial area309. In addition, Schottky contact303of gate electrode240for the depicted type of transistor has interfacial area310.FIG.2Dis a top-view schematic illustration of the semiconductor device illustrated inFIG.2A(with the cross-sections shown inFIG.2Ataken along line2A inFIG.2D). InFIG.2D, ohmic contact302A of source electrode220has interfacial area308, where source electrode220contacts III-nitride material region120. InFIG.2D, ohmic contact302B of drain electrode230has interfacial area309, where drain electrode230contacts III-nitride material region120. Schottky contact303of gate electrode240has interfacial area310, where gate electrode240contacts III-nitride material region120. Ohmic contact interfacial areas are further shown inFIG.3B. InFIG.3B, source electrodes220A-220F that make ohmic contacts302A with underlying III-nitride material region and drain electrodes230A-230F that each make an ohmic contact302B with underlying III-nitride material region120have been removed (relative toFIG.3A) for purposes of clarity, and to illustrate the interfacial areas defined by the electrodes of the electrode pairs. Referring toFIG.3B, each of areas308A-308F and309A-309F correspond to the interfacial area defined by one of the ohmic contacts (e.g.,302A and302B) fromFIG.3A. For example, inFIG.3B, electrode pair215A comprises interfacial area308A that is defined by ohmic contact302A of source electrode220A, and interfacial area309A that is defined by ohmic contact302B of drain electrode230A. In certain embodiments, each electrode pair215A-215F comprises interfacial areas308A-308F and309A-309F. Where there are multiple electrodes of a same type (e.g., drain, source, cathode) present in a device, the ohmic contact interfacial area for a type of an electrode is a sum of all constituent ohmic contact interfacial areas for electrodes of a same type. For example, a drain ohmic contact interfacial area for the device ofFIG.3Bwould be a sum of interfacial areas309A-309F. The ohmic contact interfacial area can generally be calculated by examining a top-down view of the semiconductor device and determining the geometric area of the III-nitride region that is covered by the conductive material forming the ohmic contact with the III-nitride region. The interfacial areas of the ohmic contacts can have any of a variety of suitable shapes including, but not limited to, square, rectangular, circular, and the like. According to certain embodiments, the ohmic contact interfacial area of the device is less than 50 μm2, less than 40 μm2, less than 30 μm2, less than 20 μm2, or less than 10 μm2. In certain embodiments, the ohmic contact interfacial area of the device is greater than 1 μm2, greater than 10 μm2, greater than 20 μm2, greater than 30 μm2, or greater than 40 μm2. Combinations of these ranges are also possible (e.g., less than 40 μm2and greater than 20μm2, less than 30 μm2and greater than 10 μm2). According to some embodiments, an ohmic contact interfacial area ratio can be defined for a device. For example, an ohmic contact interfacial area ratio can be defined as a ratio of the ohmic contact interfacial area of at least one type of ohmic contact for a device (e.g., interfacial area of a source or drain of a transistor or interfacial area of a cathode for a Schottky diode) to a peripheral length of a gate or anode for the device. For example and referring toFIG.2AandFIG.2D, an ohmic contact interfacial area ratio for a transistor can be a ratio of a drain interfacial area309to a gate peripheral length L that is measured transverse to the direction of current flow under the gate electrode240. In this regard, gate peripheral length L is measured in a direction that is transverse to conventional “gate length.” If a device has more than one gate or anode, then the peripheral length for the device will be the sum of all peripheral lengths for the constituent gates (e.g.,240A-240F as depicted inFIG.3C) or anodes for the device. For a diode, anode peripheral length would correspond to a length of the anode (or all anodes of the device) measured transverse to the direction of current flow from the anode. If an ohmic contact for a device comprises a plurality of ohmic contacts of a particular type (e.g., a plurality of drain contacts, as described in connection withFIG.3Afor example) then the ohmic contact interfacial area for the device is a sum of all relevant ohmic contact interfacial areas (e.g., a sum of ohmic contact interfacial areas309A-309F for drain contacts of the device) divided by the peripheral length of a selected terminal for the device. For a transistor, an ohmic contact interfacial area ratio can be calculated for the drain contact(s). Additionally or alternatively, an ohmic contact interfacial area ratio can be calculated for the source contact(s). The units of an ohmic contact interfacial area ratio (and other area-to-peripheral length ratios described herein) can be expressed in square microns/micron (μm2/μm) or (μm), where the size of the ohmic contact interfacial area and the peripheral length are both measured in microns. Other units may be used to express area-to-peripheral length ratio with a corresponding change in ratio value. In some implementations, devices formed in accordance with the present embodiments can have an ohmic contact interfacial area ratio for at least one type of ohmic contact of the device. An ohmic contact interfacial area ratio can be between 1 μm2/μm and 30 μm2/μm. The ohmic contact interfacial area ratio for at least one type of ohmic contact of a device can be less than 5 μm2/μm according to some embodiments, less than 10 μm2/μm according to some embodiments, less than 20 μm2/μm according to some embodiments, and yet less than 40 μm2/μm according to some embodiments. According to certain embodiments, the semiconductor devices described herein comprise components of transistor, including a source electrode over the III-nitride material region. For instance, referring toFIGS.2A, semiconductor device200A comprises source electrode220over III-nitride material region120. In certain embodiments, the source electrode defines a source electrode interfacial area with the III-nitride material region. The source electrode interfacial area corresponds to interfacial area of the ohmic contact between the source electrode and the III-nitride material region. For example, referring toFIG.2AandFIG.2D, source electrode220has interfacial area308. In some embodiments, the semiconductor devices described herein comprise a drain electrode over the III-nitride material region. For instance, referring toFIGS.2A, semiconductor device200A comprises drain electrode230over III-nitride material region120. In certain embodiments, the drain electrode defines a drain electrode interfacial area with the III-nitride material region. The drain electrode interfacial area corresponds to the interfacial area of the ohmic contact between the drain electrode and the III-nitride material region. Referring toFIGS.2AandFIG.2D, for example, drain electrode230has interfacial area309. According to certain embodiments, the semiconductor devices described herein comprise a gate electrode over the III-nitride material region. For instance, referring toFIGS.2A, semiconductor device200A comprises gate electrode240over III-nitride material region120. In certain embodiments, the gate electrode defines a gate electrode interfacial area with the III-nitride material region. The gate electrode interfacial area corresponds to the interfacial area of the contact between the gate electrode and the underlying material, which could be the III-nitride material or an intermediate material between the gate electrode and the III-nitride material. Referring toFIGS.2AandFIG.2D, for example, gate electrode230has interfacial area310. According to some embodiments, it may be beneficial to have an ohmic contact interfacial area that is less than 50 times the gate electrode interfacial area because reduced interfacial areas of the source and drain ohmic contacts on the III-nitride material surface can reduce the capacitive coupling to the substrate (e.g., an electronically conductive substrate). In certain embodiments, the ohmic contact interfacial area defined by the source electrodes is less than 50 times (or less than 40 times, less than 30 times, less than 20 times, less than 10 times, or less than 5 times) the Schottky contact interfacial area defined by the gate electrodes. In some embodiments, the ohmic contact interfacial area defined by the source electrodes is at least 0.01 times, at least 0.1 times, or at least 1 time the Schottky contact interfacial area defined by the gate electrodes. Combinations of these ranges are also possible. For example, referring toFIG.2D, the ohmic contact interfacial area308defined by source electrode220is less than 50 times the Schottky contact interfacial area310defined by the gate electrode. To calculate the ratio of the ohmic contact interfacial area defined by the source electrodes to the Schottky contact interfacial area defined by the gate electrodes, one would determine the ratio of:(1) interfacial area308defined by source electrode220to(2) interfacial area310defined by gate electrode240. According to certain embodiments, the ohmic contact interfacial area defined by the drain electrodes is less than 50 times (or less than 40 times, less than 30 times, less than 20 times, less than 10 times, or less than 5 times) the Schottky contact interfacial area defined by the gate electrodes. In some embodiments, the ohmic contact interfacial area defined by the drain electrodes is at least 0.01 times, at least 0.1 times, or at least 1 time the Schottky contact interfacial area defined by the gate electrodes. Combinations of these ranges are also possible. For example, referring toFIG.2D, the ohmic contact interfacial area309defined by drain electrode230is less than 50 times the Schottky contact interfacial area310defined by the gate electrode. To calculate the ratio of the ohmic contact interfacial area defined by the drain electrodes to the Schottky contact interfacial area defined by the gate electrodes, one would determine the ratio of:(1) interfacial area309defined by drain electrode230to(2) interfacial area310defined by gate electrode240. In certain embodiments, the ohmic contacts define an active area. For example, in embodiments in which the semiconductor device comprises a transistor, the source electrode and the drain electrode define an active area. The active area generally refers to the area over which electrons are transported between ohmic contacts during normal operation of the semiconductor structure. For example, in the case of a transistor, the active area refers to the area under and between the source and the drain electrodes over which electrons are transported during device operation. One example of an active area is shown inFIGS.2A. InFIGS.2A, the active area306is the area over which the drain current is transported between ohmic contacts302A and302B. In certain embodiments, the active area of a semiconductor device includes the area both beneath the ohmic contact, as well as the area between them. For example, referring toFIGS.2A, ohmic contact active area306includes the area beneath ohmic contacts302A and302B, as well as the area between ohmic contacts302A and302B. The active area shown inFIGS.2Ais also shown in the top-view schematic illustration ofFIG.2D. InFIG.2D, semiconductor device200A comprises source electrode220, drain electrode230, and gate electrode240. Source electrode220and drain electrode230define active area306, denoted by dotted box307. Exemplary active areas are also shown in the top, perspective view schematic illustration shown inFIG.3B. InFIG.3B, each electrode pair215A-215F comprises ohmic contacts302A and302B where source electrode220A-220F and drain electrode230A-230F contact the III-nitride material region120. (SeeFIG.3A). As shown inFIG.3B, in some embodiments, each electrode pair215A-215F has an active area (306A-306F), which are denoted by dotted boxes. The active area of a given semiconductor device can be defined by a single continuous region or a plurality of regions (as shown inFIGS.3A-3H). In instances in which a plurality of regions define the active area of the semiconductor device, the active area of the device (also referred to herein as the “cumulative active area” of the device) is calculated by summing the areas of the individual active area regions in the semiconductor device. For example, referring toFIG.3B, the cumulative active area of semiconductor device200A would be determined by adding the areas of regions306A,306B,306C,306D,306E, and306F. The size and shape of the active area of a given semiconductor device will depend upon the size, shape, and layout of the ohmic contacts. According to certain embodiments, the active area of the semiconductor device can be defined by regions having any of a variety of suitable shapes, including but not limited to, square regions, rectangular regions, circular regions, and the like. While examples of active areas have been described with reference to an exemplary transistor, other semiconductor devices also have active areas, and those of ordinary skill in the art would be capable of determining the active area of a given semiconductor device based on its geometry and operation. For example, in some cases, the semiconductor device can be a diode. Referring toFIG.2A, for example, a diode could be created by short circuiting electrode220(previously referred to as the source electrode in exemplary transistor embodiments) and electrode230(previously referred to as the drain electrode in exemplary transistor embodiments) such that, together, they form one electrode (e.g., a cathode of a diode). Electrode240(previously referred to as the gate electrode in exemplary transistor embodiments) could be used as a second electrode (e.g., an anode). In such a case, each of source electrode220and drain electrode230would establish an ohmic contact (i.e., contacts308and309would remain ohmic contacts. Contact310would remain a Schottky contact. The active area in such a device would correspond to the area over which electrons would be transported between the Schottky contact and ohmic contacts during normal operation of the diode. For the example ofFIG.2A, the active area for a corresponding diode embodiment may be slightly less than the active area of the transistor embodiment. However, for short gate lengths, the difference in active area may be insignificant. According to certain embodiments, the ohmic contacts in the semiconductor device define a cumulative active area that is less than 100 μm2, less than 80 μm2, less than 60 μm2, less than 40 μm2, or less than 20 μm2. In certain embodiments, the ohmic contacts define an active area that is greater than 10 μm2, greater than 20 μm2, greater than 40 μm2, greater than 60 μm2, or greater than 80 μm2. Combinations of these ranges are also possible (e.g., greater than 40 μm2and less than 80 μm2, greater than 10 μm2and less than 40 μm2). In some embodiments, the semiconductor device includes at least one region having a continuous active area that is at least 10 μm2(or at least 20 μm2, at least 40 μm2, at least 60 μm2, at least 80 μm2, or at least 100 μm2) in size. According to some embodiments, an active-area ratio can be defined for a device. For example, an active-area ratio can be defined as a ratio of the active area of a device to a peripheral length of a gate or anode for the device. The gate or anode peripheral length can be determined as described above. The active area can be the active area (e.g., active area306) of a single device having one gate or anode, or the sum of all active areas of constituent devices (e.g., when there is more than one gate or anode present in a device). In some implementations, devices formed in accordance with the present embodiments can have an active-area ratio that is between 10 μm2/μm and 250 μm2/μm. The active-area ratio of a device can be less than 20 μm2/μm according to some embodiments, less than 50 μm2/μm according to some embodiments, less than 100 μm2/μm according to some embodiments, and yet less than 200 μm2/μm according to some embodiments. In certain embodiments, the sum of the source electrode interfacial area, the drain electrode interfacial area, and the gate electrode interfacial area is substantially less than the active area defined by the source electrode, drain electrode, and the gate electrode. Without wishing to be bound by any particular theory, it is believed that employing electrodes and active areas that are sized in this way advantageously reduces capacitive coupling between the electrodes and the substrate. According to certain embodiments, the sum of the source electrode interfacial area, the drain electrode interfacial area, and the gate electrode interfacial area is less than 65% of the active area. For example, referring toFIG.2D, source electrode220has interfacial area308with III-nitride material region120that is about 30% of active area306. In addition, inFIG.2D, drain electrode230has interfacial area309with III-nitride material region120that is about 30% of active area306. In certain embodiments, inFIG.2D, gate electrode240has interfacial area310with III-nitride material region120that is about 2.5% of active area306. Thus, inFIG.2D, the sum of the interfacial areas310,309, and310is about 60% of active area306(which is less than 65% of active area306). In certain embodiments, the sum of the source electrode interfacial area and the drain electrode interfacial area is less than 60% of the active area. For example, referring toFIG.2D, in some embodiments, the sum of interfacial areas308and309is less than 58.5% of active area306. In certain embodiments, the gate electrode interfacial area is less than 3% of the active area. For example, inFIG.2D, in some embodiments, the interfacial area310is less than 2.6% of active area306. In certain embodiments, the sum of the device ohmic interfacial area and the device gate interfacial areas is substantially less than the device cumulative active area. According to certain embodiments, the sum of the device ohmic interfacial area and the device gate interfacial areas is less than 65% of the device cumulative active area. For example, referring toFIG.3B, the sum of interfacial areas308A-308F is about 30% of the sum of active areas306A-306F. In addition, inFIG.3B, the sum of interfacial areas309A-309F is about 30% of the sum of active areas306A-306F. In certain embodiments, inFIG.3C, gate electrodes240A-240F define interfacial areas310A-310F with III-nitride material region120that is about 5% of the sum of active areas306A-306F (inFIG.3B). Thus, the sum of the interfacial areas308A-309F,309A-309F, and310A-310F is about 60% of active area306A-306F (which is less than 65% of active area306A-306F). In certain embodiments, the device ohmic interfacial area is substantially less than the device cumulative active area. According to certain embodiments, the device ohmic interfacial area is less than 60% of the device cumulative active area. For example, referring toFIG.3B, the sum of interfacial areas308A-308F is about 30% of the sum of active areas306A-306F. In addition, inFIG.3B, the sum of interfacial areas309A-309F is about 30% of the sum of active areas306A-306F. Thus, the sum of the interfacial areas308A-309F and309A-309FF is about 58% of active area306A-306F (which is less than 60% of active area306A-306F). In certain embodiments, the gate electrode cumulative interfacial area is less than 3% of the cumulative active area. For example, referring toFIG.3C, in some embodiments, the sum of interfacial areas310A-310F is less than 2.5% of active area306A-306(inFIG.3B). According to certain embodiments, the semiconductor structures described herein comprise a thick III-nitride material region located over the substrate. For example, referring toFIGS.2A, semiconductor device200A comprises III-nitride material region120that can be thick. As noted above, in certain embodiments the III-nitride material region located over the substrate has a thickness of at least 2.0 micrometers. For example, in some embodiments, the III-nitride material region located over the substrate has a thickness of 4.8 micrometers. According to certain embodiments, the use of a relatively thick III-nitride material region reduces undesired leakage current and transport of electrons from a first electrode structure (e.g., a source electrode), through the electronically conductive substrate (e.g., a silicon-containing substrate), and to a second electrode structure (e.g., a drain electrode).FIG.2Bis a is a cross-sectional schematic illustration of a semiconductor device having a semiconductor structure that includes an electronically conductive substrate, according to some embodiments. Referring toFIG.2B, source electrode220is electrically connected to drain electrode230by current flow304through III-nitride material region120and substrate110. In certain embodiments, the use of a thick III-nitride material region120can reduce the amount of leakage current between source electrode220and drain electrode230as less current is leaked along current flow304. In certain embodiments, the use of a relatively thick III-nitride material region reduces the capacitive coupling between electrode structures (e.g., metal electrodes) and the substrate. In some instances, the use of an electronically conductive substrate (e.g., a silicon-containing substrate) results in an increase in the capacitance between electrode structures and the substrate, effectively reducing the efficiency of devices or components formed using the semiconductor structure. Thickening the III-nitride material region, according to some embodiments, reduces the amount of energy transferred between the electrode structures and the substrate. Referring toFIG.2B, use of a thick III-nitride material region120can reduce the amount of capacitive coupling between source electrode220, drain electrode230, and gate electrode240with substrate110. In certain cases, the source electrode, the drain electrode, and/or the gate electrode of transistors can capacitively couple to the substrate. Similarly, anode and cathode electrodes of diodes can capacitively couple to the substrate. Certain embodiments are directed to employing component configurations and/or methods of operation that reduce the degree to which capacitive coupling is observed. In some cases, the capacitive coupling results from the use of conductive substrates, as conductive structures (e.g., source, drain, and/or gate electrodes) capacitively couple to the substrate (e.g., silicon-containing substrate). In certain embodiments, the capacitive coupling can be reduced by the use of thick III-nitride materials, and/or the use of small ohmic contacts associated with the electrodes. In certain embodiments, the capacitive coupling of the at least one type of ohmic contact (e.g., drain, source, cathode) with the substrate is small. According to some implementations, an ohmic contact capacitance ratio can be defined for a device. The ohmic contact capacitance can depend on at least the ohmic contact area and on a thickness of the epitaxial structure between the ohmic contact(s) and the conductive substrate. Without being bound to any particular theory, a capacitance ratio of an ohmic contact can be expressed as follows Coc=(ε0εrAoc)/(tL) (2) where ε0is the permittivity of free space, εris the effective relative permittivity of the epitaxial structure between the ohmic contact and the conductive substrate, Aocis the area of the ohmic contact, t is the thickness of the epitaxial structure between the ohmic contact and the conductive substrate, and L is the gate or anode peripheral length. If there is more than one ohmic contact (e.g., multiple drain contacts), then the areas of the ohmic contacts are summed to obtain Aoc. Similarly, the gate or anode peripheral length L is a sum of peripheral lengths of constituent gates or anodes in a device, as described above. As an example for an epitaxial structure of the present embodiments that is approximately 1.6 microns thick with εrof approximately 9.5, an ohmic contact capacitance ratio for at least one type of ohmic contact of a device can have a value between 0.1 pF/mm and 2.5 pF/mm. The ohmic contact capacitance ratio for at least one type of ohmic contact of a device can be less than 0.25 pF/mm in some cases, less than 0.5 pF/mm in some cases, less than 1 pF/mm in some cases, and yet less than 2 pF/mm in some cases. As another example for an epitaxial structure of the present embodiments that is approximately 4.8 microns thick with εrof approximately 9.5, an ohmic contact capacitance ratio for at least one type of ohmic contact of a device can have a value between 0.05 pF/mm and 0.8 pF/mm. For this example, the ohmic contact capacitance ratio for at least one type of ohmic contact of a device can be less than 0.1 pF/mm in some cases, less than 0.2 pF/mm in some cases, less than 0.4 pF/mm in some cases, and yet less than 0.6 pF/mm in some cases. According to some embodiments, the semiconductor devices comprise at least one contact pad over the substrate, over the III-nitride material region, and over at least one ohmic contact. In some embodiments, the ohmic contacts are relatively small compared to the size of the contact pads. Large contact pads are, in accordance with certain embodiments, beneficial in the operation of the semiconductor devices that include semiconductor structures, as external connections can easily be made to the semiconductor structure through the large contact pads. According to certain embodiments, the contact pads are located over the substrate, over the III-nitride material, and over an electrode (including the electrode's ohmic contact). In some embodiments, the gate contact pad(s) is(are) located over the substrate, over the III-nitride material, and over the gate electrode(s). Referring back toFIG.3D, for example, gate contact pad244is positioned over and in electrical contact with gate electrodes240A,240B,240C,240D,240E, and240F. Gate contact pad244is not visible inFIGS.2A-2D, as the gate contact pad resides behind the plane of the cross-section. According to certain embodiments, the drain contact pad(s) is(are) located over the substrate, over the III-nitride material, and over the drain electrode(s). Referring back toFIG.3E, for example, drain contact pad234is positioned over and in electrical contact with drain electrodes230A,230B,230C,230D,230E, and230F. Drain contact pad234is also illustrated in the cross-sections shown inFIGS.2A-2D. InFIGS.2A-2D, drain contact pad234contacts drain electrode230, and extends laterally beyond interfacial area309of ohmic contact302B. In some embodiments, the source contact pad(s) is(are) located over the substrate, over the III-nitride material, and over the source electrode(s). Referring back toFIG.3F, for example, source contact pad224A is positioned over and in electrical contact with source electrode220A, source contact pad224B is positioned over and in electrical contact with source electrode220B, source contact pad224C is positioned over and in electrical contact with source electrode220C, and source contact pad224D is positioned over an in electrical contact with source electrode220D. Source contact pad224A is also illustrated in the cross-sections shown inFIGS.2A-2D. InFIGS.2A-2D, source contact pad224A contacts source electrode220A and extends laterally beyond interfacial area308of ohmic contact302A. FIGS.3G and3Hinclude top, perspective views of the device once the source, gate, and drain contact pads have been added to the device. To reduce deleterious effects of contact pads above a conductive substrate, areas of the contact pads can be reduced. In this regard, contact-pad area ratios Arcpreferenced to peripheral lengths can be defined for devices of the present embodiments and represented, for example, as follows Arcp=Acp/L(3) where Acprepresents the area of all contact pads of a same type (e.g., all drain contact pads, all anode contact pads) for a device, and L is the gate peripheral length or anode peripheral length for a device as described above. In some implementations, devices formed in accordance with the present embodiments can have a contact-pad area ratio for gate or anode contact pads that is between 15 μm2/μm and 20 μm2/μm. In some cases, the contact-pad area ratio for gate or anode contact pads of a device can be less than 17 μm2/μm according to some embodiments, less than 18 μm2/μm according to some embodiments, less than 19 μm2/μm according to some embodiments, and yet less than 20 μm2/μm according to some embodiments. In some implementations, devices formed in accordance with the present embodiments can have a contact-pad area ratio for drain, source, or cathode contact pads that is between 30 μm2/μm and 50 μm2/μm. In some cases, the contact-pad area ratio for gate or anode contact pads of a device can be less than 35 μm2/μm according to some embodiments, less than 40 μm2/μm according to some embodiments, less than 45 μm2/μm according to some embodiments, and yet less than 50 μm2/μm according to some embodiments. In embodiments, any of the aforementioned contact pads can capacitively couple to a conductive substrate. Accordingly, capacitance of a contact pad can be reduced to ameliorate deleterious effects of such capacitive coupling. A contact-pad capacitance ratio referenced to peripheral length can be defined for contact pads of devices of the present embodiments. Without being bound to any particular theory, a contact-pad capacitance ratio can be expressed as follows Ccp=(1C1+1C2)-1 (4) where C1represents a capacitance component attributed to epitaxial material in a region between the conductive substrate110and dielectric region250, and C2represents a capacitance component attributed to the dielectric region250, for example and referring toFIG.2A. C1and C2can be expressed as follows C1=(ε0εr1Acp)/(t1L) (5) C2=(ε0εr2Acp)/(t2L) where ε0is the permittivity of free space, εr1is the effective relative permittivity of the epitaxial structure between the conductive substrate110and dielectric region250, εr2is the relative permittivity of the dielectric region250, Acpis the area of the contact pad as described above, t1is the thickness of the epitaxial structure between the conductive substrate110and dielectric region250, t2is the thickness of the dielectric region250, and L is the gate peripheral length or anode peripheral length as described above. The area of the contact pad can be the area of a source contact pad, a drain contact pad, a gate contact pad, an anode contact pad, or a cathode contact pad. If there is a plurality of a same type of contact pads in a device (e.g., plural drain contact pads for a transistor), then the area of the contact pad Acpwould be the sum of all areas of the contact pads of the same type when determining the capacitance ratio. If there is a plurality of gates or anodes for a device, then the peripheral length L would be the sum of all gate peripheral lengths or anode peripheral lengths. As examples for an epitaxial structure of the present embodiments that is approximately 4.8 microns thick with εr1of approximately 9.5 and that is covered with at least one layer of dielectric material (e.g., approximately 4 microns of benzocyclobutane (BCB) with εr2of approximately 2.65), a contact-pad capacitance ratio for a gate or anode of a device can have a value between 0.05 pF/mm and 1.0 pF/mm. The contact-pad capacitance ratio for a gate or anode of a device can be less than 0.1 pF/mm in some cases, less than 0.2 pF/mm in some cases, less than 0.4 pF/mm in some cases, less than 0.6 pF/mm in some cases, less than 0.8 pF/mm in some cases, and yet less than 1 pF/mm in some cases. In some implementations, the dielectric region can include additional layers of dielectric material (e.g., a layer of silicon nitride between 0.1 micron and 1 micron thick with εr2of approximately 6.44). As additional examples for an epitaxial structure of the present embodiments that is approximately 4.8 microns thick with εr1of approximately 9.5 and that is covered with at least one layer of dielectric material (e.g., approximately 4 microns of benzocyclobutane (BCB) with εr2of approximately 2.65), a contact-pad capacitance ratio for a drain, source, or cathode of a device can have a value between 0.1 pF/mm and 1.5 pF/mm. The contact-pad capacitance ratio for a drain, source, or cathode of a device can be less than 0.2 pF/mm in some cases, less than 0.4 pF/mm in some cases, less than 0.6 pF/mm in some cases, less than 0.8 pF/mm in some cases, less than 1.0 pF/mm in some cases, and yet less than 1.2 pF/mm in some cases. In some implementations, the dielectric region can include additional layers of dielectric material (e.g., a layer of silicon nitride between 0.1 micron and 1 micron thick with ere of approximately 6.44). According to some embodiments, an active-area capacitance ratio Cacan be defined for a device formed over a conductive substrate as follows Ca=(ε0εrAa)/(tL) (6) where ε0is the permittivity of free space, εris the effective relative permittivity of the epitaxial structure between the conductive substrate110and the devices active area306, Aais the active area of the device as described above (e.g., a sum of active areas for a transistor that comprises multiple source, gate, and drain electrode groups as inFIG.3C), t is the thickness of the epitaxial structure between the conductive substrate110and active area306, and L is the gate peripheral length or anode peripheral length as described above. In some implementations, an active-area capacitance ratio Cafor a device is between 0.05 pF/mm and 0.5 pF/mm. The active-area capacitance ratio Cafor a device can be no greater than 0.2 pF/mm in some embodiments, no greater than 0.3 pF/mm in some embodiments, and yet no greater than 0.4 pF/mm in some embodiments. In certain embodiments, the at least one contact pad defines a contact pad area. The contact pad area of a particular contact pad refers to the area over which that contact pad forms an interface with the underlying material. For example, referring toFIG.3D, gate contact pad244defines contact pad area242, which is the entire black area of contact pad244. InFIG.3E, drain contact pad234defines contact pad area232, which is the entire black area of contact pad234. Referring toFIG.3F, source contact pads224A,224B,224C, and224D define contact pad areas222A,222B,222C, and222D, respectively (which, each, correspond to the entire black areas of contact pads224A-224D). In some embodiments, for at least one contact pad, the ratio of (1) the ohmic contact interfacial area of the electrode connected to that contact pad to (2) the contact pad area of that contact pad is less than 12%. In some cases, the ratio of (1) the ohmic contact interfacial area of the electrode connected to that contact pad to (2) the contact pad area of that contact pad is less than 10%. In some cases, the ratio of (1) the ohmic contact interfacial area of the electrode connected to that contact pad to (2) the contact pad area of that contact pad is less than 15%. In some cases, the ratio of (1) the ohmic contact interfacial area of the electrode connected to that contact pad to (2) the contact pad area of that contact pad is less than 20%. In some cases, the ratio of (1) the ohmic contact interfacial area of the electrode connected to that contact pad to (2) the contact pad area of that contact pad is less than 30%. In certain embodiments, for at least one gate or anode contact pad, the ratio of (1) the Schottky contact interfacial area of the gate or anode electrode(s) connected to the gate or anode contact pad to (2) the contact pad area of the gate or anode contact pad is less than 2.5%. For example, inFIG.3D, gate contact pad244is connected to each of gate electrodes240A,240B,240C,240D,240E, and240F. Thus, to calculate the ratio of the Schottky contact interfacial area to the contact pad area for contact pad244, one would determine the ratio of:(1) the sum of the interfacial areas of the gate (or anode) electrodes240A-240F (which would be determined by summing the interfacial areas of each of the six gate or anode electrodes) to(2) the contact pad area242. According to certain embodiments, this ratio is less than 1.5%. In some cases, this ratio is less than 30%. In some cases, this ratio is less than 20%. In some cases, this ratio is less than 15%. In accordance with certain embodiments, for at least one drain or cathode contact pad, the ratio of (1) the ohmic contact interfacial area of the drain or cathode electrode(s) connected to the drain or cathode contact pad to (2) the contact pad area of the drain or cathode contact pad is less than 12%. For example, referring toFIG.3E, drain contact pad234is connected to each of drain electrodes230A,230B,230C,230D,230E, and230F. Thus, to calculate the ratio of the ohmic contact interfacial area to the contact pad area for contact pad234, one would determine the ratio of:(1) the sum of the interfacial areas of the drain (or cathode) electrodes230A-230F (which would be determined by summing the interfacial areas of each of the six drain electrodes) to(2) the drain or cathode contact pad area232. According to certain embodiments, this ratio is less than 10%. In some cases, this ratio is less than 30%. In some cases, this ratio is less than 20%. In some cases, this ratio is less than 15%. In some embodiments, for at least one source contact pad, the ratio of (1) the ohmic contact interfacial area of the source electrode(s) connected to the source contact pad to (2) the contact pad area of the source contact pad is less than 15%. For example, referring toFIG.3F, source contact pad224A is connected to a single source electrode220A. Thus, to calculate the ratio of the ohmic contact interfacial area to the contact pad area for contact pad224A, one would determine the ratio of:(1) the interfacial area of the source electrodes220A connected to contact pad224A to(2) the source contact pad area222A. According to certain embodiments, this ratio is less than 28%. In some cases, this ratio is less than 30%. In some cases, this ratio is less than 20%. In some cases, this ratio is less than 15%. As another example, inFIG.3F, source contact pad224B is connected to two source electrodes220B and220C. Thus, to calculate the ratio of the ohmic contact interfacial area to the contact pad area for contact pad224B, one would determine the ratio of:(1) the interfacial areas of the two source electrodes220B and220C connected to contact pad224B to(2) the source contact pad area222B. According to certain embodiments, this ratio is less than 13.6%. In some cases, this ratio is less than 30%. In some cases, this ratio is less than 20%. In some cases, this ratio is less than 15%. According to certain embodiments, the device ohmic interfacial area is relatively small compared to the device ohmic contact pad area. As noted above, the device ohmic interfacial area refers to the sum of all of the interfacial areas of the ohmic contacts of that device. In a similar manner, the “device ohmic contact pad area” refers to the sum of all of the areas of contact pads connected to electrodes that establish ohmic contacts of that device. For example, referring back toFIG.3G. The device ohmic interfacial area would be calculated by summing twelve (12) interfacial areas (i.e., the six interfacial areas defined by the six source electrodes220and the six interfacial areas defined by the six drain electrodes230). InFIG.3G, the device ohmic contact pad area would be calculated by summing five (5) contact pad areas (i.e., drain contact pad area232, source contact pad area222A, source contact pad area222B, source contact pad area222C, and source contact pad area222D). In certain embodiments, the ratio of the device ohmic interfacial area to the device ohmic contact pad area is less than 13.6%. In some cases, the ratio of the device ohmic interfacial area to the device ohmic contact pad area is less than 15%. In some cases, the ratio of the device ohmic interfacial area to the device ohmic contact pad area is less than 20%. In some cases, the ratio of the device ohmic interfacial area to the device ohmic contact pad area is less than 30%. According to certain embodiments, the semiconductor devices and semiconductor structures described herein comprise a dielectric region (e.g., a single dielectric layer, a combination of dielectric layers). In certain embodiments, the dielectric region is located over the substrate and over the III-nitride material region. For instance, as shown inFIG.2B, semiconductor device200A comprises dielectric region250located over substrate110and over III-nitride material region120. According to certain embodiments, the dielectric region can be made of any of a variety of suitable dielectric materials. Non-limiting examples of suitable materials from which the dielectric region can be made include silicon dioxide (SiO2), tetraethyl orthosilicate (TEOS), high-k dielectrics or transition metal (TM) oxides, polyimide, polybenzoxazole (PBO), and/or benzocyclobutane (BCB). In some embodiments, the dielectric region of the semiconductor device is thick. For example, referring toFIGS.2A-2D, in some embodiments, dielectric region250can be relatively thick (with the thickness illustrated inFIGS.2A-2Das dimension252). In certain embodiments, the dielectric region has a thickness of at least 1 micrometer, at least 2 micrometers, at least 3 micrometers, at least 5 micrometers, or at least 10 micrometers. In some embodiments, the dielectric region thickness is less than 10 micrometers, less than 5 micrometers, less than 3 micrometers, or less than 2 micrometers. Combinations of these ranges are also possible (e.g., greater than 3 micrometers and less than 10 micrometers, greater than 1 micrometer and less than 5 micrometers). In certain embodiments, at least one of the contact pads is located over the dielectric region. Contact pad(s) located over the dielectric region can, for example, sit on top of the dielectric region. Referring toFIG.2A, for example, semiconductor device200A comprises contact pad244located over substrate110, over III-nitride material region120, and over dielectric region250. In other cases, a contact pad(s) positioned over the dielectric region can be embedded within the dielectride layer. According to certain embodiments, a large contact pad located over a thick dielectric region can lower the amount of RF current displaced through the silicon-containing substrate. In certain embodiments, the dielectric region material has any of variety of suitable dielectric constants. In certain embodiments, the dielectric material has a dielectric constant of less than 4, less than 3, or less than 2. In certain embodiments, the dielectric material has a dielectric constant of greater than 1, greater than 2, or greater than 3. Combinations of these ranges are also possible (e.g., greater than 1 and less than 4, greater than 2 and less than 3). In some embodiments, the dielectric material has a dielectric constant of 2.65. According to certain embodiments, the semiconductor devices described herein comprise an electronically conductive material located within and/or over the III-nitride material region. The electrically conductive material (e.g., a conductive via) can be arranged such that it establishes an electrical connection between top side electronic structures (e.g., one or more contact pads) and the electronically conductive substrate by passing vertically through the III-nitride material region. In some implementations, the electrically conductive substrate can be held at ground potential (or some other reference potential) and provide a backside ground at the location of integrated circuit components. According to certain embodiments, the use of electronically conductive materials located within and/or over the III-nitride material region is advantageous as grounding can be achieved in such devices without the need for an external wire(s) and/or patterning other interconnects on the substrate to provide ground. The backside ground can also provide, in accordance with certain embodiments, improved gain. FIG.4is a cross-sectional schematic illustration of a semiconductor device comprising an electronically conductive material coupled to a contact pad and a substrate, according to certain embodiments. As shown inFIG.4, semiconductor structure600A comprises substrate110and III-nitride material region120over substrate110. Also shown inFIG.4is electronically conductive material610, which has been deposited within cavity612formed in the device. In some embodiments, the electronically conductive material is electrically coupled to the electronically conductive portion of the substrate through the thickness of the III-nitride material region. For example, referring toFIG.4, electronically conductive material610is electrically coupled to electronically conductive portion of substrate110through the thickness of the III-nitride material region120by way of cavity612. Cavity612can function, for example, as a front-side (or top-side) via. In certain embodiments, cavity612is formed (e.g., etched) into the layers of the semiconductor structure (such as III-nitride material region120), and electronically conductive material610is deposited or otherwise formed in cavity612such that it is coupled to the electronically conductive portion of the substrate through the thickness of the III-nitride material region. In some embodiments, the perimeter (e.g., sidewalls and base) of the cavity or via is lined with a conductive metal, and in other embodiments a metal or conductive plug is formed by filling the cavity or via. According to certain embodiments, the semiconductor structure can be grounded to the electronically conductive substrate through electronically conductive material610without using an external connection from the drain electrode to an external ground. In certain embodiments, the electronically conductive material can make an electrical connection from the source electrode to an electronically conductive portion of the substrate. For example, inFIG.4, electronically conductive material makes an electrical connection from source electrode220to substrate110by connecting source contact pad224(which is electrically coupled to source electrode220) to substrate110. As described elsewhere herein, the use of an electronically conductive substrate can lower thermal runaway within the semiconductor structure. In addition, the use of thick III-nitride materials, small ohmic contacts, and/or thick dielectric regions can reduce capacitive coupling. Such improvements can, in accordance with certain embodiments, result in performance enhancements with high operational frequencies and/or high input frequencies are employed. In certain embodiments, operating semiconductor structures with electronically conductive structures at high operational frequencies and high input frequencies results in generated RF signals with a reduction in the dissipated current throughout the electronically conductive substrate. As a result, and according to certain embodiments, the devices can be operated at high frequencies at higher temperatures with less device degradation, which will be described herein in further detail. In some embodiments, the semiconductor structures described herein are capable of operation at a high operational frequency. As used herein, operational frequency can be understood as the frequency of a signal that is input to a device having a semiconductor structure of the present embodiments, and operated on by the device (e.g., amplified, switched, modulated, etc.) to produce an output signal. In some embodiments, the semiconductor structures described herein are capable of receiving a high input frequency without significant attenuation (e.g., less than 6 dB of power attenuation between input and output of a device formed using the semiconductor structures described herein). As used herein, input frequency can be understood as the frequency of the applied signal to the gate of a transistor or anode of a diode. High operational frequencies can be in the radio frequency (RF) range and have a value between 50 MHz and 50 GHz. In some embodiments, certain of the devices described herein are configured to maintain high operational frequencies over a relatively large number of operation cycles. For example, in some embodiments, devices and components formed using the semiconductor structure can maintain an operational frequency of greater than 50 MHz (or greater than 60 MHz, greater than 70 MHz, greater than 80 MHz, greater than 90 MHz, or greater than 100 MHz, and/or, in some embodiments, up to 50 GHz) for at least 10 seconds, at least 100 seconds, at least 10 minutes, at least 100 minutes, at least 10 hours, at least 100 hours, or more (and/or, in some embodiments, up to 107hours). According to certain embodiments, devices and components formed using the semiconductor structures have an operational frequency of greater than 50 MHz. In certain embodiments, the operational frequency of the devices or components is greater than 60 MHz, greater than 70 MHz, greater than 80 MHz, greater than 90 MHz, or greater than 100 MHz. According to certain embodiments, the operational frequency is less than 110 MHz, less than 100 MHz, less than 90 MHz, less than 80 MHz, less than 70 MHz, or less than 60 MHz. Combinations of these ranges are also possible (e.g., greater than 50 MHz and less than 80 MHz, greater than 70 MHz and less than 100 MHz). In certain embodiments, devices or components comprising the semiconductor structures have an input frequency of greater than 800 MHz. The input frequency can be less than 20 GHz in some cases, can be less than 10 GHz in some cases, less than 7 GHz in some cases, less than 4 GHz in some cases, less than 2 GHz in some cases, and yet less than 1 GHz in some cases. Combinations of these ranges are also possible (e.g., greater than 800 MHz and less than 1 GHz, greater than 800 MHz and less than 4 GHz). According to certain embodiments, deviced formed using certain semiconductor structures described herein have high operating efficiency at elevated temperatures (e.g., substrate lattice temperatures). For example, transistors having semiconductor structures described herein can operate with high drain efficiencies (DE) or power-added efficiencies (PAE). Drain efficiency as used herein is a ratio of RF power output from a device to the DC power input to the device. Power-added efficiency as used herein is a ratio of a net RF power output from a device (RF power out minus RF power input) to the DC power input to the device. Without wishing to be bound by any theory, it is believed that relatively high efficiencies can be achieved, at least in part, due to the use of electronically conductive substrates, thick-III nitride layers, small ohmic contact areas, and/or a backside ground plane, which can result in reduced capacitive coupling and/or leakage current to the substrate. In certain embodiments, a device comprising a semiconductor structure of the present embodiments is configured such that when the device's conductive substrate is at 25° C. the device exhibits a power-added efficiency between 50% and 60% and that a PAE of greater than 50% can be maintained for an increases in substrate temperature to as high as 100° C. According to some embodiments, a device is configured such that when the device's conductive substrate is at 25° C. the device exhibits a PAE between 50% and 60% and that a PAE of greater than 50% can be maintained for an increase in substrate temperature to as high as 135° C. According to some embodiments, a device is configured such that when the device's conductive substrate is at 25° C. the device exhibits a PAE between 50% and 60% and that a PAE of greater than 45% can be maintained for an increase in substrate temperature to as high as 200° C. In some embodiments, a device is configured such that when the device's conductive substrate is at 25° C. the device exhibits a PAE of up to 55%, up to 60%, up to 65%, up to 70%, up to 75%, up to 80%, up to 85%, or more. According to some embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of no greater than 5% when the temperature of the device's conductive substrate is increased in temperature from 25° C. to 100° C. According to some embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of no greater than 5% when the temperature of the device's conductive substrate is increased in temperature from 25° C. to 130° C. According to some embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of no greater than 10% when the temperature of the device's conductive substrate is increased in temperature from 25° C. to 130° C. According to some embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of no greater than 10% when the temperature of the device's conductive substrate is increased in temperature from 25° C. to 200° C. In some embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of up to 1%, up to 2%, up to 3%, up to 4%, or more when the substrate is increased in temperature from 25° C. to 105° C. According to certain embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of as little as 4%, as little as 3%, as little as 2%, as little as 1%, or less when the substrate is increased in temperature from 25° C. to 105° C. Combinations of these ranges are also possible (e.g., as little as 2% and up to 4%, as little as 3% and up to 5%). According to certain embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of up to 1%, up to 3%, up to 5%, up to 7%, up to 9%, or more when the substrate is increased in temperature from 25° C. to 125° C. According to certain embodiments, a device comprising a semiconductor structure of the present embodiments can exhibit a drop in PAE of as little as 9%, as little as 7%, as little as 5%, as little as 3%, or less when the substrate is increased in temperature from 25° C. to 125° C. Combinations of these ranges are also possible (e.g., as little as 3% and up to 10%, as little as 5% and up to 7%). According to certain embodiments, the semiconductor structures described herein can be used in RF signal handling (e.g., wireless communications), radar applications, RF switching, and power applications. In certain embodiments, the semiconductor structures used for such applications comprise GaN on a conductive silicon substrate. Various of the devices described herein may be made using conventional semiconductor processing techniques. Such processing techniques can involve, for example, growing layers on the substrate in a process chamber under vacuum conditions. Some methods may include cleaning the substrate surface prior to growing overlying layers and, typically, before introduction into the process chamber. The substrate surface may be cleaned to remove residual dopant species that may diffuse into the substrate during processing. For example, the substrate may be cleaned by wet chemical cleaning agents such as buffered oxide etch (BOE), hydro-fluoric acid (HF), RCA clean (which is a commercial, proprietary silicon surface cleaning agent), etc. Substrates may also be cleaned by a combination of such agents. The surface of the substrate may be cleaned with organic solvents such as acetone, methanol, trichloroethylene, isopropyl alcohol, etc., for example, to rid a surface of organic contamination. In some embodiments, methods may include controlling the residual (e.g., residual reaction by-products) amounts of dopant in the process chamber. For example, the amount of residual dopant may be reduced by purging the chamber with a gas (e.g., NH3) while heating to an elevated temperature, prior to introducing the substrate into the chamber. Purging has been found to minimize accumulation of reaction-by-products on reaction chamber walls and components. In certain embodiments in which a diffusion barrier layer is present, the diffusion barrier layer may be formed in-situ with overlying layers (e.g., the III-nitride material region) of the structure. That is, the diffusion barrier layer may be formed during the same deposition step as the III-nitride material region (e.g., including the optional III-nitride material nucleation layer, the optional III-nitride material transition layer, the optional III-nitride material buffer layer, and/or the III-nitride material device region). The III-nitride material region may be formed using known growth techniques. In some embodiments, the optional III-nitride nucleation layer, the optional III-nitride transition layer, the optional III-nitride buffer layer, and/or the III-nitride device region are grown using a metalorganic chemical vapor deposition (MOCVD) process. It should be understood that other suitable techniques known in the art may also be utilized to deposit these layers including molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), and the like. In certain embodiments, more than one growth technique may be used to grow different III-nitride material layers. For example, in one set of embodiments, MBE could be used to grow the nucleation layer, and the remaining III-nitride material layers may be formed using MOCVD. Other combinations are also possible. Generally, the MOCVD process involves introducing different reactive source gases (e.g., Al source gases, Ga source gases, N source gases) into the process chamber and providing conditions which promote a reaction between the gases to form a layer. The reaction proceeds until a layer of desired thickness is achieved. The composition of the layer may be controlled, as described further below, by several factors including gas composition, gas concentration, and the reaction conditions (e.g., temperature and pressure). Examples of suitable source gases for MOCVD growth of the optional III-nitride material nucleation layer, the optional III-nitride material transition layer, the optional III-nitride material buffer layer, and/or the III-nitride material device region include trimethylaluminum (TMA) or triethylaluminum (TEA) as sources of aluminum; trimethylindium (TMI) or triethylindium (TEI) as sources of indium; trimethylgallium (TMG) or trimethylgallium (TEG) as sources of gallium; and ammonia (NH3) as a source of nitrogen. The particular source gas used depends upon the desired composition of the layers. For example, an aluminum source (e.g., TMA or TEA), a gallium source (TMG or TEG), and a nitrogen source are used to deposit films having an AlxGa1−xN composition. The flow rates of the source gases, the ratios of the source gases, and the absolute concentrations of the source gases may be controlled to provide layers (e.g., transition layers and gallium nitride material regions) having a desired composition. For the growth of AlxGa1−xN layers, typical TMA flow rates are between about 5 μmol/min and about 50 μmol/min with a flow rate of about 20 μmol/min being preferred in some cases; typical TMG flow rates are between about 5 μmol/min and 250 μmol/min, with a flow rate of 115 μmol/min being preferred in some cases; and the flow rate of ammonia is typically between about 3 slpm to about 10 slpm. According to certain embodiments, relatively high flow rates (and also higher gas velocities) can be used, which have been found to be particularly effective in minimizing accumulation of dopants. According to certain embodiments, the reaction temperatures are generally between about 900° C. and about 1200° C. In some embodiments, the process pressures are between about 1 Torr and about 760 Torr. It is to be understood that the process conditions, and in particular the flow rate, are highly dependent on the process system configuration. Typically, smaller throughput systems require less flow than larger throughput systems. When forming a compositionally-graded layer (e.g., a compositionally graded transition layer, which might be formed, for example, within transition layer170), process parameters may be suitably adjusted to control the compositional grading. The composition may be graded by changing the process conditions to favor the growth of particular compositions. For example, to increase incorporation of gallium in the transition layer thereby increasing the gallium concentration, the flow rate and/or the concentration of the gallium source (e.g., TMG or TEG) may be increased. Similarly, to increase incorporation of aluminum into the transition layer thereby increasing the aluminum concentration, the flow rate and/or the concentration of the aluminum source (e.g., TMA or TEA) may be increased. The manner in which the flow rate and/or the concentration of the source is increased (or decreased) can control the manner in which the composition is graded. In other embodiments, the temperature and/or pressure is adjusted to favor the growth of a particular compound. Growth temperatures and pressures favoring the incorporation of gallium into the transition layer differ from the growth temperatures and pressures favoring the incorporation of aluminum into the transition layer. Thus, the composition may be graded by suitably adjusting temperature and pressure. When depositing a layer having a constant composition (e.g., a transition layer, a gallium nitride material layer, etc.), however, the process parameters can be maintained constant so as to provide a layer having a constant composition. When III-nitride material regions (e.g., gallium nitride material regions) include more than one material layer (e.g., more than one gallium nitride material layer) having different respective compositions, the process parameters may be changed at the appropriate time to change the composition of the layer being formed. It should be understood that all of the layers/regions on the substrate (e.g., the optional III-nitride material nucleation layer, the optional III-nitride material transition layer, the optional III-nitride material buffer layer, and/or the III-nitride material device region) may be grown in the same process, or respective layers/regions may be grown separately. The processes described herein have been described as involving growing the layers/regions (e.g., the optional III-nitride material nucleation layer, the optional III-nitride material transition layer, the optional III-nitride material buffer layer, and/or the III-nitride material device region) in vertical growth processes. That is, these layers/regions have been described as being grown in a vertical direction with respect to underlying layers/regions (including the substrate). However, in other embodiments of the invention (not shown), it is possible to grow at least a portion of the layer(s) of the III-nitride material region (e.g., gallium nitride material layer(s)) using a lateral epitaxial overgrowth (LEO) technique, for example, as described in U.S. Pat. No. 6,051,849; or a pendeoepitaxial technique that involves growing sidewalls of gallium nitride material posts into trenches until growth from adjacent sidewalls coalesces to form a gallium nitride material region, for example, as described in U.S. Pat. No. 6,265,289. U.S. Pat. No. 7,071,498 entitled “Gallium Nitride Material Devices Including an Electrode-Defining Layer and Methods of Forming the Same,” filed Dec. 17, 2003, and issued Jul. 4, 2006, which is incorporated herein by reference above, further describes techniques used to grow other layers and features shown in the various embodiments described herein. It should also be understood that other processes may be used to form structures and devices of the present invention as known to those of ordinary skill in the art. Certain of the layers and/or regions are referred to as being “formed on,” “formed over,” “formed directly on,” “formed directly over,” and/or “covering” another layer or region (e.g., the substrate). It should be understood that such phrases include situations in which a top surface of an underlying region or layer (e.g., substrate) is converted to the layer or region that is being formed. Such phrases also refer to situations in which new layers are formed by depositing the new, separate layer on the top surface of the underlying layer and/or region (e.g., a substrate). As noted above, the term “region” may refer to one layer or may refer to multiple layers. It should also be understood that, wherever a single layer is described, the single layer may be replaced, according to certain embodiments, with multiple layers. For example, in certain instances, single layers described herein can be replaced with multiple layers that perform a similar function. The following examples are intended to illustrate certain embodiments of the present invention, but do not exemplify the full scope of the invention. EXAMPLE 1 Example results from fabricated devices and simulations are described in this section.FIG.5Ashows measured power-added efficiency (PAE) at 2.5 GHz for two GaN-on-silicon high-electron mobiltiy transistors (HEMTs) versus measured temperature of the silicon substrate. One GaN HEMT transistor was manufactured on a 625 μm thick highly conductive (0.02 Ω-cm i.e. conductive) silicon substrate and the other was manufactured on a 625 μm thick highly resistive (10,000 Ω-cm i.e. float-zone) silicon substrate. The transistor using a highly conductive substrate (upper trace) shows improved power added efficiency at all temperatures and particularly at elevated substrate temperatures compared to the HEMT formed on the highly resistive substrate. FIG.5Bshows measured output power density at 2.5 GHz as a function of substrate temperature for the same two GaN-on-silicon HEMT transistors that were used to obtain the results inFIG.5A. The transistor formed on a highly conductive substrate (upper trace) shows improved output power density at all temperatures and particularly at elevated substrate temperatures compared to the transistor formed on the highly resistive substrate. FIG.6plots calculated power dissipation in a 50 μm thick silicon substrate as a function of the substrate's bulk resistivity for five different applied RF signals. The RF signals (2.5 GHz sinusoidal), ranging from 10 volts peak-to-peak to 50 volts peak-to-peak are capacitively coupled (over a 1 mm×1 mm area) to the silicon substrate through a 400-nm-thick silicon-nitride layer and 1.6-μm-thick GaN dielectric layer on top of the silicon substrate. The bottom of the silicon substrate is at ground potential. To minimize power dissipation in the silicon substrate, either a highly conductive or highly resistive substrate can be used (corresponding to either side of the bell curves). However, the change in bulk resistivity of highly resistive silicon substrates at elevated temperatures (˜200° C.) tends towards the peak of the bell curves inFIG.6, whereas the change in bulk resistivity of highly conductive silicon substrates at elevated temperatures tends away from the peak of the bell curves. Therefore, highly conductive silicon substrates dissipate less power at elevated substrate temperatures compared to highly resistive ones and are preferred for GaN-on-silicon HEMTs, diodes, and other semiconductor devices operating at elevated temperatures. FIG.7plots simulated power dissipation in a silicon substrate for a 1 mm gate peripheral length GaN-on-silicon HEMT transistor versus the silicon substrate temperature for five 2.5 GHz sinusoidal RF signals (ranging from 10 volts to 50 volts peak-to-peak) that are applied between the transistor's drain and source contacts. The simulation uses a silicon substrate thickness of 50 μm (10,000 Ω-cm bulk resistivity), gate-to-gate pitch of 65 μm, and total GaN layer thickness of 1.6 μm for the transistor to calculate capacitive coupling to the substrate. Also plotted on the same graph are simulation results at 50 volts peak-to-peak for a same structure that instead has a highly conductive substrate (0.015 Ω-cm bulk resistivity). As can be seen, for a 50 volt signal, the power dissipated in the highly resistive silicon at 180° C. substrate temperature is about 1.0 Watt/mm and essentially zero for the highly conductive silicon substrate. In embodiments, a GaN-on-silicon HEMT transistor can output about 7.0 Watts/mm (gate peripheral length) RF output power at 2.5 GHz with a drain-to-source bias VDSof 50 volts. Accordingly, 1.0 Watt/mm dissipation into the substrate will dramatically degrade both output power capability of the transistor (e.g., reduced to about 6.0 Watts/mm) as well as degrade device efficiency and increase the transistor junction temperature due to substrate heating. FIG.8plots calculated active-area-to-substrate capacitance of a 1.0 mm gate peripheral length GaN-on-silicon HEMT transistor formed on a highly conductive silicon substrate as a function of GaN epitaxy thickness in the semiconductor structure. For this simulation the thickness of the epitaxial region is measured from the location of the 2-dimensional electron gas (2DEG) down to the surface of the conductive substrate. The simulation results represent a lower bound to the device's output capacitance that can be achieved for a GaN on highly conductive silicon substrate HEMT transistor, since it does not include capacitances associated with interconnects and contact pads, for example. The plotted capacitance values can influence maximum transistor bandwidth. The calculation assumes reduced-size ohmic contacts (e.g., 4.5 μm wide) and a gate-to-drain ohmic contact spacing of 5.0 μm (which can be typical for transistors configured for 50-volt operation). The results ofFIG.8indicate that a thicker GaN epitaxy is desired to minimize the active area capacitance and capacitive coupling to a highly conductive silicon substrate (which may be held at a reference potential, such as ground potential). While several embodiments of the present invention have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the functions and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the present invention. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings of the present invention is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the invention may be practiced otherwise than as specifically described and claimed. The present invention is directed to each individual feature, system, article, material, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, and/or methods, if such features, systems, articles, materials, and/or methods are not mutually inconsistent, is included within the scope of the present invention. In cases where the present specification and a document incorporated by reference include conflicting and/or inconsistent disclosure, the present specification shall control. If two or more documents incorporated by reference include conflicting and/or inconsistent disclosure with respect to each other, then the document having the later effective date shall control. All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms. The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.” The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified unless clearly indicated to the contrary. Thus, as a non-limiting example, a reference to “A and/or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A without B (optionally including elements other than B); in another embodiment, to B without A (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc. As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law. As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc. In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03. | 156,399 |
11942519 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “over”, “above”, “upper”, “bottom”, “top” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “under” other elements or features would then be oriented “above” and/or “over” the other elements or features. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first”, “second”, and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments. As disclosed herein, the term “about” or “substantial” generally means within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages disclosed herein should be understood as modified in all instances by the term “about” or “substantial”. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. In the present disclosure, a “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N), phosphorous (P), arsenic (As), or antimony (Sb). Furthermore, the group III-V semiconductor may refer to, but not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), AlGaAs, InAlAs, InGaAs, or the like, or the combination thereof. Besides, based on different requirements, group III-V semiconductor may contain dopants to become semiconductor with specific conductivity type, such as n-type or p-type. Although the disclosure is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present disclosure, certain details have been left out in order to not obscure the inventive aspects of the disclosure. The details left out are within the knowledge of a person having ordinary skill in the art. The present disclosure is directed to a semiconductor structure and a high electron mobility transistor (HEMT) including the semiconductor structure, which may be used as power switching transistors for voltage converter applications. Compared to silicon power transistors, group III-V semiconductor HEMTs (III-V HEMTs) feature low on-state resistances and low switching losses due to wide band gap properties. FIG.1is a schematic cross-sectional diagram of a HEMT according to one embodiment of the present disclosure. Referring toFIG.1, according to one embodiment, a HEMT100such as an enhancement mode HEMT is disposed on a substrate102. In addition, a nucleation layer104, a superlattice (SL) structure106, a composition gradient layer110, an electrical isolation layer112, a channel layer114, a barrier layer116, a doped semiconductor cap layer118, and a passivation layer128are disposed on the substrate102in sequence. In an embodiment, the superlattice structure106may include two or more different superlattice stacks, for example, a first superlattice stack106-1is disposed on a second superlattice stack106-2. Each superlattice stack may include a plurality of pairs of superlattice layers, and the superlattice layers may be stacked in a periodic alternate sequence. Each superlattice layer may be composed of two or more materials, and the thickness of each superlattice layer is about several nanometers (nm) to tens of nanometers. The first superlattice stack106-1and the second superlattice stack106-2may have different materials, different composition ratios, or different periodic alternate stacking modes. In another embodiment, the superlattice structure106may be a single superlattice stack, for example, the first superlattice stack106-1. Moreover, the HEMT100further includes a gate electrode126, a source electrode122, and a drain electrode124. The gate electrode126is disposed on the doped semiconductor cap layer118and passes through the passivation layer128. The source electrode122and the drain electrode124are disposed on two opposite sides of the gate electrode126respectively. According to some embodiments, the source electrode122and the drain electrode124may extend downward from the passivation layer128to the barrier layer116or the channel layer114, and are separated from the electrical isolation layer112by a vertical distance. In addition, an isolation region120is disposed to surround the source electrode122and the drain electrode124to isolate the adjacent HEMTs from each other. The isolation region120passes through the barrier layer116into the channel layer114, and the bottom of the isolation region120is lower than the bottoms of the source electrode122and the drain electrode124, so that the isolation region120is closer to the electrical isolation layer112than the source electrode122and the drain electrode124are to achieve a good electrical isolation. However, in other embodiments, the isolation region120may extend to other layers according to actual requirements to achieve electrical isolation. According to one embodiment of the present disclosure, the channel layer114may include one or more group III-V semiconductor layers. The composition of the group III-V semiconductor layer may be GaN, AlGaN, InGaN, or InAlGaN, but not limited thereto. In addition, the channel layer114may be one or more group III-V semiconductor layers that are undoped or doped. The doped channel layer114is, for example, a p-type group III-V semiconductor layer. For the p-type group III-V semiconductor layer, the dopant may be carbon (C), iron (Fe), magnesium (Mg) or zinc (Zn), but not limited thereto. The barrier layer116may include one or more group III-V semiconductor layers, and the composition of the barrier layer116is different from the group III-V semiconductor of the channel layer114. For example, the barrier layer116may include AlN, AlzGa(1-z)N (0<z<1), or a combination thereof. In one embodiment, the channel layer114may be an undoped GaN layer, and the barrier layer116may be an undoped or an intrinsic n-type AlGaN layer. Since there is a discontinuous energy gap between the channel layer114and the barrier layer116, by stacking the channel layer114and the barrier layer116on each other, electrons will be gathered in the hetero-junction between the channel layer114and the barrier layer116due to the piezoelectric effect. Therefore, a thin layer with high electron mobility, i.e., a two-dimensional electron gas (2-DEG) region130is generated. For normally off devices, when no voltage is applied to the gate electrode126, the area covered by the doped semiconductor cap layer118will not form 2-DEG, which may be regarded as a 2-DEG cut-off region, and there is no conduction between the source electrode122and the drain electrode124at this time. When a positive voltage is applied to the gate electrode126, the area covered by the doped semiconductor cap layer118will form 2-DEG, so that the 2-DEG region130between the source electrode122and the drain electrode124becomes continuous, and there is conduction between the source electrode122and the drain electrode124. FIG.2is a schematic enlarged cross-sectional diagram of a first superlattice stack, a tensile stress layer, a composition gradient layer, and an electrical isolation layer of a HEMT according to another embodiment of the present disclosure. The difference between the embodiments ofFIG.2andFIG.1is that there is a tensile stress layer108disposed between a first superlattice stack106-1and a composition gradient layer110ofFIG.2. As shown inFIG.2, according to an embodiment, the first superlattice stack106-1of the HEMT100may be composed of a plurality of pairs of first superlattice layers106A and second superlattice layers106B stacked in pairs. AlthoughFIG.2only shows four pairs of stacked superlattice layers, according to other embodiments of the present disclosure, the first superlattice stack106-1may be composed of more pairs of stacked superlattice layers, for example, the first superlattice stack106-1may be composed of more than 100 pairs of stacked superlattice layers. In one embodiment, the first superlattice layer106A has tensile stress, the second superlattice layer106B has compressive stress, and the second superlattice layer106B is stacked on the first superlattice layer106A. In other words, the first superlattice layer106A generates tensile stress on the adjacent second superlattice layer106B, and the second superlattice layer106B generates compressive stress on the adjacent first superlattice layer106A. By adjusting the thickness of each layer of the first superlattice layers106A and the second superlattice layers106B, a 2-DEG150and a 2-DHG140are paired with each other in each of the second superlattice layers106B other than the uppermost second superlattice layer106B, thereby offsetting the effects of 2-DEG layer and 2-DHG layer by each other. In addition, according to an embodiment of the present disclosure, a tensile stress layer108is disposed on the uppermost second superlattice layer106B, so that a 2-DEG is generated in the uppermost second superlattice layer106B to offset the 2-DHG in the upper second superlattice layer106B. Accordingly, a 2-DHG layer that is not paired with 2-DEG is not generated in the uppermost second superlattice layer106B, thereby preventing the generation of lateral current transmission paths in the HEMTs. Therefore, leakage current between the adjacent HEMTs is avoided. In addition, according to an embodiment of the present disclosure, a composition gradient layer110is disposed between the electrical isolation layer112and the first superlattice stack106-1of the superlattice structure106, and the composition gradient layer110is disposed on the tensile stress layer108. The composition gradient layer110may be used to eliminate the compressive stress of the electrical isolation layer112to the tensile stress layer108. According to an embodiment of the present disclosure, the compositions of the superlattice structure106, the tensile stress layer108, and the composition gradient layer110include a same group III element. The atomic percentage of the same group III element in the composition gradient layer110is gradually decreased in the direction from the superlattice structure106to the electrical isolation layer112, thereby preventing the electrical isolation layer112from generating compressive stress. Therefore, 2-DHG will not be generated at the interface between the electrical isolation layer112and the composition gradient layer110. Accordingly, there is no 2-DHG layer generated on the bottom surface of the electrical isolation layer112, thereby preventing the generation of lateral current transmission paths in the HEMTS and avoiding leakage current between the adjacent HEMTs. Furthermore, according to an embodiment of the present disclosure, through adjusting the components of the composition gradient layer110, the bottom of the composition gradient layer110will have tensile stress, thereby generating tensile stress on the uppermost second superlattice layer106B, and producing 2-DEG in the uppermost second superlattice layer106B to offset the 2-DHG in the uppermost second superlattice layer106B. Therefore, even if the tensile stress layer108is not disposed, the degree of leakage current between the adjacent HEMTs is also reduced. Moreover, in addition to avoiding leakage current between the adjacent HEMTs, the embodiments of the present disclosure provide a good lattice matching between the stacked layers of the HEMT due to the compositions of the composition gradient layer110, the tensile stress layer108and the superlattice structure106. Accordingly, the embodiments of the present disclosure avoid the generation of stress in the HEMT's stacked layers, thereby avoiding the polarization effect to be generated in the HEMTs. Therefore, various leakage currents of the HEMTs are reduced according to the embodiments of the present disclosure, and the electrical performances of the HEMTs are also improved. According to an embodiment of the present disclosure, the composition of the composition gradient layer110may be a ternary group III-V semiconductor, such as aluminum gallium nitride (AlxGa(1-x)N), wherein 0.1<x<0.9, and the value of x is gradually decreased in the direction from the superlattice structure106to the electrical isolation layer112, i.e., in the depth direction, the atomic percentage of the same group III element such as aluminum (Al) in the composition gradient layer110is gradually decreased from bottom to top. The atomic percentage of another group III element such as gallium (Ga) in the composition gradient layer110is gradually increased from bottom to top. The electrical isolation layer112also includes the aforementioned another group III element such as gallium (Ga). In one embodiment, the composition of the tensile stress layer108may be a binary group III-V semiconductor, such as aluminum nitride (AlN). According to an embodiment, the average atomic concentration of the same group III element such as aluminum (Al) in the tensile stress layer108is higher than the average atomic concentration of the same group III element such as aluminum (Al) in the composition gradient layer110. Moreover, in one embodiment, the thickness of the composition gradient layer110may be 0.5% to 5% of the thickness of the electrical isolation layer112. The thickness of the tensile stress layer108may be 0.2% to 2% of the thickness of the electrical isolation layer112. It should be noted that the thickness of the composition gradient layer110and the thickness of the tensile stress layer108must be greater than the thickness of each superlattice layer, for example, greater than the thickness of the first superlattice layer106A or the thickness of the second superlattice layer106B. When the composition gradient layer110and the tensile stress layer108are in the thickness range mentioned above, they are able to produce or eliminate the stress on the interface. According to an embodiment of the present disclosure, the composition gradient layer110may be doped with a dopant. The dopant may be carbon or iron, thereby increasing the resistivity of the composition gradient layer110. According to an embodiment of the present disclosure, while comparing the first superlattice layer106A and the second superlattice layer106B, the composition of the first superlattice layer106A, for example, aluminum nitride (AlN), has a smaller lattice constant and a wider energy gap, and the composition of the second superlattice layer106B, for example, aluminum gallium nitride (AlyGa(1-y)N, wherein 0.05<y<0.3), has a larger lattice constant and a narrower energy gap. The average atomic concentration of the same group III element such as aluminum (Al) in the composition gradient layer110is higher than the average atomic concentration of the same group III element such as aluminum (Al) in the second superlattice layers106B. According to an embodiment, the atomic percentages of aluminum (Al) in each second superlattice layer106B in the first superlattice stack106-1may be different from each other. In other words, the atomic percentage of gallium (Ga) in each second superlattice layer106B may also be different from each other. For example, the atomic percentage of aluminum (Al) in each second superlattice layer106B may be varied with each layer, such as being decreased from the lower layer to the upper layer, so as to reduce the stress of the first superlattice stack106-1. In addition, according to an embodiment, the first superlattice layers106A and the second superlattice layers106B of the first superlattice stack106-1may be doped with a dopant. The dopant may be carbon or iron, thereby increasing the resistivity of the first superlattice stack106-1. In addition, according to an embodiment of the present disclosure, as shown inFIG.1, the superlattice structure106may further include a second superlattice stack106-2disposed under the first superlattice stack106-1. The second superlattice stack106-2is similar to the first superlattice stack106-1as shown inFIG.2. The second superlattice stack106-2may be composed of a plurality of pairs of third superlattice layers and fourth superlattice layers that are stacked in pairs, where the third superlattice layer has tensile stress, the fourth superlattice layer has compressive stress, and the fourth superlattice layer is stacked on the third superlattice layer. Through adjusting the thickness of each layer of the third superlattice layers and the fourth superlattice layers, there is no unpaired 2-DEG layer and 2-DHG layer generated in the second superlattice stack106-2. Moreover, in one embodiment, the composition of the third superlattice layer is, for example, aluminum nitride (AlN), and the composition of the fourth superlattice layer is, for example, aluminum gallium nitride (AlwGa(1-w)N, wherein 0.1<w<0.5). The average atomic concentration of aluminum (Al) in the second superlattice stack106-2is higher than the average atomic concentration of aluminum (Al) in the first superlattice stack106-1. In one embodiment, the atomic percentage of aluminum (Al) in each fourth superlattice layer may be different from each other. In other words, the atomic percentage of gallium (Ga) in each fourth superlattice layer may also be different from each other. For example, the atomic percentage of aluminum (Al) in each fourth superlattice layer may be varied with each layer, such as being gradually decreased from the lower layer to the upper layer, so as to reduce the stress of the second superlattice stack106-2. In addition, according to an embodiment, the third superlattice layers and the fourth superlattice layers of the second superlattice stack106-2may be doped with a dopant. The dopant may be carbon or iron, thereby increasing the resistivity of the second superlattice stack106-2. According to an embodiment, the average atomic concentration of the same group III element such as aluminum (Al) in the composition gradient layer110is higher than the average atomic concentration of the same group III element such as aluminum (Al) in the fourth superlattice layers. Furthermore, according to an embodiment of the present disclosure, the average atomic concentration of the same group III element such as aluminum (Al) in the composition gradient layer110is lower than the average atomic concentration of the same group III element such as aluminum (Al) in the overall superlattice structure106. In one embodiment, the thickness of the tensile stress layer108is greater than the thickness of each superlattice layer in the superlattice structure106, for example, greater than the thickness of the first superlattice layer106A, and greater than the thickness of the second superlattice layer106B of the first superlattice stack106-1. In addition, the thickness of the tensile stress layer108is also greater than the thickness of the third superlattice layer, and greater than the thickness of the fourth superlattice layer of the second superlattice stack106-2. According to an embodiment of the present disclosure, the composition of the electrical isolation layer112may be a doped or undoped binary group III-V semiconductor, such as carbon-doped gallium nitride (c-GaN). The concentration of the carbon dopant in the electrical isolation layer112is gradually increased in the direction from the composition gradient layer110to the channel layer114. In other words, in the depth direction, the concentration of the carbon dopant in the electrical isolation layer112is gradually increased from bottom to top, so as to prevent the carbon dopant from accumulating at the interface between the electrical isolation layer112and the composition gradient layer110. Accordingly, the surface of the electrical isolation layer112closer to the channel layer114has a higher resistance to provide a better electrical isolation. FIG.3shows a concentration profile of the atomic percentage of the same group III element such as aluminum (Al) varying with different positions in the depth direction in the composition gradient layer, the tensile stress layer and the uppermost second superlattice layer of a HEMT according to an embodiment of the present disclosure. The horizontal axis ofFIG.3is the position in the depth direction of the composition gradient layer110, the tensile stress layer108, and the uppermost second superlattice layer106B. The vertical axis ofFIG.3is the atomic percentage of aluminum (Al). According to an embodiment, as shown inFIG.3, the aluminum (Al) atomic percentage of the uppermost second superlattice layer106B is approximately at the value C3, and the highest aluminum (Al) atomic percentage of the tensile stress layer108is at the value C2. The aluminum (Al) atomic percentage of the composition gradient layer110is gradually decreased in the depth direction from bottom to top, such as being gradually decreased from the value C1 to the value close to zero. In one embodiment, the value C3 is about 10%, the value C2 is about 50%, and the value C1 is about 30%. In this embodiment, the concentration profile of the atomic percentage of aluminum (Al) varying with the position in the depth direction in the composition gradient layer110ofFIG.3may be a straight line profile201. In one embodiment, the atomic percentage of aluminum (Al) in the composition gradient layer110may also have other values higher or lower than the value C1 as a starting value and be gradually decreased from the starting value to the value close to zero along the depth direction from bottom to top. According to an embodiment of the present disclosure, the average atomic concentration of aluminum (Al) in the tensile stress layer108is higher than the average atomic concentration of aluminum (Al) in the composition gradient layer110, and the average atomic concentration of aluminum (Al) in the composition gradient layer110is higher than the average atomic concentration of aluminum (Al) in the uppermost second superlattice layer106B. FIG.4,FIG.5andFIG.6are various concentration profiles of the atomic percentage of the same group III element such as aluminum (Al) varying with different positions in the depth direction in the composition gradient layer, the tensile stress layer, and the uppermost second superlattice layer of the HEMTs according to some embodiments of the present disclosure. The difference between the embodiments ofFIG.4andFIG.3is that the concentration profile of the atomic percentage of aluminum (Al) varying with different positions in the depth direction in the composition gradient layer110ofFIG.4may be an arc profile202. The difference between the embodiments ofFIG.5andFIG.3is that the concentration profile of the atomic percentage of aluminum (Al) varying with different positions in the depth direction in the composition gradient layer110ofFIG.5may be a step-shaped profile203. The difference between the embodiments ofFIG.6andFIG.3is that the concentration profile of the atomic percentage of aluminum (Al) varying with different positions in the depth direction in the composition gradient layer110ofFIG.6may be a wavy profile204. For other similar parts ofFIG.4,FIG.5andFIG.6, please refer to the aforementioned description ofFIG.3. FIG.7,FIG.8,FIG.9, andFIG.10are schematic cross-sectional diagrams of various intermediate stages of fabricating the HEMT100according to an embodiment of the present disclosure. According to an embodiment, as shown inFIG.7, a substrate102is provided. In addition, a nucleation layer104, a superlattice structure106, a tensile stress layer108, a composition gradient layer110, an electrical isolation layer112, a channel layer114, a barrier layer116and a doped semiconductor cap layer118are formed on the substrate102in sequence. In one embodiment, the superlattice structure106may be composed of a first superlattice stack106-1disposed on a second superlattice stack106-2. In another embodiment, the superlattice structure106may be composed of the first superlattice stack106-1. In one embodiment, the substrate102may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, but not limited thereto. In another embodiment, the substrate102further includes a single or multiple layers of insulating material and/or other suitable material layers (such as a semiconductor layer) and a core layer. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating materials. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum gallium nitride (AlGaN), zinc oxide (ZnO) or gallium oxide (Ga2O3), or other suitable ceramic materials. In one embodiment, the single or multiple layers of insulating material and/or other suitable material layers wraps the core layer. The nucleation layer104may be optionally disposed on the substrate102, which has fewer lattice defects, so that the epitaxial quality of the superlattice structure106grown on the nucleation layer104may be improved. In one embodiment, the nucleation layer104may include an aluminum nitride (AlN) stacked layer, for example, including a first nitride layer and a second nitride layer. In one embodiment, the first nitride layer is, for example, a low-temperature aluminum nitride layer (LT-AlN), and the second nitride layer is, for example, a high-temperature aluminum nitride layer (HT-AlN). The LT-AlN layer may be deposited by metal-organic CVD (MOCVD) at an ambient temperature of 800° C. to 1100° C., and the HT-AlN layer may be deposited by MOCVD at an ambient temperature of 1100° C. to 1400° C., but not limited thereto. The superlattice structure106is disposed on the substrate102. According to an embodiment of the present disclosure, the second superlattice stack106-2of the superlattice structure106may be optionally disposed on the nucleation layer104, and then the first superlattice stack106-1is disposed on the second superlattice stack106-2. Alternatively, when the second superlattice stack106-2is omitted, the first superlattice stack106-1may be disposed on the nucleation layer104. The superlattice structure106may be used to reduce the degree of lattice mismatch between the substrate102and the semiconductor layer disposed on the superlattice structure106, and to reduce the stress caused by the lattice mismatch. According to an embodiment of the present disclosure, as shown inFIG.2, the first superlattice stack106-1may include a plurality of pairs of first superlattice layers106A and second superlattice layers106B. Similarly, the second superlattice stack106-2may include a plurality of pairs of superlattice layers, such as third superlattice layers and fourth superlattice layers. According to different requirements, the first superlattice stack106-1and the second superlattice stack106-2may each be a structure formed by periodically and alternately stacking at least two kinds of group III-V semiconductor layers. For example, each of the first superlattice stack106-1and the second superlattice stack106-2may include a plurality of pairs of AlN thin layers and AlGaN thin layers, or a plurality of pairs of AlN thin layers and GaN thin layers. Alternatively, each of the first superlattice stack106-1and the second superlattice stack106-2may be a structure composed of a stack of multiple group III-V semiconductor layers with gradually-varied composition ratio. For example, the composition ratio of aluminum in aluminum gallium nitride (AlaGa(1-a)N, wherein 0.15≤a≤0.9) is gradually decreased from the lower superlattice layer to the upper superlattice layer, but not limited thereto. According to an embodiment, the superlattice structure106may be formed by an atomic layer deposition (ALD) process, through adjusting the gas source ratio for depositing each atomic layer, such as adjusting gas source ratio of aluminum (Al), nitrogen (N), and gallium (Ga) may deposit a stack of multiple superlattice layers with various composition ratios. According to an embodiment of the present disclosure, the tensile stress layer108may be optionally disposed on the superlattice structure106, and the composition gradient layer110may be formed on the tensile stress layer108. The compositions of the tensile stress layer108and the composition gradient layer110are as the aforementioned description, and not repeated herein. According to an embodiment, the composition gradient layer110and the tensile stress layer108may be formed by an ALD process, through adjusting the gas source ratio for depositing each atomic layer, such as adjusting the gas source ratio of aluminum (Al), nitrogen (N) and gallium (Ga) may deposit a stack of multiple atomic layers with gradually-varied composition ratio to form the composition gradient layer110with, for example, a gradually-varied atomic percentage or atomic concentration of aluminum (Al). In one embodiment, the thickness of the tensile stress layer108may be 2 nm to 20 nm. Alternatively, the thickness of the tensile stress layer108may be 0.2% to 2% of the thickness of the electrical isolation layer112. The thickness of the composition gradient layer110may be 5 nm to 50 nm. Alternatively, the thickness of the composition gradient layer110may be 0.5% to 5% of the thickness of the electrical isolation layer112. According to an embodiment of the present disclosure, the electrical isolation layer112is disposed on the composition gradient layer110. The electrical isolation layer112has a higher resistivity than other layers, thereby avoiding leakage current between the substrates102and the semiconductor layers disposed on the electrical isolation layer112. The channel layer114may be disposed on the electrical isolation layer112, and the barrier layer116may be disposed on the channel layer114. The compositions of the channel layer114and the barrier layer116are as the aforementioned description, and not repeated herein. The doped semiconductor cap layer118may be formed on the barrier layer116for depleting the two-dimensional electron gas (2-DEG) region to achieve the normally-off state of the HEMT. The doped semiconductor cap layer118may be one or more doped group III-V semiconductor layers, such as GaN doped with p-type dopants or n-type dopants. The composition of the doped semiconductor cap layer118may be GaN, AlGaN, InGaN or InAlGaN, and the dopant thereof may be C, Fe, Mg or Zn, but not limited thereto. According to an embodiment, the doped semiconductor cap layer118may be a p-type GaN layer. Next, according to an embodiment of the present disclosure, as shown inFIG.8, a patterned doped semiconductor cap layer118is formed on the barrier layer116. The patterned doped semiconductor cap layer118may be formed by a photolithography process and an etching process. Then, an isolation region120is formed on the periphery of the HEMT to isolate the adjacent HEMTs from each other. According to an embodiment, the isolation region120passes through the barrier layer116and may extend downward into the channel layer114. The isolation region120is separated from the electrical isolation layer112by a distance. In one embodiment, the isolation region120may be a shallow trench isolation (STI), which may be formed by forming a trench in the barrier layer116and the channel layer114through an etching process, and then filling the trench with one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or a combination thereof. Thereafter, a chemical mechanical polishing (CMP) process is performed on the aforementioned structure to form the isolation region120. In another embodiment, the isolation region120may be formed by ion implantation. A hard mask is used to cover the area outside the predetermined area where the isolation region120is to be formed, and then a dopant is implanted in the barrier layer116and the channel layer114to form the isolation region120. The dopant is such as helium or carbon. Next, according to an embodiment of the present disclosure, as shown inFIG.9, a first passivation layer128-1is formed on the isolation region120and the barrier layer116, and a source electrode122and a drain electrode124are formed on two opposite sides of the doped semiconductor cap layer118respectively. In one embodiment, the source electrode122and the drain electrode124pass through the first passivation layer128-1and the barrier layer116, and extend downward into the channel layer114, so that the bottoms of the source electrode122and the drain electrode124are higher than the bottom of the isolation region120and lower than the top surface of the channel layer114. In another embodiment, the source electrode122and the drain electrode124pass through the first passivation layer128-1and extend downward into the barrier layer116, so that the bottoms of the source electrode122and the drain electrode124are higher than the bottom of the isolation region120and lower than the top surface of the barrier layer116. According to an embodiment, the first passivation layer128-1may be firstly deposited to cover the isolation region120, the barrier layer116and the doped semiconductor cap layer118, and then contact holes of the source electrode122and the drain electrode124are formed in the first passivation layer128-1, the barrier layer116and the channel layer114, and on two opposite sides of the doped semiconductor cap layer118respectively. Thereafter, a conductive material layer is deposited in the contact holes and on the first passivation layer128-1. In one embodiment, the source electrode122and the drain electrode124may be formed through a CMP process, such that the top surface of the doped semiconductor cap layer118is exposed, where the top surfaces of the source electrode122and the drain electrode124may be in the same level with the top surface of the doped semiconductor cap layer118. In another embodiment, after the conductive material layer is deposited, an etching process may be used to remove the conductive material layer outside the contact holes to form the source electrode122and the drain electrode124, such that the top surface of the doped semiconductor cap layer118may still be covered by the first passivation layer128-1. According to an embodiment, the source electrode122and the drain electrode124may have a single-layered or multiple-layered structure, and the composition thereof may include an ohmic contact metal. The ohmic contact metal refers to a metal, an alloy or a stacked layer thereof that produces ohmic contact with a semiconductor layer (such as the channel layer114). The ohmic contact metal is for example Ti, Ti/Al, Ti/Al/Ti/TiN, Ti/Al/Ti/Au, Ti/Al/Ni/Au or Ti/Al/Mo/Au, but not limited thereto. Next, according to an embodiment of the present disclosure, as shown inFIG.10, a second passivation layer128-2is formed to cover the first passivation layer128-1, the doped semiconductor cap layer118, the source electrode122and the drain electrode124. The first passivation layer128-1and the second passivation layer128-2may be collectively referred to as the passivation layer128. Then, a contact hole125of the gate electrode126is formed in the second passivation layer128-2to expose the top surface of the doped semiconductor cap layer118. According to an embodiment of the present disclosure, for the case where an etch stop layer (not shown) is disposed on the top surface of the doped semiconductor cap layer118, the etch stop layer may be exposed from the contact hole125. The etch stop layer may be used to protect the doped semiconductor cap layer118and to prevent the doped semiconductor cap layer118from being in direct contact with the etchant used in the etching process of forming the contact hole125. Afterwards, a conductive material layer is deposited in the contact hole125and on the second passivation layer128-2. Then, the conductive material layer is patterned through a photolithography process and an etching process to form the gate electrode126as shown inFIG.1. In one embodiment, the top surface of the gate electrode126is higher than the top surface of the passivation layer128. In another embodiment, a part of the gate electrode126may further extend onto the top surface of the passivation layer128. According to an embodiment, the gate electrode126may have a single-layered or multiple-layered structure, for example, a double-layered structure including a first conductive layer and a second conductive layer. Where, the first conductive layer may be in direct contact with the doped semiconductor cap layer118, and its composition includes a Schottky contact metal. The Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that produces Schottky contact with a semiconductor layer (such as the doped semiconductor cap layer118). The Schottky contact metal is for example TiN, W, Pt, Ni or Ni, but not limited thereto. The composition of the second conductive layer may include Ti, Al, Au, or Mo, but not limited thereto. In one embodiment, the first conductive layer may further include a metal nitride of a refractory metal. The refractory metal may be selected from a group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, technetium, rhenium, ruthenium, osmium, rhodium and iridium. According to an embodiment of the present disclosure, the materials of the first passivation layer128-1and the second passivation layer128-2include aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON) or silicon oxide (SiO2). In one embodiment, the materials of the first passivation layer128-1and the second passivation layer128-2may be the same. In another embodiment, the materials of the first passivation layer128-1and the second passivation layer128-2may be different from each other. According to one objective of the embodiments of the present disclosure, it avoids a current transmission path between the superlattice structure and the electrical isolation layer of the HEMT. According to another objective of the embodiments of the present disclosure, it avoids a cross-link interference problem due to leakage current between the adjacent HEMTs. Therefore, the accuracy of the bare die chip probing (CP) test before packaging is improved to more accurately determine whether the HEMTs meet the electrical specifications. Meanwhile, the 2-DEG performance of the HEMTs is maintained and the electrical performance of the HEMTs is also improved. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 41,520 |
11942520 | DETAILED DESCRIPTION OF THE INVENTION Semiconductor Film The semiconductor film of the present invention has a corundum-type crystal structure composed of α-Ga2O3or an α-Ga2O3solid solution. α-Ga2O3belongs to a trigonal crystal group and has a corundum-type crystal structure. Further, the α-Ga2O3solid solution is a solid solution in which other components are dissolved in α-Ga2O3, and the corundum-type crystal structure is maintained. In the α-Ga2O3based semiconductor film of the present invention, the crystal defect density on at least one surface thereof is 1.0×106/cm2or less, preferably 1.0×105/cm2, more preferably 4.0×103/cm2or less, and still more preferably 1.0×103/cm2or less. Such a semiconductor film having an extremely low crystal defect density is excellent in dielectric breakdown electric field characteristics and is suitable for application in power semiconductors. The lower limit of the crystal defect density is not particularly limited and is preferably low. Further, in a case where a functional layer is formed on (or inside) the surface of such a semiconductor film having a low crystal defect density, it is preferable because the crystal defects do not propagate inside the functional layer. Note that as used herein, the “at least one surface” means at least one of two main surfaces (that is, a film surface or a plate surface) of a semiconductor film opposing each other, regardless of the top surface or the bottom surface. Note that as used herein, the “surface” means a surface forming the outside of an object, and it does not matter whether the surface is exposed to the outside (for example, the surface may be in contact with or coupled to another object). On the other hand, the “top surface” means a surface opposite the “bottom surface”. The crystal defect density of the semiconductor film is preferably smaller on one surface of the semiconductor film (hereinafter, referred to as “top surface”) than on a surface opposite the surface (hereinafter referred to as “bottom surface”). In other words, it is preferable to satisfy the relationship of (crystal defect density on bottom surface)/(crystal defect density on top surface)>1. For example, when a semiconductor film is formed on a base substrate for film formation and the crystal defect density of a surface on a film forming side and a surface opposite the surface (surface adjacent to the base substrate for film formation) are evaluated, the crystal defect density of the surface on the film forming side may be smaller than the crystal defect density of the surface adjacent to the base substrate for film formation. At this time, when the side with a small crystal defect density is the top surface and the side in contact with the base substrate for film formation is the bottom surface, (crystal defect density on bottom surface)/(crystal defect density on top surface)>1 is satisfied. This relationship means that crystal defects are reduced during the formation of the semiconductor film. In such a film, a high-quality functional layer having a small crystal defect density or the like can be formed by forming a functional layer on (or inside) the surface having a small crystal defect density. Also, in a case where a semiconductor film prepared on a base substrate for film formation is separated and reprinted on another support substrate for use, it is preferable to form the functional layer on (or inside) the surface on the side with a small crystal defect density to obtain a high-quality functional layer. Specifically, the ratio of the crystal defect density on a surface (bottom surface) opposite one surface (top surface) of the semiconductor film to a crystal defect density on the one surface of the semiconductor film preferably exceeds 1.0, more preferably 1.2 or more, still more preferably 2.0 or more, particularly preferably 10 or more, and most preferably 100 or more. Further, the upper limit of the ratio of the crystal defect density on the bottom surface of the semiconductor film to the crystal defect density on the top surface of the semiconductor film is not particularly limited, but is, for example, 1000 or less. Here, as described above, the bottom surface of the semiconductor film refers to the surface on the side opposite the surface (top surface) on the side with a small crystal defect density, but typically refers to the surface on the side that is adjacent to (or was adjacent to) the base substrate used for forming the semiconductor film. The crystal defect density of the α-Ga2O3based semiconductor film can be evaluated by plane TEM observation (plan view) or cross-section TEM observation. For example, when performing plane TEM observation of the semiconductor film surface, it can be performed using a general transmission electron microscope. For example, in a case where H-90001UHR-I manufactured by Hitachi is used as the transmission electron microscope, TEM observation may be performed at an acceleration voltage of 300 kV. The test piece used for TEM observation is preferably such that a sample is cut out so as to include one surface of the semiconductor film, and a measurement field of view of 50 μm×50 μm can be observed. More specifically, the test piece may be processed by ion milling so that the region of the measurement field of view of 4.1 μm×3.1 μm can be observed at eight or more places and the thickness around the measurement field of view is 150 nm. The crystal defect density can be evaluated from the plane TEM image of the surface of the test piece thus obtained. Similarly, in the case of performing plane TEM observation of the surface (bottom surface) on the side opposite the semiconductor film surface (top surface) observed, a test piece may be cut out so as to include the semiconductor film bottom surface, and TEM observation may be performed. Further, in a case where the semiconductor film is thin, it is also possible to evaluate the defect density of the top surface and the bottom surface at the same time by cross-section TEM observation of the film. In a case where the crystal defect density is low and it is difficult to observe the crystal defects by plane TEM observation, other known methods, for example, etch pit evaluation by wet etching, can also be used. The semiconductor film of the present invention may be composed of an α-Ga2O3solid solution in which one or more components selected from the group consisting of Cr2O3, Fe2O3, Ti2O3, V2O3, Ir2O3, Rh2O3, In2O3, and Al2O3are dissolved in α-Ga2O3. All of these components have a corundum-type crystal structure, and their lattice constants are relatively close to each other. Therefore, the metal atoms of these components easily replace Ga atoms in the solid solution. Further, by dissolving these components in solid solution, it becomes possible to control the band gap, electrical characteristics, and/or lattice constant of the semiconductor film. The amount of solid solution of these components can be appropriately changed according to the desired characteristics. Incidentally, as a method for evaluating crystal defects and domain, a method is known in which X-ray rocking curve (XRC) measurement is performed on the (006) plane and the (104) plane of, and evaluation is performed with the full width at half maximum (FWHM) thereof. In XRC measurement, it is common to correct the warpage of the sample using a vacuum chuck or the like, but it is often difficult to correct the warpage in a case where the amount of warpage is large. Therefore, it can be said that the X-ray rocking curve full width at half maximum (hereinafter, referred to as XRC full width at half maximum) reflects not only crystal defects and domains but also the amount of warpage. In particular, the XRC full width at half maximum of the (104) plane reflects all of various defects such as threading edge dislocations and threading screw dislocations, the presence (mosaicity) of regions (domains) having different tilts (inclinations of crystal axes in the growth orientation) and twists (rotations of crystal axes in the surface plane), and the state of warpage, and therefore, the XRC full width at half maximum is suitable as an evaluation method for semiconductor films. The XRC full width at half maximum of the (104) plane on at least one surface of the semiconductor film of the present invention is preferably small, preferably 500 arcsec or less, more preferably 150 arcsec or less, still more preferably 100 arcsec or less, particularly preferably 50 arcsec or less, and most preferably 40 arcsec or less. There is no problem even if the XRC full width at half maximum of the (104) plane is equivalent to the full width at half maximum specific to the X-ray source used for measurement, 30 arcsec or more is actually preferable. When the XRC full width at half maximum is within the above range, there are few crystal defects, small mosaicity, and small warpage, and as a result, in a case where a functional layer is formed on (or inside) such a surface, a high-quality functional layer having even higher dielectric breakdown electric field characteristics or the like can be obtained. The measurement of the XRC profile of the (104) plane for the α-Ga2O3based semiconductor film can be performed using a general XRD apparatus. For example, when D8-DISCOVER manufactured by Bruker-AXS is used as the XRD apparatus, 2θ, ω, χ, and φ may be adjusted to perform axial alignment so that the peak of the (104) plane of α-Ga2O3appears, and then measurement may be performed by under conditions of a tube voltage of 40 kV, a tube current of 40 mA, a collimator diameter of 0.5 mm, an anti-scattering slit of 3 mm, in a range of an ω=15.5 to 19.5°, an w step width of 0.005°, and a counting time of 0.5 seconds. This measurement is preferably performed after converting CuKα rays into parallel monochromatic light with a Ge (022) asymmetric reflection monochromator. The full width at half maximum in the XRC profile of the (104) plane can be determined by performing peak search after profile smoothing using XRD analysis software (“LEPTOS” Ver 4.03, manufactured by Bruker-AXS). Further, the XRC full width at half maximum of the (006) plane on at least one surface of the semiconductor film of the present invention is also desirably small, preferably 50 arcsec or less, and more preferably 40 arcsec or less. There is no problem even if the XRC full width at half maximum of the (006) plane is equivalent to the full width at half maximum specific to the X-ray source used for measurement, 30 arcsec or more is actually preferable. The XRC full width at half maximum of the (006) plane reflects information on threading screw dislocations, tilts and warpages. Therefore, when the XRC full width at half maximum is within the above range, there are few crystal defects, small mosaicity, and small warpage, and as a result, even higher dielectric breakdown electric field characteristics can be obtained. The measurement of the XRC profile of the (006) plane for the α-Ga2O3based semiconductor film can also be performed using a general XRD apparatus. For example, the measurement conditions in the case of using D8-DISCOVER manufactured by Bruker-AXS as the XRD apparatus can be the same as the conditions described above for the (104) plane except that 2θ, ω, χ, and φ are adjusted to perform axial alignment so that the peak of the (006) plane of α-Ga2O3appears, and then ω is set to 18.0 to 22.0°. The semiconductor film can contain a Group 14 element as a dopant at a proportion of 1.0×1016to 1.0×1021/cm3. Here, the term “Group 14 element” refers to a Group 14 element according to the periodic table formulated by the IUPAC (International Union of Pure and Applied Chemistry), and specifically, is any one of carbon (C), silicon (Si), germanium (Ge), tin (Sn) and lead (Pb). The amount of the dopant can be appropriately changed according to the desired characteristics, but is preferably 1.0×1016to 1.0×1021/cm3, and more preferably 1.0×1017to 1.0×1019/cm3. It is preferable that these dopants are uniformly distributed in the film and the concentrations on one surface (top surface) and the surface opposite the surface (bottom surface) are about the same. That is, it is preferable that the semiconductor film uniformly contains the Group 14 element as the dopant in the above proportion. Further, it is preferable that the semiconductor film is an orientation film crystallographically oriented in a specific plane orientation, for example, a c-axis orientation film. The orientation of the semiconductor film can be examined by a known method, for example, by performing reverse pole figure orientation mapping using, an electron backscatter diffraction apparatus (EBSD). The thickness of the semiconductor film may be appropriately adjusted from the viewpoint of cost and required characteristics. That is, it takes time to form a film when the film to be formed is too thick, so it is preferable that the film is not extremely thick from the viewpoint of cost. Further, in a case where a device that requires a particularly high dielectric strength is prepared, it is preferable to prepare a thick film. On the other hand, in a case where a device that requires conductivity in the vertical direction (thickness direction) is prepared, it is preferable to prepare a thin film. As described above, the film thickness may be appropriately adjusted according to the desired characteristics, but typically 0.3 to 50 μm, or 0.5 to 20 μm, or 0.5 to 10 μm. By setting the thickness in such a range, it is possible to achieve both cost and semiconductor characteristics. In a case where a self-standing semiconductor film is required, a thick film may be used, for example, 50 μm or more, or 100 μm or more, and there is no particular upper limit unless there is a cost limitation. The semiconductor film has an area of preferably 20 cm2or more, more preferably 70 cm2or more, and still more preferably 170 cm2or more on one side thereof. By increasing the area of the semiconductor film in this way, it is possible to obtain a large number of semiconductor elements from one semiconductor film, and it is possible to reduce the manufacturing cost. The upper limit of the size of the semiconductor film is not particularly limited, but is typically 700 cm2or less on one side. The semiconductor film may be in the form of a self-standing film of a single film or may be formed on a support substrate. The support substrate is preferably a substrate having a corundum structure and oriented in two axes, the c-axis and the a-axis (biaxial orientation substrate). By using a biaxial orientation substrate having a corundum structure as the support substrate, the semiconductor film can also serve as a seed crystal for heteroepitaxial growth (base substrate for film formation). The biaxial orientation substrate may be a polycrystal, a mosaic crystal (a set of crystals of which crystal orientations are slightly deviated), or a single-crystal. As long as it has a corundum structure, it may be composed of a single material or a solid solution of a plurality of materials. The main component of the support substrate is preferably a material selected from the group consisting of α-Al2O3, α-Cr2O3, α-Fe2O3, α-Ti2O3, α-V2O3, and α-Rh2O3, or a solid solution containing two or more selected from the group consisting of α-Al2O3, α-Cr2O3, α-Fe2O3, α-Ti2O3, α-V2O3, and α-Rh2O3, and particularly preferably α-Cr2O3, or a solid solution of α-Cr2O3and a different material. Further, as a seed crystal for support substrate and heteroepitaxial growth (base substrate for film formation), a composite base substrate in which an orientation layer composed of a material having a corundum-type crystal structure having an a-axis length and/or a c-axis length larger than that of sapphire is formed on a corundum single crystal such as sapphire or Cr2O3can be used. In this case, the orientation layer preferably contains a material selected from the group consisting of α-Cr2O3, α-Fe2O3, α-Ti2O3, α-V2O3, and α-Rh2O3, or a solid solution containing two or more selected from the group consisting of α-Al2O3, α-Cr2O3, α-Fe2O3, α-Ti2O3, α-V2O3, and α-Rh2O3. Further, the semiconductor film prepared on the base substrate for film formation may be separated and reprinted on another support substrate. The material of the other support substrate is not particularly limited, but a suitable material may be selected from the viewpoint of material properties. For example, from the viewpoint of thermal conductivity, a metal substrate made of Cu or the like, a ceramic substrate made of SiC, AlN or the like, is preferably used. It is also preferable to use a substrate having a coefficient of thermal expansion of 6 to 13 ppm/K at 25 to 400° C. That is, the semiconductor film is preferably provided on a support substrate having a coefficient of thermal expansion of 6 to 13 ppm/K at 25 to 400° C., and such a semiconductor film or composite material is also provided as a preferred embodiment of the present invention. By using a support substrate having such a coefficient of thermal expansion, the difference in thermal expansion between the semiconductor film and the support substrate can be reduced, and as a result, the occurrence of cracks in the semiconductor film due to thermal stress and the peeling of the film can be suppressed. An example of such a support substrate is a substrate made of a Cu—Mo composite material. The composite ratio of Cu and Mo can be appropriately selected in consideration of the matching of the coefficient of thermal expansion with the semiconductor film, the thermal conductivity, the conductivity and the like. The supporting substrate for the semiconductor film is preferably any of a biaxial orientation substrate composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, or a composite substrate having an orientation layer composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material. By doing so, the semiconductor film can also serve as both a seed crystal (base substrate for film formation) for heteroepitaxial growth and a support substrate, and the crystal defects in the semiconductor film can also be significantly reduced. As described above, the semiconductor film of the present invention has remarkably few crystal defects and can exhibit high dielectric breakdown electric field characteristics. As far as the present inventor knows, a technique for obtaining a semiconductor film having such a low crystal defect density has not been conventionally known. For example, Non-Patent Literature 1 discloses that an α-Ga2O3layer is formed using a substrate in which a (Alx, Ga1-x)2O3layer (x=0.2 to 0.9) is introduced as a buffer layer between sapphire and the α-Ga2O3layer, and in the obtained α-Ga2O3layer, the densities of edge dislocations and screw dislocations are 3×108/cm2and 6×108/cm2, respectively. Method for Manufacturing Semiconductor Film The production method of the semiconductor film is not particularly limited as long as a semiconductor film having a corundum-type crystal structure composed of α-Ga2O3or an α-Ga2O3solid solution can be formed so that the crystal defect density on at least one surface of the semiconductor film is 1.0×106/cm2or less. However, as described above, it is preferable to use any of a biaxial orientation substrate composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, or a composite base substrate having an orientation layer composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, as a base substrate for film formation. Hereinafter, the method for producing the semiconductor film will be described in the order of (1) preparation of a composite base substrate and (2) formation of a semiconductor film. (1) Preparation of Composite Base Substrate The composite base substrate can be preferably produced by (a) providing a sapphire substrate, (b) preparing a predetermined orientation precursor layer, (c) performing heat treatment on the orientation precursor layer on the sapphire substrate to convert at least a portion near the sapphire substrate into an orientation layer, and optionally (d) subjecting the orientation layer to processing such as grinding or polishing to expose the surface of the orientation layer. This orientation precursor layer becomes an orientation layer by heat treatment and contains a material having a corundum-type crystal structure having an a-axis length and/or c-axis length larger than that of sapphire, or a material capable of having a corundum-type crystal structure having an a-axis length and/or c-axis length larger than that of sapphire by heat treatment to be described later. Further, the orientation precursor layer may contain trace components in addition to the material having a corundum-type crystal structure. According to such a production method, the growth of the orientation layer can be promoted by using the sapphire substrate as a seed crystal. That is, the high crystallinity and crystal orientation peculiar to the single-crystal of the sapphire substrate are inherited by the orientation layer. (a) Provision of Sapphire Substrate To prepare the composite base substrate, first, a sapphire substrate is provided. The sapphire substrate used may have any orientation plane. That is, the sapphire substrate may have an α-plane, a c-plane, an r-plane, or an m-plane, or may have a predetermined off-angle with respect to these planes. For example, in a case where a c-plane sapphire is used, since the c-axis is oriented with respect to the surface, it is possible to easily heteroepitaxially grow a c-axis oriented orientation layer thereon. A sapphire substrate to which a dopant is added may also be used to adjust electrical properties. As such a dopant, a known dopant can be used. (b) Preparation of Orientation Precursor Layer An orientation precursor layer containing a material having a corundum-type crystal structure having an a-axis length and/or c-axis length larger than that of sapphire, or a material capable of having a corundum-type crystal structure having an a-axis length and/or c-axis length larger than that of sapphire by heat treatment is prepared. The method for forming the orientation precursor layer is not particularly limited, and a known method can be adopted. Examples of the method for forming the orientation precursor layer include an aerosol deposition (AD) method, a sol-gel method, a hydrothermal method, a sputtering method, an evaporation method, various chemical vapor deposition (CVD) methods, a PLD method, a chemical vapor transport (CVT) method, and a sublimation method. Examples of the CVD method include a thermal CVD method, a plasma CVD method, a mist CVD method, and an MO (metal organic) CVD method. Alternatively, a method may be used in which a molded body of the orientation precursor is prepared in advance and the molded body is placed on a sapphire substrate. Such a molded body can be produced by molding the material of the orientation precursor by a method such as tape casting or press molding. Further, it is also possible to use a method in which a polycrystal prepared in advance by various CVD methods, sintering, or the like is used as the orientation precursor layer and is placed on a sapphire substrate. However, a method of directly forming the orientation precursor layer by using an aerosol deposition (AD) method, various CVD methods, or a sputtering method is preferred. By using these methods, a dense orientation precursor layer can be formed in a relatively short time, and heteroepitaxial growth using a sapphire substrate as a seed crystal can be easily caused. In particular, the AD method does not require a high vacuum process and has a relatively high film formation rate, and is therefore preferable in terms of production cost. In the case of using a sputtering method, a film can be formed using a target of the same material as that of the orientation precursor layer, but a reactive sputtering method in which a film is formed in an oxygen atmosphere using a metal target can also be used. A method of placing a molded body prepared in advance on sapphire is also preferable as a simple method, but since the orientation precursor layer is not dense, a process of densification is required in the heat treatment step described later. In the method of using a polycrystalline prepared in advance as an orientation precursor layer, two steps of a step of preparing a polycrystalline body and a step of performing heat treatment on a sapphire substrate are required. Further, in order to improve the adhesion between the polycrystal and the sapphire substrate, it is necessary to take measures such as keeping the surface of the polycrystal sufficiently smooth. Although known conditions can be used for any of the methods, a method of directly forming an orientation precursor layer using an AD method and a method of placing a molded body prepared in advance on a sapphire substrate will be described below. The AD method is a technique for forming a film by mixing fine particles or a fine particle raw material with a gas to form an aerosol, and impacting the aerosol on a substrate by injecting the aerosol at a high speed from a nozzle, and has a feature of forming a film densified at ordinary temperature.FIG.1shows an example of a film forming apparatus (aerosol deposition (AD) apparatus) used in such an AD method. The film forming apparatus20shown inFIG.1is configured as an apparatus used in an AD method in which a raw material powder is injected onto a substrate in an atmosphere having a pressure lower than atmospheric pressure. The film forming apparatus20includes an aerosol generating unit22that generates an aerosol of raw material powder containing raw material components, and a film forming unit30that forms a film containing the raw material components by injecting the raw material powder onto the sapphire substrate21. The aerosol generating unit22includes an aerosol generating chamber23that stores raw material powder and receives a carrier gas supply from a gas cylinder (not shown) to generate an aerosol, and a raw material supply pipe24that supplies the generated aerosol to the film forming unit30, and a vibrator25that applies vibration at frequencies of 10 to 100 Hz to the aerosol generating chamber23and the aerosol therein. The film forming unit30has a film forming chamber32that injects aerosols onto the sapphire substrate21, a substrate holder34that is disposed inside the film forming chamber32and fixes the sapphire substrate21, and an X-Y stage33that moves the substrate holder34in the X-Y axis direction. Further, the film forming unit30includes an injection nozzle36in which a slit37is formed at a tip thereof to inject aerosol into the sapphire substrate21, and a vacuum pump38for reducing the pressure in the film forming chamber32. It is known that the AD method can control a film thickness, a film quality, and the like according to film forming conditions. For example, the form of the AD film is easily affected by the collision rate of the raw material powder to the substrate, the particle size of the raw material powder, the aggregated state of the raw material powder in the aerosol, the injection amount per unit time, and the like. The collision rate of the raw material powder with the substrate is affected by the differential pressure between the film forming chamber32and the injection nozzle36, the opening area of the injection nozzle, and the like. If appropriate conditions are not used, the coating may become a green compact or generate pores, so it is necessary to appropriately control these factors. In a case where a molded body in which the orientation precursor layer is prepared in advance is used, the raw material powder of the orientation precursor can be molded to prepare the molded body. For example, in a case where press molding is used, the orientation precursor layer is a press molded body. The press molded body can be prepared by press-molding the raw material powder of the orientation precursor based on a known method, and may be prepared, for example, by placing the raw material powder in a mold and pressing the raw material powder at pressures of preferably 100 to 400 kgf/cm2, and more preferably 150 to 300 kgf/cm2. The molding method is not particularly limited, and in addition to press molding, tape casting, slip casting, extrusion molding, doctor blade method, and any combination thereof can be used. For example, in the case of using tape casting, it is preferable that additives such as a binder, a plasticizer, a dispersant, and a dispersion medium are appropriately added to the raw material powder to form a slurry, and the slurry is discharged and molded into a sheet shape by passing through a slit-shaped thin discharge port. The thickness of the molded body formed into a sheet is not limited, but is preferably 5 to 500 μm from the viewpoint of handling. Further, in a case where a thick orientation precursor layer is required, a large number of these sheet molded bodies may be stacked and used as a desired thickness. In these molded bodies, the portion near the sapphire substrate becomes an orientation layer by the subsequent heat treatment on the sapphire substrate. As described above, in such a method, it is necessary to sinter and densify the molded body in the heat treatment step described later. Therefore, the molded body may contain trace components such as a sintering aid in addition to the material having or resulting in a corundum-type crystal structure. (c) Heat Treatment of Orientation Precursor Layer on Sapphire Substrate A heat treatment is performed on the sapphire substrate on which the orientation precursor layer is formed at a temperature of 1000° C. or more. By this heat treatment, at least a portion of the orientation precursor layer near the sapphire substrate can be converted into a dense orientation layer. Further, this heat treatment enables heteroepitaxial growth of the orientation layer. That is, by forming the orientation layer with a material having a corundum-type crystal structure, heteroepitaxial growth occurs in which the material having a corundum-type crystal structure crystal grows using a sapphire substrate as a seed crystal during heat treatment. At that time, the crystals are rearranged, and the crystals are arranged according to the crystal plane of the sapphire substrate. As a result, the crystal axes of the sapphire substrate and the orientation layer can be aligned. For example, when a c-plane sapphire substrate is used, both the sapphire substrate and the orientation layer can be c-axis oriented with respect to the surface of the base substrate. Moreover, this heat treatment makes it possible to form a gradient composition region in a part of the orientation layer. That is, during the heat treatment, a reaction occurs at the interface between the sapphire substrate and the orientation precursor layer, and the Al component in the sapphire substrate diffuses into the orientation precursor layer, and/or the component in the orientation precursor layer diffuses into the sapphire substrate, thereby forming a gradient composition region composed of a solid solution containing α-Al2O3. It is known that methods such as various CVD methods, a sputtering method, a PLD method, a CVT method, and a sublimation method may cause heteroepitaxial growth on a sapphire substrate without heat treatment at 1000° C. or more. However, it is preferable that the orientation precursor layer is in a non-oriented state, that is, amorphous or non-oriented polycrystalline, at the time of preparation thereof, and the crystal rearrangement is caused by using sapphire as a seed crystal at the time of the heat treatment step. By doing so, it is possible to effectively reduce the crystal defects that reach the surface of the orientation layer. The reason for this is not clear, but it is considered that the crystal structure of the solid-phase orientation precursor layer once formed may be rearranged using sapphire as a seed, which may also be effective in eliminating crystal defects. The heat treatment is not particularly limited as long as a corundum-type crystal structure is obtained and heteroepitaxial growth using a sapphire substrate as a seed occurs, and can be performed in a known heat treatment furnace such as a tubular furnace or a hot plate. Further, in addition to the heat treatment under normal pressure (without pressing), a heat treatment under pressure such as hot pressing or HIP, or a combination of a heat treatment under normal pressure and a heat treatment under pressure can also be used. The heat treatment conditions can be appropriately selected depending on the material used for the orientation layer. For example, the atmosphere of the heat treatment can be selected from the air, vacuum, nitrogen and inert gas atmosphere. The preferred heat treatment temperature also varies depending on the material used for the orientation layer, but is preferably 1000 to 2000° C., and more preferably 1200 to 2000° C., for example. The heat treatment temperature and the retention time are related to the thickness of the orientation layer formed by heteroepitaxial growth and the thickness of the gradient composition region formed by diffusion with the sapphire substrate, and can be appropriately adjusted depending on the kind of the material, the target orientation layer, the thickness of the gradient composition region, and the like. However, in the case of using molded body prepared in advance is used as the orientation precursor layer, it is necessary to perform sintering and densification during heat treatment, and normal pressure firing at a high temperature, hot pressing, HIP, or a combination thereof is suitable. For example, when using a hot press, the surface pressure is preferably 50 kgf/cm2or more, more preferably 100 kgf/cm2or more, particularly preferably 200 kgf/cm2or more, the upper limit is not particularly limited. The firing temperature is also not particularly limited as long as sintering, densification, and heteroepitaxial growth occur, but is preferably 1000° C. or more, more preferably 1200° C. or more, still more preferably 1400° C. or more, and particularly preferably 1600° C. or more. The firing atmosphere can also be selected from atmosphere, vacuum, nitrogen and an inert gas atmosphere. As the firing jig such as a mold, those made of graphite or alumina can be used. (d) Exposure of Surface of Orientation Layer On the orientation layer formed near the sapphire substrate by the heat treatment, an orientation precursor layer or a surface layer having poor orientation or no orientation may exist or remain. In this case, it is preferable that the surface derived from the orientation precursor layer is subjected to processing such as grinding or polishing to expose the surface of the orientation layer. By doing so, a material having excellent orientation is exposed on the surface of the orientation layer, so that the semiconductor layer can be effectively epitaxially grown on the material. The method for removing the orientation precursor layer and the surface layer is not particularly limited, and examples thereof include a method for grinding and polishing and a method for ion beam milling. The surface of the orientation layer is preferably polished by lapping using abrasive grains or chemical mechanical polishing (CMP). (2) Formation of Semiconductor Film Next, a semiconductor film is formed on the orientation layer of the obtained composite base substrate. As for the method of forming a semiconductor film, as long as the semiconductor film having the characteristics specified in the present invention can be obtained, in other words, as long as the film can be formed so that crystal defect density on at least one surface of the semiconductor film is 1.0×106/cm2or less, known methods can be used. However, any of the mist CVD method, HVPE method, MBE method, MOCVD method, hydrothermal method and sputtering method is preferable, and the mist CVD method, hydrothermal method or HVPE method is particularly preferable. Among these methods, the HVPE method will be described below. The HVPE method (halide vapor phase epitaxy method) is a type of CVD and is a method applicable to film formation of compound semiconductors such as Ga2O3and GaN. In this method, the Ga raw material and the halide are reacted to generate gallium halide gas, which is supplied onto the base substrate for film formation. At the same time, O2gas is supplied onto the base substrate for film formation, and the reaction between the gallium halide gas and the O2gas causes Ga2O3to grow on the base substrate for film formation. This method has been widely used industrially due to its high speed and thick film growth capability, and examples of film formation of not only α-Ga2O3but also β-Ga2O3have been reported. FIG.2shows an example of a vapor deposition apparatus using a HVPE method. A vapor deposition apparatus40using the HVPE method includes a reaction furnace50, a susceptor58on which a base substrate for film formation56is placed, an oxygen raw material supply source51, a carrier gas supply source52, and a Ga raw material supply source53, a heater54, and a gas discharge unit57. The reactor50may be any reactor that does not react with the raw material, such as a quartz tube. The heater54may be any heater capable of heating up to at least 700° C. (preferably 900° C. or higher), for example, a resistance heating type heater. A metal Ga55is placed inside the Ga raw material supply source53, and a halogen gas or a hydrogen halide gas, for example, HCl is supplied. The halogen gas or halogenated gas is preferably Cl2or HCl. The supplied halogen gas or halogenated gas reacts with the metal Ga55to generate gallium halide gas, which is supplied to the base substrate for film formation. The gallium halide gas preferably contains GaCl and/or GaCl3. The oxygen raw material supply source51can supply an oxygen source selected from the group consisting of O2, H2O and N2O, and O2is preferable. These oxygen raw material gases are supplied to the base substrate for film formation for film formation at the same time as the gallium halide gas. The Ga raw material and the oxygen raw material gas may be supplied together with a carrier gas such as N2or a rare gas. The gas discharge unit57may be connected to a vacuum pump such as a diffusion pump or a rotary pump, for example, and may control not only the discharge of unreacted gas in the reaction furnace50but also the inside of the reaction furnace50under reduced pressure. This can suppress the gas phase reaction and improve the growth rate distribution. By heating the base substrate for film formation56to a predetermined temperature using the heater54and simultaneously supplying the gallium halide gas and the oxygen raw material gas, α-Ga2O3is formed on the base substrate for film formation56. The film formation temperature is not particularly limited as long as α-Ga2O3is formed, but is typically 250° C. to 900° C., for example. The partial pressure of the Ga raw material gas and the oxygen raw material gas is also not particularly limited. For example, the partial pressure of the Ga raw material gas (gallium halide gas) may be in the range of 0.05 kPa or more and 10 kPa or less, and the partial pressure of the oxygen raw material gas may be in the range of 0.25 kPa or more and 50 kPa or less. In a case where an α-Ga2O3based semiconductor film containing a Group 14 element is formed, or in the case where a mixed crystal film with α-Ga2O3containing an oxide of In or Al is formed as a dopant, these halides may be supplied from a separate supply source, or these halides may be mixed and supplied from the Ga raw material supply source53. Further, a material containing a Group 14 element, In, Al or the like may be placed in the same place as the metal Ga55, reacted with a halogen gas or a hydrogen halide gas, and supplied as a halide. These halide gas supplied to the base substrate for film formation56react with the oxygen raw material gas to form oxides in the same manner as gallium halide, and are incorporated into the α-Ga2O3based semiconductor film. When forming a semiconductor film by the HVPE method, it is possible to form a film having a single-layer structure by keeping the supply amounts of Ga raw material, oxygen raw material, and the like constant and appropriately controlling the film forming conditions. In this way, a semiconductor film having a remarkably low surface crystal defect density of 1.0×106/cm2or less can be formed on the composite base substrate. The semiconductor film of the present invention has a remarkably small warpage after formed on a base substrate for film formation or when separated from the base substrate for film formation to form a self-standing film. In particular, in the case of using any of a biaxial orientation substrate composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, or a composite substrate having an orientation layer composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, as a base substrate for film formation, the warpage amount can be particularly reduced. For example, the warpage amount in a case where a 2-inch size semiconductor film is prepared can be 30 μm or less, more preferably 20 μm or less, and still more preferably 10 μm or less. As described above, the semiconductor film of the present invention can be a film with small mosaicity. The α-Ga2O3film formed on the conventional sapphire substrate may be an aggregate of domains (mosaic crystal) having slightly different crystal orientations. The cause of this is not clear, but it may be attributed to the fact that α-Ga2O3is a metastable phase and therefore the film formation temperature is relatively low. Since the film formation temperature is low, it is difficult for the adsorbed components to migrate on the substrate surface, thus suppressing step-flow growth. Therefore, the growth mode of island-shaped growth (three-dimensional growth) tends to be dominant. Further, in a case where a sapphire substrate is used as the base substrate for film formation, there may be a lattice mismatch between the semiconductor film and the sapphire, and each island-shaped growth part (domain) may have slightly different crystal orientation. For this reason, the domains do not meet completely and tend to form mosaic crystals. The semiconductor film of the present invention, in particular as base substrate for film formation, can be formed by using any of a single-crystal substrate composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, or a composite substrate having a single-crystal substrate composed of α-Cr2O3or a solid solution of α-Cr2O3and a different material, and in a case where the film formation conditions are properly controlled, a semiconductor film without mosaicity (that is, single-crystal) or with small mosaicity can be obtained. From the viewpoint of mosaicity, the film formation temperature is, for example, 600° C. or higher, preferably 700° C. or higher, more preferably 800° C. or higher, and still more preferably 900° C. or higher. In order to evaluate the mosaicity of the semiconductor film, known methods such as XRC measurement, EBSD measurement, and TEM can be used, but evaluation at a full width at half maximum in XRC as described above is particularly suitable. The obtained semiconductor film can be formed as it is or divided into semiconductor elements. Alternatively, the semiconductor film may be peeled off from the composite base substrate to form a single film. In this case, in order to facilitate peeling from the composite base substrate, a semiconductor film in which a peeling layer is provided in advance on the orientation layer surface (film forming surface) of the composite base substrate may be used. Examples of such a release layer include those provided with a C injection layer and an H injection layer on the surface of the composite base substrate. Further, C or H may be injected into the film at the initial stage of film formation of the semiconductor film, and a release layer may be provided on the semiconductor film side. Furthermore, it is also possible to adhere and bond a support substrate (mounting substrate) different from the composite base substrate to the surface of the semiconductor film formed on the composite base substrate (that is, the opposite side of the composite base substrate), and then peel and remove the composite base substrate from the semiconductor film. As such a support substrate (mounting substrate), a substrate having a coefficient of thermal expansion at 25 to 400° C. of 6 to 13 ppm/K, for example, a substrate composed of a Cu—Mo composite material can be used. Further, example of the method of adhering and bonding the semiconductor film and the support substrate (mounting substrate) include known methods such as brazing, soldering, and solid phase bonding. Further, an electrode such as an ohmic electrode or a Schottky electrode, or another layer such as an adhesive layer may be provided between the semiconductor film and the support substrate. EXAMPLES The present invention will be described in more detail with reference to the following examples. Example 1 A commercially available Cr2O3single-crystal (size 8 mm×8 mm, thickness 0.5 mm, c-plane, no off-angle) (hereinafter, referred to as Cr2O3substrate) was used as a base substrate for film formation, and an α-Ga2O3film (semiconductor film) was formed as follows. (1) Formation of α-Ga2O3Film by Mist CVD Method (1a) Mist CVD Apparatus FIG.3schematically shows a mist CVD apparatus61used in this example. The mist CVD apparatus61includes a dilution gas source62a, a carrier gas source62b, a flow control valve63b, a mist generation source64, a vessel65, an ultrasonic vibrator66, a quartz tube67, a heater68, a susceptor70, and an exhaust port71. A substrate69is placed on the susceptor70. The flow control valve63ais configured to be capable of controlling the flow rate of the dilution gas sent from the dilution gas source62a, and the flow control valve63bis configured to be capable of controlling the flow rate of the carrier gas sent from the carrier gas source62b. The mist source64contains the raw material solution64a, while the vessel65contains the water65a. The ultrasonic vibrator66is attached to the bottom surface of the vessel65. The quartz tube67forms a film forming chamber, and the heater68is installed around the quartz tube67. The susceptor70is composed of quartz, and the surface on which the substrate69is placed is inclined from the horizontal plane. (1b) Preparation of Raw Material Solution An aqueous solution having a gallium acetylacetonate concentration of 0.05 mol/L was prepared. At this time, 36% hydrochloric acid was contained in a volume ratio of 1.5% to prepare a raw material solution64a. (1c) Preparation for Film Formation The obtained raw material solution64awas stored in the mist generation source64. The base substrate for film formation (Cr2O3substrate) was placed on the susceptor70as the substrate69, and the heater68was operated to raise the temperature inside the quartz tube67to 600° C. Next, the flow control valves63aand63bwere opened to supply the diluted gas and the carrier gas into the quartz tube67from the dilution gas source62aand the carrier gas source62b, respectively. After sufficiently replacing the atmosphere in the quartz tube67with a diluting gas and a carrier gas, the flow rates of the dilution gas and the carrier gas were adjusted to 0.5 L/min and 1 L/min, respectively. Nitrogen gas was used as the dilution gas and the carrier gas. (1d) Film Formation The ultrasonic vibrator66was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution64athrough the water65ato mist the raw material solution64aand generate mist64b. The mist64bwas introduced into the quartz tube67as a film forming chamber by the dilution gas and the carrier gas, and reacted in the quartz tube67to form a film on the substrate69by the CVD reaction on the surface of the substrate69. Thus, a crystalline semiconductor film (semiconductor layer) was obtained. The film formation time was 60 minutes. (2) Evaluation of Semiconductor Film (2a) Surface EDS As a result of EDS measurement of the film surface of the obtained film on the film forming side (that is, the side opposite to the Cr2O3substrate), only Ga and O were detected, and it was found that the obtained film was a Ga oxide. (2b) EBSD An SEM (SU-5000, manufactured by Hitachi High-Technologies Corporation) equipped with an electron backscatter diffraction apparatus (EBSD) (Nordlys Nano, manufactured by Oxford Instruments Inc.) was used to perform reverse pole figure orientation mapping of the surface of the film on the film formation side composed of the Ga oxide in a field of view of 500 μm×500 μm. The conditions for this EBSD measurement were as follows. <EBSD Measurement Conditions> Acceleration voltage: 15 kVSpot intensity: 70Working distance: 22.5 mmStep size: 0.5 μmSample tilt angle: 70°Measurement program: Aztec (version 3.3) From the obtained reverse pole figure orientation mapping, it was found that the Ga oxide film has a biaxially oriented corundum-type crystal structure in which the Ga oxide film was c-axis oriented in the substrate normal direction with in-plane orientation. From these, it was shown that an orientation film composed of α-Ga2O3was formed. (2c) Plane TEM of Film Forming Side Surface Plane TEM observation (plan view) was performed to evaluate the crystal defect density of the α-Ga2O3film. The test piece was cut out so as to include the surface on the film formation side, and processed by ion milling so that the sample thickness (T) around the measurement field of view was 150 nm. The obtained sections were subjected to TEM observation at an acceleration voltage of 300 kV using a transmission electron microscope (H-90001UHR-I manufactured by Hitachi) to evaluate the crystal defect density. Actually, eight TEM images having a measurement field of view of 4.1 μm×3.1 μm were observed, and the number of defects observed therein was calculated. As a result, no crystal defect was observed in the obtained TEM images, and the crystal defect density was found to be less than 9.9×105/cm2. An example of the obtained TEM image is shown inFIG.4. (2d) Plane TEM of Base Substrate for Film Formation Side Surface In order to evaluate the crystal defect density of the surface of the α-Ga2O3film opposite the surface observed in (2c) above (that is, surface adjacent to Cr2O3substrate), a plane TEM observation (plan view) was performed. The test piece was cut out so as to include the film surface, and processed by ion milling so that the sample thickness (T) around the measurement field of view was 150 nm. The obtained sections were subjected to TEM observation at an acceleration voltage of 300 kV using a transmission electron microscope (H-90001UHR-I manufactured by Hitachi) to evaluate the crystal defect density. Actually, eight TEM images having a measurement field of view of 4.1 μm×3.1 μm were observed, and the number of defects observed therein was calculated. As a result, no crystal defect was observed in the obtained TEM images, and the crystal defect density was found to be less than 9.9×105/cm2. (2e) Cross-Section TEM A cross-sectional test piece was cut out from the α-Ga2O3film so that both the surface on the film forming side and the surface adjacent to the Cr2O3substrate were included and the sample thicknesses (T) around the measurement field of view became 200 nm. Using the obtained test piece, TEM observation was performed at an acceleration voltage of 300 kV using a transmission electron microscope (H-90001UHR-I manufactured by Hitachi). As a result of measuring the thickness of the α-Ga2O3film from the obtained TEM image, it was 0.7 μm. (2f) XRC of Film Forming Side Surface Using an XRD apparatus (D8-DISCOVER, manufactured by Bruker-AXS Inc.), XRC measurement was performed on the (104) plane of the film forming surface side surface of the α-Ga2O3film. Actually, after adjusting 2θ, ω, χ, and φ to perform axial alignment so that the peak of the (104) plane of α-Ga2O3appears, conditions were used in which the tube voltage was 40 kV, the tube current was 40 mA, the collimator diameter was 0.5 mm, the anti-scattering slit was 3 mm, w was in the range of 15.5 to 19.5°, the w step width was 0.005°, and the counting time was 0.5 seconds. As the X-ray source, a Ge (022) asymmetric reflection monochromator was used to convert CuKα rays into parallel monochromatic light. The full width at half maximum (FWHM) in the obtained XRC profile of the (104) plane was determined by performing peak search after profile smoothing using XRD analysis software (“LEPTOS” Ver 4.03, manufactured by Bruker-AXS). As a result, the full width at half maximum of the (104) plane XRC profile of the α-Ga2O3film was 127 arcsec. (2g) Sn Concentration The Sn concentration in the α-Ga2O3film was measured using D-SIMS (IMS-7f manufactured by CAMECA). Cs+ion was used as the primary ion species at the time of measurement, and the measurement was performed at a primary ion acceleration voltage of 14.5 kV. As a result, the Sn concentration in the α-Ga2O3film was below the detection limit. Example 2 The formation of the α-Ga2O3film and various evaluations were performed in the same manner as in Example 1 except that the raw material solution in (1b) was prepared as follows and the film formation time in (1d) was set to 130 minutes. The results were as shown in Table 1. (1b′) Preparation of Raw Material Solution An aqueous solution having a gallium acetylacetonate concentration of 0.05 mol/L was prepared. At this time, 36% hydrochloric acid was contained in a volume ratio of 1.5%. Tin (II) chloride dihydrate (SnCl2·2H2O) was added to the obtained gallium acetylacetonate solution, and the concentration was adjusted so that the atomic ratio of tin to gallium was 0.2, thereby obtaining a raw material solution64a. Example 3 The formation of the α-Ga2O3film and various evaluations were performed in the same manner as in Example 1 except that the temperature in the quartz tube67was set at 460° C. in (1c) and the film formation time in (1d) was set at 200 minutes. The results were as shown in Table 1. In this example, the crystal defect density on the film forming side surface of the α-Ga2O3film was smaller than that on the base substrate for film formation side surface. Therefore, when (crystal defect density on bottom surface)/(crystal defect density on top surface) is calculated with the film forming side surface as the top surface and the base substrate for film formation side surface as the bottom surface, it was shown that the calculated values are larger than 1. Example 4 The formation of the α-Ga2O3film and various evaluations were performed in the same manner as in Example 2, except that tin (II) chloride dihydrate was added so that the atomic ratio of tin to gallium was 5.0×10−6in (1b′), the temperature in the quartz tube67was set at 460° C. in (1c), and the film formation time was set at 110 minutes in (1d). The results were as shown in Table 1. In this example, the crystal defect density on the film forming side surface was smaller than that on the base substrate for film formation side surface. Therefore, when (crystal defect density on bottom surface)/(crystal defect density on top surface) is calculated with the film forming side surface as the top surface and the base substrate for film formation side surface as the bottom surface, it was shown that the calculated values are larger than 1. Example 5 The formation of the α-Ga2O3film and various evaluations were performed in the same manner as in Example 2, except that a composite base substrate prepared as described below was used as the base substrate for film formation, tin (II) chloride dihydrate was added so that the atomic ratio of tin to gallium was 0.7 in (1b′), and the film formation time was set at 280 minutes in (1d). The results were as shown in Table 1. (Preparation of Composite Base Substrate) (a) Preparation of Orientation Precursor Layer An AD film (orientation precursor layer) composed of Cr2O3was formed on a seed substrate (sapphire substrate) by an aerosol deposition (AD) apparatus20shown inFIG.1using Cr2O3powder (Colortherm Green manufactured by Lanxess) as the raw material powder and sapphire (diameter 50.8 mm (2 inches), thickness 0.43 mm, c-plane, off-angle 0.2°) as the substrate. The configuration of the aerosol deposition (AD) apparatus20is as described above. The AD film formation conditions were as follows. That is, N2was used as a carrier gas, and a ceramic nozzle having a slit having a long side of 5 mm and a short side of 0.3 mm was used. The scanning conditions of the nozzle were to move 55 mm in the direction perpendicular to the long side of the slit and forward, to move 5 mm in the long side direction of the slit, to move 55 mm in the direction perpendicular to the long side of the slit and backward, and to move 5 mm in the long side direction of the slit and opposite to the initial position, repeatedly at a scanning speed of 0.5 mm/s, and at the time of 55 mm movement from the initial position in the long side direction of the slit, scanning was performed in the direction opposite to the previous direction, and the nozzle returned to the initial position. This was defined as one cycle, and repeated for 500 cycles. In one cycle of film formation at room temperature, the set pressure of the transport gas was adjusted to 0.06 MPa, the flow rate was adjusted to 6 L/min, and the pressure in the chamber was adjusted to 100 Pa or less. The AD film (orientation precursor layer) thus formed had a thickness of about 100 μm. (b) Heat Treatment of Orientation Precursor Layer The sapphire substrate on which the AD film (orientation precursor layer) was formed was taken out from the AD apparatus and annealed at 1700° C. for 4 hours in a nitrogen atmosphere. (c) Grinding and Polishing The obtained substrate was fixed to a ceramic surface plate, the surface on the side derived from the AD film was ground using a grinding stone having a grit size of #2000 or less until the orientation layer was exposed, and then the plate surface was further smoothed by lapping using diamond abrasive grains. At this time, lapping was performed while gradually reducing the size of the diamond abrasive grains from 3 μm to 0.5 μm, thereby improving the flatness of the plate surface. Thereafter, mirror finishing was performed by chemical mechanical polishing (CMP) using colloidal silica to obtain a composite base substrate having an orientation layer on a sapphire substrate. The surface of the substrate on the side derived from the AD film was designated as the “top surface”. The arithmetical mean roughness Ra of the orientation layer top surfaces after processing was 0.1 nm, the amount of grinding and polishing was 50 μm, and the thicknesses of the composite base substrate after polishing was 0.48 mm. (d) Evaluation of Orientation Layer (d1) Cross-Section EDX The composition of the cross-section orthogonal to the main surface of the substrate was analyzed using an energy dispersive X-ray analyzer (EDX). As a result, only Cr and O were detected in the range from the top surface of the composite base substrate to a depth of about 20 μm. It was found that the ratio of Cr and O did not substantially change in the range of the depth of about 20 μm, and a Cr oxide layer having a thickness of about 20 μm was formed. Further, Cr, O and Al were detected in the range from the Cr oxide layer to a depth of 30 μm, and it was found that a Cr—Al oxide layer (gradient composition layer) having a thickness of about 30 μm was formed between the Cr oxide layer and the sapphire substrate. In the Cr—Al oxide layer, the ratios of Cr and Al were different, and it was observed that the Al concentration was high on the sapphire substrate side and decreased on the side close to the Cr oxide layer. (d2) Surface EBSD An SEM (SU-5000, manufactured by Hitachi High-Technologies Corporation) equipped with an electron backscatter diffraction apparatus (EBSD) (Nordlys Nano, manufactured by Oxford Instruments Inc.) was used to perform reverse pole figure orientation mapping of the top surface of the orientation layer composed of the Cr oxide layer in a field of view of 500 μm×500 μm. The conditions for this EBSD measurement were as follows. <EBSD Measurement Conditions> Acceleration voltage: 15 kVSpot intensity: 70Working distance: 22.5 mmStep size: 0.5 μmSample tilt angle: 70°Measurement program: Aztec (version 3.3) From the obtained reverse pole figure orientation mapping, it was found that the Cr oxide layer was a layer having a biaxially oriented corundum-type crystal structure in which the Cr oxide layer was c-axis oriented in the substrate normal direction and was also oriented in the in-plane direction. From these, it was shown that the orientation layer composed of α-Cr2O3was formed on the substrate top surface. Based on the above results, the preparation step of the composite base substrate is schematically shown inFIGS.5(a) to5(d). (d3) XRD XRD in-plane measurement of the substrate top surface was performed using a multifunctional high-resolution X-ray diffraction (XRD) apparatus (D8 DISCOVER, manufactured by Bruker AXS Inc.). Specifically, after the Z axis was adjusted in accordance with the height of the substrate surface, the axis was set by adjusting Chi, Phi, ω, and 2θ with respect to the (11-20) plane, and 2θ−ω measurement was performed under the following conditions. <XRD Measurement Conditions> Tube voltage: 40 kVTube current: 40 mADetector: Triple Ge (220) AnalyzerCuKα rays converted to parallel monochromatic light (full width at half maximum 28 seconds) with a Ge (022) asymmetric reflection monochromator.Step width: 0.001°Scan speed: 1.0 second/step From the XRD measurement, it was found that the a-axis length of the orientation layer was 4.961 Å. Example 6 The formation of the α-Ga2O3film and various evaluations were performed in the same manner as in Example 5, except that tin (II) chloride dihydrate was added so that the atomic ratio of tin to gallium was 0.2 in (1b′), and the film formation time was set at 600 minutes in (1d). The results were as shown in Table 1. TABLE 1Crystal defect density(104) plane(/cm2)XRC fullFilmFilm formingBase substrate forwidth at halfformationSnFilmsurfacefilm formation sidemaximumtemperatureconcentrationthicknessside surfacesurface (bottomFWHM(° C.)(atom/cm3)(μm)(top surface)surface)(arcsec.)Example 1600—0.7less than 9.9 × 105less than 9.9 × 105127Example 26001.3 × 10191.5less than 9.9 × 105less than 9.9 × 105131Example 3460—2.3less than 9.9 × 1059.9 × 105348Example 44601.1 × 10161.3less than 9.9 × 1052.0 × 106438Example 56001.2 × 10203.2less than 9.9 × 105less than 9.9 × 10562Example 66001.0 × 10197.1less than 9.9 × 105less than 9.9 × 10535 | 63,427 |
11942521 | DETAILED DESCRIPTION To make the figures clear and concise, unless otherwise specified, the same reference numerals in different figures indicate the same components. In addition, to simplify the description, descriptions and details of well-known steps and components may be omitted. Although devices may be described herein as some n-channel or p-channel devices or some n-type or p-type doping devices, it is found through effortful research that, the present invention may also be applied to complementary devices. The word “approximately,” “substantially” or “basically” used herein means that a value of a component has a parameter that is expected to be close to a stated value or position. However, as is well known in the art, there are always small differences that prevent a value or position from being exactly the stated value or position. It is acknowledged in the art that a deviation of up to at least ten percent (10%) (and even to twenty percent (20%) for some components including semiconductor doping concentrations) is a reasonable deviation from an ideal target exactly as described. The terms “first”, “second”, “third”, and the like (as used in part of a component name) in the claims and/or specific embodiments are used to distinguish similar components, and do not necessarily describe an order in time, space, rank, or any other way. It should be understood that, such terms may be interchanged under appropriate circumstances, and the embodiments described herein may be operated in other orders than that described or exemplified herein. The phrase “some embodiments” means that specific features, structures, or characteristics described in combination with the embodiments are included in at least one embodiment of the present invention. Therefore, the phrase “in some embodiments” appearing at different positions throughout this specification does not necessarily refer to the same embodiment, but in some cases, may refer to the same embodiment. In addition, it is apparent to a person of ordinary skill in the art that, in one or more embodiments, specific features, structures, or characteristics may be combined in any appropriate manner. In this specification, the term “lattice constant” is understood to be the lattice constant of the material when its crystal lattice is relaxed. If the material forms a strained heteroepitaxial layer as in case of the second layer deposited on the first layer, its actual in-plane lattice constant deviates from the lattice constant of the material in a relaxed state. The term “in-plane lattice constant” refers to the lattice spacing along the direction substantially parallel to the interface between the first layer and the second layer. The term “epitaxy” refers to any method enabling oriented growth of a single crystalline material on another single crystalline material. The so-called “normal direction” refers to a normal direction of an interface between a first nitride semiconductor layer and a second nitride semiconductor layer of an HEMT device; in some cases, the “normal direction” may alternatively be a normal direction of a flowing direction of two-dimensional electron gas of an HEMT device; and in some cases, the “normal direction” may alternatively be a stacking direction of epitaxial layers. The so-called “tangential direction” refers to a tangential direction of an interface between a first nitride semiconductor layer and a second nitride semiconductor layer of an HEMT device; in some cases, the “tangential direction” may alternatively be a tangential direction of a flowing direction of two-dimensional electron gas of an HEMT device; and in some cases, the “tangential direction” alternatively refers to a direction along a connecting line between a source contact and a drain contact of an HEMT device. The following disclosure provides various embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below. Certainly, the descriptions are merely examples and are not intended to be limiting. In this application, in the following descriptions, the description of the first feature being formed on or above the second feature may include an embodiment formed by direct contact between the first feature and the second feature, and may further include an embodiment in which an additional feature may be formed between the first feature and the second feature to enable the first feature and the second feature to be not in direct contact. In addition, in this application, reference numerals and/or letters may be repeated in examples. This repetition is for the purpose of simplification and clarity, and does not indicate a relationship between the described various embodiments and/or configurations. The embodiments of the present invention are described in detail below. However, it should be understood that many applicable concepts provided by the present invention may be implemented in a plurality of specific environments. The described specific embodiments are only illustrative and do not limit the scope of the present invention. In theory, single crystalline GaN is the ideal substrate for the epitaxial growth of III-nitrides, in particular GaN. However, since bulk GaN, e.g. more than 2 inches (50 mm) in size, is not currently available under industrially viable conditions and has an excessively high cost, sapphire and SiC are other potential substrates for growing III-nitrides. In addition to the cost concern of growing III-nitrides on sapphire or SiC, the major defect of growing III-nitride layers on sapphire or SiC is the presence of the “micropipes” in the epilayers. The micropipes are the defects caused by the formation of screw dislocation during material growth and typically have a diameter of the order of 250 to 500 nm. The density of the micropipes of the order of 3×105to 6×105cm′ has thus been identified. In the aspect of optimizing the cost of the semiconductor devices, the substrate supporting the III-nitrides should be available in a large size (typically greater than or equal to 6 inches (150 mm)) and have a reasonable cost. In this connection, Si is one of the preferred substrates due to its low cost, availability, and suitability for standardized semiconductor processing methods. However, except for the aforementioned advantages, the Si substrate, has two main drawbacks: (1) a significant lattice mismatch with respect to III-nitrides; and (2) a significant mismatch in TECs between Si and III-nitrides. Specifically, for the a Si(111) substrate with a lattice parameter of 3.840 Å, the lattice mismatch between GaN (0001), of which the lattice parameter is 3.189 Å, and Si(111) is 16.9%. The TEC of GaN is 5.6×10−6K−1; whereas that of Si is 2.6×10−6K−1. This represents a TEC mismatch of 53.7%. FIG.1shows the formation of dislocations or cracks in the epilayers and the formation of the substrate warp/bow due to the TEC mismatch between III-nitride layers epitaxially grown on a heterogeneous substrate.FIG.1(a)shows a wafer1with a plurality of III-nitride semiconductor dies (units or chips)19disposed thereon.FIG.1(b)shows a cross-sectional view of the wafer drawn on a tangent plane along the connecting line A-A′ inFIG.1(a)at an elevated temperature for manufacturing the plurality of semiconductor dies. The wafer1is comprises, from bottom to top, a substrate10, a stack of III-nitride epilayers11on the substrate10, and a III-nitride heterojunction12on the stack of III-nitride transition layers11. Since the III-nitride epilayers are grown at elevated temperatures, and as stated above the TEC of a III-nitride epilayer is about two times that of the substrate10, the III-nitride epilayers would elongate more than diameter of the Si wafer so that the wafer1would be convexly bended at an elevated temperature for growing the III-nitride epilayers as shown inFIG.1(b). When the wafer1cools down from an elevated temperature to room temperature, since the contraction rate of the substrate10is lower that and that of the stack of III-nitride transition layers11, on returning to room temperature after epitaxy, the difference in TECs results in a semiconductor device having a considerable concave bow as shown inFIG.1(c). If a GaN-on-Si structure is taken as an example, the Si wafer may apply tensile stress of approximately +1.4 GPa to a GaN epilayer at room temperature. Moreover, the amount of bow increases with increasing thickness of the III-nitride epilayers. Typically, the amount of bow may reach to at least 60 μm. Any further processing would not be possible due to such high amount of bow. For example, the bow of a wafer would result in a non-uniform temperature distribution on the growth surface of a wafer and leads to poor epi quality. The bow of a wafer causes defocus problems in a photolithography process and is disadvantageous to a wafer transfer system operated on the basis of vacuum absorption. Since the process yield is greatly affected by the bow of a wafer, the degree of bow should be kept as low as possible. To relax such huge stress, a great quantity of dislocations or cracks11ais generally formed in the stack of III-nitride transition layers11as shown inFIG.1(c). In other words, TEC mismatch is the source of dislocations or cracks formed in the stack of III-nitride transition layers11to release the stress.FIG.1(d)shows an enlarge view of the dotted region B inFIG.1(c)and reveals the details of the III-nitride heterojunction12. The III-nitride heterojunction12typically comprise a III-nitride layer121as a channel layer on the stack of III-nitride transition layers11, a III-nitride layer122as a barrier layer on the III-nitride layer121, a gate electrode123on the III-nitride layer122, and a source contact124and drain contact125separated by the gate electrode123on the III-nitride layer122. The semiconductor devices can be isolated by the isolations126. The gate electrode123, source contact124, and drain contact125may be covered and/or surrounded by one or more dielectric layers127. In some cases, one or more field plates128can be arranged on the channel region between the gate electrode123and drain contact125to modulate the distribution of the electrical field. The gate electrode123, source contact124, drain contact may be connected to the vias129and metal layers130to provide electrical connections. Due to the lattice discontinuity caused by the dislocations or cracks11apenetrated to the III-nitride heterojunction12, such defects are potentially harmful for device performances (leakage currents, ageing, etc.). Specifically, since the dislocations or cracks11amay serve as energy traps of carries, the concentration of 2DEG in the regions around the dislocations or cracks may be much lower than that of the other regions so that the current density of a HEMT may be decreased. According to the present invention, this concave bow (created by the mismatch of the TECs) can be compensated by the stack of III-nitride transition layers11through an optimized design of the geometry and composition of each of the layers in the stack of III-nitride transition layers11. The novel semiconductor device according to an embodiment of the present invention is provided inFIG.2(a). The semiconductor device100is constructed on a substrate10. A stack of III-nitride transition layers11is disposed on the substrate10. A III-nitride layer121is arranged on the stack of III-nitride transition layers11. Since the stack of III-nitride transition layers11functions to modulate the strain/stress state of the layer disposed thereon, the III-nitride layer121preferably is a stress or stain relaxed epilayer. For HEMT applications, a III-nitride layer122may be optionally arranged on the III-nitride layer122so that The III-nitride layer121and the III-nitride layer122are configured to form two-dimensional electron gas (2DEG)121ain the III-nitride layer121along an interface between the III-nitride layer121and the III-nitride layer122. In this connection, the III-nitride layer121may be considered as a channel layer, whereas the III-nitride layer122may be considered as a barrier layer. A gate electrode123, a source contact124, and a drain contact125may be arranged on the III-nitride layer122. The gate electrode123is positioned between the source contact124and the drain contact15substantially along the tangential direction. FIG.2(b)shows the substrate10suitable for the present invention. The substrate10and the III-nitride layer121should be of heterogeneous materials. For example, if GaN is selected as the material of the III-nitride layer121, the substrate10should be the materials other than GaN. The substrate10may include, but is not limited to, silicon (Si), doped silicon (doped Si), porous silicon, zinc oxide, silicon carbide (4H—SiC or 6H—SiC), silicon-germanium (SiGe) alloy, gallium arsenide (GaAs), sapphire, silicon on an insulator (SOI), SOP SiC (Silicon-on-poly SiC), 3C—SiC/Si(111), or other suitable materials. The substrate10is advantageously a single crystalline substrate, which is available in large sizes (typically greater than 6 inches (150 mm), for example, 8, 10, or 12 inches), inexpensive and suitable for the epitaxial growth of III-nitrides. In this respect, Si is a particularly preferred material. The Si substrate suitable for the present invention can be obtained by using the Czochralski (CZ) method, highly doped with boron (conveyed by a resistivity of less than 5 mΩ·cm), having a thickness of 650 to 1300 μm, provided with or devoid of a flat area. The Si substrate may have a very high boron doping, such that its resistivity is less than 2 mΩ·cm. The Si substrate may be doped with nitrogen, the N concentration being of the order of 5×1014cm−3. With such a very high boron doping and/or nitrogen co-doping, the Si substrate presents a greater yield strength, thereby providing to the grown the subsequent the stack of III-nitride transition layers11a greater compressive strain, which in turn better compensates for the tensile strain during cooling. The Si substrate may have a TEC of 2.6×10−6K−1. As shown inFIG.2(b), the Si substrate preferably has a diamond structure, and thus has two atoms in a primitive cell. The crystal lattice of silicon can be represented as two penetrating face-centered cubic lattices with the cube side a=5.43 Å. The Si substrate is preferably is a Si (111) substrate, such that the growth surface of the Si substrate is (111) facet. On the (111) facet, the lattice parameter of Si may be 3.840 Å. It is noteworthy that the present invention is also applicable to any substrate having the same features as Si in respect of the target applications. The substrate10may be a bulk substrate or formed of an assembly of layers; it may have undergone a structuring method (masking, slicing, etc.), or any chemical and/or physical treatment (surface treatment, implantation, doping, etc.). The stack of III-nitride transition layers11helps to modulate the stress or strain that arises due to lattice and TEC mismatches between the substrate10and the overlying III-nitride layer121. In the absence of the stack of III-nitride transition layers11, the stress is typically accommodated by the generation of misfit dislocations or macroscopic cracks in the epilayers as stated above. Thus, by providing an alternative mechanism for accommodating stress, the presence of the stack of III-nitride transition layers11may reduce the generation of dislocations or cracks. Surprisingly, the stack of III-nitride transition layers11can further promote the generation of favorable stress or strain conditions which can prevent the overlying III-nitride layer121from forming the discloses, cracks or other defects and can reduce warp or bow of the overall semiconductor device100. To modulate the stress or strain state of the overlying III-nitride layer121, the stack of III-nitride transition layers11is disposed on the substrate10. The stack of III-nitride transition layers11takes over the crystal structure of the substrate10. The stack of III-nitride transition layers11maintains an epitaxial relationship to the substrate10. The stack of III-nitride transition layers11may be used to promote lattice match between the substrate10and the overlying III-nitride layer121. It is noteworthy that the stack of III-nitride transition layers11is structurally and functionally different from a conventional super lattice and should be arranged under a conventional super lattice. The stack of III-nitride transition layers11comprises a transition layer111, a transition layer112on the transition layer111, and a transition layer113on the transition layer112. The transition layer111functions to compress the overlying epilayer. As shown inFIG.2(c), the transition layer111is disposed on the substrate10. The transition layer111is in direct contact with the substrate10. The transition layer111may take over the crystal structure of the substrate10. The transition layer111and the substrate10should be of heterogeneous materials. Preferably, the transition layer111comprises AlwGa1-wN, where 0.9≤w≤1. For example, w may be, but not limited to, 0.900, 0.905, 0.910, 0.915, 0.920, 0.925, 0.930, 0.935, 0.940, 0.945, 0.950, 0.955, 0.96, 0.965, 0.970, 0.975, 0.980, 0.985, 0.990, 0.995, or 1.000. The transition layer111is single crystalline. The transition layer111has basic hexagonal symmetry and may be a wurtzite structure. It is noteworthy that the atomic arrangement along the <1-100> axis in a wurtzite structure is similar to the atomic arrangement along the <111> direction in a diamond structure. In this connection, the transition layer111maintains an epitaxial relationship to the substrate10even if the transition layer111and the substrate10are of heterogeneous materials with different crystal structure. To reduce the lattice mismatch between the substrate10and the transition layer111, a coincidence site lattice structure as indicated in the dotted box regions inFIG.2(c)can be formed at the interface between the substrate10and the transition layer111. The coincidence range of the transition layer111to the substrate10can be 10:1 to 1:10, in which the proportion number of the transition layer111can be an integer from 1 to 10; whereas the proportion number of the substrate10can be an integer from 1 to 10. Such a commensurate relationship makes the effective lattice mismatch between the transition layer111and the substrate10greatly reduced to less than or equal to 5%, e.g. 4.5, 4, 3.5, 3, 2.5, 2, 1.5, 1 or 0.5%, compared to the bulk lattice constant mismatch. The transition layer111preferably has an in-plane lattice constant ranging from approximately 3.112 Å to approximately 3.120 Å. For example, the in-plane lattice constant of the transition layer111may be, but not limited to, 3.112, 3.113, 3.114, 3.115, 3.116, 3.117, 3.118, 3.119, or 3.120 Å. Since an epitaxial relationship is established between the transition layer111and substrate10, on returning from an elevated temperature to room temperature after epitaxy, the substrate10gives rise to very high tensile strain to the transition layer111due to the significant difference in TECs between the transition layer111and the substrate10. The transition layer111has a thickness less than that of the transition layer112. The transition layer111has a thickness equal to that of the transition layer112. The transition layer111has a thickness greater than that of the transition layer112. The transition layer111has a thickness less than that of the transition layer113. The transition layer111has a thickness equal to that of the transition layer113. The transition layer111has a thickness greater than that of the transition layer113. The transition layer111has a thickness ranging from approximately 50 nm to approximately 300 nm. For example, the thickness of the transition layer111may be, but not limited to, 50, 60, 80, 100, 120, 140, 150, 160, 180, 200, 220, 240, 250, 260, 280 or 300 nm. As shown inFIG.2(d), the transition layer112is disposed on the transition layer111. The transition layer112is in direct contact with the transition layer111. The transition layer112takes over the crystal structure of the transition layer111. The transition layer112and the transition layer111should be of heterogeneous materials. The transition layer112functions to expand the underlying epilayer (see the arrows inFIG.2(d)). The transition layer112functions to expand the overlying epilayer. Preferably, the transition layer112comprises AlxGa1-xN, where 0.4≤x≤0.8. For example, x may be, but not limited to, 0.40, 0.42, 0.44, 0.45, 0.46, 0.48, 0.50, 0.52, 0.54, 0.55, 0.56, 0.58, 0.60, 0.62, 0.64, 0.65, 0.66, 0.68, 0.70, 0.72, 0.74, 0.75, 0.76, 0.78 or 0.80. The transition layer112has a thickness less than that of the transition layer111. The transition layer112has a thickness equal to that of the transition layer111. The transition layer112has a thickness greater than that of the transition layer111. The transition layer112has a thickness less than that of the transition layer113. The transition layer112has a thickness equal to that of the transition layer113. The transition layer112has a thickness greater than that of the transition layer113. The transition layer112has a thickness ranging from approximately 50 nm to approximately 300 nm. For example, the thickness of the transition layer112may be, but not limited to, 50, 60, 80, 100, 120, 140, 150, 160, 180, 200, 220, 240, 250, 260, 280 or 300 nm. The transition layer112is single crystalline. The transition layer112has basic hexagonal symmetry and may be a wurtzite structure. In this connection, the transition layer112maintains an epitaxial relationship to the transition layer111. The transition layer112has an in-plane lattice constant greater than that of the transition layer111. The transition layer112has an in-plane lattice constant greater than that of the transition layer113. The transition layer112preferably has an in-plane lattice constant ranging from approximately 3.127 Å to approximately 3.158 Å. For example, the in-plane lattice constant of the transition layer112may be, but not limited to, 3.127, 3.128, 3.130, 3.132, 3.134, 3.135, 3.136, 3.138, 3.140, 3.142, 3.144, 3.145, 3.146, 3.148, 3.150, 3.152, 3.154, 3.155, 3.156 or 3.158 Å. Since the in-plane lattice constant of the transition layer112is greater than that of the transition layer111, the translation layer112is subject to compressive stress when grown epitaxially on the transition layer111. Without wishing to be bound to the theory, it is believed that if the transition layer112is grown on the transition layer111, the compressive stress exerted on the transition layer112can be up to several GPa, and thus compensate for the thermally induced tensile stress generated on returning from an elevated temperature to room temperature by the difference in TECs between the III-nitride epilayers and the substrate10. At room temperature, while the transition layer111is subject to high tensile strain, the transition layer112is practically at equilibrium, the compressive stress maintained in the transition layer112having compensated for the thermally induced tensile strain generated during cooling. As shown inFIG.2(e), the transition layer113is disposed on the transition layer112. The transition layer113is in direct contact with the transition layer112. The transition layer113takes over the crystal structure of the transition layer112. The transition layer113and the transition layer112should be of heterogeneous materials. The transition layer113functions to compress the underlying epilayer (see the arrows inFIG.2(e)). The transition layer113functions to compress the overlying epilayer. Preferably, the transition layer113comprises AlyGa1-yN, where 0.4≤y≤0.8. For example, y may be, but not limited to, 0.40, 0.42, 0.44, 0.45, 0.46, 0.48, 0.50, 0.52, 0.54, 0.55, 0.56, 0.58, 0.60, 0.62, 0.64, 0.65, 0.66, 0.68, 0.70, 0.72, 0.74, 0.75, 0.76, 0.78 or 0.80. The transition layer113has a thickness less than that of the transition layer111. The transition layer113has a thickness equal to that of the transition layer111. The transition layer113has a thickness greater than that of the transition layer111. The transition layer113has a thickness less than that of the transition layer112. The transition layer113has a thickness equal to that of the transition layer112. The transition layer113has a thickness greater than that of the transition layer112. The transition layer113has a thickness ranging from approximately 50 nm to approximately 300 nm. For example, the thickness of the transition layer113may be, but not limited to, 50, 60, 80, 100, 120, 140, 150, 160, 180, 200, 220, 240, 250, 260, 280 or 300 nm. The transition layer113is single crystalline. The transition layer113has basic hexagonal symmetry and may be a wurtzite structure. In this connection, the transition layer113maintains an epitaxial relationship to the transition layer112. The transition layer113has an in-plane lattice constant less than that of the transition layer111. The transition layer113has an in-plane lattice constant equal to that of the transition layer111. The transition layer113has an in-plane lattice constant greater than that of the transition layer111. The transition layer112has an in-plane lattice constant less than that of the transition layer112. The transition layer113preferably has an in-plane lattice constant ranging from approximately 3.127 Å to approximately 3.158 Å. For example, the in-plane lattice constant of the transition layer113may be, but not limited to, 3.127, 3.128, 3.130, 3.132, 3.134, 3.135, 3.136, 3.138, 3.140, 3.142, 3.144, 3.145, 3.146, 3.148, 3.150, 3.152, 3.154, 3.155, 3.156 or 3.158 Å. Since the in-plane lattice constant of the transition layer112is greater than that of the transition layer113, the translation layer112is subject to compressive stress when the transition layer113is epitaxially grown on the transition layer112. Without wishing to be bound to the theory, it is believed that if the transition layer113is grown on the transition layer112, the compressive stress exerted on the transition layer112can be up to several GPa, and thus compensate for the thermally induced tensile stress generated on returning elevated temperature to room temperature by the difference in TECs between the III-nitride epilayers and the substrate10. At room temperature, the transition layer113helps to maintain the compressive stress resulted in the transition layer112. The compressive stress functions to compensate for the thermally induced tensile strain generated during cooling. When the stack of III-nitride transition layers11according to the present invention is applied to a heterogeneous substrate10, one of the following design rules may be followed:1. The transition layer111comprises AlwGa1-wN, where 0.9≤w≤1 and has a thickness t111ranging from approximately 50 nm to approximately 300 nm.2. The transition layer111has an in-plane lattice constant a111ranging from approximately 3.112 Å to approximately 3.120 Å and a thickness t111ranging from approximately 50 nm to approximately 300 nm.3. The transition layer112comprises AlxGa1-xN, where 0.4≤x≤0.8 and has a thickness t112ranging from approximately 50 nm to approximately 300 nm.4. The transition layer112has an in-plane lattice constant a112ranging from approximately 3.127 Å to approximately 3.158 Å and a thickness t112ranging from approximately 50 nm to approximately 300 nm.5. The transition layer113comprises AlyGa1-yN, where 0.4≤y≤0.8 and has a thicknesst113ranging from approximately 50 nm to approximately 300 nm.6. The transition layer113has an in-plane lattice constant a113ranging from approximately 3.127 Å to approximately 3.158 Å and a thickness t113ranging from approximately 50 nm to approximately 300 nm.7. The transition layer111comprises AlwGa1-wN, where 0.9≤w≤1. The transition layer112comprises AlxGa1-xN, where 0.4≤x≤0.8. The transition layer111has a thickness till ranging from approximately 50 nm to approximately 300 nm. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. In this case, w>x, t111<t112, 0.25≤w−x≤0.5, and t112−t111≥40 nm8. The transition layer111has an in-plane lattice constant a111ranging from approximately 3.112 Å to approximately 3.120 Å. The transition layer112has an in-plane lattice constant a112ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer111has a thickness t111ranging from approximately 50 nm to approximately 300 nm. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. In this case, a111<a112and t111<t112. The transition layer112may apply tensile stress to the transition layer111at room temperature. In this case, 0.0185≤a112−a111≤0.037, and t112−t111≥40 nm9. The transition layer111comprises AlwGa1-wN, where 0.9≤w≤1. The transition layer113comprises AlyGa1-yN, where 0.4≤y≤0.8. The transition layer111has a thickness t111ranging from approximately 50 nm to approximately 300 nm. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. In this case, w>y, t111<t113, 0.25≤w−y≤0.5, and t113−t111≥100 nm.10. The transition layer111has an in-plane lattice constant a111ranging from approximately 3.112 Å to approximately 3.120 Å. The transition layer113has an in-plane lattice constant a113ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer111has a thickness t111ranging from approximately 50 nm to approximately 300 nm. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. In this case, a111<a113, t111<t113, 0.0185≤a113−a111≤0.037 and t113−t111≥100 nm11. The transition layer112comprises AlxGa1-xN, where 0.4≤x≤0.8. The transition layer113comprises AlyGa1-yN, where 0.4≤y≤0.8. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. In this case, x<y, t112<t113, 0≤x−y≤0.5, and t113−t112≥100 nm.12. The transition layer112has an in-plane lattice constant a112ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer113has an in-plane lattice constant a113ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. In this case, a112>a113and t112<t113. The transition layer113may apply compressive stress to the transition layer112at room temperature. In this case, 0≤a113−a112≤0.037 and t113−t112≥100 nm.13. The transition layers111,112and113may be designed according to the proviso given in Table 1: TABLE 1CompositionThicknessRelation-Relation-AlloyshipRange (nm)shipTransitionAlwGa1-wN,w > x; andt111= 50-300t111< t112<layer 111where 0.9 ≤ w ≤ 1x < yt113TransitionAlxGa1-xN,t112= 50-300layer 112where 0.4 ≤ x ≤ 0.8TransitionAlyGa1-yN,t113= 50-300layer 113where 0.4 ≤ y ≤ 0.814. The transition layers111,112and113may be designed according to the proviso given in Table 2: TABLE 2In-plane lattice constantThicknessRelation-Relation-Range (Å)shipRange (nm)shipTransitiona111= 3.112-3.120a111< a112; andt111= 50-300t111< t112<layer 111a112> a113t113Transitiona112= 3.127-3.158t112= 50-300layer 112Transitiona113= 3.127-3.158t113= 50-300layer 113The transition layer112may apply tensile stress to the transition layer111at room temperature. The transition layer113may apply compressive stress to the transition layer112at room temperature. Accordingly, the present invention overcomes the lattice mismatch and thermal mismatch between the substrate10and the III-nitride layer121by using the stack of III-nitride transition layers11. The present invention thus allows the growth of a high quality III-nitride heterojunction12on a heterogeneous substrate10by using a specially designed strain release structure, i.e., the stack of III-nitride transition layers11. As shown inFIG.2(f), the III-nitride layer121of the III-nitride heterojunction12is then disposed on the stack of III-nitride transition layers11. The III-nitride layer121may serve as the channel layer of the semiconductor device100. Since the III-nitride layer121is grown in a relaxed manner, the III-nitride layer121has a reduced number of dislocations and cracks, preferably is free of dislocations and cracks. The III-nitride layer121may comprise, but being not limited to, InαAlβGa1-α-βN, where α+β≤1, for example, α=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0; β=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0. The III-nitride layer121may comprise, but being not limited to, AlβGa1-βN, where β≤1, for example, β=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0. The thickness of the III-nitride layer121may be, but not limited to 0.3 μm or more, for example 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.2, 1.4, 1.5, 1.6, 1.8, 2, 2.2, 2.4, 2.5, 2.6, 2.8 or 3, preferably 0.5 μm or more. Surprisingly, the III-nitride layer121having a thickness of 0.3 μm or more, preferably 0.5 μm or more that is free of cracks can thus be obtained according to the present invention. The III-nitride layer122of the III-nitride heterojunction12is then disposed on the III-nitride layer121. The III-nitride layer122may serve as the barrier layer of the semiconductor device100. The III-nitride layer122may comprise, but being not limited to, InαAlβGa1-αβN, where α+β≤1, for example, α=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0; β=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0. The III-nitride layer122may comprise, but being not limited to, AlβGa1-βN, where for example, β=0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0. The III-nitride layer122has a band gap energy greater than that of the III-nitride layer121. For example, the III-nitride layer121may include a GaN layer, which has a bandgap of about 3.4 eV. The III-nitride layer122may include Al0.25Ga0.75N, which has a bandgap of about 4 eV. A heterojunction may be formed between the III-nitride layer121and the III-nitride layer122. The 2DEG region121a, as shown by dotted lines, is formed in the III-nitride layer121through polarization of the heterojunction of different nitrides and is generally formed in a layer with a smaller bandgap (for example GaN) to serve as an electron channel region. In the 2DEG region121a, the electron gas may freely move in a two-dimensional direction, and is limited in a three-dimensional direction (for example, substantially in the normal direction of the two-dimensional electron gas). The III-nitride layer121can provide or remove electrons in the 2DEG region, and conduction of the semiconductor device100can be further controlled. If the III-nitride layer122has a higher bandgap, the carrier concentration in the 2DEG region121ais thus increased. A higher carrier concentration of the channel for high-current operation is a very important parameter for high-power devices. If AlGaN is used as a material of the III-nitride layer122, the Aluminium molar ratio may be 20 to 40%. If the Al content is too high, crystalline blocks can be easily formed in the III-nitride layer122, and a problem of stress release of the epitaxial layer may be appeared. The stack of III-nitride transition layers11according to the present invention is suitable for either a gate-first process or a gate-last process. Said gate-first process refers to the case that a gate electrode123is formed before a source contact124and a drain contact125are formed. Said gate-last process refers to the case that a source contact124and a drain contact125are formed before a gate electrode123is formed. The gate electrode123may be formed on the III-nitride layer122, for example, formed on the surface of the III-nitride layer122so as to provide electric connection of the semiconductor device100. The gate electrode123may include a conductive material, for example, but be not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), plumbum (Pb), molybdenum (Mo). The gate electrode123may include the compounds of the aforementioned material, for example, but be not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides, or conductive oxides), metal alloy (such as Al—Cu alloy), or other suitable materials. The gate electrode123may be formed by a single metal or a metal stack (such as tungsten and/or titanium or other well-known electrode materials). The gate electrode123should be configured to form a Schottky junction with the III-nitride layer122to further reduce the gate leakage current. Having generated a practical channel, i.e. the 2DEG region121a, under the gate electrode123, the III-nitride layer121is preset to be in an ON state when the gate electrode123is in a zero-bias state. Such a device may also be known as a depletion mode device. An enhancement mode device is contrary to the depletion mode device. The III-nitride layer121of an enhancement mode device is preset to be in an OFF state when the gate electrode123is in the zero-bias state. To form the enhancement mode device, a doped III-nitride layer (not shown in the figures) is necessarily disposed between the gate electrode123and the III-nitride layer122so as to deplete or remove part of the two-dimensional electron gas121a. It should also be understood by skilled persons that, the two-dimensional electron gas121a, including its depleted region, in the III-nitride layer121forms a channel region of the III-nitride layer121, and flowing of electrons through the channel region is controlled through a gate voltage applied onto the gate electrode123during operation. The doped III-nitride layer and the III-nitride layer122may form a pn junction used to deplete the two-dimensional electron gas121a. Since the pn junction depletes the two-dimensional electron gas121a, when the gate electrode123is in the zero-bias state, no current can passes through the III-nitride layer121, i.e., a threshold voltage of the semiconductor device100is a positive value. The doped III-nitride layer is favorable for reducing the leakage current, and increasing the threshold voltage. The gate electrode123may be in direct contact with the doped III-nitride layer. The gate electrode123may also be electrically connected to the doped III-nitride layer. Substantially in the normal direction, the doped III-nitride layer may be disposed under the gate electrode123, and the gate electrode123may be positioned above the doped III-nitride layer. The gate electrode should be configured to form a Schottky junction with the doped III-nitride layer to further reduce the gate leakage current. In low-voltage application (for example, semiconductor devices applicable to 10 V to 200 V), the gate electrode123may have a width greater than about 0.4 μm substantially in the tangential direction. The width of the gate electrode123may be about 0.4 μm to about 1.2 μm. If the doped III-nitride layer is present, the width of the gate electrode123is smaller than the width of the doped III-nitride layer substantially in the tangential direction. In high-voltage application (for example, semiconductor devices applicable to 200 V or higher), the gate electrode123may have a width greater than about 1.6 μm substantially in the tangential direction. The semiconductor device100may also include a source contact124and a drain contact125, and the source contact124and the drain contact125may be formed into a metal region disposed on the portion of the III-nitride layer122. The material of the source contact124and that of the drain contact125form an ohmic contact with the III-nitride layer122, respectively so as to collect or provide electrons to the 2DEG region121a. The source contact124and the drain contact125may include, for example, but are not limited to, a conductor material. The conductor material may include, for example, but is not limited to, a metal, an alloy, a doped semiconductor material (for example, doped crystalline silicon), or other suitable conductor materials. Metal for forming the source contact124or the drain contact125may include refractory metals or compounds thereof, for example, but not limited to, metals such as aluminum (Al), titanium (Ti), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), hafnium (Hf), ruthenium (Ru), osmium (Os) and iridium (Ir) or compounds of the metals, such as tantalum nitride (TaN), titanium nitride (TiN), and tungsten carbide (WC). The source contact124and the drain contact125may be formed by a single metal or a metal stack (such as tungsten and/or titanium or other well-known electrode materials). Part of the source contact124may be positioned in the III-nitride layer122. Part of the drain contact125may be positioned in the III-nitride layer122. Part of the source contact124may be in direct contact with the 2DEG region121a. Part of the drain contact125may be in direct contact with the 2DEG region121a. The source contact124may be disposed on the III-nitride layer122. The drain contact125may be disposed on the III-nitride layer122. The semiconductor device100of the present invention may further include one or more field plates128(seeFIG.1(d)) on the III-nitride layer122to modulate the electric field nearest to the drain contact125and at a corner position of the gate electrode123, thereby improving the stability of the semiconductor device100and increasing the breakdown voltage between the gate electrode123and the drain contact125. The semiconductor device100may include one, two, three, four or more field plates128. The field plate128may be disposed above the doped III-nitride layer (if present) or the gate electrode123. The field plate128may have a common potential with the source contact124or have a common potential with the gate electrode123. The field plate128may be directly connected to the source contact124. The field plate128may be electrically connected to the source contact124. The field plate128may enable the electric field among the conductor structures (for example, the gate electrode123, source contact124, and drain contact125) to be averagely distributed, and improve the voltage tolerance so as to smoothly release the voltage, thereby further improving the reliability of the device. The field plate128may reduce the electric field of the gate electrode123, and increase the threshold voltage. Typically, the length range of the field plate128in the low-voltage device may be 0.4 to 1.2 μm. An oversized field plate128may increase the capacitance effect between the gate electrode123and the drain contact125, thereby causing negative Miller feedback, and reducing the cut-off frequency of the current gain and the power gain. Additionally, if the field plate128approaches to the drain contact125, the electric field intensity of the field plate128at the end point of the side near the drain contact125may be improved, and the breakdown voltage is further reduced. FIG.3shows a semiconductor device200similar to the semiconductor100described above. The differences reside in that the aluminium molar ratios of the transition layers111′-113′ progressively and discretely decreases along the normal direction from the transition layer111′ to the transition layers113′, such that the in-plane lattice constants of the transition layers a111′-a113′are monotonously increased. Surprisingly, it is found that the absolute value of the stress/strain in the III-nitride layer121of the semiconductor device100is far less that of the semiconductor device200. The degree of substrate bow of the semiconductor device100is far less than that of the semiconductor device200. FIG.4shows a semiconductor device300similar to the semiconductor100according to the present invention. The difference resides in that the transition layer112of the semiconductor device100is replaced by a gradient transition layer112″, of which the aluminium molar ratio progressively and gradually decreases from the interface between the transition layer111and the gradient transition layer112″ to the interface between gradient transition layer112″ and the transition layer113. Surprisingly, it is found that the absolute value of the stress/strain in the III-nitride layer121of the semiconductor device100is far less that of the semiconductor device300. The degree of substrate bow of the semiconductor device100is far less than that of the semiconductor device300. FIG.5shows a semiconductor device400according to an embodiment of the present invention, in which the transition layer111comprises AlN, the transition layer112comprises GaN, and the transition layer113comprises AlN. Surprisingly, it is found that the absolute value of the stress/strain in the III-nitride layer121of the semiconductor device100is far less that of the semiconductor device400. The degree of substrate bow of the semiconductor device100is far less than that of the semiconductor device400. Surprisingly, by adjusting the compositions, in-plane lattice constants, and the thicknesses of the transition layers111-113, a certain amount of stress is generated in the epilayers on a convex bowing wafer at an elevated temperature. The amount of stress that is generated in the epilayers is enough to counterbalance the thermally induced stress generated on returning from an elevated temperature to room temperature by the difference in TECs between the III-nitride epilayers and the substrate10. Structures obtained by means of the present invention preferably have a dislocation density less than or equal to 1×109cm−2, particularly when the thickness of the III-nitride layer121exceeds 1 μm in thickness. FIG.6(a)shows a semiconductor device500according to an embodiment of the present invention. The semiconductor is 500 is similar to the semiconductor device100. The difference resides in that the stack of III-nitride transition layers11further comprises a transition layer114sandwiched between the transition layer113and the III-nitride layer121. As shown inFIG.6(b), the transition layer114is disposed on the transition layer113. The transition layer114is in direct contact with the transition layer113. The transition layer114takes over the crystal structure of the transition layer113. The transition layer114and the transition layer113should be of heterogeneous materials. The transition layer114functions to expend the underlying epilayer (see the arrows inFIG.6(b)). The transition layer114functions to expend the overlying epilayer. Preferably, the transition layer114comprises AlzGa1-zN, where 0.4≤z≤0.8. For example, z may be, but not limited to, 0.40, 0.42, 0.44, 0.45, 0.46, 0.48, 0.50, 0.52, 0.54, 0.55, 0.56, 0.58, 0.60, 0.62, 0.64, 0.65, 0.66, 0.68, 0.70, 0.72, 0.74, 0.75, 0.76, 0.78 or 0.80. The transition layer114has a thickness less than that of the transition layer111. The transition layer114has a thickness equal to that of the transition layer111. The transition layer114has a thickness greater than that of the transition layer111. The transition layer114has a thickness less than that of the transition layer112. The transition layer114has a thickness equal to that of the transition layer112. The transition layer114has a thickness greater than that of the transition layer112. The transition layer114has a thickness less than that of the transition layer113. The transition layer114has a thickness equal to that of the transition layer113. The transition layer114has a thickness greater than that of the transition layer113. The transition layer114has a thickness ranging from approximately 50 nm to approximately 300 nm. For example, the thickness of the transition layer114may be, but not limited to, 50, 60, 80, 100, 120, 140, 150, 160, 180, 200, 220, 240, 250, 260, 280 or 300 nm. The transition layer114is single crystalline. The transition layer114has basic hexagonal symmetry and may be a wurtzite structure. In this connection, the transition layer114maintains an epitaxial relationship to the transition layer113. The transition layer114has an in-plane lattice constant less than that of the transition layer111. The transition layer114has an in-plane lattice constant equal to that of the transition layer111. The transition layer114has an in-plane lattice constant greater than that of the transition layer111. The transition layer114has an in-plane lattice constant less than that of the transition layer112. The transition layer114has an in-plane lattice constant equal to that of the transition layer112. The transition layer114has an in-plane lattice constant greater than that of the transition layer112. The transition layer114has an in-plane lattice constant greater than that of the transition layer113. The transition layer114preferably has an in-plane lattice constant ranging from approximately 3.127 Å to approximately 3.158 Å. For example, the in-plane lattice constant of the transition layer114may be, but not limited to, 3.127, 3.128, 3.130, 3.132, 3.134, 3.135, 3.136, 3.138, 3.140, 3.142, 3.144, 3.145, 3.146, 3.148, 3.150, 3.152, 3.154, 3.155, 3.156 or 3.158 Å. Since the in-plane lattice constant of the transition layer114is greater than that of the transition layer113, the translation layer114is subject to compressive stress when grown epitaxially on the transition layer113. Without wishing to be bound to the theory, it is believed that if the transition layer114is grown on the transition layer113, the compressive stress exerted on the transition layer114can be up to several GPa. Surprisingly, the inventors of the present invention have found that that the compressive generated in the transition layer114can additionally compensates for the thermally induced tensile stress generated on returning from an elevated temperature to room temperature by the difference in TECs between the III-nitride epilayers and the substrate10. When the stack of III-nitride transition layers11additionally comprise the transition layer114, one of the following design rules may be followed:1. The transition layer114comprises AlzGa1-zN, where 0.4≤z≤0.8 and has a thickness t114ranging from approximately 50 nm to approximately 300 nm.2. The transition layer114has an in-plane lattice constant a114ranging from approximately 3.127 Å to approximately 3.158 Å and a thickness t114ranging from approximately 50 nm to approximately 300 nm.3. The transition layer111comprises AlwGa1-wN, where 0.9≤w≤1. The transition layer114comprises AlzGa1-zN, where 0.4≤z≤0.8. The transition layer111has a thickness t111ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, w>z, t111<t114, 0.20≤w-z≤0.5, t111*w≤200, and t114*z≤200.4. The transition layer111has an in-plane lattice constant a111ranging from approximately 3.112 Å to approximately 3.120 Å. The transition layer114has an in-plane lattice constant a114ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer111has a thickness t111ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, a111<a114, t111<t114, a114−a111≥30*(3.189−3.112)/100=0.0231, t111≤200/(100−100*(a111−3.112)/(3.189−3.112)), and t114≤200/(100−100*(a114−3.112)/(3.189−3.112)).5. The transition layer112comprises AlxGa1-xN, where 0.4≤x≤0.8. The transition layer114comprises AlzGa1-zN, where 0.4≤z≤0.8. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, x>z and t112<t114, 0.20≤x−z≤0.5, t112*x≤200, and t114*z≤200.6. The transition layer112has an in-plane lattice constant a112ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer114has an in-plane lattice constant a114ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer112has a thickness t112ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, a112<a114, t112<t114, a114−a112≥20*(3.189−3.112)/100=0.0154, t112≤200/(100−100*(a112−3.112)/(3.189−3.112)), and t114≤200/(100−100*(a114−3.112)/(3.189−3.112)).7. The transition layer113comprises AlyGa1-yN, where 0.4≤y≤0.8. The transition layer114comprises AlzGa1-zN, where 0.4≤z≤0.8. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, y>z, t113<t114, 0.20≤y−z≤0.5, and t113*y≤200, t114*z≤200.8. The transition layer113has an in-plane lattice constant a113ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer114has an in-plane lattice constant a114ranging from approximately 3.127 Å to approximately 3.158 Å. The transition layer113has a thickness t113ranging from approximately 50 nm to approximately 300 nm. The transition layer114has a thickness t114ranging from approximately 50 nm to approximately 300 nm. In this case, a113<a114and t113<t114. The transition layer114may apply tensile stress to the transition layer113at room temperature. In this case, a114−a113≥10*(3.189−3.112)/100=0.0077, t113≤200/(100−100*(a113−3.112)/(3.189−3.112)), t114≤200/(100−100*(a114−3.112)/(3.189−3.112)).9. The transition layers112,113and114may be designed according to the proviso given in Table 3: TABLE 3CompositionThicknessRelation-Relation-AlloyshipRange (nm)shipTransitionAlxGa1-xN,z < x < yt112= 50-300t112< t113<layer 112where 0.4 ≤ x ≤ 0.8t114TransitionAlyGa1-yN,t113= 50-300layer 113where 0.4 ≤ y ≤ 0.8TransitionAlzGa1-zN,t114= 50-300layer 114where 0.4 ≤ z ≤ 0.810. The transition layers112,113and114may be designed according to the proviso given in Table 4: TABLE 4In-plane lattice constantThicknessRelation-Relation-Range (Å)shipRange (nm)shipTransitiona112= 3.127-3.158a113< a112<t112= 50-300t112< t113<layer 112a114t114Transitiona113= 3.127-3.158t113= 50-300layer 113Transitiona114= 3.127-3.158t114= 50-300layer 114The transition layer113may apply compressive stress to the transition layer112at room temperature. The transition layer114may apply tensile stress to the transition layer113at room temperature.11. If the transition layer4is present, The transition layers111,113and114may be designed according to the proviso given in Table 5: TABLE 5CompositionThicknessRelation-Relation-AlloyshipRange (nm)shipTransitionAlwGa1-wN,z < y < wt111= 50-300t111< t113<layer 111where 0.9 ≤ w ≤ 1t114TransitionAlyGa1-yN,t113= 50-300layer 113where 0.4 ≤ y ≤ 0.8TransitionAlzGa1-zN,t114= 50-300layer 114where 0.4 ≤ z ≤ 0.812. The transition layers111,113and114may be designed according to the proviso given in Table 6: TABLE 6In-plane lattice constantThicknessRelation-Relation-Range (Å)shipRange (nm)shipTransitiona111= 3.112-3.120a111< a113<t111= 50-300t111< t113<layer 111a114t114Transitiona113= 3.127-3.158t113= 50-300layer 113Transitiona114= 3.127-3.158t114= 50-300layer 114The transition layer114may apply tensile stress to the transition layer113at room temperature.13. The transition layers111,112and114may be designed according to the proviso given in Table 7: TABLE 7CompositionThicknessRelation-Relation-AlloyshipRange (nm)shipTransitionAlwGa1-wN,z < x < wt111= 50-300t111< t112<layer 111where 0.9 ≤ w ≤ 1t114TransitionAlxGa1-xN,t112= 50-300layer 112where 0.4 ≤ x ≤ 0.8TransitionAlzGa1-zN,t114= 50-300layer 114where 0.4 ≤ z ≤ 0.814. If the transition layer4is present, The transition layers111,112and114may be designed according to the proviso given in Table 8: TABLE 8In-plane lattice constantThicknessRelation-Relation-Range (Å)shipRange (nm)shipTransitiona111= 3.112-3.120a111< a112<t111= 50-300t111< t112<layer 111a114t114Transitiona112= 3.127-3.158t112= 50-300layer 112Transitiona114= 3.127-3.158t114= 50-300layer 114The transition layer112may apply tensile stress to the transition layer111at room temperature.15. If the transition layer4is present, the transition layers111,112,113and114may be designed according to the proviso given in Table 9: TABLE 9CompositionThicknessRelation-Relation-AlloyshipRange (nm)shipTransitionAlwGa1-wN,z < x <t111= 50-300t111< t112<layer 111where 0.9 ≤ w ≤ 1y < wt113< t114TransitionAlxGa1-xN,t112= 50-300layer 112where 0.4 ≤ x ≤ 0.8TransitionAlyGa1-yN,t113= 50-300layer 113where 0.4 ≤ y ≤ 0.8TransitionAlzGa1-zN,t114= 50-300layer 114where 0.4 ≤ z ≤ 0.816. If the transition layer4is present, the transition layers111,112,113and114may be designed according to the proviso given in Table 10: TABLE 10In-plane lattice constantThicknessRange (Å)RelationshipRange (nm)RelationshipTransitiona111= 3.112-3.120a111< a113<t111= 50-300t111< t112<layer 111a112< a114t113< t114Transitiona112= 3.127-3.158t112= 50-300layer 112Transitiona113= 3.127-3.158t113= 50-300layer 113Transitiona114= 3.127-3.158t114= 50-300layer 114The transition layer112may apply tensile stress to the transition layer111at room temperature. The transition layer113may apply compressive stress to the transition layer112at room temperature. The transition layer114may apply tensile stress to the transition layer113at room temperature. FIG.7shows a semiconductor device600according to an embodiment of the present invention. The semiconductor is600is similar to the semiconductor device100. The difference resides in that the semiconductor device600further comprises a superlattice15sandwiched between the stack of III-nitride transition layers11and the III-nitride heterojunction12. The superlattice15may be a plurality of layers or a multi-layer stack, for example an AlGaN/GaN pair or a multi-layer stack of AlN/GaN. Thickness of the each of layers of the super lattice may be less than 20 nm, for example, but being not limited to 1, 2, 4, 5, 6, 8, 10, 12, 14, 15, 16, 18 or 20 nm. The superlattice15may further compensate for the tensile stress or strain during cooling. The superlattice15may also prevent defects (such as dislocations or cracks) from propagating into the III-nitride layers121and122from a layer (such as the transition layers) under the superlattice15, so as to enhance the crystallization quality to the III-nitride layers121and122and avoid the dysfunction of the semiconductor device. The superlattice15may trap electrons diffused from the substrate10to the III-nitride layer121, thereby further improving the efficiency and reliability of the device. In high-voltage application, in order to avoid direct breakdown of the voltage to the substrate10, the superlattice15may increase the integral size of the semiconductor device or structure to increase the breakdown voltage. The total thickness of the superlattice15is generally about 1 μm to 4 μm, and is greater than that of the buffer layer. When the superlattice15is disposed, defects, such as delamination or peeling off, caused by the lattice number and/or TEC difference of the superlattice15from adjacent materials still need to be considered. Additionally, the manufacturing cost will be greatly increased due to use of the superlattice15. In high-voltage application, in order to avoid direct breakdown of the voltage to the substrate10, the buffer layer or the superlattice15may be doped with other heterogeneous elements, for example, but not limited to, carbon, oxygen, or nitrogen, and they may be intentionally doped or unintentionally doped. The composition of each of the transition layers111-113according to the present invention can be characterized by any conventional chemical analysis techniques, such as energy dispersive spectrometer (EDS) or electron energy loss spectroscopy (EELS) used in a TEM. The in-plan lattice constant of each of the transition layers a111, a112, a113can be detected by means of a TEM in high-resolution (HR) mode or an electron selected-area diffraction (SAD) pattern or by means of a high-resolution X-ray diffractometry (HR-XRD). The crystal orientations among the single crystalline layers in a semiconductor device also can be confirmed by means of a TEM or an HR-XRD. Specifically, the crystallinity of each of the epi layers can be confirmed by analyzing the full width at half maximum (FWHM) of the peaks in a HR-XRD ω scan spectrum; whereas the composition of each of the epi layers can be confirmed by analyzing the peaks in a HR-XRD ω-2θ scan spectrum. The thickness of each of the epilayers can be confirmed by analyzing a cross-sectional TEM image. The present invention also provides a method of forming the semiconductor device100. The method comprises the following steps: providing the substrate10; forming the transition layer111on the substrate10at a temperature T1; forming the transition layer112on the transition layer111at a temperature T2; forming the transition layer113on the transition layer112at a temperature T3; forming the III-nitride layer121on the transition layer113; and forming the III-nitride layer122having a band gap energy greater than that of the III-nitride layer121on the III-nitride layer121. Preferably, the temperature T2may be equal to or greater than the first temperature T1. The temperature difference between the temperature T1and the temperature T2may be about 50 to 400° C., for example, but being not limited to 50, 100, 150, 200, 250, 300, 350 or 400° C. Preferably, the temperature T3may be equal to or greater than the temperature T1. The temperature difference between the temperature T3and the temperature T1may be about 50 to 400° C., for example, but being not limited to 50, 100, 150, 200, 250, 300, 350 or 400° C. The method further comprising forming the transition layer114on the transition layer113prior to forming the III-nitride layer121. Preferably, the transition layer114is preferably formed at a fourth temperature greater than the temperature T1. The temperature difference between the fourth temperature and the temperature T1may be about 50 to 400° C., for example, but being not limited to 50, 100, 150, 200, 250, 300, 350 or 400° C. Preferably, the transition layer111may be epitaxially formed on the substrate10. The transition layer112may be epitaxially formed on the transition layer111. The transition layer113may be epitaxially formed on the transition layer112. The III-nitride layer121may be epitaxially formed on the transition layer113. The III-nitride layer122may be epitaxially formed on the III-nitride layer121. In the case that the transition layer114is present, the transition layer114may be epitaxially formed on the transition layer113, and the III-nitride layer121may be epitaxially formed on the transition layer114. The term “epitaxy” thus particularly covers the techniques known as “metalorganic vapor phase epitaxy” (MOVPE), or metalorganic chemical vapor deposition (MOCVD), or molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HYPE). Although MOVPE epitaxy is preferred due to the industrial application thereof, all the epitaxy steps mentioned hereinafter can be implemented using each of these techniques. Optionally, some epitaxy steps are performed using one technique and other steps using another technique. As used herein, for ease of description, space-related terms such as “under”, “below”, “lower portion”, “above”, “upper portion”, “lower portion”, “left side”, “right side”, and the like may be used herein to describe a relationship between one component or feature and another component or feature as shown in the figures. In addition to orientations shown in the figures, space-related terms are intended to encompass different orientations of the device in use or operation. A device may be oriented in other ways (rotated 90 degrees or at other orientations), and the space-related descriptors used herein may also be used for explanation accordingly. It should be understood that when a component is “connected” or “coupled” to another component, the component may be directly connected to or coupled to another component, or an intermediate component may exist. As used herein, terms “approximately”, “basically”, “substantially”, and “about” are used for describing and considering a small variation. When being used in combination with an event or circumstance, the term may refer to a case in which the event or circumstance occurs precisely, and a case in which the event or circumstance occurs approximately. As used herein with respect to a given value or range, the term “about” generally means in the range of ±10%, ±5%, ±1%, or ±0.5% of the given value or range. The range may be indicated herein as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all the ranges disclosed in the disclosure include endpoints. The term “substantially coplanar” may refer to two surfaces within a few micrometers (μm) positioned along the same plane, for example, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm located along the same plane. When reference is made to “substantially” the same numerical value or characteristic, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the values. Several embodiments of the disclosure and features of details are briefly described above. The embodiments described in the disclosure may be easily used as a basis for designing or modifying other processes and structures for realizing the same or similar objectives and/or obtaining the same or similar advantages introduced in the embodiments of the disclosure. Such equivalent constructions do not depart from the spirit and scope of the disclosure, and various variations, replacements, and modifications can be made without departing from the spirit and scope of the disclosure. | 66,309 |
11942522 | DETAILED DESCRIPTION In a related technology, referring toFIG.1toFIG.15, a semiconductor structure may be manufactured by the following operations. A substrate is provided. As shown inFIG.2, the substrate100may include multiple active areas110arranged at intervals. Referring toFIG.1andFIG.2, a third laminated structure700, an intermediate layer800, a fourth laminated structure900and a first photoresist layer300are sequentially formed on the substrate100. The first photoresist layer300is provided with a fifth pattern. Referring toFIG.3andFIG.4, the fourth laminated structure900and the intermediate layer800are etched by taking the first photoresist layer300as a mask, to form a sixth pattern in the intermediate layer800. Referring toFIG.5andFIG.7, the fourth laminated structure900is backfilled on the intermediate layer800, and a second photoresist layer600is formed on the fourth laminated structure900, the second photoresist layer600is provided with a seventh pattern. Referring toFIG.8andFIG.9, the fourth laminated structure900and the intermediate layer800are etched by taking the second photoresist layer600as a mask, to form an eighth pattern. The eighth pattern is not coincided with the sixth pattern. Referring toFIG.10andFIG.11, the third laminated structure700and the substrate100are etched by taking the intermediate layer800as a mask, and a bit line contact area is formed on the substrate100, and the active area110is exposed in the bit line contact area. It can be understood that, a part of the substrate100is etched to expose the active area110, and an area which is not etched in the substrate100is reserved, to form a plurality of protuberances arranged at intervals. However, in the above manufacturing process, the eighth pattern is subject to coincide with the sixth pattern, which results in bridging of patterns on the intermediate layer800, and the reserved third laminated structure700generates bridging as shown in a dotted line ofFIG.12, thereby reducing stability of the semiconductor structure and performance of a semiconductor device. Referring toFIG.13andFIG.14, a bit line400is formed on the substrate100, and the bit line400passes through the protuberance and the active area110. A part of the bit line400is located on the protuberance reserved on the substrate100, as an area L2shown inFIG.13, and this part of bit line400is a penetration bit line. A part of the bit line400is located on the active area110of the substrate100, as an area L1shown inFIG.13, this part of bit line400is an own bit line. However, in a process of forming the bit line400, the protuberance near the bit line400is subject to be damaged, as an area shown in a dotted line ofFIG.15, which reduces stability of the semiconductor structure and performance of the semiconductor device. In order to improve the stability of the semiconductor structure and the performance of the semiconductor device, the embodiments of the disclosure provide a method for manufacturing a semiconductor structure, which may include operations as follows. A first laminated structure and a first photoresist layer are sequentially formed on a substrate. Negative type develop is performed on the first photoresist layer by taking a first mask plate as a mask, to form a first pattern. The first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. The substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess, and form multiple protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances. Negative type develop is performed on the first photoresist layer only once, and the first laminated structure is etched only once to form a required pattern, thereby avoiding an alignment problem caused by double development and etching, and thus improving stability of the semiconductor structure and performance of the semiconductor device. In order to make the above objectives, features and advantages of the embodiments of the disclosure apparent and understandable, the technical solutions in the embodiments of the disclosure are clearly and completely described below in combination with the drawings in the embodiments of the disclosure. It is apparent that the described embodiments are only a part rather than all of the embodiments of the disclosure. On the basis of the embodiments of the disclosure, all other embodiments obtained by those of ordinary skilled in the art without creative work shall fall within the scope of protection of the disclosure. Referring toFIG.16, a method for manufacturing a semiconductor structure in the embodiments of the disclosure may include the following operations S101to S105. At S101, a substrate is provided. Multiple active areas are arranged at intervals in the substrate. Referring toFIG.17andFIG.18, the active area110is arranged in the substrate100. As shown inFIG.18, the active area110is unexposed to a surface of the substrate100. The number of active areas110may be multiple and multiple active areas110are arranged at intervals. Exemplarily, a Shallow Trench Isolation (STI) structure is arranged among the multiple active areas110, and silicon oxide (SiO2) is provided in the STI structure120, to isolate the multiple active areas110from each other. The material of the active area110may include silicon (Si). It should be illustrated that the substrate100may be a Si substrate, and the substrate may also be a germanium (Ge) substrate, a Silicon On Insulator (SOI) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate or a gallium nitride (GaN) substrate and the like. At S102, a first laminated structure and a first photoresist layer are sequentially formed on the substrate. Continuously referring toFIG.17andFIG.18, the first laminated structure200is formed on the substrate100, the first laminated structure200covers the active area110of the substrate100. The first photoresist layer300is formed on the first laminated structure200. The first photoresist layer300covers the first laminated structure200. In a possible example, an insulating layer210, a first conductive layer220, a hard mask layer230, a first mask layer240and a first antireflective layer250are sequentially formed on the substrate100. The insulating layer210is configured to isolate the active area110in the substrate100, and protect the active area110, and the material of the insulating layer210may include one or more of silicon nitride, silicon oxide and silicon oxynitride. The material of the first conductive layer220may include polycrystalline silicon, the material of the hard mask layer230may include one or more of silicon oxide, titanium nitride or silicon nitride, the material of the first mask layer240may include Spin on Hardmask (SOH), and the material of the first antireflective layer may include silicon oxynitride. After the first antireflective layer250is formed, the first photoresist layer300is formed on the first antireflective layer250. The first photoresist layer300may be a phenol-formaldehyde polymer, a chemical structure of the photoresist may be changed by light, and an exposed part of the photoresist or an unexposed part of the photoresist may be removed through a chemical solvent. At S103, negative type develop is performed on the first photoresist layer by taking a first mask plate as a mask, to form a first pattern. Continuously referring toFIG.17andFIG.18, the first mask plate (not shown inFIG.17andFIG.18) is formed on the first photoresist layer300, and negative type develop (NTD) is performed on the first photoresist layer300by taking the first mask plate as the mask. Through NTD, the exposed part in the first photoresist layer300is reserved, and the unexposed part in the first photoresist layer300is removed. Exemplarily, in an NTD process, the exposure time may range from 10 s to 15 s, the NTD time may range from 50 s to 80 s, and negative type develop solution may be Tima90. Through NTD, developing is performed on the first photoresist layer300to form a first pattern. The first pattern has relatively dense graphics. With the above arrangement, a subsequent manufacturing process of the first laminated structure200is reduced, and the efficiency of manufacturing the semiconductor structure is improved on one hand, an alignment problem of double development is avoided on the other hand, to avoiding bridging after the first laminated structure200is etched, thereby improving the stability of the semiconductor structure and the performance of the semiconductor device. In some possible examples, patterns of the first mask plate may be multiple ovals arranged at intervals. Due to the above arrangement, the area of an orthographic projection of the protuberance on the substrate100is reduced, and the area of the bit line contact area is increased, and an adjacent protuberance is prevented from being etched when the bit line is formed subsequently. It can be understood that, compared with a related technology that patterns of the first mask plate are multiple circles arranged at intervals, in the embodiment of the disclosure, when the first photoresist layer300, the first laminated structure200and the substrate100are etched subsequently, the first photoresist layer300forms an oval cylinder, the first laminated structure200forms an oval cylinder, and an oval protuberance is formed on the substrate100. As shown inFIG.19, when a long axis L3of the oval is equal to a radius R of the circle to ensure that the active areas110are separated from each other, the area of the oval is less than the area of the circle. Therefore, the distance between two adjacent ovals is increased, and the possibility of damage to the adjacent protuberance is reduced. At S104, the first laminated structure is etched along the first pattern, to form a second pattern in the first laminated structure. Continuously referring toFIG.17andFIG.18, in a possible example, the first antireflective layer250, the first mask layer240, the hard mask layer230, the insulating layer210and the first conductive layer220are etched along the first pattern. It can be understood that the method may also include removing the first photoresist layer300after etching the first laminated structure200along the first pattern. At S105, the substrate is etched up to a preset depth by taking the first laminated structure having the second pattern as a mask, to form a recess, and form multiple protuberances arranged at intervals on the reserved substrate. The recess surrounds the protuberance, and the active area is exposed between the protuberances. Referring toFIG.20andFIG.21, the substrate100is etched up to a preset depth (H as shown inFIG.21) by taking the first laminated structure200having the second pattern as the mask. As shown inFIG.20andFIG.21, an upper part of the substrate100is etched to form a required pattern, and a lower part of the substrate100is not etched. That is, the lower part of the substrate100is reserved. In a possible example, the preset depth may range from one fifth to one third of the thickness of the substrate100. That is, the recess130is formed in the substrate100, the depth of the recess130ranges from one fifth to one third of the thickness of the substrate100, and the multiple protuberances are arranged at intervals on the reserved substrate100. It can be understood that, in an upper area of the substrate100as shown inFIG.21, an area removed by etching forms the recess130, an area of the substrate100which is not etched forms the protuberance. The recess130is arranged to surround the protuberance, and the active area110is exposed between the protuberances, that is, a part of the bottom of the recess130is the active area110. Furthermore, the protuberance may be a bit line contact, and the bit line is connected with a transistor through the bit line contact. In the same row of protuberances as shown inFIG.20, the active area110is exposed between the adjacent protuberances. The two adjacent active areas110are separated by the protuberance. For example, the protuberance covers a part of the area at two ends of the active area110. The method for manufacturing the semiconductor structure provided by the embodiments of the disclosure may include the following operations. The substrate100provided with the multiple active areas arranged at intervals is provided. The first laminated structure200and the first photoresist layer300are sequentially formed on the substrate100. Negative type develop is performed on the first photoresist layer300by taking a first mask plate as a mask, to form a first pattern. The first laminated structure200is etched along the first pattern, to form a second pattern in the first laminated structure200. The substrate100is etched up to a preset depth by taking the first laminated structure200having the second pattern as a mask, to form a recess130and form multiple protuberances arranged at intervals on the reserved substrate. The recess130surrounds the protuberance, and the active area110is exposed between the protuberances. Compared with a related technology that two photoresist layers are formed, developing is performed on each photoresist layer, and an intermediate layer800is etched twice to form a required pattern, in the embodiments of the disclosure, negative type develop is performed on the first photoresist layer300only once, and the first laminated structure200is etched only once to form a required pattern, thereby avoiding an alignment problem caused by double development and etching, and thus improving stability of the semiconductor structure and performance of the semiconductor device. Moreover, it is not required to backfill the first laminated structure, thereby reducing a manufacturing process, and further decreasing the number of layers in the first laminated structure200, and thus reducing the complexity of the first laminated structure200. A required pattern is transferred to the substrate100through the first laminated structure200, thereby reducing the possibility of bridging between the protuberances, and further improving the stability of the semiconductor structure and the performance of the semiconductor device. It can be understood that, referring toFIG.22andFIG.31, the method may further include the following operations after the substrate is etched up to the preset depth by taking the first laminated structure having the second pattern as the mask to form the recess. Referring toFIG.22andFIG.23, the first antireflective layer250, the first mask layer240and the hard mask layer230are removed to expose the first conductive layer220. As shown inFIG.22andFIG.23, the insulating layer210and the first conductive layer220are sequentially reserved on the substrate100, and the insulating layer210covers the protuberance of the substrate100. Referring toFIG.24andFIG.25, after the first antireflective layer250, the first mask layer240and the hard mask layer230are removed, the recess130is filled with a second conductive layer410, and the second conductive layer410covers the first conductive layer220. As shown inFIG.24andFIG.25, a conductive material is deposited within the recess130and on the first conductive layer220, to form the second conductive layer410. That is, the second conductive layer410fully fills the recess130, covers the substrate100, and covers the first conductive layer220. As shown inFIG.25, an upper surface of the second conductive layer410is flattened. The material of the second conductive layer410may be the same as the material of the first conductive layer220. For example, both the second conductive layer410and the first conductive layer220are polycrystalline silicon. Referring toFIG.26andFIG.27, after the second conductive layer410is formed, a part of the second conductive layer410and the whole first conductive layer220on the insulating layer210are removed, and the reserved second conductive layer410is flush with the insulating layer210. As shown inFIG.26andFIG.27, a part of the second conductive layer410and the whole first conductive layer220departing from the substrate100are removed, to expose the insulating layer210. The upper surface of the insulating layer210is flush with the upper surface of the second conductive layer410, so that the upper surface of the semiconductor structure as shown inFIG.27is flat, which facilitates forming other layers on the surface. As a part of the second conductive layer410and the whole first conductive layer220are removed, there is no second conductive layer410between a second bit line structure (a penetrating bit line) in the bit line400subsequently formed and the substrate100. That is, there is no second conductive layer410between the second bit line structure and the protuberance. Also, the thickness of the second conductive layer410between a first bit line structure (the own bit line) in the bit line400subsequently formed and the substrate100is also be reduced. With the above arrangement, a capacitive contact is formed between the bit lines400in a subsequent process, and the capacitive contact is usually made of a conductive material to be electrically connected to a capacitor. The insulating layer is arranged between the bit line400and the capacitive contact to perform electric isolation. Therefore, the bit line400, the insulating layer and the capacitive contact may form a parasitic capacitance. In the embodiments of the disclosure, as a part of the second conductive layer410is removed, the polar plate area of the parasitic capacitance is reduced, thereby reducing the parasitic capacitance, improving the signal stability of the bit line400, so that the semiconductor structure has better electrical parameters. After a part of the second conductive layer410and the whole first conductive layer220on the insulating layer210are removed, a third conductive layer and a protection layer are sequentially formed on the insulating layer210and the reserved second conductive layer410. The material of the third conductive layer may include one or more of tungsten, titanium, aluminum, nickel, titanium oxide or titanium nitride, and the material of the protection layer may include silicon nitride. As the third conductive layer and the protection layer are formed after the part of the second conductive layer410is removed, in a condition that the third conductive layer and the protection layer are constant in thickness, the height between the upper surface of the protection layer and the upper surface of the substrate100is reduced, which reduces the height of the bit line400subsequently formed, and thus facilitates the stability of the bit line400. It is to be noted that, in a possible example, referring toFIG.28andFIG.29, After the part of the second conductive layer410and the whole first conductive layer220on the insulating layer210are removed, the insulating layer210and a part of the second conductive layer410are also removed, so that the reserved second conductive layer410is flush with the substrate100. As shown inFIG.28andFIG.29, after a part of the second conductive layer410and the whole first conductive layer220on the insulating layer210are removed, the insulating layer210and a part of the second conductive layer410may also be removed, to expose the substrate100. The reserved second conductive layer410is flush with the substrate100. After the insulating layer210and a part of the second conductive layer410are removed, the third conductive layer420and the protection layer430are sequentially formed on the substrate100and the second conductive layer410. Continuously referring toFIG.30andFIG.31, after the third conductive layer420and the protection layer430are formed, a part of the protection layer430, a part of the third conductive layer420and a part of the reserved second conductive layer410are removed, to form multiple bit lines400arranged at intervals. Each of the bit lines400extends along a first direction and passes through the active area and the protuberance. The multiple bit lines400are arranged along a second direction, and the second direction is vertical to the first direction. As shown inFIG.30andFIG.31, a part of the protection layer430, a part of the third conductive layer420and a part of the reserved second conductive layer410are removed, and the reserved protection layer430, the reserved third conductive layer420and the reserved second conductive layer410form the bit line400. As shown inFIG.30, each bit line400passes through the active area110and the protuberance in a vertical direction (Y direction as shown inFIG.30). Each bit line400extends along the first direction, and the multiple bit lines400are arranged along the second direction. Referring toFIG.30, each bit line400extends along the vertical direction, such as the Y direction as shown inFIG.30, and the multiple bit lines400are arranged at intervals along the horizontal direction, such as the X direction as shown inFIG.30. The bit line400may include multiple first bit line structures and multiple second bit line structures, and the first bit line structure and the second bit line structure are alternately arranged along the first direction. The first bit line structure is located on the active area110. As shown inFIG.30, the first bit line structure is located at L1, and the first bit line structure is an own bit line and passes through the active area110. The second bit line structure is located on the protuberance, as shown inFIG.30. The second bit line structure is located at L2, and the second bit line structure is a penetrating bit line and passes through the protuberance. The height of the bit line400may range from 90 to 100 nm, compared with a related technology in which the height of the bit line400ranges from 130 to 140 nm, the height of the bit line400in the embodiments of the disclosure is reduced, thereby improving the stability of the bit line400. It is to be noted that, referring toFIG.32andFIG.33, the step of removing a part of the protection layer430, a part of the third conductive layer420and a part of the reserved second conductive layer410to form multiple bit lines400arranged at intervals may include the following operations. Referring toFIG.32andFIG.33, a second laminated structure500is formed on the protection layer430. In a possible example, the step of forming the second laminated structure500on the protection layer430may include forming a filling layer510, a second antireflective layer520, a second mask layer530and a third antireflective layer540on the protection layer430in sequence. Herein, the material of the filling layer510may include amorphous carbon, the material of the second antireflective layer520and the third antireflective layer540may include silicon oxynitride, and the material of the second mask layer530may include SOH. Continuously referring toFIG.32andFIG.33, after the second laminated structure500is formed, a second photoresist layer600is formed on the second laminated structure500, and positive developing is performed on the second photoresist layer600by taking a second mask plate as a mask, to form a third pattern. As shown inFIG.32, patterns of the second mask plate may be multiple rectangles arranged in parallel. The pattern of the second mask plate corresponds to the active area110and the protuberance. After the third pattern is formed, the second laminated structure500is etched along the third pattern, to form a fourth pattern in the second laminated structure500. The pattern on the second mask plate is transferred onto the second laminated structure500through the second photoresist layer600. After the fourth pattern is formed, the protection layer430, the third conductive layer420and the second conductive layer410are etched by taking the second laminated structure500having the fourth pattern as a mask, and the reserved protection layer430, the reserved third conductive layer420and the reserved second conductive layer410form the bit line400. On one hand, the bit line400is relatively low, and thus has good stability. On the other hand, the second conductive layer410below the bit line400is removed, which reduces the parasitic capacitance of the bit line400. It is to be noted that, as shown inFIG.30andFIG.31, the reserved second laminated structure500is removed after the bit line400is formed. The embodiments of the disclosure further provide a semiconductor structure. As shown inFIG.30andFIG.31, the semiconductor structure may include a bit line400, the bit line400is formed according to the method for manufacturing the semiconductor structure in the above embodiment, and the formed bit line400passes through the protuberance and the active area110of the substrate100, thereby reducing the possibility of bridging between the protuberances, and improving the stability of the semiconductor structure and the performance of the semiconductor device. The height of the formed bit line400is relatively low. For example, the height of the bit line400ranges from 90 to 100 nm. Therefore the bit line400has better stability. Moreover, there is no second conductive layer410between the second bit line structure in the bit line400subsequently formed and the substrate100, that is, there is no second conductive layer410between the second bit line structure and the protuberance, and the thickness of the second conductive layer410between the first bit line structure in the bit line400subsequently formed and the substrate100may also be reduced. With the above arrangement, in a subsequent process, a capacitive contact is formed between the bit lines400, and the capacitive contact is a conductive material, to be electrically connected to a capacitor. The insulating layer is arranged between the bit line400and the capacitive contact to perform electric isolation. Therefore, the bit line400, the insulating layer and the capacitive contact may form parasitic capacitance. In the embodiments of the disclosure, as a part of the second conductive layer410is removed, the polar plate area of the parasitic capacitance is reduced, thereby reducing the parasitic capacitance, improving the signal stability of the bit line400, so that the semiconductor structure has better electrical parameters. Various embodiments or implementation in the specification are described in a progressive way, each of the embodiments focuses on the difference from other embodiments, and regarding same and similar parts among various embodiments, reference may be made to each other. In description of the specification, description of referring terms such as “one embodiment”, “some embodiments”, “a schematic embodiment”, “example”, “a specific example”, or “some examples” refers to that specific features, structures, materials or features described in combination with the embodiments or examples are involved in at least one embodiment or example of the disclosure. In the specification, schematic description on the above terms does not always refer to same embodiment or example. Moreover, the described specific features, structures, materials or features may be combined in any one or more embodiments or examples in a proper manner. Finally, it is to be noted that the above various embodiments are used to illustrate the technical solutions of the disclosure, rather than limiting the technical solution. Although the disclosure has been described in detail with reference to the foregoing various embodiments, those of ordinary skill in the art should understand that the technical solutions described in the foregoing various embodiments may also be modified, or a part or all technical features of the technical solutions are equivalently replaced, but the modifications and replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of various embodiments of the disclosure. | 28,106 |
11942523 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In accordance with some embodiments, source/drain regions for nano-FETs are grown around nanostructures. The source/drain regions are wrapped around all (e.g., four) sides of the nanostructures. Subsequently formed contacts can thus wrap around all (e.g., four) sides of the source/drain regions. The contact area can thus be increased, reducing the contact resistance (RC) of the source/drain contacts and improving the performance of the nano-FETs. FIG.1illustrates an example of simplified nano-FETs, in accordance with some embodiments.FIG.1is a cutaway three-dimensional view, where some features of the nano-FETs are omitted for illustration clarity. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like. The nano-FETs include nanostructures56over a substrate50, such as over fins54extending from the substrate50. The nanostructures56are semiconductor layer that act as channel regions for the nano-FETs. Isolation regions60, such as shallow trench isolation (STI) regions, are disposed over the substrate50and between adjacent ones of the fins54, which may protrude above and from between neighboring isolation regions60. Although the isolation regions60are described/illustrated as being separate from the substrate50, as used herein, the term “substrate” may refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions. Additionally, although the fins54are illustrated as single, continuous materials with the substrate50, the fins54and/or the substrate50may include a single material or a plurality of materials. In this context, the fins54refer to the portion extending above and from between the neighboring isolation regions60. Gate structures100are wrapped around the nanostructures56. The gate structures100include gate dielectrics102and gate electrodes104. The gate dielectrics102are along top surfaces, sidewalls, and bottom surfaces of the nanostructures56and may extend along sidewalls and over top surfaces of the fins54. The gate electrodes104are over the gate dielectrics102. Epitaxial source/drain regions88are wrapped around the nanostructures56and are disposed on opposite sides of the gate structures100. In embodiments where multiple transistors are formed, the epitaxial source/drain regions88may be shared between various transistors. For example, neighboring epitaxial source/drain regions88may be electrically coupled, such as by coupling the epitaxial source/drain regions88with a same source/drain contact. One or more interlayer dielectric (ILD) layer(s) (discussed in greater detail below) are over the epitaxial source/drain regions88and/or the gate structures100, through which contacts (discussed in greater detail below) to the epitaxial source/drain regions88and the gate electrodes104are formed. Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs). FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of a nanostructure56and in a direction, for example, of current flow between the epitaxial source/drain regions88of a nano-FET. Cross-section B-B is perpendicular to cross-section A-A, and is along a longitudinal axis of a gate electrode104. Cross-section C-C is perpendicular to cross-section A-A and parallel to cross-section B-B, and extends through epitaxial source/drain regions88of the nano-FETs. Subsequent figures refer to these reference cross-sections for clarity. FIGS.2through6are three-dimensional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS.2through6show a similar three-dimensional view asFIG.1. InFIG.2, a substrate50is provided for forming nano-FETs. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nano-FETs, and the p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nano-FETs. The n-type region50N may be physically separated from the p-type region50P (not separately illustrated), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. The substrate50may be lightly doped with a p-type or an n-type impurity. An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate50to form an APT region. During the APT implantation, dopants may be implanted in the n-type region50N and the p-type region50P. The dopants may have a conductivity type opposite from a conductivity type of source/drain regions that will be subsequently formed in each of the n-type region50N and the p-type region50P. The APT region may extend under subsequently formed source/drain regions in the nano-FETs, which will be formed in subsequent processes. The APT region may be used to reduce the leakage from the source/drain regions to the substrate50. In some embodiments, the doping concentration in the APT region may be in the range of about 1018cm−3to about 1019cm−3. A multi-layer stack52is formed over the substrate50. The multi-layer stack52includes alternating first semiconductor layers52A and second semiconductor layers52B. The first semiconductor layers52A are formed of a first semiconductor material, and the second semiconductor layers52B are formed of a second semiconductor material. The semiconductor materials may each be selected from the candidate semiconductor materials of the substrate50. In the illustrated embodiment, the multi-layer stack52includes three layers of each of the first semiconductor layers52A and the second semiconductor layers52B. It should be appreciated that the multi-layer stack52may include any number of the first semiconductor layers52A and the second semiconductor layers52B. In the illustrated embodiment, the second semiconductor layers52B will be used to form channel regions for the nano-FETs in both the n-type region50N and the p-type region50P. The first semiconductor layers52A are sacrificial layers (or dummy layers), which will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the second semiconductor layers52B in both regions. The second semiconductor material of the second semiconductor layers52B is a material suitable for both n-type and p-type nano-FETs, such as silicon, and the first semiconductor material of the first semiconductor layers52A is a material that has a high etching selectivity from the etching of the second semiconductor material, such as silicon germanium. In another embodiment, the first semiconductor layers52A will be used to form channel regions for the nano-FETs in one region (e.g., the p-type region50P), and the second semiconductor layers52B will be used to form channel regions for the nano-FETs in another region (e.g., the n-type region50N). The first semiconductor material of the first semiconductor layers52A may be suitable for p-type nano-FETs, such as silicon germanium (e.g., SixGe1-x, where x can be in the range of 0 to 1), pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like, and the second semiconductor material of the second semiconductor layers52B may be suitable for n-type nano-FETs, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material may have a high etching selectivity from the etching of one another, so that the first semiconductor layers52A may be removed without removing the second semiconductor layers52B in the n-type region50N, and the second semiconductor layers52B may be removed without removing the first semiconductor layers52A in the p-type region50P. Each of the layers of the multi-layer stack52may be formed using a process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Each of the layers may be formed to a small thickness, such as a thickness in a range of about 5 nm to about 30 nm. In some embodiments, one group of layers (e.g., the second semiconductor layers52B) is formed to be thinner than the other group of layers (e.g., the first semiconductor layers52A). For example, in embodiments where the second semiconductor layers52B are used to form channel regions and the first semiconductor layers52A are sacrificial layers (or dummy layers), the first semiconductor layers52A can be formed to a first thickness T1and the second semiconductor layers52B can be formed to a second thickness T2, with the second thickness T2being from about 30% to about 60% less than the first thickness T1. Forming the second semiconductor layers52B to a smaller thickness allows the channel regions to be formed at a greater density. InFIG.3, trenches are etched in the substrate50and the multi-layer stack52to form fins54and nanostructures56. The fins54are semiconductor strips patterned in the substrate50. The nanostructures56include the remaining portions of the multi-layer stack52on the fins54. Specifically, nanostructures56include alternating first nanostructures56A and second nanostructures56B. The first nanostructures56A and the second nanostructures56B are formed of remaining portions of the first semiconductor layers52A and the second semiconductor layers52B, respectively. After formation, the second nanostructures56B in the intermediate levels of the structure are each disposed between two of the first nanostructures56A. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The fins54and the nanostructures56may be patterned by any suitable method. For example, the fins54and the nanostructures56may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins54and the nanostructures56. The fins54and the nanostructures56may have widths in a range of about 8 nm to about 40 nm. The fins54and the nanostructures56in the n-type region50N and the p-type region50P are illustrated as having substantially equal widths for illustrative purposes. In some embodiments, the fins54and the nanostructures56in one region (e.g., the n-type region50N) may be wider or narrower than the fins54and the nanostructures56in the other region (e.g., the p-type region50P). InFIG.4, STI regions60are formed adjacent the fins54. The STI regions60may be formed by depositing an insulation material over the substrate50and the nanostructures56and between adjacent ones of the fins54. The insulation material may be an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by an FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material is formed such that excess insulation material covers the nanostructures56. Although the insulation material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner may first be formed along surfaces of the substrate50, the fins54, and the nanostructures56. Thereafter, a fill material, such as those discussed above may be formed over the liner. A removal process is then applied to the insulation material to remove excess insulation material over the nanostructures56. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the nanostructures56such that top surfaces of the nanostructures56and the insulation material are coplanar (within process variations) after the planarization process is complete. The insulation material is then recessed to form the STI regions60. The insulation material is recessed such that the upper portions of the fins54protrude from between neighboring STI regions60. In the illustrated embodiment, the top surfaces of the STI regions60are below the top surfaces of the fins54. In some embodiments, the top surfaces of the STI regions60are above or coplanar (within process variations) with the top surfaces of the fins54. Further, the top surfaces of the STI regions60may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions60may be formed flat, convex, and/or concave by an appropriate etch. The STI regions60may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material (e.g., etches the material of the insulation material at a faster rate than the materials of the fins54and the nanostructures56). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. The process described above is just one example of how the fins54and the nanostructures56may be formed. In some embodiments, the fins54and the nanostructures56may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins54and the nanostructures56. The epitaxial structures may include the alternating semiconductor materials discussed above, such as the first semiconductor material and the second semiconductor material. In embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and/or subsequent implantations, although in situ and implantation doping may be used together. Further, appropriate wells may be formed in the substrate50, the fins54, and/or the nanostructures56. In some embodiments, a p-type well may be formed in the n-type region50N, and a n-type well may be formed in the p-type region50P. In another embodiment, p-type wells or n-type wells may be formed in both the n-type region50N and the p-type region50P. In embodiments with different well types, different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist or other masks. For example, a photoresist may be formed over the fins54, the nanostructures56, and the STI regions60in the n-type region50N. The photoresist is patterned to expose the p-type region50P. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration in the range of about 1013cm−3to about 1014cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following the implanting of the p-type region50P, a photoresist is formed over the fins54, the nanostructures56, and the STI regions60in the p-type region50P. The photoresist is patterned to expose the n-type region50N. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration in the range of about 1013cm−3to about 1014cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.5, a dummy dielectric layer62is formed on the fins54and the nanostructures56. The dummy dielectric layer62may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer64is formed over the dummy dielectric layer62, and a mask layer66is formed over the dummy gate layer64. The dummy gate layer64may be deposited over the dummy dielectric layer62and then planarized, such as by a CMP. The mask layer66may be deposited over the dummy gate layer64. The dummy gate layer64may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer64may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer64may be made of material(s) that have a high etching selectivity from the etching of insulation materials, e.g., the material(s) of the STI regions60and/or the dummy dielectric layer62. The mask layer66may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer64and a single mask layer66are formed across the n-type region50N and the p-type region50P. Although the dummy dielectric layer62is shown covering the STI regions60, it should be appreciate that the dummy dielectric layer62can be formed in other manners. In some embodiments, such as when the dummy dielectric layer62is thermally grown, the dummy dielectric layer62is formed to only cover the fins54and the nanostructures56. InFIG.6, the mask layer66is patterned using acceptable photolithography and etching techniques to form masks76. The pattern of the masks76is then transferred to the dummy gate layer64by an acceptable etching technique to form dummy gates74. The pattern of the masks76may optionally be further transferred to the dummy dielectric layer62by an acceptable etching technique to form dummy dielectrics72. The dummy gates74cover portions of the nanostructures56that will be exposed in subsequent processing to form channel regions. Specifically, the dummy gates74extend along the portions of the second nanostructures56B that will be used to form channel regions58(seeFIG.7A). The pattern of the masks76may be used to physically separate adjacent dummy gates74. The dummy gates74may also have lengthwise directions substantially perpendicular (within process variations) to the lengthwise directions of the fins54. The masks76can optionally be removed after patterning, such as by an acceptable etching technique. FIGS.7A through20Care cross-sectional views of further intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments.FIGS.7A,8A,9A,10A,11A,12A,13A,14A,15A,16A,17A,18A,19A, and20Aare illustrated along reference cross-section A-A inFIG.1.FIGS.7B,8B,9B,10B,11B,12B,13B,14B,15B,16B,17B,18B,19B, and20Bare illustrated along reference cross-section B-B inFIG.1, except two fins are shown.FIGS.7C,8C,9C,10C,11C,12C,13C,14C,15C,16C,17C,18C,19C, and20Care illustrated along reference cross-section C-C inFIG.1, except two fins are shown.FIGS.7A through20Cmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure. InFIGS.7A,7B, and7C, gate spacers80are formed over the nanostructures56and the fins54, on exposed sidewalls of the masks76, the dummy gates74, and the dummy dielectrics72. The gate spacers80may be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material of the gate spacers80may be silicon nitride, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or the like, and may be formed by thermal oxidation, deposition, a combination thereof, or the like. The gate spacers80can be formed from a singled-layered insulating material or multiple layers of insulating materials. In some embodiments, the gate spacers80include multiple layers of silicon oxycarbonitride, where each layer may have a different composition of silicon oxycarbonitride. In some embodiments, the gate spacers80include a layer of silicon oxide disposed between two layers of silicon nitride. Other spacer structures may be formed. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as RIE, NBE, or the like. After etching, the gate spacers80can have straight sidewalls or curved sidewalls. The dry etching process is performed so that the insulating material on the sidewalls of the nanostructures56(and optionally the fins54) is removed. For example, the dry etching process can be performed for a duration in the range of about 1 seconds to about 15 seconds to remove the insulating material from the sidewalls of the nanostructures56. In the embodiment shown, the insulating material is also removed from the sidewalls of the fins54so that no material of the gate spacers80remains over the STI regions60. In another embodiment, some insulating material can remain on the sidewalls of the fins54but not on the sidewalls of the nanostructures56. Before the formation of the gate spacers80, implants for lightly doped source/drain (LDD) regions82may be performed. In the embodiments with different device types, similar to the implants discussed above, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the nanostructures56and the fins54exposed in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the nanostructures56and the fins54exposed in the n-type region50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities previously discussed, and the p-type impurities may be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in the range of about 1015cm−3to about 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. During the implanting, the channel regions58remain covered by the dummy gates74, so that the channel regions58remain substantially free from the impurity implanted in the LDD regions82. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., additional spacers may be formed and removed, etc.), and/or the like. Furthermore, the n-type and p-type devices may be formed using a different structures and steps. InFIGS.8A,8B, and8C, portions of the first nanostructures56A are removed to form source/drain openings84. Specifically, the portions of the first nanostructures56A laterally uncovered by the gate spacers80and the dummy gates74are removed to expose the top and bottom surfaces of the second nanostructures56B, such as the top and bottom surfaces of the LDD regions82. The source/drain openings84thus extend laterally between sidewalls of the fins54, as shown byFIG.8C. The portions of the first nanostructures56A can be removed by an acceptable etching process that selectively etches the material of the first nanostructures56A at a faster rate than the material(s) of the second nanostructures56B and the fins54. The etching may be isotropic. For example, when the fins54and the second nanostructures56B are formed of silicon and the first nanostructures56A are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. Because the gate spacers80do not extend along sidewalls of the nanostructures56, the first nanostructures56A can be completely removed in the cross-section ofFIG.8C. InFIGS.9A,9B, and9C, inner spacers86are optionally formed on the sidewalls of the remaining portions of the first nanostructures56A, e.g., those sidewalls expose by the source/drain openings84. As will be discussed in greater detail below, source/drain regions will be subsequently formed in the source/drain openings84, and the first nanostructures56A will be subsequently replaced with corresponding gate structures. The inner spacers86act as isolation features between the subsequently formed source/drain regions and the subsequently formed gate structures. Further, the inner spacers86may be used to prevent damage to the subsequently formed source/drain regions by subsequent etching processes, such as etching processes used to subsequently form the gate structures. As an example to form the inner spacers86, the source/drain openings84can be expanded. Specifically, portions of the sidewalls of the first nanostructures56A exposed by the source/drain openings84may be recessed. Although sidewalls of the first nanostructures56A are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by an acceptable etching process that selectively etches the material of the first nanostructures56A at a faster rate than the material(s) of the second nanostructures56B and the fins54. The etching may be isotropic. For example, when the fins54and the second nanostructures56B are formed of silicon and the first nanostructures56A are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas such as hydrogen fluoride. In some embodiments, the same etching process may be continually performed to both form the source/drain openings84and recess the sidewalls of the first nanostructures56A. The inner spacers86can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material may be a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The insulating material may be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etch such as RIE, NBE, or the like. Although outer sidewalls of the inner spacers86are illustrated as being flush with respect to the sidewalls of the gate spacers80, the outer sidewalls of the inner spacers86may extend beyond or be recessed from the sidewalls of the gate spacers80. In other words, the inner spacers86may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the inner spacers86are illustrated as being straight, the sidewalls of the inner spacers86may be concave or convex. InFIGS.10A,10B, and10C, the portions of the second nanostructures56B and the fins54exposed by the source/drain openings84are optionally trimmed. The trimming reduces the dimensions (e.g., thicknesses and widths) of the exposed portions of the second nanostructures56B (e.g., the LDD regions82), with the unexposed portions of the second nanostructures56B (e.g., the channel regions58) retaining their original dimensions. The unexposed portions of the second nanostructures56B are those portions covered by the gate spacers80and the dummy gates74. The unexposed portions of the fins54are those portions extending above the STI regions60. For example, the trimming may reduce the thicknesses of the exposed portions of the second nanostructures56B from the second thickness T2(discussed above with respect toFIG.2) to a third thickness T3, with the third thickness T3being in a range of about 3 nm to about 15 nm, and the third thickness T3being from about 25% to about 40% less than the second thickness T2. Similarly, the trimming may reduce the widths of the exposed portions of the fins54and the second nanostructures56B from a first width W1to a second width W2, with the first width W1being in a range of about 5 nm to about 20 nm, the second width W2being in a range of about 3 nm to about 15 nm, and the second width W2being from about 25% to about 50% less than the first width W1. After the trimming, the second nanostructures56B have a first perimeter in the cross-section ofFIG.10B(e.g., twice the sum of the second thickness T2and the first width W1) and have a second perimeter in the cross-section ofFIG.10C(e.g., twice the sum of the third thickness T3and the second width W2), with the second perimeter being smaller than the first perimeter. The trimming expands the source/drain openings84so that they can accommodate larger source/drain regions for the nano-FETs. The exposed portions of the second nanostructures56B and the fins54may be trimmed by an acceptable etching process that selectively etches the material(s) of the second nanostructures56B and the fins54at a faster rate than the materials of the first nanostructures56A, the inner spacers86, and the gate spacers80. The etching may be isotropic. For example, when the fins54and the second nanostructures56B are formed of silicon and the first nanostructures56A are formed of silicon germanium, the etching process may be a wet etch using a diluted ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), or the like. When the trimming process is omitted, the channel regions58and the LDD regions82can each have the same thickness. InFIGS.11A,11B, and11C, epitaxial source/drain regions88are formed in the source/drain openings84and around the exposed/trimmed portions of the second nanostructures56B (e.g., the LDD regions82). After formation, the epitaxial source/drain regions88are wrapped around four sides (e.g., top surfaces, sidewalls, and bottom surfaces) of the second nanostructures56B. The epitaxial source/drain regions88thus completely surround the second nanostructures56B in the cross-section ofFIG.11C. The epitaxial source/drain regions88can also optionally be formed on exposed/trimmed portions of the fins54, so that a first subset of the epitaxial source/drain regions88A are wrapped around the second nanostructures56B and a second subset of the epitaxial source/drain regions88B extend along the fins54. The epitaxial source/drain regions88are formed in the source/drain openings84such that respective groups of the epitaxial source/drain regions88are disposed between neighboring pairs of the dummy gates74. In some embodiments, the gate spacers80and the inner spacers86are used to separate the epitaxial source/drain regions88from the dummy gates74and the first nanostructures56A by an appropriate lateral distance so that the epitaxial source/drain regions88do not short out subsequently formed gates of the nano-FETs. The epitaxial source/drain regions88may be formed in contact with the inner spacers86(if present). When the nanostructures56B are trimmed, the epitaxial source/drain regions88can exert stress on the channel regions58, thereby improving performance. The epitaxial source/drain regions88in the n-type region50N may be formed by masking the p-type region50P. Then, the epitaxial source/drain regions88are epitaxially grown in the source/drain openings84in the n-type region50N. The epitaxial source/drain regions88may include any acceptable material appropriate for n-type nano-FETs. For example, the epitaxial source/drain regions88in the n-type region50N may include materials exerting a tensile strain on the channel regions58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions88in the n-type region50N may have surfaces raised from respective surfaces of the second nanostructures56B and the fins54, and may have facets. The epitaxial source/drain regions88in the p-type region50P may be formed by masking the n-type region50N. Then, the epitaxial source/drain regions88are epitaxially grown in the source/drain openings84in the p-type region50P. The epitaxial source/drain regions88may include any acceptable material appropriate for p-type nano-FETs. For example, the epitaxial source/drain regions88in the p-type region50P may include materials exerting a compressive strain on the channel regions58, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions88in the p-type region50P may also have surfaces raised from respective surfaces of the second nanostructures56B and the fins54, and may have facets. The epitaxial source/drain regions88, the second nanostructures56B, and/or the fins54may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of about 1019cm−3to about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions88may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions88, upper surfaces of the epitaxial source/drain regions88have facets which expand laterally outward beyond surfaces of the second nanostructures56B and the fins54. In embodiments where no material of the gate spacers80remains over the STI regions60, the epitaxial source/drain regions88B can extend along and contact the STI regions60. The epitaxial source/drain regions88are formed to a thickness T4that is selected so the epitaxial source/drain regions88do not merge during the epitaxy process. In some embodiments, the thickness T4of the epitaxial source/drain regions88is up to about one quarter of the original thickness T1(discussed above with respect toFIG.2) of the first nanostructures56A. For example, the thickness T4can be in the range of about 5 nm to about 15 nm. Forming the epitaxial source/drain regions88to a thickness T4in this range allows merging of the epitaxial source/drain regions88to be avoided. Forming the epitaxial source/drain regions88to a thickness T4outside of this range may not allow merging of the epitaxial source/drain regions88to be avoided. Avoiding merging of the epitaxial source/drain regions88allows subsequently formed source/drain contacts to wrap around all (e.g., four) sides of the epitaxial source/drain regions88A, thereby increasing the contact area and reducing the contact resistance (RC) of the source/drain contacts. The epitaxial source/drain regions88may include one or more semiconductor material layers. For example, the epitaxial source/drain regions88may include first semiconductor material layers, second semiconductor material layers, and third semiconductor material layers. Any number of semiconductor material layers may be used for the epitaxial source/drain regions88. Each of the first semiconductor material layers, the second semiconductor material layers, and the third semiconductor material layers may be formed of different semiconductor materials and/or may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layers may have a dopant concentration that is less than the second semiconductor material layers and greater than the third semiconductor material layers. When the epitaxial source/drain regions88include three semiconductor material layers, the first semiconductor material layers may be grown from the second nanostructures56B and the fins54, the second semiconductor material layers may be grown from the first semiconductor material layers, and the third semiconductor material layers may be grown from the second semiconductor material layers. InFIGS.12A,12B, and12C, dummy layers92are formed on and around the epitaxial source/drain regions88. The dummy layers92are wrapped around four sides (e.g., top surfaces, sidewalls, and bottom surfaces) of the epitaxial source/drain regions88A and are wrapped around three sides (e.g., top surfaces and sidewalls) of the epitaxial source/drain regions88B. Specifically, a dummy layer92is formed around each group of epitaxial source/drain regions88disposed between neighboring dummy gates74. The dummy layers92fill the remaining portions of the source/drain openings84that are not filled by the epitaxial source/drain regions88. The dummy layers92may be formed of a dielectric material such as silicon carbonitride, silicon oxynitride, or silicon oxycarbonitride, although other suitable dielectric materials may be utilized. Notably, the dummy layers92are formed of a dielectric material that has a high etching selectivity from the etching of a subsequently formed ILD. The dummy layers92are so named because they will be removed in a subsequent process for forming source/drain contacts through the subsequently formed ILD. The dummy layers92may be deposited by a conformal deposition process, such as ALD, CVD, or the like. As an example to form the dummy layers92, the dielectric material of the dummy layers92may be conformally deposited around the epitaxial source/drain regions88and over the gate spacers80and the masks76, such as by ALD. A removal process is then applied to remove excess of the dielectric material over the gate spacers80and the masks76. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the gate spacers80and the masks76such that top surfaces of the dielectric material, the gate spacers80, and the masks76are coplanar (within process variations) after the planarization process is complete. The dielectric material is then recessed to form the dummy layers92. The top surfaces of the dummy layers92are recessed below the top surfaces of the masks76, and can be recessed below the top surfaces of the dummy gates74. InFIGS.13A,13B, and13C, a first ILD94is deposited over the dummy layers92, the gate spacers80, and the masks76. The first ILD94may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, an etch stop layer is formed between the dummy layers92and the first ILD94. The etch stop layer may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the first ILD94. InFIGS.14A,14B, and14C, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD94with the top surfaces of the dummy gates74or the masks76. The planarization process may also remove the masks76on the dummy gates74, and portions of the gate spacers80along sidewalls of the masks76. After the planarization process, the top surfaces of the first ILD94, the gate spacers80, and the masks76(if present) or the dummy gates74are coplanar (within process variations). Accordingly, the top surfaces of the masks76(if present) or the dummy gates74are exposed through the first ILD94. In the illustrated embodiment, the masks76remain, and the planarization process levels the top surface of the first ILD94with the top surfaces of the masks76. InFIGS.15A,15B, and15C, the masks76(if present) and the dummy gates74are removed in an etching process, so that recesses96are formed. Portions of the dummy dielectrics72in the recesses96may also be removed. In some embodiments, the dummy gates74are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates74at a faster rate than the first ILD94or the gate spacers80. During the removal, the dummy dielectrics72may be used as etch stop layers when the dummy gates74are etched. The dummy dielectric dielectrics72may then be removed after the removal of the dummy gates74. Each recess96exposes and/or overlies portions of the channel regions58in the second nanostructures56B. Portions of the second nanostructures56B which act as the channel regions58are disposed between neighboring pairs of the epitaxial source/drain regions88. The remaining portions of the first nanostructures56A are then removed to expand the recesses96. The remaining portions of the first nanostructures56A can be removed by an acceptable etching process that selectively etches the material of the first nanostructures56A at a faster rate than the materials of the second nanostructures56B, the fins54, and the STI regions60. The etching may be isotropic. For example, when the fins54and the second nanostructures56B are formed of silicon and the first nanostructures56A are formed of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. InFIGS.16A,16B, and16C, gate dielectrics102and gate electrodes104are formed for replacement gates. The gate dielectrics102are deposited conformally in the recesses96, such as on top surfaces and sidewalls of the fins54and on top surfaces, sidewalls, and bottom surfaces of the second nanostructures56B. The gate dielectrics102may also be deposited on top surfaces of the first ILD94, the gate spacers80, and the STI regions60. In accordance with some embodiments, the gate dielectrics102comprise silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectrics102include a high-k dielectric material, and in these embodiments, the gate dielectrics102may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation methods of the gate dielectrics102may include molecular-beam deposition (MBD), ALD, PECVD, and the like. The gate electrodes104are deposited over the gate dielectrics102, respectively, and fill the remaining portions of the recesses96. The gate electrodes104may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although single layered gate electrodes104are illustrated, the gate electrodes104may comprise any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of the layers which make up the gate electrodes104may be deposited in the areas between each of the second nanostructures56B and between the fins54and the second nanostructures56B. After the filling of the recesses96, a planarization process, such as a CMP, may be performed to remove the excess portions of the materials of the gate dielectrics102and the gate electrodes104, which excess portions are over the top surface of the first ILD94and the gate spacers80. The remaining portions of the materials of the gate dielectrics102and the gate electrodes104thus form replacement gates of the resulting nano-FETs. The gate dielectrics102and the gate electrodes104may be collectively referred to as gate structures100or “gate stacks.” The formation of the gate dielectrics102in the region50N and the region50P may occur simultaneously such that the gate dielectrics102in each region are formed from the same materials, and the formation of the gate electrodes104may occur simultaneously such that the gate electrodes104in each region are formed from the same materials. In some embodiments, the gate dielectrics102in each region may be formed by distinct processes, such that the gate dielectrics102may be different materials, and/or the gate electrodes104in each region may be formed by distinct processes, such that the gate electrodes104may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. InFIGS.17A,17B, and17C, source/drain contact openings106are formed through the first ILD94. The source/drain contact openings106may be formed using acceptable photolithography and etching techniques, such as with an etching process that is selective to the first ILD94(e.g., etches the material of the first ILD94at a faster rate than the material of the dummy layers92). During the etching, the dummy layers92may be used as etch stop layers so that the source/drain contact openings106expose the dummy layers92. InFIGS.18A,18B, and18C, the dummy layers92are removed to expand the source/drain contact openings106and expose the epitaxial source/drain regions88. Removing the dummy layers92exposes all the exterior surfaces (e.g., top surfaces, sidewalls, and bottom surfaces) of the epitaxial source/drain regions88. The dummy layers92may be removed using an acceptable etching process, such as one that is selective to the dummy layers92(e.g., etches the material of the dummy layers92at a faster rate than the material of the first ILD94). InFIGS.19A,19B, and19C, silicides108are formed in the source/drain contact openings106and on the epitaxial source/drain regions88. The silicides108are wrapped around the epitaxial source/drain regions88. The silicides108may be formed by depositing a metal layer in the source/drain contact openings106and performing an anneal process. The metal layer may be conformally formed on the top surfaces of the first ILD94, the sidewalls of the first ILD94, and all of the surfaces (e.g., top surfaces, sidewalls, and bottom surfaces) of the epitaxial source/drain regions88. The metal layer may formed of titanium, cobalt, tungsten, or the like, and may be deposited by any suitable method, such as ALD, PVD, CVD, and PECVD. In some embodiments, a liner is also formed in the source/drain contact openings106. The liner may be a diffusion barrier layer, an adhesion layer, or the like, and may help prevent the metal layer from diffusing into the first ILD94during annealing. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The metal layer and optionally the liner are then annealed to form the silicides108. The silicides108are physically and electrically coupled to the epitaxial source/drain regions88. Excess portions of the metal layer and/or the liner may then be removed by an acceptable etching process. Lower source/drain contacts112A are then formed in the source/drain contact openings106. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the source/drain contact openings106. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the first ILD94. The remaining liner and conductive material in the source/drain contact openings106forms the lower source/drain contacts112A. The lower source/drain contacts112A are physically and electrically coupled to the silicides108. InFIGS.20A,20B, and20C, a second ILD114is deposited over the first ILD94. The second ILD114may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), or the like; nitrides such as silicon nitride; or the like. After formation, the second ILD114can be planarized, such as by a CMP. In some embodiments, an etch stop layer is formed between the first ILD94and the second ILD114. The etch stop layer may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the second ILD114. Upper source/drain contacts112B and gate contacts116are then formed extending through the second ILD114. Openings for the upper source/drain contacts112B and the gate contacts116are formed through the second ILD114. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner may be deposited by a conformal deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. The conductive material may be deposited by ALD, CVD, PVD, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD114. The remaining liner and conductive material in the source/drain contact openings106forms the upper source/drain contacts112B and the gate contacts116. The upper source/drain contacts112B are physically and electrically coupled to the lower source/drain contacts112A, and the gate contacts116are physically and electrically coupled to the gate electrodes104. The upper source/drain contacts112B and the lower source/drain contacts112A may be collectively referred to as source/drain contacts112. After formation, the lower source/drain contacts112A physically contact the gate spacers80and the inner spacers86, and have portions disposed between the epitaxial source/drain regions88of a same column. In this embodiment, the source/drain contacts112include first conductive features (e.g., the lower source/drain contacts112A) extending through the first ILD94, and include second conductive features (e.g., the upper source/drain contacts112B) extending through the second ILD114. The source/drain contacts112and the gate contacts116may be formed in different processes, or may be formed in the same process. Although the source/drain contacts112and the gate contacts116are illustrated in the same cross-section, the contacts may be formed in different cross-sections, which may avoid shorting of the contacts. FIGS.21through23are cross-sectional views of intermediate stages in the manufacturing of nano-FETs, in accordance with some embodiments. As will be discussed in greater detail below,FIGS.21through23illustrate a contact cut process, where adjacent lower source/drain contacts112A are separated from one another by forming a dielectric feature between the adjacent lower source/drain contacts112A.FIGS.21through23are illustrated along reference cross-section C-C inFIG.1, except four fins are shown.FIGS.7A through20Cmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure. InFIG.21, a structure at a similar state of processing as that described with respect toFIG.12Cis obtained.FIG.21illustrates a first group of the fins54(e.g., at the left-hand side of the page) and a second group of the fins54(e.g., at the right-hand side of the page) over the substrate50. Each group of the fins54may be used to form a nano-FET. A cut opening98is formed in the dummy layer92. The cut opening98may be formed using acceptable photolithography and etching techniques. After formation, the cut opening98exposes underlying insulation materials, e.g., the STI regions60. The cut opening98is formed between the first group and the second group of the fins54, and defines where a dielectric feature will be formed between subsequently formed source/drain contacts to the nano-FET. InFIG.22, the first ILD94is formed and planarized, using a similar process as that described with respect toFIGS.13A through14C. The first ILD94is formed in the cut opening98and above the dummy layer92. Thus, the first ILD94includes a lower region94A (e.g., in the cut opening98) and an upper region (e.g., above the dummy layer92)94B. InFIG.23, the lower source/drain contacts112A, the second ILD114, and the upper source/drain contacts112B are formed, using a similar process as that described with respect toFIGS.17A through20C. After formation, the lower region94A of the first ILD94is thus a dielectric feature that separates the neighboring lower source/drain contacts112A. It should be appreciated thatFIGS.21through23illustrate an example contact cut process. Other dielectric features could be formed separating the neighboring lower source/drain contacts112A. For example, a dielectric feature formed of a different material than the first ILD94and the dummy layer92may be formed between the neighboring lower source/drain contacts112A. In the embodiments described above, neighboring epitaxial source/drain regions88(e.g., epitaxial source/drain regions88disposed over different fins54) are electrically coupled with a same source/drain contact112. In other words, each lower source/drain contact112A is coupled to multiple columns of epitaxial source/drain regions88. In another embodiment (discussed in greater detail below), neighboring epitaxial source/drain regions88can each be coupled to a different respective source/drain contact112. FIG.24is a cross-sectional view of nano-FETs, in accordance with some other embodiments. This embodiment is similar to that described with respect toFIG.23, except neighboring epitaxial source/drain regions88are each coupled to a different lower source/drain contact112A. In other words, each lower source/drain contact112A is coupled to one column of epitaxial source/drain regions88. FIGS.25A,25B, and25Care cross-sectional view of nano-FETs, in accordance with some other embodiments. This embodiment is similar to that described with respect toFIGS.20A,20B, and20C, except the source/drain contacts112are continuous conductive features that extend through both the first ILD layer94and the second ILD layer114. The nano-FETs according to this embodiment may be formed by obtaining a structure at a similar state of processing as that described with respect toFIGS.16A,16B, and16C, and then forming the second ILD layer114over the first ILD layer94before forming the source/drain contact openings106. After the second ILD layer114is formed, the source/drain contact openings106can be formed through both of the second ILD layer114and the first ILD layer94and the dummy layers92can be removed, using a similar process as that described with respect toFIGS.17A through18C. The source/drain contacts112can then be formed in the source/drain contact openings106, using a similar process as that described with respect toFIGS.19A,19B, and19C. It should be appreciated that the embodiment described with respect toFIGS.25A,25B, and25Ccould be combined with features from the embodiments described with respect toFIGS.21through24. For example, the source/drain contacts112ofFIGS.25A,25B, and25Ccould be coupled to one or multiple columns of epitaxial source/drain regions88. Likewise, a contact cut process could be performed on the source/drain contacts112ofFIGS.25A,25B, and25C. Embodiments may achieve advantages. Forming the source/drain contacts112by forming and removing the dummy layers92allows the source/drain contacts112to extend around all (e.g., four) sides of the epitaxial source/drain regions88. The contact area for the source/drain contacts112can thus be increased, reducing the contact resistance (RC) of the source/drain contacts112and improving the performance of the nano-FETs. Specifically, the source/drain contacts112can have a similar contact resistance for the epitaxial source/drain regions88that are disposed proximate to the substrate50and the epitaxial source/drain regions88that are disposed distal the substrate50. In an embodiment, a method includes: patterning a plurality of semiconductor layers to form a first nanostructure, a second nanostructure, and a third nanostructure, the second nanostructure disposed between the first nanostructure and the third nanostructure; doping a first region of the second nanostructure with an impurity while covering a second region of the second nanostructure; removing portions of the first nanostructure and the third nanostructure to expose the top and the bottom of the first region of the second nanostructure; growing an epitaxial source/drain region around the top and the bottom of the first region of the second nanostructure; and forming a gate stack around the top and the bottom of the second region of the second nanostructure. In some embodiments, the method further includes: before growing the epitaxial source/drain region, trimming the first region of the second nanostructure to reduce a thickness of the first region of the second nanostructure. In some embodiments of the method, after trimming the first region of the second nanostructure, the thickness of the first region of the second nanostructure is less than the thickness of the second region of the second nanostructure. In some embodiments, the method further includes: after growing the epitaxial source/drain region, depositing a dummy layer around the top and the bottom of the epitaxial source/drain region; depositing an interlayer dielectric (ILD) layer on the dummy layer; etching the ILD layer to form a first opening exposing the dummy layer; and etching the dummy layer to expand the first opening and expose the epitaxial source/drain region. In some embodiments, the method further includes: depositing a metal layer in the first opening and around the epitaxial source/drain region; annealing the metal layer to form a silicide around the epitaxial source/drain region; and depositing a conductive material in the first opening to form a source/drain contact around the silicide. In some embodiments of the method, the dummy layer includes a first dielectric material, the ILD layer includes a second dielectric material, etching the ILD layer includes etching the second dielectric material at a faster rate than the first dielectric material, and etching the dummy layer includes etching the first dielectric material at a faster rate than the second dielectric material. In some embodiments of the method, the first dielectric material is silicon carbonitride and the second dielectric material is silicon oxide. In some embodiments, the method further includes: before depositing the ILD layer, etching a second opening in the dummy layer, where depositing the ILD layer includes depositing a portion of the ILD layer in the second opening. In some embodiments, the method further includes: forming the semiconductor layers over a substrate; patterning the substrate to form a fin, the second nanostructure disposed over the fin; and before growing the epitaxial source/drain region, trimming an upper portion of the fin. In some embodiments of the method, forming the gate stack includes: removing remaining portions of the first nanostructure and the third nanostructure to expose the top and the bottom of the second region of the second nanostructure; depositing a gate dielectric around the top and the bottom of the second region of the second nanostructure; and forming a gate electrode on the gate dielectric. In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region. In some embodiments of the device, the first LDD region has a first thickness, the channel region has a second thickness, and the second thickness is greater than the first thickness. In some embodiments of the device, the first LDD region and the channel region have a same thickness. In some embodiments, the device further includes: a second nanostructure over the substrate, the second nanostructure including a second LDD region; and a second epitaxial source/drain region wrapped around four sides of the second LDD region, the source/drain contact wrapped around four sides of the second epitaxial source/drain region. In some embodiments, the device further includes: a first spacer disposed between the gate stack and the first epitaxial source/drain region, the source/drain contact physically contacting the first spacer; and a second spacer disposed between the gate stack and the second epitaxial source/drain region, the source/drain contact physically contacting the second spacer. In some embodiments of the device, the source/drain contact has a first portion and a second portion, the first portion extending through the ILD layer, the second portion disposed between the first epitaxial source/drain region and the second epitaxial source/drain region, the second portion having a greater width than the first portion. In an embodiment, a device includes: a nanostructure over a substrate, the nanostructure including a channel region and a lightly doped source/drain (LDD) region, the LDD region adjacent the channel region, the channel region having a first width and a first thickness in a first cross-section, the LDD region having a second width and a second thickness in a second cross-section, the second width being less than the first width, the second thickness being less than the first thickness, the first cross-section and the second cross-section each being perpendicular to a longitudinal axis of the nanostructure; a gate stack completely surrounding the channel region in the first cross-section; and an epitaxial source/drain region completely surrounding the LDD region in the second cross-section. In some embodiments, the device further includes: an interlayer dielectric (ILD) layer over the epitaxial source/drain region; and a source/drain contact extending through the ILD layer, the source/drain contact completely surrounding the epitaxial source/drain region in the second cross-section. In some embodiments, the device further includes: a silicide between the source/drain contact and the epitaxial source/drain region, the silicide completely surrounding the epitaxial source/drain region in the second cross-section. In some embodiments, the device further includes: an isolation region over the substrate; and a fin having a first portion and a second portion, the first portion extending through the isolation region, the second portion extending above the isolation region, the nanostructure disposed over the fin, the first portion of the fin having a third width, the second portion of the fin having a fourth width, the second width and the fourth width being less than the third width. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 70,011 |
11942525 | PREFERRED EMBODIMENT OF THE PRESENT INVENTION The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Certainly, these descriptions are merely examples and are not intended to be limiting. In the present disclosure, in the following descriptions, the description of the first feature being formed on or above the second feature may include an embodiment formed by direct contact between the first feature and the second feature, and may further include an embodiment in which an additional feature may be formed between the first feature and the second feature to enable the first feature and the second feature to not be in direct contact. In addition, in the present invention, reference numerals and/or letters may be repeated in examples. This repetition is for the purpose of simplification and clarity, and does not indicate a relationship between the described various embodiments and/or configurations. The embodiments of the present disclosure are described in detail below. However, it should be understood that many applicable concepts provided by the present disclosure may be implemented in a plurality of specific environments. The described specific embodiments are only illustrative and do not limit the scope of the present disclosure. FIG.1Ais a cross-sectional view of a semiconductor device100according to some embodiments of the present disclosure. The semiconductor device100includes a semiconductor heterostructure layer110and a conductive structure130. According to some embodiments of the present disclosure, the semiconductor device100further includes a buffer layer140and a carrier150. The carrier150may be a semiconductor substrate, a glass substrate, a PCB substrate, a flexible substrate (for example, a polymer or paper) or any medium capable of carrying the semiconductor heterostructure layer110. The buffer layer140may be further provided between the semiconductor heterostructure layer110and the carrier150. In some embodiments, a buffer layer140is formed between a semiconductor material layer111and the carrier150. In some embodiments, the buffer layer140may be of a superlattice structure consisting of AlGaN and GaN. The thickness of the buffer layer140is in a range of about 0.5 μm to 10 μm. The semiconductor heterostructure layer110includes a stack of alternating semiconductor material layers111and semiconductor material layers112. The semiconductor material layers111and the semiconductor material layers112are formed by semiconductor materials with different energy gaps, so that 2DHGs (not shown) can be generated between each semiconductor material layer111and its adjacent semiconductor material layer112. The semiconductor material layers111and the semiconductor material layers112are formed by the semiconductor materials with different energy gaps. Through piezoelectricity, the 2DHGs are formed at interfaces of the semiconductor material layers111and the semiconductor material layers112under the dual effects of spontaneous polarization and piezoelectric polarization. Compared with the semiconductor material layers112, the semiconductor material layers111have wider energy gap. For example, in an embodiment, the semiconductor material layers111are AlGaN, and the energy gap is about 4 eV; and the semiconductor material layers112are GaN, and the energy gap is about 3.4 eV. According to some embodiments of the present disclosure, the semiconductor material layers111and the semiconductor material layers112may respectively include group III-V compounds. A combination of the semiconductor material layers111and the semiconductor material layers112may include, but is not limited to, one of the following: a combination of AlGaN and GaN, a combination of InAlN and GaN, a combination of AlN and GaN, and a combination of InAlGaN and GaN. In an embodiment, the thickness of the semiconductor heterostructure layer110is in a range of 8 nm to 1000 nm. In an embodiment, the thickness of each semiconductor material layer111in the semiconductor heterostructure layer110is in a range of 2 nm to 30 nm. In an embodiment, the thickness of each semiconductor material layer111is in a range of 3 nm to 10 nm. The thickness of the semiconductor material layer112in the semiconductor heterostructure layer110may be greater than or equal to that of the semiconductor material layer111. In an embodiment, the thickness of each semiconductor material layer112in the semiconductor heterostructure layer110is in a range of 2 nm to 70 nm. In an embodiment, the thickness of each semiconductor material layer112is in a range of 3 nm to 20 nm. In some embodiments, an interposer layer (not shown in the figures) may be provided between the semiconductor material layers111and the semiconductor material layers112. The interposer layer may include AlN, and the thickness may be about 1 nm. According to the present disclosure, the 2DHGs between the semiconductor material layers111and the semiconductor material layers112provide multiple channels for the semiconductor device to transfer electron holes and form a multichannel heterostructure device. In some embodiments, the 2DHGs between the semiconductor material layers111and the semiconductor material layers112in the semiconductor heterostructure layer110include at least 2 layers. In preferred embodiments, the number of layers of the 2DHGs is in a range of 2 to 10. The conductive structure130includes conductive fingers131,132, and133. The conductive fingers131,132, and133are arranged in a direction substantially parallel to a surface110aof the semiconductor heterostructure layer110. End portions131E,132E, and133E of each conductive finger are positioned at different depths in the semiconductor material layers112, and are not in contact with the 2DHGs. In the present embodiment, the conductive structure130includes 3 conductive fingers131,132, and133. However, according to the present disclosure, the number of conductive fingers may be any integer greater than or equal to 2, and is not limited to the above embodiments. According to some preferred embodiments of the present disclosure, the conductive structure130may include 2 to 10 conductive fingers. In some embodiments, the number of conductive fingers is associated with the number of interfaces between the semiconductor material layers111and the semiconductor material layers112. TakingFIG.1Aas an example, the number of interfaces between the semiconductor material layers111and the semiconductor material layers112and the number of conductive fingers are both three. According to other embodiments, both the number of interfaces between the semiconductor material layers111and the semiconductor material layers112and the number of conductive fingers may be four, five, or other integers. The conductive fingers may be arranged in a direction X as shown inFIG.1A. Additionally, the lengths of the conductive fingers131,132, and133extending deep into the semiconductor heterostructure layer110gradually increase in the direction X. That is, the conductive finger131is the shortest, the conductive finger132is medium-length, and the conductive finger133is the longest. However, in other embodiments, the conductive fingers131,132, and133may also be arranged in other directions substantially parallel to the surface110a. Additionally, the lengths of the conductive fingers131,132, and133extending deep into the semiconductor heterostructure layer110may gradually increase in the arrangement direction. In some embodiments of the present disclosure, the widths of the conductive fingers are substantially identical. In some preferred embodiments of the present disclosure, the widths of the conductive fingers are increased along with their length. For example, inFIG.1A, the lengths of the conductive fingers131,132, and133gradually increase in the direction X, and the widths are also gradually increased in the direction X. In some preferred embodiments, the lengths of the conductive fingers are in a range of 1 nm to 1000 nm, and the widths are in a range of 5 nm to 800 nm. In some more preferred embodiments, the lengths of the conductive fingers are in a range of 1 nm to 300 nm, and the widths are in a range of 5 nm to 200 nm. FIG.1Bis a schematic diagram of flow of electron holes in the semiconductor device100in a two-dimensional hole gas channel. As shown inFIG.1B, the two-dimensional hole gases (2DHGs) can be generated between each semiconductor material layer111and its adjacent semiconductor material layer112. Therefore, a plurality of 2DHGs115,117, and119are generated at different depths (a direction Z as shown inFIG.1B) of the semiconductor heterostructure layer110. These 2DHGs115,117, and119extend along the interfaces of the semiconductor material layers111and the semiconductor material layers112. When the semiconductor device electrically connects to a power supply, the electron holes can flow in the 2DHG channels to form electron hole flowing paths. According to the embodiment inFIG.1B, the electron holes in the 2DHGs115,117, and119all flow in the direction X. In a position approaching any one conductive finger, the electron holes will enter the conductive finger through ohmic contact between the approached conductive finger and the semiconductor material layer112. For example, in the 2DHG115closest to the surface110a, the electron holes can first flow through a position near the conductive finger131. When approaching the conductive finger131, the electron holes mainly enter the conductive finger131through the ohmic contact between the conductive finger131and the semiconductor material layer112. The electron hole flowing path at that point is shown inFIG.1Bas HP1. In the second-layer 2DHG117below the surface110a, the electron holes can first flow through a position near the conductive finger132. When approaching the conductive finger132, the electron holes mainly enter the conductive finger132through the ohmic contact between the conductive finger132and the semiconductor material layer112. The electron hole flowing path at that point is represented by HP2. Accordingly, in the 2DHG119farthest from the surface110a, the electron holes can first flow through a position near the conductive finger133. When approaching the conductive finger133, the electron holes mainly enter the conductive finger133through the ohmic contact between the conductive finger133and the semiconductor material layer112. The electron hole flowing path at that point is represented by HP3. The electron holes flowing in the 2DHGs115,117, and119at different depths can enter the conductive structure130through the conductive fingers131,132, and133at different depths, so that dispersion of electron holes can be achieved. The conductive finger according to the present disclosure can be formed by a one-layer or multilayer conductive material. Taking the conductive finger inFIG.1Aas an example, it is formed by a single kind of metal material. In some embodiments, the conductive finger may include one of the following conductive materials: titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), nickel (Ni), copper (Cu), titanium nitride (TiN), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof. However, the conductive finger used in the present disclosure is not limited to the embodiment inFIG.1A. For example, in the embodiment inFIG.2, a conductive finger230may include a metal material layer230aand a metal material layer230b. The metal material layer230bis in contact with the semiconductor heterostructure layer110. The metal material layer230ais formed on the metal material layer230b. The metal material layer230bmay be a single or multiple metal material layer. The metal material layer230bmay include at least one of the following: nickel (Ni), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof. The metal material layer230amay include at least one of the following: a titanium (Ti), aluminum (Al), copper (Cu), aurum (Au), platinum (Pt), palladium (Pd), and a tungsten (W) layer. The metal material layer230acan reduce resistance of the conductive finger230. FIG.3is a cross-sectional view of a semiconductor device300according to some embodiments of the present disclosure. The semiconductor device300includes a semiconductor heterostructure layer110and a conductive structure330. The conductive structure330includes conductive fingers331,332, and333. In some embodiments, the conductive fingers331,332, and333may be formed by a one-layer or multilayer metal material, and may include trenches. That is, the centers of the conductive fingers331,332, and333are not completely filled with metal materials. The conductive fingers331,332, and333may include at least one of the following: titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), nickel (Ni), copper (Cu), titanium nitride (TiN), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof. In some embodiments, the conductive fingers may include a single or multiple metal material layers and a nickel (Ni) layer between the single or multiple metal material layer and the semiconductor heterostructure layer110. FIG.4is a cross-sectional view of a semiconductor device400according to a comparative embodiment. The semiconductor device400includes a semiconductor heterostructure layer110and a conductive structure430. Some elements in the semiconductor device400are represented by the same numerals as those of the semiconductor device100inFIG.1, and are made of similar materials, so detailed description thereof will not be repeated herein. The conductive structure430includes a conductive finger431extending from a surface of the semiconductor heterostructure layer110in a direction Z towards the semiconductor heterostructure layer110. When entering the conductive finger431, electron holes in 2DHGs are crowded near an interface of the 2DHGs and the conductive finger. i.e., current crowding can occur when the electron holes enter or leave the interface of the conductive finger431. Further, the temperature rises, it becomes harder for heat to dissipate, and electrical performance of the semiconductor device400is further reduced. FIG.5is a cross-sectional view of a semiconductor device500according to another comparative embodiment. The semiconductor device500includes a semiconductor heterostructure layer110and a conductive structure530. Some elements in the semiconductor device500are represented by the same numerals as those of the semiconductor device100inFIG.1, and are made of similar materials, so detailed description thereof will not be repeated herein. The conductive structure530is formed on a surface of the semiconductor heterostructure layer110, is in direct contact with the semiconductor heterostructure layer110, and forms an ohmic contact surface with the surface of the semiconductor heterostructure layer110. However, electron holes in the semiconductor heterostructure layer110mainly flow in 2DHG channels. 2DHGs, particularly the 2DHGs farther from the conductive structure530, have high resistance with the conductive structure530, and this will cause the semiconductor device500to form high ohmic resistance. FIG.6Ais a cross-sectional view of a semiconductor device600according to some embodiments of the present disclosure. The semiconductor device600includes a semiconductor heterostructure layer110, a drain structure620, a source structure630, and a gate structure640. According to some embodiments of the present disclosure, the semiconductor device600further includes a buffer layer140and a carrier150. Some elements in the semiconductor device600are represented by the same numerals as those of the semiconductor device100inFIG.1, and are made of similar materials, so detailed description thereof will not be repeated herein. The gate structure640is disposed between the drain structure620and the source structure630to control flow of electron holes between the drain structure620and the source structure630and further control on-off of the semiconductor device600. The drain structure620includes conductive fingers621,622, and623. The conductive fingers621,622, and623are arranged substantially in a direction parallel to a surface110aof the semiconductor heterostructure layer110. End portions621E,622E, and623E of each conductive finger of the drain structure620are positioned in the semiconductor material layers112at different depths, and are not in contact with 2DHGs. In the present embodiment, the drain structure620includes 3 conductive fingers. However, according to the present disclosure, the number of conductive fingers of the drain structure620may be any integer greater than or equal to 2, and is not limited to the above embodiments. According to some preferred embodiments of the present disclosure, the drain structure620may include 2 to 10 conductive fingers. In other preferred embodiments, the number of conductive fingers is associated with the number of interfaces between the semiconductor material layers111and the semiconductor material layers112. According to some embodiments of the present disclosure, the conductive fingers may be arranged in a direction X as shown inFIG.6A. Additionally, the lengths of the conductive fingers621,622, and623extending deep into the semiconductor heterostructure layer110gradually increase in the direction X. That is, the conductive finger621is the shortest, the conductive finger622is medium-length, and the conductive finger623is the longest. However, in other embodiments, the conductive fingers621,622, and623of the drain structure620may also be arranged in other directions substantially parallel to the surface110a. In this case, the lengths of the conductive fingers621,622, and623of the drain structure620extending deep into the semiconductor heterostructure layer110may gradually increase in the arrangement direction. In some preferred embodiments of the present disclosure, the width of each conductive finger is substantially identical. In some preferred embodiments of the present disclosure, the widths of the conductive fingers increase along with their length. For example, inFIG.6A, the lengths of the conductive fingers621,622, and623of the drain structure620gradually increase in the direction X, and the widths thereof also gradually increase in the direction X. In some preferred embodiments, the lengths of the conductive fingers of the drain structure are in a range of 1 nm to 1000 nm, and the widths are in a range of 5 nm to 800 nm. In some more preferred embodiments, the lengths of the conductive fingers of the drain structure are in a range of 1 nm to 300 nm, and the widths are in a range of 5 nm to 200 nm. The source structure630includes conductive fingers631,632, and633. The conductive fingers631,632, and633are arranged substantially in a direction parallel to the surface110aof the semiconductor heterostructure layer110. End portions631E,632E, and633E of each conductive finger of the source structure630are positioned in the semiconductor material layers112at different depths, and are not in contact with the 2DHGs. In the present embodiment, the source structure630includes 3 conductive fingers. However, according to the present disclosure, the number of conductive fingers of the source structure630may be any integer greater than or equal to 2, and is not limited to the above embodiments. According to some preferred embodiments of the present disclosure, the source structure630may include 2 to 10 conductive fingers. In some preferred embodiments, the number of conductive fingers is associated with the number of interfaces between the semiconductor material layers111and the semiconductor material layers112. Additionally, the conductive fingers631,632, and633may be arranged in the direction X as shown inFIG.6A. Additionally, the lengths of the conductive fingers631,632, and633extending deep into the semiconductor heterostructure layer110gradually decrease in the direction X. That is, the conductive finger631is the shortest, the conductive finger632is medium-length, and the conductive finger633is the longest. However, in other embodiments, the conductive fingers631,632, and633of the source structure630may also be arranged in other directions substantially parallel to the surface110a. In this case, the lengths of the conductive fingers631,632, and633of the source structure630extending deep into the semiconductor heterostructure layer110may gradually decrease in the arrangement direction. In some preferred embodiments of the present disclosure, the widths of the conductive fingers631,632, and633gradually decrease along with the length decrease. For example, inFIG.6A, the lengths of the conductive fingers631,632, and633gradually decrease in the direction X, and the widths thereof also gradually decrease in the direction X. In some preferred embodiments, the lengths of the conductive fingers of the source structure are in a range of 1 nm to 1000 nm, and the widths are in a range of 5 nm to 800 nm. In some more preferred embodiments, the lengths of the conductive fingers of the source structure are in a range of 1 nm to 300 nm, and the widths are in a range of 5 nm to 200 nm. FIG.6Bis a schematic diagram of flow of electron holes in the semiconductor device600in a two-dimensional hole gas channel. As shown inFIG.6B, the 2DHGs can be generated between each semiconductor material layer111and its adjacent semiconductor material layer112. Therefore, a plurality of 2DHGs115,117, and119are generated at different depths (a direction Z as shown inFIG.6B) of the semiconductor heterostructure layer110. These 2DHGs115,117, and119extend along the interfaces of the semiconductor material layers111and the semiconductor material layers112. When the semiconductor device is conducted to a power supply, the electron holes can flow in the 2DHG to form hole flowing paths. According to the embodiment inFIG.6B, the electron holes in the 2DHGs115,117, and119all flow in the direction X. In a position approaching any one conductive finger, the electron holes will leave or enter the conductive finger through ohmic contact between the approached conductive finger and the semiconductor material layer112. For example, in the 2DHG115closest to the surface110a, the electron holes leave the source structure630through the ohmic contact between the conductive finger631and the semiconductor material layer112to enter the 2DHG115. When approaching the conductive finger621of the drain structure620, the electron holes mainly enter the drain structure620mainly through the ohmic contact between the conductive finger621and the semiconductor material layer112. In this case, a mainly hole flowing path is HP61as shown inFIG.6B. In the second-layer 2DHG117below the surface110a, the holes mainly leave the source structure630through the ohmic contact between the conductive finger632and the semiconductor material layer112to enter the 2DHG117. When approaching the conductive finger622of the drain structure620, the electron holes mainly enter the drain structure620through the ohmic contact between the conductive finger622and the semiconductor material layer112. The electron hole flowing path at that point is represented by HP62as shown inFIG.6B. Accordingly, in the 2DHG119farthest from the surface610a, the electron holes leave the source structure630from the ohmic contact between the conductive finger633and the semiconductor material layer112to enter the 2DHG119. When approaching the conductive finger623of the drain structure620, the electron holes mainly enter the drain structure620through the ohmic contact between the conductive finger623and the semiconductor material layer112. The electron hole flowing path at that point is represented by HP63as shown inFIG.6B. The electron holes flowing in the 2DHGs115,117, and119at different depths can leave the source structure630through the conductive fingers631,632, and633at different depths, and enter the drain structure620through the conductive fingers621,622, and623at different depths, so that distribution of electron holes can be achieved. However, the drain structure620and the source structure630of the present disclosure are not limited to the embodiment inFIG.6A. In some embodiments, the drain structure620and the source structure630respectively may include a nickel (Ni) layer in contact with the semiconductor heterostructure layer110. A single or multiple metal material layer may be further included on the nickel (Ni) layer in contact with the semiconductor heterostructure layer110. At least one of the following is included: titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), nickel (Ni), copper (Cu), titanium nitride (TiN), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof. In some embodiments, the conductive fingers of the drain structure620and the source structure630may also include a multilayer metal material layer as the conductive finger shown inFIG.2. In some embodiments, the conductive fingers621,622, and623of the drain structure620and the conductive fingers631,632, and633of the source structure630may be completely filled with conductive materials. In some embodiments, one or more of the conductive fingers621,622, and623of the drain structure620and/or the conductive fingers631,632, and633of the source structure630may include trenches. That is, the conductive fingers are not completely filled with the conductive materials. FIG.7is a cross-sectional view of a semiconductor device700according to some embodiments of the present disclosure. The semiconductor device700includes a semiconductor heterostructure layer110, a drain structure620, a source structure730, and a gate structure640. According to some embodiments of the present disclosure, the semiconductor device700further includes a buffer layer140and a carrier150. Some elements in the semiconductor device700are represented by the same numerals as those of the semiconductor device600inFIG.6A, and are made of similar materials, so detailed description thereof will not be repeated herein. The gate structure640is disposed between the drain structure620and the source structure730to control flow of electron holes between the drain structure620and the source structure730and further control on-off of the semiconductor device700. The source structure730includes a conductive finger731. The conductive finger731extends from a surface110aof the semiconductor heterostructure layer110to the semiconductor heterostructure layer110in a direction Z. When a conductive state is implemented between the drain structure620and the source structure730, electron holes will leave the source structure730to enter 2DHGs at each depth and then enter the drain structure620through the conductive fingers621,622, and623. According to some embodiments of the present disclosure, the reference numerals of the source structure and the drain structure can be exchanged with each other. That is, the source structure can be denoted by620and the drain structure denoted by730, in which case current direction will be opposite. That is, the electron holes will leave the source structure620through the conductive fingers621,622, and623to enter the 2DHGs at each depth and then enter the drain structure730. FIG.8is a cross-sectional view of a semiconductor device800according to some embodiments of the present disclosure. The semiconductor device800includes a semiconductor heterostructure layer110, a drain structure620, a source structure830and a gate structure640. According to some embodiments of the present disclosure, the semiconductor device800further includes a buffer layer140and a carrier150. Some elements in the semiconductor device800are represented by the same numerals as those of the semiconductor device600inFIG.6A, and are made of similar materials, so detailed description thereof will not be repeated herein. The source structure830is formed on a surface110aof the semiconductor heterostructure layer110, and is in direct contact with the semiconductor heterostructure layer110. The source structure830forms an ohmic contact surface with the surface110aof the semiconductor heterostructure layer110. When the semiconductor device800electrically connects to a power supply, and a conductive state is implemented between the drain structure620and the source structure830, electron holes will leave the source structure830to enter 2DHGs at each depth and then enter the drain structure620through the conductive fingers621,622, and623. According to some embodiments of the present disclosure, the reference numerals of the source structure and the drain structure can be exchanged with each other. That is, the source structure can be denoted by620, the drain structure denoted by830, in which case current direction will be opposite. That is, the electron holes will leave the source structure620through the conductive fingers621,622, and623to enter the 2DHGs at each depth and then enter the drain structure830. FIG.9is a cross-sectional view of a semiconductor device900according to some embodiments of the present disclosure. The semiconductor device900may be a diode, and include a semiconductor heterostructure layer110, a cathode structure920, and an anode structure940. According to some embodiments of the present disclosure, the semiconductor device900further includes a buffer layer140and a carrier150. Some elements in the semiconductor device900are represented by the same numerals as those of the semiconductor device600inFIG.6A, and are made of similar materials, so detailed description thereof will not be repeated herein. The cathode structure920includes conductive fingers921,922, and923. The conductive fingers921,922, and923are arranged substantially in a direction parallel to a surface110aof the semiconductor heterostructure layer110. End portions921E,922E, and923E of each conductive finger of the cathode structure920are positioned in the semiconductor material layers112at different depths, and are not in contact with 2DHGs. The anode structure940is formed on the surface110aof the semiconductor heterostructure layer110, and is in direct contact with the semiconductor heterostructure layer110. The anode structure940forms a Schottky contact surface with the surface110aof the semiconductor heterostructure layer110. When the semiconductor device900electrically connects to a power supply, electron holes will enter the 2DHGs at each depth through the anode structure940, and then enter the cathode structure920through the conductive fingers921,922, and923, so that dispersion of electron holes can occur at the cathode structure. FIG.10A,FIG.10B, andFIG.10Cshow steps of manufacturing the semiconductor device100. FIG.10Ashows a step of forming s stack of alternating semiconductor material layers111and semiconductor material layers112on a carrier150to form a semiconductor heterostructure layer110. The semiconductor material layers111and the semiconductor material layers112may be respectively formed by any one or more modes of epitaxial growth, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, before the semiconductor heterostructure layer110is formed, a buffer layer140can first be formed on the carrier150. The buffer layer140may be formed by any one or more modes of epitaxial growth, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like. FIG.10Bshows a step of forming a plurality of trenches131T,132T, and133T arranged substantially in a direction parallel to a surface110aof the semiconductor heterostructure layer110on the semiconductor heterostructure layer110. According to some embodiments of the present disclosure, the surface110aof the semiconductor heterostructure layer110is patterned (for example, in a lithography mode) to form a plurality of openings. Through the plurality of openings, the semiconductor heterostructure layer110is etched to form the plurality of trenches131T,132T, and133T. The plurality of trenches may be formed by one or more modes of chemical wet etching, dry etching, such as plasma etching and reactive ion etching (RIE), and the like. In an embodiment, the plurality of openings are designed as openings with different dimensions, so that the etching speeds of the semiconductor heterostructure layer110at each opening are different. For example, in wet and/or dry etching, the larger the opening dimension, the higher the etching speed of the semiconductor heterostructure layer110in a direction Z. In the present embodiment, the dimensions of the openings gradually increase on the surface110ain the direction X, and through an etching process, the depths of the plurality of trenches131T,132T, and133T in the direction X gradually increase. However, in other embodiments, the plurality of trenches131T,132T, and133T may be arranged in other directions substantially parallel to the surface110a. In that case, the lengths of the plurality of trenches131T,132T, and133T extending deep into the semiconductor heterostructure layer110may also gradually increase in the arrangement direction. By designing the openings with different dimensions, the etching speeds of the semiconductor heterostructure layer110in the direction Z are different. Etching of the trenches at different depths can be achieved in one step, while avoiding complicated etching procedures. According to some preferred embodiments of the present disclosure, the dimensions of the plurality of openings are designed so that the plurality of trenches131T,132T, and133T can be etched in one step. Additionally, end portions131TE,132TE, and133TE of each trench131T,132T, and133T are positioned in the semiconductor material layers112at different depths in the semiconductor heterostructure layer110, and are not in contact with 2DHGs. The dimension designs of the plurality of openings may be modified according to different materials of the semiconductor heterostructure layer110For example, the semiconductor heterostructure layers of structures such as AlGaN/GaN/AlGaN, InAlN/GaN/InAlN, AlN/GaN/AlN and InAlGaN/GaN/InAlGaN have respective opening dimension designs. In an embodiment, the semiconductor material layer111in the semiconductor heterostructure layer110is AlGaN. The thickness of each layer of the semiconductor material layer111is about 5 nm. The semiconductor material layer112is GaN. The thickness of each layer of the semiconductor material layer112is about 10 nm. An etching agent based on chlorine, for example, an etching agent including at least one of Cl2and BCl3, is used to perform dry etching. Table 1 exemplarily shows a plurality of trenches with different opening widths and trench depths etched in one step. TABLE 1TrenchOpening widthTrench depth131T5 to 100 nm1 to 10 nm132T100 to 200 nm15 to 25 nm133T200 to 800 nm30 to 40 nm FIG.10Cshows a step of depositing a conductive material in the plurality of trenches131T,132T, and133T so as to form a conductive structure130with conductive fingers131,132, and133. Additionally, annealing is further performed to form the semiconductor device100inFIG.1. The conductive structure130may form a single or multiple metal material layer through one or more deposition steps, for example, in one or more modes of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). In some embodiments, the step of forming the conductive structure130may include the following: first a titanium (Ti) layer or a titanium nitride (TiN) layer is formed on surfaces of the trenches131T,132T, and133T to be in contact with the semiconductor heterostructure layer110; the single or multiple metal material layer, such as one of the following: titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), nickel (Ni), copper (Cu), titanium nitride (TiN), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof is further formed; and the trenches131T,132T, and133T are completely filled to form conductive fingers131,132, and133. After the conductive structure130is formed, the semiconductor device100is annealed at 750° C. to 950° C. In some embodiments, the semiconductor device100may be annealed at 800° C. to 900° C. Ohmic contact surfaces are formed among the conductive fingers131,132, and133of the conductive structure130and the semiconductor heterostructure layer110. In some embodiments of the present disclosure, the step inFIG.10Cmay be replaced by that inFIG.10Dto form the semiconductor device300inFIG.3.FIG.10Dshows a step of depositing a conductive material in the plurality of trenches131T,132T and133T to form a conductive structure330with conductive fingers331,332, and333, and annealing is further performed. FIG.10Dis different fromFIG.10Cin that the conductive material covers bottom and side surfaces of the trenches131T,132T, and133T, so the trenches are still formed in the conductive fingers331,332, and333. The step of forming the conductive structure330may include: first, a titanium (Ti) layer or a titanium nitride (TiN) layer is formed on the surfaces of the trenches131T,132T, and133T to be in contact with the semiconductor heterostructure layer110; and then, a single or multiple metal material layer is further formed, such as at least one of the following: titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), aurum (Au), platinum (Pt), palladium (Pd), tungsten (W), and an alloy thereof. The conductive structure330may be formed in one or more modes of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, partial trenches remain in the conductive fingers331,332, and333. After the conductive structure330is formed, the semiconductor device100is annealed at 750° C. to 950° C. In some embodiments, the semiconductor device100may be annealed at 800° C. to 900° C. Ohmic contact surfaces are formed among the conductive fingers331,332, and333of the conductive structure330and the semiconductor heterostructure layer110. As used herein, the terms “approximately”, “basically”, “substantially”, and “about” are used to describe and explain small variations. When used in combination with an event or a situation, the terms may refer to an example in which an event or a situation occurs precisely and an example in which the event or situation occurs approximately. For example, when used in combination with a value, the term may refer to a variation range of less than or equal to ±10% of the value, for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a difference between two values is less than or equal to ±10% of an average value of the value (for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), it could be considered that the two values are “substantially” the same. For example, “substantially” parallel may refer to an angular variation range of less than or equal to ±10° with respect to 0°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular may refer to an angular variation range of less than or equal to ±10° with respect to 90°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. If a displacement between two surfaces is not more than 5 μm, not more than 2 μm, not more than 1 μm, or not more than 0.5 μm, the two surfaces may be considered to be coplanar or substantially coplanar. As used herein, the terms “conductive”, “electrically conductive”, and “electrical conductivity” refer to an ability to conduct an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature. As used herein, the singular terms “a”, “an”, and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, assemblies provided “on” or “above” another assembly may encompass a case in which a former assembly is directly on a latter assembly (for example, in physical contact with the latter assembly), and a case in which one or more intermediate assemblies are located between the former assembly and the latter assembly. Although the present application has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present application. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present application as defined by the appended claims. The drawings may not necessarily be drawn to scale. There may be variables between the artistic renditions in the present application and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present application which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present application. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to the specific operations that are performed in a specific order, it should be understood that these operations can be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present application. Therefore, unless otherwise specifically indicated herein, the order and grouping of operations shall not be construed as any limitation on the present application. | 43,246 |
11942526 | DETAILED DESCRIPTION Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element. In another example, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material having a doped portion that is adjacent to the metal. The metal may conductively couple the doped portion and the electrical element. The IC contact structures disclosed herein may be used advantageously in a number of different device settings. For example, some IC devices may include transistors located above the conventional device layer on the substrate; these transistors may be positioned in an additional device layer higher up in an interlayer dielectric stack, above transistors in the lowest device layer. Because these IC devices include transistors arrayed in the z-direction (as well as the x- and y-directions), these IC devices may be referred to as “three-dimensional” devices. It may be desirable to make connections from the source/drain (S/D) of these “upper” transistors in a monolithic device down to transistors or other electrical elements “lower” in the interlayer dielectric stack. Such connections may be made by routing a metal laterally out from the S/D of an upper transistor and then vertically downward, but this approach may consume valuable x-y area. The IC contact structures disclosed herein may be used in the three-dimensional device setting (as well as in other settings) to reduce the x-y footprint of connections between an upper transistor and a lower electrical element, thereby increasing transistor density and improving device performance. Some of the embodiments disclosed herein may include epitaxial growth of a semiconductor material for an S/D region (e.g., silicon or germanium) at least partially on a previously formed metal contact. Other embodiments disclosed herein may create S/D regions in a transistor by doping (e.g., ion implantation) rather than epitaxial growth, and a metal contact adjacent to the S/D regions may extend vertically down to an electrical element. A number of these, and other, embodiments are discussed in detail herein. In the following detailed description, reference is made to the accompanying drawings that form a part hereof, wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). For ease of discussion, the term “FIG.2” may be used to refer to the collection of drawings ofFIGS.2A-2C, the term “FIG.3” may be used to refer to the collection of drawings ofFIGS.3A-3C, etc. As used herein, the term “electrical element” may include elements that are semiconductive (e.g., doped or epitaxial regions of a transistor). As used herein, the term “between” when used to describe a range includes the ends of the range. The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Although various elements in the accompanying drawings are illustrated as being substantially rectangular or otherwise having flat faces, it will be understood that these elements, when manufactured in accordance with practical techniques, may be rounded or otherwise shaped differently from their representation of the accompanying drawings. For example, the semiconductor body102illustrated in a number of the drawings as a substantially rectangular “fin” may, in practice, be shaped as a rounded ridge. In another example, the interface between different materials may have significant roughness. FIG.1is a cross-sectional view of an IC contact structure100, in accordance with various embodiments. The IC contact structure100may include an electrical element106, a semiconductor material122, and a metal120that conductively couples the electrical element106and the semiconductor material122. Although the electrical element106, the metal120, and the semiconductor material122ofFIG.1are drawn as laterally coextensive, this is simply for ease of illustration, and the metal120may provide a conductive pathway between the electrical element106and the semiconductor material122using any particular geometry of the IC contact structure100. The interface between the metal120and the semiconductor material122may provide a Schottky junction. The electrical element106may include any suitable electrical element or portion of an electrical element. In some embodiments, the electrical element106may be a conductive line (e.g., in accordance with any of the embodiments of the trench structures2428adiscussed below with reference toFIG.40) or a conductive via (e.g., in accordance with any of the embodiments of the via structures2428bdiscussed below with reference toFIG.40). In some embodiments, the electrical element106may be a portion of an electrical device, such as a diode, varactor, capacitor, resistor (e.g., variable resistor), or a memory cell (e.g., a magnetic random-access memory (MRAM) cell). In some embodiments, the electrical element106may be a portion of a transistor, such as a gate or a source/drain (S/D) region. For example, the electrical element106may be a portion of a transistor2440in accordance with any of the embodiments discussed below with reference toFIG.40(e.g., the electrical element106may be a portion of a gate2422or an S/D region2420of a planar or non-planar transistor2440). In some particular embodiments, the electrical element106may be an “embedded epi” S/D region of a transistor or a doped S/D region of a transistor; various examples of S/D configurations are discussed in further detail below. In some embodiments, the electrical element106may be a front-end transistor (e.g., a transistor formed in a device layer on or closest to a substrate of the IC device, as discussed below with reference toFIG.40). In other embodiments, the electrical element106may be a non-front-end transistor (e.g., a transistor formed in an interconnect layer that is spaced apart from a device layer on or closest to a substrate of the IC device, as discussed below with reference toFIG.40). The metal120may include any suitable metal. In some embodiments, the metal120may include tungsten, titanium (e.g., titanium nitride), nickel, platinum, gold, tantalum, molybdenum, erbium, strontium, magnesium, scandium, niobium, vanadium, cesium, calcium, zinc, copper, cobalt, nickel zirconium, yttrium, sulfur, manganese, iron, indium, tin, antimony, bismuth, cadmium, silver, palladium, rhodium, ruthenium, rubidium, selenium, gallium, osmium, rhenium, hafnium, lanthanides, and/or any combination thereof. The material composition of the metal120may depend upon the setting of the IC contact structure100. For example, the material composition of the metal120may be selected to provide a low Schottky barrier height between the metal120and the semiconductor material122. The semiconductor material122may include any semiconductor, such as silicon or germanium. In some embodiments, the semiconductor material122may be grown on the metal120. For example, the semiconductor material122may be grown by epitaxial processes on the metal120. As discussed below, the semiconductor material122may be substantially homogeneous, or may not be substantially homogeneous. For example, in some embodiments in which the semiconductor material122includes portions grown on a metal120and portions grown on a crystalline material (e.g., such as the semiconductor body102, discussed below), the portions of the semiconductor material122grown on the metal120may be polycrystalline, while the portions grown on the crystalline material may be crystalline. In some embodiments, the semiconductor material122may include different portions associated with different deposition techniques. For example, the semiconductor material122may include a conformal layer of semiconductor material130and a semiconductor material fill portion134, as discussed below with reference toFIGS.13-20. The semiconductor material122may have an n-type conductivity or a p-type conductivity. In some embodiments, the semiconductor material122may have a doping concentration between 1×1018atoms/cm3to 1×1021atoms/cm3. The semiconductor material122may have a uniform doping concentration or may include sub-regions of different concentrations or dopant profiles. The semiconductor material122may include any suitable semiconductor material or combination of materials. For example, in some embodiments, the semiconductor material122may include an epitaxially grown single crystalline semiconductor such as, but not limited to, silicon, germanium, germanium tin, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenic antimonide, gallium nitride, gallium phosphide, and/or indium phosphide. In some embodiments, the semiconductor material122may include a III-V material. The IC contact structure100ofFIG.1may be implemented in any suitable manner, and a number of examples are discussed below with reference toFIGS.2-11,FIGS.12-14, andFIGS.15-20. For example,FIGS.2-11are cross-sectional views of various stages in the manufacture of an assembly including a transistor150having an IC contact structure100in accordance withFIG.1. In particular, the “A” sub-figures ofFIGS.2-11are cross-sectional views across a semiconductor body102(taken along the section C-C of the “B” and “C” sub-figures), the “B” sub-figures ofFIGS.2-11are cross-sectional views along the semiconductor body102(taken along the section A-A of the “A” sub-figures), and the “C” sub-figures ofFIGS.2-11are cross-sectional views offset from the semiconductor body102(taken along the section B-B of the “A” sub-figures). FIG.2depicts an assembly including an electrical element106and an insulating material104disposed thereon. The electrical element106may take the form of any of the embodiments disclosed herein. The insulating material104may include any suitable insulating material, such as an oxide or nitride. In some embodiments, the insulating material104may be an interlayer dielectric (ILD), such as undoped silicon oxide, doped silicon oxide (e.g., borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG)), silicon nitride, silicon oxynitride, or any combination. A semiconductor body102may be disposed on the insulating material104so that the insulating material104insulates the semiconductor body102from the electrical element106. InFIGS.2-11, the semiconductor body102is shaped as a fin, but this is simply for ease of illustration, and the semiconductor body102may take other forms. For example, in some embodiments, the semiconductor body102may include one or more nanowires (e.g., when the transistor150is an all-around gate transistor). Insulating material109may be located at either “end” of the semiconductor body102; the insulating material109may take the form of any of the embodiments of the insulating material104discussed herein. The semiconductor body102may include any suitable semiconductor material or combination of materials, such as silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium arsenic antimonide, and/or indium. In some particular embodiments, the semiconductor body102may include an undoped lattice-stressed single crystalline semiconductor material having a carrier mobility greater than single crystalline silicon. In some particular embodiments, the semiconductor body102may be a doped single crystalline semiconductor material (such as doped single crystalline silicon). Lattice stress in at least some of the semiconductor body102may enhance carrier mobility and improve device performance. In some embodiments, the semiconductor body102may be compressively stressed for enhanced hole mobility in p-type devices, and may be tensilely stressed for enhanced electron mobility in n-type devices. An insulating material110may be disposed on either face of the semiconductor body102. In some embodiments, the insulating material110may be a shallow trench isolation (STI) material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, yttrium oxide, scandium oxide, erbium oxide, lanthanum oxide, hafnium oxide, titanium oxide, indium gallium oxide, indium oxide, gallium oxide, tantalum oxide, germanium oxide, silicon germanium oxide, any combination thereof, and/or any appropriate dielectric material. As illustrated inFIG.2, the insulating material110may extend between the semiconductor body102and parallel isolation walls108(also referred to as “etch walls”). The isolation walls108may be formed of any suitable insulating material, such as any of the materials discussed above with reference to the insulating material110. In some embodiments, the isolation walls108may not be included in the assembly ofFIG.2. FIG.3illustrates an assembly subsequent to forming a sacrificial gate144on the semiconductor body102of the assembly ofFIG.2. The sacrificial gate144may include a sacrificial gate electrode112and a sacrificial gate dielectric114disposed between the sacrificial gate electrode112and the semiconductor body102. As illustrated inFIGS.3B and3C, when the semiconductor body102has a fin shape, the sacrificial gate144may extend over the top face of the semiconductor body102and at least partially down the side faces of the semiconductor body102. In some embodiments, a hardmask116may be disposed on the sacrificial gate electrode112. In some embodiments, the sacrificial gate dielectric114may be deposited to a thickness between 10 angstroms and 50 angstroms. The sacrificial gate dielectric114may serve as an etch stop layer during the patterning and formation of the sacrificial gate electrode112, thereby mitigating damage to the semiconductor body102. In some embodiments, the sacrificial gate dielectric114and the sacrificial gate electrode112may be formed from materials that have sufficiently different etch selectivity so that the sacrificial gate dielectric114may serve as an etch stop layer for etching the sacrificial gate electrode112to form the sacrificial gate144. In a particular embodiment, the sacrificial gate dielectric114may be a dielectric layer (e.g., silicon oxide, silicon nitride, and silicon oxynitride) and the sacrificial gate electrode112may be a semiconductor material (e.g., polycrystalline silicon). In some embodiments, the sacrificial gate144(and the final gate152, discussed below) may have a width163between 5 nanometers and 100 nanometers. FIG.4illustrates an assembly subsequent to providing spacers118on side (e.g., vertical) faces of the elements of the assembly ofFIG.3. In particular, the spacers118may be provided on the side faces of the sacrificial gate144and the side faces of the semiconductor body102. The spacers118may take the form of any of the sidewall spacers discussed below with reference toFIG.40. FIG.5illustrates an assembly subsequent to forming recesses115proximate to the longitudinal ends of the semiconductor body102of the assembly ofFIG.4. In particular, a pair of recesses115-1may be formed proximate to the side faces of the semiconductor body102at one longitudinal end of the semiconductor body102, and a pair of recesses115-2may be formed proximate to the side faces of the semiconductor body102at the opposite longitudinal end of the semiconductor body102. The recesses115may extend through the insulating material104to expose different portions of a top surface of the electrical element106. The recesses115may be formed using any conventional lithographic and etching techniques. Note that the electrical element106illustrated in various ones of the drawings herein may not be a uniform conductive material, and instead, may include different regions of conductivity and insulation as desired. Thus, for example, the different portions of the top surface of the electrical element106exposed by the recesses115may not necessarily be “shorted” together within the electrical element106, and may instead be associated with different conductive pathways within the electrical element106. The recesses115may be spaced apart from the semiconductor body102by portions of the insulating material110and spacers118. Similarly, the recesses115may be spaced apart from the isolation walls108and the insulating material109by portions of the insulating material110and spacers118, as shown. FIG.6illustrates an assembly subsequent to recessing portions of the semiconductor body102to form recesses119at the longitudinal ends of the semiconductor body102of the assembly ofFIG.5. Any suitable etching technique may be used to recess the semiconductor body102. FIG.7illustrates an assembly subsequent to providing metal120in the recesses115of the assembly ofFIG.6. The metal120may be disposed on the previously exposed portions of the top surface of the electrical element106. The metal120may take the form of any of the embodiments disclosed herein, and may be deposited using any suitable technique (e.g., blanket deposition, followed by chemical mechanical polishing (CMP) to planarized, followed by recessing). In some embodiments, the metal120may have a height123between 20 nanometers and 100 nanometers. FIG.8illustrates an assembly subsequent to growing a semiconductor material122on the exposed top surface of the semiconductor body102(including in the recesses119) and the exposed top surface of the metal120of the assembly ofFIG.7. The metal120may provide a conductive pathway between the semiconductor material122and the associated portions of the top surface of the electrical element106. The semiconductor material122, the metal120, and the electrical element106of the assembly ofFIG.8(andFIGS.9-11) may form IC contact structures100, as discussed above with reference toFIG.1. In some embodiments, the semiconductor material122may have a height121between 10 nanometers and 80 nanometers. The semiconductor material122may take the form of any of the embodiments disclosed herein. In some embodiments, the portions of the semiconductor material122grown on the metal120may be polycrystalline, while the portions grown on the semiconductor body102(which may have a substantially crystalline structure) may be crystalline. Thus, the semiconductor material122may not have a homogeneous structural composition. The semiconductor material122may provide the S/D regions of a transistor, as discussed below. In some embodiments, the semiconductor material122may be grown by epitaxy (e.g., using low-pressure chemical vapor deposition (CVD), vapor phase epitaxy, or molecular beam epitaxy). In some embodiments, the epitaxially deposited semiconductor material122may be doped in situ with dopants such as boron, arsenic, or phosphorous. For example, growth of the semiconductor material122may include deposition of the semiconductor material122(e.g., silicon germanium) in a hot wall reactor with the dopant (e.g., boron) present in a carrier gas. In some embodiments, the use of regions of epitaxial semiconductor material122may improve performance by providing anchors to the semiconductor body102that help maintain the uniaxial stress in the semiconductor body102already present from earlier fabrication processes, such as fin patterning. In some embodiments, the semiconductor material122may be stressed and, thus, may further stress the adjacent semiconductor body102. The stress in the semiconductor body102may be further enhanced by using a material for the semiconductor material122that has a different lattice constant than the material used to form the semiconductor body102(e.g., different semiconductor materials). FIG.9illustrates an assembly subsequent to providing additional spacers124on side (e.g., vertical) faces of the elements of the assembly ofFIG.8. The additional spacers124may be provided in accordance with any of the embodiments discussed above with reference to the spacers118ofFIG.5. In some embodiments, the additional spacers124may not be provided. FIG.10illustrates an assembly subsequent to removing the sacrificial gate144(and the hardmask116) from the assembly ofFIG.9and forming a gate152in its place. The gate152may include a gate dielectric140and a gate electrode142. The gate dielectric140may be disposed between the gate electrode142and the semiconductor body102. The gate dielectric140may take the form of any of the gate dielectric layers discussed below with reference to the gate2442of the transistor2440ofFIG.40, and the gate electrode142may take the form of any of the gate electrode layers discussed below with reference to the gate2442of the transistor2440ofFIG.40. In some embodiments, the deposition of the gate dielectric140may be conformal (e.g., via atomic layer deposition (ALD)), and thus the gate dielectric140may both be disposed on the semiconductor body102and on the sides of the spacers118, as shown inFIGS.10B and10C. In some embodiments, the gate dielectric140may have a thickness between 10 angstroms and 60 angstroms. In a specific embodiment, the gate dielectric140includes HfO2and has a thickness between 1 nanometer and 6 nanometers. The gate electrode142may be formed of any suitable gate electrode material. For example, in some embodiments, the gate electrode142may include a superconducting material. In some embodiments, the gate electrode142may include a metal such as, but not limited to, Ti, TiN, TaN, W, Ru, TiAl, or any combination thereof. In some embodiments, the gate electrode142may be formed from a material having a work function between 3.9 eV and 4.2 eV. In some embodiments, the gate electrode142may be formed from a material having a work function between 4.8 eV and 5.2 eV. In some embodiments in which the semiconductor body102is undoped or very lightly doped, the gate electrode142may be formed from a material having a mid-gap work function between 4.3 eV and 4.7 eV. The assembly ofFIG.10may thus include a transistor150having S/D regions provided by the semiconductor material122, a channel provided by the semiconductor body102between the portions of the semiconductor material122, and a gate provided by the gate152. The metal120may provide contacts from the S/D regions to the electrical element106below the transistor150(and as discussed above, may be part of an IC contact structure100). FIG.11illustrates an assembly subsequent to providing conductive material126on the semiconductor material122(between the additional spacers124) of the assembly ofFIG.10. The conductive material126may include any suitable conductive material, such as any of the embodiments of the metal120discussed herein. The conductive material126may provide a contact to the semiconductor material122(and thus to the S/D regions of the transistor150) from above the transistor150(in contrast to the IC contact structure100, which provides a contact to the electrical element106below the transistor150). In some embodiments, the conductive material126may not be present, and thus no conductive contact to the semiconductor material122above the transistor150may be made (instead, an insulating material may be provided). FIGS.12-14are cross-sectional views of various stages in the manufacture of an assembly including a transistor150and another IC contact structure100in accordance withFIG.1. The manufacturing operations illustrated inFIGS.12-14begin with the assembly ofFIG.7(discussed above). In particular, the “A” sub-figures ofFIGS.12-14are cross-sectional views across a semiconductor body102(taken along the section C-C of the “B” and “C” sub-figures), the “B” sub-figures ofFIGS.12-14are cross-sectional views along the semiconductor body102(taken along the section A-A of the “A” sub-figures), and the “C” sub-figures ofFIGS.12-14are cross-sectional views offset from the semiconductor body102(taken along the section B-B of the “A” sub-figures). FIG.12illustrates an assembly subsequent to growing a semiconductor material122on the exposed top surface of the semiconductor body102(including in the recesses119) and the exposed top surface of the metal120of the assembly ofFIG.7. In contrast to the assembly ofFIG.8, the semiconductor material122of the assembly ofFIG.12does not extend all the way out to the spacers118on the isolation walls108, but instead extends over the metal120while stopping short of reaching the spacers118on the isolation walls108. In the assembly ofFIG.12, the metal120may provide a conductive pathway between the semiconductor material122and the associated portions of the top surface of the electrical element106. The semiconductor material122, the metal120, and the electrical element106of the assembly ofFIG.12(andFIGS.13-14) may form IC contact structures100, as discussed above with reference toFIG.1. The semiconductor material122of FIG.12may take the form of any of the embodiments of the semiconductor material122discussed herein (e.g., as discussed above with reference toFIG.8). The assembly ofFIG.12may be formed by providing a sacrificial material (not shown) along the outer sidewall spacers118of the assembly ofFIG.7, grow the semiconductor material122, and then remove the sacrificial material, resulting in the assembly ofFIG.12. In some embodiments, the sacrificial material may be initially conformally deposited, then removed from everywhere but the outer sidewall spacers118(to expose the top surface of the semiconductor body102and the top surface of the metal120of the assembly ofFIG.7) with or without a patterning step. If the geometry of the assembly ofFIG.7is amenable to spacer-like self-aligned sidewall coverage, then no patterning of the sacrificial material may be needed. If the geometry of the central topography of the assembly ofFIG.7is too “tall” for a spacer-like process, then the “central” portion of the sacrificial material may be masked, patterned, and etched before growth of the semiconductor material122. FIG.13illustrates an assembly subsequent to providing additional spacers124on side (e.g., vertical) faces of the elements of the assembly ofFIG.12. The additional spacers124ofFIG.13may take the form of any of the embodiments of the additional spacers124ofFIG.9. In some embodiments, the additional spacers124may not be provided. FIG.14illustrates an assembly subsequent to removing the sacrificial gate144(and the hardmask116) from the assembly ofFIG.13, forming a gate152(including a gate dielectric140and a gate electrode142) in its place, and providing conductive material126on the semiconductor material122(between the additional spacers124). The gate dielectric140, the gate electrode142, and the conductive material126may take the form of any of the embodiments disclosed herein (e.g., discussed above with reference toFIGS.10and11). The assembly ofFIG.14may thus include a transistor150having S/D regions provided by the semiconductor material122, a channel provided by the semiconductor body102between the portions of the semiconductor material122, and a gate provided by the gate152. The metal120may provide contacts from the S/D regions to the electrical element106below the transistor150(and as discussed above, may be part of an IC contact structure100). The conductive material126may provide further conductive material between the semiconductor material122and the metal120. In some embodiments, the conductive material126may provide a conductive contact to the semiconductor material122above the transistor150. In other embodiments, when the conductive material126is not to provide an “above” contact to the transistor150, an insulating material (not shown) may be disposed on top of the conductive material126. FIGS.15-20are cross-sectional views of various stages in the manufacture of an assembly including a transistor150and another IC contact structure100in accordance withFIG.1. Like the manufacturing operations discussed above with reference toFIGS.12-14, the manufacturing operations illustrated inFIGS.15-20also begin with the assembly ofFIG.7(discussed above). The “A” sub-figures ofFIGS.15-20are cross-sectional views across a semiconductor body102(taken along the section C-C of the “B” and “C” sub-figures), the “B” sub-figures ofFIGS.15-20are cross-sectional views along the semiconductor body102(taken along the section A-A of the “A” sub-figures), and the “C” sub-figures ofFIGS.15-20are cross-sectional views offset from the semiconductor body102(taken along the section B-B of the “A” sub-figures). FIG.15illustrates an assembly subsequent to providing a conformal layer of semiconductor material130on the assembly ofFIG.7. The semiconductor material130may be disposed over the semiconductor body102(e.g., in the recesses119), and over the metal120, as shown. In some embodiments, the conformal layer of semiconductor material130may be grown using non-selective epitaxy, employing precursors with weaker bonds than used for selective growth. For example, in some embodiments, silicon, germanium, silicon-germanium alloys, and many III-V materials may be grown non-selectively with precursors that have a relatively higher proportion of weaker silicon-silicon bonds and a relatively lower proportion of stronger silicon-hydrogen bonds (e.g., disilane, trisilane and tetrasilane), as understood in the art. Across a number of semiconductor materials, increasing non-selectivity may be achieved by utilizing precursors with greater molecular weights. In some embodiments, the conformal layer of semiconductor material130may have a thickness between 1 and 50 nanometers (e.g., between 2 and 30 nanometers). FIG.16illustrates an assembly subsequent to providing a sacrificial material132on a portion of the semiconductor material130of the assembly ofFIG.15. In particular, the sacrificial material132may fill the recesses119in the semiconductor body102and may cover the portion of the semiconductor material130over the metal120, the semiconductor body102, and the intervening spacers118(as shown inFIG.16A). The sacrificial material132may include any suitable material, such as a polymer, oxide, or sacrificial metal. FIG.17illustrates an assembly subsequent to removing the semiconductor material130of the assembly ofFIG.16that is not protected by the sacrificial material132. In particular, the semiconductor material130on the sacrificial gate144, on the top surfaces of the isolation walls108, and on the top surfaces of the insulating material109, may be removed. The exposed semiconductor material130may be removed using any suitable selective etch technique. FIG.18illustrates an assembly subsequent to removing the sacrificial material132of the assembly ofFIG.17, using any suitable selective etch technique. The semiconductor material130may remain. FIG.19illustrates an assembly subsequent to growing a semiconductor material134on the semiconductor material130of the assembly ofFIG.18. The semiconductor material134may be grown using any suitable epitaxial method (e.g., any of the methods disclosed herein), with the semiconductor material130serving as a seed layer for the growth of the semiconductor material134. The semiconductor material134may at least partially fill the recesses119in the semiconductor body102, and may extend over the metal120and the intervening semiconductor body102(as shown inFIG.19). Together, the semiconductor material134and the semiconductor material130may provide the semiconductor material122. The semiconductor material122, the metal120, and the electrical element106of the assembly ofFIG.19(andFIG.20) may form IC contact structures100, as discussed above with reference toFIG.1. FIG.20illustrates an assembly subsequent to forming additional spacers124, removing the sacrificial gate144(and the hardmask116) from the assembly ofFIG.19, forming a gate152(including a gate dielectric140and a gate electrode142) in its place, and providing conductive material126on the semiconductor material122(between the additional spacers124). The additional spacers124, the gate dielectric140, the gate electrode142, and the conductive material126may take the form of any of the embodiments disclosed herein (e.g., discussed above with reference toFIGS.9-11). The assembly ofFIG.20may thus include a transistor150having S/D regions provided by the semiconductor material122, a channel provided by the semiconductor body102between the portions of the semiconductor material122, and a gate provided by the gate152. The metal120may provide contacts from the S/D regions to the electrical element106below the transistor150(and as discussed above, may be part of an IC contact structure100). In some embodiments, the conductive material126may provide a conductive contact to the semiconductor material122above the transistor150. In other embodiments, the conductive material126may be omitted. FIG.21is a cross-sectional view of an IC contact structure200, in accordance with various embodiments. The IC contact structure200may include an electrical element106, a semiconductor body102having a doped portion135, an insulating material104between the electrical element106and the semiconductor body102, and a metal120that conductively couples the electrical element106and the doped portion135. Although the electrical element106, the insulating material104, the semiconductor body102, and the metal120are shown in a particular geometric relationship inFIG.21, this is simply for ease of illustration, and the metal120may provide a conductive pathway between the doped portion135of the semiconductor body102and the electrical element106using any particular geometry of the IC contact structure200. The electrical element106, the insulating material104, and the semiconductor body102of the IC contact structure200may take the form of any of the embodiments disclosed herein (e.g., as discussed above with reference toFIG.1). The semiconductor body102may be, for example, a fin or one or more nanowires. The doped portion135may be formed by implanting dopants such as boron, aluminum, antimony, phosphorous, or arsenic into the semiconductor body102. An annealing process that activates the dopants and causes them to diffuse farther into the semiconductor body102may follow the implantation process. In some embodiments, the doped portion135and the remainder of the semiconductor body102may not be strained. In some such embodiments, the doped portion135may provide the S/D of an n-type metal oxide semiconductor (NMOS) transistor, while a portion of the semiconductor body102provides the channel of the NMOS transistor (e.g., as discussed below with reference toFIGS.22-24). In other embodiments, strain may be imparted to the semiconductor body102(to improve mobility as discussed above) using any suitable technique. The IC contact structure200ofFIG.21may be implemented in any suitable manner, and a number of examples are discussed below with reference toFIGS.22-24. In particular,FIGS.22-24are cross-sectional views of various stages in the manufacture of an assembly including a transistor150having an IC contact structure200in accordance withFIG.21. The manufacturing operations illustrated inFIGS.22-24begin with the assembly ofFIG.4(discussed above). The “A” sub-figures ofFIGS.22-24are cross-sectional views across a semiconductor body102(taken along the section C-C of the “B” and “C” sub-figures), the “B” sub-figures ofFIGS.22-24are cross-sectional views along the semiconductor body102(taken along the section A-A of the “A” sub-figures), and the “C” sub-figures ofFIGS.22-24are cross-sectional views offset from the semiconductor body102(taken along the section B-B of the “A” sub-figures). FIG.22illustrates an assembly subsequent to removing the spacers118on side faces of the semiconductor body102of the assembly ofFIG.4, and doping regions at the longitudinal ends of the semiconductor body102(e.g., using ion implantation) to form doped portions135. In some embodiments, the spacers118on side faces of the sacrificial gates144may act as doping barriers to constrain the doping to the portions of the semiconductor body102to the regions not under the sacrificial gates144or adjacent spacers118. FIG.23illustrates an assembly subsequent to forming recesses115in the assembly ofFIG.22. The recesses115may take the form of the recesses115discussed above with reference toFIG.5, and may expose portions of the top surface of the electrical element106. FIG.24illustrates an assembly subsequent to providing a metal120in the recesses115of the assembly ofFIG.23, removing the sacrificial gate144(and the hardmask116) from the assembly ofFIG.19, and forming a gate152(including a gate dielectric140and a gate electrode142) in its place. The gate dielectric140, the gate electrode142, and the metal120may take the form of any of the embodiments disclosed herein (e.g., discussed above with reference toFIGS.7and11). The metal120may extend over the doped portions135, and thus may provide a conductive pathway between the doped portions135and the portions of the top surface of the electrical element106in contact with the metal120. The electrical element106, the insulating material104, the doped portions135of the semiconductor body102, the semiconductor material122, and the metal120of the assembly ofFIG.24may form IC contact structures200, as discussed above with reference toFIG.21. The assembly ofFIG.24may thus include a transistor150having S/D regions provided by the doped portions135, a channel provided by the semiconductor body102between the doped portions135, and a gate provided by the gate152. The metal120may provide contacts from the S/D regions to the electrical element106below the transistor150(and as discussed above, may be part of an IC contact structure200). In some embodiments, the metal120may provide a conductive contact to the doped portions135above the transistor150. In other embodiments, when the metal120is not to provide an “above” contact to the transistor150, an insulating material (not shown) may be disposed on top of the metal120ofFIG.24. The IC contact structures100and200disclosed herein may be used in any suitable manner in an IC device. In particular, the IC contact structures100and200may be used to provide a “vertical” conductive contact within an IC device, reducing the footprint of the device relative to contact structures with a larger lateral footprint. For example,FIGS.25-36are cross-sectional views of various stages in the manufacture of an inverter circuit element including IC contact structures100in accordance withFIG.1. The technique illustrated with reference toFIGS.25-36may be applied to the manufacture of any circuit element (e.g., a pass gate, other logic element, or any other arrangement of transistors). The “A” sub-figures ofFIGS.25-36are cross-sectional views along a semiconductor body102(taken along the section B-B of the “B” and “C” sub-figures), the “B” sub-figures ofFIGS.25-36are cross-sectional views across the semiconductor body102(taken along the section A-A of the “A” sub-figures), and the “C” sub-figures ofFIGS.25-36are cross-sectional views across the semiconductor body102(taken along the section C-C of the “A” sub-figures). FIG.25illustrates an assembly including a semiconductor body102having a lower portion102A and an upper portion102B. The semiconductor body102may be shaped as a fin, as discussed above. The lower portion102A is separated from the upper portion102B by a layer105. The layer105may be a sacrificial epitaxial layer (e.g., silicon germanium with a high germanium content), a crystalline insulator (e.g., yttria-stabilized zirconia (YSZ)), or any other suitable material. Isolation walls108may segregate multiple semiconductor bodies102. A plurality of sacrificial gates144may be formed over the semiconductor body102, with source/drain locations between each of the plurality of sacrificial gates144, as discussed below. Each of the plurality of sacrificial gates144may include a sacrificial gate dielectric114and a sacrificial gate electrode112, as depicted inFIG.25. The formation of the semiconductor body102may begin with a starting structure of blanket layers that is then etched to provide a fin structure. A shallow trench isolation oxide may be formed adjacent to lower regions of the etched fin stack. The plurality of sacrificial gates144may form a grid pattern into and out of the page relative to the perspective ofFIG.25A, and the patterning may involve pitch halving or pitch quartering patterning. Additionally, it is to be appreciated that the plurality of sacrificial gates144extends from the top of the upper portion102B of the semiconductor body102(as shown) and further wraps the upper portion102B, the lower portion102A (e.g., as discussed above with reference toFIGS.2-20), and the layer105of the semiconductor body102at locations into and out of the page with respect to the perspective ofFIG.25A. FIG.26illustrates an assembly subsequent to removing portions of the layer105of the semiconductor body102of the assembly ofFIG.25. The removed regions are those laterally “between” the sacrificial gates144, and may correspond with source/drain locations, as discussed below. The regions of the layer105of the semiconductor body102may be removed using an etch process selective against etching of the material of the portions102A and102B of the semiconductor body102. For example, when the upper portion102B is formed of silicon germanium, the layer105may include silicon germanium having a higher germanium content than the silicon germanium of the upper portion102B. In embodiments in which the layer105includes a crystalline insulator, the crystalline insulator may only be included in a layer105in regions that are not the removed regions; in the removed regions, the layer105may include a sacrificial epitaxial layer (e.g., silicon germanium with a high germanium content). FIG.27illustrates an assembly subsequent to forming spacers118adjacent the sidewalls of each of the plurality of sacrificial gates144of the assembly ofFIG.26. As discussed above, the spacers118may be fabricated by first forming a conformal dielectric layer on the assembly ofFIG.26and then anisotropically etching the conformal dielectric layer. In some embodiments, as illustrated inFIG.27, the dielectric material of the spacers118may remain in the removed regions of the layer105to form dielectric regions162. FIG.28illustrates an assembly subsequent to performing a vertical undercut etch on the assembly ofFIG.27to remove portions of the semiconductor body102from the source/drain locations to form recesses138. Two recesses,138-1and138-2, are shown inFIG.28. The width of the undercut feature may depend on whether n-type or p-type semiconductor regions will ultimately be formed in the recesses138. FIG.29illustrates an assembly subsequent to providing epitaxial semiconductor material164in the recesses138of the assembly ofFIG.28. Two regions of epitaxial semiconductor material,164-1and164-2, are shown inFIG.28in the recesses138-1and138-2, respectively. The regions of epitaxial semiconductor material164may provide electrical elements106in IC contact structures100, as discussed below. The epitaxial semiconductor material164may be n-type (such as n-type silicon) or p-type (such as p-type silicon germanium) regions, depending on the structural arrangement required. Epitaxial growth from semiconductor body102to semiconductor body102(e.g., fin to fin) may be restricted by the isolation walls108, in some embodiments. FIG.30illustrates an assembly subsequent to etching back the epitaxial semiconductor material164of the assembly ofFIG.29. The etched back epitaxial semiconductor material164(referred to subsequently as the “semiconductor material164”) may provide S/D regions for a lower transistor150-1that may act as the electrical element106, as discussed below. In some embodiments, the semiconductor material164is formed to a height at or below the height of the lower portion102A of the semiconductor body102. In particular, the layer105may serve as a marker layer. FIG.31illustrates an assembly subsequent to providing an insulating material104on the semiconductor material164of the assembly ofFIG.30. In some embodiments, the insulating material104may be an isolation oxide, and may be formed using an oxide fill, recess, and wet clean processing scheme. In some embodiments, the top of the insulating material104is approximately at the same level as the top of the layer105of the semiconductor body102. The insulating material104may be ultimately used to isolate corresponding bottom and top transistors, as discussed below. FIG.32illustrates an assembly subsequent to patterning the insulating material104of the assembly ofFIG.31to remove portions of the insulating material104in the recess138-1. In particular, portions of the insulating material104in the recess138-1near the isolation walls108may be removed to expose portions of a top surface of the semiconductor material164-1. The portions of the insulating material104may be removed using any suitable etch technique. Note that the insulating material104in the recess138-2may not be removed in the illustrated embodiment. FIG.33illustrates an assembly subsequent to providing a metal120around the insulating material104in the recess138-1of the assembly ofFIG.32. The metal120may take the form of any of the embodiments disclosed herein. In some embodiments, the metal120may be restricted to the sides of the insulating material104in the recess138-1, while in other embodiments, the metal120may extend over the insulating material104(not shown). In some embodiments, metal120may also be provided on the insulating material104in the recess138-2(not shown). FIG.34illustrates an assembly subsequent to providing semiconductor material122in the recesses138of the assembly ofFIG.33. In some embodiments, the semiconductor material122may be epitaxially grown on the metal120/insulating material104in the recess138-1, and on the insulating material104in the recess138-2. The semiconductor material122of the assembly ofFIG.34may take the form of any of the embodiments disclosed herein. The semiconductor material122may serve as S/D regions for an upper transistor, discussed further below. The semiconductor material122, the metal120, and the electrical elements106may provide IC contact structures100. FIG.35illustrates an assembly subsequent to performing a replacement gate process to remove the sacrificial gates144and replace them with upper gates152including a gate electrode142and a gate dielectric140. This replacement gate process may take the form of any of the embodiments disclosed herein. A set of lower gates (not shown) may also be formed within the trench formed upon removal of the sacrificial gate144, which may involve deposition and recessing of gate materials to a level approximately at the level of the lower portion102A, on either side of the semiconductor body102(i.e., into and out of the page of the perspective shown inFIG.35). The upper gates152may then be formed above the lower gates. In the case of the inverter structure ofFIGS.25-36, the upper gates152may be of an opposite conductivity type than that of the lower gates. When the operations discussed with reference toFIGS.25-36are modified to form a pass gate structure, for example, the upper gates152may be of a same conductivity type as that of the lower gates. In either case, within a same gate trench, an isolation layer (not shown) may be formed between the lower gate and the upper gates152. FIG.36illustrates an assembly subsequent to providing a conductive material126above the semiconductor material122of the assembly ofFIG.35. The conductive material126may act as a “top” contact to the S/D regions provided by the semiconductor material122, and may take the form of any of the embodiments disclosed herein. The assembly ofFIG.36may include a lower transistor150-1, and an upper transistor150-2. In the assembly ofFIG.36, the lower transistor150-1may be an NMOS device and the semiconductor material164is an n-type material, such as n-type silicon regions. The upper transistor150-2of the inverter structure ofFIG.36may be a PMOS device and the semiconductor material122is a p-type material, such as p-type silicon germanium regions. In other embodiments, the upper portion102B may not be undercut with recesses138prior to provision of the semiconductor material122, as was discussed above with reference toFIGS.28and34. Instead, the portion of the semiconductor body102between the spacers118may be narrowed and implanted or in-diffused with a dopant. Subsequently, a metal120may be provided along side faces of the narrowed semiconductor body, forming IC contact structures200with the electrical elements106(instead of IC contact structures100). Any suitable techniques may be used to manufacture any of the assemblies (e.g., any of the IC contact structures) disclosed herein.FIGS.37and38are flow diagrams of methods1000and1100, respectively, of manufacturing an IC contact structure, in accordance with various embodiments. Although various operations are arranged in particular order and illustrated once each inFIGS.37and38, various ones of the operations may be repeated or performed in any suitable order. Additionally, although various operations of the methods ofFIGS.37and38are illustrated with reference to particular ones of the embodiments disclosed herein, the methods ofFIGS.37and38may be used to form any suitable IC contact structures. Turning to the method1000ofFIG.37, at1002, a metal may be provided on an electrical element in an IC device. For example, a metal120may be provided on an electrical element106, in accordance with a number of the embodiments disclosed herein. At1004, a semiconductor material may be grown at least partially on the metal. For example, a semiconductor material122may be grown (e.g., by epitaxy) at least partially on the metal120, in accordance with a number of the embodiments disclosed herein. Turning to the method1100ofFIG.38, at1102, a semiconductor body may be formed above an electrical element in an IC device. For example, a semiconductor body102may be formed above an electrical element106, in accordance with a number of the embodiments disclosed herein. At1104, a portion of the semiconductor body may be doped to form a doped region. For example, a semiconductor body102may be doped to form doped portions135in the semiconductor body102, in accordance with a number of the embodiments disclosed herein. At1106, a metal may be provided adjacent to the doped region and extending down to the electrical element. The metal may conductively couple the doped region and the electrical element. For example, a metal120may be provided adjacent to a doped portion135such that the metal120extends down to the electrical element106to conductively couple the doped portion135and the electrical element106. The IC contact structures disclosed herein may be included in any suitable IC device, which may in turn be included in any suitable computing device.FIGS.39-42illustrate various examples of apparatuses that may include any of the IC contact structures disclosed herein. Similarly, the methods disclosed herein may be used in any suitable stage in the manufacture of an apparatus, including any of the apparatuses discussed below with reference toFIGS.39-42. FIGS.39A-Bare top views of a wafer2300and dies2302that may include one or more IC contact structures in accordance with any of the embodiments disclosed herein (e.g., the IC contact structures100or200). An IC contact structure may be one of multiple IC structures formed on the wafer2300. The wafer2300may be composed of semiconductor material and may include one or more dies2302having IC structures formed on a surface of the wafer2300. Each of the dies2302may be a repeating unit of a semiconductor product that includes one or more of the IC contact structures. After the fabrication of the semiconductor product is complete, the wafer2300may undergo a singulation process in which each of the dies2302is separated from one another to provide discrete “chips” of the semiconductor product. Thus, the IC contact structures may be present in the wafer2300due to its presence in the dies2302. In particular, the IC contact structures may be included in an apparatus that takes the form of the wafer2300(e.g., not singulated) or the form of the die2302(e.g., singulated). As discussed above, the IC contact structures may be part of a multi-transistor structure included in the die2302. In addition to the IC contact structures, and any associated transistors150, the die2302may include one or more other transistors (e.g., some of the transistor(s)2440ofFIG.40, discussed below) and/or supporting circuitry to route electrical signals to the one or more multi-transistor structure, as well as any other IC components. In some embodiments, an IC contact structure may be included in a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die2302. For example, a memory array formed by multiple memory devices may be formed on a same die2302as a processing device (e.g., the processing device2602ofFIG.42) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array; any one or more of these devices may include one or more IC contact structures. FIG.40is a cross-sectional side view of an IC device2400that may include one or more IC contact structures in accordance with any of the embodiments disclosed herein (e.g., any of the IC contact structures100or200). The IC device2400may be formed on a substrate2402(e.g., the wafer2300ofFIG.39A) and may be included in a die (e.g., the die2302ofFIG.39B). The substrate2402may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems. The substrate2402may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In some embodiments, the semiconductor substrate2402may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate2402. Although a few examples of materials from which the substrate2402may be formed are described here, any material that may serve as a foundation for an IC device2400may be used. The substrate2402may be part of a singulated die (e.g., the dies2302ofFIG.39B) or a wafer (e.g., the wafer2300ofFIG.39A). The IC device2400may include one or more device layers2404disposed on the substrate2402. The device layer2404may include features of one or more transistors2440(e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the substrate2402. The device layer2404may include, for example, one or more source and/or drain (S/D) regions2420, a gate2422to control current flow in transistors2440between the S/D regions2420, and one or more S/D contacts2424to route electrical signals to/from the S/D regions2420. The transistors2440may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors2440are not limited to the type and configuration depicted inFIG.40and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. The transistors150discussed above may take the form of any of the transistors2440discussed herein. AlthoughFIG.40illustrates a single “front-end” device layer2404(i.e., a device layer located on or closest to the substrate2402), the IC device2400may include multiple device layers2404located “higher up” in the stack of the IC device2400. In particular, the IC device2400may include one or more additional, non-front-end (“back-end”) device layers2404, some of which may be separated from the front-end device layer2404by one or more intervening interconnect layers. Any of the IC contact structures disclosed herein may include an electrical element106in the back-end of an IC device2400, or an electrical element106in another layer of the IC device2400. Although the transistors2440illustrated inFIG.40are planar transistors, the IC device2400may include non-planar transistors and/or multi-transistor structures arranged vertically on a fin, as illustrated inFIGS.25-36, in addition to or instead of planar transistors. Additionally, a computing device (e.g., the computing device2600ofFIG.42) may include planar transistors, non-planar transistors, devices with multiple transistors arranged vertically on a fin, etc. Any suitable ones of the materials used in the transistors2440, or processes used to form the transistors2440, may be used to form the transistors150(and the IC contact structures) disclosed herein. Each transistor2440may include a gate2422formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used. The gate electrode layer may be formed on the gate dielectric layer and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor2440is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. In some embodiments, when viewed as a cross-section of the transistor2440along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, a pair of sidewall spacers (e.g., the sidewall spacers118) may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. The sidewall spacers may be formed using conventional methods of forming selective spacers, as known in the art. In some embodiments, a conformal dielectric spacer layer, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, is first blanket-deposited on all structures. The dielectric spacer layer may be deposited in a conformal manner so that it has substantially equal thicknesses on both vertical surfaces and horizontal surfaces. The dielectric spacer layer may be deposited using conventional CVD methods such as low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), for example. In some embodiments, the dielectric spacer layer may be deposited to a thickness between 2 nanometers and 10 nanometers. Next, an unpatterned anisotropic etch may be performed on the dielectric spacer layer using conventional anisotropic etch methods, such as reactive ion etching (RIE). During the anisotropic etching process, most of the dielectric spacer layer may be removed from horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces, as shown. Next, an unpatterned isotropic etch may be performed to remove the remaining dielectric spacer layer from any horizontal surfaces, leaving the sidewall spacers. In some embodiments, the isotropic etch is a wet etch process. In a specific embodiment, where the dielectric spacer layer is silicon nitride or silicon oxide, the isotropic etch may employ a wet etchant solution comprising phosphoric acid (H3PO4) or a buffered oxide etch (BOE), respectively. In an alternate embodiment, the isotropic etch may be a dry etch process. In one such embodiment, nitrogen trifluoride (NF3) gas may be employed in a downstream plasma reactor to isotropically etch the dielectric spacer layers. The S/D regions2420may be formed within the substrate2402adjacent to the gate2422of each transistor2440. The S/D regions2420may be formed using either an implantation/diffusion process or an etching/growth process, as discussed above with reference to the doped portions135and the semiconductor material122, respectively. In some embodiments, one or more layers of metal and/or metal alloys may be included in the S/D regions2420. Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors2440of the device layer2404through one or more interconnect layers disposed on the device layer2404(illustrated inFIG.40as interconnect layers2406-2410). For example, electrically conductive features of the device layer2404(e.g., the gate2422and the S/D contacts2424) may be electrically coupled with interconnect structures2428of the interconnect layers2406-2410. The one or more interconnect layers2406-2410may form an interlayer dielectric (ILD) stack2419of the IC device2400. The interconnect structures2428may be arranged within the interconnect layers2406-2410to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures2428depicted inFIG.40). Although a particular number of interconnect layers2406-2410is depicted inFIG.40, embodiments of the present disclosure include IC devices having more or fewer interconnect layers2406-2410than depicted. In some embodiments, the interconnect structures2428may include trench structures2428a(sometimes referred to as “lines”) and/or via structures2428b(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench structures2428amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate2402upon which the device layer2404is formed. For example, the trench structures2428amay route electrical signals in a direction in and out of the page from the perspective ofFIG.40. The via structures2428bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate2402upon which the device layer2404is formed. In some embodiments, the via structures2428bmay electrically couple trench structures2428aof different interconnect layers2406-2410together. The interconnect layers2406-2410may include a dielectric material2426disposed between the interconnect structures2428, as shown inFIG.40. In some embodiments, the dielectric material2426disposed between the interconnect structures2428in different ones of the interconnect layers2406-2410may have different compositions; in other embodiments, the composition of the dielectric material2426between different interconnect layers2406-2410may be the same. A first interconnect layer2406(referred to as Metal 1 or “M1”) may be formed directly on the device layer2404. In some embodiments, the first interconnect layer2406may include trench structures2428aand/or via structures2428b, as shown. Trench structures2428aof the first interconnect layer2406may be coupled with contacts (e.g., S/D contacts2424) of the device layer2404. A second interconnect layer2408(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer2406. In some embodiments, the second interconnect layer2408may include via structures2428bto couple the trench structures2428aof the second interconnect layer2408with the trench structures2428aof the first interconnect layer2406. Although the trench structures2428aand the via structures2428bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer2408) for the sake of clarity, the trench structures2428aand the via structures2428bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments. A third interconnect layer2410(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer2408according to similar techniques and configurations described in connection with the second interconnect layer2408on the first interconnect layer2406. The IC device2400may include a solder resist material2434(e.g., polyimide or similar material) and one or more bond pads2436formed on the interconnect layers2406-2410. The bond pads2436may be electrically coupled with the interconnect structures2428and configured to route the electrical signals of transistor(s)2440to other external devices. For example, solder bonds may be formed on the one or more bond pads2436to mechanically and/or electrically couple a chip including the IC device2400with another component (e.g., a circuit board). The IC device2400may have other alternative configurations to route the electrical signals from the interconnect layers2406-2410than depicted in other embodiments. For example, the bond pads2436may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components. FIG.41is a cross-sectional side view of an IC device assembly2500that may include one or more IC contact structures, in accordance with any of the embodiments disclosed herein (e.g., the IC contact structures100or200). The IC device assembly2500includes a number of components disposed on a circuit board2502(which may be, for example, a motherboard). The IC device assembly2500includes components disposed on a first face2540of the circuit board2502and an opposing second face2542of the circuit board2502; generally, components may be disposed on one or both faces2540and2542. In some embodiments, the circuit board2502may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board2502. In other embodiments, the circuit board2502may be a non-PCB substrate. The IC device assembly2500illustrated inFIG.41includes a package-on-interposer structure2536coupled to the first face2540of the circuit board2502by coupling components2516. The coupling components2516may electrically and mechanically couple the package-on-interposer structure2536to the circuit board2502, and may include solder balls (as shown inFIG.41), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. The package-on-interposer structure2536may include an IC package2520coupled to an interposer2504by coupling components2518. The coupling components2518may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2516. Although a single IC package2520is shown inFIG.41, multiple IC packages may be coupled to the interposer2504; indeed, additional interposers may be coupled to the interposer2504. The interposer2504may provide an intervening substrate used to bridge the circuit board2502and the IC package2520. The IC package2520may be or include, for example, a die (the die2302ofFIG.39B), an IC device (e.g., the IC device2400ofFIG.40, or any of the assemblies disclosed herein), or any other suitable component. Generally, the interposer2504may spread a connection to a wider pitch or to reroute a connection to a different connection. For example, the interposer2504may couple the IC package2520(e.g., a die) to a ball grid array (BGA) of the coupling components2516for coupling to the circuit board2502. In the embodiment illustrated inFIG.41, the IC package2520and the circuit board2502are attached to opposing sides of the interposer2504; in other embodiments, the IC package2520and the circuit board2502may be attached to a same side of the interposer2504. In some embodiments, three or more components may be interconnected by way of the interposer2504. The interposer2504may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer2504may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer2504may include metal interconnects2508and vias2510, including but not limited to through-silicon vias (TSVs)2506. The interposer2504may further include embedded devices2514, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer2504. The package-on-interposer structure2536may take the form of any of the package-on-interposer structures known in the art. The IC device assembly2500may include an IC package2524coupled to the first face2540of the circuit board2502by coupling components2522. The coupling components2522may take the form of any of the embodiments discussed above with reference to the coupling components2516, and the IC package2524may take the form of any of the embodiments discussed above with reference to the IC package2520. The IC device assembly2500illustrated inFIG.41includes a package-on-package structure2534coupled to the second face2542of the circuit board2502by coupling components2528. The package-on-package structure2534may include an IC package2526and an IC package2532coupled together by coupling components2530such that the IC package2526is disposed between the circuit board2502and the IC package2532. The coupling components2528and2530may take the form of any of the embodiments of the coupling components2516discussed above, and the IC packages2526and2532may take the form of any of the embodiments of the IC package2520discussed above. The package-on-package structure2534may be configured in accordance with any of the package-on-package structures known in the art. FIG.42is a block diagram of an example computing device2600that may include one or more IC contact structures in accordance with the teachings of the present disclosure (e.g., any of the IC contact structures100or200). A number of components are illustrated inFIG.42as included in the computing device2600, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device2600may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the computing device2600may not include one or more of the components illustrated inFIG.42, but the computing device2600may include interface circuitry for coupling to the one or more components. For example, the computing device2600may not include a display device2606, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2606may be coupled. In another set of examples, the computing device2600may not include an audio input device2624or an audio output device2608, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2624or audio output device2608may be coupled. Any one or more of the components of the computing device2600may be included in one or more IC devices that may include an embodiment of the IC contact structures disclosed herein. The computing device2600may include a processing device2602(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device2602may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device2600may include a memory2604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory2604may include memory that shares a die with the processing device2602. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque MRAM (STT-MRAM). The processing device2602and/or the memory2604may include one or more of the IC contact structures disclosed herein. In some embodiments, the computing device2600may include a communication chip2612(e.g., one or more communication chips). For example, the communication chip2612may be configured for managing wireless communications for the transfer of data to and from the computing device2600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip2612may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip2612may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip2612may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip2612may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip2612may operate in accordance with other wireless protocols in other embodiments. The computing device2600may include an antenna2622to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). In some embodiments, the communication chip2612may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip2612may include multiple communication chips. For instance, a first communication chip2612may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip2612may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip2612may be dedicated to wireless communications, and a second communication chip2612may be dedicated to wired communications. The communication chip2612may include one or more of the IC contact structures disclosed herein. The computing device2600may include battery/power circuitry2614. The battery/power circuitry2614may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device2600to an energy source separate from the computing device2600(e.g., AC line power). The computing device2600may include a display device2606(or corresponding interface circuitry, as discussed above). The display device2606may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example. The computing device2600may include an audio output device2608(or corresponding interface circuitry, as discussed above). The audio output device2608may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example. The computing device2600may include an audio input device2624(or corresponding interface circuitry, as discussed above). The audio input device2624may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The computing device2600may include a global positioning system (GPS) device2618(or corresponding interface circuitry, as discussed above). The GPS device2618may be in communication with a satellite-based system and may receive a location of the computing device2600, as known in the art. The computing device2600may include an other output device2610(or corresponding interface circuitry, as discussed above). Examples of the other output device2610may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. The computing device2600may include an other input device2620(or corresponding interface circuitry, as discussed above). Examples of the other input device2620may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. The computing device2600may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device2600may be any other electronic device that processes data. The following paragraphs provide various examples of the embodiments disclosed herein. Example 1 is an integrated circuit (IC) contact structure, including: an electrical element; a metal on the electrical element; and a semiconductor material on the metal, wherein the metal conductively couples the semiconductor material and the electrical element. Example 2 may include the subject matter of Example 1, and may further specify that the electrical element includes a conductive line. Example 3 may include the subject matter of any of Examples 1-2, and may further specify that the electrical element includes an epitaxial semiconductor material portion of a transistor. Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the electrical element includes a source/drain of a transistor. Example 5 may include the subject matter of Example 4, and may further specify that the transistor is a back-end transistor. Example 6 may include the subject matter of Example 4, and may further specify that the transistor is not a back-end transistor. Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the metal includes tungsten, titanium, nickel, platinum, gold, tantalum, molybdenum, erbium, strontium, magnesium, scandium, niobium, vanadium, cesium, calcium, zinc, copper, cobalt, nickel zirconium, yttrium, sulfur, manganese, iron, indium, tin, antimony, bismuth, cadmium, silver, palladium, rhodium, ruthenium, rubidium, selenium, gallium, osmium, rhenium, hafnium, or a lanthanide. Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the semiconductor material is an epitaxial semiconductor material. Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the semiconductor material is part of a source/drain of a transistor. Example 10 may include the subject matter of Example 9, and may further specify that the transistor is a non-planar transistor. Example 11 may include the subject matter of Example 10, and may further specify that the transistor is a trigate transistor. Example 12 may include the subject matter of any of Examples 9-11, and may further specify that the semiconductor material has a height between 10 nanometers and 80 nanometers. Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the metal extends around an end of a semiconductor fin. Example 14 may include the subject matter of any of Examples 1-13, and may further include a semiconductor fin between the electrical element and the semiconductor material. Example 15 may include the subject matter of Example 14, and may further specify that the semiconductor material is also on the semiconductor fin. Example 16 may include the subject matter of Example 15, and may further specify that the semiconductor material is crystalline above the semiconductor fin, and polycrystalline above the metal. Example 17 may include the subject matter of any of Examples 14-16, and may further specify that the semiconductor fin is adjacent to the metal. Example 18 may include the subject matter of any of Examples 14-17, and may further include an insulating material between the semiconductor fin and the electrical element. Example 19 may include the subject matter of any of Examples 1-18, and may further specify that the metal is a first metal, and the IC contact structure further includes a second metal on the semiconductor material and on the first metal. Example 20 may include the subject matter of any of Examples 1-19, and may further specify that the IC contact structure is between two isolation walls. Example 21 is a method of forming an integrated circuit (IC) contact structure, including: providing a metal on an electrical element in an IC device; and growing a semiconductor material at least partially on the metal. Example 22 may include the subject matter of Example 21, and may further include providing additional metal on the semiconductor material. Example 23 may include the subject matter of Example 22, and may further specify that the additional metal is provided above and on side faces of the semiconductor material. Example 24 may include the subject matter of any of Examples 21-23, and may further include, before providing the metal on the electrical element, forming a semiconductor body above the electrical element, wherein an insulating material is disposed between the semiconductor body and the electrical element; wherein the semiconductor material extends over the semiconductor body. Example 25 may include the subject matter of Example 24, and may further specify that the semiconductor body includes a fin or a nanowire. Example 26 may include the subject matter of any of Examples 21-25, and may further specify that growing the semiconductor material on the metal includes: providing a conformal layer of epitaxial material on the metal; and growing additional epitaxial material on the conformal layer. Example 27 may include the subject matter of Example 26, and may further include: after providing the conformal layer of epitaxial material, depositing a sacrificial material; recessing the sacrificial material; removing portions of the conformal layer of epitaxial material that are not covered by the sacrificial material; and removing the sacrificial material. Example 28 may include the subject matter of any of Examples 21-27, and may further include stopping growth of the semiconductor material after it contacts adjacent isolation walls. Example 29 may include the subject matter of any of Examples 21-27, and may further include stopping growth of the semiconductor material before it contacts adjacent isolation walls. Example 30 is a computing device, including: a processing device including an electrical element, a metal on the electrical element, and an epitaxial material on the metal, wherein the metal conductively couples the epitaxial material and the electrical element; and a memory device in electrical communication with the processing device. Example 31 may include the subject matter of Example 30, and may further specify that the epitaxial material is a part of a transistor. Example 32 may include the subject matter of any of Examples 30-31, and may further specify that the electrical element is part of a diode, a varactor, a capacitor, a variable resistor, a transistor, or a memory cell. Example 33 may include the subject matter of any of Examples 30-32, and may further include a communication chip. Example 34 is an integrated circuit (IC) contact structure, including: an electrical element; a metal on the electrical element; and a semiconductor material having a doped region that is adjacent to the metal, wherein the metal conductively couples the doped region and the electrical element. Example 35 may include the subject matter of Example 34, and may further specify that the electrical element includes a conductive line. Example 36 may include the subject matter of any of Examples 34-35, and may further specify that the electrical element includes an epitaxial semiconductor material portion of a transistor. Example 37 may include the subject matter of any of Examples 34-36, and may further specify that the electrical element includes a source/drain of a transistor. Example 38 may include the subject matter of Example 37, and may further specify that the transistor is a back-end transistor. Example 39 may include the subject matter of Example 37, and may further specify that the transistor is not a back-end transistor. Example 40 may include the subject matter of any of Examples 34-39, and may further specify that the metal includes tungsten, titanium, nickel, platinum, gold, tantalum, molybdenum, erbium, strontium, magnesium, scandium, niobium, vanadium, cesium, calcium, zinc, copper, cobalt, nickel zirconium, yttrium, sulfur, manganese, iron, indium, tin, antimony, bismuth, cadmium, silver, palladium, rhodium, ruthenium, rubidium, selenium, gallium, osmium, rhenium, hafnium, or a lanthanide. Example 41 may include the subject matter of any of Examples 34-40, and may further specify that the metal is adjacent to at least one lateral face of the doped region, and extends above the doped region. Example 42 may include the subject matter of any of Examples 34-41, and may further specify that the doped region is a source/drain of a transistor. Example 43 may include the subject matter of Example 42, and may further specify that the transistor is a non-planar transistor. Example 44 may include the subject matter of Example 43, and may further specify that the transistor is a trigate transistor. Example 45 may include the subject matter of any of Examples 34-44, and may further specify that the metal extends laterally around the doped region. Example 46 may include the subject matter of any of Examples 34-45, and may further include an insulating material between the semiconductor material and the electrical element. Example 47 may include the subject matter of any of Examples 34-46, and may further specify that the IC contact structure is between two isolation walls. Example 48 is a method of forming an integrated circuit (IC) contact structure, including: forming a semiconductor body above an electrical element in an IC device; doping a portion of the semiconductor body to form a doped region; and providing a metal adjacent to the doped region and extending down to the electrical element to conductively couple the doped region and the electrical element. Example 49 may include the subject matter of Example 48, and may further specify that the electrical element includes a source/drain of a transistor. Example 50 may include the subject matter of Example 49, and may further specify that the electrical element includes an epitaxial semiconductor material. Example 51 may include the subject matter of any of Examples 48-50, and may further specify that the metal is laterally adjacent to the doped region, and extends above the doped region. Example 52 may include the subject matter of any of Examples 48-51, and may further specify that the semiconductor body includes a fin or a nanowire. Example 53 may include the subject matter of any of Examples 48-52, and may further specify that doping the portion of the semiconductor body includes implanting a dopant into the portion of the semiconductor body. Example 54 is a computing device, including: a processing device including an electrical element, a metal on the electrical element, and a semiconductor material having a doped region that is adjacent to the metal, wherein the metal conductively couples the doped region and the electrical element; and a memory device in electrical communication with the processing device. Example 55 may include the subject matter of Example 54, and may further specify that the doped region is a part of a transistor. Example 56 may include the subject matter of any of Examples 54-55, and may further specify that the electrical element includes an epitaxial source/drain portion of a transistor. Example 57 may include the subject matter of any of Examples 54-56, and may further include a communication chip. | 95,948 |
11942527 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. An integrated chip may comprise, in some embodiments, a transistor device arranged over a substrate. In some configurations, to increase device density on the substrate, the transistor device may comprise, for example, a nanosheet field effect transistor (NSFET), a fin field effect transistor (finFET), or some other type of transistor. As transistor devices reduce in size to increase device density, an interconnect structure may be formed on a frontside of the substrate over the transistor device, and then, a backside of the substrate may be patterned to form a backside contact coupled to one or more components (e.g., source/drain regions, gate electrode) of the transistor device. Some advantages of using the frontside and the backside of the transistor device include, for example, an increase in device density, a reduction in capacitance/cross-talk between conductive features, and the ability to use both sides of the transistor device in packaging. In some instances, during the formation of a transistor device over a frontside of a substrate, a first removal process is performed to form a trench within a semiconductor material to define channel structures. To accommodate a backside contact on the source/drain region, the trench extends further below the channel structures such that a lower portion of the trench is arranged below the channel structures, and an upper portion of the trench is arranged between the channel structures. A dummy source/drain material is formed within the lower portion of the trench, and a source/drain region is formed within the upper portion of the trench. After the formation of the transistor device and a frontside interconnect structure arranged over the transistor device, a backside of the substrate is thinned to expose a surface of the dummy source/drain material within the lower portion of the trench. Then, the dummy source/drain material is removed and replaced by a conductive material within the lower portion of the trench, thereby forming a backside contact coupled to the source/drain region. However, the lower portion of the trench has a width that increases from the backside of the transistor device towards the frontside of the transistor device, which may cause voids to form within the backside contact upon deposition of the conductive material within the lower portion of the trench. Various embodiments of the present disclosure are directed towards performing a second removal process after the first removal process to form a wide cavity below the channel structures. Thus, in some embodiments, the first removal process forms a trench that defines channel structures of the transistor device. After the first removal process, a second removal process is performed using a wet etch to form a cavity below and connected to the trench. The wet etch of the second removal process removes portions of the substrate in the vertical and horizontal directions such that the cavity has a larger maximum width than the trench. In some embodiments, the backside of the substrate is later thinned such that the exposed surface of the dummy source/drain material is the widest surface of the remaining dummy source/drain material. This way, when the dummy source/drain material is removed, a backside opening extends from a backside of the transistor device towards the source/drain region. Further, the backside opening has a width that decreases from the backside of the transistor device towards the source/drain region. In such embodiments, a conductive material is formed within the backside opening to form a backside contact coupled to the source/drain region. Because the backside opening has a width that decreases from the backside of the transistor device towards the source/drain region, voids and/or seams are mitigated in the backside contact which increases reliability of the backside contact and thus, overall transistor device. FIG.1Aillustrates a cross-sectional view100A of some embodiments of an integrated chip comprising a nanosheet field effect transistor (NSFET) that comprises a backside contact. The integrated chip of the cross-sectional view100A is on an xz-plane and includes a source/drain region106arranged between channel structures107. In some embodiments, a gate electrode104is arranged over the channel structures107. In some embodiments, each channel structure107comprises multiple nanosheet channel structures102, wherein the gate electrode104is arranged above and below each nanosheet channel structures102. In some embodiments, a gate dielectric layer112is arranged between the gate electrode104and the channel structure107. In some embodiments (not shown), the gate dielectric layer112is also arranged between lower portions of the gate electrode104and each nanosheet channel structure102. In some embodiments, inner gate spacer structures108are arranged directly between the nanosheet channel structures102in the z-direction and surrounding outer sidewalls of the gate electrode104in the x-direction. In some embodiments, upper gate spacer structures110are arranged on outer sidewalls of the gate electrode104arranged over the channel structures107. In some embodiments, an upper interconnect structure117is arranged over the gate electrode104. In some embodiments, the upper interconnect structure117comprises an interconnect contact116and an interconnect conductive structure118embedded in an upper interconnect dielectric structure114. In some embodiments, the upper interconnect structure117is electrically coupled to the gate electrode104. In some embodiments, the interconnect contact116comprises a topmost surface that is wider than a bottommost surface. In some embodiments, the interconnect conductive structure118is, for example, another interconnect contact, an interconnect wire, an interconnect via, or the like. In some embodiments, the source/drain region106extends in the z-direction from the upper interconnect structure117to a lower interconnect structure124. In some embodiments, the lower interconnect structure124comprises a backside contact122that is surrounded by a lower interconnect dielectric structure120and that is electrically coupled to the source/drain region106. In some embodiments, by forming a lower interconnect structure124on the NSFET, device density may be increased and electrical isolation between the backside contact122and the gate electrode104, the interconnect contact116, and/or the interconnect conductive structure118may be increased. In some embodiments, the backside contact122has a topmost surface122tthat has a first width w1measured in the x-direction and a bottommost surface122bmthat has a second width w2measure in the x-direction. In some embodiments, the first width w1is a minimum width of the backside contact122, and the second width w2is a maximum width of the backside contact122. Thus, the second width w2is greater than the first width w1. Further, in some embodiments, the topmost surface122tof the backside contact122is coupled to the bottommost surface122bmof the backside contact122through outermost sidewalls122sof the backside contact122. In some embodiments, the outermost sidewalls122sof the backside contact122are substantially flat or planar. In some embodiments, the first width w1may be in a range of between, for example, approximately 10 nanometers and approximately 75 nanometers. In some embodiments, the second width w2may be in a range of between, for example, approximately 20 nanometers and approximately 80 nanometers. Further, in some embodiments, the outermost sidewalls122smay be arranged at a first angle a1measured between the outermost sidewall122sof the backside contact122and a bottommost surface of the gate electrode104. In some embodiments, the first angle a1is an acute angle (e.g., less than 90 degrees). In some embodiments, the first angle a1may be in a range of between, for example, approximately 40 degrees and approximately 60 degrees. In some embodiments, the backside contact122may have a height measured in the z-direction between the topmost and bottommost surfaces122t,122bmthat is in a range of between, approximately 10 nanometers and approximately 40 nanometers, for example. Further, in some embodiments, a width of the backside contact122continuously decreases as the width of the backside contact122, which is measured in the x-direction, is measured from the bottommost surface122bmof the backside contact122towards the topmost surface122tof the backside contact122in the z-direction. In some embodiments, to form the backside contact122, a conductive material is formed within a backside opening in the lower interconnect dielectric structure120. The backside opening has a same profile as the backside contact122and thus, has a continuously decreasing width measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114. In some embodiments, the backside opening may be formed using a wet etch prior to the formation of the source/drain region106. The wet etch may widen the backside opening. Because a width of the backside contact122continuously decreases as the width of the backside contact122is measured from the bottommost surface122bmmof the backside contact122towards the topmost surface122tof the backside contact, the backside contact122is formed without or with a reduced number of voids and/or seams. Thus, the NSFET may comprise an upper interconnect structure117and a lower interconnect structure124to save space in the x-direction, thereby increasing device density of the NSFET, with mitigated reliability issues in the backside contact122. FIG.1Billustrates a cross-sectional view100B of some embodiments of the NSFET ofFIG.1Aon a yz-plane. In some embodiments, the cross-sectional view100B ofFIG.1Bcorresponds to cross-section line BB′ ofFIG.1A. In some such embodiments, the backside contact122may still have a trapezoidal-like shape on the yz-plane, wherein the topmost surface122tof the backside contact122is narrower than the bottommost surface122bmof the backside contact122. In some embodiments, the yz-plane is substantially perpendicular to the xz-plane ofFIG.1A. In some embodiments, the inner gate spacer structure108is arranged on upper surfaces of the source/drain region106and may laterally surround the source/drain region106. In some embodiments, the source/drain region106has a substantially hexagonal profile from the yz-plane. In some other embodiments, the source/drain region106has a different shaped profile from the yz-plane such as, for example, an octagon, a diamond, a pentagon, or the like. Nevertheless, it will be appreciated that the source/drain region106may exhibit a different shape when viewing the NSFET from a yz-plane versus an xz-plane. FIG.2Aillustrates a cross-sectional view200A of some other embodiments of an integrated chip comprising a nanosheet field effect transistor (NSFET) that comprises a backside contact. In some embodiments, the outermost sidewalls122sof the backside contact122may be substantially rounded. In some embodiments, the outermost sidewalls122smay be concave down with respect to the xz-axis. In some embodiments, a width of the backside contact122still continuously decreases as the width of the backside contact122, which is measured in the x-direction, is measured from the bottommost surface122bmof the backside contact122towards the topmost surface122tof the backside contact122in the z-direction. In some embodiments, the first width w1may be in a range of between, for example, approximately 10 nanometers and approximately 90 nanometers. In some embodiments, the second width w2may be in a range of between, for example, approximately 20 nanometers and approximately 100 nanometers. It will be appreciated, as further described inFIGS.11A and11Bof the method, that the various shapes of the backside contact122are due to different wet etchants used to form the backside opening. FIG.2Billustrates a cross-sectional view200B of some embodiments of the NSFET ofFIG.2Aon a yz-plane. In some embodiments, the cross-sectional view200B ofFIG.2Bcorresponds to cross-section line BB′ ofFIG.2A. In some such embodiments, the backside contact122may still have outermost sidewalls122sthat are substantially rounded and coupled the topmost surface122tto the bottommost surface122bmof the backside contact122on the yz-plane. Further, from the yz-plane, in some embodiments, the topmost surface122tof the backside contact122is still narrower than the bottommost surface122bmof the backside contact122. FIG.3Aillustrates a cross-sectional view300A of some embodiments of an integrated chip comprising a fin field effect transistor (finFET) that comprises a backside contact. In some other embodiments, the channel structures107that surround the source/drain region106may be fin structures302. In some embodiments, the fin structures302extend from the lower interconnect dielectric structure120to the gate electrode104in the z-direction. In some embodiments, the backside contact122may still be arranged below and coupled to the source/drain region106. In some embodiments, the backside contact122has a trapezoidal-like shape as described inFIG.1A, for example. In some embodiments, the channel structures107may comprise a first semiconductor material, and the source/drain region106may comprise a second semiconductor material that is different than the first semiconductor material. In some embodiments, for example, the first semiconductor material comprises polysilicon, germanium, or the like, and the second semiconductor material comprises silicon germanium, for example. In some embodiments, the backside contact122may comprise a conductive material such as, for example, tungsten, ruthenium, aluminum, copper, or some other suitable conductive material. In some embodiments (not shown), liner and/or barrier layers may be arranged between the backside contact122and the lower interconnect dielectric structure120and/or between the backside contact122and the source/drain region106. FIG.3Billustrates a cross-sectional view300B of some other embodiments of an integrated chip comprising a fin field effect transistor (finFET) that comprises a backside contact. In some other embodiments, the backside contact122arranged below and coupled to the source/drain region106of the finFET comprises outermost sidewalls122sthat are substantially rounded. Thus, in some embodiments, the backside contact122has a rounded shape as described inFIG.2A, for example. FIG.4Aillustrates a cross-sectional view400A of some embodiments of an integrated chip comprising an NSFET with first and second source/drain regions between a channel structure, wherein a first backside contact is arranged on the first source/drain region. In some embodiments, an NSFET401comprises a channel structure107extending between a first source/drain region106aand a second source/drain region106b. It will be appreciated that in some other embodiments, the NSFET401may be also known as, for example, a gate-all-around FET, a gate surrounding transistor, a multi-bridge channel (MBC) transistor, a nanowire FET, or the like. In some embodiments, the gate electrode104is arranged over the channel structure107and coupled to a gate voltage line VGthrough the upper interconnect structure117. In some embodiments, a drain contact404is arranged over and coupled to second source/drain region106b. Thus, in some embodiments, a drain voltage line VD1is coupled to the second source/drain region106bthrough the upper interconnect structure117. In some embodiments, the drain contact404and the interconnect contacts116of the upper interconnect structure have upper surfaces wider than bottom surfaces. In some embodiments, the channel structure107comprises nanosheet channel structures102, wherein the gate electrode104also is arranged between the nanosheet channel structures102in the z-direction. In some embodiments, the first source/drain region106ais coupled to a first backside contact122aarranged below the first source/drain region106a. In such embodiments, to reduce defects (e.g., voids, seams, etc.) in the first backside contact122a, the first backside contact122ahas a width that continuously decreases when measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114. In some embodiments, the first source/drain region106ais a source region, and the second source/drain region106bis a drain region. In some embodiments, the first source/drain region106ais coupled to a source voltage line VS1through the first backside contact122a. When a voltage bias that is greater than a threshold voltage of the NSFET401is applied across the nanosheet channel structures102by way of the gate voltage line VG, the source voltage line VS1, and the drain voltage line VD1, the nanosheet channel structures102may be turned “ON” such that mobile charge carriers travel through a channel region402between the first and second source/drain regions106a,106b. At least due to the decreasing width of the first backside contact122ain the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114, the NSFET401may be reliably turned “ON” and “OFF” when voltages are applied to the gate voltage line VG, the source voltage line VS1, and the drain voltage line VD2. FIG.4Billustrates a bottom-view400B of some embodiments of the NSFET ofFIG.4A. In some embodiments, the bottom-view400B ofFIG.4Bis from a bottom-side perspective ofFIG.4A. Further, in some embodiments the bottom-view400B ofFIG.4Bignores the lower interconnect dielectric structure120ofFIG.4A. The bottom-view400B ofFIG.4Bis from an xy-plane perspective. In some embodiments, the cross-sectional view400A ofFIG.4Amay correspond to cross-section line AA′ ofFIG.4B. As illustrated in the bottom-view400B ofFIG.4B, in some embodiments, the first source/drain region106ais arranged behind the first backside contact122a, and thus, the first source/drain region106ais illustrated with a hashed line. In some embodiments, the gate electrode104has a larger height in the y-direction than the first and second source/drain regions106a,106b. In some embodiments, the interconnect contact116coupled to the gate electrode104and the drain contact404coupled to the second source/drain region106bare arranged behind the gate electrode104and the second source/drain region106b, respectively, and thus, are not illustrated in the bottom-view400B ofFIG.4B. FIG.4Cillustrates a cross-sectional view400C of some other embodiments of an NSFET, wherein backside contacts are arranged on the first and second source/drain regions. As shown in the cross-sectional view400C ofFIG.4C, in some other embodiments, a second backside contact122bmay be arranged below and coupled to the second source/drain region106bof the NSFET401instead of the drain contact (404ofFIG.4A). In such embodiments, the second backside contact122bmay also have a width that continuously decreases when measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114. In such embodiments, the first and second backside contacts122a,122bmay be spaced apart from one another in the x-direction by the lower interconnect dielectric structure120. To reduce defects (e.g., voids, seams, etc.) in the first and second backside contacts122a,122b, the first and second backside contacts122a,122bhave a width that continuously decreases when measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114. When a voltage bias that is greater than a threshold voltage of the NSFET401is applied across the nanosheet channel structures102by way of the gate voltage line VG, the source voltage line VS1, and the drain voltage line VD1, the nanosheet channel structures102may be turned “ON” such that mobile charge carriers travel through a channel region402between the first and second source/drain regions106a,106b. At least due to the decreasing width of the first and second backside contacts122a,122bin the z-direction from the lower interconnect dielectric structure120towards the upper interconnect dielectric structure114, the NSFET401may be reliably turned “ON” and “OFF” when voltages are applied to the gate voltage line VG, the source voltage line VS1, and the drain voltage line VD1. FIG.4Dillustrates a bottom-view400D of some embodiments of the NSFET ofFIG.4C. In some embodiments, the bottom-view400D ofFIG.4Dis from a bottom-side perspective ofFIG.4C. Further, in some embodiments the bottom-view400D ofFIG.4Dignores the lower interconnect dielectric structure120ofFIG.4C. The bottom-view400D ofFIG.4Dis from an xy-plane perspective. In some embodiments, the cross-sectional view400C ofFIG.4Cmay correspond to cross-section line CC′ ofFIG.4D. As illustrated in the bottom-view400D ofFIG.4D, in some embodiments, the first source/drain region106ais arranged behind the first backside contact122a, and the second source/drain region106bis arranged behind the second backside contact122b. Thus, the first and source/drain regions106a,106bare illustrated with hashed lines. In some embodiments, the interconnect contact116coupled to the gate electrode104is arranged behind the gate electrode104, and thus, is not illustrated in the bottom-view400D ofFIG.4D. FIGS.5A-24illustrate cross-sectional views500A-2400of some embodiments of a method of forming a backside contact on a source/drain region of a transistor device. AlthoughFIGS.5A-24are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.5A-24are not limited to such a method, but instead may stand alone as structures independent of the method. As shown in cross-sectional view500A ofFIG.5A, a substrate502is provided. In various embodiments, the substrate502may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, Ge, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. In some embodiments, the substrate502comprises a lower semiconductor layer503, an etch stop layer505arranged over the lower semiconductor layer503, and an upper semiconductor layer507arranged over the etch stop layer505. In some embodiments, the etch stop layer505comprises a semiconductor material, such as silicon germanium, that is different than the upper and lower semiconductor layers503,507. In some other embodiments, the etch stop layer505may comprise an oxide. In such other embodiments, the substrate502may be a silicon-on-insulator substrate, and the etch stop layer505may comprise, for example, silicon oxide. In some embodiments, the etch stop layer505may be partially doped. In other words, in some embodiments, the etch stop layer505may have a doping concentration in a range of between about 60 percent and about 85 percent, for example. In some embodiments, the etch stop layer505has a thickness in a range of between, for example, approximately 10 nanometers and approximately 20 nanometers. In some embodiments, a stack of semiconductor layers501is formed over a frontside502fof the substrate502. The stack of semiconductor layers501may comprise spacer layers504and semiconductor layers506arranged in an alternating order. In some embodiments, the spacer layers504comprise a different material than the semiconductor layers506. In some embodiments, for example, the spacer layers504comprise germanium silicon or germanium, whereas the semiconductor layers506comprise silicon. In some embodiments, the semiconductor layers506and the spacer layers504are formed by an epitaxy growth process from the substrate502. In some embodiments, there may be more or less than three semiconductor layers506and three spacer layers504. FIG.5Billustrates a cross-sectional view500B of some alternative embodiments ofFIG.5A, wherein the substrate502is a bulk substrate and does not comprise the etch stop layer (505ofFIG.5A). As shown in cross-sectional view600ofFIG.6, in some embodiments, a dummy gate structure604arranged over a gate dielectric layer112are formed over the stack of semiconductor layers501. In some embodiments, to form the dummy gate structure604and the gate dielectric layer112, a continuous gate dielectric layer is formed over the stack of semiconductor layers501. In some embodiments, the continuous gate dielectric layer, and thus, the gate dielectric layer112, comprises a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. In some embodiments, a continuous dummy gate layer is then formed over the continuous gate dielectric layer. In some embodiments, the dummy gate layer, and thus, the dummy gate structure604, may comprise, for example, polysilicon. In some embodiments, the continuous gate dielectric layer and the continuous dummy gate layer are formed by way of a thermal oxidation process and/or deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), etc.). Then, in some embodiments, the gate dielectric layer112and the dummy gate structure604may be formed from the continuous gate dielectric layer and the continuous dummy gate layer, respectively, using photolithography and removal (e.g., etching) processes. In some embodiments, more than one dummy gate structure604and underlying gate dielectric layer112may be arranged over the stack of semiconductor layers501. For example, in the cross-sectional view600ofFIG.6, two dummy gate structures604are spaced apart from one another over the stack of semiconductor layers501. As shown in cross-sectional view700ofFIG.7, in some embodiments, a conformal first gate layer710is formed over the stack of semiconductor layers501and the dummy gate structure604. In some embodiments, the conformal first gate layer710comprises an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), or some other suitable dielectric material. In some embodiments, the conformal first gate layer710is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). As shown in cross-sectional view800A ofFIG.8A, in some embodiments, a first removal process802is performed to form a trench804between the dummy gate structures604, thereby forming a first channel structure107aspaced apart from a second channel structure107bby the trench804and on a frontside502fof the substrate502. In some embodiments, the trench804has a depth measured in the z-direction in a range of between, for example, approximately 40 nanometers and approximately 100 nanometers. In some embodiments, the first removal process802removes portions of the semiconductor layers (506ofFIG.7) and the spacer layers (504ofFIG.7) that are uncovered by the dummy gate structures604. In some embodiments, the dummy gate structures604act as a masking structure for the first removal process802such that each of the first and second channel structures107a,107bare arranged directly below the dummy gate structures604. In some embodiments, the first and second channel structures107a,107bcomprise multiple nanosheet channel structures102spaced apart from one another by patterned spacer layers806after the first removal process802. Further, in some embodiments, the first removal process802removes substantially horizontal portions of the conformal first gate layer (710ofFIG.7) to form upper gate spacer structures110on outermost sidewalls of the dummy gate structure604and the gate dielectric layer112. In some embodiments, the first removal process802removes a portion of the substrate502. For example, in some embodiments, the trench804extends below the first and second channel structures107a,107band into the substrate502by a first distance d1. In some embodiments, the first distance d1is in a range of between, for example, approximately 5 nanometers and approximately 55 nanometers. In some embodiments, the first removal process802comprises a dry etchant and may be performed in the substantially vertical or the z-direction. In some such embodiments, the trench804may have a width measured in the x-direction that continuously decreases as the width of the trench804is measured from the dummy gate structure604to the substrate502. FIG.8Billustrates a cross-sectional view800B of some other embodiments of the method, wherein after the first removal process, the first and second channel structures107a,107bcomprise fin structures302. In other words, in some other embodiments, the method ofFIGS.5A-24may be applied to transistors other than NSFETs. For example, in some embodiments, the method ofFIGS.5A-24illustrating steps to form a backside contact on a source/drain region may be applied to a fin field effect transistor (finFET). In such other embodiments, the formation of the stack of semiconductor layers (501ofFIG.5A) may be omitted from the method. In such embodiments, after the first removal process802, the first channel structure107aand the second channel structure107bmay each comprise a fin structure302that is continuously connected to and comprises a same material as the substrate502. As shown in cross-sectional view900ofFIG.9, after the first removal process (802ofFIG.8A), a continuous protection layer902is formed over the dummy gate structures604, along outer sidewalls of the first and second channel structures107a,107b, and the substrate502. In some embodiments, the continuous protection layer902comprises, for example, an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), or some other suitable material. In some embodiments, the continuous protection layer902may be formed by way of a thermal oxidation process or deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). As shown in cross-sectional view1000ofFIG.10, in some embodiments, a removal process is performed to remove substantially horizontal portions of the continuous protection layer (902ofFIG.9) from the substrate502and the dummy gate structures604, thereby forming a protection layer1002on outer sidewalls of the first and second channel structures107a,107b. In some embodiments, the removal process ofFIG.10used to form the protection layer1002comprises a dry etching process that utilizes a dry etchant performed in the substantially vertical or z-direction. As shown in cross-sectional view1100A ofFIG.11A, in some embodiments, a second removal process1102is performed to form a cavity1104within the substrate502that is coupled to the trench804. In some embodiments, the cavity1104is arranged below the first and second channel structures107a,107b. In some embodiments, the second removal process1102is a wet etching process that utilizes a wet etchant. Thus, in some embodiments, the cavity1104is wider than the trench804and is arranged directly below the first and second channel structures107a,107bbecause the wet etchant of the second removal process1102removes portions of the substrate502in the x-direction and in the y-direction. In some embodiments, the protection layer1002protects the first and second channel structures107a,107bfrom removal by the second removal process1102. In other words, in some embodiments, the protection layer1002, the dummy gate structure604and the upper gate spacer structures110are substantially resistant to removal by the second removal process1102. In some embodiments, the wet etchant used during the second removal process1102comprises ammonium hydroxide. In such embodiments, the cavity1104may exhibit a hexagonal-like profile from the xz-plane as inFIG.11Abecause the ammonium hydroxide removes the substrate502along certain planes of the substrate502at different etch rates. In such embodiments, the ammonium hydroxide is an anisotropic etch because it has different etch rates in different directions. In some embodiments, the ammonium hydroxide removes the [111] planes of the substrate502faster (e.g., up to 10-20 times) than the [100] planes of the substrate502. Further, in some embodiments, the ammonium hydroxide removes the [100] planes of the substrate502faster (e.g., 1-2 times) than the [110] planes of the substrate502. In some embodiments, a bottom surface1104bof the cavity1104is defined by the etch stop layer505of the substrate502. Thus, in some embodiments, the etch stop layer505of the substrate502is substantially resistant to removal by the second removal process1102and prevents the second removal process1102from extending through the entire substrate502. In some such embodiments, the cavity1104is formed within the upper semiconductor layer507and not the lower semiconductor layer503of the substrate502. It will be appreciated that the exact shape of the cavity1104is dependent upon the material of the substrate502, the crystal structure of the substrate502, and/or the second removal process1102parameters (e.g., etchant time, etchant composition, etc.). In some embodiments, wherein the second removal process1102comprises an anisotropic wet etchant, such as ammonium hydroxide, the cavity1104formed in the substrate502will resemble some type of polygon-shape. In some embodiments, the ammonium hydroxide is between approximately 20 weight percent to approximately 35 weight percent in a water solvent. In some embodiments, the concentration between the ammonium hydroxide to the water solvent ranges from a ratio between approximately 1:3 to approximately 1:20. In some embodiments, the second removal process1102may be conducted in a single wafer processing chamber set to a temperature in a range of between about 25 degrees Celsius and about 60 degrees Celsius. In some embodiments, the second removal process1102may be performed for approximately 10 seconds to approximately 120 seconds when ammonium hydroxide is used. In some embodiments, the bottom surface1104bof the cavity1104is arranged at a first angle a1with a lower outermost sidewall of the cavity1104. Similarly, in some embodiments, an upper outermost sidewall of the cavity1104is arranged at the first angle a1with the frontside502fof the substrate502. In some embodiments, the first angle a1is an acute angle (e.g., less than 90 degrees). In some embodiments, the first angle a1may be in a range of between, for example, approximately 40 degrees and approximately 60 degrees. In some embodiments, the bottom surface1104bof the cavity is arranged at a second distance d2below the frontside502fof the substrate502. In some embodiments, the second distance d2is in a range of between, for example, approximately 40 nanometers and approximately 90 nanometers. Further, in some embodiments, the cavity1104may have a variable width1104wthat is measured in the x-direction. In some embodiments, the variable width1104wof the cavity1104varies through the z-direction of the cavity1104. In some embodiments, the variable width1104wof the cavity1104may be in a range of between, for example, approximately 20 nanometers and approximately 80 nanometers. In some embodiments, the variable width1104whas a maximum value arranged at a third distance d3below a lowermost one of the patterned spacer layers806. Similarly, in some embodiments, the variable width1104whas a maximum value arranged at a fourth distance d4above the etch stop layer505. FIG.11Billustrates a cross-sectional view1100B of some other embodiments, wherein the cavity1104formed by the second removal process1102resembles a circle on the xz-plane. In some such embodiments, the second removal process1102may comprise an isotropic wet etchant. For example, in some embodiments, the isotropic wet etchant comprises diluted hydrofluoric acid in an ozone water mixture, which is commonly known as a “FOM isotropic etchant.” In such embodiments, the ozone water mixture of the FOM isotropic etchant oxidizes portions of the substrate502(e.g., oxidizes a silicon substrate to silicon dioxide) while the diluted hydrofluoric acid of the FOM isotropic etchant removes the oxidized portions of the substrate502(e.g., silicon dioxide) to form the cavity1104. In such embodiments, the isotropic wet etchant may remove portions of the substrate502in all directions at a substantially constant rate of removal such that the cavity1104has an overall circular shape. In some embodiments, the hydrofluoric acid is between approximately 40 weight percent to approximately 60 weight percent in ozone-water. In some embodiments, the concentration between the hydrofluoric acid to the ozone-water ranges from a ratio between approximately 1:1 to approximately 1:10. In some embodiments, the second removal process1102may be conducted in a single wafer processing chamber set to a temperature in a range of between about 20 degrees Celsius and about 40 degrees Celsius. In some embodiments, the second removal process1102may be performed for approximately 30 minutes to approximately 120 minutes when the FOM isotropic etchant is used. In some embodiments, a bottom surface1104bof the cavity, as defined by the etch stop layer505, is arranged at a second distance d2below the frontside502fof the substrate502. In some embodiments, the second distance d2is in a range of between, for example, approximately 40 nanometers and approximately 90 nanometers. Further, in some embodiments, the cavity1104may have a variable width1104wthat is measured in the x-direction. In some embodiments, the variable width1104wof the cavity1104varies through the z-direction of the cavity1104. In some embodiments, the variable width1104wof the cavity1104may be in a range of between, for example, approximately 20 nanometers and approximately 100 nanometers. In some embodiments, the variable width1104whas a maximum value arranged at a third distance d3below a lowermost one of the patterned spacer layers806. Similarly, in some embodiments, the variable width1104whas a maximum value arranged at a fourth distance d4above the etch stop layer505. FIG.11Cillustrates a cross-sectional view1100C of some other embodiments of the method after the second removal process1102, wherein first and second channel structures107a,107bcomprise fin structures302. In some such embodiments, the wet etchant used during the second removal process1102comprises ammonium hydroxide. In such embodiments, the cavity1104may exhibit a hexagonal-like profile from the xz-plane as explained inFIG.11Abecause the ammonium hydroxide removes the substrate502along certain planes of the substrate502at different etch rates. In some other embodiments (not shown), the wet etchant of the second removal process1102may comprise the FOM isotropic etchant as described inFIG.11B, and thus, the cavity1104ofFIG.11Cwould have a more rounded profile. In some embodiments, the cavity1104ofFIG.11Chas a depth equal to a second distance d2measured in the z-direction. In some embodiments, the second depth d2is in a range of between, for example approximately 40 nanometers and approximately 80 nanometers. In some embodiments, an upper portion of the cavity1104may have a depth equal to a third distance d3, and a lower portion of the cavity1104may have a depth equal to a fourth distance d4, wherein the second distance d2equals to the sum of the third and fourth distances d3, d4. In some embodiments, the third distance d3may be in a range of between, for example, approximately 10 nanometers and approximately 30 nanometers, and the fourth distance d4may be in a range of between for example, approximately 30 nanometers and approximately 50 nanometers, for example, As shown in cross-sectional view1200ofFIG.12, in some embodiments, the method proceeds fromFIG.11AtoFIG.12. In some embodiments, inFIG.12, the protection layer (1002ofFIG.11A) is removed from the first and second channel structures107a,107b. In some embodiments, the removal of the protection layer (1002ofFIG.11A) may be performed through a wet or dry etching process. As shown in cross-sectional view1300ofFIG.13, in some embodiments, a lateral removal process may be performed to selectively remove outer portions of the patterned spacer layers806. In some embodiments, the lateral removal process reduces a width of the patterned spacer layers806by two times a fifth distance d5. In some embodiments, the lateral removal process is a wet or dry etching process. In some embodiments, the lateral removal process comprises an isotropic etchant. In some embodiments, the nanosheet channel structures102and the substrate502comprise different materials than the patterned spacer layers806and are resistant to removal by the lateral removal process ofFIG.13. As shown in cross-sectional view1400ofFIG.14, in some embodiments, a spacer layer1408is formed over the first and second channel structures107a,107band the etch stop layer505of the substrate502. In some embodiments, the spacer layer1408comprises, for example, a dielectric material such as silicon nitride, silicon oxynitride, silicon carbon nitride, or some other suitable dielectric material. In some embodiments, the spacer layer1408is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the spacer layer1408has a thickness that is at least equal to the third distance d3. As shown in cross-sectional view1500ofFIG.15, a removal process is performed to remove portions of the spacer layer (1408) that are not arranged directly on the patterned spacer layers806to form inner gate spacer structures108directly between the nanosheet channel structures102. In some embodiments, the removal process ofFIG.15comprises a wet or dry etchant. It will be appreciated that in some other embodiments, wherein the first and second channel structures do not comprise nanosheet channel structures102such as in a finFET device, the steps inFIG.13-15may be omitted. As shown in cross-sectional view1600ofFIG.16, in some embodiments, a dummy source/drain material1604is formed within the cavity (1104ofFIG.15) of the substrate502, and a source/drain region106is formed over the dummy source/drain material1604and directly between the first and second channel structures107a,107b. In some embodiments, the dummy source/drain material1604may comprise a semiconductor material that is formed by an epitaxy growth process from the etch stop layer505of substrate502. For example, in some embodiments, the dummy source/drain material1604comprise silicon germanium or some other suitable semiconductor material. The dummy source/drain material1604comprises a same or different material than the etch stop layer505of the substrate502. In some embodiments, the source/drain region106also comprises a semiconductor material that is formed by an epitaxy growth process. In some embodiments, the source/drain region106comprises doped (e.g., n-type, p-type) silicon germanium or some other suitable semiconductor material. In some embodiments, the dummy source/drain material1604comprises an undoped semiconductor material, whereas the source/drain region106comprises a doped material. Further, in some embodiments, the dummy source/drain material1604is wider than the source/drain region106. As shown in cross-sectional view1700ofFIG.17, in some embodiments, an upper interconnect dielectric structure114is formed over the source/drain region106and between the dummy gate structures604. In some embodiments, the upper interconnect dielectric structure114comprises, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. In some embodiments, the upper interconnect dielectric structure114may be formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). As shown in cross-sectional view1800ofFIG.18, in some embodiments, the dummy gate structures (604ofFIG.17) are removed and replaced by gate electrodes104. In some embodiments, the dummy gate structures (604ofFIG.17) are removed by an etching (e.g., wet, dry) process. In some embodiments, the inner gate spacer structures108, the upper gate spacer structures110, and the gate dielectric layer112are substantial resistant to removal by the removal process ofFIG.18. In some embodiments, the gate electrodes104are formed over and between the nanosheet channel structures102. In some embodiments, the gate electrodes104are formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, the gate electrodes104comprise a conductive material, such as, for example, titanium, tantalum, aluminum, or some other suitable conductive material. Further, in some embodiments, after removing the dummy gate structures (604ofFIG.17) but before forming the gate electrodes104, additional gate dielectric layers may be formed on the nanosheet channel structures102. Further in some embodiments, the gate electrodes104may comprise multiple layers of conductive materials. As illustrated in cross-sectional view1900ofFIG.19, in some embodiments, an upper interconnect structure117is formed over the gate electrodes104. In some embodiments, the upper interconnect structure117comprises an interconnect contact116and an interconnect conductive structure118arranged within the upper interconnect dielectric structure114. In some embodiments, the interconnect contact116and the interconnect conductive structure118may comprise a conductive material such as, for example, copper, aluminum, tungsten, tantalum, titanium, or some other suitable conductive material. In some embodiments, the upper interconnect structure117is formed through various steps comprising deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and/or patterning processes (e.g., photolithography/etching). Further, in some embodiments, the upper interconnect structure117does not comprise any contacts/vias coupled to the source/drain region106. As shown in cross-sectional view2000ofFIG.20, in some embodiments, a first bonding layer2006is formed over the upper interconnect structure117, and then a second bonding layer2004arranged on a carrier substrate2002is bonded to the first bonding layer2006. In other words, in some embodiments, the carrier substrate2002is bonded to the upper interconnect structure117on the frontside502fof the substrate502through the first and second bonding layers2006,2004. In some embodiments, the first and second bonding layers2006,2004are formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first and second bonding layers2006,2004comprise an oxide, such as, for example, silicon dioxide. In some embodiments, the bonding process to bond the first bonding layer2006to the second bonding layer2004may comprise a thermal bonding process, for example. It will be appreciated that other bonding processes are also within the scope of the disclosure. As shown in cross-sectional view2100ofFIG.21, in some embodiments, the structure in the cross-sectional view2000ofFIG.20is flipped such that a backside502bof the substrate502is facing “up” to be patterned. In such embodiments, the carrier substrate2002may protect the upper interconnect structure117from damage. As shown in cross-sectional view2200A ofFIG.22A, in some embodiments, a thinning process is performed on the backside (502bofFIG.21) of the substrate (502ofFIG.21) to remove portions of the substrate (e.g.,503,505of substrate502ofFIG.21) and the dummy source/drain material1604to expose a surface1604sof the dummy source/drain material1604. In some embodiments, the thinning process comprises a planarization process such as, for example, chemical mechanical planarization (CMP). In some embodiments, after the exposure of the surface1604sof the dummy source/drain material1604, the substrate (e.g.,507of substrate502ofFIG.21) is removed by a removal process and replaced by a lower interconnect dielectric structure120. In some embodiments, the lower interconnect dielectric structure120may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.) and may comprise, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or the like. In some embodiments, the upper interconnect dielectric structure114may be formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the dummy source/drain material is substantially resistant to removal by the removal process used to remove the substrate (502ofFIG.21). In some embodiments, the exposed surface1604sof the dummy source/drain material1604has a second width w2that is a maximum width of the dummy source/drain material1604inFIG.22A. In some embodiments, the second width w2ofFIG.22Ais less than or equal to a maximum value of the variable width (1104wofFIG.11A) of the cavity (1104ofFIG.11A) previously formed inFIG.11A. In some embodiments, an interface1604ibetween the dummy source/drain material1604has a first width w1that is a minimum width of the dummy source/drain material1604. Further, in such embodiments, a width of the dummy source/drain material1604ofFIG.22Acontinuously decreases as the width is measured from the exposed surface1604sto the interface1604i. Thus, in some embodiments, the thinning process ofFIG.22Ais stopped once the width of the dummy source/drain material1604ofFIG.22Acontinuously decreases as the width is measured from the exposed surface1604sto the interface1604i. Therefore, in some embodiments, the dummy source/drain material1604has a first height h1measured in the z-direction that is less than or equal to the third distance (d3ofFIG.21). Thus, the thinning process ofFIG.22Aat least removes a thickness of the dummy source/drain material1604ofFIG.21equal to the fourth distance (d4ofFIG.21) such that inFIG.22A, after the thinning process, the exposed surface1604sof the dummy source/drain material1604has a second width w2that is a maximum width of the dummy source/drain material1604. FIG.22Billustrates a cross-sectional view2200B of some alternative embodiments of the dummy source/drain material1604after the thinning process described inFIG.22A. Thus, in some other embodiments, the first height h1of the dummy source/drain material1604after the thinning process may have an exposed surface1604sthat is not a maximum width of the dummy source/drain material1604. In such embodiments, the exposed surface1604sof the dummy source/drain material1604has a second width w2that is between a maximum width and a minimum width of the dummy source/drain material1604inFIG.22A. In some such embodiments, the timing of the thinning process may have been reduced such that the first height h1of the dummy source/drain material is greater than the third distance (d3of FIG.21). In some embodiments, the thinning process may be repeated until the second width w2of the exposed surface1604sis a maximum width of the dummy source/drain material1604, or the method may proceed without repeating the thinning process. As shown in cross-sectional view2300ofFIG.23, which proceeds fromFIG.22A, in some embodiments, the dummy source/drain material (1604ofFIG.22A) is removed from the source/drain region106thereby forming a backside opening2302in the lower interconnect dielectric structure120and over the source/drain region106. In some embodiments, the dummy source/drain material (1604ofFIG.22A) is removed using a wet etch or a dry etch. In some embodiments, the backside opening2302has a bottom surface having the first width w1and an upper surface having the second width w2. Further, in some embodiments, a width of the backside opening2302continuously decreases as the width is measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect structure117. As shown in cross-sectional view2400ofFIG.24, in some embodiments, a conductive material is formed within the backside opening (2302ofFIG.23) to form a backside contact122coupled to the source/drain region106and surrounded by the lower interconnect dielectric structure120. In some embodiments, the backside contact122is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.) followed by a removal process (e.g., CMP) such that the backside contact122has surfaces that are substantially co-planar with the lower interconnect dielectric structure120. In some embodiments, the backside contact122comprises a conductive material such as, for example, tungsten, ruthenium, aluminum, copper, or some other suitable conductive material. Thus, in some embodiments, a lower interconnect structure124comprising the backside contact122and the lower interconnect dielectric structure120is arranged on a backside of a transistor device, such as an NSFET, as illustrated in the cross-sectional view2400ofFIG.24. In some embodiments, the first angle a1being acute allows for the backside contact122to have a width that continuously decreased as the width was measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect structure117. If the first angle a1were obtuse, the width would increase as the width was measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect structure117. In some embodiments, the first angle a1is based on the angle between the [111] planes and the [100] planes of the substrate502. In some embodiments, the first angle a1is in a range of between, for example, approximately 50 degrees and 60 degrees. In some embodiments, one half of a difference between the first and second widths w1, w2(i.e., ½(w2-w1)) is equal to the first height h1divided by the tangent of the first angle a1(i.e., h1/(tan(a1)). For example, in some embodiments, the first angle a1may equal 54.7 degrees. In such embodiments, the first height h1may equal 1.41(½(w2-w1)) because the tangent of 54.7 degrees is about equal to 1.41. Because the backside opening (2302ofFIG.23) had a width that continuously decreased as the width was measured in the z-direction from the lower interconnect dielectric structure120towards the upper interconnect structure117, the backside contact122was formed within the backside opening (2302ofFIG.23) without or with mitigated voids and seams. This way, the backside contact122has a reduced number of defects which increases the reliability of the overall NSFET. Further, in such embodiments, by utilizing the frontside and the backside of the NSFET, the device density of the overall device is increased. FIG.25illustrates a flow diagram of some embodiments of a method2500corresponding to the method of forming an NSFET or a finFET with a backside contact coupled to a source/drain region as illustrated inFIGS.5A-24. While method2500is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At act2502, a first dummy gate structure and a second dummy gate structure are formed over a frontside of a substrate.FIG.6illustrates a cross-sectional view600of some embodiments corresponding to act2502. At act2504, a first removal process is performed to form a trench in the substrate and between the first and second dummy gate structures.FIGS.8A and8Brespectively illustrate cross-sectional views800A and800B of some embodiments corresponding to act2504. At act2506, a second removal process is performed to from a cavity within the substrate, below and connected to the trench, and that has a maximum width that is greater than a maximum width of the trench.FIGS.11A and11Brespectively illustrate cross-sectional views1100A and1100B of some embodiments corresponding to act2506. At act2508, a dummy material is formed within the cavity. At act2510, a source/drain region is formed within the trench.FIG.16illustrates a cross-sectional view1600of some embodiments corresponding to acts2508and2510. At act2512, the first and second dummy gate structures are replaced by first and second gate electrodes, respectively.FIG.18illustrates a cross-sectional view1800of some embodiments corresponding to act2512. At act2514, an upper interconnect structure is formed over the first and second gate electrodes.FIG.19illustrates a cross-sectional view1900of some embodiments corresponding to act2514. At act2516, a backside of the substrate is thinned to expose the dummy material within the cavity.FIG.22Aillustrates a cross-sectional view2200A of some embodiments corresponding to act2516. At act2518, the dummy material is replaced with a conductive material to form a backside contact coupled to the source/drain region, wherein the backside contact has a maximum width that is less than or equal to the maximum width of the cavity.FIG.24illustrates a cross-sectional view2400of some embodiments corresponding to act2518. Therefore, the present disclosure relates to a method of forming a backside contact on a source/drain region of a transistor by using a wet etch such that the backside contact has a width that continuously decreases from a bottommost surface to a topmost surface of the backside contact to mitigate defects of the backside contact. Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising: a channel structure extending between a first source/drain region and a second source/drain region; a gate electrode arranged directly over the channel structure; an upper interconnect contact arranged over and coupled to the gate electrode; and a backside contact arranged below and coupled to the first source/drain region, wherein the backside contact has a width that continuously decreases as its measured at different heights from a bottommost surface of the backside contact to a topmost surface of the backside contact. In other embodiments, the present disclosure relates to an integrated chip comprising: a channel structure extending between a first source/drain region and a second source/drain region; a gate electrode arranged directly over the channel structure; an upper interconnect contact arranged over and coupled to the gate electrode; and a first backside contact arranged below and coupled to the first source/drain region, wherein a bottommost surface of the first backside contact has a first width, wherein a topmost surface of the first backside contact has a second width, wherein the first width is a maximum width of the first backside contact, and wherein the second width is a minimum width of the first backside contact. In yet other embodiments, the present disclosure relates to a method comprising: forming a first dummy gate structure and a second dummy gate structure over a frontside of a substrate; performing a first removal process to form a trench by removing portions of the substrate according to the first and second dummy gate structures, wherein the trench defines a first channel structure underlying the first dummy gate structure and a second channel structure underlying the second dummy gate structure; performing a second removal process to form a cavity within the substrate, wherein the cavity is arranged below the first and second channel structures, wherein the cavity has a first width that is greater than a second width of the trench, wherein the first width is a maximum width of the cavity, and wherein the second width is a maximum width of the trench; forming a dummy material within the cavity; forming a source/drain region within the trench; replacing the first and second dummy gate structures with first and second gate electrodes, respectively; forming an upper interconnect structure over the first and second gate electrodes; thinning a backside of the substrate to expose the dummy material within the cavity; and replacing the dummy material with a conductive material to form a backside contact coupled to the source/drain region, wherein the backside contact has a maximum width that is less than or equal to the first width of the cavity. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 63,598 |
11942528 | DETAILED DESCRIPTION FIGS.1A,2A,3A, and4Aillustrate plan views showing operations of methods of manufacturing semiconductor devices according to some of the present inventive concepts.FIGS.1B,2B,3B, and4Billustrate cross-sectional views taken along line A-A′ ofFIGS.1A,2A,3A, and4A, respectively.FIGS.2C,3C, and4Cillustrate cross-sectional views taken along line B-B′ ofFIGS.2A,3A, and4A, respectively.FIGS.2D,3D, and4Dillustrate cross-sectional views taken along line C-C′ ofFIGS.2A,3A, and4A, respectively. Referring toFIGS.1A and1B, a substrate100may be provided. The substrate100may be a semiconductor substrate, or may include a semiconductor substrate. For example, the substrate100may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. A device isolation layer ST may be formed on the substrate100. The formation of the device isolation layer ST may include patterning the substrate100to form trenches defining first to fourth active patterns AP1to AP4, forming an insulation layer on an entire surface of the substrate100, and recessing the insulation layer. The device isolation layer ST may have a top surface lower than those of the first to fourth active patterns AP1to AP4. The device isolation layer ST may define the first to fourth active patterns AP1to AP4on an upper portion of the substrate100. Each of the first to fourth active patterns AP1to AP4may have a linear or bar shape extending in a second direction D2. The first to fourth active patterns AP1to AP4may be sequentially arranged along a first direction D1. The first to fourth active patterns AP1to AP4may be spaced apart from each other in the first direction D1. In some embodiments, the first to fourth active patterns AP1to AP4may be equally spaced apart from each other in the first direction D1. The first and fourth active patterns AP1and AP4may be active patterns positioned at outermost positions. For example, the first and fourth active patterns AP1and AP4may be outermost active patterns. The second and third active patterns AP2and AP3may be between the first and fourth active patterns AP1and AP4. For example, the second and third active patterns AP2and AP3may be inner active patterns. The first active pattern AP1may include a first sidewall SW1and a second sidewall SW2. The first sidewall SW1may face the second active pattern AP2. The second sidewall SW2may stand opposite to the first sidewall SW1. The fourth active pattern AP4may include a third sidewall SW3and a fourth sidewall SW4. The third sidewall SW3may face the third active pattern AP3. The fourth sidewall SW4may stand opposite to the third sidewall SW3. The second active pattern AP2and the third active pattern AP3may have sidewalls, which are unlabeled inFIG.1B. The device isolation layer ST may include outer segments ST1and intermediate segments ST2. The outer segments ST1may be formed on the second sidewall SW2of the first active pattern AP1and on the fourth sidewall SW4of the fourth active pattern AP4. The intermediate segments ST2may be formed between the first and second active patterns AP1and AP2, between the second and third active patterns AP2and AP3, and between the third and fourth active patterns AP3and AP4. Referring toFIGS.2A to2D, sacrificial patterns PP may be formed to run across the first to fourth active patterns AP1to AP4. Each of the sacrificial patterns PP may have a linear or bar shape extending in the first direction D1. Each of the sacrificial patterns PP may be perpendicular to the first through fourth active patterns AP1to AP4, when viewed in a plan view. The formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate100, forming mask patterns MP on the sacrificial layer, and using the mask patterns MP as an etching mask to etch the sacrificial layer. The sacrificial layer may be formed using polysilicon. The mask patterns MP may be formed using a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. For example, the gate spacers GS may include one or more of SiCN, SiCON, and SiN. For another example, the gate spacers GS may include a multiple layer consisting of two or more of SiCN, SiCON, and SiN. The formation of the gate spacers GS may include performing a deposition process, such as CVD or ALD, to form a spacer layer on the entire surface of the substrate100, and performing an anisotropic etching process on the spacer layer. The mask patterns MP and the gate spacers GS may be used as an etching mask to etch the first to fourth active patterns AP1to AP4. The first to fourth active patterns AP1to AP4may be etched to form recesses RS, as best seen inFIG.2D. The device isolation layer ST may be etched at the same time when the first to fourth active patterns AP1to AP4are etched. The outer segment ST1of the device isolation layer ST may have an etched top surface at a level lower than that of an etched top surface of the intermediate segment ST2of the device isolation layer ST. The second sidewall SW2of the first active pattern AP1and the fourth sidewall SW4of the fourth active pattern AP4may be partially exposed by the outer segments ST1of the device isolation layer ST, as best seen inFIG.2B. Referring toFIGS.3A to3D, source/drain patterns SD may be formed to fill the recesses RS. The formation of the source/drain patterns SD may include performing a selective epitaxial growth process in which the first to fourth active patterns AP1to AP4are used as seed layers. After the selective epitaxial growth process, the source/drain patterns SD may be doped with P-type impurities or N-type impurities. The source/drain pattern SD may have a flat top surface. Each of the source/drain patterns SD may include first to sixth parts SDP1to SDP6, as best seen inFIG.3B. The first part SDP1may be formed on the first active pattern AP1, the second part SDP2may be formed on the second active pattern AP2, the third part SDP3may be formed on the third active pattern AP3, and the fourth part SDP4may be formed on the fourth active pattern AP4. The first to fourth parts SDP1to SDP4may be formed on respective upper surfaces of the first to fourth active patterns AP1to AP4. The first to fourth parts SDP1to SDP4may be connected to each other. For example, the first to fourth parts SDP1to SDP4may be merged with each other. The fifth part SDP5may be formed on the second sidewall SW2of the first active pattern AP1. The fifth part SDP5may extend from the first part SDP1and along an upper portion of the second sidewall SW2. The fifth part SDP5may have a bottom surface whose lowermost level is lower than a lowermost level of the top surface of each of the intermediate segments ST2between the first to fourth active patterns AP1to AP4below the source/drain pattern SD. The lowermost level of the bottom surface of the fifth part SDP5may be lower than an uppermost level of the top surface of the outer segment ST1on the second sidewall SW2of the first active pattern AP1below the source/drain pattern SD. The fifth part SDP5may partially cover the top surface of the outer segment ST1on the second sidewall SW2of the first active pattern AP1. The top surfaces of the first to fourth active patterns AP1to AP4below the source/drain pattern SD may be located at a first level LV1. The lowermost level of the bottom surface of the fifth part SDP5may be lower than the first level LV1. The sixth part SDP6may be formed on the fourth sidewall SW4of the fourth active pattern AP4. The sixth part SDP6may extend from the fourth part SDP4and along an upper portion the fourth sidewall SW4. The sixth part SDP6may have a bottom surface whose lowermost level is lower than the lowermost level of the top surface of each of the intermediate segments ST2between the first to fourth active patterns AP1to AP4below the source/drain pattern SD. The lowermost level of the bottom surface of the sixth part SDP6may be lower than an uppermost level of the top surface of the outer segment ST1on the fourth sidewall SW4of the fourth active pattern AP4below the source/drain pattern SD. The sixth part SDP6may partially cover a top surface of the outer segment ST1on the fourth sidewall SW4of the fourth active pattern AP4. The lowermost level of the bottom surface of the sixth part SDP6may be lower than the first level LV1. In some embodiments, the source/drain pattern SD may differ from that shown, and may include one, or only one, of the fifth and sixth parts SDP5and SDP6. Voids VO may be formed between the source/drain pattern SD and the intermediate segments ST2of the device isolation layer ST. For example, a void VO may be formed between the third active pattern AP3and the fourth active pattern AP4, above the intermediate segment ST2between the third active pattern AP3and the fourth active pattern AP4, and below the source/drain pattern SD (and more specifically, below a portion of the third part SDP3and below a portion of the fourth part SDP4). The voids VO may be substantially empty spaces. The voids VO may be filled with air. Referring toFIGS.4A to4D, a first interlayer dielectric layer110may be formed on the substrate100. A planarization process may be performed on the first interlayer dielectric layer110until top surfaces of the sacrificial patterns PP are exposed. The planarization process may include an etch-back process and/or a chemical mechanical polishing (CMP) process. When the first interlayer dielectric layer110is planarized, the mask patterns MP may be removed. The first interlayer dielectric layer110may include, for example, a silicon oxide layer or a silicon oxynitride layer. The planarization process may remove the exposed sacrificial patterns PP. The removal of the sacrificial patterns PP may form empty spaces each of which is provided between a pair of neighboring gate spacers GS. The empty spaces may expose the first to fourth active patterns AP1to AP4. A gate dielectric pattern GI and a gate electrode GE may be formed in each of the empty spaces. The formation of the gate dielectric pattern GI and the gate electrode GE may include forming a gate dielectric layer on surfaces in the empty space, partially filling the empty space, and forming a gate electrode layer to completely fill the empty space. The filling of the empty space with the gate electrode layer may form the gate electrode GE. The gate dielectric layer may include a high-k dielectric material. The high-k dielectric material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate electrode layer may include, for example, one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). Gate capping patterns CP may be formed on the gate electrodes GE. The gate capping pattern CP may include a material having an etch selectivity with respect to the first interlayer dielectric layer110. The gate capping patterns CP may include, for example, one or more of SiON, SiCN, SiCON, and SiN. A second interlayer dielectric layer120may be formed on the first interlayer dielectric layer110and the gate capping patterns CP. The second interlayer dielectric layer120may include, for example, a silicon oxide layer or a silicon oxynitride layer. Contacts CT may be formed to penetrate the first and second interlayer dielectric layers110and120and to come into connection with the source/drain patterns SD. For example, the contacts CT may include metal, such as titanium, tantalum, tungsten, copper, or aluminum. A third interlayer dielectric layer130may be formed on the second interlayer dielectric layer120and the contacts CT. The third interlayer dielectric layer130may include, for example, a silicon oxide layer or a silicon oxynitride layer. Via contacts V1and wiring lines M1may be formed in the third interlayer dielectric layer130. The via contact V1may electrically connect the wiring line M1and the contact CT to each other. Each of the via contact V1and the wiring line M1may include metal whose resistance is low. The low resistance metal may be or include, for example, copper or tungsten. The wiring line M1may be provided on the via contact V1. The wiring line M1may extend in the second direction D2. The wiring lines M1may be spaced apart from each other in the first direction D1. A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference toFIGS.4A to4D. The device isolation layer ST may be provided on the substrate100. The device isolation layer ST may define the first to fourth active patterns AP1to AP4on an upper portion of the substrate100. The device isolation layer ST may have a top surface lower than those of the first to fourth active patterns AP1to AP4. The first to fourth active patterns AP1to AP4may be sequentially arranged along the first direction D1. Each of the first to fourth active patterns AP1to AP4may extend in the second direction D2. The recesses RS may be correspondingly provided on the first to fourth active patterns AP1to AP4. The device isolation layer ST may include the outer segments ST1and the intermediate segments ST2. The outer segment ST1of the device isolation layer ST may have a top surface at a level lower than that of a top surface of the intermediate segment ST2of the device isolation layer ST. The top surface of the outer segment ST1on the second sidewall SW2of the first active pattern AP1may become lower with increasing distance from the first active pattern AP1. The top surface of the outer segment ST1on the fourth sidewall SW4of the fourth active pattern AP4may become lower with increasing distance from the fourth active pattern AP4. The source/drain patterns SD may be provided on the first to fourth active patterns AP1to AP4. The source/drain patterns SD may fill the recesses RS. Each of the source/drain patterns SD may include the first to sixth parts SDP1to SDP6. The first to fourth parts SDP1to SDP4may be merged with each other. The fifth part SDP5may extend from the first part SDP1and along the second sidewall SW2of the first active pattern AP1. The sixth part SDP6may extend from the fourth part SDP4and along the fourth sidewall SW4of the fourth active pattern AP4. The gate electrodes GE may extend in the first direction D1, while running across the first to fourth active patterns AP1to AP4. The gate electrodes GE may be spaced apart from each other in the second direction D2. For example, the gate electrode GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D1along the gate electrode GE. The gate spacers GS may have top surfaces higher than that of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with that of the first interlayer dielectric layer110. The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to fourth active patterns AP1to AP4. The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate dielectric pattern GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate capping pattern CP may be provided on each of the gate electrodes GE. The gate capping pattern CP may extend in the first direction D1along the gate electrode GE. The first interlayer dielectric layer110may be provided on an entire surface of the substrate100. The first interlayer dielectric layer110may cover the device isolation layer ST, the gate electrodes GE, and the source/drain patterns SD. The first interlayer dielectric layer110may have a top surface substantially coplanar with those of the gate capping patterns CP. The second interlayer dielectric layer120may be provided on the first interlayer dielectric layer110. The contacts CT may extend at least partially into the first and second interlayer dielectric layers110and120and come into connection with the source/drain patterns SD. The third interlayer dielectric layer130may be provided on the second interlayer dielectric layer120and the contacts CT. The via contacts V1and the wiring lines M1may be provided in the third interlayer dielectric layer130. A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference toFIGS.4A,4C,4D, and5.FIG.5illustrates a cross-sectional view taken along line A-A′ ofFIG.4Aof a semiconductor device according to an example of an embodiment. For brevity of description, components substantially the same as those discussed with reference toFIGS.4A to4Dare allocated the same reference numerals thereto, and repetitive explanations thereof may be omitted in favor of the description provided above. The device isolation layer ST may be provided on the substrate100. The device isolation layer ST may define the first to fourth active patterns AP1to AP4on an upper portion of the substrate100. Each of the outer segments ST1of the device isolation layer ST may have a top surface at a level substantially the same as or similar to that of a top surface of each of the intermediate segments ST2of the device isolation layer ST. For example, the level of the top surface of each outer segment ST1ofFIG.5may be higher than the top surface of each outer segment ST1ofFIG.2B. The recesses RS may be correspondingly provided on the first to fourth active patterns AP1to AP4. The source/drain patterns SD may be provided on the first to fourth active patterns AP1to AP4. Each of the source/drain patterns SD may include the first to fourth parts SDP1to SDP4. The first part SDP1may be formed on the first active pattern AP1, the second part SDP2may be formed on the second active pattern AP2, the third part SDP3may be formed on the third active pattern AP3, and the fourth part SDP4may be formed on the fourth active pattern AP4. The first to fourth parts SDP1to SDP4may be connected to each other. For example, the first to fourth parts SDP1to SDP4may be merged with each other. According to the present example embodiment, the source/drain patterns SD may not include the fifth and sixth parts SDP5and SDP6discussed above with reference toFIGS.3A to3D. The first and second parts SDP1and SDP2may define a first valley VA1. For example, the first valley VA1may be defined by top surfaces of the first and second parts SDP1and SDP2. The first valley VA1may cause the source/drain pattern SD to have a non-flat top surface that connects an uppermost portion of the first part SDP1to an uppermost portion of the second part SDP2. The first valley VA1may cause the source/drain pattern SD to have a non-flat top surface between an uppermost portion of the first part SDP1and an uppermost portion of the second part SDP2. The first valley VA1may be interposed between the first and second parts SDP1and SDP2. The first valley VA1may have a first depth D1. The first depth D1may correspond to a height between a bottom VA1B of the first valley VA1and the uppermost portion of the first part SDP1and/or the second part SDP2. The bottom VA1B of the first valley VA1may be located at a level lower than that of the uppermost portion of the first part SDP1and that of the uppermost portion of the second part SDP2. The second and third parts SDP2and SDP3may define a second valley VA2. For example, the second valley VA2may be defined by top surfaces of the second and third parts SDP2and SDP3. The second valley VA2may cause the source/drain pattern SD to have a non-flat top surface that connects the uppermost portion of the second part SDP2to an uppermost portion of the third part SDP3. The second valley VA2may cause the source/drain pattern SD to have a non-flat top surface between the uppermost portion of the second part SDP2and an uppermost portion of the third part SDP3. The second valley VA2may be interposed between the second and third parts SDP2and SDP3. The second valley VA2may have a second depth D2. The second depth D2may correspond to a height between a bottom VA2B of the second valley VA2and the uppermost portion of the second part SDP2and/or the third part SDP3. The second depth D2may be less than the first depth D1. The bottom VA2B of the second valley VA2may be located at a level lower than that of the uppermost portion of the second part SDP2and that of the uppermost portion of the third part SDP3. The level of the bottom VA2B of the second valley VA2may be higher than the level of the bottom VA1B of the first valley VA1. The source/drain pattern SD may have a flat top surface that connects the uppermost portion of the third part SDP3to an uppermost portion of the fourth part SDP4. For example, no valley may be formed between the third and fourth parts SDP3and SDP4. The gate electrodes GE may be provided to extend in the first direction D1, while running across the first to fourth active patterns AP1to AP4. A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to fourth active patterns AP1to AP4. The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate capping pattern CP may be provided on each of the gate electrodes GE. The first interlayer dielectric layer110may be provided on an entire surface of the substrate100. The second interlayer dielectric layer120may be provided on the first interlayer dielectric layer110. The contacts CT may extend at least partially into the first and second interlayer dielectric layers110and120and to come into connection with the source/drain patterns SD. The third interlayer dielectric layer130may be provided on the second interlayer dielectric layer120and the contacts CT. The via contacts V1and the wiring lines M1may be provided in the third interlayer dielectric layer130. FIGS.6A,7A,8A,9A,10A, and11Aillustrate plan views showing a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concepts.FIGS.6B,7B,8B,9B,10B, and11Billustrate cross-sectional views taken along line A-A′ ofFIGS.6A,7A,8A,9A,10A, and11A, respectively.FIGS.7C,8C,9C,10C, and11C illustrate cross-sectional views taken along line B-B′ ofFIGS.7A,8A,9A,10A, and11A, respectively.FIGS.7D,8D,9D,10D, and11Dillustrate cross-sectional views taken along line C-C′ ofFIGS.7A,8A,9A,10A, and11A, respectively. For brevity of description, components substantially the same as those discussed with reference toFIGS.1A to4Dare allocated the same reference numerals thereto, and a repetitive explanation thereof may be omitted herein in favor of the explanation provided above. Referring toFIGS.6A and6B, a substrate100may be provided. The substrate100may include a first region RG1and a second region RG2. A device isolation layer ST may be formed on the substrate100. The formation of the device isolation layer ST may include patterning the first and second regions RG1and RG2to form trenches that define first to fourth active patterns AP1to AP4on the first region RG1and also define fifth to eighth active patterns AP5to AP8on the second region RG2, forming an insulation layer on an entire surface of the substrate100, and then recessing the insulation layer. The device isolation layer ST may have a top surface lower than those of the first to eighth active patterns AP1to AP8. The device isolation layer ST may define the first to eighth active patterns AP1to AP8on an upper portion of the substrate100. Each of the first to eighth active patterns AP1to AP8may have a linear or bar shape extending in a second direction D2. The first to eighth active patterns AP1to AP8may be sequentially arranged along a first direction D1. The first to eighth active patterns AP1to AP8may be spaced apart from each other in the first direction D1. Referring toFIGS.7A to7D, sacrificial patterns PP may be formed to run across the first to eighth active patterns AP1to AP8. Each of the sacrificial patterns PP may be perpendicular to the first to eighth active patterns AP1to AP8, when viewed in a plan view. The formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate100, forming mask patterns MP on the sacrificial layer, and using the mask patterns MP as an etching mask to etch the sacrificial layer. A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. A pair of insulation spacers IS may be formed on opposite sidewalls of each of the first to eighth active patterns AP1to AP8. The gate spacers GS and the insulation spacers IS may be formed at the same time. The gate spacers GS and the insulation spacers IS may include the same material. For example, the gate spacers GS and the insulation spacers IS may each include one or more of SiCN, SiCON, and SiN. For another example, the gate spacers GS and the insulation spacers IS may each include a multiple layer consisting of two or more of SiCN, SiCON, and SiN. The formation of the gate spacers GS and the insulation spacers IS may include performing a deposition process, such as CVD or ALD, to form a spacer layer on the entire surface of the substrate100, and performing an anisotropic etching process on the spacer layer. Referring toFIGS.8A to8D, the first to fourth active patterns AP1to AP4on the first region RG1of the substrate100may be etched to form first recesses RS1. The first recesses RS1are best seen inFIG.8D. The etching of the first to fourth active patterns AP1to AP4may include coating a first photoresist layer on the entire surface of the substrate100, patterning the first photoresist layer by a first photolithography process to form a first photoresist pattern PR1, and using the first photoresist pattern PR1as an etching mask to etch the first to fourth active patterns AP1to AP4. The insulation spacers IS may include first to fourth insulation spacers IS1to IS4. The first to fourth insulation spacers IS1to IS4may be formed on opposite sidewalls of the first to fourth active patterns AP1to AP4, respectively. When the first to fourth active patterns AP1to AP4are etched, the first to fourth insulation spacers IS1to IS4may also be etched. The first to fourth insulation spacers IS1to IS4may have different etching degrees from each other. In such cases, the first to fourth insulation spacers IS1to IS4may have different maximum heights from each other. For example, the maximum heights of the first insulation spacers IS1on the opposite sidewalls of the first active pattern AP1may be greater than the maximum heights of the second insulation spacers IS2on the opposite sidewalls of the second active pattern AP2. The maximum heights of the third insulation spacers IS3on the opposite sidewalls of the third active pattern AP3may be greater than the maximum heights of the first insulation spacers IS1. The first insulation spacers IS1may partially expose the sidewalls of the first active pattern AP1. The second insulation spacers IS2may partially expose the sidewalls of the second active pattern AP2. A first trench TR1may be formed at the same time when the first to fourth active patterns AP1to AP4are etched. The first trench TR1may be formed by etching the device isolation layer ST between the fourth and fifth active patterns AP4and AP5. For example, a portion of the device isolation layer ST that is adjacent to the fourth active pattern AP4may be etched, which may result in the formation of the first trench TR1. The first trench TR1may extend in the second direction D2. Referring toFIGS.9A to9D, the fifth to eighth active patterns AP5to AP8on the second region RG2of the substrate100may be etched to form second recesses RS2. The etching of the fifth to eighth active patterns AP5to AP8may include coating a second photoresist layer on the entire surface of the substrate100, patterning the second photoresist layer by a second photolithography process to form a second photoresist pattern PR2, and using the second photoresist pattern PR2as an etching mask to etch the fifth to eighth active patterns AP5to AP8. The insulation spacers IS may include fifth to eighth insulation spacers IS5to IS8. The fifth to eighth insulation spacers IS5to IS8may be formed on opposite sidewalls of the fifth to eighth active patterns AP5to AP8, respectively. When the fifth to eighth active patterns AP5to AP8are etched, the fifth to eighth insulation spacers IS5to IS8may also be etched. The fifth to eighth insulation spacers IS5to IS8may have different etching degrees from each other. In such cases, the fifth to eighth insulation spacers IS5to IS8may have different maximum heights from each other. For example, the maximum heights of the fifth insulation spacers IS5on the opposite sidewalls of the fifth active pattern AP5may be greater than the maximum heights of the sixth insulation spacers IS6on the opposite sidewalls of the sixth active pattern AP6. The maximum heights of the seventh insulation spacers IS7on the opposite sidewalls of the seventh active pattern AP7may be greater than the maximum heights of the fifth insulation spacers IS5. The fifth insulation spacers IS5may partially expose the sidewalls of the fifth active pattern AP5. The sixth insulation spacers IS6may partially expose the sidewalls of the sixth active pattern AP6. A second trench TR2may be formed at the same time when the fifth to eighth active patterns AP5to AP8are formed. The second trench TR2may be formed by etching the device isolation layer ST between the first trench TR1and the fifth active pattern AP5. For example, a portion of the device isolation layer ST that is adjacent to the fifth active pattern AP5may be etched, which may result in the formation of the second trench TR2. The second trench TR2may extend in the second direction D2. The first and second trenches TR1and TR2may define a protrusion PT therebetween, as best seen inFIG.9B. The protrusion PT may be a portion of the device isolation layer ST provided between the first and second trenches TR1and TR2. The protrusion PT may extend in the second direction D2. A first length L1may refer to a shortest distance in the first direction D1between the fourth active pattern AP4and an uppermost portion of the protrusion PT. A second length L2may refer to a shortest distance in the first direction D1between the fifth active pattern AP5and the uppermost portion of the protrusion PT. Stated differently, a first length L1may refer to a shortest distance in the first direction D1from the uppermost portion of the protrusion PT to the active pattern on the first region RG1that is closest to the protrusion PT, and a second length L2may refer to a shortest direction in the first direction D1from the uppermost portion of the protrusion PT to the active pattern on the second region RG2that is closest to the protrusion PT. For example, as shown inFIG.9B, the first length L1may be less than the second length L2. For another example, differently from that shown inFIG.9B, the first length L1may be the same as or greater than the second length L2. Referring toFIGS.10A to10D, first source/drain patterns SD1may be formed to fill the first recesses RS1. The formation of the first source/drain patterns SD1may include performing a selective epitaxial growth process in which the first to fourth active patterns AP1to AP4are used as seed layers. Simultaneously with or after the selective epitaxial growth process to form the first source/drain patterns SD1, the first source/drain patterns SD1may be doped with P-type impurities. Second source/drain patterns SD2may be formed to fill the second recesses RS2. The formation of the second source/drain patterns SD2may include performing a selective epitaxial growth process in which the fifth to eighth active patterns AP5to AP8are used as seed layers. The formation of the second source/drain patterns SD2may be formed simultaneously with the formation of the first source/drain patterns SD1, but the present disclosure is not limited thereto. Simultaneously with or after the selective epitaxial growth process to form the second source/drain patterns SD2, the second source/drain patterns SD2may be doped with N-type impurities. Each of the first source/drain patterns SD1may include first to fourth parts SD1P1to SD1P4. The first part SD1P1may be formed on the first active pattern AP1, the second part SD1P2may be formed on the second active pattern AP2, the third part SD1P3may be formed on the third active pattern AP3, and the fourth part SD1P4may be formed on the fourth active pattern AP4. The first part SD1P1may be spaced apart from the second part SD1P2. The fourth part SD1P4may be spaced apart from the third part SD1P3. The second part SD1P2may be merged with the third part SD1P3. The second and third parts SD1P2and SD1P3may have therebetween a boundary at a location where the second and third parts SD1P2and SD2P3are connected to each other while being selectively epitaxially grown. The first to fourth parts SD1P1to SD1P4may have their uppermost portions at the same level. The first part SD may have a first width W1corresponding to a maximum width in the first direction D1and a first height H1corresponding to a maximum height in a third direction D3. The second part SD1P2may have a second width W2corresponding to a maximum width in the first direction D1and a second height H2corresponding to a maximum height in the third direction D3. The third part SD1P3may have a third width W3corresponding to a maximum width in the first direction D1and a third height H3corresponding to a maximum height in the third direction D3. The fourth part SD1P4may have a fourth width W4corresponding to a maximum width in the first direction D1and a fourth height H4corresponding to a maximum height in the third direction D3. The second width W2may be greater than the first width W1, and the second height H2may be greater than the first height H1. For example, the second part SD1P2may have a size greater than that of the first part SD1P1. The second part SD1P2may have a bottom surface whose lowermost level is lower than a lowermost level of a bottom surface of the first part SD1P1. The third width W3may be less than the second width W2, and the third height H3may be less than the second height H2. For example, the third part SD1P3may have a size less than that of the second part SD1P2. The lowermost level of the bottom surface of the second part SD1P2may be lower than a lowermost level of a bottom surface of the third part SD1P3. The fourth width W4may be less than the second width W2, and the fourth height H4may be less than the second height H2. For example, the fourth part SD1P4may have a size less than that of the second part SD1P2. The lowermost level of the bottom surface of the second part SD1P2may be lower than a lowermost level of a bottom surface of the fourth part SD1P4. Each of the second source/drain patterns SD2may include fifth to eighth parts SD2P5to SD2P8. The fifth part SD2P5may be formed on the fifth active pattern AP5, the sixth part SD2P6may be formed on the sixth active pattern AP6, the seventh part SD2P7may be formed on the seventh active pattern AP7, and the eighth part SD2P8may be formed on the eighth active pattern APB. The fifth part SD2P5may be spaced apart from the sixth part SD2P6. The eighth part SD2P8may be spaced apart from the seventh part SD2P7. The sixth part SD2P6may be merged with the seventh part SD2P7. The sixth and seventh parts SD2P6and SD2P7may have therebetween a boundary at a location where the sixth and seventh parts SD2P6and SD2P7are connected to each other while being selectively epitaxially grown. The fifth to eighth parts SD2P5to SD2P8may have their uppermost portions at the same level. The fifth part SD2P5may have a fifth width W5corresponding to a maximum width in the first direction D1and a fifth height H5corresponding to a maximum height in the third direction D3. The sixth part SD2P6may have a sixth width W6corresponding to a maximum width in the first direction D1and a sixth height H6corresponding to a maximum height in the third direction D3. The seventh part SD2P7may have a seventh width W7corresponding to a maximum width in the first direction D1and a seventh height H7corresponding to a maximum height in the third direction D3. The eighth part SD2P8may have an eighth width W8corresponding to a maximum width in the first direction D1and an eighth height H8corresponding to a maximum height in the third direction D3. The sixth width W6may be greater than the fifth width W5, and the sixth height H6may be greater than the fifth height H5. For example, the sixth part SD2P6may have a size greater than that of the fifth part SD2P5. The sixth part SD2P6may have a bottom surface whose lowermost level is lower than a lowermost level of a bottom surface of the fifth part SD2P5. The seventh width W7may be less than the sixth width W6, and the seventh height H7may be less than the sixth height H6. For example, the seventh part SD2P7may have a size less than that of the sixth part SD2P6. The lowermost level of the bottom surface of the sixth part SD2P6may be lower than a lowermost level of a bottom surface of the seventh part SD2P7. The eighth width W8may be less than the sixth width W6, and the eighth height H8may be less than the sixth height H6. For example, the eighth part SD2P8may have a size less than that of the sixth part SD2P6. The lowermost level of the bottom surface of the sixth part SD2P6may be lower than a lowermost level of a bottom surface of the eighth part SD2P8. A void VO may be formed between the second and third parts SD1P2and SD1P3of the first source/drain pattern SD1. A void VO may also be formed between the sixth and seventh parts SD2P6and SD2P7of the second source/drain pattern SD2. The voids VO may be substantially empty spaces. Referring toFIGS.11A to11D, a first interlayer dielectric layer110may be formed on the substrate100. A planarization process may be performed on the first interlayer dielectric layer110until top surfaces of the sacrificial patterns PP are exposed. When the first interlayer dielectric layer110is planarized, the mask patterns MP may be removed. The planarization process may remove the exposed sacrificial patterns PP. The removal of the sacrificial patterns PP may form empty spaces each of which is provided between a pair of neighboring gate spacers GS. The empty spaces may expose the first to eighth active patterns AP1to AP8. A gate dielectric pattern GI and a gate electrode GE may be formed in each of the empty spaces. The formation of the gate dielectric pattern GI and the gate electrode GE may include conformally forming a gate dielectric layer in the empty space and forming a gate electrode layer to completely fill the empty space. The filling of the empty space with the gate electrode layer may form the gate electrode GE. Gate capping patterns CP may be formed on the gate electrodes GE. A second interlayer dielectric layer120may be formed on the first interlayer dielectric layer110and the gate capping patterns CP. First contacts CT1may be formed to penetrate the first and second interlayer dielectric layers110and120and to come into connection with the first source/drain patterns SD1. Second contacts CT2may be formed to penetrate the first and second interlayer dielectric layers110and120and to come into connection with the second source/drain patterns SD2. A third interlayer dielectric layer130may be formed on the second interlayer dielectric layer120, the first contacts CT1, and the second contacts CT2. Via contacts V1and wiring lines M1may be formed in the third interlayer dielectric layer130. The via contact V1may electrically connect the wiring line M1to the first contact CT1or to the second contact CT2. A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference toFIGS.11A to11D. The device isolation layer ST may be provided on the substrate100. The device isolation layer ST may define the first to eighth active patterns AP1to AP8on an upper portion of the substrate100. The first to fourth active patterns AP1to AP4may be provided on the first region RG1of the substrate100. The fifth to eighth active patterns AP5to AP8may be provided on the second region RG2of the substrate100. The device isolation layer ST may have a top surface lower than those of the first to eighth active patterns AP1to AP8. The first to eighth active patterns AP1to AP8may be sequentially arranged along the first direction D1. Each of the first to eighth active patterns AP1to AP8may extend in the second direction D2. The first recesses RS1may be correspondingly provided on the first to fourth active patterns AP1to AP4. The second recesses RS2may be correspondingly provided on the fifth to eighth active patterns AP5to AP8. The first source/drain patterns SD1may be provided on the first to fourth active patterns AP1to AP4. The first source/drain patterns SD1may fill the first recesses RS1. Each of the first source/drain patterns SD1may include the first to fourth parts SD1P1to SD1P4. The second and third parts SD1P2and SD1P3may be merged with each other. The first part SD1P1may be spaced apart from the second part SD1P2. The second part SD1P2may be larger than the first part SD1P1. The third part SD1P3may be smaller than the second part SD1P2. The second source/drain patterns SD2may be provided on the fifth to eighth active patterns AP5to AP8. The second source/drain patterns SD2may fill the second recesses RS2. Each of the second source/drain patterns SD2may include the fifth to eighth parts SD2P5to SD2P8. The sixth and seventh parts SD2P6and SD2P7may be merged with each other. The fifth part SD2P5may be spaced apart from the sixth part SD2P6. The sixth part SD2P6may be larger than the fifth part SD2P5. The seventh part SD2P7may be smaller than the sixth part SD2P6. The gate electrodes GE may be provided to extend in the first direction D1, while running across the first to eighth active patterns AP1to AP8. The gate electrodes GE may be spaced apart from each other in the second direction D2. For example, the gate electrode GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D1along the gate electrode GE. The gate spacers GS may have top surfaces higher than that of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with that of the first interlayer dielectric layer110. The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to eighth active patterns AP1to AP8. The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate dielectric pattern GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate capping pattern CP may be provided on each of the gate electrodes GE. The gate capping pattern CP may extend in the first direction D1along the gate electrode GE. The first interlayer dielectric layer110may be provided on an entire surface of the substrate100. The first interlayer dielectric layer110may cover the device isolation layer ST, the gate electrodes GE, and the first and second source/drain patterns SD1and SD2. The first interlayer dielectric layer110may have a top surface substantially coplanar with those of the gate capping patterns CP. The second interlayer dielectric layer120may be provided on the first interlayer dielectric layer110. The first contacts CT1may be provided to penetrate the first and second interlayer dielectric layers110and120and to come into connection with the first source/drain patterns SD1. The second contacts CT2may be provided to penetrate the first and second interlayer dielectric layers110and120and to come into connection with the second source/drain patterns SD2. The third interlayer dielectric layer130may be provided on the second interlayer dielectric layer120, the first contacts CT1, and the second contacts CT2. The via contacts V1and the wiring lines M1may be provided in the third interlayer dielectric layer130. AlthoughFIGS.1A to5show four active patterns AP1to AP4, this number of active patterns is merely an example used herein to discuss the inventive concepts disclosed herein, and in some embodiments there may be less than four active patterns or greater than four active patterns. Likewise, althoughFIGS.6A to11Dshow four active patterns AP1to AP4on the first region RG1, and four active patterns AP5to AP8on the second region RG2, these numbers of active patterns are merely examples used herein to discuss the inventive concepts disclosed herein, and in some embodiments there may be less than four active patterns on each region or greater than four active patterns on each region. In some embodiments, the number of active patterns in each region RG1and RG2may be different. A semiconductor device according to some of the present inventive concepts may include variously shaped source/drain patterns, and thus may have improved electrical characteristics. Although some examples of embodiments of the inventive concepts disclosed herein have been discussed with reference to the accompanying figures, it will be understood that various changes in form and details may be made therein without departing from the scope of the present disclosure. It therefore will be understood that the some example embodiments described above are merely illustrative, and are not limitative in all aspects. | 47,242 |
11942529 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments of the present disclosure are discussed in the context of forming a gate-all-around (GAA) field-effect-transistor (FET) device, and in particular, in the context of forming a replacement gate of a GAA FET device. In some embodiments, after forming a fin including a number of first semiconductor layers and a number of second semiconductor layers, which serve as sacrificial layers and channel layers, respectively, a connected (or interfacial) layer is formed over the fin. The connected layer may present a certain etching selectivity with respect to respective materials of the first and second semiconductor layers. Next, a dummy gate structure is formed over the fin, followed by a pull-back process that etches end portions of the sacrificial (first semiconductor) layers of the fin and end portions of the dummy gate structure more quickly than the connected layer (along a lengthwise direction of the fin). The respective etched portions (of the sacrificial layers and the dummy gate structure) are then filled with inner spacers. Next, source/drain structures are formed on opposite sides of the dummy gate structure, with an interlayer dielectric (ILD) overlaying them. Upon forming the ILD, the dummy gate structure is removed to form a gate trench. Next, the sacrificial layers are removed to extend the gate trench. An active gate structure is next formed in the gate trench to wrap around each of the channel layers. An active gate structure formed by the above described method can provide various advantages in advanced technology nodes. In general, a dummy gate structure is replaced with an active gate structure, and thus, the active gate structure may inherit the dimensions and profiles of the dummy gate structure (as formed). The existing technologies, however, face various issues, when forming the dummy gate structure over a fin that have first and second semiconductor layers formed of different materials. For example, the interface between the dummy gate structure and the fin is relatively rough (which may in turn result in forming one or more voids after the dummy gate structure is replaced). This may be partially due to the different materials of the first and second semiconductor layers having respective interfacial reaction with the dummy gate structure. By overlaying the fin with the disclosed connected layer that may “integrate” such different materials of the first and second semiconductor layers, the above-identified issues may be avoided. Further, the dummy gate structure can have a relatively smooth interface contacting the fin (or the connected layer), which can enhance overall performance of the formed device (e.g., by increasing controllability of the active gate structure that replaces the dummy gate structure). FIG.1illustrates a perspective view of an example GAA FET device100, in accordance with various embodiments. The GAA FET device100includes a substrate102and a number of nanostructures (e.g., nanosheets, nanowires, etc.)104above the substrate102. The semiconductor layers104are vertically separated from one another. Isolation regions106are formed on opposing sides of a protruded portion of the substrate102, with the nanostructures104disposed above the protruded portion. A gate structure108wraps around each of the nanostructures104(e.g., a full perimeter of each of the nanostructures104). Source/drain structures are disposed on opposing sides of the gate structure108, e.g., source/drain structure110shown inFIG.1. An interlayer dielectric (ILD)112is disposed over the source/drain structure110. FIG.1depicts a simplified GAA FET device, and thus, it should be understood that one or more features of a completed GAA FET device may not be shown inFIG.1. For example, the other source/drain structure opposite the gate structure108from the source/drain structure110and the ILD disposed over such a source/drain structure are not shown inFIG.1. Further,FIG.1is provided as a reference to illustrate a number of cross-sections in subsequent figures. As indicated, cross-section A-A is cut along a longitudinal axis of the gate structure108(e.g., in the X direction); cross-section B-B is cut along a longitudinal axis of one of the semiconductor layers104; cross-section C-C, which is parallel with cross-section B-B, is cut between two adjacent ones of the semiconductor layers104; and cross-section D-D, which is perpendicular to the cross-section A-A, is cut along a longitudinal axis of the semiconductor layers104and in a direction of a current flow between the source/drain structures (e.g., in the Y direction). Subsequent figures refer to these reference cross-sections for clarity. FIG.2illustrates a flowchart of a method200to form a non-planar transistor device, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method200can be used to form a FinFET device, a GAA FET device (e.g., GAA FET device100), a nanosheet transistor device, a nanowire transistor device, a vertical transistor device, a gate-all-around (GAA) transistor device, or the like. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIG.2, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional views of an example GAA FET device at various fabrication stages as shown inFIGS.3,4A,4B,5A,5B,5C,6A,6B,6C,7A,7B,7C,8,9A,9B,9C,9D,9E,10A,10B,10C,10D,10E,11A,11B,11C,11D,11E,11F,11G,11H,11I,11J, and11K, respectively, which will be discussed in further detail below. In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming a fin structure including a number of first semiconductor layers and a number of second semiconductor layers. The method200continues to operation206of forming an isolation structure. The method200continues to operation208of forming a connected layer over the fin structure. The method200continues to operation210of forming a dummy gate structure. The method200continues to operation212of removing portions of the fin structure. The method200continues to operation214of etching portions of the first semiconductor layers and portions of the dummy gate structure. The method200continues to operation216of forming inner spacers. The method200continues to operation218of removing the first semiconductor layers and forming an active gate structure. As mentioned above,FIGS.3-11Keach illustrate, in a cross-sectional view, a portion of a GAA FET device300at various fabrication stages of the method200ofFIG.2. The GAA FET device300is similar to the GAA FET device100shown inFIG.1, but with certain features/structures/regions not shown, for the purposes of brevity. For example, the following figures of the GAA FET device300do not include source/drain structures (e.g.,110ofFIG.1). It should be understood the GAA FET device300may further include a number of other devices (not shown in the following figures) such as inductors, fuses, capacitors, coils, etc., while remaining within the scope of the present disclosure. Corresponding to operation202ofFIG.2,FIG.3is a cross-sectional view of the GAA FET device300including a semiconductor substrate302at one of the various stages of fabrication. The cross-sectional view ofFIG.3is cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). The substrate302may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate302may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate302may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Corresponding to operation204ofFIG.2,FIG.4Ais a cross-sectional view of the GAA FET device300including a number of first semiconductor layers410and a number of second semiconductor layers420formed on the substrate302at one of the various stages of fabrication. Still corresponding to operation204ofFIG.2,FIG.4Bis a cross-sectional view of the GAA FET device300including a different number of the first semiconductor layers410and the same number of second semiconductor layers420formed on the substrate302at one of the various stages of fabrication. The cross-sectional views ofFIGS.4A-Bare each cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). Referring first toFIG.4A, the first semiconductor layers410and the second semiconductor layers420are alternatingly disposed on top of one another (e.g., along the Z direction) to form a first stack. For example, one of the second semiconductor layers420is disposed over one of the first semiconductor layers410then another one of the first semiconductor layers420is disposed over the second semiconductor layer410, so on and so forth. Similarly, inFIG.4B, the first semiconductor layers410and the second semiconductor layers420are alternatingly disposed on top of one another (e.g., along a vertical direction) to form a second stack. The first and second stacks may include any number of alternately disposed first and second semiconductor layers410and420, respectively. For example inFIG.4A, the first stack includes 4 first semiconductor layers410, with 3 second semiconductor layers420alternatingly disposed therebetween and with one of the first semiconductor layers410being the topmost semiconductor layer. For example inFIG.4B, the second stack includes 3 first semiconductor layers410, with 2 second semiconductor layers420alternatingly disposed therebetween and with one of the second semiconductor layer420being the topmost semiconductor layer. It should be understood that the GAA FET device300can include any number of first semiconductor layers and any number of second semiconductor layers, with either one of the first or second semiconductor layers being the topmost semiconductor layer, while remaining within the scope of the present disclosure. Thus, in most of the following discussion, the stack shown inFIG.4Awill be used as a representative example. The semiconductor layers410and420may have respective different thicknesses. Further, the first semiconductor layers410may have different thicknesses from one layer to another layer. The second semiconductor layers420may have different thicknesses from one layer to another layer. The thickness of each of the semiconductor layers410and420may range from few nanometers to few tens of nanometers. The first layer of the stack may be thicker than other semiconductor layers410and420. In an embodiment, each of the first semiconductor layers410has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each of the second semiconductor layers420has a thickness ranging from about 5 nm to about 20 nm. The two semiconductor layers410and420have different compositions. In various embodiments, the two semiconductor layers410and420have compositions that provide for different oxidation rates and/or different etch selectivity between the layers. In an embodiment, the first semiconductor layers410include silicon germanium (Si1-xGex), and the second semiconductor layers include silicon (Si). In an embodiment, each of the semiconductor layers420is silicon that may be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed when forming the layers420(e.g., of silicon). In various embodiments, the semiconductor layers420may be intentionally doped. For example, when the GAA FET device300is configured in n-type (and operates in an enhancement mode), each of the semiconductor layers420may be silicon that is doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the GAA FET device300is configured in p-type (and operates in an enhancement mode), each of the semiconductor layers420may be silicon that is doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In another example, when the GAA FET device300is configured in n-type (and operates in a depletion mode), each of the semiconductor layers420may be silicon that is doped with an n-type dopant instead; and when the GAA FET device300is configured in p-type (and operates in a depletion mode), each of the semiconductor layers420may be silicon that is doped with a p-type dopant instead. In some embodiments, each of the semiconductor layers410is Si1-xGexthat includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the semiconductor layers410of Si1-xGexin molar ratio. Furthermore, the first semiconductor layers410may include different compositions among them, and the second semiconductor layers420may include different compositions among them. Either of the semiconductor layers410and420may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. The materials of the semiconductor layers410and420may be chosen based on providing differing oxidation rates and/or etch selectivity. The semiconductor layers410and420can be epitaxially grown from the semiconductor substrate302. For example, each of the semiconductor layers410and420may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate302extends upwardly, resulting in the semiconductor layers410and420having the same crystal orientation with the semiconductor substrate302. Upon growing the semiconductor layers410and420on the semiconductor substrate302(as a stack), the stack may be patterned to form one or more fin structures (e.g.,401). Each of the fin structures is elongated along a lateral direction (e.g., the Y direction), and includes a stack of patterned semiconductor layers410-420interleaved with each other. The fin structure401is formed by patterning the semiconductor layers410-420and the semiconductor substrate302using, for example, photolithography and etching techniques. For example, a mask layer (which can include multiple layers such as, for example, a pad oxide layer and an overlying pad nitride layer) is formed over the topmost semiconductor layer (e.g.,410inFIG.4A, or420inFIG.4B). The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may act as an adhesion layer between the topmost semiconductor layer410(or the semiconductor layer420in some other embodiments) and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The pad nitride layer may be formed using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example. The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer and pad nitride layer to form a patterned mask. The patterned mask can be subsequently used to pattern exposed portions of the semiconductor layers410-420and the substrate302to form trenches (or openings), thereby defining the fin structures401between adjacent trenches. When multiple fin structures are formed, such a trench may be disposed between any adjacent ones of the fin structures. In some embodiments, the fin structure401is formed by etching trenches in the semiconductor layers410-420and substrate302using, for example, reactive ion etch (ME), neutral beam etch (NBE), the like, or combinations thereof. The etch may be anisotropic. In some embodiments, the trenches may be strips (when viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches may be continuous and surround the fin structure401. Corresponding to operation206ofFIG.2,FIG.5Ais a cross-sectional view of the GAA FET device300including one or more isolation structures502, at one of the various stages of fabrication. The cross-sectional view ofFIG.5Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). Also corresponding to the same operation206,FIGS.5B and5Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. The isolation structure502, which can includes multiple portions, may be formed between adjacent fin structures, or next to a single fin structure. The isolation structure502, which are formed of an insulation material, can electrically isolate neighboring fin structures from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In an example, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CAR′) process, may remove any excess insulation material and form a top surface of the insulation material and a top surface of a patterned mask (not shown) defining the fin structure401. The patterned mask may also be removed by the planarization process, in various embodiments. Next, the insulation material is recessed to form the isolation structure502, as shown inFIG.5A, which is sometimes referred to as a shallow trench isolation (STI). The isolation structure502is recessed such that the fin structure401protrudes from between neighboring portions of the isolation structure502. The top surface of the isolation structures (STIs)502may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surface of the isolation structure502may be formed flat, convex, and/or concave by an appropriate etch. The isolation structure502may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation structure502. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation structure502. As mentioned above, each of the first semiconductor layers410and second semiconductor layer420of the fin structure401is elongated along a lateral direction (e.g., the Y direction). For example inFIG.5B, the second semiconductor layer420extends along the Y direction, with portions of the isolation structure502disposed next to the sides of the second semiconductor layer420along the X direction. For example inFIG.5C, the first semiconductor layer410extends along the Y direction, with portions of the isolation structure502disposed next to the sides of the first semiconductor layer410along the X direction. Corresponding to operation208ofFIG.2,FIG.6Ais a cross-sectional view of the GAA FET device300including a connected layer602, at one of the various stages of fabrication. The cross-sectional view ofFIG.6Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). Also corresponding to the same operation208,FIGS.6B and6Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. As shown inFIG.6A, the connected layer602may be (e.g., conformally) formed to overlay the fin structure401and the isolation structure502. For example, the connected layer602overlays a top surface of the fin structure401and extends along sidewalls of the fin structure401, and further extends along the X direction, for example, to overlay the top surface of the isolation structure502. As such, the connected layer602extends along sidewalls of each of the first semiconductor layers410and each of the second semiconductor layers420(that extend along the Y direction), as illustrated inFIGS.6B and6C. In some embodiments, the connected layer602may be formed with a relatively thin thickness (e.g., from about 2 angstroms (Å) to about 50 (Å)) to smooth the surfaces of the fin structure401, which may be constituted by multiple different materials. As such, a structure (e.g., a dummy gate structure, and a corresponding active gate structure) overlaying the fin structure401can be in better contact with the surfaces of the fin structure401, which can significantly limit the odds of forming voids along the surfaces of the fin structure401. Further, in some embodiments, the connected layer602may include one or more materials that have a certain etching selectivity with respect to the materials of the first and second semiconductor layers,410and420, and the lower portion of a dummy gate structure. Accordingly, in one or more subsequent fabrication stages (e.g., etching portions of the first semiconductor layers and/or the dummy gate structure to form inner spacers), the first semiconductor layers and the dummy gate structure may each present a curvature-based profile, which will be discussed in further detail below. In some embodiments, the connected layer602may be formed by treating the fin structure401having the first and second semiconductor layers410and420. The treatment can include oxidizing, nitridizing, and/or sulfurizing the fin structure401. As such, the connected layer602may include one or more treated materials of the first and second semiconductor layers410and420. In an example where the first semiconductor layers410include SiGe and the second semiconductor layers420include Si, the connected layer602may include at least one of SiGeO or SiO (e.g., through an oxidizing treatment). In the same example, the connected layer602may include at least one of SiGeN or SiN (e.g., through a nitridizing treatment). Continuing with the same example, the connected layer602may include at least one of SiGeS or SiS (e.g., through a sulfurizing treatment). For example, the connected layer602may be formed by performing an in-situ or ex-situ plasma process on the fin structure401. In such a plasma process, passivation gases, such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof, can be used. Moreover, the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof to reach a certain condition. As a non-limiting example, a source power of 10 watts to 3000 watts, a bias power of 0 watts to 3000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 standard cubic centimeters per minute to 5000 standard cubic centimeters per minute may be used in the plasma process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges can also be contemplated. In another example, the connected layer602may be formed by performing an ex-situ chemical/wet process on the fin structure401. In such a chemical/wet process, passivation gases, such as ozone (O3), carbon dioxide (CO2), and other suitable passivation gases and combinations thereof, can be used, with assistive etch chemicals, such as sulfuric acid (H2SO4), ammonia (NH3), and other suitable assistive etch chemicals and combinations thereof as well as solvents such as deionized water, alcohol, acetone, and other suitable solvents and combinations thereof. In some other embodiments, the connected layer602may be formed by depositing a material over the fin structure401. In such a case, the connected layer602may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or combinations thereof. The deposition can include CVD, PECVD, ALD, FCVD, or combinations thereof. Corresponding to operation210ofFIG.2,FIG.7Ais a cross-sectional view of the GAA FET device300including a dummy gate structure702, at one of the various stages of fabrication. The cross-sectional view ofFIG.7Ais cut in a direction perpendicular to the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). Also corresponding to the same operation210,FIGS.7B and7Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. Next, the dummy gate structure702is formed over the fin structure401and the isolation structure502, with the connected layer602disposed therebetween. The dummy gate structure702can extend along a lateral direction (e.g., the X direction) perpendicular to the lateral direction along which the fin structure401extends. The dummy gate structure702may be placed where an active (e.g., metal) gate structure is later formed, in various embodiments. In some embodiments, the dummy gate structure702is placed over a portion of fin structure401, with the connected layer602sandwiched therebetween. Such an overlaid portion of the fin structure401is later formed as a conduction channel, which includes portions of the second semiconductor layers420and portions of the first semiconductor layers410that are each replaced with an active gate structure. As such, the active gate structure can wrap around each of the portions of the second semiconductor layers420, which will be discussed in further detail below. In some embodiments, the dummy gate structure702can include one or more Si-based or SiGe-based materials that are similar (or having similar etching rates) as the first semiconductor layers410such as, for example, SiGe. The dummy gate structure702may be deposited by CVD, PECVD, ALD, FCVD, or combinations thereof. Although the dummy gate structure702is shown as being formed as a single-piece in the illustrated embodiment ofFIG.7A, it should be understood that the dummy gate structure702can be formed to have multiple portions, each of which may include respective different materials. For example, the dummy gate structure702may include a lower portion that extends from the isolation structure502to around a top surface of the connected layer602, and an upper portion that further extends from the lower portion. In such embodiments, the lower portion of the dummy gate structure702can include the above-mentioned material that has a similar etching rate as the first semiconductor layers410(e.g., SiGe), and the upper portion of the dummy gate structure702can include a material that has a certain etching selectivity with respect to the fin structure401or is unfavorable to epitaxially grow source/drain structures. Corresponding to operation212ofFIG.2,FIG.8is a cross-sectional view of the GAA FET device300in which portions of the fin structure401that are not overlaid by the dummy gate structure702are removed, at one of the various stages of fabrication. The cross-sectional view ofFIG.8is cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG.1). The dummy gate structure702can serve as a mask to etch the non-overlaid portions of the fin structure401, which results in the fin structure401having one or more alternatingly stacks including remaining portions of the semiconductor layers410and420. As a result, along the Z direction, newly formed sidewalls of each of the fin structures401are aligned with sidewalls of the dummy gate structure702. For example inFIG.8, semiconductor layers810and820are the remaining portions of the semiconductor layers410and420overlaid by the dummy gate structure702, respectively. In some embodiments, the semiconductor layers810and820may sometimes be referred to as nanostructures (e.g., nanosheets)810and820, respectively. Corresponding to operation214ofFIG.2,FIG.9Ais a cross-sectional view of the GAA FET device300in which end portions of the nanostructures810(along the Y direction) are etched, at one of the various stages of fabrication. The cross-sectional view ofFIG.9Ais cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG.1). Also corresponding to the same operation214,FIGS.9B and9Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. As shown inFIG.9A, respective end portions of each of the nanostructures810are removed. The end portions of the nanostructures810can be removed (e.g., etched) using a “pull-back” process to pull the nanostructures810back by a pull-back distance. In an example where the semiconductor layers820include Si, and the semiconductor layers810include SiGe, the pull-back process may include a hydrogen chloride (HCl) gas isotropic etch process, which etches SiGe without attacking Si. As such, the Si layers (nanostructures)820may remain intact during this process. Consequently, recess901can be formed. Further, in various embodiments, the material of the nanostructures810(and the material of at least the lower portion of the dummy gate structure702) have a certain etching selectivity with respect to the connected layer602. For example, the pull-back process may etch the nanostructures810(and at least the lower portion of the dummy gate structure702) more quickly than the connected layer602, which can cause the recess901to present one or more curvature-based profiles at its ends. In various embodiments, the difference of etching rates between the nanostructures810(and the dummy gate structure702) and the connected layer602may be adjusted by varying the molar ratio of Ge in the nanostructures810, when first growing the semiconductor layers410. For example inFIG.9B, the nanostructure820may remain intact, while end portions of the dummy gate structure702(along the Y direction) and end portions of the connected layer602(along the Y direction) are etched. Further, as the dummy gate structure702is etched faster than the connected layer602, the recess901can present a first curvature-based profile903(e.g., at each end of a remaining portion of the dummy gate structure702that is about coplanar with one of the nanostructures820). The first curvature-based profile903may include a single arc that inwardly curves toward the remaining dummy gate structure702. As such, the profile903and the sidewall of the nanostructure820(or the connected layer602) extending along the Y direction may form an angle, θ1. In some embodiments, the angle θ1is less than 90 degrees. For example inFIG.9C, different from the nanostructure820, the nanostructures810may be concurrently etched, while etching the end portions of the dummy gate structure702(along the Y direction) and the end portions of the connected layer602(along the Y direction). Further, as the dummy gate structure702and nanostructure820are etched faster than the connected layer602, the recess901can present a second curvature-based profile905(e.g., at each end of respective remaining portions of the dummy gate structure702and one of the nanostructures810that are about coplanar with such nanostructure810). The second curvature-based profile905may include multiple arcs that each inwardly curve toward either the remaining dummy gate structure702or the remaining nanostructure810. As such, each arc of the profile905and the sidewall of the nanostructure810(or the connected layer602) extending along the Y direction may form two angles, θ2and θ3. In some embodiments, the angles θ2and θ3are each less than 90 degrees. FIG.9Dillustrates another embodiment to form the recess901, in which the connected layer602may remain substantially intact during the pull-back process. As such, the connected layer602may wholly extend the sidewalls of the nanostructure820, when compared to the embodiment ofFIG.9Bwhere the connected layer602may partially extend the sidewalls of the nanostructure820.FIG.9Eillustrates yet another embodiment to form the recess901, in which the connected layer602may be etched during the pull-back process but in a slower etching rate, when compared to the embodiment ofFIG.9B. For example inFIG.9E, only end portions of the connected layer602(along the Y direction) are partially etched, which causes the connected layer602to present a tapered profile. Specifically, the tapered profile may have a varying thickness, at the portion not exposed by the remaining dummy gate structure702. The thickness can gradually decrease from the portion of the connected layer602at around the end of the remaining dummy gate structure702toward the end of the connected layer602. Corresponding to operation216ofFIG.2,FIG.10Ais a cross-sectional view of the GAA FET device300including an inner spacer1002, at one of the various stages of fabrication. The cross-sectional view ofFIG.10Ais cut in the lengthwise direction of a fin structure of the GAA FET device300(e.g., cross-section D-D indicated inFIG.1). Also corresponding to the same operation216,FIGS.10B and10Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. The inner spacer1002is formed along respective etched ends of the nanostructures810. Thus, the inner spacer1002(e.g., their respective inner sidewalls) may follow the curvature-based profile (e.g.,903,905) of the recess901. For example inFIG.10Bwhere the inner spacer1002follows the curvature-based profile903shown inFIG.9B, a first group of the inner spacer1002can present a first curvature-based profile1003that is similar to the profile903. Each of the first group of the inner spacer1002may be laterally aligned with a corresponding one of the nanostructures820. For example inFIG.10Cwhere the inner spacer1002follows the curvature-based profile905shown inFIG.9C, a second group of the inner spacer1002can present a second curvature-based profile1005that is similar to the profile905. Each of the second group of the inner spacer1002may be laterally aligned with a corresponding one of the nanostructures810. In some embodiments, the inner spacer1002can be formed conformally by chemical vapor deposition (CVD), or by monolayer doping (MLD) of nitride followed by spacer ME. The inner spacer1002can be deposited using, e.g., a conformal deposition process and subsequent isotropic or anisotropic etch back to remove excess spacer material on the sidewalls of the stacks of the fin structure401and on a surface of the semiconductor substrate302. The inner spacer1002can be formed of silicon nitride, silicoboron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5) appropriate to the role of forming an insulating gate sidewall spacers of transistors. FIGS.10D and10Eillustrate other embodiments of the profile of the inner spacer1002. As shown inFIG.10D, the inner spacer1002follows the profile of the recess901, as shown inFIG.9D. As such, the inner spacer1002may be separated from the nanostructure820with the intact connected layer602. As shown inFIG.10E, the inner spacer1002follows the profile of the recess901, as shown inFIG.9E. As such, the inner spacer1002may be separated from the nanostructure820with the tapered connected layer602. Although the sidewalls of the nanostructure820are not exposed by the tapered connected layer602in the illustrated embodiment ofFIG.10E, it should be understood that portions (e.g., one or more end portions) of the sidewalls of the nanostructure820may be in direct contact with the inner spacer1002, while remaining within the scope of the present disclosure. Corresponding to operation218ofFIG.2,FIG.11Ais a cross-sectional view of the GAA FET device300including an active gate structure1100, at one of the various stages of fabrication. The cross-sectional view ofFIG.11Ais cut in the lengthwise direction of an active/dummy gate structure of the GAA FET device300(e.g., cross-section A-A indicated inFIG.1). Also corresponding to the same operation218,FIGS.11B and10Cdepict cross-sectional views of the GAA FET device300, which are cut along cross-section B-B and cross-section C-C (as indicated inFIG.1), respectively. Subsequently to forming source/drain structures on the sides of the fin structure401(along the Y direction) and an ILD overlaying the source/drain structures, both of which are not shown for purposes of clarity of illustration, the dummy gate structure702(or at least its lower portion that is formed of the similar material as the nanostructures810), the nanostructures810, and selectively at least a portion of the connected layer602may be concurrently removed. In various embodiments, the dummy gate structure702(or at least its lower portion) and the nanostructures810can be removed by applying a selective etch (e.g., a hydrochloric acid (HCl)), while leaving the nanostructures820substantially intact. After the removal of the dummy gate structure702, a gate trench, exposing respective sidewalls of each of the nanostructures820that face the X direction, may be formed. After the removal of the nanostructures810to further extend the gate trench, respective bottom surface and/or top surface of each of the nanostructures820may be exposed. Consequently, a full circumference of each of the nanostructures820can be exposed. Next, the active gate structure1100is formed to wrap around each of the nanostructures820. The active gate structure1100is formed in the extended gate trench by filling with at least a gate dielectric and a gate metal. Thus, the active gate structure1100can inherit the dimensions and profiles of the gate trench, which are defined by the formed inner spacer1002, the removed dummy gate structure702, the removed nanostructures810, and selectively the removed portion of the connected layer602.FIG.11Billustrates an embodiment where the connected layer602is wholly removed, after removing the dummy gate structure702shown inFIG.10B. As such, each of a number of first gate sections of the active gate structure1100can present a first curvature-based profile1103at its respective ends that extend along the X direction. Each of the first gate sections is laterally aligned with a corresponding one of the nanostructures820. The first curvature-based profile1103can follow the profile1003of the inner spacer1002and further extends toward the nanostructure820through the wholly removed connected layer602. On the other hand, the connected layer602may not remain along the nanostructures810. For example inFIG.11C, each of a number of second gate sections of the active gate structure1100can present a second curvature-based profile1105at its respective ends that extend along the X direction. Each of the second gate sections is laterally aligned with a corresponding one of the removed nanostructures810. The second curvature-based profile1105can follow the profile1005of the inner spacer1002. In various embodiments, the active gate structure1100and the inner spacer1002may be characterized with one or more critical dimensions (CDs). For example inFIG.11B, the active gate structure1100can be characterized with CD4and CD5, which correspond to lengths of the sidewalls of the active gate structure1100extending along the Y direction, respectively; and the inner spacer1002can be characterized with CDdand CDe, which correspond to lengths of the sidewalls of the inner spacer1002extending along the Y direction, respectively. The sidewalls of the active gate structure1100, having CD4and CD5, respectively, are connected to each other through the inwardly curved arc (e.g., profile1103). Accordingly, CD4is greater than CD5. In a non-limiting example, CD4and CD5may each range from about 2 nanometers (nm) to about 300 nm. The sidewalls of the inner spacer1002, having CDdand CDe, respectively, are connected to each other through the inwardly curved arc (e.g., profile1103). Accordingly, CDdis greater than CDe. In a non-limiting example, CDdand CDemay each range from about 0.3 nanometers (nm) to about 15 nm. Further, the profile1103can inherit the profile903(FIG.9B), and thus, the angle θ1present between the sidewall of the nanostructure820extending along the Y direction and the profile1103can be reserved. In some embodiments, the angle θ1is less than 90 degrees. For example, the angle θ1may range from about 30 degrees to about 88 degrees. For example inFIG.11C, the active gate structure1100can be characterized with CD1, CD2, and CD3, which correspond to lengths of different portions of the active gate structure1100extending along the Y direction, respectively; and the inner spacer1002can be characterized with CDa, CDb, and CDc, which correspond to different portions of the inner spacer1002extending along the Y direction, respectively. The portion of the active gate structure1100, having CD1, may be located between respective middle points of the middle arcs on its opposite sides; the portion of the active gate structure1100, having CD2, may be located between junctions of the adjacent arcs on its opposite sides; and the portion of the active gate structure1100, having CD3, may be located between respective end points of the side arcs. In some embodiments, CD2is greater than CD1and CD3is greater than CD1. In a non-limiting example, CD1, CD2and CD3may each range from about 2 nanometers (nm) to about 300 nm. The portion of the active gate structure1100, having CD1, may be located between respective middle points of the middle arcs on its opposite sides; the portion of the active gate structure1100, having CD2, may be located between junctions of the adjacent arcs on its opposite sides; and the portion of the active gate structure1100, having CD3, may be located between respective end points of the side arcs. In some embodiments, CD2is greater than CD1and CD3is greater than CD1. In a non-limiting example, CD1, CD2, and CD3may each range from about 2 nanometers (nm) to about 300 nm. The portion of the inner spacer1002, having CDc, may be extended from the middle point of the middle arc; the portion of the inner spacer1002, having CDb, may be extended from the junction of the adjacent arcs; and the portion of the inner spacer1002, having CDa, may be extended from the end point of the side arc. In some embodiments, CDais greater than CDband CDcis greater than CDb. In a non-limiting example, CDa, CDb, and CDcmay each range from about 0.3 nanometers (nm) to about 15 nm. Further, the profile1105can inherit the profile905(FIG.9C), and thus, the angles θ2and θ3can be reserved. In some embodiments, the angles θ2and θ3are each less than 90 degrees. For example, the angles θ2and θ3may each range from about 30 degrees to about 88 degrees. The active gate structure1100includes a gate dielectric and a gate metal, in some embodiments. The gate dielectric can wrap around each of the nanostructures820, e.g., the top and bottom surfaces and sidewalls facing the X direction). The gate dielectric may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may include a stack of multiple high-k dielectric materials. The gate dielectric can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the gate dielectric may optionally include a substantially thin oxide (e.g., SiOx) layer, which may be a native oxide layer formed on the surface of each of the nanostructures820. The gate metal can wrap around each of the nanostructures820with the gate dielectric disposed therebetween. Specifically, the gate metal can include a number of gate metal sections abutted to each other along the Z direction. Each of the gate metal sections can extend not only along a horizontal plane (e.g., the plane expanded by the X direction and the Y direction), but also along a vertical direction (e.g., the Z direction). As such, two adjacent ones of the gate metal sections can adjoin together to wrap around a corresponding one of the nanostructures820, with the gate dielectric disposed therebetween. The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process. FIGS.11D-Killustrate various other embodiments where the connected layer602is partially removed from or remains substantially intact along the sidewalls of the nanostructures820, after forming the active gate structure1100. For example inFIG.11D, the whole remaining portion of the connected layer602that is not exposed by the remaining dummy gate structure702(when forming the recess901inFIG.9B), may remain. InFIG.11E, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and the active gate structure1100, and the tapered portions on the same side of the nanostructure820are tapered toward each other. InFIG.11F, one or more non-tapered portions of the connected layer602may remain. Specifically, each of such non-tapered portions is disposed between the nanostructure820and the inner spacer1002. InFIG.11G, the whole connected layer602may remain. InFIG.11H, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and combination of a portion of the active gate structure1100and the inner spacer1002. The tapered portions on the same side of the nanostructure820are tapered toward each other. InFIG.11I, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and the inner spacer1002, and the tapered portions on the same side of the nanostructure820are tapered away from each other. InFIG.11J, the whole connected layer602may remain. Different form the embodiment ofFIG.11G, the connected layer602may present a tapered profile toward its both ends. InFIG.11K, one or more tapered portions of the connected layer602may remain. Specifically, each of such tapered portions is disposed between the nanostructure820and combination of a portion of the active gate structure1100and the inner spacer1002. Each of the tapered portions has its ends tapered away from each other. In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile. In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction. The gate structure comprises a plurality of first gate sections and a plurality of second gate sections. The plurality of first gate sections are laterally aligned with the plurality of semiconductor layers, respectively. The plurality of second gate sections are each vertically disposed between adjacent ones of the plurality of semiconductor layers. The semiconductor device includes an inner spacer comprising a first group and a second group. Each of the first group of the inner spacer contacts an end of a corresponding one of the plurality of first gate sections in a first curvature-based profile, and each of the second group of the inner spacer contacts an end of a corresponding one of the plurality of second gate sections in a second curvature-based profile. In yet another aspect of the present disclosure, a method for fabricating a semiconductor device is disclosed. The method includes forming a fin structure extending along a first lateral direction. The fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another. The method includes forming a connected layer overlaying the fin structure. The method includes forming a dummy gate structure over a portion of the fin structure with the connected layer disposed between the dummy gate structure and the fin structure. The dummy gate structure extends along a second lateral direction perpendicular to the first lateral direction. The method includes removing portions of the fin structure that are not overlaid by the dummy gate structure. The method includes etching, along the first lateral direction, respective end portions of each of the first semiconductor layers, respective end portions of at least lower portions of the dummy gate structure, and end portions of the connected layer. A respective remaining portion of each of the first semiconductor layers and a respective remaining portion of each of the lower portions of the dummy gate structure each present a curvature-based profile. The method includes forming inner spacers that fill the etched end portions of the first semiconductor layers and the etched end portions of the dummy gate structure. The method includes replacing respective remaining portions of the first semiconductor layers and the dummy gate structure with an active gate structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 55,672 |
11942530 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein. In the present disclosure, a source/drain refers to a source and/or a drain. A source and a drain are interchangeably used. The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. An integrated circuit (IC) typically includes a plurality of semiconductor devices, such as field-effect transistors and metal interconnection layers formed on a semiconductor substrate. The interconnection layers, designed to connect the semiconductor devices to power supplies, input/output signals, and to each other, may include signal lines and power rails, such as a positive voltage rail (VDD) and a ground rail (GND). As semiconductor device size shrinks, space for metal power rails and signal lines decreases. Embodiments of the present disclosure provide semiconductor devices having metal contacts for connecting to power rails formed on a backside of a substrate, and methods for fabricating such semiconductor devices. When the power rails are formed on the backside of the substrate, metal layers in the back end of line (BEOL) may be manufactured using reduced number of masks with improved performance, width of gates in field-effector transistors (FETs) can be enlarged, and width of power rails can also be increased. Metal contacts on the backside and the backside power rail are formed by backside processes which are performed after completing BEOL processes and flipping the substrate over. As a result, backside processes are performed within the conditions to maintain integrities of the BEOL structures. For example, it is challenging to form a silicide layer between an active semiconductor region, such as a source/drain region, and a backside metal contact. Embodiments of the present disclosure provide a semiconductor device having a conductive feature, which is formed during backside processes and connects with a source/drain feature through a silicide layer formed on the front side of the substrate. FIGS.1-28Cillustrate various stages of manufacturing a nanosheet FET device according to one embodiment of the present disclosure. Additional operations can be provided before, during, and after processes shown byFIGS.1-28C, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. InFIG.1, a substrate10is provided to form a semiconductor device thereon. The substrate10may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate10may include various doping configurations depending on circuit design. For example, different doping profiles, e.g., n-wells, p-wells, may be formed in the substrate10in regions designed for different device types, such as n-type field effect transistors (NFET), and p-type field effect transistors (PFET). In some embodiments, the substrate10may be a silicon-on-insulator (SOI) substrate including an insulator structure12for enhancement. The substrate10has a front surface10fand a back surface10b. A buffer layer14is formed over a region on the front surface10fof the substrate10. The buffer layer14functions to gradually change the lattice constant from that of the substrate10to that of source/drain regions to be formed over the substrate10. The buffer layer14may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, SiGe, SiGe, SiGeB, SiP, SiAs, or other Si related material. In some embodiments, the buffer layer14has a thickness between about 5 nm and about 50 nm. A semiconductor stack20is formed over the buffer layer14. The semiconductor stack20includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate device, such as nanosheet channel FETs. In some embodiments, the semiconductor stack20includes first semiconductor layers22interposed by second semiconductor layers24. The first semiconductor layers22and second semiconductor layers24have different oxidation rates and/or etch selectivity. In later fabrication stages, portions of the semiconductor layers24form nanosheet channels in a multi-gate device. Three first semiconductor layers22and three second semiconductor layers24are alternately arranged as illustrated inFIG.1as an example. More or less semiconductor layers22and24may be included in the semiconductor stack20depending on the desired number of channels in the semiconductor device to be formed. In some embodiments, the number of semiconductor layers24is between 1 and 10. The semiconductor layers22,24may be formed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the semiconductor layers24include the same material as the substrate10. In some embodiments, the semiconductor layers22and24include different materials than the substrate10. In some embodiments, the semiconductor layers22and24are made of materials having different lattice constants. In some embodiments, the first semiconductor layers22include an epitaxially grown silicon germanium (SiGe) layer and the second semiconductor layers24include an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the semiconductor layers22and24may include other materials such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GalnAsP, or combinations thereof. In some embodiments, each second semiconductor layer24has a thickness in a range between about 5 nm and about 30 nm. In other embodiments, each second semiconductor layer24has a thickness in a range between about 10 nm and about 20 nm. In some embodiments, each second semiconductor layer24has a thickness in a range between about 6 nm and about 12 nm. In some embodiments, the second semiconductor layers24in the semiconductor stack20are uniform in thickness. The first semiconductor layers22in channel regions may eventually be removed and serve to define a vertical distance between adjacent channel regions for a subsequently formed multi-gate device. In some embodiments, the thickness of the first semiconductor layer22is equal to or greater than the thickness of the second semiconductor layer24. In some embodiments, each semiconductor layer22has a thickness in a range between about 5 nm and about 50 nm. In other embodiments, each first semiconductor layer22has a thickness in a range between about 10 nm and about 30 nm. InFIG.2, semiconductor fins30are formed from the semiconductor stack20, the buffer layer14, and a portion of the substrate10. The semiconductor fins30may be formed by patterning a hard mask (not shown) formed on the semiconductor stack20and one or more etching processes. Each semiconductor fin30has an upper portion including the semiconductor layers22,24and a well portion32formed from the substrate10. InFIG.2, the semiconductor fins30are formed along the X direction. A width W1of the semiconductor fins30along the Y direction is in a range between about 10 nm and about 40 nm. In some embodiments, the width W1of the semiconductor fins30along the Y direction is in a range between about 20 nm and about 30 nm. InFIG.3, an isolation layer36is formed over the substrate10and hybrid fins34are formed in the isolation layer36between neighboring semiconductor fins30. The isolation layer36may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or other suitable deposition process. In some embodiments, the isolation layer36is formed conformally to cover the semiconductor fins30by a suitable deposition process, such as atomic layer deposition (ALD). In some embodiments, the isolation layer36may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof. In some embodiments, the conformal deposition of the isolation layer36results in trenches formed in the isolation layer36between neighboring semiconductor fins30. The trenches are subsequently filled with one or more dielectric layers to form the hybrid fins34therein. After the formation of the hybrid fins34, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove the excessive isolation layer36and hybrid fins34until the semiconductor fins30are exposed. In some embodiments, the hybrid fins34, also referred to as dummy fins or dielectric fins, include a high-k dielectric material layer, a low-k dielectric material layer, or a bi-layer dielectric material including high-k upper part and a low-k lower part. In some embodiments, the hybrid fins34include a high-k metal oxide, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, and the like, a low-k material such as SiONC, SiCN, SiOC, or other dielectric material. In some embodiments, a width W2of the hybrid fins34along the Y direction is in a range from about 3 nm to about 50 nm. In some embodiments, the hybrid fins34may extend to the level of the buffer layer14. For example, the bottom of the hybrid fin34may be at a height H1below the top of the buffer layer14along the Z direction. In some embodiments, the height H1is in a range between about 5 nm and 8 nm. InFIG.4, the isolation layer36is recess etched using a suitable anisotropic etching process to expose the semiconductor fins30and the hybrid fins34. In some embodiments, the isolation layer36is etched to expose at least a portion of the buffer layer14in the semiconductor fins30. InFIGS.5A-5DtoFIGS.18A-18D,FIGS.5B-18Bare cross sectional views corresponding to line Y1-Y1inFIG.5A.FIGS.5C-18Care cross sectional views corresponding to line Y2-Y2inFIG.5A.FIGS.5D-18Dare across sectional views corresponding to line X-X inFIG.5A. InFIGS.5A-5D, sacrificial gate structures40are formed over the semiconductor fins30and the hybrid fins34. Sidewall spacers50are subsequently formed on sidewalls of each sacrificial gate structure40. The sacrificial gate structure40is formed over a portion of the semiconductor fin30which is to be a channel region. The sacrificial gate structure40may include a sacrificial gate dielectric layer42, a sacrificial gate electrode layer44, a pad layer46, and a mask layer48. The sacrificial gate dielectric layer42is formed by a blanket deposition over the semiconductor fins30and the hybrid fins34. The sacrificial gate dielectric layer42includes one or more layers of insulating material, such as a silicon oxide-based material. In some embodiments, silicon oxide formed by CVD is used. In some embodiments, the sacrificial gate dielectric layer42has a thickness in a range between about 1 nm and about 5 nm. The sacrificial gate electrode layer44is then blanket deposited on the sacrificial gate dielectric layer42and over the semiconductor fins30and the hybrid fins34, such that the fin structures are fully embedded in the sacrificial gate electrode layer44. The sacrificial gate electrode layer44includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range between about 100 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer44is subjected to a planarization operation. The sacrificial gate electrode layer44may be deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, the pad layer46and the mask layer48are formed over the sacrificial gate electrode layer44. The pad layer46may include silicon nitride. The mask layer48may include silicon oxide. Next, a patterning operation is performed on the mask layer48, the pad layer46, the sacrificial gate electrode layer44, and the sacrificial gate dielectric layer42to form the sacrificial gate structure40. After the sacrificial gate structure40is formed, the sidewall spacers50are formed by a blanket deposition of an insulating material followed by anisotropic etch to remove insulating material from horizontal surfaces. The sidewall spacers50may have a thickness in a range between about 2 nm and about 10 nm. In some embodiments, the insulating material of the sidewall spacers50is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof. InFIGS.6A-6D, the semiconductor fins30on opposite sides of the sacrificial gate structure40are recess etched, forming source/drain spaces52and54between the neighboring hybrid fins34on either side of the sacrificial gate structure40. The first semiconductor layers22and the second semiconductor layers24in the semiconductor fins30are etched down on both sides of the sacrificial gate structure40using one or more lithography and etching operations. In some embodiments, all layers in the semiconductor stack20of the semiconductor fins30are etched to expose the well portion32of the semiconductor fin30. In some embodiments, suitable dry etching and/or wet etching may be used to remove the first semiconductor layers22, the second semiconductor layer24, and the buffer layer14, together or separately. As shown inFIGS.6A and6B, the hybrid fins34separate neighboring source/drain spaces52on one side of the sacrificial gate structure40. Similarly, the hybrid fins34also separate neighboring source/drain spaces54on opposite side of the sacrificial gate structure40. InFIGS.7A-7D, the remaining portions of the semiconductor fins30corresponding to regions below the source/drain space52,54to be connected to a power rail therebelow are further etched to form alignment recesses58. A patterned protective layer56, such as a patterned stack including a photoresist layer and hard mask layer, may be used to expose areas where the alignment recesses58are to be formed and to protect areas where the alignment recesses58are not to be formed. Suitable dry etching and/or wet etching is used to remove at least part of the well portions32of the semiconductor fins30to form the alignment recesses58. Each alignment recess58has a height “H2”, which is a distance measured from the top of the buffer layer14to the bottom of the alignment recess58. In some embodiments, the height H2is in a range between about 10 nm and about 30 nm. InFIGS.8A-8D, backside contact alignment features60are formed in the alignment recesses58by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. In some embodiments, the backside contact alignment features60are formed by a selective deposition process. The backside contact alignment features60will be removed to form backside contact holes in the substrate10at a later stage. The backside contact alignment features60are formed from a material to have etch selectivity relative to the material of the substrate10, material in the well portions32of the semiconductor fins30and the insulating material in the isolation layer36. During backside process, the material in the backside contact alignment features60allows portions of the semiconductor fins30in the channel region and opposite source/drain region to be selectively removed from the backside contact alignment features60. Additionally, the backside contact alignment features60can be selectively removed without etching the dielectric materials in the isolation layers36. In some embodiments, the backside contact alignment features60may include SiGe, such as a single crystal SiGe material. In some embodiments, the backside contact alignment features60is formed from SiGe having a germanium composition percentage between about 50% and 95%. Alternatively, the backside contact alignment features60may include other materials such as Si, Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. After the formation of the backside contact alignment features60on one side of the sacrificial gate structure40, the patterned protective layer56formed on the other side of the sacrificial gate structure40is removed. InFIGS.9A-9D, inner spacers62are formed on exposed ends of the first semiconductor layers22under the sacrificial gate structure40. The first semiconductor layers22exposed to the source/drain spaces52,54are first etched horizontally along the X direction to form cavities. In some embodiments, the first semiconductor layers22can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. In some embodiments, the amount of etching of the first semiconductor layer22is in a range between about 2 nm and about 10 nm along the X direction. By selecting an appropriate crystal orientation of the first semiconductor layers22and an etchant, the cavity at the end of the first semiconductor layers22can have different shapes, such as a rectangular shape as shown inFIG.9Dor an open-triangle shape (not shown). After forming cavities in the first semiconductor layers22, the inner spacers62can be formed in the cavities by conformally deposit and then partially remove an insulating layer. The insulating layer can be formed by ALD or any other suitable method. In some embodiments, the insulating layer may include one of silicon nitride (SiN) and silicon oxide (SiO2) and have a thickness in a range from about 0.5 nm to about 3.0 nm. The subsequent etch process removes most of the insulating layer except inside the cavities, resulting in the inner spacers62. InFIGS.10A-10D, epitaxial source/drain features66are formed in the source/drain spaces52,54. In some embodiments, a preclean process may be performed prior to epitaxial growth of semiconductor material in the source/drain spaces52,54. As shown inFIG.10ft exposed areas of the isolation layers36may be recessed during the preclean process. Transitional epitaxial layer64may be first formed on the exposed surfaces, such as the exposed surfaces of the backside contact alignment features60in the source/drain spaces52and the exposed surfaces of the semiconductor fins30in the source/drain spaces54. The transitional epitaxial layer64function to provide a bridge of lattice structures between the existing semiconductor features, such as the backside contact alignment features60or the remaining portion of the semiconductor fins30, and the epitaxial source/drain features66to be formed. In some embodiments, the transitional epitaxial layer64is formed from Si, SiGe, SiGeB, SiP, SiAs, and other silicon related epitaxial materials. In some embodiments, material of the transitional epitaxial layer64is selected to have different etch and/or oxidation rate relative to the material of the substrate10, the material of the buffer layer14, and the backside contact alignment features60. In some embodiments, the transitional epitaxial layer64is formed from SiGeB when the backside contact alignment features60are formed from SiGe. According to embodiments of the present disclosure, the transitional epitaxial layer64is grown in a bar-shape having generally rectangular cross section along the Y1-Y1as shown inFIG.10Bso that gaps68are formed between the transitional epitaxial layer64and the hybrid fins34. In some embodiments, the transitional epitaxial layer64has a height H3along the Z direction in a range between about 5 nm and about 50 nm. The epitaxial source/drain features66are formed over the transitional epitaxial layer64within the source/drain spaces52,54. The epitaxial source/drain features66are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). The epitaxial source/drain features66may include one or more layers of Si, SiP, SiC and SiCP for NFET or Si, SiGe, Ge for a PFET. For the PFET, p-type dopants, such as boron (B), may also be included in the epitaxial source/drain features66. As shown inFIG.10D, the epitaxial source/drain features66are formed in contact with the second semiconductor layers24under the sacrificial gate structure40through transitional regions63. According to embodiments of the present disclosure, the epitaxial source/drain features66are formed in a bar-shape, having generally rectangular cross section along the Y1-Y1as shown inFIG.10B. The bar-shape can be achieved by selecting an appropriate crystal orientation for epitaxial growth. In some embodiments, the bar-shape is achieved by selecting the <110> crystal orientation for epitaxial growth. In the cross sectional view shown inFIG.10B, each epitaxial source/drain feature66has a top surface66t, a bottom surface66b, and two side surfaces66s. The bottom surface66bcontacts the transitional epitaxial layer64. Each side surface66sfaces a hybrid fin34. After the formation of the epitaxial source/drain features66, the gaps68between the epitaxial source/drain features66and the hybrid fins34are extended along the Z direction. In some embodiments, the epitaxial source/drain features66have a height H4along the Z direction in a range between about 10 nm and about 70 nm. The epitaxial source/drain features66have a width W3along the Y direction. The width W3can be smaller, larger and equal to the channel width W1, which is shown inFIG.2. The epitaxial source/drain features66have a length L1along the X direction. In some embodiments, the length L1is in a range between about 10 nm and about 50 nm. Each gap68may have a width W4along the Y direction in a range between about 1 nm and about 15 nm. As described below, each gap68is first filled with a dielectric material and then replaced with a conductive material. The width W4of the gap68is selected to enable formation and function of the conductive material. When the width W4is less than 1 nm, it would be difficult to form a continuous conductive material therein, and the resistance of the conductive material would be large and not suitable as a contact for the epitaxial source/drain features66, in some instances. When the width W4is greater than 15 nm, the size of the epitaxial source/drain features66would be reduced without significant additional advantages, in some instance. InFIGS.11A-11D, a gap fill dielectric layer70is formed over the substrate10. In some embodiments, the gap fill dielectric layer70is formed conformally to cover exposed surfaces on the substrate10by a suitable deposition process, such as atomic layer deposition (ALD). During deposition, as the thickness of the gap fill dielectric layer70increases, material deposited on the side surfaces66sof the epitaxial source/drain feature66and film deposition on the neighboring hybrid fins34converge together filling the gaps68. In some embodiments, the gap fill dielectric layer70may include a low-k material, such as SiONC, SiCN, SiOC, a high-k metal oxide, such as HfO2, ZrO2, HfAlOx, HfSiOx, Al2O3, and the like, or other dielectric material. Material of the gap fill dielectric layer70is selected to have etch selectivity relative to the material of the epitaxial source/drain features66and the material of the hybrid fins34. In some embodiments, the gap fill dielectric layer70is a high-k metal oxide, such as Al2O3. During backside process, the material of the gap fill dielectric layer70can be selectively removed without etching the epitaxial source/drain features66. InFIGS.12A-12D, an isotropic etch is performed to remove the gap fill dielectric layer70from horizontal and vertical surfaces on the substrate, leaving the gaps68filled with the gap fill dielectric layer70. Any suitable etching method can be used, for example a wet etching process with a suitable etchant can be used to remove a portion of the gap fill dielectric layer70. InFIGS.13A-13D, a contact etch stop layer (CESL)76is formed over the substrate10. The CESL76is formed on the epitaxial source/drain features66and the gap fill dielectric layer70. In some embodiments, the CESL76has a thickness in a range between about 1 nm and about 15 nm. The CESL76may include Si3N4, SiON, SiCN or any other suitable material, and may be formed by CVD, PVD, or ALD. InFIGS.14A-14D, an interlayer dielectric (ILD) layer78is formed over the substrate10. The materials for the ILD layer78include compounds comprising Si, O, C, and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer78. After the ILD layer78is formed, a planarization operation, such as CMP, is performed to expose the sacrificial gate electrode layer44for subsequent removal of the sacrificial gate structures40. The ILD layer78protects the epitaxial source/drain features66during the removal of the sacrificial gate structures40. InFIGS.15A-15D, the sacrificial gate electrode layer44and the sacrificial gate dielectric layer42are removed. The sacrificial gate structures40can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode layer44is polysilicon and the ILD layer78is silicon oxide, a wet etchant such as a Tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer44without removing the dielectric materials of the ILD layer78, the CESL76, and the sidewall spacers50. The sacrificial gate dielectric layer42is thereafter removed using plasma dry etching and/or wet etching. As shown inFIG.15C, after the sacrificial gate electrode layer44and the sacrificial gate dielectric layer42are removed, the first semiconductor layers22and second semiconductor layers24are exposed. The first semiconductor layers22can be selectively removed resulting in nanosheets of the second semiconductor layers24. The first semiconductor layers22can be removed using an etchant that can selectively etch the first semiconductor layers22against the second semiconductor layers24. When the first semiconductor layers22are Ge or SiGe and the second semiconductor layers24are Si, the first semiconductor layers22can be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. As shown inFIGS.16A-16D, after the nanosheets of the second semiconductor layers24are formed, a gate dielectric layer82is formed around each nanosheet of the second semiconductor layers24, and a gate electrode layer84is formed on the gate dielectric layer82. The gate dielectric layer82and the gate electrode layer84may be referred to as a gate stack. The gate dielectric layer82may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer82is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer82having a uniform thickness around each of the second semiconductor layers24. In some embodiments, the thickness of the gate dielectric layer82is in a range between about 1 nm and about 6 nm. The gate dielectric layer82includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, an interfacial layer (not shown) is formed between the second semiconductor layer24and the gate dielectric layer82. In some embodiments, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer82and the gate electrode layer84. The gate electrode layer84is formed on the gate dielectric layer82to surround each of the second semiconductor layer24(i.e., each channel) and the gate dielectric layer82. The gate electrode layer84includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layer84may be formed by CVD, ALD, electro-plating, or other suitable method. After the formation of the gate electrode layer84, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer78. After the planarization operation, the gate electrode layer84is recessed and a cap insulating layer86is formed over the recessed gate electrode layer84. The cap insulating layer86includes one or more layers of a silicon nitride-based material, such as SiN. The cap insulating layer86can be formed by depositing an insulating material followed by a planarization operation. In some embodiments, the cap insulating layer86may be omitted. InFIGS.17A-17D, front side source/drain contacts92,94are formed in the ILD layer78. Prior to forming the front side source/drain contacts92,94, contact holes are formed. Suitable photolithographic and etching techniques are used to form the contact holes through various layers, including the ILD layer78and the CESL76to expose the epitaxial source/drain features66. In some embodiments, the contact holes for front side source/drain contacts92,94are formed to expose the top of the gap fill dielectric layer70on one or both sides of the epitaxial source/drain features66. After the formation of the contact holes, a silicide layer90is selectively formed over the exposed top surface66tof the epitaxial source/drain features66. The silicide layer90conductively couples the epitaxial source/drain features66to the subsequently formed front side source/drain contacts92,94. The silicide layer90may be formed by depositing a metal source layer over the substrate10to cover the epitaxial source/drain features66and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After the formation of the metal source layer, a rapid thermal anneal process is performed, for example, a rapid anneal at about 800° C. During the rapid anneal process, the portion of the metal source layer over the epitaxial source/drain features66reacts with silicon in the epitaxial source/drain features66to form the silicide layer90. Unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer90includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, the silicide layer90has a thickness in a range between about 4 nm and 10 nm, for example between 5 nm and 6 nm. After the silicide layer90is formed, the front side source/drain contacts92,94are formed in the contact holes by CVD, ALD, electro-plating, or other suitable method. The front side source/drain contacts92,94may be in contact with the silicide layer90and the exposed surfaces of the gap fill dielectric layer70. The front side source/drain contacts92,94may include one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. In some embodiments, a barrier layer88may be formed on sidewalls of the contact holes prior to forming the front side source/drain contacts92,94. After deposition to fill the contact holes, a planarization process, such as CMP, is performed to remove excess deposition of the contact material and expose the top surface of the cap insulating layer86. The front side source/drain contact92denotes conductive features in connection with the epitaxial source/drain features66to be connected to a power rail, such as VDD or GND disposed therebelow. In some embodiments, the front side source/drain contacts92are not further connected to signal lines formed on subsequent interconnect layers thereabove. As shown inFIG.17B, at this stage of the fabrication, the front side source/drain contacts92(92a,92b) are in contact with the gap fill dielectric layer70next to the corresponding epitaxial source/drain features66. As shown inFIG.17B, the gap fill dielectric layers70(70a,70b) are positioned on either side of the epitaxial source/drain features66. In the example ofFIG.17B, the front side source/drain contact92acontacts only the gap fill dielectric layer70a. The front side source/drain contact92bcontacts the gap fill dielectric layer70aand70b. The front side source/drain contact94denotes conductive features in connection with the epitaxial source/drain features66to be connected to a signal line in the subsequent formed interconnect layers or to other devices on the substrate10. InFIGS.18A-18D, a second ILD layer96is formed over the substrate10. Conductive features are formed in the second ILD layer96to provide electrical connections to the epitaxial source/drain features66and/or the gate electrode layers84. In the example ofFIG.18A-18D, a conductive feature98in the second ILD layer96is connected to the front side source/drain contact94. In some embodiments, the conductive feature98is a signal line or connected to a signal line. A gate contact99is formed in the second ILD layer96to connect the gate electrode layer84to a signal line or to other devices. In some embodiments, the front side source/drain contacts92are not further connected to conductive features in the second ILD layer96. As shown inFIG.19A, after conductive features are formed in the second ILD layer96, an interconnect structure100, which includes multiple dielectric layers having metal lines and vias (not shown) formed therein, is formed on the second ILD layer96and electrically connected to the active semiconductor devices on the substrate10. The metal lines and vias in the interconnect structure100may be formed of copper or copper alloys, and may be formed using one or more damascene processes. The interconnect structure100may include multiple sets of inter-layer dielectric (ILD) layers and inter-metal dielectrics (IMDs) layers. In some embodiments, the interconnect structure100includes metal lines and vias for connecting signal lines only, but not connecting to power rails or connections to power rails. In other embodiments, the interconnect structure100includes a portion of power rails. Power rails indicate conductive lines connecting between the epitaxial source/drain features66and a power source, such as VDD, and VSS (GND). After the formation of the interconnect structure100, a carrier wafer110is temporarily bonded to a top side of the interconnect structure100. The carrier wafer110serves to provide mechanical support for the interconnect structure100and devices formed on the substrate10. InFIG.19B, the carrier wafer110along with the substrate10is flipped over so that the backside of the substrate10(i.e., the back surface10b) is facing up for backside processing as shown inFIGS.20A-Dto25A-D,FIGS.26A-G, andFIGS.27A-D.FIGS.20B-27Bare cross sectional views corresponding to line Y1-Y1inFIG.20A.FIGS.20C-27Care cross sectional views corresponding to line Y2-Y2inFIG.20A.FIGS.20D-27Dare across sectional views corresponding to line X-X inFIG.20A. InFIGS.20A-20D, a backside grinding is performed to expose the isolation layer36, the well portion32of the semiconductor fins30and the backside contact alignment features60. InFIGS.21A-21D, the exposed well portion32of the semiconductor fins30and the buffer layer14in contact with the gate dielectric layer82layer are removed from the backside by one or more etching processes. A liner layer122and a dielectric layer124are subsequently formed in the space vacated by the well portion32and the buffer layer14. The well portions32of the semiconductor fins30can be removed using an etch process having an etch selectivity for the material of the well portions32semiconductor fins30over the materials of the backside contact alignment features60and the transitional epitaxial layers64. In some embodiments, the well portions32of the semiconductor fins30can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. The buffer layer14adjacent the sacrificial gate dielectric layer42can be removed using the same or different etch process. After removal of the well portions32of the semiconductor fins30and the buffer layer14, the liner layer122is deposited on the exposed surfaces. In some embodiments, the liner layer122is deposited by a conformal deposition. The liner layer122can include a nitride material, such as silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), or any combinations thereof, a silicon oxide, silicon oxycarbide (SiOC), or silicon carbide (SiC). The liner layer122can be formed by, for example, ALD, CVD, PVD, PECVD, remote plasma CVD, or any suitable deposition technique. The dielectric layer124is deposited over the liner layer122to fill the cavities vacated by the well portions32of the semiconductor fins30and the buffer layer14. In some embodiments, the dielectric layer124includes a silicon oxide, a silicon oxide, a material convertible to a silicon oxide, a silicate glass (USG), an alkoxysilane compound (e.g., tetraethoxysilane (TEOS), tetramethoxysilane (TMOS)), thermal oxide, or any suitable dielectric material, or any combination thereof, and can be formed by FCVD, a spin-on coating process, or any suitable deposition technique. After the formation of the dielectric layer124, a planarization process, such as CMP, is performed to expose the backside contact alignment features60. The backside contact alignment features60are subsequently removed to form contact holes126to eventually expose the epitaxial source/drain feature66underneath for metal formation. InFIGS.22A-22D, the backside contact alignment features60are removed to expose the transitional epitaxial layer64. Any suitable etch processes can be used to remove the backside contact alignment features60. Since the transitional epitaxial layer64is formed on the backside contact alignment feature60, and the epitaxial source/drain feature66is formed on the transitional epitaxial layer64, the backside contact alignment feature60is aligned with the corresponding epitaxial source/drain feature66. The contact hole126vacated by the backside contact alignment feature60is aligned with the epitaxial source/drain feature66without using any photolithography and patterning process. InFIGS.23A-23D, an etching process is performed on the isolation layer36to expand the contact holes126. In some embodiments, an isotropic etching process is performed to trim the isolation layer36. The dielectric layer124is also trimmed during the process. In some embodiments, an isotropic plasma etching with an etchant comprising fluorocarbons is used. In other embodiments, a suitable wet etch can be used. In some embodiments, the contact holes126are expanded to expose the gap fill dielectric layers70adjacent to the epitaxial source/drain features66. InFIGS.24A-24D, the gap fill dielectric layers70are removed by a suitable etch process. In some embodiments, the gap fill dielectric layers70are removed using a wet etching method. For example, the gap fill dielectric layers70can be removed using wet etchant including NH4OH, and H2O2. The removal process is a selective removal process to remove the gap fill dielectric layers70, while the other exposed materials, such as the transitional epitaxial layer64and the dielectric layer124, are not removed. InFIGS.25A-25D, the transitional epitaxial layers64are removed by a suitable etch process to expose a top surface of the epitaxial source/drain features66. In some embodiments, the transitional epitaxial layers64are removed by a dry etch method. For example, the transitional epitaxial layers64can be removed by a dry etching process using fluorine-based etchant, such as CF4, NF3, SF6. In some embodiments, the transitional epitaxial layer64may be removed prior to removal of the gap fill dielectric layer70. As shown inFIGS.25A-25D, after the removal of the transitional epitaxial layer64and the gap fill dielectric layer70, the contact hole126extends further from between the gaps68to the front side source/drain contacts92, and a portion of the front side source/drain contacts92, the bottom surface66band side surfaces66sof the epitaxial source/drain features66are exposed. InFIGS.26A-26D, backside source/drain contacts128are formed by filling in the contact holes126with a conductive material. In some embodiments, a preclean process is performed prior to depositing the backside source/drain contacts128to remove residue left after the removal of the transitional epitaxial layer64and the gap fill dielectric layer70. The preclean process may be performed using a plasma process. In some embodiments, the exposed surfaces of the front side source/drain contact92may be recessed in a range between 1 nm and 3 nm during the preclean. After preclean, a conductive material is filled in the contact holes126to form the backside source/drain contacts128. The conductive material may be one or more of Co, W, Mo, Ru, Al, or compounds thereof. In some embodiments, the conductive material is filled in the contact holes126by CVD, ALD, electro-plating, or other suitable method. In some embodiments, a planarization process, such as CMP, may be performed after filling the contact holes126to form the backside source/drain contacts128. As shown inFIGS.26A-D, each backside source/drain contact128has a body portion128mand two sidewall portions128wextending from the body portion128m. The body portion128mcontacts the bottom surface66bof the epitaxial source/drain feature66. The two sidewall portions128wextend from the body portion128mto the front side source/drain contact92along the side surface66sof the epitaxial source/drain feature66. In some embodiments, the sidewall portion128wextends from the bottom surface66bto the top surface66tof the epitaxial source/drain feature66. The sidewall portions128wof the backside source/drain contact128fill the gaps68between the epitaxial source/drain feature66and the hybrid fins34. A cross section of the backside source/drain contacts128has an U-shape with the body portion128mand the sidewall portions128wforming a trench128t. The epitaxial source/drain feature66is enclosed in the trench128t. In some embodiments, the body portion128mhas a height H5, measured from a bottom surface128bof the body portion128mto the bottom surface66bof the epitaxial source/drain feature66. In some embodiments, the height H5is in a range between about 10 nm and about 30 nm. In some embodiments, the sidewall portion128whas a height H6, measured from the bottom surface66bof the epitaxial source/drain feature66to a surface of the front side source/drain contact92. In some embodiments, the height H6is in a range between from about 10 nm and about 70 nm. Alternatively, the height H6is similar to the height H4of the epitaxial source/drain feature66(marked inFIG.10B). The backside source/drain contacts128replace the removed gap fill dielectric layer70a,70band are in direct contact with the front side source/drain contacts92. Each backside source/drain contact128can be in contact with the front side source/drain contact92at one side or both sides of epitaxial source/drain feature66depending on the location of the corresponding front side source/drain contact92. In the example ofFIG.26B, the front side source/drain contact92ais in contact with the corresponding backside source/drain contact128on one side of the epitaxial source/drain feature66, while the front side source/drain contact92bis in contact with the corresponding backside source/drain contact128on both sides of the epitaxial source/drain feature66. Because the front side source/drain contact92is in electrical connection with the epitaxial source/drain feature66through the silicide layer90, the direct contact between the backside source/drain contact128and the front side source/drain contact92will allow electrical connection of the backside source/drain contact128to the epitaxial source/drain feature66. Therefore, an electrical connection is established between the backside source/drain contact128and the epitaxial source/drain feature66without relying on a silicide layer formed during backside processing, e.g., a silicide layer between the backside source/drain contact128and the epitaxial source/drain feature66. As shown inFIGS.26B-26D, the conductive material of the backside source/drain contacts128is deposited in the contact holes126without forming a silicide layer on the bottom surface66band side surfaces66sof the epitaxial source/drain features66. As a result, the backside source/drain contacts128are in direct contact with the epitaxial source/drain features66at one or more of surfaces, such as the side surfaces66sand the bottom surface66b, of the epitaxial source/drain features66. By omitting the silicide process during formation of the backside source/drain contacts128, embodiments of the present disclosure avoid exposing metal structures formed on the front side of the substrate10, such as the metal structures in the interconnect structure100, to a high temperature of a silicide process. Thus, the integrity of the metal structures is preserved. Using the silicide layer90formed during the front side processing as part of the conductive path for a backside source/drain contact, devices according to embodiments of the present disclosure effectively reduces high interface resistance between the source/drain feature and a source/drain contact formed on the backside of the substrate. FIGS.26E-26Gshow an embodiment alternative to the embodiment shown inFIGS.26B-D. In this embodiment, instead of omitting the silicide process, a low temperature silicide process is performed to form a silicide layer on the exposed surfaces of the epitaxial source/drain features66. As shown inFIGS.26E-26G, a silicide layer130is formed between the epitaxial source/drain features66and the backside source/drain contact128. The silicide layer130can be formed by depositing a metal source layer over the substrate to cover the epitaxial source/drain features66, followed by a low temperature anneal to form the silicide layer130over the epitaxial source/drain features66. In some embodiments, the metal source layer may include or be a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. The lower temperature anneal may be performed at a temperature below 400° C., for example at a temperature range between about 300° C. and 400° C. During the low temperature anneal, the portion of the metal source layer over the epitaxial source/drain features66reacts with silicon in the epitaxial source/drain features66to form the silicide layer130, as shown inFIGS.26E-26G. Unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer130includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, the silicide layer130has a thickness in a range between greater than 0 nm and less than 3 nm. The silicide layer130is thinner than the silicide layer90. In some embodiments, the silicide layer130has a thickness in a range between 0% and 50% thickness of the silicide layer90. In the device shown inFIGS.26E-26G, the backside source/drain contact128is in electrical connection with the epitaxial source/drain feature66through both the silicide layer130and the current path including the front side source/drain contact92and the silicide layer90. The additional connection through the silicide layer130improves performance of the device. By performing a low temperature silicide process, embodiments of the present disclosure avoid exposing metal structures formed on the front side of the substrate10, such as the metal structures in the interconnect structure100, thus, reducing interface resistance and preserving integrity of the metal structure at the same time. InFIGS.27A-27D, an ILD layer132is formed over the substrate. One or more conductive features134(only one is shown) may be formed in the ILD layer132. The conductive feature134is in contact with the backside source/drain contact128. In some embodiments, the conductive feature134is a portion of a power rail or is in connection with a power rail to be connected to a power supply. In other embodiments, the conductive feature134may be connected to an interconnect structure other than a power rail. FIG.28Ais a cross section view ofFIG.27Aalong the Y3-Y3as shown inFIG.20A. As shown inFIG.28A, when the epitaxial source/drain feature66is not connected to a backside source/drain contact, the gap fill dielectric layer70remains in the alignment recess58between the epitaxial source/drain feature66and the hybrid fin34. FIG.28Bis an extended cross section ofFIG.27Bto include two dielectric features, e.g. hybrid fins34in the sectional view. As shown inFIG.28B, the sidewall portions128wof the backside source/drain contact128are positioned between side surfaces66sof the epitaxial source/drain feature66and the adjacent dielectric features, e.g. hybrid fins34. FIG.28Cis an extended cross section ofFIG.27Dto include two gate stacks to show a length L2of the backside source/drain contact128along the X direction. In some embodiments, the length L2is in arrange between about 10 nm and about 50 nm. Various embodiments or examples described herein offer multiple advantages over the state-of-art technology. Some embodiments provide a semiconductor device having a backside source/drain contact using a silicide layer formed on the front side, thereby, reducing interface resistance between the backside source/drain contact and the source/drain feature. Some embodiments using a low temperature annealing to form a silicide layer during backside processing, therefore further reducing interface resistance and preserving integrity of the metal structure at the same time. Embodiments of the present disclosure also improve alignment between backside contact and front side transistors using a self-alignment feature in forming the backside source/drain contact. It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. Some embodiments of the present provide a semiconductor device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature. Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes first and second dielectric features, a first epitaxial source/drain feature formed between the first and second dielectric features, and a conductive feature having a first portion and a second portion, wherein the first portion of the conductive feature is disposed between the first dielectric feature and the first epitaxial source/drain feature, and the second portion of the conductive feature is disposed between the second dielectric feature and the first epitaxial source/drain feature. Some embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes forming an epitaxial source/drain feature between a first dielectric feature and a second dielectric feature on a substrate, wherein a first gap is formed between the epitaxial source/drain feature and the first dielectric features, and a second gap is formed between the epitaxial source/drain feature and the second dielectric features, filling the first and second gaps with a gap fill dielectric material, forming a source/drain contact on a front side of the substrate over the epitaxial source/drain feature and the gap fill dielectric material, removing the gap fill dielectric material from a backside of the substrate, and after removal of the gap fill dielectric material, filling the first and second gaps with a conductive material. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 56,945 |
11942531 | DETAILED DESCRIPTION Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of Semiconductor Device Including Sense Insulated-Gate Bipolar Transistor are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments. The semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell. According to this arrangement, the first diode and the second diode are electrically connected to the respective resistance portions in a manner oriented reversely to each other. It can thereby be selectively designated according to the polarity (positive/negative) of a voltage that is applied to the gate wiring portion whether through a first diode channel or a second diode channel a sense gate voltage is applied. If an arrangement is provided such that the first diode channel becomes conductive when turning on the main IGBT, at the turn-on time, a sense gate voltage is applied through the first resistance portion (first gate resistance) having a relatively low resistance. Thus, designing the first resistance value Rg1at the same level as a gate resistance Rgmof the main IGBT allows bringing a timing at which the sense IGBT is turned on close to a timing at which the main IGBT is turned on. As a result, a phase shift (phase difference) therebetween can be reduced, so that flow of an unexpected overcurrent to the sense IGBT can be suppressed. Accordingly, current noise at the turn-on time can be reduced. On the other hand, at the turn-off time of the main IGBT, the second diode channel becomes conductive, and a sense gate voltage is applied through the second resistance portion (second gate resistance) having a relatively high resistance. It can thereby be suppressed that a Hall current flows to the sense IGBT. Therefore, current noise at the turn-off time can be reduced, and the main IGBT can be gradually turned off (softly turned off). As a result of the above, introduction of a filter circuit and margin design such as setting a high overcurrent detection value for avoiding a malfunction can be made unnecessary. Because a gate driver can thereby be improved in detection sensitivity, the performance of a system including the semiconductor device of the present invention can be improved. The gate wiring portion of the sense IGBT cell may include a gate electrode formed with a predetermined wiring pattern to divide the sense IGBT cell into respective cell units, and the first resistance portion and the second resistance portion may be disposed on peripheral edge portions of the gate electrode, respectively. The gate electrode may include a striped pattern, and the first resistance portion and the second resistance portion may be disposed on one end portion of the gate electrode in the striped pattern and the other end portion on a side opposite to the one end portion, respectively. The first resistance portion may have a short wiring length compared to that of the second resistance portion. The first resistance portion may have a wide wiring width compared to that of the second resistance portion. According to this arrangement, by adjusting each of the first resistance portion and the second resistance portion in wiring length and wiring width, a difference in resistance value can be simply provided therebetween. The first diode may be formed of a first deposition layer disposed on the semiconductor layer, having a central portion of a first conductivity type and a peripheral edge portion of a second conductivity type enclosing the central portion, and the second diode is formed of a second deposition layer disposed on the semiconductor layer, having a central portion of a first conductivity type and a peripheral edge portion of a second conductivity type enclosing the central portion. According to this arrangement, by depositing and patterning a semiconductor material, the first diode and the second diode can be simply fabricated. Any one or both of the peripheral edge portion of the first deposition layer and the peripheral edge portion of the second deposition layer may be formed so as to enclose an entire circumference of the central portion inside thereof, respectively. According to this arrangement, p-n junctions can be formed across the entire circumferences of the respective central portions of one or both of the first deposition layer and the second deposition layer, so that the occurrence of a leak current can be suppressed. Any one or both of the peripheral edge portion of the first deposition layer and the peripheral edge portion of the second deposition layer may be formed so as to selectively enclose a part of the central portion inside thereof, respectively. According to this arrangement, any one or both of the first diode and the second diode can be downsized as compared with when the entire circumference of the central portion is enclosed by the peripheral edge portion. As a result, the degree of freedom in the layout of any one or both of the first diode and the second diode can be increased. Any one or both of the first deposition layer and the second deposition layer may be made of doped polysilicon. Because being made of doped polysilicon allows for easy processing (such as patterning) by an existing technique, any one or both of the first and second diodes can be fabricated with efficiency. The gate wiring may be connected to the central portion of the first deposition layer and the peripheral edge portion of the second deposition layer, and the semiconductor device may include a first contact wiring that connects the peripheral edge portion of the first deposition layer and the first resistance portion and a second contact wiring that connects the central portion of the second deposition layer and the second resistance portion. The first resistance portion and the second resistance portion may be formed using a deposition layer that is the same as the first deposition layer and the second deposition layer. According to this arrangement, because the respective diodes and the respective resistance portions can be simultaneously formed, the manufacturing efficiency can be improved. The gate wiring may include a main line portion and a first branching portion and a second branching portion branching off the main line portion, and the first branching portion and the second branching portion may be connected to the first diode and the second diode, respectively. The semiconductor device may include a collector electrode disposed on a back surface of the semiconductor layer, being common between the main IGBT and the sense IGBT. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, for the sake of clarification, dimensional ratios among components are sometimes changed from figure to figure for illustration. FIG.1is a schematic perspective view of a semiconductor device1according to a preferred embodiment of the present invention.FIG.2is a schematic plan view of the semiconductor device1inFIG.1. InFIG.2, a gate wiring7is hatched for clarification. The semiconductor device1has a basic form as a trench gate type IGBT. The semiconductor device1includes a semiconductor substrate2as an example of a semiconductor layer of the present invention. The semiconductor substrate2has a structure in which a p+-type collector region3, an n-type buffer region4, and an n−-type drift region5are laminated in order from its back surface toward its front surface. On the semiconductor substrate2, an electrode film9including a main emitter electrode6, a gate wiring7, and a sense emitter electrode8is formed. On the back surface of the semiconductor substrate2, a collector electrode10is formed substantially entirely thereacross. The semiconductor substrate2is formed in, for example, a rectangular shape in a plan view, and the semiconductor device1accordingly has a rectangular shape in a plan view. The electrode film9is formed in a rectangular region extending substantially the entirety of the front surface of the semiconductor substrate2. The gate wiring7includes a pad portion11formed in a corner portion of the semiconductor device1, an outer peripheral wiring portion12as an example of a main line portion of the present invention formed across the entire circumference of an outer peripheral portion of a front surface of the semiconductor device1, a plurality of (in the present preferred embodiment, four) main gate finger portions13extending from the outer peripheral wiring portion12toward an inner region of the front surface of the semiconductor device1, and a plurality of (in the present preferred embodiment, two) sense gate finger portions14that are likewise extending from the outer peripheral wiring portion12toward an inner region of the front surface of the semiconductor device1. The front surface of the semiconductor device1has an oblong shape having a pair of short sides and a pair of long sides connecting the short sides, and accordingly, the outer peripheral wiring portion12is formed in an oblong ring shape. The main gate finger portions13are formed such that two each extend parallel to each other at an interval therebetween from the pair of long side parts of the outer peripheral wiring portion12. The sense gate finger portions14are formed one each from the long side part and short side part composing a corner portion of the outer peripheral wiring portion12such that a predetermined pad region23is defined inside thereof. One and the other of the sense gate finger portions14are, respectively, an ON-side finger15and an OFF-side finger16as an example of a first branching portion and second branching portion of the present invention. The ON-side finger15and the OFF-side finger16are opposed such that an open portion22to open a part of the pad region23is formed between each other's distal end portions. The sense emitter electrode8is disposed in a corner portion (pad region23) of the semiconductor substrate2enclosed by the sense gate finger portions14and the corner portion of the outer peripheral wiring portion12, and the main emitter electrode6is disposed in a region covering substantially the entirety of the semiconductor substrate2enclosed by the outer peripheral wiring portion12outside of said corner portion. The main emitter electrode6, the gate wiring7, and the sense emitter electrode8are formed in a mutually isolated state. In each section between the electrodes6to8, a separation region51for isolation therebetween is formed. A passivation film (not shown) is formed in a manner covering the main emitter electrode6, the gate wiring7, and the sense emitter electrode8and the front surface of the semiconductor substrate2exposed from the wiring and electrodes. In the passivation film, as shown by alternate long and two short dashed lines inFIG.1andFIG.2, a gate pad opening17, main emitter pad openings18, and a sense emitter pad opening19are formed. The gate pad opening17is formed so as to expose a part of the pad portion11. The main emitter pad opening18is formed so as to expose a part of a front surface of the main emitter electrode6. The sense emitter pad opening19is formed so as to expose a part of the sense emitter electrode8. In the present preferred embodiment, a plurality of (for example, four) main emitter pad openings18are arrayed along a long side of the rectangular front surface of the semiconductor device1. The semiconductor device1is connected to a driver IC21(gate driver) to control IGBT operation by bonding wires20connected to the pad openings17to19. FIG.3is an enlarged view of a part surrounded by a broken line III inFIG.2.FIGS.4A to4Care schematic views showing cell patterns of a sense cell region25and a main cell region26. As described above, on the semiconductor substrate2, the pad region23a part of which is opened by the open portion22is formed, and the sense emitter electrode8is disposed in the pad region23. The sense emitter electrode8has a projection portion24projecting from the pad region23to the open portion22. The projection portion24is sandwiched by the distal end portion of the ON-side finger15and the distal end portion of the OFF-side finger16. On the other hand, the main emitter electrode6is disposed outside of the pad region23. Moreover, as front surface regions of the semiconductor substrate2, the sense cell region25is defined under the sense emitter electrode8, and the main cell region26is defined under the main emitter electrode6. As shown inFIGS.4A and4B, in the sense cell region25and the main cell region26, a plurality of sense side trenches27and a plurality of main side trenches28are arrayed at equal intervals. Moreover, both ends of each of the sense side trenches27and the main side trenches28are respectively electrically connected to the outer peripheral wiring portion12, the main gate finger portion13, or the sense gate finger portion14. By the sense side trenches27and the main side trenches28, the sense cell region25and the main cell region26are defined into sense cells31(sense IGBT cells) and main cells32(main IGBT cells) in stripe shapes, respectively. Also, the sense side trenches27, in the present preferred embodiment, include an ON-side contact portion29and an OFF-side contact portion30led out from under the open portion22toward the ON-side finger15and the OFF-side finger16. That is, the gate wiring7is, as shown inFIG.3, via mutually different channels branched off from the outer peripheral wiring portion12being the ON-side finger15and the OFF-side finger16, made to contact the ON-side contact portion29and the OFF-side contact portion30via resistance wirings39and40to be described later, respectively. In addition, the sense side trenches27may be, as shown inFIG.4C, formed in a grid shape in a manner defining matrix-shaped sense cells31. In this case, it suffices that the ON-side contact portion29and the OFF-side contact portion30are disposed on peripheral edge portions of a grid-shaped pattern, respectively. Of course, the grid-shaped gate trench pattern can also be applied to the main side trenches28of the main cell region26(not shown). As shown inFIG.3, between the ON-side contact portion29and the ON-side finger15, an ON-side diode33as an example of a first diode of the present invention is interposed. On the other hand, between the OFF-side contact portion30and the OFF-side finger16, an OFF-side diode34as an example of a second diode of the present invention is interposed. Next, referring toFIG.5toFIGS.9A,9B, and9C, the configuration of the semiconductor device1will be described in greater detail. FIG.5is a sectional view presented when the semiconductor device1is cut along a cutting line V-V inFIG.3.FIGS.6A and6Bare sectional views presented when the semiconductor device1is cut along a cutting line VIA-VIA and a cutting line VIB-VIB inFIG.3, respectively.FIGS.7A and7Bare sectional views presented when the semiconductor device1is cut along a cutting line VIIA-VIIA and a cutting line VIIB-VIIB inFIG.3, respectively.FIGS.8A to8Care schematic views for explaining arrangements of the ON-side diode33.FIGS.9A to9Care schematic views for explaining arrangements of the OFF-side diode34. The semiconductor substrate2may be, for example, an n−-type silicon substrate having a thickness of 50 μm to 200 μm. The semiconductor substrate2, as described above, has a structure in which the p+-type collector region3, the n-type buffer region4, and the n−-type drift region5are laminated. As a p-type dopant of the p+-type collector region3, for example, B (boron), Al (aluminum), and the like can be used (hereinafter, the same applies to p-type impurity regions). On the other hand, as an n-type dopant of the n-type buffer region4and the n−-type drift region5, for example, N (nitride), P (phosphorous), As (arsenic), and the like can be used (hereinafter, the same applies to n-type impurity regions). Also, the p+-type collector region3has a dopant concentration of, for example, 1×1015cm−3to 2×1019cm−3. On the other hand, the n-type buffer region4has a dopant concentration of, for example, 1×1015cm−3to 5×1017cm−3, and the n−-type drift region5has a dopant concentration of, for example, 1×1013cm−3to 5×1014cm−3. In a front surface portion of the n−-type drift region5, a p-type base region35is formed. The p-type base region35is formed substantially across the entire region of the semiconductor substrate2in a manner extending across the sense cell region25and the main cell region26. The p-type base region35has a dopant concentration of, for example, 1×1016cm−3to 1×1018cm−3. Also, the p-type base region35has a depth of, for example, 1.0 μm to 3.0 μm from its front surface. Moreover, the sense side trenches27and the main side trenches28are formed in a manner extending from the front surface of the semiconductor substrate2beyond a bottom portion of the p-type base region35. The p-type base regions35between adjacent sense side trenches27and adjacent main side trenches28are thereby respectively divided in stripe shapes. The divided stripe-shaped semiconductor regions (Si crystal regions) are defined as an active region of a sense IGBT and an active region of a main IGBT, respectively. As shown inFIG.5, the interval P1between the adjacent sense side trenches27(center to center distance of the sense side trenches27) is, for example, 1.5 μm to 7.0 μm. Also, the width W1of the sense side trench27is, for example, 0.5 μm to 1.5 μm. Also, the interval P2between the adjacent main side trenches28(center to center distance of the main side trenches28) and the width W2of the main side trench28are the same as the interval P1between the sense side trenches27and the width W1of the sense side trench27, respectively. On an inner surface of the sense side trench27and the main side trench28and the front surface of the semiconductor substrate2, a gate insulating film36is integrally formed. The gate insulating film36is made of, for example, SiO2. Also, the gate insulating film36has a thickness of, for example, 1100 Å to 1300 Å (in the present preferred embodiment, 1200 Å). Moreover, in the respective trenches27and28, an electrode material made of, for example, polysilicon or the like is buried via the gate insulating film36. Thereby, a sense side gate electrode37is formed in the sense side trenches27, and a main side gate electrode38is formed in the main side trenches28. The respective electrodes (resistance portions)37and38are, in the present preferred embodiment, buried up to opening ends of the respective trenches27and28, respectively. In a front surface portion of the p-type base region35of each of the sense cells31and the main cells32, an n+-type emitter region46,47is formed. The n+-type emitter region46,47has a depth of, for example, 0.2 μm to 0.6 μm. Also, the n+-type emitter region46,47has a dopant concentration of 1×1019cm−3to 5>1020cm−3. Also, in a front surface portion of the p-type base region35of each of the sense cells31and the main cells32, a p+-type base contact region48,49is formed. The p+-type base contact region48,49is formed in a manner extending from the front surface of the semiconductor substrate2beyond a bottom portion of the n+-type emitter region46,47. The p+-type base contact region48,49has a depth of, for example, 0.2 μm to 0.8 μm. Also, the p+-type base contact region48,49has a dopant concentration of, for example, 5×1018cm−3to 1×1020cm−3. As shown inFIGS.6A and6BandFIGS.7A and7B, on the gate insulating film36in the front surface region of the semiconductor substrate2, a wiring film63including the ON-side diode33, the OFF-side diode34, the ON-side resistance wiring39, and the OFF-side resistance wiring40is formed. The wiring film63is formed of deposition layers (a first deposition layer and a second deposition layer) of doped polysilicon, and is insulated by the gate insulating film36with respect to the semiconductor substrate2. Because being made of doped polysilicon allows for easy processing (such as patterning) by an existing technique, the ON-side diode33, the OFF-side diode34, the ON-side resistance wiring39, and the OFF-side resistance wiring40can be fabricated with efficiency. The ON-side diode33is, as shown inFIG.7A, disposed near the ON-side contact portion29separately from a terminal end portion of said trench27, and the ON-side resistance wiring39is disposed between the ON-side diode33and the ON-side contact portion29. On the other hand, the OFF-side diode34is, as shown inFIG.7B, disposed near the OFF-side contact portion30separately from a terminal end portion of said trench27, and the OFF-side resistance wiring40is disposed between the OFF-side diode34and the OFF-side contact portion30. The ON-side diode33, as shown inFIGS.8A and8B, includes a p-type portion41as an example of a central portion of the present invention being in a circular shape and an n-type portion42as an example of a peripheral edge portion of the present invention being in a quadrangular ring shape enclosing the entire circumference of said p-type portion41for example, and a p-n junction is formed along an outer periphery of the p-type portion41. Similarly, the OFF-side diode34, as shown inFIGS.9A and9B, includes a p-type portion43as an example of a central portion of the present invention being in a circular shape and an n-type portion44as an example of a peripheral edge portion of the present invention being in a quadrangular ring shape enclosing the entire circumference of said p-type portion43for example, and a p-n junction is formed along an outer periphery of the p-type portion43. As above, the p-n junctions are formed across the entire circumferences of the respective central portions (p-type portions41and43) of the ON-side diode33and the OFF-side diode34, so that the occurrence of a leak current from the ON-side diode33and the OFF-side diode34can be suppressed. In addition, the p-type portion41,43is not necessarily in a circular shape, and may be in, for example, a triangular shape, a quadrangular shape, etc. Also, the n-type portion42,44is not necessarily in a quadrangular ring shape, and may be in, for example, a circular ring shape. Further, the entire circumference of the p-type portion41,43may not be enclosed by the n-type portion42,44. For example, as shown inFIG.8CandFIG.9C, an arch-shaped n-type portion42,44enclosing three sides of a quadrangular-shaped p-type portion41,43may be formed, and a remaining side of the p-type portion41,44may be exposed. This arrangement allows downsizing the ON-side diode33and the OFF-side diode34by the regions surrounded by broken lines45, as compared with when the entire circumference of the p-type portion41,43is enclosed. As a result, the degree of freedom in the layout of the ON-side diode33and the OFF-side diode34can be increased, and the semiconductor device1can also be miniaturized. The ON-side resistance wiring39, as shown inFIGS.8A to8C, extends linearly between the ON-side contact portion29and the ON-side diode33, and has a length Lon(for example, 10 μm to 50 μm) and a width Won(for example, 10 μm to 100 μm). Also, as shown inFIG.7A, the ON-side resistant wiring39is disposed so as to overlap the sense side gate electrode37within the ON-side contact portion29, and connected to the sense side gate electrode37. Similarly, the OFF-side resistance wiring40, as shown inFIGS.9A to9C, extends linearly between the OFF-side contact portion30and the OFF-side diode34, and has a length Loff(for example, 10 μm to 50 μm) and a width Woff(for example, 10 μm to 100 μm). Also, as shown inFIG.7B, the OFF-side resistant wiring40is disposed so as to overlap the sense side gate electrode37within the OFF-side contact portion30, and connected to the sense side gate electrode37. In the present preferred embodiment, the width Wonof the ON-side resistance wiring39and the width Woffof the OFF-side resistance wiring40are the same as each other. On the other hand, regarding the length, the length Lonof the ON-side resistance wiring39is shorter than the length Loffof the OFF-side resistance wiring40. That is, when the ON-side resistance wiring39and the OFF-side resistance wiring40are compared, a resistance value Rg1(first resistance value) of the ON-side resistance wiring39having a relatively short length Lonis smaller than a resistance value Rg2(second resistance value) of the OFF-side resistance wiring40having a length Lofflonger than the length Lon. In the present preferred embodiment, the resistance value Rg1of the ON-side resistance wiring39is, for example, 1Ω to 50Ω. On the other hand, the resistance value Rg2of the OFF-side resistance wiring40is 400Ω to 600Ω. In addition, the resistance value Rg1is preferably the same as a resistance value Rgsof the sense side gate electrode37and a resistance value Rgmof the main side gate electrode38. An interlayer insulating film50is formed so as to cover substantially the entirety of the front surface region of the semiconductor substrate2. The interlayer insulating film50is made of, for example, SiO2. In addition, the interlayer insulating film50has a thickness of, for example, 3000 Å to 8000 Å (in the present preferred embodiment, 6000 Å). In the interlayer insulating film50, various contact holes52to59are formed. The main emitter electrode6, the gate wiring7, and the sense emitter electrode8are formed on the interlayer insulating film50. As shown inFIG.5, the main emitter electrode6and the sense emitter electrode8are connected to the n+-type emitter regions47and46and the p+-type base contact regions49and48via the contact holes53and52, respectively. As shown inFIGS.7A and7B, to the p-type portion41of the ON-side diode33exposed from the contact hole56, the distal end portion of the ON-side finger15is connected. On the other hand, the n-type portion42exposed from the contact hole57is connected to an ON-side contact wiring60as an example of a first contact wiring of the present invention connected to the ON-side resistance wiring39via the contact hole54. To the n-type portion44of the OFF-side diode34exposed from the contact hole59, the distal end portion of the OFF-side finger16is connected. On the other hand, the p-type portion43exposed from the contact hole58is connected to an OFF-side contact wiring61as an example of a second contact wiring of the present invention connected to the OFF-side resistance wiring40via the contact hole55. In addition, the ON-side contact wiring60and the OFF-side contact wiring61are, in the present preferred embodiment, constructed as the electrode film9described above. As above, the ON-side diode33is connected at an anode side (p-side) to the gate wiring7, and the OFF-side diode34is connected at a cathode side (n-side) to the gate wiring7. That is, the ON-side diode33is connected in a forward direction with respect to a positive gate voltage (reverse direction with respect to a negative gate voltage), and the OFF-side diode34is connected in a reverse direction with respect to a positive gate voltage (forward direction with respect to a negative gate voltage). It can thereby be selectively designated according to the polarity (positive/negative) of a voltage that is applied to the gate electrode37,38whether through a channel that is through the ON-side diode33or a channel that is through the OFF-side diode34a sense gate voltage is applied. The shapes of the distal end portion of the ON-side finger15(OFF-side finger16) and the ON-side contact wiring60(OFF-side contact wiring61) will be described in greater detail. First, as shown inFIG.8A, the distal end portion of the ON-side finger15is formed along the outer periphery of the p-type portion41in the center, and in the present preferred embodiment, formed in a circular shape. The contact hole56is also similarly formed in a circular shape. The ON-side contact wiring60is formed in a ring shape to enclose the distal end portion of its ON-side finger15, and connected to the n-type portion42via the contact hole57formed along the periphery of distal end portion of the ON-side finger15. A separation region62is formed in a part of the ON-side contact wiring60. The ON-side finger15is, via the separation region62, accessible to the p-type portion41located in the central portion of the ON-side diode33. On the other hand, the distal end portion of the OFF-side finger16and the OFF-side contact wiring61have shapes identical to the shapes of the distal end portion of the ON-side finger15and the ON-side contact wiring60that have been rotated 180°. Specifically, as shown inFIG.9A, an end portion of the OFF-side contact wiring61is formed along the outer periphery of the p-type portion43in the center, and in the present preferred embodiment, formed in a circular shape. The contact hole58is also similarly formed in a circular shape. The distal end portion of the OFF-side finger16is formed in a ring shape to enclose an end portion of its OFF-side contact wiring61, and connected to the n-type portion44via the contact hole59formed along the periphery of the end portion of the OFF-side contact wiring61. A separation region64is formed in a part of the OFF-side finger16. The OFF-side contact wiring61is, via the separation region64, accessible to the p-type portion43located in the central portion of the OFF-side diode34. The electrode film9including the main emitter electrode6, the gate wiring7, the sense emitter electrode8, the ON-side contact wiring60, and the OFF-side contact wiring61is made of, for example, an Al—Si—Cu-based alloy. Also, between the semiconductor substrate2and the electrode film9, a barrier film (not shown) having, for example, a Ti/TiN/Ti laminated structure may be interposed. A collector electrode10formed on the back surface of the semiconductor substrate2has an AlSi/Ti/Ni/Au laminated structure laminated in order from the back surface. The collector electrode10, as shown inFIG.5, serves as a common electrode between the sense cells31and the main cells32. An equivalent circuit of the semiconductor device1having been described above is shown inFIG.10. In the equivalent circuit, to the sense cell31, a sense current that is on the order of 1/2000 (absolute value) of a main current flowing to the main cell32can be made to flow. Moreover, according to the semiconductor device1, with respect to a positive gate voltage, the ON-side diode33is connected in a forward direction, and the OFF-side diode34is connected in a reverse direction. It can thereby be selectively designated according to the polarity (positive/negative) of a voltage that is applied to the gate electrode37,38whether through a channel of the ON-side diode33using the ON-side finger15or a channel of the OFF-side diode34using the OFF-side finger16a sense gate voltage is applied. Because the ON-side diode33channel becomes conductive when turning on the main cell32, at the turn-on time, a sense gate voltage is applied through the ON-side resistance wiring39having a short wiring length Loncompared to that of the OFF-side resistance wiring40. The resistance value Rg1of the ON-side resistance wiring39can thus be made substantially the same as the resistance value Rgm of the main side gate electrode38. Therefore, a timing at which the sense cell31is turned on can be substantially synchronized with a timing at which the main cell32is turned on. As a result, a phase shift (phase difference) therebetween can be reduced, so that flow of an unexpected overcurrent to the sense cell31can be suppressed. Accordingly, current noise at the turn-on time can be reduced. On the other hand, at the turn-off time of the main cell32, the OFF-side diode34channel becomes conductive, and a sense gate voltage is applied through the highly resistant OFF-side resistance wiring40having a long wiring length Loffcompared to that of the ON-side resistance wiring39. It can thereby be suppressed that a Hall current flows to the sense cell31beyond the main cell region26. Therefore, current noise at the turn-off time can be reduced, and the main cell32can be gradually turned off (softly turned off). The effect to reduce current noise at the turn-on and turn-off time mentioned above can be proved byFIG.11.FIG.11is a graph showing a relationship between a gate resistance of the sense cell31and a peak sense current flowing in the sense cell31. As shown inFIG.11, it can be understood that at the turn-on time of the main cell32, the smaller the gate resistance of the sense cell31, the smaller the peak sense current (that is, a peak value of current noise). On the other hand, it can be understood that at the turn-off time of the main cell32, the greater the gate resistance of the sense cell31, the smaller the peak sense current. Thus, as in the present preferred embodiment, using the ON-side resistance wiring39having a low resistance value Rg1as a gate resistance at the turn-on time and, at the turn-off time, using the OFF-side resistance wiring40having a high resistance value Rg2as a gate resistance allows reducing current noise either at the turn-on or the turn-off time. As a result of the above, it becomes no longer necessary, in order to avoid the sense cell31malfunctioning, to introduce a filter circuit into the semiconductor device1and carry out margin design such as setting a high overcurrent detection value in the driver IC21(refer toFIG.1). Because the driver IC21can thereby be improved in detection sensitivity, the performance of a system including the semiconductor device1of the present invention can be improved. FIG.12is a flowchart of a manufacturing process of the semiconductor device1. The manufacturing process of the semiconductor device1will be described with reference toFIG.12andFIG.5toFIGS.7A,7B, and7C. For manufacturing the semiconductor device1, first, by a semiconductor substrate2(n−-type drift region5) being selectively etched, sense side trenches27and main side trenches28are simultaneously formed (S1). Next, by the semiconductor substrate2being thermally oxidized, a gate insulating film36is formed in the entire front surface region including the inner surface of the trenches27and28(S2). Next, by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method, polysilicon is deposited on the semiconductor substrate2(S3). The deposition of polysilicon is continued until the trenches27and28are completely filled back and the semiconductor substrate2is covered with polysilicon. Next, by said polysilicon being etched back, an unnecessary part of the polysilicon is removed. A sense side gate electrode37and a main side gate electrode38buried in the respective trenches27and28are simultaneously formed (S4). Thereafter, by performing thermal oxidation according to necessity, a thermally oxidized film may be formed on an upper surface of the gate electrode37,38(buried polysilicon). Next, by, for example, an LPCVD (Low Pressure Chemical Vapor Deposition) method, polysilicon is deposited on the semiconductor substrate2(S5). Thereafter, into said polysilicon, a p-type dopant and an n-type dopant are respectively selectively ion-implanted. Next, by the ion-implanted polysilicon being selectively etched, an ON-side diode33, an OFF-side diode34, an ON-side resistance wiring39, and an OFF-side resistance wiring40are simultaneously formed (S6). Next, a p-type dopant is ion-implanted to the front surface of the n−-type semiconductor substrate2, and thereafter, the semiconductor substrate2is annealed. The p-type dopant is thereby subjected to drive-in diffusion, and thus a p-type base region35is formed (S7). Next, an n-type dopant is ion-implanted to the front surface of the semiconductor substrate2, and thereafter, the semiconductor substrate2is annealed. The n-type dopant is thereby subjected to drive-in diffusion, and thus n+-type emitter regions46and47are formed (S8). Next, a p-type dopant is ion-implanted to the front surface of the semiconductor substrate2, and thereafter, the semiconductor substrate2is annealed. The p-type dopant is thereby subjected to drive-in diffusion, and thus p+-type base regions48and49are formed (S9). Next, an interlayer insulating film50is formed on the semiconductor substrate2by, for example, a CVD method (S10). Next, on the semiconductor substrate2, a material for an electrode film9is deposited by, for example, a sputtering method. Then, by patterning said electrode film material, an main emitter electrode6, a gate wiring7, a sense emitter electrode8, an ON-side contact wiring60, and an OFF-side contact wiring61are simultaneously formed (S11). Next, after the semiconductor substrate2is reduced in thickness by grinding from the back surface according to necessity, n-type and p-type dopants are selectively ion-implanted to the back surface of the semiconductor substrate2, and thereafter, the semiconductor substrate2is annealed (in the present preferred embodiment, annealed by laser). The n-type and p-type dopants are thereby subjected to drive-in diffusion, and thus an n-type buffer region4and a p+-type collector region3are formed (S12). Thereafter, by depositing an electrode material on the back surface of the semiconductor substrate2by, for example, a sputtering method, a collector electrode10is formed. The semiconductor device1shown inFIG.1toFIGS.7A,7B, and7Cis obtained through the steps as above. In addition, the manufacturing process mentioned above merely represents a part of the manufacturing process of the semiconductor device1, and the manufacturing process of the semiconductor device1may include steps that are not described in the above. Next, description will be given of usage modes of the semiconductor device1. <Semiconductor Package> FIG.13is a schematic plan view of a semiconductor package71into which the semiconductor device1is incorporated.FIG.14is a sectional view showing a mounting structure of the semiconductor package71inFIG.13. The semiconductor package71includes a semiconductor device1and electrodes72to74, wires75to77and a resin package78. InFIG.13, the resin package78is shown by alternate long and two short dashed lines. The semiconductor package71is mounted on a mounting substrate79. As shown inFIG.14, the semiconductor package71is used as an electronic component that performs a switching function, a rectifying function, an amplifying function, or the like, in an electrical circuit depending on the type of the semiconductor device1. The electrode72includes a die bonding pad80and a lead81. The die bonding pad80and the lead81are made of, for example, a conductive material such as copper. The die bonding pad80is for loading the semiconductor device1. The die bonding pad80is in a flat plate shape. The die bonding pad80has an arrangement surface801and a back surface802. The arrangement surface801faces in a direction z1. The back surface802faces in a direction z2. On the arrangement surface801, the semiconductor device1is disposed. Heat generated in the semiconductor device1is transferred to the die bonding pad80. In the die bonding pad80, a hole82that penetrates from the arrangement surface801to the back surface802is formed. As shown inFIG.13, the hole82may have a shape, in an x-y plane view, recessed in a direction x1from an end portion at a side in a direction x2of the die bonding pad80. The lead81has a shape linearly extending from the die bonding pad80. The lead81is for insertion mounting. As shown inFIG.14, the lead81is inserted into a hole83. The semiconductor package71is thereby mounted on the mounting substrate79. The hole83is filled with solder84in order to fix the lead81to the mounting substrate79. As shown inFIG.13, the lead81has a coupling portion811and a terminal portion812. The coupling portion811and the terminal portion812may be integrally molded. The coupling portion811connects to the die bonding pad80. The coupling portion811has a shape extending from the die bonding pad80in a direction to cross the arrangement surface801. The terminal portion812connects to the coupling portion811. The terminal portion812extends from the coupling portion811in the direction x1. The terminal portion812has a part projecting from the resin package78. The electrode73includes a wire bonding pad85and a lead86. The electrode73is positioned, in an x-y plane view, on a side in the direction x1of the die bonding pad80and on a side in a direction y1of the lead81. The wire bonding pad85and the lead86may be integrally molded. The wire bonding pad85and the lead86are made of, for example, a conductive material such as cooper. The wire bonding pad85has a substantially rectangular flat plate shape smaller than the die bonding pad80. The lead86connects to the wire bonding pad85. The lead86has a shape linearly extending from the wire bonding pad85in the direction x1. The lead86is in juxtaposition to the lead81. The lead86has a part projecting from the resin package78. The lead86is for insertion mounting. As shown inFIG.14, the lead86is inserted into the hole83. The semiconductor package71is thereby mounted on the mounting substrate79. The hole83is filled with solder84in order to fix the lead86to the mounting substrate79. The electrode74includes a wire bonding pad87and a lead88. The electrode74is positioned, in an x-y plane view, on a side in the direction x1of the die bonding pad80and on a side in a direction y2of the lead81. The wire bonding pad87and the lead88may be integrally molded. The wire bonding pad87and the lead88are made of, for example, a conductive material such as cooper. The wire bonding pad87has a substantially rectangular flat plate shape smaller than the die bonding pad80. The lead88connects to the wire bonding pad87. The lead88has a shape linearly extending from the die bonding pad87in the direction x1. The hole83is filled with solder84in order to fix the lead88to the mounting substrate79. The lead88is in juxtaposition to the lead81. Between the lead88and the lead86, the lead81is positioned. The lead88has a part projecting from the resin package78. The lead88is for insertion mounting. As shown inFIG.14, the lead88is inserted into the hole83. The semiconductor package71is thereby mounted on the mounting substrate79. Referring mainly toFIG.14, the resin package78covers the semiconductor device1and the electrodes72to74. The resin package78is made of, for example, a black epoxy resin. As shown inFIG.14, the resin package78has a first surface781and a second surface782. The first surface781has a flat surface783and a tapered surface784. As shown inFIG.14, the flat surface783is a mounting surface for mounting the semiconductor package71on the mounting substrate79. From the flat surface783, the back surface802of the die bonding pad80is exposed. The flat surface783may be flush with the back surface802, and may not be flush with the back surface802. The tapered surface784continues to the flat surface783. The tapered surface784has a shape heading to the outside in an x-y plane gradually in the direction z1. The second surface782has a plurality of flat surfaces785and a plurality of tapered surfaces786. The respective tapered surfaces786connect to any of the plurality of flat surfaces785. The respective tapered surfaces786have shapes heading to the outside in an x-y plane gradually in the direction z2. The respective tapered surfaces786connect to the tapered surface784. In the resin package78, a pin trace787that is recessed from one of the plurality of flat surfaces785is formed. Also, in the resin package78, a screw hole788is formed. Through the screw hole788, a screw90to fix the semiconductor package71to a heat dissipation plate89is inserted. The wires75to77are made of, for example, a metal such as aluminum. The wire75is bonded to the gate wiring7of the semiconductor device1and the wire bonding pad85. The gate wiring7and the wire bonding pad85are thereby conductive. The wire76is bonded to the main emitter electrode6of the semiconductor device1and the wire bonding pad87. The main emitter electrode6and the wire bonding pad87are thereby conductive. The wire77is bonded to the sense emitter electrode8of the semiconductor device1and the wire bonding pad87. The sense emitter electrode8and the wire bonding pad87are thereby conductive. <Semiconductor Module> FIG.15is a schematic plan view of a semiconductor module91into which the semiconductor device1is incorporated.FIG.16is a view in which a resin-made base portion92of the semiconductor module91inFIG.15is omitted.FIG.17is a diagram showing an inverter circuit101constituted by the semiconductor module91inFIG.15. The semiconductor module91includes mainly a base portion92made of resin, electrode plates93and94(94u,94v, and94w), and95made of metal. The base portion92is formed in a case shape showing an oblong shape in a plan view, and is opened upward. The electrode plates93to95may be made of, for example, Cu (copper), Al (aluminum), or an alloy of Cu and Al. The semiconductor module91is constructed by molding the electrode plates93to95on the base portion92. The semiconductor module91may be fixed (for example, screwed) to a heat sink via a heat dissipation sheet. The resin electrode plates94u,94v, and94ware arranged side by side with their respective low step portions96provided with a gap therebetween, and the electrode plate93is disposed opposite to end edges of the respective low step portions96of the side-by-side electrode plates94. The electrode plate95may have a communicating portion97extending in the direction in which the electrode plates94u,94v, and94ware arranged and extending portions98(98a,98b,98c, and98d) provided at predetermined intervals from the communicating portion97. The communicating portion97overlaps, along an end edge of the electrode plate93opposed to the respective low step portions96of the electrode plates94, the electrode plate93at a predetermined clearance thereover. Moreover, the extending portions98overlap respective sides of the metal electrode plates94u,94v, and94w. Accordingly, the extending portion98bextends along a gap between the electrode plates94uand94vwith a width across both plates, and the extending portion98cextends along a gap between the electrode plates94vand94wwith a width across both plates. The electrode plates94respectively include narrow-width high step portions99extending from widthwise central portions of end edges opposed to the electrode plate93of their low step portions96. The high step portion99with an upward offset climbs over the communicating portion97of the electrode plate95and then extends over the electrode plate93with a predetermined clearance at the same height (the same layer) as that of the electrode plate95, and a distal end of the high step portion99projects as an external connection portion100laterally from the base portion92to be exposed. The electrode plate93similarly includes a communicating portion65in a region overlapped by the communicating portion97of the electrode plate95, and has a slit67in a main portion66overlapped by the high step portion99of the electrode plate94. The slit67has a narrow width, and the high step portion99of the electrode plate94extends with a width over the slit67. The communicating portion65of the electrode plate93and the communicating portion97of the electrode plate95are bent perpendicularly upward with a clearance therebetween maintained respectively at one-end sides (here, the side of the extending portion98d) to extend upward from the base portion92, and are then bent as external connection portions68and69in mutually opposite directions and parallel to the communicating portions65and97. In terms of a phase (for example, a u-phase) of the inverter circuit101, on the main portion66of the electrode plate93located on a bottom surface of the base portion92, one set each of semiconductor devices (IGBTs)1pand FWDs70p, a total of two sets, are bonded, across the high step portion99of the electrode plate94(94u), by solder that is a conductive bonding material on both sides along the high step portion99. Similarly, also on the low step portion96of the electrode plate94in the bottom surface of the base portion92, in a region enclosed in a U-shape by the communicating portion97and the extending portions98(98aand98b) of the electrode plate95, one set each of semiconductor devices (IGBTs)1nand FWDs70nare bonded by solder along the respective extending portions. Further, at an opening side in the region enclosed in an U-shape near the electrode plate94u, gate terminals102nand sense emitter terminals103nare molded on the base portion92in a manner corresponding to the sets of the semiconductor devices1nand the FWD70n. On a side opposite to the communicating portion65near the electrode plate93, gate terminals102pand sense emitter terminals103pare molded on the base portion92in a manner corresponding to the sets of the semiconductor devices1pand the FWD70p. The semiconductor device1uses its solder bonded surface as a collector, and the main emitter electrode6on an upper surface of the semiconductor device1plocated on the electrode plate93is connected to the high step portion99of the electrode plate94uby a plurality of metal wires W1. Also, the gate wiring7on the upper surface of the semiconductor device1pis connected with the gate terminal102pby a metal wire W3. Also, the sense emitter electrode8on the upper surface of the semiconductor device1is connected with the sense emitter terminal103pby a metal wire W4. The FWD70uses its solder bonded surface as a cathode, and an anode electrode on an upper surface thereof is connected to the high step portion99by a plurality of metal wires W2. The main emitter electrode6on an upper surface of the semiconductor device1nlocated on the metal electrode plate94uis connected to the extending portion98(98a,98b) of the electrode plate95by a plurality of metal wires W1, and the gate wiring7is connected with a gate terminal102nby a metal wire W3, and the sense emitter electrode8is connected with a sense emitter terminal103nby a metal wire W4. Also, the anode electrode at an upper surface of the FWD70nis connected to the extending portion98by a plurality of metal wires W2. The same applies to other phases, and the inverter circuit101shown inFIG.17is thereby formed. In addition,FIG.17is an illustration in which a circuit configuration of a sense emitter is omitted. The external connection portion68of the electrode plate93serves as a P terminal of circuit input, and the external connection portion69of the electrode plate95serves as an N terminal, and the respective external connection portions100of the electrode plates94(94u,94v, and94w) serve as output terminals U, V, and W. The input/output terminals are further connected to a bus bar or high-current cable (not shown) in an inverter device. Also, the gate terminals102pand102nand the sense emitter terminals103pand103nare connected to, for example, a drive signal output terminal (not shown) of a drive signal control board that is attached onto the base portion92of the semiconductor module91. In corner portions of the base portion92, middle portions between the high step portions99, and near distal ends of the extending portions98, screw holes104are provided to make screws105for fixing the semiconductor module91to a heat sink (not shown) insertable therethrough. In the electrode plate93and the low step portions96of the electrode plates94, cut-aways106and107are formed so as to have a predetermined clearance with the screw hole104, and an inner wall of the screw holes104is provided as a molding resin so as to be insulated from the screw105. Also, in a central portion of the semiconductor module91, screw through-holes108are provided in the high step portions99of the electrode plates94and the overlapping part of the communicating portions97and65of the electrode plates95and93to make screws105insertable therethrough, which is the same as with a peripheral portion. Also around the screw through-holes108, in the high step portions99and the communicating portions65and97, holes that are larger in diameter than the screw through-holes108are formed, and an inner wall of the screw through-holes108is provided as a molding resin so as to be insulated from the screw105. Although preferred embodiments of the present invention have been described above, the present invention can be embodied in other forms. For example, an arrangement may be adopted in which the conductivity type of each semiconductor part of the semiconductor device1is inverted. That is, in the semiconductor device1, the p-type parts may be n-type and the n-type parts may be p-type. Also, in the foregoing preferred embodiment, the difference between the resistance value Rg1of the ON-side resistance wiring39and the resistance value Rg2of the OFF-side resistance wiring40is provided by the lengths Lonand Loffof the resistance wirings39and40, however, a relationship of Rg1<Rg2may be provided by making the width Wonof the ON-side resistance wiring39wider than the width Woffof the OFF-side resistance wiring40. Also, in the foregoing preferred embodiment, only the arrangement of the IGBT included in the semiconductor device1is illustrated, however, a semiconductor device of the present invention may include elements other than the IGBTs (for example, MOSFETs, diodes, and the like) in a region different from a region where the IGBTs are formed. Also, in the foregoing preferred embodiment, only the form of an IGBT having a trench gate structure is mentioned, however, the present invention can also be applied to an IGBT having a planar gate structure. In this case, it suffices to provide an ON-side resistance electrode (wiring) having a relatively wide width and an OFF-side resistance electrode (wiring) having a relatively narrow width compared to that of the ON-side resistance electrode by becoming creative with the pattern of a gate electrode to be formed on the semiconductor substrate2. The semiconductor device of the present invention can be incorporated in, for example, a power module for use in an inverter circuit that constitutes a drive circuit for driving an electric motor available as a power source for an electric vehicle (including a hybrid vehicle), an electric train, an industrial robot, and the like (for example, the semiconductor module91and the like inFIG.15andFIG.16). Additionally, the semiconductor device of the present invention can also be incorporated in a power module for use in an inverter circuit that converts electric power generated by a solar cell, a wind power generator, and other power generators (particularly, private electric generators) so as to be matched with electric power from commercial power sources. Various other design modifications can be made within the scope of the matters described in the claims. | 56,210 |
11942532 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments of the present disclosure are discussed in the context of forming a semiconductor device. In some embodiments, a coating layer is deposited on a first region and a second region. The coating layer is deposited under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. Processing gas is applied to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region. Depositing a coating layer over regions of a semiconductor device can cause loading, where the height of the coating layer depends on the density of underlying structures in different regions of the device. Loading contributes to lower device yields, increased defect counts, leakages, and damage to device sublayers, and in the case of FinFET devices, fin top damage. Applying a processing gas to the coating layer such that a height of the coating layer is the same different regions of the device eliminates loading problems, thus reducing device defects and sublayer damage, and increasing yield. FIG.1illustrates a perspective view of an example semiconductor device100, in accordance with various embodiments.FIG.1is provided as a reference to illustrate a number of cross-sections in subsequent figures. For example, cross-section Y-Y extends along a longitudinal axis of the trench1000. Cross-section X-X is perpendicular to cross-section Y-Y and is along a longitudinal axis of the fins404. A long axis of the interlevel dielectric structures1010extends along the Y-Y direction. The fins404also extend upward from the substrate302. Subsequent figures refer to these reference cross-sections for clarity. FIGS.2A-2Billustrate a flowchart of a method200to form a semiconductor device300, according to one or more embodiments of the present disclosure. For example, at least some of the operations of the method200can be used to form a FinFET device (e.g., FinFET device100), a nano-sheet transistor device, a nanowire transistor device, a vertical transistor, or the like. It is noted that the method200is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method200ofFIGS.2A-2B, and that some other operations may only be briefly described herein. In some embodiments, operations of the method200may be associated with cross-sectional views of an example FinFET device at various fabrication stages as shown inFIGS.3-21, respectively, which will be discussed in further detail below. In brief overview, the method200starts with operation202of providing a substrate. The method200continues to operation204of forming fins. The method200continues to operation206of forming isolation regions. The method200continues to operation208of forming a dummy gate structure. The method200continues to operation210of forming sidewall gate spacers. The method200continues to operation212of forming source/drain regions800. The method200continues to operation214of forming an interlayer dielectric (ILD). The method200continues to operation216of forming gate trenches. The method200continues to operation218of ILD structures arranged in first and second regions. The method200continues to operation220of forming a processing layer and a coating layer on the processing layer. The method200continues to operation222of performing a planarization etch. The method200continues to operation224of performing a conformal etch. The method200continues to operation226of performing a wet pull-back etch. The method200continues to operation228of removing the coating layer. The method200continues to operation230of removing portion of gate dielectric. The method200continues to operation232of forming n-metal and glue layers. The method200continues to operation234of etching back n-metal and glue layers, and forming a tungsten layer. The method200continues to operation236of forming a dielectric layer above the tungsten layer. As mentioned above,FIGS.3-21each illustrates, in a cross-sectional view, a portion of a semiconductor device300at various fabrication stages of the method200ofFIGS.2A-2B. AlthoughFIGS.3-21illustrate the semiconductor device300, it is understood the semiconductor device300may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are not shown inFIGS.3-21, for purposes of clarity of illustration.FIGS.3-6illustrate cross-sectional views of the device300along cross-section Y-Y (as indicated inFIG.1); andFIGS.7-21illustrate cross-sectional views of the device300along cross-section X-X (as indicated inFIG.1). Corresponding to operation202ofFIG.2A,FIG.3is a cross-sectional view of the semiconductor device300including a semiconductor substrate302at one of the various stages of fabrication. The substrate302may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate302may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate302may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Corresponding to operation204ofFIG.2A,FIG.4is a cross-sectional view of the semiconductor device300including (semiconductor) fins404at one of the various stages of fabrication. Although two fins are shown in the illustrated embodiment ofFIG.4(and the following figures), it should be appreciated that the semiconductor device300can include any number of fins while remaining within the scope of the present disclosure. In some embodiments, the fins404are formed by patterning the substrate302using, for example, photolithography and etching techniques. For example, a mask layer, such as a pad oxide layer and an overlying pad nitride layer, may be formed over the substrate302. The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. The patterned mask layer is subsequently used to pattern exposed portions of the substrate302to form trenches (or openings)411, thereby defining fins404between adjacent trenches411as illustrated inFIG.4. In some embodiments, the fins404are formed by etching trenches in the substrate302using, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or combinations thereof. The etching may be anisotropic. In some embodiments, the trenches411may be strips (viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches411may be continuous and surround the fins404. The fins404may be patterned by any suitable method. For example, the fins404may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin. Corresponding to operation206ofFIG.2,FIG.5is a cross-sectional view of the semiconductor device300including isolation regions500at one of the various stages of fabrication. The isolation regions500, which are formed of an insulation material, can electrically isolate neighboring fins404from each other. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or combinations thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or combinations thereof. Other insulation materials and/or other formation processes may be used. In the illustrated embodiment, the insulation material is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. A planarization process, such as a chemical mechanical polish (CMP), may remove any excess insulation material and form top surfaces of the isolation regions500and top surfaces of the fins404that are coplanar (not shown, the isolation regions500will be recessed as shown inFIG.5). The patterned mask may also be removed by the planarization process. In some embodiments, the a liner, e.g., a liner oxide (not shown), may be provided at the interface between each of the isolation regions500and the substrate302(fins404). In some embodiments, the liner oxide is formed to reduce crystalline defects at the interface between the substrate302and the isolation region500. Similarly, the liner oxide may also be used to reduce crystalline defects at the interface between the fin404and the isolation region500. The liner oxide (e.g., silicon oxide) may be a thermal oxide formed through a thermal oxidation of a surface layer of the substrate302, although other suitable methods may also be used to form the liner oxide. Next, the isolation regions500are recessed to form shallow trench isolation (STI) regions500, as shown inFIG.5. The isolation regions500are recessed such that the upper portions of the fins404protrude from between neighboring STI regions500. Respective top surfaces of the STI regions500may have a flat surface (as illustrated), a convex surface, a concave surface (such as dishing), or combinations thereof. The top surfaces of the STI regions500may be formed flat, convex, and/or concave by an appropriate etch. The isolation regions500may be recessed using an acceptable etching process, such as one that is selective to the material of the isolation regions500. For example, a dry etch or a wet etch using dilute hydrofluoric (DHF) acid may be performed to recess the isolation regions500. FIGS.3through5illustrate an embodiment of forming one or more fins (such as fins404), but a fin may be formed in various different processes. For example, a top portion of the substrate302may be replaced by a suitable material, such as an epitaxial material suitable for an intended type (e.g., N-type or P-type) of semiconductor devices to be formed. Thereafter, the substrate302, with epitaxial material on top, is patterned to form the fin404that includes the epitaxial material. As another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form one or more fins. In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form one or more fins. In embodiments where epitaxial material(s) or epitaxial structures (e.g., the heteroepitaxial structures or the homoepitaxial structures) are grown, the grown material(s) or structures may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in an NMOS region different from the material in a PMOS region. In various embodiments, the fins404may include silicon germanium (SixGe1-x, where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Corresponding to operation208ofFIG.2A,FIG.6is a cross-sectional view of the semiconductor device300including a dummy gate structure600at one of the various stages of fabrication. The dummy gate structure600may include a dummy gate dielectric602and a dummy gate604, in some embodiments. A mask may be formed over the dummy gate structure600. To form the dummy gate structure600, a dielectric layer may be formed on the fins404. The dielectric layer may be, for example, silicon oxide, silicon nitride, multilayers thereof, or the like, and may be deposited or thermally grown. A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like. After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using acceptable photolithography and etching techniques to form the mask. The pattern of the mask then may be transferred to the gate layer and the dielectric layer by an acceptable etching technique to form the dummy gate604and the underlying dummy gate dielectric602, respectively. The dummy gate604and the dummy gate dielectric602cover a central portion (e.g., a channel region) of the fins404. The dummy gate604may also have a lengthwise direction (e.g., direction Y-Y ofFIG.1) substantially perpendicular to the lengthwise direction (e.g., direction of X-X ofFIG.1) of the fins404. The dummy gate dielectric602is shown to be formed over the fins404(e.g., over top surfaces and sidewalls of the fins404) and over the STI regions500in the example ofFIG.6. In other embodiments, the dummy gate dielectric602may be formed by, e.g., thermal oxidization of a material of the fin404, and therefore, may be formed over the fins404but not over the STI regions500. It should be appreciated that these and other variations are still included within the scope of the present disclosure. FIGS.7-21illustrate the cross-sectional views of further processing (or making) of the semiconductor device300along cross-section X-X (along a longitudinal axis of the fins404), as shown inFIG.1. In brief overview, three dummy gate structures600are illustrated over a fin404in the examples ofFIGS.7-10. It should be appreciated that more or less than three dummy gate structures can be formed over the fins404, while remaining within the scope of the present disclosure. Corresponding to operation210ofFIG.2A,FIG.7is a cross-sectional view of the semiconductor device300including sidewall gate spacers700formed on the sidewalls of the dummy gate structures600at one of the various stages of fabrication. Referring toFIG.7, in some embodiments, sidewall gate spacers700are formed around (e.g., along and contacting the sidewalls of) the dummy gate structures600. The sidewall gate spacers700may a single layer or may be formed of multiple layers. It should be understood that any number of gate spacers can be formed around the dummy gate structures600while remaining within the scope of the present disclosure. The sidewall gate spacers700may each include a first gate spacer702and a second gate spacer704, for example. The first gate spacer702may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. The second gate spacer704may be formed of a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), or the like, may be used to form the first gate spacer702and the second gate spacer704. In accordance with various embodiments, the first gate spacer702and the second gate spacer704are formed of different materials to provide etching selectivity in subsequent processing. The first gate spacer702and the second gate spacer704may sometimes be collectively referred to as gate spacers702/704. The shapes and formation methods of the gate spacers702/704as illustrated inFIG.7(and the following figures) are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure. Corresponding to operation212ofFIG.2A,FIG.8is a cross-sectional view of the semiconductor device300including a number of source/drain regions800at one of the various stages of fabrication. The source/drain regions800are formed in recesses of the fins404adjacent to the dummy gate structures600. For example, the source/drain regions800and the dummy gate structures600are alternately arranged. In other words, one source/drain region800is sandwiched between adjacent dummy gate structures600and/or merely one side of the source/drain region800is disposed next to a dummy gate structure600. The recesses are formed by, e.g., an anisotropic etching process using the dummy gate structures600as an etching mask, in some embodiments, although any other suitable etching process may also be used. The source/drain regions800are formed by epitaxially growing a semiconductor material in the recess, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. As illustrated inFIG.8, the epitaxial source/drain regions800may have surfaces raised from respective surfaces of the fin404(e.g. raised above the non-recessed portions of the fin404) and may have facets. In some embodiments, the source/drain regions800of the adjacent fins may merge to form a continuous epitaxial source/drain region (not shown). In some embodiments, the source/drain regions800of the adjacent fins may not merge together and remain separate source/drain regions800(not shown). In some embodiments, when the resulting semiconductor device is an n-type FinFET, the source/drain regions800can include silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), or the like. In some embodiments, when the resulting semiconductor device is a p-type FinFET, the source/drain regions800comprise SiGe, and a p-type impurity such as boron or indium. The epitaxial source/drain regions800may be implanted with dopants to form source/drain regions800followed by an annealing process. The implanting process may include forming and patterning masks such as a photoresist to cover the regions of the semiconductor device300that are to be protected from the implanting process. The source/drain regions800may have an impurity (e.g., dopant) concentration in a range from about 1×1019cm−3to about 1×1021cm−3. P-type impurities, such as boron or indium, may be implanted in the source/drain region800of a P-type transistor. N-type impurities, such as phosphorous or arsenide, may be implanted in the source/drain regions800of an N-type transistor. In some embodiments, the epitaxial source/drain regions800may be in situ doped during their growth. Corresponding to operation214ofFIG.2A,FIG.9is a cross-sectional view of the semiconductor device300including an interlayer dielectric (ILD)900at one of the various stages of fabrication. In some embodiments, prior to forming the ILD900, a contact etch stop layer (CESL)902is formed over the structure illustrated inFIG.9. The CESL902can function as an etch stop layer in a subsequent etching process, and may comprise a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be formed by a suitable formation method such as CVD, PVD, combinations thereof, or the like. Next, the ILD900is formed over the CESL902and over the dummy gate structures600. In some embodiments, the ILD900is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. An example gate-last process (sometimes referred to as replacement gate process) is performed subsequently to replacing the dummy gate604and the dummy gate dielectric602of each of the dummy gate structures600with an active gate (which may also be referred to as a replacement gate or a metal gate). Corresponding to operation216ofFIG.2A,FIG.10is a cross-sectional view of the semiconductor device300in which the dummy gate structures600(FIG.9) are removed to form respective gate trenches1000, at one of the various stages of fabrication. Next, upper portions of the gate trenches1000are horizontally expanded by removing relative upper portions of the gate spacers700, such that each of the gate trenches1000has an upper trench1000U and a lower trench1000L, where the upper trench1000U is wider than the lower trench1000L horizontally. Details of forming the gate trenches1000will be discussed below. In some embodiments, to remove the dummy gate structures600, one or more etching steps are performed to remove the dummy gate604and the dummy gate dielectric602directly under the dummy gate604, so that the gate trenches1000(which may also be referred to as recesses) are formed between respective gate spacers700. Each gate trench1000exposes the channel region of a fin404. During the dummy gate removal, the dummy gate dielectric602may be used as an etch stop layer when the dummy gate604is etched. The dummy gate dielectric602may then be removed after the removal of the dummy gate604. Next, an anisotropic etching process, such as a dry etch process, is performed to remove upper portions of the gate spacer700. In some embodiments, the anisotropic etching process is performed using an etchant that is selective to (e.g., having a higher etching rate for) the material of the first gate spacer702, such that the first gate spacer702is recessed (e.g., upper portions removed) without substantially attacking the second gate spacer704and the dielectric layer904. After the upper portions of the first gate spacers702are removed, upper sidewalls of the second gate spacer704are exposed. In some embodiments, upper sidewalls of the second gate spacer704may also be removed. As illustrated inFIG.10, after the upper portions of the first gate spacers702, and in some embodiments upper portions of the second gate spacers704, are removed, each of the gate trenches1000has an upper trench1000U and a lower trench1000L. The lower trench1000L is between the remaining lower portions of the first gate spacer702. The upper trench1000U is over the lower trench1000L, and is defined (e.g., bordered) by the upper sidewalls of the second gate spacer704, if the upper sidewalls of the second gate spacer704are not removed. The width of the upper trench1000U may be between 3 and 30 nm. Corresponding to operation218ofFIG.2A,FIG.11illustrates ILD structures1010where some of the ILD structures1010are arranged in a first region1100A and others of the ILD structures1010are arranged in a second region1100B. The ILD structures1010may include the features as shown inFIG.10such as the gate spacers700and ILD900. Thus, first ILD structures of the ILD structures1010with first trenches between are arranged in the first region1100A, while second ILD structures of the ILD structures1010with second trenches between are arranged in the second region1100B. As discussed above, the ILD structures1010include the ILD900and the remaining sidewall spacer700. The trenches1000between adjacent ILD structures1010include an upper trench1000U, which is wider than a lower trench1000L. The trenches1000in the first region1100A may be narrower than at least some of the trenches1000in the second region1100B, such that the density of the ILD structures1010is greater in the first region1100A than in the second region1100B. This difference in density may cause a loading effect when a coating layer1200(FIG.12) is deposited on the semiconductor device, thus reducing a height of the coating layer1200in the second region1100B as compared to a height of the coating layer1200in the first region1100A.FIG.11illustrates four ILD structures1010in the first region1100A and three ILD structures1010in the second region1100B for the sake of illustration. The number of ILD structures1010in the first region1100A and second region1100B, however, may be other than four and three, respectively. Corresponding to operation220ofFIG.2A,FIG.12illustrates the formation of a processing layer1202on sidewalls of the ILD structures1010, and then formation of a coating layer1200on the processing layer1202. The processing layer1202may be a single layer, or may have multiple sub-layers. The processing layer1202may be etched or otherwise processed upon sufficient of the coating layer1200being removed to expose the processing layer1202. The processing layer1202may include, for example, a gate dielectric layer1204on sidewalls of the ILD structures1010, and a p-metal (p-type work function metal) layer1206, as a work function metal layer, on the gate dielectric1204. The processing layer1202may include in general, different types of material, such as conductors, semiconductors, and insulating materials. In example embodiments, the gate dielectric layer1204includes a high-k dielectric material, and in these embodiments, the gate dielectric layers1204may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of gate dielectric layer1204may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. Next, the p-metal layer1206is formed (e.g., conformally) over the gate dielectric layer1204. Example P-type work function metals that may be included as the p-metal layer1206include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. The p-metal layer1206may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process. The coating layer1200may be formed as a photoresist layer, and may additionally or alternatively include a bottom antireflection coating (BARC). The BARC may be an organic thermally crosslinking material, for example. The photoresist and BARC may be spun on, deposited, or otherwise formed on and over the first region1100A and second region1100B. As can be seen inFIG.12, the height of the coating layer1200is greater in the first region1100A, which has a higher density of ILD structures1010than in the second region1100B due to loading. Corresponding to operation222ofFIG.2A,FIG.13illustrates a planarization etch where the coating layer1200is etched in such a manner that a height of a top surface of the coating layer1200in the first region1100A is the same as a height of a top surface of the coating layer1200in the second region1100B. As shown, the coating layer1200is etched such that its top surface is near a top surface of the ILD structures1010. The etch inFIG.13may be, for example, a dry etch under conditions that etching of the coating layer1200occurs at regions outside the trenches1000, but not substantially within the trenches, although some etching into the trenches1000may occur. In this regard, a planarization processing gas may be applied to the coating layer1200such that etching of the coating layer1200occurs substantially only at regions outside the trenches1000. The purpose of the etch is to reduce the difference in height of the coating layer1200in the first region1100A and the second region1100B. The dry etch may be performed in a plasma chamber, for example. The planarization processing gas may include an etching gas, which tends to etch the coating layer1200, and a deposition gas, which tends to deposit material. The planarization processing gas is applied to the coating layer1200in a composition and bias such that etching of the coating layer1200occurs only at regions outside the trenches1000. The etching stops in the trenches1000due to heavy deposition, and thus processes the coating layer1200similar to chemical mechanical polishing, leaving the coating layer1200only in the trenches1000, thus removing coating loading between regions1100A and1100B. The deposition gas may include He, CH4or H2gas, for example, and the etch gas may include NH3, for example. As an example, the deposition gas may be CH4and the etch gas may include NH3. The NH3flow may be between 50 and 200 sccm. An Ar gas may have a flow between 100 and 400 sccm. The CH4flow may be between 100 and 300 sccm. The pressure range may be between 50 and 200 mT. The plasma power range may be between 50 and 300 W. Corresponding to operation224ofFIG.2A,FIG.14illustrates the coating layer1200being etched in a conformal etch in such a manner to remove the coating layer1200from the upper trench1000U, and to leave the coating layer1200in lower trench1000L both in the first region1100A and in the second region1100B. In the conformal etch, the coating layer1200is etched such that its top surface is near the interface between the upper trench1000U and the lower trench1000L, and the coating layer1200has a substantially same height in the first region1100A and in the second region1100B. The height difference may be 0 to 10 nm, for example. The etch inFIG.14may be, for example, a dry etch under conditions that etching of the coating layer1200removes the coating layer1200from the upper trench1000U, and leaves the coating layer1200in lower trench1000L. In this regard, a conformal etch processing gas may be applied to the coating layer1200such that etching of the coating layer1200removes the coating layer1200from the upper trench1000U, and leaves the coating layer1200in lower trench1000L. The dry etch may be performed in a plasma chamber, for example. The processing gas for the conformal etch may include an etching gas, which tends to etch the coating layer1200, and a deposition gas, which tends to deposit material. The processing gas for the conformal etch is applied to the coating layer1200in a composition and bias such that etching of the coating layer1200removes the coating layer1200from the upper trench1000U, and leaves the coating layer1200in lower trench1000L. For the conformal etch, the deposition gas may include He, CH4, CxFy, Cl, HBr, BCl, H2, or Ar gas, for example, and the etch gas may include NH3and N2, for example. As an example of the conformal etch, the etch gas may include NH3and N2. The NH3may have a flow between 50 and 200 sccm. The N2may have a flow between 300 and 1000 sccm. The pressure range may be between 50 and 200 mT. The plasma power range may be between 50 and 300 W. Corresponding to operation226ofFIG.2A,FIG.15illustrates an etch of the p-metal layer1206being etched in regions exposed by the conformal etch described with respect toFIG.14. In particular the p-metal layer1206is exposed in the upper trench1000U, but not in the lower trench1000L in which the coating layer1200remains. The p-metal layer1206is etched to remove the p-metal layer1206from the upper trench1000U. The p-metal layer1206may be etched for example in a wet pull-back etch process, which is selective to etching the p-metal layer1206over the gate dielectric layer1204. WhileFIG.15illustrates an etch which etches the p-metal layer1206, but does not etch the gate dielectric layer1204, the metal layer1206and the gate dielectric layer1204may be etched in the same step. The p-metal layer1206may be etched in a wet etch process. The wet etch process may be performed using a chemical comprising a base and an oxidizer, in some embodiments. For example, the chemical used may be a mixture of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), where NH4OH functions as the base and H2O2functions as the oxidizer. In some embodiments, a mixing ratio (e.g., volume ratio) between NH4OH and H2O2is between about 1:1 and 1:2001 for the wet etch process. The wet etch process may be performed at a temperature between about 40° C. and about 70° C. for a duration between about 1 minute and about 5 minutes, or else may be ended using an endpoint detection process. Corresponding to operation228ofFIG.2A,FIGS.16and17illustrates the removal of the coating layer1200after the wet etch ofFIG.15. The etchant for removing the coating layer1200depends on the material for the coating layer1200. For example, if the coating layer1200includes a photoresist and a BARC, the coating layer1200may be removed using an ashing process which exposes the coating layer1200to oxygen. FIG.17illustrates a portion of the semiconductor device300with two ILD structures1010with a trench1000between the two ILD structures1010. Only two ILD structures1010with a trench1000between are shown inFIGS.17-21for the sake of simplicity. In general, the device300will have more than two ILD structures1010, and corresponding trenches. Corresponding to operation230ofFIG.2A,FIG.18illustrates the removal of a portion of the gate dielectric layer1204which is in the upper trench1000U. Alternatively, the gate dielectric layer1204may be etched in the etch ofFIG.15. The portion of the gate dielectric layer1204may be removed by a wet etch process using a wet etching solution. The wet etching solution may include an etchant and an oxidant placed into a solvent, for example. For example, the etchant may be an amine with a formula such as R—NH2, R—N—R′, NR1R2R3, combinations of these, or the like, wherein each of R, R′, R1, R2and R3may be an alkyl group, a phenyl group, or the like. In other embodiments the etchant may be an amine such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), tetrabutylammonium hydroxide (TBAH), combinations of these, or the like. However, any suitable etchant may be utilized. In some embodiments, the oxidant may be a mixture of the fluoride-based acid with one or more other acids such as, for example, perchloric acid (HClO4), chloric acid (HClO3), hypochlorous acid (HClO), chlorous acid (HClO2), metaperiodic acid (HIO4), iodic acid (HIO3), iodous acid (HIO2), hypoiodous acid (HIO), perbromic acid (HBrO4), bromic acid (HBrO3), bromous acid (HBrO2), hypobromous acid (HBrO), nitric acid (HNO3), combinations of these, or the like. However, any suitable oxidant may be utilized. Corresponding to operation232ofFIG.2B,FIG.19illustrates the formation of an n-metal (n-type work function metal) layer1900and a glue layer1910on the interlevel dielectric structure1010, and the p-metal layer1206. The n-metal layer1900may be formed (e.g., conformally) over the interlevel dielectric structure1010, and the p-metal layer1206. Example n-metal layers1900that may be included are Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The n-metal layer1900may be deposited by CVD, PVD, ALD, and/or other suitable process. Next, the glue layer1910is formed (e.g., conformally) on the n-metal layer1900. The glue layer1910functions as an adhesion layer between the underlying layer (e.g.,1900) and a subsequently formed material (e.g.,2000) over the glue layer1910. The glue layer1910may be formed of a suitable material, such as titanium nitride, using a suitable deposition method such as CVD, PVD, ALD, or the like. Depending on the width of the lower trench1000L and the thicknesses of the previously formed layers in the trenches, the glue layer1910may fill the remaining portions of the lower trench1000L, as illustrated in the example ofFIG.19. Further, depending on the width of the upper trench1000U, the width of the lower trench1000L, and the thicknesses of the previously formed layers in the gate trenches, the glue layer1910may fill the whole trench1000. Corresponding to operation234ofFIG.2B,FIG.20illustrates the etchback of the n-metal layer1900and the glue layer1910on the interlevel dielectric structure1010, and the formation of a tungsten layer2000on the etched back n-metal layer1900and glue layer1910. In some embodiments, a portion of the glue layer1910is removed from the upper trench1000U of the trench1000by a glue layer pull-back process. In some embodiments, a wet etch process is performed as the glue layer pull-back process to selectively remove the glue layer1910from the upper trench1000U without attacking (e.g., damaging, removing) the underlying layer (e.g., the n-metal layer1900). The wet etch process is performed using a chemical including an acid and an oxidizer, in some embodiments. For example, the chemical used may be a mixture of hydrochloric acid (HCl) and hydrogen peroxide (H2O2), where HCl functions as the acid and H2O2functions as the oxidizer. In some embodiments, a mixing ratio (e.g., volume ratio) between HCl and H2O2is between about 1:1 and 1:20 for the wet etch process. The wet etch process may be performed at a temperature between about 40° C. and about 70° C. for a duration between about 1 minute and about 5 minutes, or else may be ended using an endpoint detection process. As illustrated inFIG.20, after the glue layer1910pull-back process, at least a portion of the n-metal layer1900is exposed in the upper trench1000U, and a remaining portion of the glue layer1910still fills the lower trench1000L. The n-metal layer1900is exposed in the upper trench1000U, but not in the lower trench1000L, and exposed portions of the n-metal layer1900may be etched in a wet etch, for example. The n-metal layer1900is etched to remove the n-metal layer1900from the upper trench1000U. The n-metal layer1900may be etched for example in a wet pull-back etch process. The wet etch process may be performed using a chemical comprising a base and an oxidizer, in some embodiments. For example, the chemical used may be a mixture of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), where NH4OH functions as the base and H2O2functions as the oxidizer. In some embodiments, a mixing ratio (e.g., volume ratio) between NH4OH and H2O2is between about 1:1 and 1:2001 for the wet etch process. The wet etch process may be performed at a temperature between about 40° C. and about 70° C. for a duration between about 1 minute and about 5 minutes, or else may be ended using an endpoint detection process. A tungsten layer2000may be formed on the n-metal layer1900and the glue layer1910, for example, by PVD or CVD. The tungsten layer2000may be formed to directly contact the n-metal layer1900and the glue layer1910. Corresponding to operation236ofFIG.2B,FIG.21illustrates the formation of a dielectric layer2100formed in the trench1000above the tungsten layer2000. The dielectric layer2100(e.g., silicon oxide, silicon nitride, a low-k dielectric material, or the like) is formed in the trench1000, using a suitable formation method such as PVD, CVD, or the like. According to some embodiments, and as shown inFIG.21, the formation and etching of the p-metal layer1206, the gate dielectric layer1204, and the n-metal layer1900may be such that a top portion of the p-metal layer1206is below a top portion of the gate dielectric layer1204, and the n-metal layer1900. In this case, the gate dielectric layer1204may contact sidewalls of a respective of the interlevel dielectric structures1010, the p-metal layer may contact an inner sidewall of the gate dielectric layer1204, and the n-metal layer1900may contact an inner sidewall of the p-metal layer1206, wherein a top portion of the n-metal layer1900is above a top portion of the p-metal layer1206. According to some embodiments, the top portion of the n-metal layer1900may be directly above a top portion of the p-metal layer1206. In one aspect of the present disclosure, a method of manufacturing a semiconductor device is disclosed. The method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. A processing gas is applied to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region. In yet another aspect of the present disclosure, a method of making semiconductor device is disclosed. A coating layer is deposited on a first region and a second region under a loading condition such that a first portion in the first region and a second portion in the second region have a height difference. The first region has a first trench with a first upper portion and a first lower portion. The second region has a second trench with a second upper portion and a second lower portion. The first upper portion is wider than the first lower portion and the second upper portion id wider than the second lower portion. A deposition gas and an etch gas are applied to the coating layer to remove an upper portion of the coating layer to reduce the height difference. The coating layer is removed from the first and second upper portions, but not the first and second lower portions. In yet another aspect of the present disclosure, a method of making semiconductor device is disclosed. A coating layer is deposited on a first region and a second region under a loading condition such that a first portion in the first region and a second portion in the second region have a height difference. The first region has a first trench with a first upper portion and a first lower portion. The second region has a second trench with a second upper portion and a second lower portion. The first upper portion is wider than the first lower portion and the second upper portion id wider than the second lower portion. A deposition gas and an etch gas are applied to the coating layer to remove an upper portion of the coating layer to reduce the height difference. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 45,949 |
11942533 | Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein. The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures. The present disclosure provides example multi-Vt devices (e.g., semiconductor device100ofFIG.1A) with FETs (e.g., finFETs or GAA FETs) having an improved channel structure configurations. A substantially uniform germanium (Ge) cladding layer wrapped around the silicon (Si) channel layer is critical for Ge tuning pFET Vth in scaled down advanced device structures (e.g. finFETs, nanowire, nanosheet). The present disclosure provides a thin uniform Ge cladding layer, which thickness is less than about 2 nm or less than about 1 nm. One method to form a Ge cladding layer is by ion implanting Ge atoms in a Si channel. Such method does not require extra volume/thickness for adding the Ge cladding layer, but may only be feasible for planar device structures. The Ge ion implantation process may not be feasible in scaled down device structures, such as three-dimensional (3D) nanosheets, nanowires, and finFET structures, due to pattern geometry shadowing. Another method to form a Ge cladding layer is by directly inserting a SiGe cladding layer covering a Si channel layer at a sheet formation stage. A Ge epitaxial growth by a chemical vapor deposition (CVD) process can form the cladding layer at certain thicknesses (e.g., larger than 5 nm), which may not accommodate scaled down device structures, such as 3D nanosheets, nanowires, and finFET structures. Embodiments of the present disclosure provide methods to form a thin uniform Ge cladding layer for scaled down device structures, such as 3D nanosheets, nanowires, and finFET structures. The embodiments described herein are not constrained by pattern geometry by using reduced pressure CVD tools at specific design process conditions. In some embodiments, a Ge treatment less than about 1300 seconds is performed at a process temperature of about 450° C., using germane (GeH4) as a Ge reacting gas, and at a partial pressure (pp) of about 4 mTorr and a reactor chamber total pressure less than about 30 Torr, to epitaxially grow a Ge layer on the surfaces of a Si channel layer. An annealing process can then be performed at about 500° C. to about 800° C. in hydrogen (H2) ambient for silicon-germanium (SiGe) alloying and Ge atom thermal diffusion into the Si channel layer. As a result, an ultra-thin (e.g., thickness less than 1 nm) Ge or GeSi cladding layer can be formed on the Si channel layer. In some embodiments, a Ge treatment followed by an annealing process can be cyclically repeated to avoid uncontrolled Ge island-to-island mergers in scaled down device structures which can cause device performance failure. Each cycle of Ge treatment can be performed in a time duration to form a Ge layer with a thickness less than a critical thickness of a Ge epitaxial growth from 2D to 3D. Each cycle of annealing process can be performed for surface Ge atom redistribution and diffusion. The cycles of Ge treatment and annealing process can be repeated until the formed Ge/GeSi cladding layer reaches a desired thickness and/or the surface Ge composition reaches a desired percentage, according to some embodiments. FIG.1Aillustrates an isometric view of a semiconductor device100, according to some embodiments.FIG.1Billustrates a cross-sectional view of a FET102of semiconductor device100along line A-A′ with additional structures that are not shown inFIG.1Afor simplicity.FIG.1Cillustrates a cross-sectional view of FET102of semiconductor device100along line B-B′ with additional structures that are not shown inFIG.1Afor simplicity. The discussion of elements inFIGS.1A-1Cwith the same annotations applies to each other, unless mentioned otherwise. In some embodiments, FET102can represent an n-type FET (NFET) or a p-type FET (PFET) and the discussion of FET102applies to both NFET and PFET, unless mentioned otherwise. Referring toFIGS.1A-1C, semiconductor device100can include a plurality of FETs102. Semiconductor device100can include an array of gate structures112disposed on a fin structure108and an array of S/D regions110disposed on portions of fin structure108that are not covered by gate structures138. Semiconductor device100can further include gate spacers114, shallow trench isolation (STI) regions119, etch stop layers (ESLs)116, and interlayer dielectric (ILD) layers118. In some embodiments, gate spacers114, STI regions119, ESLs116, and ILD layers118can include an insulating material, such as silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide. In some embodiments, gate spacers114can have a thickness of about 2 nm to about 9 nm for adequate electrical isolation of gate structures138from adjacent structures. FET102of semiconductor device100can be formed on a substrate106. There may be other FETs and/or structures (e.g., isolation structures) formed on substrate106. Substrate106can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and a combination thereof. Further, substrate106can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, fin structure108can include a material similar to substrate106and extend along an X-axis. Referring toFIGS.1B and1C, cross-sectional views of FET102of semiconductor device100along line A-A′ (i.e., X-axis) and line B-B′ (i.e., Y-axis) are illustrated respectively. In some embodiments, as illustrated inFIG.1B, FET102of semiconductor device100can include (i) fin structure108on substrate106, (ii) stacks of channel structures122disposed on fin structure108, (iii) gate structure112disposed on and wrapped around respective channel structures122(iv) epitaxial S/D regions110disposed on portions of fin structure108that are adjacent to channel structures122, (v) S/D contact structures140disposed on epitaxial S/D regions110. As used herein, the term “nanostructure” or “nanostructured” defines a structure, layer, and/or region as having a horizontal dimension (e.g., along X- and/or Y-axis) and/or a vertical dimension (e.g., along Z-axis) less than, for example, 100 nm. In some embodiments, FET102can have fin regions (not shown) instead of nanostructured channel regions122. Such finFETs102can have gate structures112disposed on the fin regions. Fin structure108can be formed from substrate106and can extend along an X-axis. Epitaxial S/D regions110can be grown on fin structure108and can include epitaxially-grown semiconductor materials similar to or different from each other. In some embodiments, the epitaxially-grown semiconductor material can include the same material or a different material from the material of substrate106. Epitaxial S/D regions110can be n-type or p-type. As used herein, the term “p-type” defines a structure, layer, and/or region as being doped with p-type dopants, such as boron. As used herein, the term “n-type” defines a structure, layer, and/or region as being doped with n-type dopants, such as phosphorus. In some embodiments, n-type S/D regions110can include SiAs, SiC, or SiCP and p-type S/D regions110can include SiGe, SiGeB, GeB, SiGeSnB, a III-V semiconductor compound, any other suitable semiconductor material, or a combination thereof. In some embodiments, each of S/D contact structures140on an epitaxial S/D region110can include (i) a silicide layer140A and (ii) a contact plug140B disposed on silicide layer140A. In some embodiments, silicide layers140A can include nickel silicide (NiSi), tungsten silicide (WSi2), titanium silicide (TiSi2), cobalt silicide (CoSi2), or other suitable metal silicides. In some embodiments, contact plugs140B can include conductive materials, such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), Osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), stannum (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), other suitable conductive materials, and a combination thereof. In some embodiments, each nanostructured channel region122can include a channel layer120having semiconductor materials similar to or different from substrate106. For example, channel layer120can be an N type channel layer including Si, silicon arsenic (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), or other suitable semiconductor materials. As another example, channel layer120can be a P type channel layer including Si, silicon arsenic (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), or other suitable semiconductor materials. Each nanostructured channel region122can further include a cladding layer115having semiconductor materials different from channel layer120. In some embodiments, cladding layer115can be a thin film containing germanium (Ge) atoms, such as a Ge film and a SiGe alloy film. In some embodiments, a concentration of Ge atoms in cladding layer115can be in between about 10% and about 40%. The Ge atoms in cladding layer115can reduce pFET threshold voltages Vth. In some embodiments, cladding layer115can be a substantially uniform film located on both top and bottom surfaces of each channel layer120in an X-Z plane as shown inFIG.1B, and surrounding around each channel layer120in a Y-Z plane as shown inFIG.1C. In some embodiments, the Ge film or SiGe film115-1may also be formed on a top surface of fin structure108, as shown inFIGS.1C and1D. Though rectangular cross-sections of channel structures122are shown inFIG.1C, channel structures122can have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). For example, as illustrated inFIG.1D, channel structures122can have non-perfect rectangular cross-sections with rounded corners. In some embodiments, a width We of channel structures122in Y-direction can be in a range from about 5 nm to about 20 nm, a thickness Tc of channel structures122in Z-direction can be in a range from about 5 nm to about 10 nm. As described above, the Ge/SiGe film formed by inserting a SiGe cladding layer to cover Si channel has an undesired thickness larger than 4 nm, such as about 4 nm to about 5 nm. Such large thickness of Ge/SiGe film reduces the vertical distance between adjacent channels, resulting in narrow spaces for gate structures formed between the channels. The present disclosure provides methods for forming a substantially uniform cladding layer115with a thickness Te less than about 2 nm or even less than about 1 nm, as shown inFIG.1D. As a result, a distance Dc of channel structures122in Z-direction can be in a range from about 5 nm to about 10 nm, allowing sufficient space for forming a multi-layer gate structure between adjacent channel structures122. As illustrated inFIG.1C, in some embodiments, gate structures112can be multi-layered structures and can surround channel structures122, for which gate structures112can be referred to as “gate-all-around (GAA) structures” or “horizontal gate-all-around (HGAA) structures.” As illustrated inFIG.1B, gate portions112-1of gate structures112surrounding channel structures122can be electrically isolated from adjacent S/D regions110by inner spacers113. Gate portions112-2of gate structures112disposed on the stacks of channel structures122can be electrically isolated from adjacent S/D regions110by gate spacers114. Inner spacers113and gate spacers114can include an insulating material, such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and other suitable insulating materials. In some embodiments, gate lengths of gate structures112are substantially equal to each to other. Gate structures112can include (i) interfacial oxide (IO) layers127, (ii) high-k (HK) gate dielectric layers128, and (iii) gate metal fill layers138. As shown inFIGS.1B and1C, channel structures122can be wrapped around by IO layers127and HK gate dielectric layers128to fill the spaces between adjacent channel structures122. Accordingly, channel structures122can be electrically isolated from each other to prevent shorting between gate structures112and S/D regions110during operation of finFET102. IO layers127can be disposed on channel structures122. In some embodiments, IO layers127can include SiO2, silicon germanium oxide (SiGeOx), germanium oxide (GeOx), or other suitable oxide materials. HK gate dielectric layers128can be disposed on IO layers127and can include (i) a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and (ii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), (iii) a combination thereof, or (iv) other suitable high-k dielectric materials. As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2(e.g., greater than 3.9). In some embodiments, gate metal fill layers138can include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), other suitable conductive materials, and a combination thereof. In some embodiments, gate metal fill layers138can include a substantially fluorine-free metal layer (e.g., fluorine-free W). The substantially fluorine-free metal layer can include an amount of fluorine contaminants less than about 5 atomic percent in the form of ions, atoms, and/or molecules. FIG.2is a flow diagram of an example method200for fabricating FET102of semiconductor device100, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.2will be described with reference to the example fabrication process for fabricating FET102as illustrated inFIGS.3A-9B.FIGS.3A-9Bare cross-sectional views of FET102along lines A-A′ and B-B′ of semiconductor device100at various stages of fabrication, according to various embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method200may not produce a complete FET102. Accordingly, it is understood that additional processes can be provided before, during, and after method200, and that some other processes may only be briefly described herein. Elements inFIGS.3A-9Bwith the same annotations as elements inFIGS.1A-1Dare described above. In operation205, a superlattice structure can be formed on a fin structure of a FET, and a polysilicon structure can be formed on the superlattice structure. For example, as shown inFIGS.3A-3B, superlattice structure125can be epitaxially formed on fin structure108. Superlattice structure125can include nanostructured layers121and123arranged in an alternating configuration. In some embodiments, nanostructured layers121include materials similar to each other and nanostructured layers123include materials similar to each other. In some embodiments, nanostructured layers121can include any suitable crystallinity materials such as Si, SiGe, and group III-IV elements (e.g., GaAs, InP). In some embodiments, nanostructured layers121can include Si without any substantial amount of Ge (e.g., with no Ge) and nanostructured layers123can include SiGe. During subsequent processing, polysilicon structure312and nanostructured layers123can be replaced in a gate replacement process to form gate structures112. In some embodiments, polysilicon structure312can be formed on the top surface of superlattice structure125in an X-Z plane as shown inFIG.3A, and can be formed on the top surface and both sides of superlattice structure125and on shallow trench isolation (STI) regions119in a Y-Z plane as shown inFIG.3B. Referring toFIG.2, in operation210, S/D regions can be formed on the fin structure of FET. For example, as described with reference toFIGS.4A-5B, S/D regions110are formed on fin structure108and on both sides of superlattice structure125. S/D regions110can be either n-type S/D regions or and p-type S/D regions. The selective formation of S/D regions110can include sequential operations of (i) forming S/D openings410, through superlattice structure125, on portions of fin structure108that are not underlying polysilicon structures312, as shown inFIGS.4A-4B, and (ii) epitaxially growing n-type or p-type semiconductor materials within S/D openings410, as shown inFIGS.5A-5B. In some embodiments, inner spacers113can be formed between operations (i) and (ii) of the formation process of epitaxial S/D regions110P, as shown inFIG.4A. After the formation of S/D regions110, ESL116and ILD layer118can be formed on S/D regions110to form the structures ofFIGS.5A-5B. Referring toFIG.2, in operation215, gate openings are formed on and within the superlattice structure. For example, as shown inFIGS.6A-6B, gate openings412and422can be formed on and within superlattice structure125. The formation of gate openings412and422can include sequential operations of (i) forming a masking layer (not shown) on the structure ofFIGS.5A-5B, (ii) etching polysilicon structure312from the structure ofFIGS.5A-5B, (iii) etching nanostructured layers123from the structure ofFIGS.5A-5B, and (iv) removing the masking layer from the structure ofFIGS.5A-5B. Referring toFIG.2, in operation220, a plurality of channel structures are formed in the superlattice structure. Each channel structure can include a channel layer and a cladding layer. For example, as shown inFIGS.7A-7B, a cladding layer115can be formed on and/or within outer surfaces of nanostructured layers121that are exposed by gate openings412and422, and the remaining portions of nanostructured layers121that are wrapped by the formed cladding layers115can form channel layers120. In some embodiments, cladding layer115can be formed on the top and bottom surfaces of each channel layer120in an X-Z plane as shown inFIG.7A, and can be formed to surround each channel layer120in a Y-Z plane as shown inFIG.7B. In some embodiments, the plurality of channel structures can be formed by one or more Ge treatment processes, such as one or more Ge deposition processes and/or Ge doping processes. The process tools for the one or more Ge treatment processes can include furnace, physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and/or atomic layer deposition (ALD) tools. In the following descriptions in connection withFIGS.10-16D, CVD processes using reduced pressure CVD tools at specific design process conditions are used as examples to describe the details of the formation of channel structures120. Further details on embodiments of operation220are described below inFIGS.10and15. Referring toFIG.2, in operations225-230, GAA structures are formed in the gate openings. For example, based on operations225-230, gate structures112can be formed surrounding channel structures122, as described with reference toFIGS.8A-9B. Referring toFIG.2, in operation225, interfacial oxide layers and an HK gate dielectric layer are deposited and annealed within the gate openings. For example, as described with reference toFIGS.8A-8B,10layers127and HK gate dielectric layer128can be deposited and annealed within gate openings412and422. IO layers127can be formed on exposed surfaces of channel structures122within respective gate openings412and422. In some embodiments, IO layers127can be formed by exposing channel structures122to an oxidizing ambient. The oxidizing ambient can include a combination of ozone (03), a mixture of ammonia hydroxide, hydrogen peroxide, and water (“SC1 solution”), and/or a mixture of hydrochloric acid, hydrogen peroxide, water (“SC2 solution”). The deposition of HK gate dielectric layer128can include depositing a HK gate dielectric material within gate openings412and422after the formation of IO layers127, as shown inFIGS.8A-8B. In some embodiments, HK gate dielectric layer128can be formed with an ALD process using hafnium chloride (HfCl4) as a precursor at a temperature ranging from about 250° C. to about 350° C. Other temperature ranges are within the scope of the disclosure. In some embodiments, the formation of HK gate dielectric layer128can be followed by an annealing process to improve the electrical characteristics and/or reliability of IO layers127and/or HK gate dielectric layer128. Referring toFIG.2, in operation230, gate metal fill layers are deposited on the HK gate dielectric layers. For example, as shown inFIGS.9A-9B, gate metal fill layers138are deposited on HK gate dielectric layers128. The deposition of gate metal fill layers138can include depositing a fluorine-free metal layer (e.g., a FFW layer) within gate openings412and422ofFIGS.8A-8Bat the same time. The deposition of the fluorine-free metal layer within gate openings412can be a bottom-up deposition process, while the deposition of the fluorine-free metal layer within gate openings422between channel structures122can be a conformal deposition process. The deposition of the fluorine-free metal layer can include depositing the fluorine-free metal layer with an ALD process using tungsten pentachloride (WCl5) or Tungsten hexachloride (WCl6) and H2as precursors at a temperature ranging from about 400° C. to about 500° C. Other temperature ranges are within the scope of the disclosure. In some embodiments, the fluorine-free metal layer can be deposited in an ALD process of about 160 cycles to about 320 cycles, where one cycle can include sequential periods of: (i) first precursor gas (e.g., WCl5or WCl6) flow, (ii) a first gas purging process, (iii) a second precursor gas (e.g., H2) gas flow, and (iv) a second gas purging process. After the deposition of gate metal fill layers138, IO layer127, HK gate dielectric layer128, and/or gate metal fill layer138can be polished by a chemical mechanical polishing (CMP) process to substantially coplanarize top surfaces of IO layer127, HK gate dielectric layer128, and/or gate metal fill layer138with a top surface of ILD layer118, as shown inFIGS.9A-9B. In some embodiments, after the CMP process, S/D contact structures140as shown inFIG.1Bcan be formed. FIGS.10and15are flow diagrams of two example processes1000and1500for operation220of forming channel structures according to some embodiments.FIG.11A-11Bare cross-sectional views of a portion of a channel structure at various stages of process1000, in accordance with some embodiments.FIG.16A-16Dare cross-sectional views of a portion of a channel structure at various stages of process1500, in accordance with some embodiments. Referring toFIG.10, in operation1010, a Ge treatment is performed on exposed surfaces of the remaining nanostructured layers in the superlattice structure. For example, pure Ge can be deposited on outer surfaces of nanostructured layers121that are exposed by gate openings412and422(shown inFIGS.6A-6B). In some embodiments, the nanostructured layers121are Si nano-sized layers, and the Ge treatment can be performed by using a CVD process. In some embodiments, the precursor process gas can be germane (GeH4), digermane (Ge2H6), and/or higher order germane (Ge>2H>6) having a percentage concentration ranging from about 0.1% to about 100%. A precursor process gas partial pressure (PP) can range from about 0.001 mTorr to about 100 mTorr. A carrier gas can be H2, N2, Ar, He, or a combination thereof. A Ge treatment time can be within a range from about 1 second to about 10,000 seconds, according to some embodiments. In some embodiments, a Ge reacting gas can be GeH4gas, a PP of the CVD process can be less than about 4×10−3Torr (4 mT). A total pressure of the reactor chamber can be less than about 30 Torr. A duration time of the Ge treatment can be less than or equal to about 1300 seconds. After operation1010, a Ge layer1120with a thickness to can be formed on Si layer1110with a thickness t1, as shown inFIG.11A. In some embodiments, a top surface of Ge layer1120is not uniform. Ge layer1120can include a plurality of Ge three-dimensional (3D) islands1125, as shown inFIG.11A. When performing a Ge treatment to a Si surface, there can be about 4.2% lattice mismatch between Ge atoms that have a diameter of about 0.565 nm and Si atoms that have a diameter of about 0.543 nm. According to a Stranski-Kranstanov (S.K.) mode, a critical thickness of epitaxial growth of Ge atoms on Si atoms is about 3.5 monolayer (ML) of Ge atoms (for Ge, 1 ML is about 0.141 nm which equals about 6.3×1014atoms/cm2, and for Si, 1 ML is about 0.135 nm). As shown inFIG.12A, Ge atoms1203can grow layer by layer on Si atoms1201when the thickness of Ge epitaxial growth layer is less than the critical thickness of about 3.5 ML. When the thickness of Ge epitaxial growth layer is larger than the critical thickness of about 3.5 ML, as shown inFIG.12B, the location strain relaxation at some surface regions can cause three-dimensional (3D) islands of Ge atoms. When the thickness of Ge epitaxial growth layer is much larger than the critical thickness 3.5 ML, as shown inFIG.12C, the strain relaxation between the Ge atom layer and the Si atom layer can cause macroscopic 3D islands of Ge atoms. To form a substantially uniform Ge layer on the Si channel layer, CVD process parameters should be selected to control the thickness of Ge epitaxial growth layer to be less than the critical thickness of about 3.5 ML. Referring toFIG.13A, an example diagram of Ge composition percentage versus Ge treatment temperature is illustrated, according to some embodiments. At the conditions of using germane (GeH4) as the reacting gas, under a PP about 18 mT (30 Torr), and keeping a Ge treatment time about 32 seconds, the Ge composition percentage of the formed Ge epitaxial growth layer increases as the Ge treatment temperature increases. As shown inFIG.13A, points1310,1320, and1330illustrate that the Ge composition percentage of the channel surface after the Ge treatment at various temperatures (e.g., respective temperatures of about 400° C., about 425° C., and about 450° C.) can be, for example, between about 10% and about 20%. Point1340illustrates that the Ge composition percentage of the channel surface after the Ge treatment at a temperature of, for example, about 475° C. is between, for example, about 20% and about 30%. Points1350,1360,1370illustrate that the Ge composition percentage of the channel surface after the Ge treatment at respective temperatures of, for example, about 500° C., about 550° C., and about 600° C. is larger than, for example, about 60%. However, the top surfaces of the formed Ge layer corresponding to points1310,1320, and1330can be smooth, the top surface of the formed Ge layer corresponding to point1340can include few small 3D islands, while the top surfaces of the formed Ge layer corresponding to points1350,1360, and1370can include many macroscopic 3D islands. Accordingly, an upper level of the Ge treatment temperature can be determined as, for example, about 450° C. Referring toFIG.13B, an example diagram of Ge growth rate versus Ge treatment temperature is illustrated, according to some embodiments. The chemical formula of the chamber reaction is GeH4→Ge+2H2. Since the reaction is limited by a supply of reactant, and the reactant transport is affected by pattern geometry and aspect ratio, the mass transport is limited in a temperature range, for example, from about 400° C. to about 600° C. The hollow circular points inFIG.13Billustrate the Ge growth rate is substantially exponentially proportional to the reciprocal of temperature with a first slope in a first temperate range, for example, from about 400° C. to about 600° C. Further, the reaction is also limited by the reaction rate, which is temperature dependent. The surface reaction has a less pattern effect at a lower temperature, e.g., at a temperature lower than about 400° C. Thus, the surface reaction is limited in a temperature range, for example, from about 325° C. to about 400° C. The solid square points inFIG.13Billustrate the Ge growth rate is substantially exponentially proportional to the reciprocal of temperature with a second slope in a second temperate range, for example, from about 325° C. to about 400° C. The cross point1310of the straight lines fitting the two sets of data points, based on the mass transport limitation and the surface reaction limitation, is at a temperature of, for example, about 400° C. Therefore, the Ge treatment temperature can be determined within a range, for example, from about 350° C. to about 450° C. A preferred Ge treatment temperature can be determined, for example, at about 400° C. Referring toFIG.13C, an example diagram of Ge composition percentage versus GeH4treatment time is illustrated, according to some embodiments. The Ge composition percentage of the formed Ge epitaxial growth layer depends on GeH4treatment time, which can be controlled by CVD process time.FIG.13Cshows that the Ge composition percentage increases as the GeH4treatment time increases, when using H2as the ambient and at a temperature of, for example, about 400° C. The hollow circular points correspond to a condition of the GeH4PP of the CVD process of, for example, about 18 mT, while the solid circular points correspond to a condition of GeH4PP of, for example, about 4 mT. Thus, additional Ge composition percentage can be obtained with a higher GeH4PP during the same treatment time. Referring toFIGS.14A-14C, example cross-sectional views of formed Ge epitaxial growth layers on Si channel layers under different GeH4PPs are illustrated, according to some embodiments. Referring toFIG.14A, under a CVD condition of GeH4PP of about 180 mT and a chamber pressure about 300 Torr, the formed Ge epitaxial growth layers1120on Si channel layers1100are not uniform. Referring toFIG.14B, under a CVD condition of GeH4PP of about 18 mT and a chamber pressure about 30 Torr, the formed Ge epitaxial growth layers1120on Si channel layers1100are not uniform. Referring toFIG.14C, under a CVD condition of GeH4PP of about 4 mT and a chamber pressure of about 7 Torr, the formed Ge epitaxial growth layers1120on Si channel layers1100are substantially uniform. Therefore, the GeH4PP less than about 18 mT can improve Ge uniformity on nanosheet patterns. Based on the above discussion, in some embodiments, the CVD process parameters for the Ge treatment operation (e.g., operation1010inFIG.10) can be controlled based on the following: a process temperature at about 400° C., a GeH4partial pressure at about 4 mTorr, a process pressure at about 7 Torr, a process time of operation1010between 8 seconds and 1300 seconds, and a process ambient as Hz. Referring toFIG.10, in operation1020, a temperature ramping operation is performed, to prepare for a subsequent annealing process. In some embodiments, the above CVD process conditions during operation1010can be gradually changed in operation1020. For example, during the temperature ramping operation, the process temperature can be gradually increased from about 400° C. to about 750° C., the GeH4partial pressure can be gradually decreased from about 4 mTorr to about 0 mTorr, and the process pressure can be gradually increased from about 7 Torr to about 30 Torr. A process time of the temperature ramping operation1020can be about 600 seconds. Referring toFIG.10, in operation1030, an in-situ or ex-situ thermal annealing operation is performed for (i) SiGe alloying, (ii) smoothing the surface of the formed SiGe layer, and (iii) surface Ge atoms thermal diffusion. In some embodiments, the in-situ annealing process can be a reflection high energy electron diffraction (RHEED) process, and the ex-situ annealing process can be scanning electron microscopy (SEM), atomic force microscopy (AFM), or photoluminescence. In some embodiments, the annealing process can be performed at an annealing temperature between about 450° C. and about 1200° C. An annealing ambient can be H2, N2, Ar, He, or a combination thereof. An annealing process pressure can be within a range from about 0.1 mT to about 22,800 Torr. An annealing process time can be within a range from 1 microsecond (μs) to about 3600 seconds. In some examples, the in-situ or ex-situ annealing process can be performed at a temperature between about 500° C. and about 800° C. (e.g., about 750° C.) in an H2ambient, the process pressure can be about 30 Torr, and a process time of the annealing operation1030can be about 250 seconds. In some embodiments, when the Ge composition percentage of the Ge epitaxial growth layer1120formed in operation1010is larger than about 2.5%, the Ge 3D islands1125as shown inFIG.11Acan be smooth by the annealing operation. However, when the Ge composition percentage of the formed Ge epitaxial growth layer1120is larger than about 30% (e.g., formed by a Ge treatment time greater than 1300 s), the surface morphology may be non-uniform after the annealing process. In a first example, a GeH4PP of about 4 mT and a Ge treatment time of about 600 seconds can form a smooth Ge epitaxial growth layer1120with a Ge composition percentage of about 2.3%. After an in-situ annealing operation at about 650° C. in an H2ambient for about 250 seconds, the formed GeSi layer can have a smooth surface and a Ge composition percentage of about 2.1%. In a second example, a GeH4PP of about 4 mT and a Ge treatment time of about 900 seconds can form a smooth Ge epitaxial growth layer1120with a Ge composition percentage of about 6.6%. After an in-situ annealing operation at about 650° C. in an H2ambient for about 250 seconds, the formed GeSi layer can have a smooth surface and a Ge composition percentage of about 6%. In a third example, a GeH4PP of about 4 mT and a Ge treatment time of about 1200 seconds can form a Ge epitaxial growth layer1120with 3D Ge islands and a Ge composition percentage of about 27.5%. After an in-situ annealing operation at about 650° C. in an H2ambient for about 250 seconds, the formed GeSi layer can have a smooth surface and a Ge composition percentage of about 25%. In a fourth example, a GeH4PP of about 4 mT and a Ge treatment time of about 1350 seconds can form a Ge epitaxial growth layer1120with 3D Ge islands and a Ge composition percentage of about 40.5%. After an in-situ annealing operation at about 650° C. in an H2ambient for about 250 seconds, the formed GeSi layer can still have 3D Ge islands and a Ge composition percentage of about 30.1%. If the formed Ge epitaxial growth layer1120includes too many 3D islands or the size of the 3D islands are too big, the 3D islands cannot be repaired by an annealing process. Accordingly, the Ge treatment time can be controlled to be less than about 1300 seconds and the Ge composition percentage of the Ge epitaxial growth layer can be controlled to be less than about 30%. A desired Ge composition percentage of the formed Ge layer can be in a range from about 20% to about 30%, such as about 25%. As shown inFIG.11B, after the annealing operation, the Ge atoms of the Ge epitaxial growth layer1120can thermally diffuse into underlayer Si channel1110, such that the Ge atoms and Si atoms can form a SiGe alloy layer1130. The formed SiGe alloy layer1130can have a substantially uniform shape on the remaining portion of Si layer1140. The formed SiGe alloy layer1130can form cladding layer115, and the remaining portion of Si layer1140can form channel layer120, as described above in connection withFIGS.1B-1D and6A-9B. A thickness t3of SiGe alloy layer1130can be less than about 2 nm or less than about 1 nm. Further, since the Ge atoms thermally diffuse into the underlayer Si channel1100, a total thickness of the SiGe alloy layer1130and the remaining portion of Si layer1140can be less than (t1+t3). In one example following the process1000as shown inFIG.10, a GeH4PP of about 4 mT and a Ge treatment of about 1200 seconds can form a Ge epitaxial growth layer1120with 3D Ge islands having a height of about 3.04 nm and a Ge composition percentage of about 27.7%. After an in-situ annealing operation at about 750° C. in an H2ambient for about 250 seconds, the formed GeSi layer can have a smooth surface, a Ge composition percentage of about 24%, and a thickness ranging from about 0.87 nm to about 0.93 nm. After the Ge treatment operation1010, the formed Ge islands may have a height larger than about 5 nm in some undesired situations. Such Ge islands may merge with adjacent Ge epitaxial growth layer1120in scaled down device structures, such as in nanosheets (e.g., sheet to sheet spacing 11 nm or below), nanowires, and finFETs. Once merged, the Ge islands occur after Ge treatment operation1100with increased risk of not forming a uniform and thin Ge or GeSi cladding layer1120after the annealing operation1300, resulting in deteriorated device performance. Referring toFIG.15, a flow diagram of a second example process1500for operation220of forming channel structures is shown according to some embodiments.FIG.16A-16Dare cross-sectional views of a portion of a channel structure at various stages of process1500, according to various embodiments. In some embodiments, a cyclic Ge treatment operation1510, temperature ramping operation1520, and annealing operation1530are performed to prevent surface morphology degradation. As described above in connection withFIG.12A, Ge atoms1203can growth layer by layer on Si atoms1201when the thickness of Ge epitaxial growth layer is less than the critical thickness (e.g., 3.5 ML). Therefore, in each cycle of Ge treatment operation1510, the CVD parameters (e.g., Ge treatment time) can be controlled to keep the Ge growth thickness less than the critical thickness to prevent surface morphology degradation. In some embodiments, the CVD parameters corresponding to the critical thickness can be determined by manipulating a Ge treatment time in a specific process regime. In a first CVD process example, at about 400° C. and under 1% GeH4PP of about 4 mT, in an H2ambient, and a Ge treatment time of about 650 seconds, a Ge epitaxial growth layer can be formed. The Ge epitaxial growth layer can reach the critical thickness, which means that the Ge deposition passes through from 2D growth to 3D growth after about 650 seconds after starting the Ge treatment to generate an increasing number of Ge islands on the Si surface. In a second CVD process example, at about 400° C. and under 1% GeH4PP of about 18 mT, in an H2ambient, and a Ge treatment time of about 220 seconds, the Ge epitaxial growth layer can reach the critical thickness. After a first Ge treatment operation1510, the surface morphology is non-degraded (e.g., no visible Ge island formation) when certain CVD parameters are controlled to keep the Ge growth thickness less than the critical thickness. As shown inFIG.16A, the formed Ge epitaxial growth layer1620on the Si layer1610can have a flat top surface. The thickness t2of Ge epitaxial growth layer1620is less than the critical thickness tc. After the first temperature ramping operation1520and first annealing operation1530, the thickness t3of the formed GeSi alloy layer1630may not meet requirements for semiconductor device performance. To formed a desired thickness of cladding layer115(e.g., GeSi alloy layer1630) or surface Ge composition, Ge treatment operation1510, temperature ramping operation1520and annealing operation1530can be cyclic repeated one or more times. For example, if it is determined that the thickness of cladding layer115does not reach the desired thickness at operation1540, the 2nd, 3rd, 4th, and so forth cycles of Ge treatment operation1510, temperature ramping operation1520, and annealing operation1530can be performed sequentially to form additional Ge epitaxial growth layer1640and to increase the thickness t4of GeSi alloy layer1650and surface Ge composition. The Ge treatment time, annealing time, and the annealing temperature can be different for each cycle, according to some embodiments. The cyclic repetition of Ge treatment operation1510, temperature ramping operation1520, and annealing operation1530can be stopped when thickness t4of GeSi alloy layer1650and/or surface Ge composition meet design requirements. Although each Ge treatment operation1510does not generate Ge islands on the formed Ge epitaxial growth layer, an in-situ or ex-situ annealing operation1530may be required to be performed before a next cycle of Ge treatment operation1510. Without annealing operation1530between each Ge treatment operation1510, Ge islands may appear when forming Ge epitaxial growth layer on GeSi alloy layer, resulting in degradation of surface morphology. In a first example of performing process1000including a single Ge treatment at about 400° C. and in an H2ambient, Ge islands may appear at the surface of Ge epitaxial growth layer when the Ge composition percentage is larger than about 2.5%. In a second example of performing process1500including 8 cycles of Ge treatments under the same CVD conditions, Ge islands may appear at the surface of Ge epitaxial growth layer when the Ge composition percentage reaches about 25%, which is about a significant increase (e.g., about 10× increase) compared to the first example. The present disclosure provides example multi-Vt devices (e.g., semiconductor device100) with FETs (e.g., finFETs or GAA FETs) having an improved channel structure configurations. A thin substantially uniform Ge cladding layer wrapped around the Si channel layer is critical for Ge tuning pFET Vth in scaled down advanced device structures (e.g. finFETs, nanowire, nanosheet). The present disclosure also provides fabricating methods to form the thin substantially uniform Ge cladding layer without constrained by pattern geometry by using reduced pressure CVD tools at specific design process conditions. In some embodiments, the present disclosure provides a method for forming a channel structure of a semiconductor device. The method can include forming a superlattice structure including a plurality of first nanostructured layers and a plurality of second nanostructured layers on a fin structure; removing the plurality of second nanostructured layers to form a plurality of gate openings; forming a germanium epitaxial growth layer on the plurality of first nanostructured layers at a first temperature and a first pressure; increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time; and annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers. In some embodiments, the present disclosure provides a method for forming a channel structure of a semiconductor device. The method can include forming a germanium epitaxial growth layer on nanostructured layers at a first temperature and a first pressure; increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined time period of time; annealing the germanium epitaxial growth layer at the second temperature and the second pressure over a second predetermined time period of time to increase a thickness of a cladding layer surrounding the nanostructured layers. The method can include repeating these operations. In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device can include a substrate and a fin structure disposed on the substrate; a channel structure disposed on the fin structure; a channel layer and a cladding layer on surfaces of the channel layer. A thickness of the cladding layer can be less than about 2 nm. The semiconductor device can also include a gate structure disposed on the channel structure. The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 49,282 |
11942534 | DETAILED DESCRIPTION The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a thermal conductor and methods of manufacture. More specifically, the present disclosure relates to a lateral SiGe heterojunction bipolar transistor with a thermal conductor underneath and thermally connected to a base region. In embodiments, the thermal conductor may be a semiconductor material with a higher thermal conductivity than the base substrate. For example, the thermal conductor may be SiC material underneath the base of the bipolar transistor. Advantageously, the thermal conductor improves thermal dissipation of the bipolar transistor, while improving stress and enhancing electron mobility for improved Ft/Fmax. In more specific embodiments, the bipolar transistor is a lateral SiGe heterojunction bipolar transistor. The lateral SiGe heterojunction bipolar transistor comprises a SiGe base grown from a Si layer or grow directly on a SiGe marker layer. A SiC via may be formed in a buried insulator layer and connected with the device and an underlying SiC substrate layer. A SiC substrate layer may be formed on a handle substrate. The SiC via and SiC substrate layer may be a thermal conductor. The bipolar transistor of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the bipolar transistor of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the bipolar transistor uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art. FIG.1shows a lateral heterojunction bipolar transistor in accordance with aspects of the present disclosure. More specifically, the structure10shown inFIG.1includes a substrate12. In embodiments, the substrate12includes a handle substrate12a, a buried insulator layer12b, a semiconductor layer12cand a thermal conductive material12d. The handle substrate12aprovides mechanical support to the buried insulator layer12band the top semiconductor layer12c. In embodiments, the handle substrate12aand the semiconductor layer12cmay include any appropriate semiconductor material such as, for example, Si, Ge, SiGe, SiC, SiGeC, a III-V compound semiconductor, II-VI compound semiconductor or any combinations thereof. In preferred embodiments, the semiconductor layer12cmay be a buffer layer comprising Si or SiGe and the handle substrate12amay comprise Si. The semiconductor layer12cmay also be N+ semiconductor material. The handle substrate12aand the semiconductor layer12cmay also comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The buried insulator layer12bmay be a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof, and preferably may be buried oxide layer (BOX). The thermal conductive material12dmay be below the buried insulator layer12band include a via portion12d′ that extends through the buried insulator layer12bto contact the device, itself. For example, the thermal conductive material12dand, more particularly, the via portion12d′ extends to and contacts the semiconductor layer12c. The thermal conductive material12dmay be a non-doped semiconductor material or P+ doped semiconductor material, either of which comprises a higher thermal conductivity than the semiconductor layer12c. For example, in embodiments, the semiconductor layer12cmay be Si and the thermal conductive material12d,12d′ may be SiC. As another example, the semiconductor layer12cmay be GaAs or GaN and the thermal conductive material12d,12d′ may be Si or SiC. An N+ well15may be formed in the thermal conductive material12dbelow the buried insulator layer12bto provide electrical isolation between the via portion12d′ and the handle substrate12a. Shallow trench isolation structures14may be provided in the semiconductor layer12cand extend to the buried insulator layer12b. The shallow trench isolation structures14effectively isolate the lateral bipolar junction transistor10from other devices. As described herein, the shallow trench isolation structures14may be fabricated using conventional lithography, etching and deposition methods. A base16(e.g., intrinsic base) may be formed within and above the semiconductor layer12c. In embodiments, the base16may be above the via portion12d′. In this way, the via portion12d′ may be connected to the base16, e.g., heterojunction bipolar transistor, via the semiconductor layer12c. As such, the via portion12d′ (and thermal conductive material12d) may provide a thermal conductive pathway between the heterojunction bipolar transistor (e.g., base and/or collector and emitter) and the semiconductor substrate12a(e.g., though the insulator layer12b). The base16may be SiGe material, which is epitaxially grown on the semiconductor layer12cfollowed by patterning processes, e.g., lithography and etching processes as described in more detail with respect toFIG.2E. Also, the N+ well15is below (underneath) the base16. An extrinsic base18may be formed on the base16. In embodiments, the extrinsic base18may be P+ semiconductor material, e.g., Si, polysilicon or SiC. A spacer20may be provided on sidewalls and extend partially underneath the extrinsic base18. In embodiments, the spacer20separates (e.g., isolates) the extrinsic base18from a collector24and emitter22, and more specifically separates contacts28on the extrinsic base18from the collector24and emitter22. The spacer20may be a SiN, for example. Still referring toFIG.1, the emitter22may be formed on a first side of the extrinsic base18(and intrinsic base16) and the collector24may be formed on a second side of the base18. Accordingly, the emitter22, collector24and base18may be laterally positioned in a horizontal plane forming a lateral bipolar transistor. Both the collector24and the emitter22may comprise raised epitaxial semiconductor material on opposing sides of the base18. In more specific embodiments, the collector24and the emitter22may be N+Si material. The collector24and the emitter22may be formed over and in direct contact with the semiconductor layer12c(or optional SiGe marker layer also shown at reference numeral12c). FIG.1further shows a silicide23on the emitter22, extrinsic base18and collector24. As described in more detail herein atFIG.2F, the silicide23may be formed using conventional silicide processes. A plurality of contacts28within dielectric material26may contact the emitter22, extrinsic base18and collector24. More specifically, the plurality of contacts28contact the silicide23over the emitter22, extrinsic base18and collector24. FIGS.2A-2Fshow processing steps for fabricating the lateral heterojunction bipolar transistor ofFIG.1. InFIG.2A, a thick oxide layer12bis formed on the semiconductor layer12c. In embodiments, the thick oxide layer12bmay be formed by any suitable process, such as separation by implantation of oxygen (SIMOX), oxidation, deposition, and/or other suitable process. Also, as should be understood by those of skill in the art, the thick oxide layer12bmay be the buried insulator layer shown inFIG.1as will become apparent to those of skill in the art in view of the discussion ofFIG.2C. Still referring toFIG.2A, the semiconductor layer12cmay be subjected to an ion implantation process (as shown by the arrows) to form a smart cut implant100within the semiconductor layer12c. In embodiments, the semiconductor layer12cmay be an N+ substrate and the smart cut implant100may be a P+ implant, e.g., boron dopant. InFIG.2B, the thick oxide layer12bmay be subjected to a patterning process to form the via portion12d′. More specifically, the via portion12d′ can be formed by conventional lithography, etching and deposition methods known to those of skill in the art. For example, a resist formed over thick oxide layer40is exposed to energy (light) and developed to form a pattern (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), will be used to transfer the pattern from the patterned resist layer to thick oxide layer12bto form a via in the thick oxide layer12b. Following the resist removal by a conventional oxygen ashing process or other known stripants, semiconductor material (e.g., SiC) can be deposited by any conventional deposition processes, e.g., epitaxial growth process or chemical vapor deposition (CVD) processes. Any residual material on the surface of the thick oxide layer40can be removed by conventional chemical mechanical polishing (CMP) processes. InFIG.2C, the structure ofFIG.2Bis flipped over and the thermal conductive material12dand the handle substrate12amay be bonded to the thick oxide layer12b. In this way, the thick oxide layer12bmay become the buried insulator layer. In embodiments, the bonding may be any conventional bonding technique known to those of skill in the art such that no further explanation is required for a complete understanding of the present disclosure. Also, the semiconductor layer12cmay be thinned using the smart cut implant100as should be understood by those of skill in the art. InFIG.2D, shallow trench isolation structures14may be formed through the semiconductor layer12cto the buried insulator layer12b. The shallow trench isolation structures14can be formed by conventional lithography, etching and deposition methods known to those of skill in the art as already described herein. The N+ well15may be formed in the thermal conductive material12dbelow the buried insulator layer12b. The N+ well15may be formed by introducing a dopant by, for example, ion implantation in the thermal conductive material12d. In embodiments, a patterned implantation mask may be used to define selected areas exposed for the implantation. The implantation mask may include a layer of a light-sensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and stopping power sufficient to block masked areas against receiving a dose of the implanted ions. The N+ well15is doped with n-type dopants, e.g., Arsenic (As), Phosphorus (P) and Sb, among other suitable examples. InFIG.2E, the intrinsic base16may be formed by forming a recess in the semiconductor layer12c, followed by an epitaxial growth process. In embodiments, the intrinsic base16may be SiGe material. The extrinsic base material18may be formed on the intrinsic base material16. In embodiments, the extrinsic base material18may be a semiconductor material (e.g., Si or SiGe) formed by a conventional epitaxial growth process, with an in situ P+ dopant process, e.g., boron. Following the deposition process, the extrinsic base material18may be patterned by conventional lithography and etching processes. A spacer material20may be formed over the patterned extrinsic base material18, in addition to an exposed portion of the intrinsic base material16. In embodiments, the spacer material20may be SiN or SiCoN, as examples, deposited by a conventional CVD process followed by an anisotropic etching process. InFIG.2F, the emitter22and collector24are formed on the underlying semiconductor layer12c. In embodiments, the emitter22and collector24are raised epitaxy regions formed by selectively growing semiconductor material on the semiconductor layer12c. In embodiments, the epitaxy regions may include epitaxially grown Si material, with an in-situ doping process, e.g., N+ dopant such as arsenic or phosphorous. An annealing process may be performed to drive in the dopant into the emitter22and collector24(in addition to the P+ dopant of the extrinsic base18). A silicide23is formed on the emitter22, collector24and the extrinsic base18. As should be understood by those of skill in the art, the silicide process begins with deposition of a thin transition metal layer, e.g., nickel, cobalt or titanium, over the fully formed and patterned emitter22, collector24and extrinsic base18. After deposition of the material, the structure is heated allowing the transition metal to react with exposed silicon (or other semiconductor material as described herein) in the active regions of the semiconductor device (e.g., emitter22, collector24and the extrinsic base18) forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts23. Referring back toFIG.1, an interlevel dielectric material26may be deposited over the emitter22, collector24and extrinsic base18. The interlevel dielectric material26may be a layered structure of oxide and nitride material. The interlevel dielectric material26may be deposited by a conventional deposition method, e.g., CVD. The interlevel dielectric material26undergoes a patterning process, e.g., lithography and etching, to form vias or trenches to the emitter22, collector24and the extrinsic base18. A conductive material, e.g., tungsten, is deposited within the vias or trenches, making contact to the silicide23of the emitter22, collector24and extrinsic base18. Any residual conductive material may be removed from the interlevel dielectric material26by a conventional CMP process. It should be understood by those of ordinary skill in the art that the vias or trenches can be lined with a barrier metal, e.g., TaN, TiN, etc., prior to the deposition of the tungsten material. The bipolar transistor can be utilized in system on chip (SoC) technology. The SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. As the components are integrated on a single substrate, SoCs consume much less power and take up much less area than multichip designs with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (such as in Smartphones) and edge computing markets. SoC is also used in embedded systems and the Internet of Things. The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. | 16,582 |
11942535 | DESCRIPTION OF EXEMPLARY EMBODIMENTS Description is given below for the present invention by means of embodiments of the invention, but the following embodiments do not limit the invention according to the claims. There is no limitation to all combinations of features described in an embodiment being essential to a means for solving the problems of the invention. Herein, one direction parallel to the depth direction of a semiconductor substrate is referred to as “up”, and the other direction is referred to as “down”. In addition, one surface of the two main surfaces of a substrate, a layer, or another member is referred to as a top surface, and the other surface is referred to as a bottom surface. “Up” and “down” directions are not limited by the direction of gravity. In the present specification, technical matter may be described with reference to X, Y, and Z orthogonal coordinate axes. In the present specification, a plane parallel to the top surface of a semiconductor substrate is referred to as an XY plane, and the depth direction of the semiconductor substrate is referred to as the Z axis. In each embodiment, description is given for an example in which a first conductivity type is N type and a second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the respective conductivity types of substrate, layers, regions and the like in each embodiment are respectively opposite polarities. “Doping concentration” in the present specification indicates the concentration of impurities made to be an acceptor or a donor. The difference in concentration between donors and acceptors may be given as the doping concentration. The peak value of a doping concentration distribution in a doped region may be given as the doping concentration in that doped region. In the present specification, a layer or region that begins with “N” or “P” means that this layer or region is a majority carrier of electrons or holes, respectively. In addition, “+” and “−” added to N or P respectively mean a higher doping concentration and a lower doping concentration in relation to a layer or region to which “+” or “−” are not added. FIG.1Aillustrates an example of a cross-section of a semiconductor device100according to an embodiment. Each member illustrated inFIG.1Ais formed extending in a direction that is perpendicular to the paper surface of the drawing. The semiconductor device100reduces an ON resistance and an ON voltage in accordance with conductivity modulation. As an example, the semiconductor device100is a semiconductor chip that has an insulated gate bipolar transistor (IGBT). In the corresponding cross-section, the semiconductor device100of the present example has a semiconductor substrate10, an insulating film between layers26, an emitter electrode52, and a collector electrode24. The insulating film between layers26is provided on a front surface21of the semiconductor substrate10. The insulating film between layers26is, for example, a silicate glass film to which phosphorus has been added (a PSG film), or a silicate glass film to which phosphorus and boron have been added (a BPSG film). A contact hole54is an opening provided in the insulating film between layers26. The contact hole54is provided in order to expose the front surface21of the semiconductor substrate10, and connect the emitter electrode52with the front surface21. The contact hole54in the present example is provided in the center of a mesa portion60, but there is no limitation to this. The emitter electrode52is provided above the front surface21of the semiconductor substrate10. The emitter electrode52of the present example is formed on the top surface of the insulating film between layers26. The emitter electrode52may be in contact with some regions of the front surface21of the semiconductor substrate10. The emitter electrode52is also formed inside the contact hole54, and is in contact with emitter regions12. The insulating film between layers26also insulates between the emitter electrode52and a gate conductive portion44. The collector electrode24is provided on a back surface23of the semiconductor substrate10. The emitter electrode52and the collector electrode24are formed by an electrically-conductive material such as metal. For example, the emitter electrode52and the collector electrode24may be formed by an electrically-conductive material that includes aluminum. In addition, portions of the emitter electrode52and the collector electrode24that are formed in fine regions such as within openings in an insulating film may be formed by an electrically-conductive material that includes tungsten. The semiconductor substrate10may be a silicon substrate or a compound semiconductor substrate. The semiconductor substrate10may be, for example, a silicon carbide substrate or a nitride semiconductor substrate made of gallium nitride or the like. The semiconductor substrate10in the present example is a silicon substrate. A drift region18is a first conductivity type region provided in the semiconductor substrate10. The drift region18in the present example is of the N-type as an example. The drift region18may be a remaining region of the semiconductor substrate10where another doped region is not formed. In other words, the doping concentration of the drift region18may be the doping concentration of the semiconductor substrate10. The emitter region12is a first conductivity type region provided at the side of the front surface21of the semiconductor substrate10. The emitter region12is of the N+ type as an example. The emitter region12is provided in contact with a dummy trench portion30or a gate trench portion40. The emitter region12is provided, in a mesa portion60between adjacent trench portions, extending from one trench portion to the other trench portion. A base region14is a second conductivity type region provided at the side of the front surface21of the semiconductor substrate10. The base region14is of the P-type as an example. The base region14is provided below the emitter region12. The base region14is also provided above the drift region18. An accumulation region16is a first conductivity type region provided between the base region14and the drift region18. The accumulation region16in the present example is of the N type as an example. The accumulation region16is provided in contact with the dummy trench portion30or the gate trench portion40. The doping concentration of the accumulation region16is higher than the doping concentration of the drift region18. The accumulation region16increases the carrier density in the top surface side of the drift region18by suppressing holes that are implanted into the drift region18from the back surface23side of the semiconductor substrate10from getting through to the front surface21side of the semiconductor substrate10. In this manner, the accumulation region16modulates the conductivity of the semiconductor device100in accordance with a carrier injection enhancement effect (an IE effect). As a result, the conduction resistance of the semiconductor device100decreases, and it is possible to reduce an ON voltage. An electric field relaxation region17is provided between the base region14and the accumulation region16. The top end of the electric field relaxation region17is the location of a junction between the base region14and the electric field relaxation region17. The lower end of the electric field relaxation region17is a location of a half-value with respect to the peak of the doping concentration of the accumulation region16. The electric field relaxation region17is of the N-type as an example The doping concentration of the electric field relaxation region17is lower than the peak of the doping concentration of the accumulation region16. The doping concentration of the electric field relaxation region17may be lower than the peak of the doping concentration of the base region14. In the electric field relaxation region17, it is possible to make it easier for the depletion layer to expand and relax concentration of the electric field. In one example, the electric field relaxation region17has a region with the same doping concentration as that of the drift region18. The electric field relaxation region17has a region with the same doping concentration as that of the drift region18, with a predefined film thickness. For example, the electric field relaxation region17has a region with the same doping concentration as that of the drift region18, with a film thickness of 0.5 μm or more. A film thickness W of the electric field relaxation region17is set so that it is possible to suppress a leakage current between C-E when a high voltage is applied. The leakage current between C-E indicates a leakage current for a current Ices that flows between the collector electrode24and the emitter electrode52. In one example, the film thickness W of the electric field relaxation region17is set so that the electric field between the accumulation region16and the base region14is relaxed, and the leakage current is suppressed. For example, the film thickness W of the electric field relaxation region17is greater than or equal to the film thickness of the accumulation region16. By thickening the film thickness of the electric field relaxation region17, it is easier to suppress the leakage current. The film thickness W of the electric field relaxation region17may be less than or equal to the film thickness of the accumulation region16. The film thickness W of the electric field relaxation region17may be greater than or equal to 0.4 μm and less than or equal to 3.0 μm. The film thickness W of the electric field relaxation region17may be greater than or equal to 1.0 μm and less than or equal to 1.8 μm. The film thickness W of the electric field relaxation region17may be greater than or equal to 1.5 μm and less than or equal to 2.0 μm. A buffer region20is a first conductivity type region provided below the drift region18. The buffer region20in the present example is of the N+ type as an example. The doping concentration of the buffer region20is higher than the doping concentration of the drift region18. The buffer region20may function as a field stop layer that prevents a depletion layer which extends from the bottom surface side of the base region14from reaching the collector region22which is of the second conductivity type and a cathode region which is of the first conductivity type. The dummy trench portion30and the gate trench portion40are arrayed at predefined intervals along a predefined array direction (X axis direction in the present example). The dummy trench portion30and the gate trench portion40extend along an extension direction (Y axis direction in the present example) that is parallel to the front surface21of the semiconductor substrate10and is orthogonal to the array direction. The dummy trench portion30and the gate trench portion40penetrate from the front surface21side of the semiconductor substrate10through the emitter region12, the base region14, the electric field relaxation region17, and the accumulation region16, and extend into the drift region18. The gate trench portion40is set to a gate potential. The gate trench portion40has a gate trench and a gate insulating film42, and the gate conductive portion44which are formed in the front surface21. The gate insulating film42is formed covering the inner wall of the gate trench. The gate insulating film42may be formed by oxidizing or nitriding the semiconductor that is the inner wall of the gate trench. The gate insulating film42insulates between the gate conductive portion44and the semiconductor substrate10. The gate conductive portion44is formed inside the gate trench, more inside than the gate insulating film42. The gate conductive portion44is formed by an electrically-conductive material such as polysilicon. The gate conductive portion44is covered by the insulating film between layers26at the front surface21. The gate conductive portion44includes at least a region that faces adjacent base regions14. When a predefined voltage is applied to the gate conductive portion44, a channel is formed in the surface layer of, out of the base region14, an interface that is in contact with the gate trench portion40. The gate conductive portion44of the present example has a portion that protrudes on the back surface23side of the semiconductor substrate10beyond the bottom surface of the accumulation region16. The dummy trench portion30is set to an emitter potential. The dummy trench portion30has a dummy trench formed at the front surface21side, a dummy insulating film32, and a dummy conductive portion34. The dummy insulating film32is formed covering the inner wall of the dummy trench. The dummy insulating film32may be formed by oxidizing or nitriding the semiconductor that is the inner wall of the dummy trench. The dummy insulating film32insulates between the dummy conductive portion34and the semiconductor substrate10. The dummy conductive portion34is formed inside the dummy trench, more inside than the dummy insulating film32. The dummy conductive portion34is formed by an electrically-conductive material such as polysilicon. The dummy conductive portion34is covered by the insulating film between layers26at the front surface21. The semiconductor device100of the present example is provided with a structure in which one gate trench portion40and two dummy trench portions30are repeatedly arrayed in this order. The array structure for trench portions is not limited to the present example. A plurality of gate trench portions40may be contiguously disposed. One dummy trench portion30may be disposed sandwiched between two gate trench portions40. The semiconductor device100may be provided with only the gate trench portion40as a trench portion. A mesa portion60is a region of the semiconductor substrate10that is sandwiched between two trench portions. The emitter region12, the base region14, the electric field relaxation region17, and the accumulation region16are provided in the mesa portion60. FIG.1Billustrates an example of a top surface view of the semiconductor device100according to the embodiment. A B-B′ cross-section inFIG.1Bcorresponds to the cross-section view illustrated inFIG.1A. A contact region15is a second conductivity type region with a higher doping concentration than that of the base region14. The contact regions15in the present example are of the P+ type as an example. The contact regions15in the present example are provided at the front surface21of mesa portions60. The contact regions15in the present example are in contact with a dummy trench portion30and a gate trench portion40. In a mesa portion60, the emitter regions12and the contact regions15are provided at the front surface21of the semiconductor substrate10. Each emitter region12and contact region15is provided in contact with two trench portions adjacent to the mesa portion60. The emitter regions12and the contact regions15are alternatingly provided in the extension direction. The emitter regions12and the contact regions15are provided at the same interval in the extension direction. However, the width of the emitter region12may be larger than or smaller than the width of the contact region15in the extension direction. Contact holes54are provided extending in the extension direction. A contact hole54is formed above each of the emitter region12and the contact region15. Note that the contact holes54and the insulating films between layers26are omitted in order for the drawing to be concise. FIG.1Cillustrates an example of a doping concentration distribution in a depth direction of the semiconductor device100according to the embodiment. The vertical axis indicates the doping concentration (cm−3) with a logarithm scale, and the horizontal axis indicates the depth (μm) from the front surface21of the semiconductor substrate10. The doping concentration distribution in the present example indicates the doping concentration distribution in the A-A′ cross-section ofFIG.1A. In other words,FIG.1Cillustrates the doping concentration distribution in the emitter region12, the base region14, the electric field relaxation region17, the accumulation region16, and the drift region18, corresponding to the A-A′ cross-section inFIG.1A. Depths D1 through D4 are depths from the front surface21of the semiconductor substrate10. The depth D1 indicates the depth of the lower end of the emitter region12, with reference to the front surface21of the semiconductor substrate10. In other words, the depth D1 corresponds to the location of the boundary between the emitter region12and the base region14. The depth D1 is the depth of a doping concentration distribution junction between the N type emitter region12and the P type base region14. For example, the depth D1 is set to be within a range that is greater than or equal to 0.3 μm and less than or equal to 0.8 μm from the front surface21of the semiconductor substrate10. The doping concentration of the emitter region12shows a maximum value near the front surface21(that is, near a depth of 0 μm) of the semiconductor substrate10. The maximum value of the doping concentration of the emitter region12may be greater than or equal to 1E20 cm−3. Note that E means an exponent of 10, and for example 1E20 cm−3means 1×1020cm−3. The depth D2 indicates the depth of the lower end of the base region14, with reference to the front surface21of the semiconductor substrate10. In other words, the depth D2 corresponds to the location of a boundary between the base region14and the electric field relaxation region17. The depth D2 is the depth of a doping concentration distribution junction between the P type base region14and the N type electric field relaxation region17. For example, the depth D2 is set to be within a range that is greater than or equal to 1.5 μm and less than or equal to 2.5 μm from the front surface21of the semiconductor substrate10. A peak P1 of the doping concentration of the base region14is greater than or equal to 5E16 cm−3and less than or equal to 5E17 cm−3. In the present embodiment, the peak P1 of the doping concentration of the base region14is provided in a range that is greater than or equal to 0.8 μm and less than or equal to 1.8 μm from the front surface21of the semiconductor substrate10. The depth D3 indicates the depth of the lower end of the electric field relaxation region17, with reference to the front surface21of the semiconductor substrate10. The depth D3 corresponds to the location of the boundary between the electric field relaxation region17and the accumulation region16. The depth D3 of the present example is decided by setting a position in the doping concentration distribution for a half-value Ph for a peak P2 of the accumulation region16as the location of the boundary between the accumulation region16and the electric field relaxation region17. The doping concentration of the electric field relaxation region17is lower than the peak P1 of the doping concentration of the base region14. The doping concentration of the electric field relaxation region17is also lower than the peak P2 of the doping concentration of the accumulation region16. The electric field relaxation region17may have a region with the same doping concentration as that of the drift region18. In this case, because the electric field relaxation region17can be a region where the drift region18remains, there is no necessity to additionally perform ion implantation for the electric field relaxation region17. Accordingly, the manufacturing cost of the semiconductor device100is reduced. The depth D4 indicates the depth of lower end of the accumulation region16, with reference to the front surface21of the semiconductor substrate10. The depth D4 corresponds to a depth where the concentration is the same as that of the drift region18. For example, the depth D4 is arranged to be within a range that is greater than or equal to 2.5 μm and less than or equal to 5.0 μm from the front surface21of the semiconductor substrate10. In the present embodiment, the drift region18has a roughly constant doping concentration. In the present embodiment, the doping concentration of the drift region18is greater than or equal to 5E13 cm−3and less than or equal to 5E14 cm−3. The doping concentration of the accumulation region16is lower than the peak P1 of the doping concentration of the base region14. For example, the peak P2 of the doping concentration of the accumulation region16is greater than or equal to 1E16 cm−3and less than or equal to 4E16 cm−3. In the present embodiment, the depth location where the doping concentration of the accumulation region16becomes a maximum is disposed within a range that is greater than or equal to 2.0 μm and less than or equal to 4.5 μm from the front surface21of the semiconductor substrate10. FIG.2Aillustrates an example of a cross-section of a semiconductor device500according to a comparative example. The semiconductor device500of the present example differs to the semiconductor device100according to the embodiment in not having the electric field relaxation region17. The semiconductor device500has, in a mesa portion60, an emitter region512, a base region514, an accumulation region516, and a drift region518. In the semiconductor device500, the base region514and the accumulation region516are adjacently provided. Because the semiconductor device500does not have the electric field relaxation region17, the electric field is concentrated between the base region514and the accumulation region516. For the semiconductor device500, it is possible to, in accordance with the accumulation region516, increase the IE effect, cause the amount of carriers accumulated in a steady state to increase, and reduce the ON voltage. Because it is possible to increase the IE effect the higher the concentration of the accumulation region516, there is a tendency for the accumulation region516to be designed at a high concentration. However, when the peak of the doping concentration for the accumulation region516is a high concentration as with 1E16 cm−3or more, the leakage current may instantaneously increase between C-E. FIG.2Billustrates an example of a doping concentration distribution in a depth direction of the semiconductor device500according to the comparative example. The doping concentration distribution in the present example indicates the doping concentration distribution in the A-A′ cross-section ofFIG.2A. The depth D1′ indicates the depth of the lower end of the emitter region512, with reference to the front surface21of the semiconductor substrate10. The depth D1′ corresponds to the location of a boundary between the emitter region512and the base region514. The depth D1′ is the depth of a doping concentration distribution junction between the N type emitter region512and the P type base region514. A depth D2′ indicates the depth of the lower end of the base region514, with reference to the front surface21of the semiconductor substrate10. The depth D2 corresponds to the location of a boundary between the base region514and the accumulation region516. The depth D2′ is the depth of a doping concentration distribution junction between the P type base region514and the N type accumulation region516. A depth D3′ indicates the depth of lower end of the accumulation region516, with reference to the front surface21of the semiconductor substrate10. The depth D3′ corresponds to a depth where the concentration of the drift region518is the same. A peak P2′ of the doping concentration of the accumulation region516is 1E16 cm−3or more. In the semiconductor device500, the peak P2′ of the doping concentration of the accumulation region516is lower than a peak P1′ of the doping concentration of the base region514. In this manner, at the interface where the P type base region514and the N type accumulation region516are in direct contact, the carrier density is increased by the accumulation region516, and the electric field is more likely to be concentrated. When the electric field is concentrated, a leakage current between C-E is more likely to occur. FIG.2Cillustrates a measured waveform of a current Ices of the semiconductor device500according to the comparative example. The vertical axis indicates the voltage Vce (V) between C-E and the current Ices (A) between C-E, and the horizontal axis indicates time (sec). In the present example,FIG.2Cillustrates change in the current Ices when the voltage Vce is swept at a predefined sweep speed. The voltage Vce is swept at a speed of dv/dt=0.4 kV/ms, from 0 V to 1330 V. When the voltage Vce rises, the current Ices instantaneously rises at a predefined voltage. For example, the instantaneous increase in the leakage current between C-E is where the peak concentration of the accumulation region516is 1E16 cm−3or more, and occurs due to the electric field concentrating at the interface between the base region514and the accumulation region516. The Voltage Vce which increases the leakage current may be related to the voltage for where the depletion layer reaches the buffer region20. By the depletion layer reaching the buffer region20, the electric field ceases to apply further in the depth direction, and the leakage current increases by the electric field on the front surface21side suddenly increasing. The peak concentration here indicates the peak doping concentration. FIG.2Dillustrates a simulated waveform of the current Ices of the semiconductor device500according to the comparative example. The vertical axis indicates the voltage Vce (V) between C-E and the current Ices (A) between C-E, and the horizontal axis indicates time (sec). In the present example, the voltage Vce is swept under the same conditions as the sweep conditions ofFIG.2C. Similarly to the case inFIG.2C, a phenomenon in which the current Ices instantaneously increases accompanying an increase of the voltage Vce is confirmed. In contrast, the semiconductor device100, by providing the electric field relaxation region17, enables the IE effect to be increased while suppressing an increase of the leakage current between C-E that occurs when the accumulation region16is made to have a high concentration. As a result, loss due to the leakage current between C-E is reduced. However, because the IE effect decreases when the film thickness W of the electric field relaxation region17is made to be too large, an appropriate film thickness W for the electric field relaxation region17is selected in accordance with the peak concentration of the accumulation region16. FIG.3Aillustrates an example of a doping concentration distribution of the electric field relaxation region17. The electric field relaxation region17of the present example is changed to four different doping concentration distributions, A1 through A4, by changing conditions. A doping concentration distribution A0 is also illustrated for the semiconductor device500for comparison. The doping concentration distribution A0 indicates the doping concentration distribution of the semiconductor device500which does not have the electric field relaxation region17. In the present example, the base region514is in contact with the accumulation region516. The peak concentration of the accumulation region516is lower than the peak concentration of the base region514. The doping concentration distributions A1 through A4 indicate doping concentration distributions for the semiconductor device100which has the electric field relaxation region17with respectively predefined film thicknesses. The doping concentration distributions A1 through A4 indicate doping concentration distributions for when the film thickness W of the electric field relaxation region17is increased in this order. By increasing the film thickness W of the electric field relaxation region17, it is possible to increase the peak concentration of the accumulation region16. By increasing the peak concentration of the accumulation region16, it is possible to improve the IE effect and reduce the ON voltage. FIG.3Billustrates change of the current Ices in accordance with the film thickness W of the electric field relaxation region17. In the present example, the film thickness W of the electric field relaxation region17is changed to 0 μm, 0.3 μm, 0.6 μm, or 0.9 μm. The greater the film thickness W of the electric field relaxation region17, the easier it is for the depletion layer to extend in the depth direction, and the greater the electric field relaxation effect. Accordingly, a rise of the current Ices is suppressed in accordance with the film thickness W of the electric field relaxation region17increasing. FIG.4Aillustrates a relationship between a peak concentration of the accumulation region16and the film thickness W of the electric field relaxation region17. The vertical axis indicates the film thickness W (μm) of the electric field relaxation region17, and the horizontal axis indicates the peak concentration (cm−3) of the accumulation region16. In the present example, illustration is given for the film thickness W of the electric field relaxation region17that is necessary in order to relax the electric field in accordance with the peak concentration of the accumulation region16. The size of the film thickness W of the electric field relaxation region17that is necessary to suppress the leakage current differs in accordance with the peak concentration of the accumulation region16. In the electric field relaxation region17, it is possible to make it easier for the depletion layer to expand and relax concentration of the electric field. The thicker the film thickness W of the electric field relaxation region17, the higher an effect by which the electric field is relaxed and the leakage current is suppressed. The higher the peak concentration of the accumulation region16, the less likely it is for the depletion layer to expand, and thus the electric field is likely to be concentrated. The lower the doping concentration of the accumulation region16, the more likely it is for the depletion layer to expand, and the more likely it is for the electric field to be dispersed. Accordingly, the greater the peak concentration of the accumulation region16, the greater the film thickness W of the electric field relaxation region17that is necessary in order to suppress the leakage current. For example, the doping concentration of the accumulation region16is greater than or equal to 1E16 cm−3and less than or equal to 4E16 cm−3. When the doping concentration of the accumulation region16is 1E16 cm−3, the film thickness W of the electric field relaxation region17is 0.4 μm. When the doping concentration of the accumulation region16is 2.5E16 cm−3, the film thickness W of the electric field relaxation region17is 1.0 μm. When the doping concentration of the accumulation region16is 3E16 cm−3, the film thickness W of the electric field relaxation region17is 1.3 μm. When the doping concentration of the accumulation region16is 4E16 cm−3, the film thickness W of the electric field relaxation region17is 1.8 μm. When the film thickness W of the electric field relaxation region17is too thick, the accumulation region16may be present at a deep location that is the trench bottom, and thus a drop in the breakdown voltage occurs. Accordingly, a drop of the breakdown voltage is suppressed by making the film thickness W of the electric field relaxation region17be 3.0 μm or less. Note that the film thickness W of the electric field relaxation region17may be thicker than the values in the present example. FIG.4Billustrates a relationship between the peak concentration of the accumulation region16and an integrated concentration of the electric field relaxation region17. The vertical axis indicates the integrated concentration (cm−2) of the electric field relaxation region17, and the horizontal axis indicates the peak concentration (cm−3) of the accumulation region16. The integrated concentration of the electric field relaxation region17indicates a value calculated by integrating the doping concentration distribution within the range of the film thickness W of the electric field relaxation region17. For example, the integrated concentration of the electric field relaxation region17is greater than or equal to 5E14 cm−2and less than or equal to 5E15 cm−2. By appropriately setting the integrated concentration of the electric field relaxation region17, the electric field between the base region14and the electric field relaxation region17is relaxed, and it is possible to suppress the leakage current. The leakage current indicates the leakage current for the current Ices that flows between the collector electrode24and the emitter electrode52. FIG.4Cillustrates a relationship between the peak concentration of the accumulation region16, the film thickness W of the electric field relaxation region17, and the integrated concentration of the electric field relaxation region17. A film thickness W of the electric field relaxation region17is set so that it is possible to suppress a leakage current between C-E when a high voltage is applied. In one example, the film thickness W of the electric field relaxation region17is set so that the electric field between the accumulation region16and the base region14is relaxed, and the leakage current is suppressed. For example, the film thickness W of the electric field relaxation region17is greater than or equal to the film thickness of the accumulation region16. By thickening the film thickness of the electric field relaxation region17, it is easier to suppress the leakage current. The film thickness W of the electric field relaxation region17may be less than or equal to the film thickness of the accumulation region16. The film thickness W of the electric field relaxation region17may be greater than or equal to 0.4 μm and less than or equal to 3.0 μm. The film thickness W of the electric field relaxation region17may be greater than or equal to 1.0 μm and less than or equal to 1.8 μm. The film thickness W of the electric field relaxation region17may be greater than or equal to 1.5 μm and less than or equal to 2.0 μm. Furthermore, the integrated concentration of the electric field relaxation region17may be greater than or equal to 5E14 cm−2and less than or equal to 5E15 cm−2. FIG.5illustrates an example of an enlarged view of a cross-section view of the semiconductor device100according to embodiment. This drawing is an enlarged view of a mesa portion60sandwiched between an adjacent dummy trench portion30and an adjacent gate trench portion40. A width W1 indicates the interval between the center of the dummy trench portion30and the center of the gate trench portion40. In other words, the width W1 is the pitch of the trench portions. A width W2 indicates the width of the mesa portion60. A length L1 is the film thickness of the emitter region12. The length L1 corresponds to the film thickness from the front surface21of the semiconductor substrate10to the depth D1. For example, the length L1 is greater than or equal to 0.3 μm and less than or equal to 0.8 μm. A length L2 is the film thickness of the base region14. The length L2 corresponds to the film thickness from the depth D1 to the depth D2. A length W is the film thickness of the electric field relaxation region17. The length W corresponds to the film thickness from the depth D2 to the depth D3. For example, the length W is greater than or equal to 0.4 μm and less than or equal to 3.0 μm. A length L4 is the film thickness of the accumulation region16. The length L4 corresponds to the film thickness from the depth D3 to the depth D4. In one example, the film thickness of the accumulation region16is greater than or equal to 0.5 μm and less than or equal to 1.5 μm. For example, the film thickness of the accumulation region16is 1.0 μm. A length L5 is the distance from the lower end D4 of the accumulation region16to the lower end of the dummy trench portion30or the gate trench portion40which protrude on the lower side beyond the bottom surface of the accumulation region16. It is desirable that the accumulation region16has a film thickness of a level so as to not go beyond the lower end of the dummy trench portion30or the gate trench portion40. In a semiconductor device that has trench portions, the density of holes implanted from a collector in accordance with conductivity modulation decreases as the emitter is approached. As a result, the carrier density becomes lower on the emitter side, and it is not possible to make the ON resistance be sufficiently low. By the semiconductor device100of the present example providing the accumulation region16below the base region14, it is possible to improve the carrier density on the emitter side. In this manner, by increasing the maximum value of the doping concentration in the accumulation region16, it is possible to decrease the ON resistance and the ON voltage of the semiconductor device100. In contrast, when the total dose amount in the accumulation region16becomes too large, the electric field between the base region14and the accumulation region16becomes large and thus a leakage current occurs. Accordingly, it is desirable for the film thickness W of the electric field relaxation region17to be set in a range that enables the electric field between the base region14and the accumulation region16to be sufficiently relaxed. In one example, it is desirable for the film thickness W of the electric field relaxation region17to be smaller than the length L4 which is the film thickness of the accumulation region16. The film thickness W of the electric field relaxation region17is also less than or equal to the total of L1+L2 which is the lengths of the emitter region12and the base region14. The film thickness W of the electric field relaxation region17may be less than or equal to the length L2 of the base region14. The film thickness W of the electric field relaxation region17may be less than or equal to the length L5 of the protruding section of the gate trench portion40or may be less than or equal to half of L5. Meanwhile, by having the accumulation region16be a low doping concentration, it is easier for the depletion layer to expand, and it is possible to relax concentration of the electric field. Even in this case, an electric field relaxation region17that is greater than or equal to 0.4 μm may be provided. FIG.6illustrates another example of a doping concentration distribution in the depth direction of the semiconductor device100according to the embodiment. The semiconductor device100of the present example has a peak P3 in the electric field relaxation region17. The peak P3 is provided in the electric field relaxation region17. The peak P3 is lower than the half-value Ph of the peak P2. It is sufficient if the doping concentration of the electric field relaxation region17is a value that is lower than the half-value Ph of the peak P2 of the accumulation region16. The electric field relaxation region17may have a plurality of stepped peaks. Even in this case, each stepped concentration of the electric field relaxation region17which is formed with a plurality of steps may have any value as long as it is a value that is less than the half-value Ph of the peak P2 of the accumulation region16. For example, toward the back surface23of the semiconductor substrate10, the doping concentration of the electric field relaxation region17may gradually increase or may gradually decrease. It is sufficient if the profile of the doping concentration is that the integrated concentration of the electric field relaxation region17is greater than or equal to 5E14 cm−2and less than or equal to 5E15 cm−2, but there is no limitation to this. The present invention is described above using an embodiment, but the technical scope of the present invention is not limited to the scope of what is set forth in the embodiment above. That it is possible to add various modifications or improvements to the embodiment described above is obvious to a person skilled in the art. That an embodiment to which these various modifications or improvements have been added to can still be included in the technical scope of the present invention is obvious from what is set forth in the claims. EXPLANATION OF REFERENCES 10: semiconductor substrate,12: emitter region,14: base region,15: contact region,16: accumulation region,17: electric field relaxation region,18: drift region,20: buffer region,21: front surface,22: collector region,23: back surface,24: collector electrode,26: insulating film between layers,30: dummy trench portion,32: dummy insulating film,34: dummy conductive portion,40: gate trench portion,42: gate insulating film,44: gate conductive portion,52: emitter electrode,54: contact hole,60: mesa portion,100: semiconductor device,500: semiconductor device,512: emitter region,514: base region,516: accumulation region,518: drift region | 41,121 |
11942536 | DETAILED DESCRIPTION Reference will now be made to the illustrative embodiments depicted in the drawings, and specific language will be used here to describe the same. It will nevertheless be understood that no limitation of the scope of the claims or this disclosure is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the subject matter disclosed herein. Other embodiments may be used and/or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to be limiting of the subject matter presented. This application relates to vertically oriented transistor devices and their methods of manufacture. More specifically, described herein are structures in which the current between the drain and source is primarily in the direction normal to the surface of the die, e.g., vertical field-effect transistor (VFET) and Complementary Field Effect Transistor (CFET) structures. Electronic devices (e.g., transistors) are conventionally formed in horizontal planar configurations. However, limitations on the amount of area and required density of devices in a given footprint increasingly necessitate the use of novel structures. The present application provides devices that can be oriented in a vertical direction, such that current flows in the vertical or z-direction allowing arrays of transistors to be stacked relative to the primary planar surface of the array or underlying substrate. Further, the devices, as disclosed herein, can each include two or more 2D materials extending to form a quantum well, which allows 2D electrode or hole gas to be formed therein. The electron or hole flow of respective devices can be improved/enhanced with the implementation of the 2D materials extended between the source and drain, for example. According to the techniques described, 3D VFET devices may be created on any suitable substrate including conductive, semiconductive, or dielectric substrates. The underlying substrate may be a passive structure such as a handle wafer or passive interposer, or may have active devices, such as memory devices, circuitry, etc. Advantageously, VFETS may be provided above other active devices allowing for close proximity between devices. The VFETS may also be stacked as all one conductivity type, e.g., N-type or P-type or the conductivity type may be combined, such one or more N-type devices over or under one or more P-type devices in the stack. Such configurations may include, but are not limited to so-called CFETs, e.g., complementary Field Effect Transistors. CFET structures may include a gate-all-around (GAA) structure. According to certain implementations, one or more transistor structures are formed by stacking layers to form a source (or drain), gate, and drain (or source) separated by one or more dielectric layers to isolate each portion of the transistor. The channel may be oriented in a z-direction, i.e., perpendicular to the direction that the layers are stacked. A high k dielectric material may be provided between the gate and the channel as will be described more fully below. A general process flow for implementing the vertical CFET with 2D materials can be described below as an example process. The example process may be combined or augmented without departing from the scope of this disclosure. The techniques provided herein can utilize conductive dielectric materials (sometimes referred to herein as “conductive channels”), which may have similar properties to semiconductor materials, to fabricate vertical 3D transistors. For example, certain materials, when combined with oxygen, may form new materials that exhibit semiconductor properties (e.g., it can turn “off” with low off-state leakage current, or can become highly conductive under certain circumstances, etc.). Some examples of N-type conductive channels include In2O3, SnO2, InGaZnO, and ZnO. One example of a P-type conductive channel is SnO. Additionally, the channel can include multiple 2D materials. The 2D materials can form on a sidewall (sometimes referred to as the inner surface or canal) of the channel (e.g., deposited on oxide). Some examples of the 2D materials for use in forming the channel include, but are not limited to, LaAIO3, SrTiO3, n-aluminum gallium arsenide (n-AlGaAs), i-gallium arsenide (i-GaAs), semi-gallium arsenide (SI—GaAs), graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. These materials may be deposited by an atomic layer deposition (ALD) process and may be, for example, 5-15 angstroms thick, the thinness lending to their name—2D material. The materials may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics. Certain 2D materials (e.g., a combination of two or more 2D materials interfacing or in contact with each other) can be used herein as examples. The combination of 2D materials can be predetermined to form/create/generate a quantum well (e.g., a 2D gas channel, 2D layer, trench, among other similar terms) in response to an interface between the materials. In some cases, the 2D materials formed within the channel may be referred to as a channel structure. Further, various techniques may be implemented to form the high-k barrier between the channel structure (e.g., at least one of the 2D materials) and the gate electrode. One such technique utilizes a selective deposition of a high-k dielectric to form the transistor gates. In some implementations, a gate-recessing technique is utilized to allow a more uniform layer of doped conductive oxide material to form along the sidewall of the opening. Another similar technique provides a non-selective deposition of the high-k dielectric in the gate-recessed opening in conjunction with self-aligned directional etching. These techniques may also be implemented to fabricate stacked transistors of the same type by utilizing the same conductive oxide for two or more transistor layers. These and other aspects are described in further detail herein. Reference will now be made to the Figures, which for the convenience of visualizing the 3D fabrication techniques described herein, illustrate a substrate undergoing a process flow in cross-sectional views. Certain Figures can illustrate or present a top view of the substrate undergoing the process flow. Each Figure may represent one (or a set) of fabrication steps in a process flow for manufacturing the devices described herein. In the cross-sectional views of the Figures, connections between conductive layers or materials may be shown. However, it should be understood that these connections between various layers and masks are merely illustrative and are intended to show a capability for providing such connections and should not be considered limiting to the scope of the claims. Likewise, although the Figures and aspects of the disclosure may show or describe devices herein as having a particular shape, it should be understood that such shapes are merely illustrative and should not be considered limiting to the scope of the techniques described herein. For example, although certain figures show various layers defining transistor structures or other electric structures in a circular configuration, other shapes are also contemplated, and indeed the techniques described herein may be implemented in any shape or geometry. In addition, examples in which two transistors or devices are shown stacked on top of one another are shown for illustrative purposes only, and for the purposes of simplicity. Indeed, the techniques described herein may provide for one to any number N stacked devices. Although the devices fabricated using these techniques are shown as transistors, it should be understood that any type of electric or electronic device may be manufactured using such techniques, including but not limited to transistors, variable resistors, resistors, and capacitors. FIGS.1-8show a process flow for the manufacture of 3D VFET or vertical CFET transistor stacks, or other types of electric or electronic devices, with 2D materials. Each of theFIGS.1-8generally refer to one or more process steps in a process flow, each of which are described in detail in connection with the respective Figure. For the purposes of simplicity and ease of visualization, some reference numbers may be omitted from some Figures. As used herein, the terms “first,” “second,” “third,” and “fourth” with respect to particular layers of the stack shown inFIGS.1-8refer to the order of the layers relative to substrate102(e.g., base substrate), or in some cases the dielectric112. For example, a “first” layer of a particular type refers to the specified type of layer which is closest to the substrate102. Likewise, a “second” layer of a particular type refers to the specified type of layer which is second closest to the substrate102, and so on. In another example, a “first” layer may refer to a layer closest to the dielectric112. Similarly, the “second” layer may refer to a second closest layer to the dielectric112, etc. Referring toFIG.1, illustrated is a cross-sectional view100of a stack of layers of a device with a channel. A substrate102can be provided which may be active or passive and may comprise dielectric, conductive, or semiconductive materials or any combination thereof. The substrate102may be referred to as a base substrate or its respective material or composition. One or more dielectric layers104(e.g., shown as “Dielectric 1” in the legend) may be provided on the substrate102, among other portions of the VFET structure, to isolate the VFET structure from the underlying substrate (e.g., substrate102). The dielectric layers104may sometimes be referred to as an isolation layer, insulation layer, among other similar terms. The dielectric layers104can be formed or composed of any type of dielectric material described herein that is capable of being disposed, patterned, or otherwise provided on the various layers described herein. Some examples of dielectric materials can include, but are not limited to, oxide materials. The substrate102may remain in the final structure or may be removed during or after the formation of the VFET structure. A first dielectric layer104(or layers) may be provided or formed on top of the substrate102. The term source/drain (S/D) will be used to describe layers that may be used as either a source or a drain of a transistor structure. The first S/D layer106(e.g., shown as “Metal 1” in the legend) may be formed directly on the substrate102or on the one or more dielectric layers104described above, such as the first dielectric layer104. The S/D layers106may be any type of conductive metal suitable to form a source or drain electrode in a semiconductor device, including copper, gold, silver, platinum, nickel, tungsten, ruthenium, or other types of conductive metals or alloys. Each S/D layer106can be separated by at least one dielectric layer104or a portion of the dielectric material. For instance, a second dielectric layer104can be formed on the first S/D layer106formed/located/positioned on the first dielectric layer104. Further, herein, certain metals (e.g., S/D layers106, gate layer108, or gate layer110) can be separated from each other by one or more dielectric layers104, among other dielectric layers. The deposition or addition of layers in the stack may be performed using any type of material deposition technique, including but not limited to ALD, chemical vapor deposition (CVD), and physical vapor deposition (PVD). The techniques for forming these stacked layers is well documented elsewhere and, thus, will not be described in detail herein. A gate layer108(e.g., shown as “Metal 2” in the legend) may then be formed on top of the second layer of the dielectric layer104above the first S/D layer106. A third dielectric layer104can be formed on the gate layer108. Subsequently, a second S/D layer106may be formed on the third dielectric layer104above the gate layer108. The gate layer108may be a different material than the first and second S/D layers106. A fourth dielectric layer104may then be deposited, formed, or added on top of the second S/D layer106to complete/form/compose/structure a first transistor structure. For instance, a collection of at least the first and second S/D layers106and the gate layer108can form the first transistor structure. As shown in the cross-sectional view100, a transistor structure can include multiple dielectric layers (with the first transistor having one dielectric layer be the dielectric layer104, which separates the first transistor structure from the substrate102) and three conductive metal layers (e.g., the two S/D layers106and one gate layer108). Subsequent transistor structures may be stacked above the first transistor structure, by depositing similar layers. For instance, above the first transistor structure, a second transistor structure may be formed using one or more of the processes described above. In this case, a fourth dielectric layer104can be formed on top of the second S/D layer106. A third S/D layer106can be formed on the fourth dielectric layer104. A fifth dielectric layer104can form on the third S/D layer106. A gate layer110can form on the fifth dielectric layer104. The gate layer110(e.g., a second gate layer) may include or be composed of a different material from the gate layer108(e.g., a first gate layer). A sixth dielectric layer104can form on the gate layer110. A fourth S/D layer106can form on the gate layer110. Accordingly, the collection of at least the third and fourth S/D layers106and the gate layer110can form a second transistor structure. One or more dielectric layers104(e.g., insulation dielectric layers) may be deposited/formed/added/provided between adjacent transistor structures. These layers in the stack of layers may be formed without a mask, such that each layer forms a blanket layer over the prior layer. In some cases, once the layers are formed, each VFET structure or vertical group of VFET structures may be patterned to separate adjacent transistor structure stacks isolated in the x-y plane (e.g., where the x-y plane is perpendicular to the z-direction). The patterning process to separate adjacent transistor structure stacks herein can leverage, include, or utilize any type of patterning process. In some implementations, electrical connections between transistor structures may be formed by patterning the conductive layers described herein, as well as by forming vias to electrically connect different layers. In some other cases, electrical connections between transistor structures may be formed by adding, including, or forming one or more 2D materials between the different layers or from one layer to another. As such, transistor stacks that are isolated in the x-y plane may be electrically connected with one another to form logical or electronic circuits. As shown in this example process flow, one or more layers of dielectric104may be utilized to isolate adjacent transistors from each other (e.g., as shown above, the second S/D layer106or below the third S/D layer106of a second transistor structure). Once the desired number of transistors stacks have been formed, such as two transistors in this example of a vertical CFET structure, a final/last/top-most dielectric layer112(shown as “Dielectric 2” in the table/legend) may be formed. In this case, the dielectric layer112can be formed on or above the second transistor structure or on the fourth S/D layer106of the second transistor structure. Different types of gate metals may be used to form different types of transistors, or to form transistors with desired electronic properties. As shown in the cross-sectional view100, the second transistor structure has a gate layer formed from a layer of metal110(shown in the legend as “Metal 3”), different from the first transistor structure which has a gate layer formed from a layer of metal108(shown in the legend as “Metal 2”). Different metals may be used to pattern or use different high-k gate dielectrics (e.g., the high-k dielectric114or the high-k dielectric116), which may be suitable for either N-type or P-type vertical transistors. In some implementations, the first transistor structure can include or be composed of the gate layer108with a high-k gate dielectric suitable, compatible, or configured for an N-type vertical transistor. The second transistor structure can include or be composed of the gate layer110with a high-k gate dielectric suitable, compatible, or configured for a P-type vertical transistor. In some other implementations, the first transistor structure and the second transistor structure can be configured/structured/composed for a P-type vertical transistor or an N-type vertical transistor, respectively. Once the stack of layers has been constructed using material deposition techniques, the process flow proceeds to the next stage. Either before or after patterning the structures, one or more channels (sometimes referred to as a canal, “transistor body openings”, or tunnel of the transistor body) may be formed. To form the channels, a mask (e.g., of a photoresist or other suitable masking material) may be formed over the final dielectric layer112, with openings that define the x-y cross-section of the channels. The opening that defines the x-y cross-section of the channels can be formed at portion126of the device, for example. The opening can be formed as a circle, among other shapes, from the dielectric layer112to at least the first S/D layer106. In this case, the channel can be formed extending from the dielectric layer112beyond (e.g., below) the first S/D layer106, such as to the first dielectric layer104. As shown inFIG.1, in this example, the channel may not extend to the substrate102. In some cases, the channel can extend up to an intermediate (e.g., midsection) of the first dielectric layer104or extend from the dielectric layer112past the first S/D layer106. In some other cases, the channel can extend beyond the intermediate of the first dielectric layer104. One or more etch techniques may be performed to remove the portion of the underlying layers aligned with the opening in the mask to form the transistor body opening. Any type of suitable etching techniques may be used, including but not limited to dry etching, wet etching, or plasma etching techniques. The mask may be removed once the channel openings are defined or may be retained to protect the underlying surface or to remain as part of the final structure. FIG.2illustrates a cross-sectional view200of a device shown in the next stage of the example process flow. Once the channel opening(s) are defined, one or more of the gate layers108may be etched in the x-y direction (e.g., outward from the center of the transistor body opening) to recess the gate from the channel. The etching process may be a selective etching process that etches the gate layers108to create recessed regions of a predetermined volume, by etching the gate layers108(the gate metal) by a predetermined amount. As shown inFIG.2, the etching process can be performed at portion128of the gate layer108, in this example. Referring to the next stage of the process flow,FIG.3illustrates a cross-sectional view300of a device. A gate dielectric, such as a high-k dielectric114(e.g., labeled as “High-k1”), may be selectively formed on the gate layer108. The high-k dielectric114can be grown such that a predetermined amount of high-K dielectric114fills the recessed region of the gate layers108. Additionally or alternatively, the high-K dielectric114may be formed on recessed or non-recessed gate layer108so as to extend into the channel opening. The high-k dielectric114material may be selected to have desired attributes or properties, such as a desired dielectric constant. Likewise, the high-k dielectric114may be grown to create a predetermined separation distance between the gate layer108and the central channel of the transistor structure. The high-k dielectric114and the high-k dielectric116can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The resulting gate dielectric114(e.g., the inner wall or surface facing the center or focus of the transistor body opening) may be formed (or formed and then etched) to be slightly recessed, flush, or slightly protruding relative to the channel opening depending on the desired device characteristics and process parameters. If multiple devices, such as N-type and P-type devices, are exposed in the opening, suitable dielectrics and thicknesses may be provided to each gate to achieve the desired characteristics. Deposition control may be achieved using specific materials for each gate layer108and selecting the gate dielectric114to form selectively on that gate layer. At a next stage of the process flow,FIG.4illustrates a cross-sectional view400of a device. As shown, a first 2D material118(e.g., labeled as “2D Material 1”) can be deposited or inserted into the channel (e.g., transistor body opening). The first 2D material118can be deposited using any deposition, lining (e.g., forming a liner structure by one or more etching processes after deposition), or filming technique(s). The first 2D material118can line, coat, or cover the sidewall, surface, or portions of the channel. The first 2D material118can be a sheet, a layer, or a lining of a predetermined thickness or depth forming within the channel. For example, the first 2D material118, when deposited into the channel, can form a liner or film thereby reducing the overall diameter of the transistor body opening. In this example, the first 2D material118can form at least a part/portion of a channel structure (e.g., another channel having a diameter or radius less than the channel formed at the processes described inFIGS.1-3). Once deposited, the first 2D material118can form or be a part of the transistor body opening, the device, or the transistor (e.g., the first transistor in this process). The deposited first 2D material118can extend from the opening, entrance, or top of the channel to the bottom/lowest portion of the channel. In certain cases of this process, the first 2D material118may be deposited to extend from the bottom of the channel up to the second S/D layer106or the fourth dielectric layer104, for example. In this example, the deposited first 2D material118may not extend above/over/beyond the second S/D layer106or the fourth dielectric layer104. Therefore, when performing one or more etching procedures (e.g., at leastFIG.5), the first 2D material118may be maintained at the same vertical height, for example. Otherwise, etching operation(s) can be performed to shorten or reduce the height of the first 2D material118, among other materials, metals, etc. After depositing the first 2D material, a second 2D material (e.g., labeled as “2D Material 2”) can be deposited. The second 2D material may be thinner, thicker, or the same thickness as the first 2D material. The thickness of the 2D material can be based on the selected material. The second 2D material120can be deposited in a similar matter as the first 2D material118, such as on the sidewalls of the channel. Since the first 2D material118is deposited, the second 2D material120can be deposited on the sidewalls or surface formed by the first 2D material118. The second 2D material120may extend from the bottom of the channel to a similar height as the deposited first 2D material118. In some cases, the deposited second 2D material120may be higher or lower than the first 2D material118. The deposited first 2D material118and second 2D material120can form a whole channel structure or portions of the channel structure. In some cases, additional 2D materials (e.g., third 2D material, fourth 2D material, etc.) may be deposited having similar or varying dimensions including thickness, height/altitude, etc. The second 2D material120can be any material predetermined or preselected to form a quantum well (e.g., a 2D gas layer122, sometimes referred to as a 2D gas channel) at an interface between the first 2D material118and the second 2D material120, such as when applying voltages. The second 2D material120can be based on the selected first 2D material118. For example, if the first/second 2D material is a crystal substrate (e.g., SrTiO3), the second/first 2D material can be a thin film crystal (e.g., LaAlO3). In another example, if the first/second 2D material is graphene, the second/first 2D material can be TMDs. In some cases, the 2D gas layer122may be formed at one or more interfaces between more than two 2D materials. Accordingly, the 2D gas layer122can be formed between the interfaced or connected first 2D material118and the second 2D material120. Based on the type of transistor, the 2D gas layer122may correspond to 2D electron gas (2DEG) (e.g., for n-type FET or NMOS) or a 2D hole gas (2DHG) (e.g., for p-type FET or PMOS). The second 2D material may be shown or described in at leastFIG.10. In some implementations, the second 2D material120may be deposited before the first 2D material118. For example, the second 2D material120can be deposited into the channel (e.g., similar to the deposition of the first 2D material118as shown in conjunction withFIG.4). In this example, after depositing the second 2D material120, the first 2D material118can be deposited. Accordingly, the transistor body opening can be first (or second) filled with any one of the first 2D material118or the second 2D material120, among other 2D materials to form the 2D gas layer122. In some cases, one or more etching processes can be performed following the respective deposition of the first 2D material118and/or the second 2D material120. For instance, the process can include depositing and etching the first 2D material118, and depositing and etching the second 2D material120, or vice versa. In this case, the etching process for the respective 2D materials may form the opening that defines another x-y cross-section of the channels. Referring toFIG.5, in the next stage of the process flow, a cross-sectional view500of a device can be shown. Subsequent to/after depositing two or more layers, liners, or films of 2D materials (e.g., upon forming the first 2D material118and the second 2D material120), a first dielectric layer124(e.g., labeled as “dielectric 3”) can be deposited, inserted, or formed to fill in the channel structure. For instance, the first dielectric layer124can fill the lower portion (e.g., at least below the third S/D layer106) of the transistor body opening via a deposition process. The dielectric 3 may refer to different materials from the dielectric 2 and/or the dielectric 1. The first dielectric layer124may be deposited using any suitable deposition technique. The first dielectric layer124may include a predetermined type or selection of dielectric material. The first dielectric layer124can be deposited to fill the hollow or empty portions of the channel structure surrounded or encircled by layers of 2D materials. In some cases, the first dielectric layer124may be filled up to a similar height as one or more of the 2D materials, such as up to the second S/D layer106. In some other cases, the first dielectric layer124may be filled higher or lower than the deposited 2D material(s). Accordingly, once the 2D materials (e.g., the first 2D material118and the second 2D material120) and the first dielectric layer124is situated, deposited, located, or positioned in the channel of the transistor body opening, the channel can be filled (or substantially filled) from the bottom of the channel vertically to at least the second S/D layer106. In some cases, the 2D materials and the first dielectric layer124can be filled up to the dielectric layer112of the device (e.g., above the second transistor). As shown, the first S/D layer106, the second S/D layer106, and the gate layer108can sound respective portions of the channel structure formed by the 2D materials, and the channel structure can surround the first dielectric layer124. The first dielectric layer124in this example (e.g., shown inFIG.5) may be referred to as a first dielectric core or a first dielectric layer of the device. Additionally or alternatively, some or all of the core area may be left empty to leave an air gap (not shown). If an air gap is desired, the core area may be sealed at an upper end using a capping material to prevent unwanted debris, liquid, moisture, or other material from entering the gap and potentially affecting the devices. Subsequent to depositing the first dielectric layer124, one or more suitable etchants can be utilized to etch or remove at least a portion of the 2D materials and the first dielectric layer124. This can result in the removal of materials within the channel in the z-direction to lower the height of the first dielectric layer124. In this example, the materials deposited into the channel can be removed or etched back/down to a portion of the second S/D layer106. In some cases, the materials in the channel may be etched down to a portion of the fourth dielectric layer104. In some implementations, in this process, the channel structure may be vertically flush (e.g., in the z-direction) with the first dielectric layer124. In some other implementations, in this process, the channel structure may be higher or lower in the z-direction compared to the first dielectric layer124. The channel structure of this process may be referred to as a first channel structure. The first channel structure may exceed up to, without being at, the portion of the channel surrounded by the third S/D layer106, for example. Referring toFIG.6, as the next process of the process flow, a cross-sectional view600of a device can be shown. A second dielectric layer124can be deposited into the channel subsequent to or responsive to etching the first channel structure and the first dielectric core. As shown, the second dielectric layer124can reside in the channel at a portion surrounded by the fourth dielectric layer104. The second dielectric layer124can fill, cover, or mask the channel opening at this portion. For example, the second dielectric layer124can be located between the second S/D layer106and the third S/D layer106. The second dielectric layer124may separate the first transistor from the second transistor. In some implementations, the second dielectric layer124may include a similar material as the first dielectric layer124. In some other implementations, the second dielectric layer124may include a different material compared to the first dielectric layer124. In certain cases, the second dielectric layer124may be deposited up to the desired level or height in the channel. In some other cases, the second dielectric layer124may fill the remaining or empty portions of the channel, and be etched back to the desired level. Prior to or after depositing the second dielectric layer124, another etching process can be performed at a portion of the gate layer110, for instance, similar to etching the gate layer108. For example, one or more of the gate layers110may be etched in the x-y direction (e.g., outward from the center of the transistor body opening) to recess the gate from the channel. The etching process may be a selective etching process that etches the gate layers110to create recessed regions of a predetermined volume, by etching the gate layers110(the gate metal) by a predetermined amount. The gate layer110may be etched to a similar depth as the gate layer108. In some cases, the gate layer110may be etched more than or less than the gate layer108. Another gate dielectric, such as a high-k dielectric116(e.g., labeled as “High-k2”), may be selectively formed on the gate layer110. The high-k dielectric116can be grown such that a predetermined amount of high-K dielectric116fills the recessed region of the gate layers110. Additionally or alternatively, the high-K dielectric116may be formed on recessed or non-recessed gate layer110so as to extend into the channel opening. The high-k dielectric116material may be selected to have desired attributes or properties, such as a desired dielectric constant. Likewise, the high-k dielectric116may be grown to create a predetermined separation distance between the gate layer110and the central channel of the transistor structure. In some implementations, the high-k dielectric116can fill the recessed region of the gate layer110in a similar manner as the high-k dielectric116filling the recessed region of the gate layer108, for example. The high-k dielectric116can be different from the high-k dielectric114, such as to support a different type of transistor. For example, the material of the high-k dielectric114may be selected to support an N-type device and the high-k dielectric116may be selected to support a P-type device or vice versa. Referring toFIG.7, in the next stage of the process flow, a cross-sectional view700of a device can be shown. A first 2D material130(e.g., labeled as “2D material 3”) can be deposited or inserted into the channel subsequent to the second dielectric layer124and/or growing the high-k dielectric116. Subsequently, a second 2D material132(e.g., labeled as “2D material 4”) can be deposited into the channel or overlaying the first 2D material130, thereby forming a second channel structure. For example, the first 2D material130and the second 2D material132can form the second channel structure. In some cases, one or more other 2D materials may be deposited over the second 2D material132. The first 2D material130and/or the second 2D material132may be deposited in one or more similar manners to depositing the first 2D material118and/or the second 2D material120of the first channel structure as described in the process flow ofFIG.4. For example, the second channel structure (e.g., the first 2D material130and the second 2D material132above the first channel structure) may be deposited on the sidewall of the channel above the first transistor (or above the second dielectric layer124). The first 2D material130and the second 2D material132can include a respective predetermined thickness. The thickness of the first 2D material130and the second 2D material132of the second channel structure can be different from the 2D materials of the first channel structure. The first 2D material130and the second 2D material132can interface to form a 2D gas layer (e.g., similar to or different from 2D gas layer122). In some cases, the first 2D material130may sometimes be referred to as a third 2D material associated with the second channel structure, and the second 2D material132may sometimes be referred to as a fourth 2D material. The first 2D material130and/or the second 2D material132may be the same as or different from the first 2D material118and/or the second 2D material120. For example, the 2D materials of the first channel structure may be formed to support or be configured for a first type of transistor (e.g., NMOS or PMOS, respectively), and the 2D materials of the second channel structure may support a second type of transistor (e.g., PMOS or NMOS, respectively). In a further example, the second channel structure can extend from the top of the second dielectric layer124(or at the third S/D layer106portion of the channel) to at least the fourth S/D layer106. In some cases, the second channel structure can extend up to the dielectric layer112. In some cases, the vertical length or height of the second channel structure can be comparable (e.g., similar height) to the first channel structure. In some other cases, the second channel structure may be shorter or higher compared to the first channel structure. Similar to the process described in at leastFIG.4, the 2D materials can be preselected or predetermined to form the 2D gas layer122, such as responsive to applying voltages to the device. In some implementations, the predetermined materials of the 2D materials between the first and second channel structures may be the same. In some other cases, the 2D materials may be different between the first channel structure and the second channel structure. Referring toFIG.8, in the next stage of the process flow, a cross-sectional view800of a device can be shown. Subsequent to depositing two or more layers, liners, or films of 2D materials, a third dielectric layer124can be deposited in the channel structure. The first dielectric layer124may be deposited using any suitable deposition technique, such as in similar procedures or operations as described in conjunction withFIG.5. The third dielectric layer124may be referred to as a second dielectric core, which can be surrounded by at least the second channel structure, the third S/D layer106, the fourth S/D layer106, and the gate layer110, for example. The third dielectric layer124may be the same or different material compared to at least one of the first dielectric layer124or the second dielectric layer124. The third dielectric layer124can be deposited to fill the remaining (e.g., hollow or empty) portions of the channel structure surrounded or encircled by layers of 2D materials of the second channel structure. In some cases, the third dielectric layer124may be filled up to a similar altitude or height as the second channel structure, such as up to the fourth S/D layer106or the dielectric layer112. In some other cases, the third dielectric layer124may be filled higher or lower than the deposited 2D material(s). Additionally or alternatively, some or all of the core area may be left empty to leave an air gap (not shown). If an air gap is desired, the core area may be sealed at an upper end using a capping material to prevent unwanted debris, liquid, moisture, or other material from entering the gap and potentially affecting the devices. Accordingly, the second transistor can be formed responsive to depositing the third dielectric layer124. In some implementations, the process to form the second transistor can be similar to the process to form the first transistor of the device. In some implementations, the process flow may be repeated for other portions of the device, such as to form a different vertical CFET, additional transistor(s), or different devices on top of the second transistor, for example. The stack may be further processed (e.g., using patterning and etching techniques at various stages in the process flows described herein) to provide wiring to gates and S/D regions (not shown). The stack may be bonded to other structures to create electronic or electric circuits, such as other logic circuits, memory circuits, sensors, or other devices. The structures may also be connected to circuits and devices underlying the stack in the base substrate102, if applicable. Connections may be formed between layers by forming vias and/or traces at appropriate stages in the process flow. This enables complex and dense logical circuits to be created in both the z-direction and the x-y directions. Referring now toFIG.9, depicted is a perspective view900of the device. As shown, the process flow described in at leastFIGS.1-8can form the device (e.g., vertical CFET). In this case, first S/D layer106and the third S/D layer106can correspond to or be used as the sources of the respective transistors. The second S/D layer106and the fourth S/D layer106can correspond to the drains of the respective transistors. The deposited 2D materials (e.g., the first channel structure and/or the second channel structure) can form a link, path, channel, or interface between the source and the drain. For example, the first channel structure can form a channel between the first source (e.g., first S/D layer106) and the first drain (e.g., second S/D layer106), and the second channel structure can form another channel between the second source (e.g., third S/D layer106) and the second drain (e.g., fourth S/D layer106). Accordingly, the first and second channel structures can facilitate electron flows between the drains and sources. Although the transistor body opening may be shown as circular (e.g., top of the perspective view900), other shapes, dimensions, or patterns can be formed as the transistor body opening to construct the vertical device. FIG.10illustrates a magnified view1000of 2D materials of the device. As shown, the first 2D material118may be deposited into the channel (or the opening of the transistor body), such that the first 2D material118is in contact with the sidewall of the channel. By being in contact with the sidewall, the first 2D material118can interface with at least one or more dielectric layers104, one or more S/D layers106, and/or one or more gate layers108or gate layers110. Subsequently, as shown, the second 2D material120may be deposited to interface with the first 2D material118. In some cases, more than two 2D materials may be deposited. The 2D gas layer122(e.g., quantum well) can be formed between the first 2D material118and second 2D material120. Although shown that the first 2D material118is thicker than the second 2D material120, in some cases, the first 2D material118may be thinner or of similar thickness compared to the second 2D material120. FIG.11illustrates a flow diagram of a method1100for fabricating a VFET with 2D materials using the process flows described in connection withFIGS.1-10. The method1100may include steps1102-1106. However, other embodiments may include additional or alternative steps, or may omit one or more steps altogether. The method1100can include or describe one or more materials, components, objects, layers, compositions, or structures in conjunction withFIGS.1-10. At step1102, the method1100can include forming a stack of layers. The stack of layers may include one or more transistor structures. For example, the stack of layers can include at least a first metal layer, a second metal layer, and a third metal layer. These metal layers can be isolated from one another with at least one dielectric material (e.g., one or more dielectric layers104). Each of the first metal layer, the second metal layer, and the third metal layer can correspond to one of a source metal, a drain metal, or a gate metal. For example, the first metal layer, the second metal layer, and the third metal layer may correspond to a first source metal (e.g., first S/D layer106), a first drain metal (e.g., second S/D layer106), and a first gate metal (e.g., gate layer108), respectively. The first layer stack may be associated with a first transistor structure (e.g., two S/D layers106with a gate layer108or110positioned in-between). The stack of layers may be formed to include multiple transistors structures. For example, the stack of layers may include a second layer stack including at least three layers of at least one conductive material (e.g., other two S/D metal layers106and the gate layer108or110positioned in-between) separated by one or more layers of at least one dielectric material (e.g., the dielectric layers104). The metals and the dielectric material(s) separating the metals can be positioned above a substrate (e.g., base substrate102). Further, the dielectric layer112, among other materials, can be positioned above the transistors. For example, with a two-transistors configuration, the dielectric layer112can be positioned above the second transistor or the top-most metal layer in this example. The second layer stack may be associated with a second transistor structure. Additional transistor structures may also be formed using similar techniques. The first and second transistor structures may be separated by one or more dielectric materials (e.g., the dielectric materials124or the second dielectric layer124). The stack of layers may be formed using techniques similar to those described in connection with at leastFIG.1. At step1104, the method1100can include forming a channel opening in/through the stack. The channel opening (sometimes referred to as the “transistor body opening”) may be formed using any type of suitable etching technique, similar to the techniques described in connection with at leastFIG.1. The transistor body opening may extend through each of the transistor structures in the stack of layers. After defining the channel opening, high-k gate dielectrics (e.g., the gate dielectrics or high-k dielectrics114or116) may be deposited on one or more of the gate layers (e.g., the gate layers108and/or110) in each transistor structure in the stack of layers. To do so, one or more of the gate layers may be recessed using techniques similar to those described in conjunction with at leastFIG.2or6, and the high-k gate dielectric materials may be subsequently deposited using techniques similar to those described in connection with at leastFIG.3or6. In some cases, the high-k gate dielectrics may be deposited at one of the recessed gate layers after one or more subsequent processes, such as an etching process. For example, a first high-k gate dielectric (e.g., high-k dielectric114) may be formed or deposited into the recessed region of a first gate layer (e.g., gate layer108). Subsequent to depositing other materials to form the first transistor and etching the materials in preparation for forming the second transistor (e.g., preparing to deposit 2D materials), the second gate layer (e.g., gate layer110) may be etched or recessed. In this case, the second high-k gate dielectric (e.g., high-k dielectric116) may be deposited in the recessed region, area, or portion of the second gate layer. Other materials can be deposited subsequently to form the high-k gate dielectric, such as to structure the second transistor, for example. The high-k gate dielectrics (e.g., the first high-k gate dielectric and the second high-k gate dielectric, among others) may be positioned or interposed between different materials. For example, the first high-k gate dielectric may be interposed between a first gate metal (e.g., gate layer108) and one of the 2D materials (e.g., a first 2D material or a second 2D material of the first transistor structure) deposited to the sidewalls of the channel (e.g., in subsequent process flow). Similarly, the second high-k gate dielectric may be interposed between a second gate metal (e.g., gate layer110) and one of the 2D materials (e.g., a third 2D material or a fourth 2D material of the second transistor structure). The first high-k gate dielectric may be different from the second high-k gate dielectric to support, conform, or be configured for different types of transistors (e.g., N-type or P-type). At step1106, the method1100can include lining at least the inner sidewalls of the channel opening (e.g., transistor body opening) with a first 2D material and a second 2D material. The first 2D material can interface with the second 2D material. The first 2D material and/or second 2D material can be coupled to the respective inner sidewalls of the first metal layer, the second metal layer, and the third metal layer. The lining of the sidewalls of the channel may include depositing or inserting the materials into or through the channel. Lining the inner sidewalls can form a first channel structure within the channel opening. For example, the first channel structure can be aligned with or positioned against the first transistor structure (e.g., the first, second, and third metals). The first channel structure may be deposited using techniques similar to those described in connection withFIG.4or7. By forming the first channel structure, the first source metal, the first drain metal, and the first gate metal can surround or encircle different portions of the first channel structure. For instance, the first source metal can surround a first portion, the first drain metal can surround a second portion of the first channel structure, and the first gate metal can surround a third portion of the first channel structure. In this case, the third portion can be in between the first portion and the second portion of the first channel structure. The first high-k gate dielectric can be interposed between the third portion of the first channel structure and the first gate metal. Subsequent to depositing the first and second 2D materials to form the first channel structure, dielectric materials forming a first dielectric core (e.g., first dielectric layer124) can be deposited into the first channel structure. The first dielectric core can be deposited in the channel opening lined with the first 2D material and the second 2D material. Accordingly, the first channel structure can extend along a portion of a sidewall of the channel and a bottom surface of the first dielectric core, such as described or shown in conjunction with at leastFIGS.5-10. In this case, the portion of the sidewall corresponding to the first channel structure may extend from at least the first portion to the third portion of the first channel structure. Further, the first channel structure may wrap or encapsulate the bottom of the first dielectric core. After depositing the 2D materials and the first dielectric core to form the first transistor structure, etching can be performed to remove materials from the channel, such as down to the top of or above the second portion of the first channel structure. Dielectric materials (e.g., dielectric materials124) can be deposited above the first transistor structure (e.g., above the second portion of the first channel structure). These dielectric materials can separate between the first and second transistor structures. In some cases, the dielectric materials can be etched back below or at the bottom of the second transistor structure, such as shown in conjunction with at leastFIGS.7-10. One or more processes can be repeated to form one or more additional transistors. For example, a third 2D material and a fourth 2D material can be deposited, lining different portions of the inner sidewalls of the channel opening. The third 2D material and/or fourth 2D material can be coupled to the respective inner sidewalls of a fourth metal layer, a fifth metal layer, and a sixth metal layer associated with the second transistor structure. In this case, the fourth metal layer, fifth metal layer, and sixth metal layer may refer to or correspond to a second source metal (e.g., third S/D layer106), a second drain metal (e.g., fourth S/D layer106), and a second gate layer (e.g., gate layer110), respectively. In this case, lining the inner sidewalls (e.g., the third and fourth 2D materials) can form a second channel structure within the channel opening. The first channel structure and the second channel structure may be separated by dielectric materials (e.g., dielectric material124). Further, the second source metal can surround a first portion of the second channel structure, the second drain metal can surround a second portion of the second channel structure, and the second gate metal can surround a third portion of the second channel structure. In this case, the third portion can be in between the first portion and the second portion of the second channel structure. The second high-k gate dielectric can be interposed between the third portion of the second channel structure and the second gate metal. Upon forming the second channel structure, dielectric materials (e.g., third dielectric layer124) forming a second dielectric core can be deposited into the second channel structure. The second channel structure can surround the second dielectric core which can extend in the channel opening lined with the third 2D material and the fourth 2D material. The second dielectric core can be disposed above the first dielectric core. Accordingly, the second channel structure can extend along another portion of the sidewall (e.g., at least from the first portion to the second portion of the second channel structure) of the channel and a bottom surface of the second dielectric core, such as described or shown in conjunction with at leastFIGS.7-10. In this case, the second channel structure may extend past or beyond the second portion of the channel structure, such as to the final dielectric layer (e.g., dielectric layer112) of the transistors, for example. The first channel structure (e.g., first and second 2D materials) and the second channel structure (e.g., third and fourth 2D materials) can each form a 2D gas at an interface between at least the respective two 2D materials. For instance, a first 2D gas can form between the first and second 2D materials and a second 2D gas can form between the third and fourth 2D materials. The 2D gas can extend along the vertical direction (e.g., z-direction) from the respective source metal to the drain metal. In this case, the first 2D gas can extend from the first source metal to the first drain metal, and the second 2D gas can extend from the second source metal to the second drain metal. In some implementations, at least one of the third 2D material or the fourth 2D material may be different from at least one of the first 2D material or the second 2D material. For instance, different 2D materials can be used to form the 2D gas. The first and second 2D materials may be preselected to utilize a first set of 2D materials, and the third and fourth 2D materials may be preselected to utilize a second set of 2D materials to form the respective 2D gas. In some other cases, the first and second 2D materials can be the same as the third and fourth 2D materials. Accordingly, the first channel structure, the first source metal, the first drain metal, and the first gate metal can collectively form the first transistor. The first transistor can include or have a first conductive type (e.g., N-type or P-type). Further, and collectively, the second channel structure, the second source metal, the second drain metal, and the second gate metal can form the second transistor. The second transistor can have a second conductive type opposite to the first conductive type. Having now described some illustrative implementations, it is apparent that the foregoing is illustrative and not limiting, having been presented by way of example. In particular, although many of the examples presented herein involve specific combinations of method acts or system elements, those acts and those elements may be combined in other ways to accomplish the same objectives. Acts, elements and features discussed only in connection with one implementation are not intended to be excluded from a similar role in other implementations or implementations. The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including” “comprising” “having” “containing” “involving” “characterized by” “characterized in that” and variations thereof herein, is meant to encompass the items listed thereafter, equivalents thereof, and additional items, as well as alternate implementations consisting of the items listed thereafter exclusively. In one implementation, the systems and methods described herein consist of one, each combination of more than one, or all of the described elements, acts, or components. “Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only. Any references to implementations or elements or acts of the systems and methods herein referred to in the singular may also embrace implementations including a plurality of these elements, and any references in plural to any implementation or element or act herein may also embrace implementations including only a single element. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, their components, acts, or elements to single or plural configurations. References to any act or element being based on any information, act or element may include implementations where the act or element is based at least in part on any information, act, or element. Any implementation disclosed herein may be combined with any other implementation, and references to “an implementation,” “some implementations,” “an alternate implementation,” “various implementation,” “one implementation” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the implementation may be included in at least one implementation. Such terms as used herein are not necessarily all referring to the same implementation. Any implementation may be combined with any other implementation, inclusively or exclusively, in any manner consistent with the aspects and implementations disclosed herein. References to “or” may be construed as inclusive so that any terms described using “or” may indicate any of a single, more than one, and all of the described terms. Where technical features in the drawings, detailed description or any claim are followed by reference signs, the reference signs have been included for the sole purpose of increasing the intelligibility of the drawings, detailed description, and claims. Accordingly, neither the reference signs nor their absence have any limiting effect on the scope of any claim elements. The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein. While various aspects and embodiments have been disclosed, other aspects and embodiments are contemplated. The various aspects and embodiments disclosed are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims. | 60,113 |
11942537 | DETAILED DESCRIPTION OF THE INVENTION According to the present invention, techniques for a high voltage field effect transistor (“FET”) configured on a gallium and nitrogen containing material are provided. In an example, the present invention includes a method and resulting structure for a FET configured in a region of gallium and nitrogen containing material, such as GaN or AlGaN. Merely by way of example, the invention has been applied to a high voltage FET device. However, the techniques can be applied other types of device structures and applications. FIG.1is a simplified diagram of a vertical FET device configured on a GaN substrate according to an example of the present invention. As shown, the present invention provides a vertical FET device fabricated in GaN or other suitable material. In an example, the device100has a GaN substrate110comprising a surface region and a backside region. In an example, the GaN substrate110is n+ type or another type. As shown, the device100has an n− type GaN epitaxial layer120overlying the surface region. The device has a plurality of finger regions150, each of the finger regions150having a portion of the n− type GaN epitaxial layer120, an n+ type portion130, and a capping layer140. In an example, the device has a plurality of recessed regions152, each of the recessed regions152formed between each pair of finger regions150. The device100has an n− type GaN channel comprising a doping level and a thickness selected to provide a large gate-drain breakdown voltage in a range from 100 volts to 20 kilo-volts. The device100has an n+ type source configured from the n+ type portions130of the finger regions150and including n-type metal contact regions154. In an example, the device100has a plurality of selective area implant regions160comprising an activated impurity selected from at least one of Be, Mg, Zn, Ca, and Cd configured from at least a bottom portion of the recessed regions152and configured to be substantially free from ion implant damage using an annealing process. The device100has a p-type gate region configured from the selective area implant regions160and including p-type metal contact regions162. The device100has a depth characterizing each of the recessed regions152configured to provide physical separation between the n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. The device100has an extended drain region configured from a portion of the n− type GaN region120underlying the recessed regions152. In an example, the device100has an n+ GaN region formed by epitaxial growth directly overlying the backside region of the GaN substrate110and a backside drain contact region configured from the n+ type GaN region overlying the backside region. In an example, the device has a drain region configured from the backside region of the GaN substrate110configured as an n+ type GaN substrate. In an example, the n+ source region or regions are provided by a donor impurity ion implantation and a subsequent annealing process. In an example, the source region or regions are provided with silicon as a donor impurity. In an example, the channel region or regions are provided with silicon as a donor impurity. In an example, the device100has a dielectric spacer layer170deposited conformally overlying the recessed regions152to limit a lateral penetration of a subsequent ion implant of acceptors into the n-type GaN channel. In an example, the device100has a dielectric spacer layer170deposited conformally overlying the recessed regions152to encapsulate and passivate a plurality of GaN exposed surfaces between the n+ type source and the p-type gate region. In an example, the device100has a trench region154configured around a periphery of a device region, the trench region154comprising a dielectric fill material180and configured to form an isolation region. In an example, the dielectric fill material180is at least one of SiN, a mixed dielectric AlSiN, or AlN. In an example, device100includes a pad metal contact layer190connecting each of the n-type contact metal regions154and connecting each of the p-type metal contact regions162. In an example, the device100has a built-in voltage of a gate-source diode is approximately 3 volts to achieve a wider channel width as compared to a metal-insulator-semiconductor gate structure for a normally-off enhancement mode device. Those of ordinary skill in the art will recognize other variations, modifications, and alternatives to the configurations and materials described above. Further details of techniques including a method of fabricating the device can be found throughout the present specification and more particularly below. A method of fabricating a high-voltage switching device or vertical FET device according to an example of the present invention is briefly described as follows:1. Provide a GaN Substrate, having a surface region and a backside region;2. Form a first n+ type GaN layer overlying the surface region;3. Form a n− type GaN layer overlying the first n+ type GaN layer;4. form a second n+ type GaN layer overlying the n-type GaN layer; Form a hard mask material overlying the second n+ type GaN layer, where the hard mask material has a hard mask surface region;6. Pattern the hard mask material to expose a plurality of trench regions;7. Subject the plurality of trench regions to a reactive ion etching process including a chlorine gas, boron tri chloride, and argon gas to cause formation of the plurality of trench regions, each of which has a selected depth extending vertically from the hard mask surface region and causing formation of a plurality of finger regions, each of which is disposed between a pair of trench regions;8. Subject an exposed region of each of the finger regions and a bottom portion of the trench region to a wet chemical etch to cause exposure to a plurality of principle crystalline planes, including an m-plane and a c-plane or an a-plane or a c-plane;9. Form a thickness of a conformal layer overlying exposed surfaces of each of the fingers, the trench regions, and a peripheral region;10. Perform an implantation process using a beryllium bearing species to form a plurality of implanted regions, each of which is spatially disposed between each pair of fingers, to form an outer implanted region on each exterior finger region, and to form a peripheral implant region;11. Activate, using an annealing process, the beryllium bearing species in the plurality of implanted regions, the outer implanted region, and the peripheral implanted region such that the activating forms a plurality of p-type regions;12. Form a plurality of p-type metal contact regions, each of the p-type metal contact regions formed overlying one of the p-type regions;13. Form a thickness of planarizing material overlying a surface region including each of the finger regions, the trench regions, and the peripheral region;14. Form a plurality of openings, each of the openings exposing a portion of the second n+ type layer included in the finger region;15. Form a plurality of n-type contact metals each of which is connected to the portion of the n− type layer included in the finger region; whereupon the high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing substrate member, a gate region configured from connection to each of the p-type metal contact regions, a channel region configured between a pair of p-type regions, and a source region configured from connection to each of the n-type contact metals; and16. Perform other steps, as desired. The above sequence of steps is used to form high voltage FET devices on a die from a substrate structure according to one or more embodiments of the present invention. Depending upon the embodiment, one or more of these steps can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Further details of this method are provided throughout the present specification and more particularly below. FIGS.2to14are diagrams illustrating a method of fabricating the vertical FET device according to an example of the present invention. The same reference numbers used acrossFIGS.2to14refer to the same elements of the vertical FET device. These diagrams are merely examples, and should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. Referring toFIG.2, the method includes providing a gallium and nitrogen containing substrate210. The substrate can be a GaN substrate, having a surface region and a backside region. The GaN substrate210is homogeneously doped and can be conductive or non-conductive. In an example, the GaN substrate210can be a grown substrate or a bulk GaN substrate, among others. In an example referring toFIG.3, the method forms a first n+ type GaN layer310overlying the surface region of substrate210. The first n+ type GaN310is epitaxially grown using a MOCVD reactor, or the like. The first n+ type GaN310is formed using a tri-ethyl gallium and an ammonia gas. In an example, the epitaxial material has a thickness of about 0.5 to 2.0 microns or can be others. The n+ type characteristic is provided by a silicon dopant derived from a silane gas. In an example, the method forms an n− type GaN layer320overlying the first n+ type GaN layer310. The n− type GaN320is epitaxially grown using a MOCVD reactor, or the like. The n− type GaN320is formed using a tri-ethyl gallium and an ammonia gas. In an example, the epitaxial material has a thickness of about 1 to 200 microns or can be others. The n− type characteristic is provided by a silicon dopant derived from a silane gas. In an example, the thickness is adjusted to adjust a breakdown voltage of the field effect device. In an example, the method forms a second n+ type GaN layer330overlying the n-type GaN layer320. The second n+ type GaN330is epitaxially grown using a MOCVD reactor, or the like. The second n+ type GaN330is formed using a tri-ethyl gallium and an ammonia gas. In an example, the epitaxial material has a thickness of about 50 to 200 nanometers or can be others. The n+ type characteristic is provided by a silicon dopant derived from a silane gas. In an example referring toFIG.4, the method includes forming a hard mask material410overlying the second n+ type GaN layer330. In an example, the hard mask material410has a hard mask surface region. In an example, the hard mask material is a silicon nitride, silicon dioxide, or other materials and combinations thereof. In an example, the method includes patterning the hard mask material410to expose a plurality of trench regions420, as shown. In an example, the patterning occurs by using a photolithography process or other like process. In an example referring toFIG.5, the method includes subjecting the plurality of trench regions420using a reactive ion etching process. In an example, the reactive ion etching process uses a chlorine gas, boron tri chloride, and argon gas. The etching process forms the plurality of trench regions510. Each of the trench regions510has a selected depth extending vertically from the hard mask surface region. Each trench510extends through a portion of the hard mask410, a portion of the second n+ type region330, and a portion of the n− type region320. In an example, the trench region510has an aspect ratio of four-to-one (depth-to-width) to ten-to-one, but can be others. In an example, the trench region510causes formation of a plurality of finger regions520, each of which is disposed between a pair of trench regions510. Each of the finger regions520is a stack including the portion of the hard mask410, the second n+ type region330, and the n− type region320. After reactive ion etching, exposed surfaces of the finger regions520and trenches510are rough. In an example referring toFIG.6, the method includes subjecting an exposed region of each of the finger regions520and a bottom portion of the trench region510to a wet chemical etchant. In an example, the wet chemical etch removes surface roughness and causes exposure of a plurality of principle crystalline planes, including an m-plane and a c-plane or an a-plane or a c-plane. In an example, the wet chemical etch comprises tetramethylammonium hydroxide (TMAH) diluted in a water at an elevated temperature ranging from about 50 Degrees Celsius to about 150 Degrees Celsius. Or course, there can be other variations, modifications, and alternative. As shown inFIG.7, the method includes forming a thickness of a conformal layer710overlying exposed surfaces of each of the fingers520, the trench regions510, and a peripheral region. As shown, the conformal layer710is a blanket layer and covers an entirety of the exposed surfaces. The conformal layer710has thickness of about 25 to 300 nanometers. In an example, the conformal layer710is silicon dioxide, silicon nitride, or other materials and combinations thereof. The conformal layer710is substantially free from any pinholes or other imperfections. Referring toFIG.8, the method includes performing an implantation process using a beryllium bearing species to form a plurality of implanted regions810. Each of the implanted regions810is spatially disposed between each pair of fingers520. The implantation process also forms an outer implanted region820on each exterior finger region. The process also forms one or more peripheral implant regions830. In an example, each of the implant regions has a depth of 10 nanometers to 1000 nanometers, or can be others. In an example, each of the implanted regions extends to a region outside of the trench region510and extends into each edge of the finger regions520. In an example, the method includes activating, using an annealing process, the beryllium bearing species in the plurality of implanted regions810, the outer implanted regions820, and the peripheral implanted regions830. The activation forms a plurality of p-type regions. As shown, prior to annealing, a capping layer (i.e., hard mask410) was grown on the implanted surface. The capping layer serves to prevent nitrogen loss in addition to using the short duration high temperature anneal step. The annealing process begins with an isothermal anneal at 1000° C. in hydrogen and ammonia gas near atmospheric pressure. The ammonia prevents nitrogen loss and introduces atomic hydrogen in the crystal. This step removes much of the ion implant damage, but it fails to activate the group II acceptor impurities. The acceptor activation is realized in the next process step. To activate the magnesium or beryllium acceptors, an activation temperature of 1500° C. is desired while simultaneously preventing nitrogen loss from the crystal. To accomplish this, the time of the thermal anneal must be reduced to the nanosecond time scale. This was achieved by exposing the implanted wafer surface to a pulsed laser annealing using an XeCl excimer laser (wavelength is 308 nm). The pulse energy density was 600 mJ/cm2 and a pulse duration of 30 nano-seconds. The 3 mm by 3 mm exposure aperture was scanned across the entire wafer surface one pulse at a time. The wafer surface temperature was over 1000° C. for 10 nano-second and reached a peak temperature of 1500° C. The appearance of the wafer's surface did not change during this treatment. Higher pulse energy densities produced gallium droplets on the wafer surface indicating severe nitrogen loss. The final process step is an isothermal anneal in nitrogen gas at 800° C., which is a sufficiently low temperature to avoid nitrogen loss from the wafer surface. This anneal is designed to remove atomic hydrogen from the in-process substrate, which is known to passivate acceptor impurities rendering them electronically inactive. In an example, referring toFIG.9, the method includes forming a plurality of p-type metal contact regions. As shown, a photolithograph technique and plasma or reactive ion etching using a fluorine based entity forms a plurality of contact openings910as shown. A contact opening910is formed on a bottom portion of each of the trench regions510to expose the p-type implanted regions810. A contact opening920is formed on each peripheral region to expose the p-type implanted regions820adjacent to an outer finger region. Referring toFIG.10, the method includes forming a p-type metal contact region1010overlying at least one of the exposed p-type regions. In an example, each of the exposed p-type implanted regions has a p-type metal contact region1010. In an example, each of the p-type metal contact regions is an ohmic contact. Various types of metals can include nickel-gold, and others. Referring toFIG.11, the method forms a thickness of planarizing material1110overlying a surface region including each of the finger regions520, the trench regions510, and the peripheral region. In an example, the planarizing material1110can be an oxide, a PECVD oxide, or spin-on oxide material. In an example, the planarizing material1110can include at least one of SiN, a mixed dielectric AlSiN, or AlN. In an example, the method includes forming a plurality of openings1210, each of the openings1210exposing a portion of the second n+ type layer410included in the finger regions520, as shown in theFIG.12. The openings1210are formed using a photolithography process. In an example, the method includes forming a plurality of n-type contact metal regions1310within the plurality of openings1210, as shown inFIG.13. Each of n-type metal contact regions1310is connected to the portion of the n− type layer330included in the finger regions520. As shown inFIG.14, the method includes forming a pad contact metal layer1410connecting each of the n-type contact metal regions1310. The pad contact metal layer1410also connects each of the gate regions configured by the p-type metal contact regions1010. The high voltage switching device is configured from a drain region configured from the backside region of the gallium and nitrogen containing substrate member, a gate region configured from a connection to each of the p-type metal contact regions1010, a channel region configured between a pair of p-type regions, and a source region configured from connection to each of the n-type contact metals1310. In an example, the GaN substrate110is removed by a wafer grinding, etching, or other like thinning or removal process. In an example, the drain region is configured from a backside region of the first n+ type GaN layer. The above sequence of steps is used to form high voltage FET devices on a die from a substrate structure according to one or more embodiments of the present invention. Depending upon the embodiment, one or more of these steps can be combined, or removed, or other steps may be added without departing from the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. As an example, the implanted gallium and nitrogen containing region can include any combination of elements described above, as well as outside of the present specification. As used herein, the term “substrate” can mean the bulk substrate or can include overlying growth structures such as a gallium and nitrogen containing epitaxial region, or functional regions, combinations, and the like. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention, which is defined by the appended claims. | 19,896 |
11942538 | DETAILED DESCRIPTION Problem to be Solved by the Present Disclosure An object of the present disclosure is to provide a silicon carbide semiconductor device in which variation in breakdown voltage can be lessened. Advantageous Effect of the Present Disclosure According to the present disclosure, a silicon carbide semiconductor device in which variation in breakdown voltage can be lessened can be provided. Overview of Embodiments of the Present Disclosure Overview of embodiments of the present disclosure will initially be described. Regarding crystallographic denotation herein, an individual orientation, a group orientation, an individual plane, and a group plane are shown in [ ], < >, ( ), and { }, respectively. A crystallographically negative index is normally expressed by a number with a bar “-” thereabove, however, it is herein expressed by a negative sign preceding a number. (1) A silicon carbide semiconductor device200according to the present disclosure includes a silicon carbide substrate100including a first main surface1and a second main surface2opposite to first main surface1. Silicon carbide substrate100includes a first impurity region10containing a p-type impurity, a second impurity region20provided on first impurity region10, second impurity region20containing an n-type impurity, a third impurity region30provided on second impurity region20, third impurity region30containing a p-type impurity, a fourth impurity region40provided on third impurity region30at a distance from second impurity region20, fourth impurity region40containing an n-type impurity, and a fifth impurity region50in contact with each of first impurity region10and second impurity region20, fifth impurity region50containing an n-type impurity. In first main surface1, a gate trench7is provided, gate trench7including a side surface5in contact with each of second impurity region20, third impurity region30, and fourth impurity region40and a bottom surface6continuous to side surface5and being in contact with second impurity region20. In a direction from first main surface1toward second main surface2through each of first impurity region10and third impurity region30, a concentration profile of the p-type impurity has a first relative maximum value N1and a third relative maximum value N3located closer to the first main surface than a position where first relative maximum value N1is exhibited. In the direction from first main surface1toward second main surface2through each of second impurity region10and fourth impurity region40, a concentration profile of the n-type impurity has a second relative maximum value N2and a fourth relative maximum value N4located closer to the first main surface than a position where second relative maximum value N2is exhibited. Fourth relative maximum value N4is larger than third relative maximum value N3, third relative maximum value N3is larger than second relative maximum value N2, and second relative maximum value N2is larger than first relative maximum value N1. (2) In silicon carbide semiconductor device200according to (1), a total of a thickness of first impurity region10, a thickness of second impurity region20, a thickness of third impurity region30, and a thickness of fourth impurity region40may be not larger than 1.5 μm. (3) In silicon carbide semiconductor device200according to (1) or (2), first impurity region10may have a thickness not larger than 0.5 μm. (4) In silicon carbide semiconductor device200according to any one of (1) to (3), second impurity region20may have a thickness not larger than 0.5 μm. (5) In silicon carbide semiconductor device200according to any one of (1) to (4), first relative maximum value N1may be larger than 5×1016cm−3. (6) In silicon carbide semiconductor device200according to any one of (1) to (5), second relative maximum value N2may be larger than 1×1017cm−3. (7) In silicon carbide semiconductor device200according to any one of (1) to (6), third relative maximum value N3may be larger than 1×1018cm−3. (8) In silicon carbide semiconductor device200according to any one of (1) to (7), fourth relative maximum value N4may be larger than 1×1019cm−3. (9) In silicon carbide semiconductor device200according to any one of (1) to (8), when viewed in a direction perpendicular to second main surface2, at least a part of first impurity region10may be arranged as being superimposed on bottom surface6. (10) In silicon carbide semiconductor device200according to (9), when viewed in the direction perpendicular to second main surface2, first impurity region10may extend along a first direction101in parallel to second main surface2and bottom surface6may extend along a second direction102in parallel to second main surface2and perpendicular to first direction101. (11) In silicon carbide semiconductor device200according to (9), when viewed in the direction perpendicular to second main surface2, first impurity region10may extend along a first direction101in parallel to second main surface2and bottom surface6may extend along first direction101. (12) In silicon carbide semiconductor device200according to any one of (1) to (12), when viewed in a direction perpendicular to second main surface2, first impurity region10may be arranged as not being superimposed on bottom surface6. (13) In silicon carbide semiconductor device200according to (12), when viewed in the direction perpendicular to second main surface2, bottom surface6extends along a first direction101in parallel to second main surface2and first impurity region10extends along a second direction102in parallel to second main surface2and perpendicular to first direction101. DETAILS OF EMBODIMENTS OF THE PRESENT DISCLOSURE Details of embodiments of the present disclosure will be described below. The same or corresponding elements in the description below have the same reference characters allotted and identical description thereof will not be repeated. First Embodiment A construction of a MOSFET as silicon carbide semiconductor device200according to a first embodiment will initially be described. As shown inFIG.1, silicon carbide semiconductor device200according to the present embodiment mainly includes silicon carbide substrate100, a gate electrode64, a gate insulating film71, an interlayer insulating film72, a source electrode60, and a drain electrode63. Silicon carbide substrate100includes first main surface1and second main surface2opposite to first main surface1. Silicon carbide substrate100includes a silicon carbide single-crystal substrate4and a silicon carbide epitaxial layer3provided on silicon carbide single-crystal substrate4. Second main surface2is defined by silicon carbide single-crystal substrate4. First main surface1is defined by silicon carbide epitaxial layer3. Silicon carbide single-crystal substrate4is composed of hexagonal silicon carbide having, for example, a polytype of 4H. First main surface1of silicon carbide substrate100has a maximal diameter, for example, of 150 mm and preferably not smaller than 150 mm. First main surface1is, for example, a {0001} plane or a surface angled off by not greater than 8° from the {0001} plane. Specifically, first main surface1is, for example, a (0001) plane or a surface angled off by at most 8° from the (0001) plane. First main surface1may be, for example, a (000-1) plane or a surface angled off by at most 8° from the (000-1) plane. Silicon carbide single-crystal substrate4has a thickness, for example, of 350 μm and not greater than 500 μm. Silicon carbide epitaxial layer3mainly includes first impurity region10, second impurity region20, third impurity region30, fourth impurity region40, fifth impurity region50, and a contact region8. First impurity region10is, for example, an electric field relaxation region. Second impurity region20is, for example, a current diffusion region. Third impurity region30is, for example, a channel layer (body region). Fourth impurity region40is, for example, a source region. Fifth impurity region50is, for example, a drift region. First impurity region10contains a p-type impurity (a first p-type impurity). The first p-type impurity is a p-type impurity capable of providing the p-type such as aluminum (Al) or boron (B). First impurity region10is a p-type region. First impurity region10has a thickness (a first thickness T1), for example, of 0.35 μm. First thickness T1may be, for example, not larger than 0.5 μm or not larger than 0.4 μm. Though a lower limit of first thickness T1is not particularly limited, it may be, for example, not smaller than 0.1 μm. Second impurity region20contains an n-type impurity (a first n-type impurity). Second impurity region20is provided on first impurity region10. The first n-type impurity is an n-type impurity capable of providing the n-type such as nitrogen (N) or phosphorus (P). Second impurity region20is an n-type region. Second impurity region20has a thickness (a second thickness T2), for example, of 0.3 μm. Second thickness T2may be, for example, not larger than 0.5 μm or not larger than 0.4 μm. Though a lower limit of second thickness T2is not particularly limited, it may be, for example, not smaller than 0.1 μm. Second thickness T2may be smaller than first thickness T1. Third impurity region30contains a p-type impurity (a second p-type impurity). Third impurity region30is provided on second impurity region20. The second p-type impurity is a p-type impurity capable of providing the p-type such as aluminum (Al) or boron (B). Third impurity region30is a p-type region. Third impurity region30has a thickness (a third thickness T3), for example, of 0.2 μm. Third thickness T3may be, for example, not larger than 0.3 μm or not larger than 0.25 μm. Though a lower limit of third thickness T3is not particularly limited, it may be, for example, not smaller than 0.1 μm. Third thickness T3may be smaller than second thickness T2. Fourth impurity region40contains an n-type impurity (a second n-type impurity). Fourth impurity region40is provided on third impurity region30at a distance from second impurity region20. The second n-type impurity is an n-type impurity capable of providing the n-type such as nitrogen (N) or phosphorus (P). Fourth impurity region40is an n-type region. Fourth impurity region40has a thickness (a fourth thickness T4), for example, of 0.25 μm. Fourth thickness T4may be, for example, not larger than 0.35 μm or not larger than 0.3 μm. Though a lower limit of fourth thickness T4is not particularly limited, it may be, for example, not smaller than 0.1 μm. Fourth thickness T4may be larger than third thickness T3. Fifth impurity region50contains an n-type impurity (a third n-type impurity). Fifth impurity region50is in contact with each of first impurity region10and second impurity region20. The third n-type impurity is an n-type impurity capable of providing the n-type such as nitrogen (N). Fifth impurity region50is an n-type region. A thickness (fifth thickness T5) of fifth impurity region50is larger than the thickness (first thickness T1) of first impurity region10. The thickness (fifth thickness T5) of fifth impurity region50may be larger, for example, than 0.5 μm. Contact region8contains a third p-type impurity. Contact region8is in contact, for example, with each of third impurity region30and fourth impurity region40. The third p-type impurity is a p-type impurity capable of providing the p-type such as aluminum (Al) or boron (B). Contact region8is a p-type region. A thickness of contact region8may be larger than the thickness (fourth thickness T4) of fourth impurity region40. The first p-type impurity may be identical to or different from the second p-type impurity. The first p-type impurity may be aluminum and the second p-type impurity may be aluminum. The first p-type impurity may be aluminum and the second p-type impurity may be boron. Similarly, the first p-type impurity may be identical to or different from the third p-type impurity. Similarly, the second p-type impurity may be identical to or different from the third p-type impurity. The first n-type impurity may be identical to or different from the second n-type impurity. The first n-type impurity may be nitrogen and the second n-type impurity may be nitrogen. The first n-type impurity may be nitrogen and the second n-type impurity may be phosphorus. Similarly, the first n-type impurity may be identical to or different from the third n-type impurity. Similarly, the second n-type impurity may be identical to or different from the third n-type impurity. A total of the thickness (first thickness T1) of first impurity region10, the thickness (second thickness T2) of second impurity region20, the thickness (third thickness T3) of third impurity region30, and the thickness (fourth thickness T4) of fourth impurity region40may be, for example, not larger than 1.5 μm. The total of first thickness T1, second thickness T2, third thickness T3, and fourth thickness T4may be, for example, not larger than 1.35 μm or not larger than 1.1 μm. Though a lower limit of the total of first thickness T1, second thickness T2, third thickness T3, and fourth thickness T4is not particularly limited, it may be, for example, not smaller than 0.5 μm. First main surface1is provided with gate trench7. Gate trench7includes side surface5and bottom surface6. Bottom surface6is continuous to side surface5. Side surface5is continuous to first main surface1. Side surface5extends along a direction substantially perpendicular to first main surface1. Bottom surface6is substantially in parallel to first main surface1. A boundary between side surface5and bottom surface6may be formed to have a curvature. Gate trench7has a depth, for example, not smaller than 0.5 μm and not larger than 1.5 μm. Side surface5is in contact with each of second impurity region20, third impurity region30, and fourth impurity region40. Bottom surface6is in contact with second impurity region20. Bottom surface6is distant from third impurity region30. Bottom surface6may be distant from or in contact with first impurity region10. Gate insulating film71is composed, for example, of silicon dioxide. Gate insulating film71is provided as being in contact with side surface5and bottom surface6of gate trench7. The gate insulating film is in contact with each of second impurity region20, third impurity region30, and fourth impurity region40at side surface5. The gate insulating film is in contact with second impurity region20at bottom surface6. A channel can be formed in third impurity region30in contact with gate insulating film71. Gate insulating film71has a thickness, for example, not smaller than 40 nm and not larger than 150 nm. Gate electrode64is provided on gate insulating film71. Gate electrode64is arranged as being in contact with gate insulating film71. The gate electrode is provided to bury a groove defined by gate insulating film71. Gate electrode64is composed of a conductor such as polysilicon doped with an impurity. Source electrode60includes an electrode layer61and a source interconnection62. Electrode layer61is composed, for example, of an Ni alloy. Source electrode60is in contact with fourth impurity region40. Source electrode60may be in contact with contact region8. Electrode layer61is composed, for example, of a material containing Ti, Al, and Si. Source interconnection62is composed, for example, of a material containing AlSiCu. Interlayer insulating film72is provided to cover gate electrode64. Interlayer insulating film72is in contact with each of gate electrode64and gate insulating film71. Interlayer insulating film72is made, for example, from a non-doped silicate glass (NSG) film or a phosphorus silicate glass (PSG) film. Interlayer insulating film72electrically isolates gate electrode64and source electrode60from each other. Drain electrode63is provided as being in contact with second main surface2of silicon carbide substrate100. Drain electrode63is electrically connected to fifth impurity region50on a side of second main surface2. Drain electrode63is composed of a material that can establish ohmic contact with n-type silicon carbide single-crystal substrate4such as nickel silicide (NiSi). Drain electrode63is electrically connected to silicon carbide single-crystal substrate4. FIG.2is a schematic lateral cross-sectional view along the line II-II inFIG.1. As shown inFIG.2, when viewed in the direction perpendicular to second main surface2, gate trench7extends along first direction101. First direction101corresponds to a longitudinal direction of gate trench7. Second direction102corresponds to a direction of a short side of gate trench7. When viewed in the direction perpendicular to second main surface2, gate trench7is substantially rectangular. First direction101is, for example, a <11-20> direction. Second direction102is, for example, a <1-100> direction. First direction101may be, for example, a direction resulting from projection of the <11-20> direction on first main surface1. Second direction102may be, for example, a direction resulting from projection of the <1-100> direction on first main surface1. Each of first direction101and second direction102is in parallel to second main surface2. As shown inFIG.2, when viewed in the direction perpendicular to second main surface2, at least a part of first impurity region10may be arranged as being superimposed on bottom surface6of gate trench7. Preferably, when viewed in the direction perpendicular to second main surface2, the entire bottom surface6is arranged as being superimposed on first impurity region10. When viewed in the direction perpendicular to second main surface2, first impurity region10extends along first direction101. From another point of view, the longitudinal direction of first impurity region10corresponds to first direction101and the direction of the short side of first impurity region10corresponds to second direction102. A width of first impurity region10in first direction101is larger than a width (a first width W1) of first impurity region10in second direction102. First width W1is, for example, not smaller than 0.5 μm and not larger than 2.0 μm. First width W1may be larger than first thickness T1. As shown inFIG.2, when viewed in the direction perpendicular to second main surface2, bottom surface6of gate trench7extends along first direction101. From another point of view, the longitudinal direction of bottom surface6corresponds to first direction101and the direction of the short side of bottom surface6corresponds to second direction102. A width of bottom surface6in first direction101is larger than a width (a second width W2) of bottom surface6in second direction102. Second width W2is, for example, not smaller than 0.1 μm and not larger than 1.5 μm. Second width W2may be smaller than first width W1. Gate trenches7may be provided at regular intervals in second direction102. Similarly, first impurity regions10may be provided at regular intervals in second direction102. An interval W3between two adjacent first impurity regions10is, for example, not smaller than 0.5 μm and not larger than 5.0 μm. FIG.3is a schematic diagram showing a concentration profile of the first p-type impurity in a direction of thickness of the silicon carbide substrate. The abscissa inFIG.3represents a position in the direction of thickness. The ordinate inFIG.3represents a concentration of the first p-type impurity. The concentration of the first p-type impurity is measured, for example, in a direction along an arrow103inFIG.1. As shown inFIG.3, in a direction from first main surface1toward second main surface2, the concentration profile of the first p-type impurity (a first concentration profile11) has a first relative maximum value N1. The concentration profile of the first p-type impurity exhibits first relative maximum value N1at a first position A1. From first position A1toward first main surface1, the concentration of the first p-type impurity monotonously decreases. Similarly, from first position A1toward second main surface2, the concentration of the first p-type impurity monotonously decreases. First relative maximum value N1is a maximum value of the concentration of the first p-type impurity in first impurity region10. First relative maximum value N1is, for example, larger than 5×1016cm−3. First relative maximum value N1may be, for example, larger than 1×107cm−3or larger than 1×1018cm−3. Though an upper limit of first relative maximum value N1is not particularly limited, it may be, for example, not larger than 5×1018cm−3. FIG.4is a schematic diagram showing a concentration profile of the second p-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.4represents a position in the direction of thickness. The ordinate inFIG.4represents a concentration of the second p-type impurity. The concentration of the second p-type impurity is measured, for example, in the direction along arrow103inFIG.1. As shown inFIG.4, in the direction from first main surface1toward second main surface2, the concentration profile of the second p-type impurity (a third concentration profile13) has a third relative maximum value N3. The concentration profile of the second p-type impurity exhibits third relative maximum value N3at a third position A3. From third position A3toward first main surface1, the concentration of the second p-type impurity monotonously decreases. Similarly, from third position A3toward second main surface2, the concentration of the second p-type impurity monotonously decreases. Third relative maximum value N3is a maximum value of the concentration of the second p-type impurity in third impurity region30. Third relative maximum value N3is larger than first relative maximum value N1. Third relative maximum value N3is, for example, larger than 1×1018cm−3. Third relative maximum value N3may be, for example, larger than 2×1018cm−3or larger than 5×1018cm−3. Though an upper limit of third relative maximum value N3is not particularly limited, it may be, for example, not larger than 1×1019cm−3. As shown inFIG.4, the concentration profile of the second p-type impurity may reach first main surface1. The concentration of the second p-type impurity (a second concentration N6) at first main surface1may be lower than third relative maximum value N3. FIG.5is a schematic diagram showing a concentration profile of the p-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.5represents a position in the direction of thickness. The ordinate inFIG.5represents a concentration of the p-type impurity. The concentration of the p-type impurity is measured, for example, in the direction along arrow103inFIG.1. The concentration profile shown inFIG.5is formed as the concentration profile shown inFIG.3and the concentration profile shown inFIG.4are superimposed on each other. As shown inFIG.5, in the direction from first main surface1toward second main surface2through each of first impurity region10and third impurity region30, the concentration profile of the p-type impurity has first relative maximum value N1and third relative maximum value N3located (third position A3) closer to the first main surface than the position (first position A1) where first relative maximum value N1is exhibited. As shown inFIG.5, the concentration profile of the p-type impurity has a first relative minimum value N7. The concentration profile of the p-type impurity has first relative minimum value N7at a fifth position A5. Fifth position A5is located between first position A1and third position A3. First relative minimum value N7is smaller than first relative maximum value N1. FIG.6is a schematic diagram showing a concentration profile of the first n-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.6represents a position in the direction of thickness. The ordinate inFIG.6represents a concentration of the first n-type impurity. The concentration of the first n-type impurity is measured, for example, in the direction along arrow103inFIG.1. As shown inFIG.6, in the direction from first main surface1toward second main surface2, the concentration profile (a second concentration profile12) of the first n-type impurity has a second relative maximum value N2. The concentration profile of the first n-type impurity exhibits second relative maximum value N2at a second position A2. From second position A2toward first main surface1, the concentration of the first n-type impurity monotonously decreases. Similarly, from second position A2toward second main surface2, the concentration of the first n-type impurity monotonously decreases. Second relative maximum value N2is a maximum value of the concentration of the first n-type impurity in second impurity region20. Second relative maximum value N2is larger than first relative maximum value N1. Second relative maximum value N2is, for example, larger than 1×1017cm−3. Second relative maximum value N2may be, for example, larger than 2×1017cm−3or larger than 5×1017cm−3. Though an upper limit of second relative maximum value N2is not particularly limited, it may be, for example, not larger than 1×1018cm−3. FIG.7is a schematic diagram showing a concentration profile of the second n-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.7represents a position in the direction of thickness. The ordinate inFIG.7represents a concentration of the second n-type impurity. The concentration of the second n-type impurity is measured, for example, in the direction along arrow103inFIG.1. As shown inFIG.7, in the direction from first main surface1toward second main surface2, the concentration profile (a fourth concentration profile14) of the second n-type impurity has a fourth relative maximum value N4. The concentration profile of the second n-type impurity exhibits fourth relative maximum value N4at a fourth position A4. From fourth position A4toward first main surface1, the concentration of the second n-type impurity monotonously decreases. Similarly, from fourth position A4toward second main surface2, the concentration of the second n-type impurity monotonously decreases. Fourth relative maximum value N4is a maximum value of the concentration of the second n-type impurity in fourth impurity region40. Fourth relative maximum value N4is larger than third relative maximum value N3. Third relative maximum value N3is larger than second relative maximum value N2. Fourth relative maximum value N4is, for example, larger than 1×1019cm−3Fourth relative maximum value N4may be, for example, larger than 2×1019cm−3or larger than 5×1019cm−3. Though an upper limit of fourth relative maximum value N4is not particularly limited, it may be, for example, not larger than 1×1020cm−3. As shown inFIG.7, the concentration profile of the second n-type impurity may reach first main surface1. The concentration (a fourth concentration N8) of the second n-type impurity at first main surface1is lower than fourth relative maximum value N4. Fourth concentration N8is higher than second concentration N6(seeFIG.4). FIG.8is a schematic diagram showing a concentration profile of the third n-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.8represents a position in the direction of thickness. The ordinate inFIG.8represents a concentration of the third n-type impurity. The concentration of the third n-type impurity is measured, for example, in the direction along arrow103inFIG.1. As will be described later, the silicon carbide epitaxial layer is formed in one epitaxial growth. As shown inFIG.8, in the direction from first main surface1toward second main surface2, the concentration (a first concentration N5) of the third n-type impurity is substantially constant. From another point of view, between first main surface1and second main surface2, the concentration profile (a fifth concentration profile15) of the third n-type impurity is substantially flat. Between first main surface1and second main surface2, fifth concentration profile15is continuous. In other words, between first main surface1and second main surface2, fifth concentration profile15does not include a discontinuous portion. First concentration N5is lower than first relative maximum value N1. First concentration N5is lower, for example, than 5×1016cm−3. FIG.9is a schematic diagram showing a concentration profile of the n-type impurity in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.9represents a position in the direction of thickness. The ordinate inFIG.9represents a concentration of the n-type impurity. The concentration of the n-type impurity is measured, for example, in the direction along arrow103inFIG.1. The concentration profile shown inFIG.9is formed as the concentration profile shown inFIG.6, the concentration profile shown inFIG.7, and the concentration profile shown inFIG.8are superimposed on one another. As shown inFIG.9, in the direction from first main surface1toward second main surface2through each of second impurity region20and fourth impurity region40, the concentration profile of the n-type impurity has second relative maximum value N2and fourth relative maximum value N4located (second position A2) closer to the first main surface than a position (fourth position A4) where second relative maximum value N2is exhibited. As shown inFIG.9, the concentration profile of the n-type impurity has a second relative minimum value N9. The concentration profile of the n-type impurity has second relative minimum value N9at a sixth position A6. Sixth position A6is located between second position A2and fourth position A4. Second relative minimum value N9is smaller than second relative maximum value N2. Second relative minimum value N9may be larger than first concentration N5. FIG.10is a schematic diagram showing a carrier concentration profile in the direction of thickness of the silicon carbide substrate. The abscissa inFIG.10represents a position in the direction of thickness. The ordinate inFIG.10represents a carrier concentration. The carrier concentration is expressed as an absolute value of a difference between the concentration of the n-type impurity and the concentration of the p-type impurity. The carrier concentration is measured, for example, in the direction along arrow103inFIG.1. The carrier concentration profile is shown with a solid line. As shown inFIG.10, at first position A1in the first impurity region, the carrier concentration profile exhibits a fifth relative maximum value n1. Similarly, at second position A2in second impurity region20, the carrier concentration profile exhibits a sixth relative maximum value n2. Similarly, at third position A3in third impurity region30, the carrier concentration profile exhibits a seventh relative maximum value n3. Similarly, at fourth position A4in fourth impurity region40, the carrier concentration profile exhibits an eighth relative maximum value n4. Eighth relative maximum value n4is larger than seventh relative maximum value n3. Seventh relative maximum value n3is larger than sixth relative maximum value n2. Sixth relative maximum value n2is larger than fifth relative maximum value n1. Fifth relative maximum value n1is larger than the carrier concentration (a third concentration n5) in fifth impurity region50. In the direction perpendicular to second main surface2, fourth position A4is located between third position A3and first main surface1. Similarly, in the direction perpendicular to second main surface2, third position A3is located between fourth position A4and second position A2. Similarly, in the direction perpendicular to second main surface2, second position A2is located between third position A3and first position A1. Similarly, in the direction perpendicular to second main surface2, first position A1is located between second position A2and second main surface2. At a boundary between first impurity region10and fifth impurity region50, the carrier concentration profile has a relative minimum value. At a boundary between first impurity region10and second impurity region20, the carrier concentration profile has a relative minimum value. At a boundary between second impurity region20and third impurity region30, the carrier concentration profile has a relative minimum value. At a boundary between third impurity region30and fourth impurity region40, the carrier concentration profile has a relative minimum value. As shown inFIG.10, in first impurity region10, first concentration profile11, second concentration profile12, and fifth concentration profile15may be superimposed on one another. From another point of view, first impurity region10may contain the first n-type impurity, the first p-type impurity, and the third n-type impurity. In second impurity region20, first concentration profile11, second concentration profile12, third concentration profile13, and fifth concentration profile15may be superimposed on one another. From another point of view, second impurity region20may contain the first n-type impurity, the first p-type impurity, the second n-type impurity, and the third n-type impurity In third impurity region30, first concentration profile11, second concentration profile12, third concentration profile13, fourth concentration profile14, and fifth concentration profile15may be superimposed on one another. From another point of view, third impurity region30may contain the first n-type impurity, the first p-type impurity, the second n-type impurity, the second p-type impurity, and the third n-type impurity. In fourth impurity region40, second concentration profile12, third concentration profile13, fourth concentration profile14, and fifth concentration profile15may be superimposed on one another. From another point of view, fourth impurity region40may contain the first p-type impurity, the second n-type impurity, the second p-type impurity, and the third n-type impurity. In fifth impurity region50, first concentration profile11and fifth concentration profile15may be superimposed on each other. From another point of view, fifth impurity region50may contain the first n-type impurity and the third n-type impurity. A method of measuring the concentration of the p-type impurity and the concentration of the n-type impurity in each impurity region will now be described. The concentration of the p-type impurity and the concentration of the n-type impurity in each impurity region can be measured by secondary ion mass spectrometry (SIMS). For example, a secondary ion mass spectrometer manufactured by Cameca is adopted as a measurement apparatus. A measurement pitch is set, for example, to 0.01 μm. When nitrogen is to be detected as the n-type impurity, cesium (Cs) is adopted for primary ion beams. Primary ion energy is set to 14.5 keV. Secondary ion polarity is negative. When aluminum or boron is to be detected as the p-type impurity, oxygen (O2) is adopted for primary ion beams. Primary ion energy is set to 8 keV. Secondary ion polarity is positive. The concentration of the p-type impurity and the concentration of the n-type impurity are measured at the center of a silicon carbide epitaxial substrate. A method of measuring a thickness of each impurity region will now be described. A scanning capacitance microscope (SCM) is used in a method of distinguishing between a p-type region and an n-type region. For example, NanoScope IV manufactured by Bruker AXS is employed as a measurement apparatus. The SCM is a method of visualizing a distribution of the carrier concentration in a semiconductor. Specifically, a surface of a sample is scanned with a silicon probe coated with a metal. At this time, a high-frequency voltage is applied to the sample. Majority carriers are excited to modulate a capacitance of a system. A frequency of the high-frequency voltage applied to the sample is set to 100 kHz and the voltage is set to 4.0 V. A thickness of each impurity region is measured by the SCM. An operation of a MOSFET200according to the present embodiment will now be described. In a state that a voltage applied to gate electrode64is lower than a threshold voltage, that is, in an off state, even when the voltage is applied across source electrode60and drain electrode63, a pn junction between third impurity region30and second impurity region20is reverse biased and there is no conduction therebetween. When a voltage equal to or higher than the threshold voltage is applied to gate electrode64, an inverted layer is formed in a channel region around a portion of contact of third impurity region30with gate insulating film71. Consequently, fourth impurity region40and second impurity region20are electrically connected to each other and a current flows between source electrode60and drain electrode63. MOSFET200operates as set forth above. A method of manufacturing silicon carbide semiconductor device200according to the present embodiment will now be described. Initially, a step of preparing silicon carbide substrate100is performed. Silicon carbide single-crystal substrate4is prepared, for example, by cutting a substrate by slicing from a silicon carbide single-crystal ingot grown by the modified Lely method and mirror-polishing a surface of the substrate. Silicon carbide single-crystal substrate4is composed of hexagonal silicon carbide having, for example, a polytype of 4H. Silicon carbide single-crystal substrate4has a diameter, for example, of 150 mm. Then, a step of forming a silicon carbide epitaxial layer is performed. For example, carrier gas containing hydrogen, source material gas containing silane and propane, and dopant gas containing nitrogen are supplied over silicon carbide single-crystal substrate4, and silicon carbide single-crystal substrate4is heated, for example, to approximately 1550° C. under a pressure of 100 mbar (10 kPa). Silicon carbide epitaxial layer3having the n-type is thus formed on silicon carbide single-crystal substrate4(seeFIG.11). Silicon carbide epitaxial layer3is doped with nitrogen as the n-type impurity. The concentration of the n-type impurity is set, for example, to 8.0×1015cm−3. As set forth above, silicon carbide substrate100including silicon carbide single-crystal substrate4and silicon carbide epitaxial layer3provided on the silicon carbide single-crystal substrate is prepared. Silicon carbide substrate100includes first main surface1and second main surface2. First main surface1is, for example, a {0001} plane or a surface angled off by at most 8° from the {0001} plane. Ions are then implanted into silicon carbide epitaxial layer3. Initially, a first ion implantation mask (not shown) is provided on first main surface1. Then, ions of the first p-type impurity are implanted into silicon carbide epitaxial layer3. First impurity region10having the p-type is thus formed. For example, aluminum is employed as the first p-type impurity. Ion implantation energy is, for example, not higher than 900 keV. Then, the first ion implantation mask (not shown) is removed from first main surface1. A second ion implantation mask (not shown) is provided on first main surface1. The second ion implantation mask covers, for example, a guard ring region (not shown). Then, ions of the first n-type impurity are implanted into silicon carbide epitaxial layer3. Second impurity region20having the n-type is thus formed. Second impurity region20is formed as being in contact with first impurity region10. For example, nitrogen is employed as the first n-type impurity. Ion implantation energy is, for example, not higher than 900 keV. Then, ions of the second p-type impurity are implanted into silicon carbide epitaxial layer3. Third impurity region30having the p-type is thus formed. Third impurity region30is formed as being in contact with second impurity region20. For example, aluminum is employed as the second p-type impurity. Ion implantation energy is, for example, not higher than 900 keV. Then, ions of the second n-type impurity are implanted into silicon carbide epitaxial layer3. Fourth impurity region40having the n-type is thus formed. Second impurity region40is formed as being in contact with third impurity region30. For example, phosphorus is employed as the second n-type impurity. Ion implantation energy is, for example, not higher than 900 keV. Then, the second ion implantation mask (not shown) is removed from first main surface1. A third ion implantation mask (not shown) is then provided on first main surface1. Ions of the third p-type impurity are implanted into silicon carbide epitaxial layer3Contact region8having the p-type is thus formed. Contact region8is formed as being in contact with each of third impurity region30and fourth impurity region40. For example, aluminum is employed as the third p-type impurity. Ion implantation energy is, for example, not higher than 900 keV. Then, the third ion implantation mask (not shown) is removed from first main surface1. A portion in silicon carbide epitaxial layer3into which ions were not implanted is fifth impurity region50. As set forth above, silicon carbide substrate100including first impurity region10, second impurity region20, third impurity region30, fourth impurity region40, fifth impurity region50, and contact region8is prepared (seeFIG.12). Then, an etching mask (not shown) is formed on first main surface1. The etching mask is made, for example, of a material including a deposited oxide film. The etching mask has an opening provided over a region where gate trench7is to be formed. Silicon carbide substrate100is then etched with the use of the etching mask. For example, in an atmosphere of SF6and O2, fourth impurity region40, third impurity region30, and second impurity region20are anisotropically etched. For example, electron cyclotron resonance (ECR) plasma etching is adopted as anisotropic etching. Gate trench7is thus provided in first main surface1(seeFIG.13). Gate trench7includes side surface5and bottom surface6. Side surface5is in contact with second impurity region20, third impurity region30, and fourth impurity region40. Bottom surface6is in contact with second impurity region20. Then, gate insulating film71is formed. Specifically, gate insulating film71in contact with first main surface1, side surface5, and bottom surface6is formed. Gate insulating film71is in contact with fourth impurity region40, third impurity region30, and second impurity region20at side surface5. Gate insulating film71is in contact with second impurity region20at bottom surface6. Gate insulating film71is in contact with fourth impurity region40at first main surface1. Gate insulating film71has a thickness, for example, not smaller than 40 nm and not larger than 150 nm. Then, an NO annealing step is performed. Specifically, in an atmosphere containing nitrogen, silicon carbide substrate100on which gate insulating film71has been formed is subjected to heat treatment at a temperature, for example, not lower than 1100° C. and not higher than 1300° C. Examples of gas containing nitrogen include nitrogen monoxide diluted with nitrogen by 10%. Silicon carbide substrate100is annealed in gas containing nitrogen, for example, for a period not shorter than 30 minutes and not longer than 360 minutes. Then, gate electrode64is formed. Specifically, gate electrode64is formed on gate insulating film71to bury the groove defined by gate insulating film71. Gate electrode64is composed, for example, of a material containing polysilicon containing an impurity. Then, interlayer insulating film72is formed to cover gate electrode64. Interlayer insulating film72includes, for example, at least any of the NSG film and the PSG film. Then, source electrode60is formed. Specifically, interlayer insulating film72and gate insulating film71are removed from a region where source electrode60is to be formed. A part of fourth impurity region40and contact region8are thus exposed through interlayer insulating film72and gate insulating film71(seeFIG.14). Then, electrode layer61is formed on first main surface1as being in contact with both of fourth impurity region40and contact region8. Electrode layer61is formed, for example, by sputtering. Electrode layer61is composed, for example, of a material containing TiAlSi. Then, silicon carbide substrate100in which electrode layer61has been formed is subjected to rapid thermal annealing (RTA) for approximately two minutes, for example, at a temperature not lower than 900° C. and not higher than 1100° C. As a result of reaction with silicon contained in silicon carbide substrate100, at least a part of electrode layer61is thus converted to silicide. Electrode layer61thus establishes ohmic contact with fourth impurity region40. Preferably, electrode layer61establishes ohmic contact with each of fourth impurity region40and contact region8. Then, source interconnection62is formed as being in contact with electrode layer61and covering interlayer insulating film72. Source interconnection62is preferably composed of a material containing Al, such as a material containing AlSiCu. Then, a back surface of silicon carbide single-crystal substrate4is polished. The thickness of silicon carbide single-crystal substrate4is thus reduced. Then, drain electrode63is formed. Drain electrode63is formed as being in contact with second main surface2of silicon carbide substrate100. Drain electrode63is composed, for example, of a material containing NiSi. Drain electrode63may be composed, for example, of TiAlSi. Though drain electrode63is preferably formed by sputtering, it may be formed by vapor deposition. After drain electrode63is formed, it is heated, for example, by laser annealing. At least a part of drain electrode63is thus converted to silicide. MOSFET200shown inFIG.1is manufactured as set forth above. Second Embodiment A construction of silicon carbide semiconductor device200according to a second embodiment will now be described. Silicon carbide semiconductor device200according to the second embodiment is different from silicon carbide semiconductor device200according to the first embodiment mainly in that first impurity region10is opposed to contact region8, but otherwise similar to silicon carbide semiconductor device200according to the first embodiment. Description is given below, with the difference from silicon carbide semiconductor device200according to the first embodiment being focused on. As shown inFIG.15, in silicon carbide semiconductor device200according to the second embodiment, first impurity region10is opposed to contact region8. From another point of view, first impurity region10is located between contact region8and second main surface2. From another point of view, first impurity region10is arranged as not being opposed to bottom surface6of gate trench7. First impurity region10is opposed to each of third impurity region30and fourth impurity region40. First impurity region10is opposed to electrode layer61. FIG.16is a schematic lateral cross-sectional view along the line XVI-XVI inFIG.15. As shown inFIG.16, when viewed in the direction perpendicular to second main surface2, each of first impurity region10and gate trench7extends along first direction101. When viewed in the direction perpendicular to second main surface2, first impurity region10is arranged as not being superimposed on gate trench7. In second direction102, gate trench7and first impurity region10are alternately arranged. When viewed in the direction perpendicular to second main surface2, gate trench7is located between two adjacent first impurity regions10. Third Embodiment A construction of silicon carbide semiconductor device200according to a third embodiment will now be described. Silicon carbide semiconductor device200according to the third embodiment is different from silicon carbide semiconductor device200according to the first embodiment mainly in that a direction of extension of first impurity region10is orthogonal to a direction of extension of gate trench7, but otherwise similar to silicon carbide semiconductor device200according to the first embodiment. Description is given below, with the difference from silicon carbide semiconductor device200according to the first embodiment being focused on. As shown inFIG.17, in silicon carbide semiconductor device200according to the third embodiment, first impurity region10is opposed to bottom surface6of gate trench7, third impurity region30, contact region8, and electrode layer61. From another point of view, first impurity region10is located between each of bottom surface6of gate trench7, third impurity region30, contact region8, and electrode layer61, and second main surface2. FIG.18is a schematic lateral cross-sectional view along the line XVIII-XVIII inFIG.17. As shown inFIG.18, when viewed in the direction perpendicular to second main surface2, bottom surface6of gate trench7extends along first direction101in parallel to second main surface2and first impurity region10extends along second direction102in parallel to second main surface2and perpendicular to first direction101. From another point of view, the direction of extension of first impurity region10is orthogonal to the direction of extension of gate trench7. The longitudinal direction of first impurity region10corresponds to the direction of the short side of the gate trench. Similarly, the direction of the short side of first impurity region10corresponds to the longitudinal direction of the gate trench. First impurity regions10may be provided at regular intervals along first direction101. Fifth impurity region50is arranged between two adjacent first impurity regions10. When viewed in the direction perpendicular to second main surface2, bottom surface6of gate trench7includes a portion (a first portion) superimposed on first impurity region10and a portion (a second portion) not superimposed on first impurity region10. A fifth current flows to drain electrode63through fifth impurity region50. Though silicon carbide semiconductor device200according to the present disclosure is described above with reference to the MOSFET including gate trench7by way of example, silicon carbide semiconductor device200according to the present disclosure is not limited thereto. Silicon carbide semiconductor device200according to the present disclosure may be, for example, an insulated gate bipolar transistor (IGBT). A function and effect of silicon carbide semiconductor device200according to the embodiments will now be described. In silicon carbide semiconductor device200in which each of first impurity region10(an embedded p-type region), second impurity region20(the n-type current diffusion region), and third impurity region30(the p-type channel region) is formed by ion implantation, the concentration profile of the first n-type impurity in second impurity region20lies between the concentration profile of the first p-type impurity in first impurity region10and the concentration profile of the second p-type impurity in third impurity region30. Therefore, in second impurity region20, the first p-type impurity in a tail portion of the concentration profile of the first p-type impurity and the second p-type impurity in a tail portion of the concentration profile of the second p-type impurity are intermingled. When an interval between first impurity region10and third impurity region30is small (in other words, the thickness of second impurity region20is small), the first n-type impurity in second impurity region20is neutralized by superimposition with the tail portion of the concentration profile of the first p-type impurity in first impurity region10and superimposition with the tail portion of the concentration profile of the second p-type impurity in third impurity region30. In this case, second impurity region20does not have the n-type and silicon carbide semiconductor device200does not work. In order to set second impurity region20to the n-type, second impurity region20should have a large thickness. With increase in thickness of second impurity region20, silicon carbide epitaxial layer3has a larger thickness. Therefore, silicon carbide epitaxial layer3is normally formed by epitaxial growth split into two stages. Specifically, initially, a first silicon carbide layer is formed by epitaxial growth. Then, first impurity region10is formed by ion implantation into the first silicon carbide layer. Then, a second silicon carbide layer is formed on the first silicon carbide layer by epitaxial growth. Then, second impurity region20, third impurity region30, and fourth impurity region40are formed by ion implantation into the second silicon carbide layer. Then, gate trench7is formed in the second silicon carbide layer. The silicon carbide layer formed by first epitaxial growth has first variation in thickness. The thickness of the first silicon carbide layer corresponds to the thickness of the drift layer (fifth impurity region50). As the drift layer has a larger thickness, silicon carbide semiconductor device200has a higher breakdown voltage. In contrast, as the drift layer has a smaller thickness, silicon carbide semiconductor device200has a lower breakdown voltage. In other words, as variation in thickness of the first silicon carbide layer is larger, variation in breakdown voltage of silicon carbide semiconductor device200is also larger. The second silicon carbide layer formed by second epitaxial growth has second variation in thickness. As the second silicon carbide layer has a larger thickness, a distance between bottom surface6of gate trench7and fourth impurity region40is longer. As the distance is longer, silicon carbide semiconductor device200has a lower breakdown voltage. In contrast, as the second silicon carbide layer has a smaller thickness, the distance between bottom surface6of gate trench7and fourth impurity region40is shorter. As the distance is shorter, silicon carbide semiconductor device200has a higher breakdown voltage. In other words, as variation in thickness of the second silicon carbide layer is larger, variation in breakdown voltage of silicon carbide semiconductor device200is also larger. According to silicon carbide semiconductor device200in the present embodiment, in the direction from first main surface1toward second main surface2, the concentration profile of the first p-type impurity has first relative maximum value N1. In the direction from first main surface1toward second main surface2, the concentration profile of the first n-type impurity has second relative maximum value N2. In the direction from first main surface1toward second main surface2, the concentration profile of the second p-type impurity has third relative maximum value N3. Third relative maximum value N3is larger than second relative maximum value N2and second relative maximum value N2is larger than first relative maximum value N1. In an example in which second relative maximum value N2is larger than first relative maximum value N1, neutralization of the first n-type impurity in second impurity region20by the first p-type impurity in first impurity region10is less likely than in an example in which second relative maximum value N2is smaller than first relative maximum value N1. Therefore, in the example in which second relative maximum value N2is larger than first relative maximum value N1, second impurity region20can have a smaller thickness than in the example in which second relative maximum value N2is smaller than first relative maximum value N1. Consequently, the silicon carbide epitaxial layer can be formed in one epitaxial growth. Therefore, as compared with an example in which the silicon carbide epitaxial layer is formed in epitaxial growth in two stages, variation in thickness of the silicon carbide epitaxial layer can be lessened. Consequently, variation in breakdown voltage of silicon carbide semiconductor device200can be lessened. A lead time for forming the silicon carbide epitaxial layer can be shorter than in the example in which the silicon carbide epitaxial layer is formed by epitaxial growth in two stages. Consequently, cost for silicon carbide semiconductor device200can be lowered. Silicon carbide substrate100after second epitaxial growth may have deformed as compared with silicon carbide substrate100after first epitaxial growth. In forming the silicon carbide epitaxial layer by epitaxial growth in two stages, defective exposure may occur due to the influence by deformation of silicon carbide substrate100. By forming the silicon carbide epitaxial layer by one epitaxial growth, defective exposure can be suppressed. It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims rather than the description above and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims. REFERENCE SIGNS LIST 1first main surface;2second main surface;3silicon carbide epitaxial layer;4silicon carbide single-crystal substrate;5side surface;6bottom surface;7gate trench;8contact region;10first impurity region;11first concentration profile;12second concentration profile;13third concentration profile;14fourth concentration profile;15fifth concentration profile;20second impurity region;30third impurity region;40fourth impurity region;50fifth impurity region;60source electrode;61electrode layer;62source interconnection;63drain electrode;64gate electrode;71gate insulating film;72interlayer insulating film;100silicon carbide substrate;101first direction;102second direction;103arrow;200MOSFET (silicon carbide semiconductor device); A1first position; A2second position; A3third position; A4fourth position; A5fifth position; A6sixth position; N1first relative maximum value; N2second relative maximum value; N3third relative maximum value; N4fourth relative maximum value; N5first concentration; N6second concentration; N7first relative minimum value; N8fourth concentration; N9second relative minimum value; T1first thickness; T2second thickness; T3third thickness; T4fourth thickness; T5fifth thickness; W1first width; W2second width; W3interval; n1fifth relative maximum value; n2sixth relative maximum value; n3seventh relative maximum value; n4eighth relative maximum value; n5third concentration | 58,573 |
11942539 | DETAILED DESCRIPTION According to one embodiment, a semiconductor device includes an upper electrode; a lower electrode; a silicon substrate positioned between the upper electrode and the lower electrode, the silicon substrate being of a first conductivity type and contacting the lower electrode; a silicon layer positioned between the silicon substrate and the upper electrode, the silicon layer including a cell region, a side surface, and a termination region positioned between the cell region and the side surface; a gate electrode located in the cell region of the silicon layer; a gate insulating film located between the gate electrode and the silicon layer; and a polycrystalline silicon part buried in the termination region of the silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in the cell region and the termination region. The drift layer is of the first conductivity type and has a lower first-conductivity-type impurity concentration than the silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part. The silicon layer includes a base layer located on the drift layer of the cell region. The base layer is of a second conductivity type and contacts the upper electrode. And the silicon layer includes a source layer located on the base layer. The source layer is of the first conductivity type, contacts the upper electrode, and has a higher first-conductivity-type impurity concentration than the drift layer. The termination region does not include the base layer contacting the upper electrode, the source layer contacting the upper electrode, and the gate electrode. Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals. Although the first conductivity type is described as an n-type and the second conductivity type is described as a p-type in embodiments described below, the first conductivity type may be the p-type, and the second conductivity type may be the n-type. First Embodiment FIG.1is a schematic plan view of a semiconductor device1of a first embodiment. Only characteristic portions are shown inFIG.1for easier understanding of the description. FIG.2is a schematic cross-sectional view along line A-A ofFIG.1. As shown inFIG.2, the semiconductor device1includes an upper electrode60, a lower electrode70, a silicon substrate10that is positioned between the upper electrode60and the lower electrode70, a silicon layer20that is positioned between the silicon substrate10and the upper electrode60, and multiple buried structure parts30buried in the silicon layer20. The “upper” of the upper electrode60and the “lower” of the lower electrode70are relative positional relationships used for the description and are independent of the direction of gravity. The buried structure part30includes at least a gate electrode31and a gate insulating film42. According to the embodiment, the buried structure part30further includes a field plate electrode32, and an insulating film41that covers the upper end, lower end, and side surface of the field plate electrode32. The semiconductor device1is a vertical semiconductor device in which a current is caused to flow in a direction (the vertical direction) connecting the upper electrode60and the lower electrode70by a control of the gate electrode31. The silicon layer20is located on the silicon substrate10. The lower electrode70is located at the back surface of the silicon substrate10. Multiple trenches are formed in the silicon layer20; and the buried structure parts30are located in the trenches. The silicon layer20includes multiple mesa parts20anext to the buried structure parts30. The mesa parts20athat are next to the trenches also are formed simultaneously when forming the trenches for forming the components of the buried structure parts30described above in the silicon layer20. The buried structure parts30do not reach the silicon substrate10. As shown inFIG.1, for example, the multiple buried structure parts30and the multiple mesa parts20aextend in stripe shapes. Among the stripe-shaped multiple buried structure parts30, the buried structure part that is positioned endmost in the direction in which the multiple buried structure parts30are arranged is taken as an outermost buried structure part30a. Among the stripe-shaped multiple mesa parts20a, the mesa part that is next to the outermost buried structure part30ais taken as an outermost mesa part20b. As shown inFIG.1, the planar shape of the silicon layer20is a rectangular shape that includes four side surfaces300. The silicon layer20includes a cell region100and a termination region200. The termination region200is positioned between the cell region100and the side surfaces300. The buried structure parts30and the mesa parts20aare located in the cell region100. The shape of the rectangle that includes the four side surfaces300is arbitrary. For example, a rectangle such as that shown inFIG.6may be used. When the buried structure parts30extend in stripe shapes, the number of directions in which the stripes extend is arbitrary. For example, the stripes may extend in two directions such as those shown inFIG.6. Also, the shape of the buried structure part30when viewed along a direction perpendicular to the planar shape formed by the four side surfaces300may not be a stripe shape. For example, an aggregate of multiple regular hexagonal shapes arranged to have the densest arrangement inward of the termination region200may be used, or an aggregate of circles may be used. As shown inFIG.2, the silicon layer20includes a drift layer21that is located on the silicon substrate10, a base layer22, and a source layer23. The conductivity types of the silicon substrate10and the drift layer21are the n-type. The n-type impurity concentration of the drift layer21is lower than the n-type impurity concentration of the silicon substrate10. The silicon substrate10and the drift layer21are located in the cell region100and the termination region200. The termination region200does not include the base layer22that contacts the upper electrode60, the source layer23that contacts the upper electrode60, and the gate electrode31. The mesa part20aincludes a portion of the drift layer21, the p-type base layer22that is located on the portion of the drift layer21, and the n-type source layer23that is located at the front surface of the base layer22. The n-type impurity concentration of the source layer23is higher than the n-type impurity concentration of the drift layer21. The outermost mesa part20bthat is next to the outermost buried structure part30aincludes a portion of the drift layer21, and the p-type base layer22that is located on the portion of the drift layer21. The source layer23is not included in the outermost mesa part20b. Therefore, the current control (the MOS operation) due to the gate electrode31does not occur in the outermost mesa part20b. In the termination region200, the spreading of the depletion layer due to the fluctuation of the potential is different from that of the cell region100. By setting the mesa part that is proximate to the termination region200to be the outermost mesa part20bthat does not have a MOS operation, and by forming the outermost buried structure part30a, the spreading of the depletion layer between the cell region100and the termination region200can be uniform, and the reduction of the breakdown voltage can be suppressed. For example, in the structure of the outermost buried structure part30a, only one gate electrode31may be formed at one side (the outermost mesa part20bside), or no gate electrodes31may be formed. When the reduction of the breakdown voltage is not a problem, the outermost mesa part20band the outermost buried structure part30amay not be formed. Conversely, when the reduction of the breakdown voltage is a problem, the number of sets that include the outermost mesa part20band the outermost buried structure part30ain each set may be two or more. For example, two gate electrodes31are located in one buried structure part30. For example, the gate electrodes31may have one linked structure in one buried structure part30such as that shown inFIG.8. The gate electrode31faces the side surface of the base layer22via the gate insulating film42. The gate insulating film42is located between the gate electrode31and the side surface of the base layer22. Also, seams and/or voids may be formed in the gate electrode31. An n-type channel (an inversion layer) can be formed in the portion of the base layer22that faces the gate electrode31by applying a voltage that is not less than a threshold to the gate electrode31. The buried structure part30also includes the field plate electrode32. The field plate electrode32is positioned at substantially the center in the width direction (the lateral direction) of the buried structure part30. The field plate electrode32extends through the buried structure part30lower than the gate electrode31. The bottom portion of the field plate electrode32is more proximate than the bottom portion of the gate electrode31to the silicon substrate10. The field plate electrode32is not limited to being completely filled, and seams and/or voids may be formed in the field plate electrode32. The insulating film41is located between the field plate electrode32and the drift layer21and between the field plate electrode32and the gate electrode31. The insulating film41may be formed of the same material or may be formed of multiple different materials. For example, the field plate electrode32is electrically connected with the upper electrode60. Or, the field plate electrode32may be electrically connected with the gate electrode31. The field plate electrode32relaxes the distribution of the electric field of the drift layer21in the off-state in which the application to the gate electrode31of the voltage that is not less than the threshold is stopped. The upper electrode60is located on the silicon layer20and on the buried structure part30. An insulating film43is located between the gate electrode31and the upper electrode60and between the field plate electrode32and the upper electrode60. A contact portion26is formed in the source layer23and the base layer22that are included in the upper portion of the mesa part20a; and a portion of the upper electrode60is located inside the contact portion26. The source layer23and the base layer22are electrically connected with the upper electrode60by a so-called trench contact structure. The source layer23that is electrically connected with the upper electrode60and the base layer22that is electrically connected with the upper electrode60are provided in the cell region100but are not provided in the termination region200. A polycrystalline silicon part50is buried in the drift layer21of the termination region200. The polycrystalline silicon part50is buried by, for example, CVD (Chemical Vapor Deposition) in a trench after forming the trench in the drift layer21of the termination region200. The polycrystalline silicon part50is not limited to completely filling the interior of the trench; and seams and/or voids may be formed in the polycrystalline silicon part50. For example, a structure may be used in which a gap50asuch as that shown inFIG.7is provided in the polycrystalline silicon part50. A trench is not formed in the drift layer21in the region of the gap50a. Although the number of the gaps50aprovided in the polycrystalline silicon part50is arbitrary, a structure that surrounds the buried structure parts30as one link as shown inFIG.1is desirable. The diffusion of the heavy metal (Pt, Au, etc.) into the termination region200described below can be further prevented thereby. In the case of a structure in which the stripe-shaped buried structure parts30shown inFIG.6extend in multiple directions, the multiple buried structure parts30that extend in the same direction are taken as one set. The number of sets of the buried structure parts30surrounded with the polycrystalline silicon part50is arbitrary. For example, a structure may be used in which each set of buried structure parts30such as those shown inFIG.6is surrounded with the polycrystalline silicon part50. For example, a structure may be used in which the buried structure parts30are surrounded with two or more sets of polycrystalline silicon parts50. The gap50amay be provided in such a case. The polycrystalline silicon part50is directly buried in the trench that is formed in the drift layer21without interposing an insulating film such as a silicon oxide film or the like. The side surface and bottom surface of the polycrystalline silicon part50contact the drift layer21. An insulating film such as a silicon oxide film or the like is not provided between the polycrystalline silicon part50and the drift layer21. The upper surface of the polycrystalline silicon part50contacts the insulating film43. The polycrystalline silicon part50is electrically insulated from the upper electrode60. The silicon layer20that includes the drift layer21is a single-crystal layer (or a layer that has high crystallinity approaching that of a single crystal) that is epitaxially grown on the silicon substrate10; the polycrystalline silicon part50, however, is made of polycrystalline silicon that has a higher crystal grain density than the silicon layer20. The crystal grain boundary density of the polycrystalline silicon part50is higher than the crystal grain boundary density of the silicon layer20. The polycrystalline silicon part50includes a heavy metal. The heavy metal is, for example, Pt or Au. In the cell region100and the termination region200of the drift layer21, the region that is between the cell region100and the polycrystalline silicon part50includes the same element of heavy metal as the heavy metal included in the polycrystalline silicon part50. A method for manufacturing the semiconductor device1will now be described. The silicon layer20is formed on the silicon substrate10; and the buried structure part30and the polycrystalline silicon part50are formed in the silicon layer20. For example, the polycrystalline silicon part50is formed before the buried structure part30. The base layer22and the source layer23are formed in the upper portion of the mesa part20aby, for example, ion implantation. Subsequently, the insulating film43is formed on the silicon layer20and on the buried structure part30. After forming the insulating film43, the contact portion26that extends through the insulating film43and reaches the base layer22and the source layer23is formed. A heavy metal (Pt, Au, or the like) is diffused in the drift layer21. As a technique for diffusing the heavy metal, a technique of forming a silicide layer in the contact portion26and performing diffusion by heat treatment can be used, or a technique using ion implantation to implant the heavy metal into the contact portion26vicinity and performing diffusion by heat treatment can be used. In the technique of forming the silicide layer in the contact portion26and performing diffusion by heat treatment, for example, a Pt film is formed as a film that includes the heavy metal in the contact portion26. After forming the Pt film, heat treatment is performed to form a Pt silicide in the portion where the Pt film and the upper portion of the mesa part20a(the base layer22and the source layer23) contact. After forming the Pt silicide, heat treatment is performed at a higher temperature than the heat treatment that forms the Pt silicide; and Pt is diffused in the drift layer21. Subsequently, the Pt silicide and the Pt film are removed; and the upper electrode60is formed in the contact portion26and on the insulating film43. The heavy metal (Pt, Au, or the like) that is diffused in the drift layer21functions as a lifetime killer that forms a recombination center of electrons and holes. In a reverse recovery operation in which a reverse bias is applied to the built-in diode of the semiconductor device1(the P-I-N diode that includes the base layer22, the drift layer21, and the silicon substrate10), one of the carriers (an electron or a hole) that remains in the drift layer21is trapped by the heavy metal (Pt, Au, etc.) and recombines with the other carrier. A reverse recovery charge Qrr of the built-in diode can be reduced thereby, and the reverse recovery characteristics can be improved. The carriers that are in the drift layer21are more plentiful in the cell region100than in the termination region200; therefore, it is desirable for the heavy metal described above to exist as a lifetime killer in the cell region100for lifetime control. In a state in which the built-in diode is biased in the forward direction, the holes that are injected from the p-type base layer22of the cell region100into the drift layer21also flow in the termination region200. In the reverse recovery operation of the built-in diode, the holes of the cell region100are ejected into the upper electrode60via the base layer22; and holes also return to the cell region100side from the termination region200. The drift layer21that is at the upper surface of the termination region200does not contact the upper electrode60; therefore, in the reverse recovery operation, the holes of the termination region200are ejected into the upper electrode60by moving into the cell region100by flowing around under the outermost buried structure part30aat the outer perimeter of the cell region100. In other words, the holes of the termination region200are ejected less easily than the holes of the cell region100. It is favorable for some amount of the heavy metal also to exist in the termination region200to reduce the return current (a so-called tail current) from the termination region200. According to the embodiment, the heavy metal can be retained in the drift layer21of the cell region100; and some amount of the heavy metal also can be retained in the termination region200due to the polycrystalline silicon part50that is formed in the termination region200. The grain boundaries of the polycrystalline silicon part50function as gettering sites of the heavy metal such as Pt, Au, etc. Among the heavy metal that is introduced to the drift layer21of the cell region100by the metal silicide film formed in the contact portion26described above acting as a diffusion source, the heavy metal that diffuses into the termination region200is trapped in the polycrystalline silicon part50. The polycrystalline silicon part50that traps the heavy metal also functions as a new heavy metal diffusion source. Accordingly, the heavy metal can be retained in the drift layer21in the region between the polycrystalline silicon part50and the original heavy metal diffusion source (the formation portion of the contact portion26). The polycrystalline silicon part50may be of the n-type, may be of the p-type, or may be undoped. The polycrystalline silicon part50may have material properties similar to the gate electrode31or the field plate electrode32. The heavy metal concentration in the drift layer21of the cell region100and the heavy metal concentration in the drift layer21in the region between the cell region100and the polycrystalline silicon part50are higher than the heavy metal concentration in the drift layer21in the region between the polycrystalline silicon part50and the side surface300. The thermal diffusion length of the heavy metal (Pt, Au, etc.) in single-crystal silicon is relatively long; therefore, when the polycrystalline silicon part50is not provided in the termination region200, it is difficult to retain the heavy metal in the region of the termination region200next to the cell region100. By providing the polycrystalline silicon part50in the termination region200according to the embodiment, the heavy metal concentration in the region of the termination region200between the cell region100and the polycrystalline silicon part50also can be increased; therefore, the return current from the termination region200in the reverse recovery operation of the built-in diode can be suppressed, and the reverse recovery characteristics can be improved. To suppress the diffusion of the heavy metal into the region outward of the polycrystalline silicon part50, it is desirable for the polycrystalline silicon part50to continuously surround the cell region100as shown inFIG.1. Also, the reverse recovery current in the termination region200is suppressed because polycrystalline silicon includes more defects than single-crystal silicon; and the polycrystalline silicon part50itself includes an energy level that becomes a recombination center. The polycrystalline silicon part50functions as a structural component that restricts the spreading into the termination region200of holes that are injected into the drift layer21of the cell region100in the state in which the built-in diode is biased in the forward direction. By restricting the spreading of the holes into the termination region200, the return current from the termination region200can be reduced; the ejection path of the holes to the upper electrode60can be short; and the reverse recovery time can be short. From the perspective of restricting the spreading of the holes into the termination region200, it is desirable for the depth of the polycrystalline silicon part50to be greater than the depth of the buried structure part30. In other words, it is desirable for the distance (the shortest distance) between the polycrystalline silicon part50and the lower electrode70to be less than the distance (the shortest distance) between the buried structure part30and the lower electrode70. The polycrystalline silicon part50does not reach the silicon substrate10. A heavy metal such as Pt, Au, etc., does not easily pass through a silicon oxide film. Therefore, if a silicon oxide film is provided between the polycrystalline silicon part50and the drift layer21, there is a risk that the heavy metal that diffuses into the termination region200may be undesirably returned to the cell region100by the silicon oxide film acting as a barrier. When the depletion layer that extends into the termination region200reaches the polycrystalline silicon part50, the electric field distribution changes at that portion of the polycrystalline silicon part50; and when the electric field distribution exceeds a critical electric field intensity, there is a risk that local avalanche breakdown may occur. Therefore, it is desirable to form the polycrystalline silicon part50at a position that is not reached by the depletion layer. Second Embodiment FIG.3is a schematic cross-sectional view of a semiconductor device2of a second embodiment. The silicon layer20of the semiconductor device2further includes an n-type channel stopper25that is located between the polycrystalline silicon part50and the drift layer21of the termination region200and has a higher n-type impurity concentration than the drift layer21. After forming a trench in the termination region200, the channel stopper25is formed on the sidewall and bottom surface of the trench. Subsequently, the polycrystalline silicon part50is formed in the trench. The channel stopper25is located between the drift layer21and the side surface of the polycrystalline silicon part50and between the drift layer21and the bottom surface of the polycrystalline silicon part50. The channel stopper25can prevent the depletion layer from reaching the polycrystalline silicon part50, and can prevent local avalanche breakdown. Third Embodiment FIG.4is a schematic cross-sectional view of a semiconductor device3of a third embodiment. For example, when the n-type impurity concentration in the drift layer21is high as in a device that has a relatively low breakdown voltage, the lifetime control of many carriers is necessary, and it is desirable for much of the heavy metal to be commensurately retained in the termination region200. As shown inFIG.4, by providing multiple polycrystalline silicon parts50that include, for example, a first polycrystalline silicon part51, a second polycrystalline silicon part52, and a third polycrystalline silicon part53in the termination region200, the gettering amount of the heavy metal in the termination region200can be increased according to the increase of the necessary lifetime control of the carriers. For example, in the example shown inFIG.4, the first polycrystalline silicon part51is located most proximate to the cell region100; the second polycrystalline silicon part52is located between the first polycrystalline silicon part51and the side surface300of the silicon layer20(shown inFIG.1); and the third polycrystalline silicon part53is located between the second polycrystalline silicon part52and the side surface300. The three polycrystalline silicon parts51to53triply surround the cell region100. The number of the polycrystalline silicon parts50may be two, four, or more. Fourth Embodiment FIG.5is a schematic cross-sectional view of a semiconductor device4of a fourth embodiment. As shown inFIG.5, the first polycrystalline silicon part51that is shallower than the buried structure part30may be provided. In the example shown inFIG.5, the first polycrystalline silicon part51, the second polycrystalline silicon part52, and the third polycrystalline silicon part53that have mutually-different depths triply surround the cell region100. The first polycrystalline silicon part51, the second polycrystalline silicon part52, and the third polycrystalline silicon part53are arranged in the direction connecting the cell region100and the side surface300. The distance (the shortest distance) between the lower electrode70and the first polycrystalline silicon part51most proximate to the cell region100is longer than the distance (the shortest distance) between the buried structure part30and the lower electrode70. The distance (the shortest distance) between the second polycrystalline silicon part52and the lower electrode70is shorter than the distance (the shortest distance) between the first polycrystalline silicon part51and the lower electrode70. The distance (the shortest distance) between the third polycrystalline silicon part53and the lower electrode70is shorter than the distance (the shortest distance) between the second polycrystalline silicon part52and the lower electrode70. In the example as well, the number of the polycrystalline silicon parts50may be two, four, or more. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions. | 27,255 |
11942540 | DETAILED DESCRIPTION Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing may involve the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer may contain active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions. Passive and active components can be formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current. Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components. The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. The portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist may be removed, leaving behind a patterned layer. Alternatively, some types of materials can be patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating. Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface may be used to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization can involve polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation. To singulate the die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer may be singulated using a laser cutting tool or saw blade. After singulation, the individual die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die can then be connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, or wire bonds, as a few examples. An encapsulant or other molding material may be deposited over the package to provide physical support and electrical isolation. The finished package can then be inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components. The power switch in a switching converter/regulator may be a semiconductor transistor (e.g., a metal-oxide-semiconductor field-effect transistor [MOSFET], an insulated gate bipolar transistor [IGBT], etc.). A laterally diffused metal oxide semiconductor (LDMOS) is widely used in switching regulators as the main power switch. Referring now toFIG.1, shown is a cross-sectional diagram of an example LDMOS structure. In this example, N-type well region102may be formed in substrate101, body region109and drift region110may both be located in well region102, source region115can be formed in body region109, and drain region116may be formed in drift region110. Drain region116can withstand high voltages due to the presence of drift region110. Therefore, LDMOS transistors have advantages of relatively large drive current, low on-resistance, and high breakdown voltage, and as such are widely used in switching regulators. However, a relatively large junction depth may be required by well region102in some cases, and as a result well region102may need to be formed separately and not be combined with other processes (e.g., for CMOS structures). In addition, in order to reduce the on-resistance Rdson of an LDMOS transistor, a doping concentration of drift region110should not be too low. Further, to increase the breakdown voltage BV of LDMOS transistors, the doping concentration of drift region110should not be too high. This makes optimization of the breakdown voltage and on-resistance Rdson of a typical LDMOS device very difficult. In one embodiment, a semiconductor device having an LDMOS transistor can include: (i) a first deep well region having a first doping type; (ii) a drift region located in the first deep well region and having a second doping type; and (iii) a drain region located in the drift region and having the second doping type, where the second doping type is opposite to the first doping type, and where a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and the on-resistance of the LDMOS transistor. Referring now toFIG.2A, shown is a cross-sectional diagram of a first example semiconductor device, in accordance with embodiments of the present invention. In this particular example, the semiconductor device can include a high-voltage side structure and a low-voltage side structure. The high-voltage side structure and the low-voltage side structure may share substrate100and gate oxide layer420. The high-voltage side structure can include substrate100, well region210, deep well region221, buried layer230, body region311, drift region312, high-voltage drain oxide layer411, gate oxide layer420, gate conductor431, sidewall spacer441, body contact region511, source region512, drain region513, and a first lightly doped drain region. The low-voltage side structure can include substrate100, deep well region222, body region321, drift region322, gate oxide layer420, high-voltage drain oxide layer412, gate conductor432, sidewall spacer442, body contact region521, source region522, drain region523, and a second lightly doped drain region. For example, substrate100, deep well region221, deep well region222, body region311, body region321, body contact region511, and body contact region521are a first doping type. Also for example, well region210, buried layer230, drift region312, drift region322, source region512, drain region513, source region522, and drain region523are a second doping type, and the first doping type is opposite to the second doping type. The first doping type is one of an N-type and a P-type, and the second doping type is the other of the N-type and the P-type. For example, the doping type of substrate100is the P-type. Well region210can be located in substrate100, and surrounds region10(see, e.g.,FIG.3A) of substrate100. For example, well region210can be located at opposite sides of region10of substrate100. One end of well region210may be in contact with buried layer230, and the other end can extend to a surface of substrate100. The doping type of well region210is N-type, whereby the dopant can include phosphorus. Buried layer230can be located in substrate100and below region10, and buried layer230may not be in in contact with deep well region221. The doping type of buried layer230may be N-type, whereby the dopant can include phosphorus. Buried layer230and well region210may together surround region10to form an N-type cavity structure embedded in substrate100. Deep well regions221and222may be located in substrate100, where deep well region221is located in region10. The doping type of deep well regions221and222may be P-type, whereby the dopant can include boron. Body region311and drift region312can be located in deep well region221, and at least a portion of deep well region221may be located between body region311and drift region312. Body region321and drift region322can be located in deep well region222, and at least a portion of deep well region222may be located between body region321and drift region322. The doping type of body regions311and321may be P-type, whereby the dopant can include boron. The doping type of drift regions312and322may be N-type, whereby the dopant can include phosphorus. Body contact region511can be adjacent to source region512. Body contact region511and source region512can be located in body region311. Drain region513may be located in drift region312. Body contact region521may be adjacent to source region522. Body contact region521and source region522can be located in body region321. Drain region523may be located in drift region322. The first and second lightly doped drain regions can respectively be located in body regions311and312. The doping type of body contact region511and body contact region521can be P-type. The doping type of source region512, drain region513, source region522, drain region523, the first and second lightly doped drain regions can be N-type. The doping concentration of the first lightly doped drain region may be less than that of drain region513, and the doping concentration of the second lightly doped drain region may be less than that of drain region523. Gate oxide layer420can be located on a surface of substrate100. High-voltage drain oxide layer411can be disposed on a surface of drift region312and adjacent to gate oxide layer420. Gate conductor431may be disposed on high-voltage drain oxide layer411and gate oxide layer420. One end of gate conductor431can extend to above a side of source region512closer to drift region312, and the other end of gate conductor431may extend to above drift region312. Sidewall spacer441may be located on surfaces of the both sidewalls of gate conductor431. For example, at least a portion of deep well region221can be located below gate conductor431between source region512and drain region513. Further, at least a portion of deep well region221may be located below gate oxide layer420between body region311and drift region312. High-voltage drain oxide layer412may be located on a surface of drift region322and is adjacent to gate oxide layer420. Gate conductor432may be disposed on high-voltage drain oxide layer412and gate oxide layer420. One end of gate conductor432can extend to above a side of source region522closer to drift region322, and the other end of gate conductor432may extend to above drift region322. Sidewall spacer442may be located on surfaces of the both sidewalls of gate conductor432. For example, at least a portion of deep well region222can be located below gate conductor432between source region522and drain region523. Further, at least a portion of deep well region222can be located below gate oxide layer420between body region321and drift region322. For example, the material of gate conductors431and432can include polysilicon. In particular embodiments, the difference between the high-voltage side structure and the low-voltage side structure is that the high-voltage side structure can include buried layer230. That is, well region210and buried layer230may together surround region10to form the high-voltage side structure. The introduction of N-type buried layer230can ensure normal operation of the high-voltage side structure without affecting the breakdown voltage BV of the device and the on-resistance Rdson of the device. In addition, the introduction of buried layer230can further optimize breakdown voltage BV and on-resistance Rdson of the device based on previous BCD process architectures, and with little additional cost. For example, by adding deep well regions221and222in the semiconductor device, the concentration peak of deep well region221and the concentration peak of deep well region222can be concentrated below drift regions312and322, respectively. In this way, the compromise of the breakdown voltage BV and the on-resistance Rdson of the low-voltage side structure and high-voltage side structure can be optimized. Further, sufficient P-type impurity can be provided under drift regions312and322by adjusting the concentration distribution of deep well region221and the concentration distribution of deep well region222, thereby improving the breakdown voltage BV of semiconductor device. Further, the compromise of the breakdown voltage BV and the on-resistance Rdson of the semiconductor device may be optimized by increasing the doping concentration of drift regions312and322. Referring now toFIG.2B, shown is a flow diagram of an example method of manufacturing the first example semiconductor device, in accordance with embodiments of the present invention. Referring also toFIGS.3A-3I, shown are cross-sectional diagrams of example steps for manufacturing the first example semiconductor device, in accordance with embodiments of the present invention. In S01ofFIG.2B, an N-type well region/P-type well region may be formed in the substrate. As shown inFIG.3A, well region210may be formed in substrate100, e.g., by ion implantation. Well region210can be located at opposite sides of region10of substrate100, and region10may be surrounded by well region210. Well region210can also utilized to lead out a buried layer formed in a subsequent step. The doping type of substrate100can be P-type. The doping type of well region210can be N-type, whereby the dopant may include phosphorus. In other cases, the doping type of well region210may also be P-type. In S02ofFIG.2B, P-type deep well regions can formed be in the substrate. As shown inFIG.3B, deep well regions221and222can be formed in substrate100, e.g., by ion implantation. For example, deep well region221may be located in region10. Also, the doping concentration of deep well region221and the doping concentration of deep well region222may be adjusted in order to increase the breakdown voltage (BV) of the semiconductor device. The doping type of deep well regions221and222can be P-type, whereby the dopant may include boron. In S03ofFIG.2B, a field oxide layer can be formed on a surface of the substrate. For example, the field oxide layer may formed on a surface of the substrate by a local oxidation of silicon (LOCOS) process. In S04ofFIG.2B, drift regions may be formed in the P-type deep well region. As shown inFIG.3C, drift regions321and322may be formed in deep well regions221and222, e.g., by ion implantation, respectively. In particular embodiments, the best compromise or optimization of breakdown voltage BV and on-resistance Rdson of the semiconductor device may be achieved by adjusting the doping concentration of drift regions321and322. The doping type of drift regions321and322can be N-type, whereby the dopant can include phosphorus. In S05ofFIG.2B, high-voltage drain oxide layers can be formed on the surface of the substrate. As shown inFIG.3D, first and second high voltage drain regions can be defined by a mask, and high-voltage drain oxide layer411and high-voltage drain oxide layer412can be formed in the corresponding first and second high-voltage drain regions, e.g., by the LOCOS process. In S06ofFIG.2B, a buried layer can be formed in the substrate. As shown inFIG.3E, buried layer230may be formed in region10of substrate100, e.g., by ion implantation. Buried layer230can be located below deep well region221, and may not be in contact with deep well region221. Deep well region221may be surrounded by well region210and buried layer230. Also, one end of well region210can be in contact with buried layer230, and the other end of well region210may extend to the surface of substrate100. The doping type of buried layer230can be N-type, whereby the dopant can include phosphorus. In S07ofFIG.2B, a gate oxide layer may be on the surface of substrate100. As shown inFIG.3F, gate oxide layer420can be formed on regions of the surface of substrate100that are not covered by a high-voltage drain oxide layer. Also, gate oxide layer420can be adjacent to high-voltage drain oxide layers411and412. In S08ofFIG.2B, gate conductors can be formed on the gate oxide layer and the high-voltage drain oxide layer. As shown inFIG.3G, gate conductor431can be formed on a portion of gate oxide layer420and a portion of high-voltage drain oxide layer411. Gate conductor432may be formed on a portion of gate oxide layer420and a portion of high-voltage drain oxide layer412. For example the material of gate conductors431and432can include polysilicon. In S09ofFIG.2B, body regions can be formed in the P-type deep well regions. As shown inFIG.3H, body region311may be formed in deep well region221, and body region312may be formed in deep well region222, e.g., by ion implantation. At least a portion of deep well region221can be located between body region311and drift region312, and at least a portion of deep well region222may be located between body region321and drift region322. The threshold voltage of the semiconductor device may be determined by the doping concentration of body regions311and321. The doping type of body regions311and321can be P-type, whereby the dopant may include boron. In S010ofFIG.2B, a lightly doped drain region may be formed in the body region. As shown inFIG.3H, a lightly doped drain region can be formed in a body region of the semiconductor device by using high-voltage drain oxide layer411and gate conductor431as a hard mask. Also, the doping type of the lightly doped drain region can be N-type. In S011ofFIG.2B, sidewall spacers may be formed on surfaces of both sidewalls of the gate conductor. As shown inFIG.3I, sidewall spacers441can be formed on surfaces of both sidewalls of gate conductor431. Also, spacers442may be formed on surfaces of both sidewalls of gate conductor432. In S012ofFIG.2B, source regions and drain regions may be formed in the body regions and the drift regions, respectively. As also shown inFIG.3I, high-voltage drain oxide layer411, gate conductor431, and sidewall spacer441can be used as a hard mask to form body contact region511and source region512in body region311, and also to form drain region513in drift region312, e.g., by ion implantation. High-voltage drain oxide layer412, gate conductor432, and sidewall spacer442may be used as a hard mask to form body contact region521and source region522in body region321, and to form drain region523in drift region322, e.g., by ion implantation. Referring now toFIG.4, shown is a cross-sectional diagram of a second example semiconductor device, in accordance with embodiments of the present invention. In this particular example, the semiconductor device can include N-type LDMOS, NMOS, PMOS, and PAMOS (P-type asymmetry MOSFET), and the doping type of substrate100is P-type. In this particular example, isolation region501may be formed in well region210. The NMOS can include substrate100, N-type well region223, P-type well region330, gate oxide layer420, gate conductor433, body contact region531, source region532, and drain region533. N-type well region223can be located in substrate100, and P-type well region330may be located in N-type well region223. Body contact region531, source region532, and drain region533can be located in P-type well region330. Gate oxide layer420may be located on a surface of substrate100, and gate conductor433can be located on gate oxide layer420between source region532and drain region533. The PMOS can include substrate100, N-type well region224, gate oxide layer420, gate conductor434, body contact region541, source region542, and drain region543. N-type well region224may be located in substrate100. Body contact region541, source region542, and drain region543can be located in N-type well region224. Gate oxide layer420may be located on the surface of substrate100. Gate conductor434can be located on gate oxide layer420between source region542and drain region543. The PAMOS can include substrate100, N-type well region225, P-type well region350, high-voltage drain oxide layer415, gate oxide layer420, gate conductor435, body contact region551, source region552, and drain region553. N-type well region225can be located in substrate100, P-type well region350may be located in N-type well region225. Body contact region551and source region552can be located in N-type well region225. Drain region553can be located in P-type well region350. Gate oxide layer420may be located on the surface of substrate100, high-voltage drain oxide layer415may be located on a surface of N-type well region225and can be adjacent to gate oxide layer420. Gate conductor435may be located on a portion of high-voltage drain oxide layer415and gate oxide layer420. One end of gate conductor435may extend to above source region552, and the other end can extend to above P-type well region350. At least a portion of N-type well region225can be located below the gate conductor435between source region552and drain region553. In particular embodiments, the junction depth of well region210may be substantially the same as the junction depth of N-type well region223, N-type well region224, and N-type well region225. Thus, well region210, N-type well region223, N-type well region224, and N-type well region225may be formed together by one process. Referring now toFIGS.5A-5I, shown are cross-sectional diagrams of example steps for manufacturing the second example semiconductor device, in accordance with embodiments of the present invention. As shown inFIG.5A, well region210, N-type well region223, N-type well region224, and N-type well region225may be formed together in substrate100, e.g., by ion implantation process. P-type well region330can be formed in N-type well region223, and P-type well region350may be formed in N-type well region225. Region10of substrate100may be surrounded by well region210, and well region210can be located at opposite sides of region10of the substrate. Well region210may also be used in order to lead out a buried layer formed in a subsequent step. The doping type of substrate100may be P-type. The doping type of well region210can be N-type, whereby the dopant can include phosphorus. In other examples, the doping type of well region210may be P-type. As shown inFIG.5B, deep well regions221and222may be formed in substrate100, e.g., by ion implantation process. For example, deep well region221can be located in region10. The doping concentration of deep well region221and the doping concentration of deep well region222can be adjusted in order to increase the breakdown voltage BV of the semiconductor device. The doping type of deep well region221and the doping type of deep well region222can be P-type, whereby the dopant may include boron. Thereafter, a field oxide layer can be formed on a surface of the substrate. For example, a field oxide layer may be formed on a surface of the substrate by a LOCOS process. As shown inFIG.5C, drift region312and drift region322may respectively be formed in deep well regions221and222, e.g., by an ion implantation process. In particular embodiments, a compromise/optimization of breakdown voltage BV and the on-resistance Rdson of the semiconductor device may be achieved by adjusting the doping concentration of drift regions321and322. The doping type of drift regions321and322can be N-type, whereby the dopant may include phosphorus. As shown inFIG.5D, first, second, and third high-voltage drain regions can be defined by a mask, and high-voltage drain oxide layers411,412, and415may be formed in the corresponding first, second, and third high-voltage drain regions, e.g., by a LOCOS process. As shown inFIG.5E, buried layer230may be formed in substrate100by ion implantation process, and buried layer230can be located below deep well region221and not in contact with deep well region221. Deep well region221may be surrounded by well region210and buried layer230. One end of well region210can be in contact with buried layer230, and the other end of well region210may extend to the surface of substrate100. The doping type of buried layer230may be N-type, whereby the dopant can include phosphorus. As shown inFIG.5F, gate oxide layer420may be formed on a region of the surface of the substrate100that is not covered by a high-voltage drain oxide layer. Gate oxide layer420can be in contact with high-voltage drain oxide layers411,412, and415. As shown inFIG.5G, gate conductor431can be formed on gate oxide layer420and high-voltage drain oxide layer411. Gate conductor432may be formed on gate oxide layer420and high-voltage drain oxide layer412. Gate conductor433can be formed on gate oxide layer420located on P-type well region330. Gate conductor434may be formed on gate oxide layer420located on N-type well region224. Gate conductor435can be formed on gate oxide layer420and high-voltage drain oxide layer451. For example, gate conductors431,432,433,434, and435may each include polysilicon. As shown inFIG.5H, body region311can be formed in deep well region221, and body region321may be formed in deep well region222, e.g., by ion implantation. At least a portion of deep well region221may be located between body region311and drift region312. At least a portion of deep well region222can be located between body region321and drift region322. The doping type of body regions311and321may be P-type, whereby the dopant can include boron. A lightly doped drain region can be formed in the body region of the semiconductor device by using high-voltage drain oxide layer411and gate conductor431as a hard mask. Also, the doping type of the lightly doped drain region can be N-type. As shown inFIG.5I, sidewall spacers441may be formed on surfaces of both sidewalls of gate conductor431. Also, sidewall spacers442may be formed on surfaces of both sidewalls of gate conductor432. High-voltage drain oxide layer411, gate conductor431, and sidewall spacers441may be used as a hard mask to form body contact region511and source region512in body region311, and to form drain region513in drift region312, e.g., by ion implantation. High-voltage drain oxide layer412, gate conductor432, and sidewall spacers442may be used as a hard mask to form body contact region521and source region522in body region321, and to form drain region523in drift region322, e.g., by ion implantation. Body contact region531, source region532, and drain region533may be formed in P-type well region330by using gate conductor532as a hard mask. Body contact region541, source region542, and drain region543can be formed in N-type well region224by using gate conductor542as a hard mask. High-voltage drain oxide layer415and gate conductor451can be used as a hard mask to form body contact region551and source region552in N-type well region225, and to form drain region553in P-type well region350, e.g., by ion implantation. In particular embodiments, semiconductor devices and methods for manufacturing the same, can include a source/drain region being formed in a first region of a substrate, and a first well region and a buried layer being formed in the substrate to surround the first region. A well region with a relatively large junction depth in other approaches may be replaced by the first well region and the buried layer of particular embodiments. In this way, forming the first well region together with the well region of other devices (e.g., CMOS devices) facilitates process combination. In particular embodiments, semiconductor devices and methods for manufacturing the same, can include a first deep well region having a doping type different from the drift region being formed in the substrate. The peak of the doping concentration of the first deep well region may be distributed below the drift region by adjusting the doping concentration distribution of the first deep well region. As a result, the breakdown voltage BV and the on-resistance Rdson of the low-voltage side structure and high-voltage side structure of the semiconductor device can be optimized. In particular embodiments, the breakdown voltage BV and the on-resistance Rdson can further be optimized by adjusting the doping concentration of the drift region. In particular embodiments, semiconductor devices and methods for manufacturing the same, can include a buried layer being formed below the first region of the semiconductor device, and a cavity structure surrounding the first region being composed by the buried layer and the first well region to form the high-voltage side structure of the semiconductor device. In addition, the buried layer can be connected to the upper surface of the substrate by the first well region to separate the high-voltage side structure from the low-voltage side structure of the semiconductor device. Normal operation of the high-voltage side structure can thus be guaranteed without affecting the on-resistance Rdson and breakdown voltage BV of the semiconductor device. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to particular use(s) contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents. | 31,735 |
11942541 | DETAILED DESCRIPTION OF THE DISCLOSURE The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” or “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially.” “approximately” or “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially.” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. In order to sustain high voltage, attempts have been made to improve metal-oxide-semiconductor field effect transistors (MOSFETs), including the use of a stepped gate oxide, a protective oxide layer, split gate, etc. The process for fabricating a stepped gate oxide may require extra thermal operation(s) and extra mask(s) so as to form one or more oxide layer(s) overlying the original gate oxide, which may increase the manufacture time and cost. In some embodiments, a protective oxide layer is formed to cover a top surface of the gate, a gate sidewall spacer and a portion of the drain region. Such embodiments may involve large device pitch (i.e., spacing between half drain contact and half source contact) and the quality of the protective oxide layer may be an issue. In some other embodiments, a split gate is formed adjacent to a main gate and coupled to the ground. The split gate oxide is thicker than the main gate oxide so that it can function as a field oxide. Similarly, to form a thick split gate oxide, extra thermal operation(s) may be needed, which is unfavorable to advanced techniques. The present disclosure therefore provides a high voltage semiconductor device, e.g., a high voltage MOSFET. In some embodiments, the present disclosure provides a lateral diffused metal-oxide-semiconductor (LDMOS) field effect transistors that can sustain high voltage. The semiconductor device according to the present disclosure includes two gate structure, one of which is adjacent to and electrically coupled to a drain region. The semiconductor device according to the present disclosure exhibits advantages including an enhanced breakdown voltage, a reduced gate-induced drain leakage, a reduced on-resistance (Ron) etc, can sustain a higher voltage and can be fabricated with a reduced device pitch. The drain region is self-aligned to a sidewall spacer of an adjacent gate structure and there is no specific limit to the thickness of the gate oxide of the adjacent gate structure. Thus, semiconductor device according to the present disclosure can be applied to advanced techniques for, e.g., N40 to N5 or below and can be fabricated without extra thermal process or mask and with low manufacture cost. FIGS.1to8are diagrams illustrating a high voltage semiconductor device100at various stages of fabrication according to an exemplary embodiment of the present disclosure. It is noted thatFIGS.1to8have been simplified for a better understanding of the disclosed embodiment. The high voltage semiconductor device100may be configured as a system-on-chip (SoC) device having various PMOS and/or NMOS transistors that are fabricated to operate at different voltage levels. The PMOS and/or NMOS transistors may provide low voltage functionality including logic/memory devices and input/output devices, and high voltage functionality including power management devices. It is understood that the high voltage semiconductor device100may also include resistors, capacitors, inductors, diodes, and other suitable microelectronic devices that are typically implemented in integrated circuits. Although in the embodiment ofFIGS.1-8the high voltage semiconductor device100including an n-type high voltage MOS (NHVMOS) device is illustrated, the present disclosure may also be applied to a variety of MOS devices. The operations shown inFIGS.1to8are also reflected schematically in the flowchart shown inFIG.11. It should be noted that the operations for forming the semiconductor device100may be rearranged or otherwise modified within the scope of the various aspects. Referring toFIG.1, a semiconductor substrate101is provided. The substrate101may include a semiconductor wafer such as a silicon wafer. Alternatively, the substrate101may include other elementary semiconductors such as germanium. The substrate101may also include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, and indium phosphide. Moreover, the substrate101may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In an embodiment, the substrate101includes an epitaxial layer (epi layer) overlying a bulk semiconductor. Furthermore, the substrate101may include a semiconductor-on-insulator (SOI) structure. For example, the substrate101may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX). In various embodiments, the substrate101may include a buried layer such as an n-type buried layer (NBL), a p-type buried layer (PBL), and/or a buried dielectric layer including a buried oxide (BOX) layer. In the present embodiment, illustrated as an n-type HVMOS, the substrate101includes a p-type silicon substrate (p-substrate). To form a complementary HVMOS, an n-type buried layer, i.e., deep n-well (DNW), may be implanted deeply under the active region of the p-type HVMOS of the p-substrate101. As shown inFIG.1, a P-well (PW)102is formed in various regions of the P-substrate101by ion-implantation or diffusion techniques known in the art. In some embodiments, a patterned photoresist layer (not shown) is formed in a photolithography process or other suitable process. An exemplary photolithography process may include processing steps of photoresist coating, soft baking, mask aligning, exposing, post-exposure baking, developing, and hard baking. The patterned photoresist layer defines the regions for forming the P-well. Then, an ion implantation utilizing a p-type dopant, such as boron, may be performed to form the P-well102in the regions. Referring toFIG.2, isolation feature structures104such as shallow trench isolations (STI) or local oxidation of silicon (LOCOS) including isolation features may be formed in the substrate101to define and electrically isolate various active regions. As one example, the formation of an STI feature may include dry etching a trench in a substrate and filling the trench with insulator materials such as silicon oxide, silicon nitride, or silicon oxynitride. The filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide. In furtherance of the embodiment, the STI structure may be created using a processing sequence such as: growing a pad oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using photoresist and masking, etching a trench in the substrate, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with CVD oxide, using chemical mechanical polishing (CMP) processing to etch back and planarize, and using a nitride stripping process to remove the silicon nitride. Referring toFIG.3, an N-well (NW)106is formed in various regions of the P-substrate101by ion-implantation or diffusion techniques known in the art. The N-well106may be formed in a similar manner as discussed above for the P-well102. An N-well mask (not shown) is used to from a patterned photoresist layer105in a photolithography process or other suitable process. An exemplary photolithography process may include processing steps of photoresist coating, soft baking, mask aligning, exposing, post-exposure baking, developing, and hard baking. An ion implantation utilizing an n-type dopant, such as arsenic or phosphorus, may be performed to form the N-well (NW)106in the substrate101. The N-well106may be referred to as an extended drain of the NHVMOS device. It is noted that other ion implantation processes may also be performed to adjust threshold voltages of the core NMOS and PMOS devices in the other active regions of the substrate101as is known in the art. Referring toFIG.4, a first gate structure110and a second gate structure111are formed and disposed over the semiconductor substrate101. The second gate structure111is laterally adjacent to the first gate structure110and separated from the first gate structure110by a gap G. The first gate structure110and the second gate structure111can be electrically isolated from each other by the gap G. Thus, the length LG of the gap G should be sufficient to maintain the electrical isolation between the first gate structure110and the second gate structure111. In some embodiments, the length LG of the gap G may be in a range from about 10 nanometers (nm) to about 250 nanometers (nm), for example, from about 20 nanometers (nm) to about 200 nanometers (nm). In some embodiments, the length LG of the gap G may be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 125 nm, 150 nm, 175 nm, 200 nm, 225 nm or 250 nm. The first gate structure110is adjacent to the source region131depicted inFIG.6. Further, the first gate structure110overlies a portion of the N-well106and a portion of the P-well102. The second gate structure111is adjacent to the drain region130depicted inFIG.6. Further, the second gate structure111overlies a portion of the N-well106. In some embodiments, the second gate structure111does not cover the drain region130. In the present disclosure, the first gate structure110can be referred to as main gate and the second structure111can be referred to as split gate. In some embodiments, the length L1of the first gate structure110may be in a range from about 0.1 micrometers (μm) to about 0.5 μm, e.g., 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm. In some embodiments, the length L2of the second gate structure111may be in a range from about 0.04 μm to about 0.1 μm, e.g., 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm or 0.1 μm. In some embodiments, the length of the first gate structure is larger than or substantially the same as the length of the second gate structure. The length of the second gate structure111can be minimized as possible. In some embodiments, the second gate structure111may have a minimum length in accordance with the technology node. The first gate structure110includes a gate dielectric layer110bformed on the substrate101, and a gate electrode110aformed on the gate dielectric layer110b. The second gate structure111includes a gate dielectric layer111bformed on the substrate101, and a gate electrode111aformed on the gate dielectric layer111b. In some embodiments, the second gate structure111may be formed in the same process as the first gate structure110. In some embodiments, the first gate structure110and the second gate structure111may be formed as a large single gate structure first and a portion of the large single gate structure is then removed, e.g., by etching techniques, so as to reduce the gate to drain charge. As a result, the remaining portions of the large single gate structure become the first gate structure110and the second gate structure111, respectively. Since the second gate structure111is separated from the first gate structure110by a gap, the gate dielectric layer of the first gate structure110and the gate dielectric layer of the second gate structure111are discontinuous with each other. There is no electric field in the gap region, and thus, the hot carrier injection effect can be reduced. In addition, there is less oxide trapping and thus the reliability of the semiconductor device can be improved. The first gate dielectric layer110bmay include a silicon oxide layer. Alternatively, the gate dielectric layer110bmay optionally include a high-k dielectric material, silicon oxynitride, other suitable materials, or combinations thereof. The high-k material may be selected from metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, hafnium oxide, or combinations thereof. The gate dielectric layer110bmay have a multilayer structure such as one layer of silicon oxide and another layer of high k material. The gate dielectric layer110bmay be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxide, other suitable processes, or combinations thereof. The gate dielectric layer111bmay be made of the same or different material as the gate dielectric layer110b. In some embodiments, a thickness of the gate dielectric layer111bmay the same as that of the gate dielectric layer110b. In other embodiments, the gate dielectric layer111bmay be thinner or thicker than the gate dielectric layer110b, i.e., the gate dielectric layer111bmay have a thickness smaller or greater than the thickness of the gate dielectric layer110b. The gate electrode110amay include a doped polycrystalline silicon (or polysilicon). Alternatively, the gate electrode110amay include a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof. The gate electrode110amay be formed by CVD, PVD, plating, and other proper processes. The gate electrode110amay have a multilayer structure and may be formed in a multi-step process using a combination of different processes. The gate electrode111amay be made of the same or different material as the gate electrode110a. The gate electrode110adisposed overlying the gate dielectric layer110bmay be configured to be coupled to metal interconnects which will be fabricated in subsequent operations. The gate electrode111adisposed overlying the gate dielectric layer111bis configured to be coupled to the drain region which will be fabricated in subsequent operations as discussed below with reference toFIG.8. Referring toFIG.5, sidewall spacers120are formed on the lateral surfaces of the first gate structure110and sidewall spacers121are formed on the lateral surfaces of the second gate structure111. The sidewall spacers120and121may be made of the same or different material and may include a dielectric material such as silicon oxide. Alternatively, the sidewall spacers120and121may optionally include silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. In some embodiments, the sidewall spacers120and121may have a multilayer structure. The sidewall spacers120and121may be formed by a deposition process (such as CVD) and an anisotropic etching process (such as reactive-ion etching, RIE) as is known in the art. Each of the sidewall spacers120and121may independently have a thickness in a range from about 5 nm to 80 nm, e.g., 5 nm, 8 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm or 80 nm. The gap between the first gate structure110and the second gate structure111is filled by the sidewall spacer120and the sidewall spacer121. The sidewall spacer120and the sidewall spacer121cover a lateral surface of the first gate structure110, a lateral surface of the second gate structure111and a top surface of the semiconductor substrate101. In the embodiments illustrated inFIG.5, the sidewall spacer120and the sidewall spacer121cover a portion of the top surface of the semiconductor substrate101in the gap (i.e., a portion of the top surface of the semiconductor substrate101is exposed from the gap). In some other embodiments, the sidewall spacer120and the sidewall spacer121cover the entire top surface of the semiconductor substrate101. Referring toFIG.6, an ion implantation process is carried out to form the drain region130and the source region131. A patterned photoresist layer107is disposed on the semiconductor101to define the regions for ion implantation. In the embodiments where a portion of the top surface of the semiconductor substrate101is exposed from the gap, the patterned photoresist layer107can be applied thereon prevent the semiconductor substrate101from ion implantation. In the embodiments where the gap is fully filled by the sidewall spaces, the sidewall space can prevent N+ or P+ ions from being implanted into the semiconductor substrate101to form a floating leakage path, and therefore, there is no need to dispose a photoresist layer thereon. In some embodiments, n-type dopants, such as phosphorus, arsenic, nitrogen, antimony, combination thereof, or the like are implanted into the semiconductor substrate101to form the drain region130and the source region131. The drain region130and the source region131are n-type and can be referred to as N+ or heavily doped region. The drain region130is formed in the N-well106and adjacent to the second gate structure111. The N-well106may act as a drift region. The source region131is formed in the P-well102and adjacent to the first gate structure110. In some embodiments, the drain region130may include an edge substantially self-aligned to the sidewall spacer121. In some embodiments, the source region131may include an edge substantially self-aligned to the sidewall spacer120. In various embodiments, the drain region130and the source region131may have different doping profiles formed by multi-process implantation. It should be noted that a process to form a source/drain of a p-type (referred to as P+ or heavily doped regions) may be performed for the PMOS devices in the other active regions of the substrate; accordingly, the NMOS devices including the present embodiment may be protected by a patterned photoresist layer. Referring toFIG.7, an ion implantation process is carried out to form a p-type body contact region132. The operations for forming the p-type body contact region132as illustrated inFIG.7are similar to that for forming the n-type drain region130and the n-type source region131as illustrated inFIG.6. In the ion implantation process illustrated inFIG.7p-type dopants, such as boron, are used. The body contact region132is formed adjacent to the source region131. The body contact region132may contact the P-well102. The body contact region132may be coupled to the source region131by a source contact140formed inFIG.8. In some embodiments, various further CMOS processing operations can be carried out to further form contacts (e.g., source contact and drain contact) and/or metal features, etc., on the structure ofFIG.7. Referring toFIG.8, in some embodiments, silicidation, such as salicide, is carried out to form a source contact140and a drain contact150. A metal material, such as titanium, nickel, cobalt or combinations thereof, is applied on the drain region130, the source region131and the body contact region132, the temperature is raised to cause a reaction between the metal material and the underlying silicon of the drain region130, the source region131and the body contact region132so as to form silicide, and the un-reacted metal material is removed (e.g., by etching). The silicide may be self-aligned to be formed on the drain region130, the source region131and the body contact region132to reduce contact resistance. An annealing operation can be carried out so as to provide a desired crystalline phase to the silicide. Although details are not showed in the drawings, subsequent processing can be carried out to form a plurality of patterned dielectric layers and conductive layers on the semiconductor substrate101in order to form interconnects which provide electrical connection to the source contact140, the drain contact150, the first gate structure110and the second gate structure111. The conductive layers may include contacts, vias and metal lines and the dielectric layers are formed as interlayer dielectric (ILD) layers to separate and isolate one conductive layer from other conductive layers. In some embodiments, the materials for forming the conductive layers may include copper, copper alloy, aluminum, aluminum alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. Interconnects may be formed by a process including physical vapor deposition (or sputtering), chemical vapor deposition (CVD), combinations thereof, or other suitable processes. Other manufacturing techniques to form the interconnects may include photolithography processing and etching to pattern the conductive materials for vertical connections (vias and contacts) and horizontal connections (conductive lines). Alternatively, a copper multilayer interconnect may be used to form the metal patterns. Referring back toFIG.8, the second gate structure111is formed on the N-well (i.e., the drift region)106but does not cover the drain region130. The second gate structure111is coupled to the drain, e.g., via interconnect160. In some embodiments, the second gate structure111has an electrical potential substantially the same as an electrical potential of the drain region130. In other words, the voltage drop in the semiconductor device100would appear from the first gate structure110to the second gate structure111, and most of the voltage drop would appear in the gap. With the above structure, the gate-induced drain leakage (GIDL) can be improved and the drain-source breakdown voltage and (BVDSS) can be enhanced. FIG.9illustrates a high voltage semiconductor device according to an exemplary embodiment of the present disclosure. In the embodiments, a contact field plate may be applied to the semiconductor device100to reduce undesirable leakage current. InFIG.9, a contact field plate (field plate)170is formed above the first gate structure110and connected to the source. The contact field plate170may be electrically isolated from the first gate structure110. In some embodiments, the contact field plate170may be connected to the source and the sidewall spacer120(which is formed in the gap and covers the lateral surface of the first gate electrode110). It has been found that in such embodiments, the parasitic gate-to-drain capacitance (Cgd) can be reduced, and thus, fast switching characteristics can be achieved. Furthermore, the voltage or leakage current between the first gate electrode and the second gate electrode can be reduced, and thus, reliability can be improved. FIG.10illustrates the ID (Drain Current)-VD (Drain to source voltage) characteristics of the semiconductor devices according to some embodiments of the present disclosure. InFIG.10, the ID-VD characteristics of the three semiconductor devices were recorded: (a) a semiconductor device as illustrated inFIG.8with a length of the gap between the first gate structure (main gate) and the second gate structure (split gate) being 0.08 μm; (b) a semiconductor device same as (a) except that the split gate is electrically coupled to the ground, not the drain region; and (c) a semiconductor device same as (a) except that the split gate is absent and the drain region is self-aligned to a sidewall space of the main gate. The result reveals that the semiconductor device having a split gate tied to ground exhibits an enhanced off-state breakdown voltage (BVoff). FIG.11illustrates a flowchart of a method1100for forming a semiconductor device in accordance with some embodiments of the present disclosure. At operation1101, a substrate101is provided and a P-well102, a N-well106, isolation feature structures104are formed in the substrate101as discussed above with reference toFIG.1toFIG.3. At operation1102, a first gate structure110and a second gate structure111are formed on the substrate101, the second gate structure111is laterally adjacent to the first gate structure110and separated from the first gate structure110by a gap as discussed above with reference toFIG.4andFIG.5. Each of the first gate structure110and the second gate structure111has a gate dielectric layer (110b,111b) between the substrate101and a gate electrode (110a,111a). The gate dielectric layers110band111bare spaced from each other. Sidewall spacers120and121are formed on the lateral surfaces of the first gate structure110and the second gate structure111. At operation1103, a drain region130adjacent to the second gate structure111and a source region131adjacent to the first gate structure110are formed as discussed above with reference toFIG.6. Further, a p-type body contact region132are formed as discussed above with reference toFIG.7. At operation1104, the second gate structure111is electrically coupled to the drain region130, e.g., via interconnect160as discussed above with reference toFIG.8. Accordingly, the present disclosure provides a semiconductor device, e.g., a MOSFET and a method for forming the same. The semiconductor device includes a first gate structure and a second gate structure, the second gate structure is adjacent to the drain region and electrically coupled to the drain region. The length of the second gate structure can be minimized depending on the technology node. The semiconductor device exhibits advantages including an enhanced breakdown voltage, a reduced gate-induced drain leakage, a reduced on-resistance (Ron) etc, can sustain a higher voltage and can be fabricated with a reduced device pitch. Furthermore, there is no specific limit to the thickness of the gate dielectric layers (e.g., gate oxide) and the self-alignment ion implantation can occur no matter the gate dielectric layer is thin or thick. Furthermore, the second gate structure may be formed in the same process as the first gate structure, and the gate dielectric layers (e.g., gate oxide) of the first and second gate structures may have the same thickness, and therefore, there is no need to carry out extra thermal process or use extra mask as compared to the existing techniques which use a stepped gate oxide layer or a plurality of gate oxide layers with additional thickness. In some embodiments, a semiconductor device including a substrate, a source region, a drain region, a first gate structure and a second gate structure is provided. The source region and a drain region are formed in the substrate. The first gate structure is formed on the substrate and adjacent to the source region. The second gate structure is formed on the substrate and adjacent to the drain region. The second gate structure is electrically coupled to the drain region. In some embodiments, a semiconductor device including a substrate, a source region, a drain region, a first gate structure, a second gate structure and a sidewall space is provided. The source region and drain region are formed in the substrate. The first gate structure and the second gate structure are formed on the substrate and between the source region and the drain region. The second gate structure has an electrical potential substantially the same as an electrical potential of the drain region. In some embodiments, a method for forming a semiconductor device is provided. The method includes following operations. A substrate is provided. A first gate structure and a second gate structure are formed on the substrate and the second gate structure is laterally adjacent to the first gate structure and separated from the first gate structure by a gap. The second gate structure is electrically coupled to the drain region. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein. | 31,404 |
11942542 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “on”, “over”, “above”, “upper”, “bottom”, “top” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “under” other elements or features would then be oriented “above” and/or “over” the other elements or features. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first”, “second”, and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments. As disclosed herein, the term “about” or “substantial” generally means within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages disclosed herein should be understood as modified in all instances by the term “about” or “substantial”. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary as desired. Although the disclosure is described with respect to specific embodiments, the principles of the disclosure, as defined by the claims appended herein, may obviously be applied beyond the specifically described embodiments of the disclosure described herein. Moreover, in the description of the present disclosure, certain details have been left out in order to not obscure the inventive aspects of the disclosure. The details left out are within the knowledge of a person having ordinary skill in the art. The present disclosure is directed to a semiconductor device such as a LDMOS field-effect transistor (FET) device and a method of fabricating the same. The semiconductor device includes a dual gate structure of a gate electrode and a field plate disposed on a triple step-shaped gate dielectric layer to achieve an optimum reduced surface field (RESURF) to reduce on-state resistance (Ron) and sustain threshold voltage and off-state breakdown voltage. FIG.1is a schematic cross-sectional diagram of a semiconductor device according to one embodiment of the present disclosure. Referring toFIG.1, in one embodiment, a semiconductor device100such as a LDMOS FET device includes a substrate101. The substrate101may be a semiconductor substrate including elementary semiconductors such as Si and/or Ge; compound semiconductors such as GaN, SiC, GaAs, GaP, InP, InAs, and/or InSb; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or a combination thereof. In addition, the substrate101may also be a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate101has a first conductivity type, for example, P-type. In addition, the semiconductor device100includes a well region103and another well region105disposed in the substrate101and near the top surface of the substrate101. The well region103has a second conductivity type, for example, N-type, and the well region105has the first conductivity type, for example, P-type. The well region105may be referred to as a body region and the well region103may be referred to as a drift region. In one embodiment, the well region (body region)105is disposed adjacent to and in a direct contact with the well region (drift region)103. The well region103and the well region105are individually formed by ion implanting the substrate101through a patterned mask such as a patterned photoresist. In some other embodiments, the first conductivity type is N-type, and the second conductivity type is P-type. The P-type dopants may include B, Ga, Al, In, BF3ions, or a combination thereof. The N-type dopants may include P, As, N, Sb ions, or a combination thereof. Since the dopant concentration of the well region (body region)105is at least 100 times greater than the dopant concentration of the well region (drift region)103, the depletion region at the junction of the well regions103and105extends mostly in the well region (drift region)103and does not spread into a channel region formed in the well region (body region)105. Moreover, the semiconductor device100includes a source region109disposed in the well region105and a drain region111disposed in the well region103. In some embodiments, the source region109and the drain region111are heavy doped regions of the second conductivity type, for example, N+regions. In addition, another heavy doped region (not shown inFIG.1) of the first conductivity type, for example, a P+region may be disposed in the well region105and on the left side of the source region109. The P+region is in a direct contact with the source region109. In addition, as shown inFIG.1, a shallow trench isolation (STI)107is disposed in the well region103near the drain region111to electrically isolate the adjacent devices from each other. According to the embodiment of the present disclosure, as shown inFIG.1, the semiconductor device100includes a gate dielectric layer120of a triple step-shaped structure in a cross-sectional view. The gate dielectric layer120includes a first portion120-1having a first thickness T1, a second portion120-2having a second thickness T2and a third portion120-3having a third thickness T3. The first portion120-1, the second portion120-2and the third portion120-3are connected with each other. The first thickness T1, the second thickness T2and the third thickness T3are different from each other. In detail, the first thickness T1is smaller than the second thickness T2, and the second thickness T2is smaller than the third thickness T3(T1<T2<T3). In some embodiments, for example, the first thickness T1may be 80 Angstroms, the second thickness T2may be 160 Angstroms, and the third thickness T3may be 460 Angstroms, but not limited thereto. Moreover, the step sidewalls of the gate dielectric layer120may be a vertical sidewall, a slanted sidewall or a combination thereof. The gate dielectric layer120may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The gate dielectric layer120may be formed by a deposition process such as a chemical vapor deposition (CVD) process, other applicable processes, or a combination thereof. In some embodiments, the gate dielectric layer120may be formed by several deposition processes. In addition, the semiconductor device100includes a gate electrode131disposed on the first portion120-1of the gate dielectric layer120and a field plate132disposed on the second portion120-2and the third portion120-3of the gate dielectric layer120. As shown inFIG.1, the gate electrode131has a first length L1and the field plate132has a second length L2, where the second length L2is greater than the first length L1. In detail, a portion of the field plate132on the second portion120-2has a length L2-1and another portion of the field plate132on the third portion120-3has a length L2-2. In some embodiments, the length L2-1is substantially equal to the length L2-2. For example, in one embodiment, the first length L1may be 0.25 μm, the length L2-1may be 0.20 μm, and the length L2-2may be 0.20 μm, i.e., the second length L2may be 0.40 μm, but not limited thereto. In addition, the thickness of the field plate132may be the same as the thickness of the gate electrode131. In some embodiments, the field plate132and the gate electrode131are formed from the same gate material layer. Thus, field plate132and the gate electrode131may be formed of the same material. In some embodiments, the material of the gate electrode131and the field plate132includes polysilicon, metal (e.g., tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, the like, or a combination thereof), metal alloys, metal-nitrides (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, the like, or a combination thereof), metal-silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, the like, or a combination thereof), metal-oxides (e.g., ruthenium oxide, indium tin oxide, the like, or a combination thereof), other suitable materials, or a combination thereof. According to the embodiments of the present disclosure, the field plate132is laterally separated from the gate electrode131and electrically coupled to the gate electrode131through an interconnect structure (not shown inFIG.1). Thus, the field plate132and the gate electrode131may have the same electric potential during the operation of the semiconductor device100. The gate electrode131is used to control the conductivity of a channel region underlying the gate electrode131. The length of the channel region is defined by two boundaries, where one of the boundaries corresponds to the junction between the source region109and the well region105, and the other one of the boundaries corresponds to the junction between the well105and the well103. Besides, since the thicknesses of the second portion120-2and the third portion120-3underlying the field plate132are greater than the thickness of the first portion120-1underlying the gate electrode131, the electric field generated from the field plate132is used not to control the on-off state of the semiconductor device100but to control the electric field at the top surface of the well region103. As shown inFIG.1, there is a gap133P between the gate electrode131and the field plate132. In some embodiments, the gap133P may be directly above the first portion120-1of the gate dielectric layer120. In addition, as shown inFIG.1, in some embodiments, an edge of the field plate132is aligned with an edge of the second portion120-2of the gate dielectric layer120. Furthermore, the semiconductor device100includes a first gate spacer135-1disposed on one sidewall of the gate electrode131, a second gate spacer135-2filled in the gap133P between the gate electrode131and the field plate132, and a third gate spacer135-3disposed on one sidewall of the field plate132. The materials of the first gate spacer135-1, the second gate spacer135-2and the third gate spacer135-3include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or a combination thereof. The first gate spacer135-1, the second gate spacer135-2and the third gate spacer135-3may be a single-layered or a multi-layered structure and may be formed at the same time. As shown inFIG.1, the semiconductor device100further includes an interlayer dielectric layer (ILD)140covering the substrate101. The ILD140may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. The low-k dielectric materials may include, but are not limited to, fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD140may be formed by a CVD process (e.g., a high-density plasma chemical vapor deposition (HDPCVD) process, an atmospheric pressure chemical vapor deposition (APCVD) process, a low-pressure chemical vapor deposition (LPCVD) process, or a plasma enhanced chemical vapor deposition (PECVD) process), a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on coating process, other applicable processes, or a combination thereof. In addition, the semiconductor device100includes a source electrode142disposed in the ILD140and on one side of the gate electrode131, and a drain electrode144disposed in the ILD layer140and on one side of the field plate132. According to the embodiments of the present disclosure, there is a first distance d1between the source electrode142and the gate electrode131. There is a second distance d2between the drain electrode144and the field plate132. The second distance d2is greater than the first distance d1. Each of the source electrode142and the drain electrode144may include a barrier layer and a conductive material. The barrier layer may be formed on the sidewall and the bottom of an opening in the ILD140, and the conductive material fills in the opening. The material of the barrier layer may be TiN, Ti, Ta, TaN, W, WN, other suitable materials, or a combination thereof. The barrier layer may be formed by a PVD process (e.g., evaporation or sputtering), an ALD process, an electroplating process, other applicable process, or a combination thereof. The conductive material includes metal (such as W, Al, or Cu), metal alloys, polysilicon, other suitable conductive materials, or a combination thereof. The source electrode142and the drain electrode144may be formed by a PVD process, an electroplating process, an ALD process, other applicable process, or a combination thereof to deposit the conductive material, and then optionally performing a chemical mechanical polishing (CMP) process or an etching back process to remove extra conductive materials to form the source electrode142and the drain electrode144. Moreover, as shown inFIG.1, according to the embodiments of the present disclosure, the third portion120-3of the gate dielectric layer120protrudes from the field plate132towards the drain electrode144. In addition, there is a distance d3between the third portion120-3of the gate dielectric layer120and the drain region111. The distance d3may be greater than the first distance d1between the source electrode142and the gate electrode131. FIG.2is a schematic cross-sectional diagram of an area A of a semiconductor device100as shown inFIG.1according to another embodiment of the present disclosure. As shown inFIG.2, in some other embodiments, the gap133P between the gate electrode131and the field plate132may be directly above the second portion120-2of the gate dielectric layer120. In some other embodiments, as shown inFIG.2, an edge of the gate electrode131near the gap133P may be aligned with an edge of the step of the second portion120-2of the gate dielectric layer120. Another edge of the gate electrode131may be aligned with an edge of the step of the first portion120-1of the gate dielectric layer120. In the embodiment, an edge of the field plate132near the gap133P is back inwards from the edge of the step of the second portion120-2of the gate dielectric layer120. The other features of the semiconductor device ofFIG.2may be the same as those of the semiconductor device100ofFIG.1, and not repeated herein. FIG.3is a schematic cross-sectional diagram of a semiconductor device according to a comparative example of the present disclosure. As shown inFIG.3, a semiconductor device200of a comparative example of the present disclosure includes a gate layer230disposed on a gate dielectric layer220. The gate dielectric layer220includes a first portion220-1having a fourth thickness T4, and a second portion220-2having a fifth thickness T5, where the fourth thickness T4is smaller than the fifth thickness T5. In one comparative example, for example, the fourth thickness T4may be 102 Angstroms and the fifth thickness T5may be 510 Angstroms. The gate layer230includes a first portion disposed on the first portion220-1of the gate dielectric layer220, and a second portion disposed on the second portion220-2of the gate dielectric layer220, where the first and second portions of the gate layer230are continuous without a gap therebetween. The first portion of the gate layer230has a fourth length L4and is used as a gate electrode. The second portion of the gate layer230has a fifth length L5and is used as a field plate. In one comparative example, for example, the fourth length L4may be 0.4 μm and the fifth length L5may be 0.3 μm. Moreover, a first spacer235-1and a second spacer235-2are disposed on two sidewalls of the gate layer230respectively. The other features of the semiconductor device200ofFIG.3may be the same as those of the semiconductor device100ofFIG.1, and not repeated herein. FIG.4AandFIG.4Bshow doping concentration profiles of semiconductor devices according to a comparative example and one embodiment of the present disclosure. As shown inFIG.4A, a profile401is obtained from a semiconductor device according to one embodiment of the present disclosure, such as the semiconductor device100ofFIG.1. A profile402is obtained from a semiconductor device according to a comparative example of the present disclosure, such as the semiconductor device200ofFIG.3. In addition, the profiles401and402are taken along a horizontal cutline at the middle of a channel region of the semiconductor device100ofFIG.1and the semiconductor device200ofFIG.3, respectively. The profiles401and402are doping concentrations varying with respect to different horizontal positions. When compared the profiles401and402, it is observed that the doping concentration of the drift region of the semiconductor device100of one embodiment of the present disclosure is higher than the doping concentration of the drift region of the semiconductor device200of the comparative example. As shown inFIG.4B, a profile403is obtained from the semiconductor device100ofFIG.1, and a profile404is obtained from the semiconductor device200ofFIG.3. The profiles403and404are taken along a vertical cutline at the top surface of the substrate101and at the middle of the channel region of the semiconductor device100ofFIG.1and the semiconductor device200ofFIG.3, respectively. The profiles403and404are doping concentrations varying with different depths. When compared the profiles403and404, it is observed that the doping concentration of the drift region of the semiconductor device100of one embodiment of the present disclosure is higher than the doping concentration of the drift region of the semiconductor device200of the comparative example. In addition, the area of drift region of the semiconductor device100of one embodiment of the present disclosure is larger than area of the drift region of the semiconductor device200of the comparative example. As shown in the doping concentration profiles ofFIG.4AandFIG.4B, the doping concentration and the area of the drift region of the semiconductor device100according to the embodiments of the present disclosure are greater than these of the semiconductor device200of the comparative example. Therefore, the on-state resistance (Ron) of the semiconductor devices according to the embodiments of the present disclosure is decreased as a consequence of increased drift region doping which enhances the current flow and reduces the Ron. FIG.5AandFIG.5Bshow electric field intensity profiles of semiconductor devices according to a comparative example and one embodiment of the present disclosure. As shown inFIG.5A, a profile501is obtained from the semiconductor device100ofFIG.1according to one embodiment of the present disclosure. A profile502is obtained from the semiconductor device200ofFIG.3according to a comparative example of the present disclosure. In addition, the profiles501and502are taken along a horizontal cutline at the top surface of the substrate101of the semiconductor device100ofFIG.1and the semiconductor device200ofFIG.3, respectively. The profiles501and502are electric field intensities varying with different horizontal positions at an operating voltage of 14.4V. When compared the profiles501and502, it is observed that the highest surface electric field intensity of the semiconductor device100of the embodiment of the present disclosure is lower than the highest surface electric field intensity of the semiconductor device200of the comparative example. As shown inFIG.5B, a profile503is obtained from the semiconductor device100ofFIG.1according to one embodiment of the present disclosure. A profile504is obtained from the semiconductor device200ofFIG.3according to a comparative example of the present disclosure. The profiles503and504are also taken along a horizontal cutline at the top surface of the substrate101of the semiconductor device100ofFIG.1and the semiconductor device200ofFIG.3, respectively. The profiles503and504are electric field intensities varying with different horizontal positions at an operating voltage of 20V. When compared the profiles503and504, it is observed that the highest surface electric field intensity of the semiconductor device100of the embodiment of the present disclosure is also lower than the highest surface electric field intensity of the semiconductor device200of the comparative example which operate at a higher operating voltage than that ofFIG.5A. As shown in the electric field intensity profiles ofFIG.5AandFIG.5B, the surface electric field intensity of the semiconductor device100according to the embodiment of the present disclosure is lower than that of the semiconductor device200of the comparative example. The reduced surface electric field effect is achieved by the increased thickness T2of the second portion120-2of the gate dielectric layer120over the drift region of the semiconductor device100according to the embodiments of the present disclosure. The thicker gate dielectric layer over the drift region releases the electric field distribution. Therefore, the on-state resistance (Ron) of the semiconductor devices according to the embodiments of the present disclosure is decreased as a consequence of the reduced surface electric field effect which enhances the current driving capability and reduces the Ron. Moreover, according to the embodiments of the present disclosure, the increased thickness of the gate dielectric layer over the drift region sustains the off-state breakdown voltage of the semiconductor devices. In addition, the lower electric field intensity boosts the reliability performance of the semiconductor devices of the present disclosure. While compared the aforementioned embodiment of the present disclosure with the comparative example, it is observed that the Ron of the embodiment is reduced about 16.73% than the Ron of the comparative example. The off-state breakdown voltage of the embodiment is at the same level of the comparative example, for example about 20.80V to 21.04V. In addition, the saturation current of the embodiment is increased about 20.49% than that of the comparative example. Therefore, according to the embodiments of the present disclosure, the on-state resistance (Ron or Rdson) of the semiconductor devices is reduced. In addition, the saturation current (Idsat) of the semiconductor devices is increased. Meanwhile, the off-state breakdown voltage (VBD) of the semiconductor devices is sustained. FIG.6,FIG.7,FIG.8,FIG.9andFIG.10are schematic cross-sectional diagrams of several intermediate stages of fabricating a semiconductor device according to one embodiment of the present disclosure. Referring toFIG.6, in some embodiments, after the well regions103and105, the source region109, the drain region111and the STI107are formed in the substrate101, a first dielectric layer121is formed on the well regions103and105, and between the source region109and the drain region111. The first dielectric layer121may be formed by a deposition process and an etching process. Next, referring toFIG.7, in some embodiments, the first dielectric layer121includes a first region121-1, a second region121-2and a third region121-3. A patterned mask113is formed over the substrate101and covers the first region121-1of the first dielectric layer121. The patterned mask113has an opening to expose the second region121-2and the third region121-3of the first dielectric layer121. Then, in some embodiments, a second dielectric layer122is formed on the second region121-2and the third region121-3of the first dielectric layer121by a deposition process through the opening of the patterned mask113. Thereafter, referring toFIG.8, in some embodiments, another patterned mask115is formed on the second dielectric layer122at the second region121-2of the first dielectric layer121. A third dielectric layer123is then formed on the second dielectric layer122at the third region121-3of the first dielectric layer121by a deposition process through an opening formed of the patterned mask113and the patterned mask115. In some embodiments, the first dielectric layer121, the second dielectric layer122and the third dielectric layer123may be formed of the same material. In some other embodiments, the first dielectric layer121, the second dielectric layer122and the third dielectric layer123may be formed of the materials that are different from each other. The materials of the first dielectric layer121, the second dielectric layer122and the third dielectric layer123may include silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The deposition processes of forming the first dielectric layer121, the second dielectric layer122and the third dielectric layer123are such as a CVD process, other applicable processes, or a combination thereof. In some embodiments, the first dielectric layer121and the second dielectric layer122may have the same thickness. The thickness of the third dielectric layer123may be greater than that of the first dielectric layer121and the second dielectric layer122. For example, the thicknesses of the first dielectric layer121, the second dielectric layer122and the third dielectric layer123may be 80 Angstroms, 80 Angstroms and 300 Angstroms, respectively, but not limited thereto. Referring toFIG.1andFIG.8, in some embodiments, the first portion120-1of the gate dielectric layer120is formed from the first region121-1of the first dielectric layer121, the second portion120-2of the gate dielectric layer120is formed from the second region121-2of the first dielectric layer121and a portion of the second dielectric layer122thereon, and the third portion120-3of the gate dielectric layer120is formed from the third region121-3of the first dielectric layer121and another portion of the second dielectric layer122and the third dielectric layer123thereon. Next, referring toFIG.9, in some embodiments, the patterned masks113and115are removed and then another patterned mask117is formed over the substrate101. The patterned mask117has an opening to expose the gate dielectric layer120. Thereafter, a gate material layer130is conformally deposited on the gate dielectric layer120. The gate material layer130may be deposited by a CVD process (e.g., a low pressure chemical vapor deposition process (LPCVD), or a plasma enhanced chemical vapor deposition process (PECVD)), a PVD process (e.g., a resistive heating evaporation process, an e-beam evaporation process, or a sputtering process), an electroplating process, an ALD process, other applicable processes, or a combination thereof. Referring toFIG.10, in some embodiments, the gate material layer130is then patterned by a photolithography process and an etching process to form the gate electrode131and the field plate132. The photolithography process is such as photoresist coating, soft baking, exposure, post-exposure baking, development, other applicable techniques, or a combination thereof. The etching process is such as a wet etching process, a dry etching process, other applicable techniques, or a combination thereof. According to the embodiments of the present disclosure, the gate electrode131and the field plate132are separated from each other by the gap133P. In some embodiments, the gap133P between the gate electrode131and the field plate132may be formed directly above the first portion120-1of the gate dielectric layer120as shown inFIG.1. In some other embodiments, the gap133P may be formed directly above the second portion120-2of the gate dielectric layer120as shown inFIG.2. The position of the gap133P and the lengths of the gate electrode131and the field plate132may be controlled by the patterned photoresist used in the photolithography process. Thereafter, the other features such as the gate spacers135-1,135-2and135-3, the ILD140, the source electrode142, the drain electrode144ofFIG.1, and other features are formed over the substrate101to complete the semiconductor device100ofFIG.1. According to the embodiments of the present disclosure, the gate electrode and the field plate disposed on the gate dielectric layer of the triple step-shaped structure having three different thicknesses achieves sufficient reduced surface field (RESURF) effect that decreases the on-state resistance (Ron), increases the saturation current (Idsat) and sustains the off-state breakdown voltage of the semiconductor devices. The thinner first portion of the gate dielectric layer reduces the electric field intensity at the channel region which enhances current driving capability to reduce the Ron of the semiconductor devices of the present disclosure. The thicker second and third portions of gate dielectric layer release the electric field distribution which sustains the off-state breakdown voltage of the semiconductor devices of the present disclosure. In addition, the increased doping concentration profile at the drift region also enhances the current driving capability to reduce the Ron of the semiconductor devices of the present disclosure. Moreover, the lower electric field boosts reliability performance of the semiconductor devices of the present disclosure. Therefore, the electrical performances and reliability of the semiconductor devices according to the embodiments of the present disclosure are improved. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. | 31,776 |
11942543 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. FIG.1is a layout top view of a semiconductor device structure100, in accordance with some embodiments. In some embodiments, the semiconductor device structure100includes a high-voltage device region R1where one (or more) high-voltage voltage device is formed. The high-voltage device may include a metal-oxide-semiconductor field-effect transistor (MOSFET) which is capable of operating at high voltage. For example, the high-voltage device is capable of operating at a voltage that is in a range from about 250 V to about 1000 V. In some embodiments, the semiconductor device structure100also includes a low-voltage device region R2where one (or more) low-voltage device is formed. The low-voltage device operates at a lower voltage than the high-voltage device. In some embodiments, the low-voltage device region R2is adjacent to the high-voltage device region R1. In some embodiments, the low-voltage device region R2laterally surrounds the high-voltage device region R1. In some embodiments, a first doped region (such as a well region) in the high-voltage device region R1is in direct contact with a second doped region (such as another well region) in the low-voltage device region R2. In some embodiments, the first doped region has a conductivity type opposite to that of the second doped region. For example, the first doped region of the high-voltage device region R1is an n-type well region, and the second doped region of the low-voltage device region R2is a p-type well region. In some embodiments, the high-voltage device region R1has a periphery (or boundary)102. In some embodiments, the periphery102is also an interface between the high-voltage device region R1and the low-voltage device region R2. In some embodiments, the semiconductor device structure100includes a conductor106. The conductor106includes, for example, a conductive line. The conductor106is electrically connected to an element (such as a drain region or a source region) of the high-voltage device in the high-voltage device region R1. The conductor106extends over and across the periphery102of the high-voltage device region R1and extends further over the low-voltage device region R2. During operation of the high-voltage device, a high voltage may be applied to the high-voltage device through the conductor106. When the high voltage is applied to the high-voltage device through the conductor106, the conductor106with high voltage may negatively affect the operation of the low-voltage device in the low-voltage device region R2. For example, an inversion channel region may be unintentionally formed near the interface between the high-voltage device and the low-voltage device, which may form an electrical path leading to high leakage current. In some cases, the low-voltage device may be formed at a position away from the high-voltage device to prevent the high leakage current. A forbidden area surrounding the high-voltage device region R1may be designed. The low-voltage device is formed outside of the forbidden area to maintain a sufficient distance from the high-voltage device region. Therefore, the low-voltage device may be prevented from being negatively affected by the high-voltage device. However, the design mentioned above would occupy larger die area, which negatively affects the scaling-down of the semiconductor device structure. The design flexibility is also limited. As shown inFIG.1, a shielding element104is formed to cover the periphery102between the high-voltage device region R1and the low-voltage device region R2, in accordance with some embodiments. The shielding element104may be used to prevent the generation of the channel region near the interface between the high-voltage device and the low-voltage device. Leakage current may therefore be avoided or effectively reduced. In some embodiments, the shielding element104is positioned below the conductor106and above the periphery102of the high-voltage device region R1. In some embodiments, the shielding element104extends over and across the periphery102of the high-voltage device region R1. In some embodiments, the shielding element104is a ring structure. In some embodiments, the shielding element104is a shielding element ring. In some embodiments, the shielding element104covers the periphery102of the high-voltage device region R1. In some embodiments, the shielding element104encircles the high-voltage device region R1. In some embodiments, the shielding element104has a first portion104A extending on the high-voltage device region R1. The shielding element104also has a second portion104B extending on the low-voltage device region R2. In some cases where a high voltage bias is applied on the conductor106, an outer portion of the low-voltage region R2not covered by the shielding element104may become an inversion channel region due to the high electric field generated from the conductor106. Electrons may accumulate in the inversion channel region. Meanwhile, a portion of the high-voltage region R1directly below the first portion104A and an inner portion of the low-voltage region R2directly below the second portion104B are shielded by the shielding element104. Due to the shielding element104, electric field generated from the conductor106is shielded to avoid accumulating electrons in the region under the shielding element104. That is, the region directly below the shielding element104is prevented from becoming an inversion channel region. The high-voltage region R1is therefore electrically separated from the inversion channel region in the outer portion of the low-voltage region R2by the region directly below the shielding element104. Leakage path from the high-voltage region R1to the low-voltage region R2is therefore avoided. In some embodiments, the shielding element104is made of a conductive material. The conductive material may include a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof. In some embodiments, the shielding element104covers an entirety of the periphery102of the high-voltage device region R1. In some embodiments, the shielding element104extends along the periphery102of the high-voltage device region R1. The electrical field from the conductor106applied with high voltage may be blocked or at least partially blocked by the shielding element104. Therefore, the elements thereunder may be prevented from being negatively affected by the conductor106applied with high voltage. The performance and reliability of the semiconductor device structure100are significantly improved. FIG.2Ais a layout top view of a semiconductor device structure, in accordance with some embodiments.FIG.2Bis a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG.2Bshows the cross-sectional view of the semiconductor device structure illustrated inFIG.2A. The cross-sectional view may be taken along the line I-I′. In some embodiments, as shown inFIGS.2A and2B, a semiconductor device structure200is provided. The semiconductor device structure200includes a high-voltage device region R1where one (or more) high-voltage device is formed. For example, a transistor T is formed in the high-voltage device region R1. As shown inFIGS.2A and2B, the semiconductor device structure200also includes a low-voltage device region R2where one (or more) low-voltage device is formed. The low-voltage device may include a transistor including a doped region224, as shown inFIG.2B. In some embodiments, the doped region224is a well region. For example, the doped region224is a p-type doped well region. In some other embodiments, the doped region224is n-type doped. In some embodiments, the transistor T includes a doped region such as a drain region202, a gate stack204, and a doped region such as a source region206. In some embodiments, the transistor T is a high-voltage MOSFET. In some embodiments, the source region206is a ring structure that laterally surrounds the drain region202, as shown inFIG.2A. In some embodiments, the source region206is a source ring. In some embodiments, the drain region202takes the form of a circle, while each of the source region206and the gate stack204takes the form of a ring, as shown inFIG.2A. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the top view of the drain region202has a shape other than circle. The top view shape of the drain region202may include rectangle, square, oval, polygon, or another suitable shape. The top view shape of the source region206or the gate stack204is a rectangular ring, a square ring, an oval ring, a polygonal ring, or another suitable ring. In some embodiments, the drain region202is laterally surrounded by the gate stack204, which in turn is laterally surrounded by the source region206, as shown inFIG.2A. In some embodiments, the source region206is laterally surrounded by an isolation structure (or called isolation element)208. The isolation structure208is configured to isolate electrical communication between the source region206and another electronic component, such as another transistor formed in the low-voltage device region R2. The isolation structure208may include a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, a field oxide (FOX) structure, a deep trench isolation (DTI) feature, one or more other suitable isolation features, or a combination thereof. In some embodiments, the gate stack204is electrically connected to a conductor210A for interconnection, as shown inFIG.2A. The conductor210A may be a conductive line. The source region206is electrically connected to a conductor212A for interconnection. The conductor212A may be a conductive line. The drain region202is electrically connected to a conductor212B for interconnection. The conductor212B may be a conductive line. The conductors212A and212B may be formed from patterning the same conductive film. The conductors212A and212B may be conductive lines at the same height level. In some embodiments, top surfaces of the conductors212A and212B are substantially coplanar. In some embodiments, the conductors212A and212B are electrically isolated from each other. In some embodiments, the conductor210A is at a lower height level than the conductors212A and212B. In some embodiments, a portion of the conductor210A is positioned below the conductor212A, as shown inFIG.2A. One or more dielectric layers may be formed between the conductors212A and210A. In some embodiments, as shown inFIG.2A, a connection area7, including pickup regions D, S and G, separated from the transistor T is provided to facilitate interconnection of the drain region202, the source region206, and the gate stack204, respectively. In some embodiments, a portion of the conductor210A takes the form of a discontinuous ring over the ring-shape gate stack204, as shown inFIG.2A. In some embodiments, a portion of the conductor212B extends in the I-I′ direction between the drain region202and the connection area7. The conductors212B and210A are designed to be not overlapping each other. Therefore, an undesirable coupling effect between the conductors212B and210A may be prevented or reduced. In some embodiments, the transistor T includes a metal-oxide-semiconductor field-effect transistor (MOSFET). In some other embodiments, the transistor T includes a high-voltage MOSFET capable of operating at high voltage that is, for example, in a range from about 250 V to about 1000 V. Alternatively, the transistor T includes bipolar junction transistors (BJTs), complementary MOS (CMOS) transistors, etc. In some embodiments, the transistor T is used in a power device, such as a power diode and a thyristor. FIG.2Bshows a cross-sectional view of the semiconductor device structure200as shown inFIG.2Ataken along a line I-I′, in accordance with some embodiments. In some embodiments, the semiconductor device structure200includes a semiconductor substrate201and doped regions214and216. In some embodiments, the doped regions214and216are well regions with opposite conductivity types. For example, the doped region214may be n-type doped, and the doped region216may be p-type doped. In some embodiments, the doped region216is a ring region laterally surrounds the drain region202. The doped region216may surround or cover sides and a bottom of the source region206, as shown inFIG.2B. In some embodiments, the doped region214has a periphery (or boundary)226which defines the periphery of the high-voltage device region R1. In some embodiments, the doped region214in the high-voltage device region R1is in direct contact with the doped region224in the low-voltage device region R2. The periphery226may also be an interface between the doped regions214and224. In some embodiments, the doped regions214and224are well regions having opposite conductivity types. In some embodiments, the doped region214is n-type, and the doped region224is p-type. In some other embodiments, the doped region214is p-type, and the doped region224is n-type. In some embodiments, the drain region202of the transistor T is formed in the doped region214in the semiconductor substrate201. The doped region214surrounds or covers the sides and bottom of the drain region214, as shown inFIG.2B. In some embodiments, the drain region202and the doped region214have the same conductivity type. For example, both the drain region202and the doped region214are n-type doped. In some embodiments, the drain region202has a greater dopant concentration than that of the doped region214. In some embodiments, the source region206of the transistor T is formed in the doped region216within the doped region214. The doped region214surrounds or covers the sides and bottoms of the drain region202and the doped region216, as shown inFIG.2B. In some embodiments, the source region206and the doped region216have opposite conductivity types. For example, the source region206is n-type doped, and the doped region216is p-type doped. In some embodiments, the gate stack204of the transistor T is disposed over the doped region214and extends on an isolation structure207. The isolation structure207may be similar to the isolation structure208. The gate stack204may include a gate dielectric layer205A and a gate electrode205B. The gate dielectric layer205A may be made of silicon oxide or another suitable high-k dielectric material. The gate electrode205B may be made of polysilicon. In some other embodiments, the gate electrode205B is a metal gate electrode. The metal gate electrode may include one or more work function layers. In some embodiments, the gate stack204has a ring structure, as shown inFIG.2A. As shown inFIG.2B, a channel region15may be defined under the gate stack204between the drain region202and the source region206in the doped region214. The dopant type of the doped region216is opposite to that of the doped region214. For example, when the doped region216is p-type, then the doped region214is n-type. Alternatively, when the doped region216is n-type, then the doped region214is p-type. In some embodiments, the doped region214is a high-voltage n-well. As shown inFIGS.2A and2B, the drain region202is electrically connected to the connection area7through conductive features including a conductive contact218, a conductor210B, a conductive via220, and the conductor212B, in accordance with some embodiments. The conductive features are surrounded with multiple dielectric layers including, for example, dielectric layers222A,222B, and222C. One or more etch stop layers (not shown) may be formed between the dielectric layers. The isolation structure207defines a length of the drain region202. In some embodiments, the semiconductor substrate201is made of or includes silicon, silicon germanium, gallium arsenic, silicon carbon, one or more other suitable semiconductor materials, or a combination thereof. In some embodiments, the semiconductor substrate201is semiconductor on insulator such as silicon on insulator (SOI). In some other embodiments, the semiconductor substrate201includes a doped epi-layer, a gradient semiconductor layer, or further includes a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer. In some embodiments, the semiconductor substrate201is doped with a dopant of p-type, and the drain region202and source region206are doped with a dopant of n-type. As such, the semiconductor substrate201, the drain region202, and source region206define an n-type semiconductor device, such as an n-channel metal-oxide-semiconductor field effect transistor (MOSFET). Alternatively, for example, the semiconductor substrate201is doped with a dopant of n-type, and the drain region202and the source region206are doped with a dopant of p-type. As such, the semiconductor substrate201, the drain region202, and the source region206define a p-type semiconductor device, such as a p-channel metal-oxide-semiconductor field effect transistor (MOSFET). It should be noted that a drain region and a source region are interchangeable depending on a voltage applied thereto. In an n-type metal-oxide-semiconductor field-effect transistor (NMOS), a drain region may receive a first voltage, and a source region may receive a second voltage lower than the first voltage. In a p-type metal-oxide-semiconductor field-effect transistor (PMOS), a drain may receive a first voltage, and a source may receive a second voltage higher than the first voltage. During operation of the transistor T in the high-voltage device region R1, a high voltage may be applied to the drain region202through the conductor212B. When the high voltage is applied to the high-voltage device through the conductor212B, the conductor212B may negatively affect the operation of the low-voltage device in the low-voltage device region R2. For example, an inversion channel region may be unintentionally formed in the doped region224near the periphery226of the doped region214. Once the inversion channel region is formed, an electrical path leading to high leakage current between the doped regions214and224may be formed. As shown inFIGS.2A and2B, a shielding element228is formed over and across the interface between the high-voltage device region R1and the low-voltage device region R2, in accordance with some embodiments. In some embodiments, the shielding element228is a shielding element ring, as shown inFIG.2A. In some embodiments, the shielding element228has a first portion228A extending on the high-voltage device region R1. The shielding element228also has a second portion228B extending into the low-voltage device region R2. The shielding element228may be used to prevent the formation of the inversion channel region near the periphery226of the doped region214that is directly below the shielding element228. In some cases where a high voltage bias is applied on the conductor212B, an outer portion of the doped region224not covered by the shielding element104may become a strong inversion channel region due to the high electric field generated from the conductor212B. Electrons may accumulate in the inversion channel region. Meanwhile, a portion of the doped region214directly below the first portion228A and an inner portion of the doped region224directly below the second portion228B are shielded or protected by the shielding element104. Due to the shielding element228, electric field generated from the conductor212B is shielded to avoid accumulating electrons in the region under the shielding element228. That is, the region directly below the shielding element228is prevented from becoming an inversion channel region. The doped region214is therefore electrically separated from the inversion channel region in the outer portion of the doped region224by the region directly below the shielding element228. For example, even if the outer portion of the doped region224becomes an inversion channel region, the inner portion of the doped region224is not inversed and still acts as a p-type doped well region. Electrons are prevented from penetrating through the inner portion of the doped region224shielded by the shielding element228. Leakage path from the high-voltage region R1to the low-voltage region R2is therefore avoided. Carriers from the doped region214are also prevented from entering the doped region224. Leakage current may therefore be avoided or reduced. In some embodiments, the shielding element228is positioned between the conductor212B and the periphery226of the doped region214(which is also the periphery of the high-voltage device region R1). In some embodiments, the shielding element228extends over and across the periphery226. In some embodiments, the shielding element228covers the entire top surface of the periphery226of the high-voltage device region R1. In some embodiments, the shielding element228encircles the high-voltage device region R1. The shielding element228laterally surrounds the doped regions214and216, the source region206, the gate stack204, and the drain region202. In some embodiments, the shielding element228is made of a conductive material. The conductive material may include a metal material, a semiconductor material, one or more other suitable materials, or a combination thereof. In some embodiments, the shielding element228and the gate electrode205B are made of the same material. In some embodiments, a polysilicon layer is formed first, and then the polysilicon layer is patterned to form the gate electrode205B and the shielding element228. In some embodiments, a dielectric layer229is formed between the shielding element228and the semiconductor substrate201. In some embodiments, the dielectric layer229and the gate dielectric layer205A are made of the same material. In some embodiments, the dielectric layer229and the gate dielectric layer205A are formed by patterning the same dielectric film. The high electrical field from the conductor212B may be blocked or at least partially blocked by the shielding element228. Therefore, the elements thereunder may be prevented from being negatively affected by the conductor212B applied with high voltage. Due to the shielding element228, there is substantially no inversion channel region formed near the region covered by the shielding element228. Even if an outer portion of the doped region224becomes an inversion channel region, the inner portion of the doped region224that still acts as a p-type well region may block the accumulated electrons in the inversion channel regions from entering the doped region214. No conductive path is formed between doped regions214and224. Leakage current is significantly reduced. The performance and reliability of the semiconductor device structure200are significantly improved. Since the shielding element228may be used to cut the undesired electrical connection path between the high-voltage device region R1and low-voltage device region R2, the low-voltage devices may be formed or designed to be closer to the high-voltage device region R1. For example, the well regions of the high-voltage device region R1and low-voltage device region R2may be formed or designed to be in direct contact with each other. The layout design of the high-voltage device region R1and low-voltage device region R2becomes more flexible. It may not be needed to design a forbidden area surrounding the high-voltage device region R1, which facilitates the scaling-down and performance improvement of the semiconductor device structure. The shielding element228may also have some other advantages. For example, some advantages of the shielding element228are discussed below by way of comparison between an existing approach without such shielding element228and the transistor T with the shielding element228. In some existing transistors free of a protective layer (or a barrier layer) such as the shielding element228, an electric field established by an interconnect structure such as the conductor212B might adversely affect an isolation component, such as the isolation structure208, disposed near the source region206of the transistor. Consequently, degradation on the voltage level at the source region206may be likely to occur. In some cases, the semiconductor device structure200is not provided with the shielding element228, the semiconductor substrate201is a p-type substrate, the doped region214is an n-well, and the doped region216is a p-well. Since the electric field is very strong due to an ultra-high voltage, negative charge in the doped region214(n-well) is accelerated by the electric field, injected from the n-doped region214to the isolation structure208and trapped in the isolation structure208due to quantum mechanical direct tunneling or Fowler-Nordheim tunneling. The trapped negative charge in the isolation structure208depletes the n-doped region214near the isolation structure208, resulting in positive charge in the n-doped region214. Consequently, punch-through may occur in the n-doped region214under the isolation structure208, leading to leakage from the p-doped region216via the n-doped region214under the isolation structure208towards the semiconductor substrate201. As a result, the voltage level at the source region206is decreased (i.e., degradation) when the transistor T is enabled. In some embodiments inFIG.2B, the semiconductor substrate201is a p-type substrate, the doped region214is an n-well and the doped region216is a p-well. Since the electric field is shielded by the shielding element228, negative charge in the n-doped region214is not accelerated by the electric field and therefore is not injected from the n-doped region214to the isolation structure208. The negative charge still remains in the n-doped region214. Accordingly, substantially no depletion occurs in the n-doped region214under the isolation structure208. Substantially no punch-through occurs in the n-doped region214under the isolation structure208. There is substantially no leakage current path from the p-doped region216to the semiconductor substrate201. As a result, the voltage level at the source region206may substantially be kept intact and thus no degradation occurs when the transistor T is enabled. Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the conductor212B extending across the periphery226of the doped region214is not electrically connected to the drain region202. In some embodiments, the conductive layer extending across the periphery226of the doped region214is electrically connected to the source region206. Many variations and/or modifications can be made to embodiments of the disclosure.FIG.3is a cross-sectional view of a semiconductor device structure300, in accordance with some embodiments. Referring toFIG.3, the semiconductor device structure300is similar to the semiconductor device structure200described and illustrated with reference toFIG.2B. The main difference therebetween may include that the semiconductor device structure300includes a conductive element such as a voltage source302. The voltage source302is configured to provide a voltage Vs to the shielding element228. Since the voltage level of the shielding element228serving as a shield component is Vs, a source floating capability (SFC) of the transistor T is enhanced, as will be discussed further below. Source floating capability refers to a voltage level at which a source terminal of a transistor can float. A higher voltage level at the source terminal of the transistor would lead to better source floating capability. Assuming that the semiconductor substrate201is a p-type substrate, the doped region214is an n-well and the doped region216is a p-well, the majority carrier in the n-doped region214is electron, while the majority carrier in the p-doped region216is electron hole. When the voltage Vs is applied to the shielding element228, the shielding element228may induce negative charge from the reference ground through the semiconductor substrate201to the n-doped region214. The negative charge may be accumulated in the n-doped region214. The shielding element228raised to the voltage level Vs may facilitate accumulation of negative charge in a part of the n-doped region214adjacent to the p-doped region216. The negative charge has the same electrical type as the majority carrier in the n-doped region214. Accordingly, the amount of negative-type charge in the n-doped region214, in a condition that the shielding element228is biased, is greater than that in a condition that the shielding element228is floating. The accumulated negative-type charge may facilitate to block the leakage current path to the semiconductor substrate201or to the low-voltage device region R2. The source floating capability may be enhanced. The enhanced source floating capability may enable the source of the transistor T to operate at a higher voltage level. Therefore, the transistor T may be more power efficient. When the transistor T is disabled, the source voltage of the transistor T at a higher level may cause the gate-to-source voltage (VGS) of the transistor T to accordingly decrease. As a result, leakage current from the disabled transistor T is reduced or even eliminated. The transistor T may have no parasitic power dissipation resulting from the leakage current. The semiconductor device structure300may not only prevent the degradation on the voltage level at the source region206of the transistor T, but also may enhance the source floating capability. FIG.4is a cross-sectional view of a semiconductor device structure400, in accordance with some embodiments. The semiconductor device structure400may be similar to the semiconductor device structure200illustrated inFIG.2B. The main difference therebetween may include that the position of the shielding element is changed. In some embodiments, the shielding element228is replaced with a shielding element428. In some embodiments, the shielding element428is a ring structure. In some embodiments, the shielding element428extends over and across the periphery226. In some embodiments, the shielding element428covers an entirety of the periphery226. Unlike the shielding element228that is disposed directly on the isolation structure208, the shielding element428is disposed over the isolation structure208. For example, the shielding element428is formed over the dielectric layer222A. The shielding element428is configured to alleviate the effect of an electric field established by the conductor212B. For similar reasons as provided in the embodiment ofFIG.2B, since the shielding element428is disposed between the conductor212B and the periphery226of the high-voltage device region R1, the current leakage is significantly reduced or prevented. The effect of the electric field on the isolation structure208is also weakened or even eliminated. As a result, degradation on a voltage level at the source region206may also be alleviated or even eliminated. In some embodiments, the shielding element428is made of or includes a semiconductor material, a metal material, one or more other suitable materials, or a combination thereof. In some embodiments, the shielding element428and the conductor210B are formed from patterning the same conductive film. In these cases, the shielding element428and the conductor210B are made of the same material. In some embodiments, the shielding element428is substantially as high as the conductor210B. In some embodiments, top surfaces of the shielding element428and the conductor210B are substantially positioned at the same height level. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, both the shielding element428and the shielding element228are formed. Many variations and/or modifications can be made to embodiments of the disclosure.FIG.5is a cross-sectional view of a semiconductor device structure500, in accordance with some embodiments. The semiconductor device structure500may be similar to the semiconductor device structure400illustrated inFIG.4. As shown inFIG.5, a conductive element such as a voltage source302is provided, in accordance with some embodiments. The voltage source302is configured to provide a voltage Vs to the shielding element428. The shielding element428raised to the voltage Vs may facilitate accumulation of charge in the doped region214. Accordingly, source floating capability (SFC) of the transistor T is enhanced. For the similar reasons as provided in the embodiment ofFIG.3, as a result of the enhanced source floating capability, leakage current in the disabled transistor T may also be reduced or even eliminated. Accordingly, the semiconductor device structure500may not only prevent the degradation on the voltage level of the source region206of the transistor T, but also enhances the source floating capability. Many variations and modifications can be made to embodiments of the disclosure.FIG.6is a cross-sectional view of a semiconductor device structure600, in accordance with some embodiments. The semiconductor device structure600may be similar to the semiconductor device structure200illustrated inFIG.2B. In some embodiments, the source region206and the shielding element228are electrically shorted together. In some embodiments, conductive features602A,602B, and602C are used to short the source region206and the shielding element228together. The conductive features602A and602C may include conductive contacts and/or conductive vias. The conductive feature602B may be a conductive line. When the transistor T is enabled, the conductive layer602B raised to a voltage level as the source region206may facilitate accumulation of charge in the doped region214. Accordingly, the source floating capability (SFC) of the transistor T is enhanced. For the similar reasons provided in the embodiment ofFIG.3, as a result of the enhanced source floating capability, leakage current in the transistor T when disabled is reduced or even eliminated. Accordingly, the transistor T may have substantially no parasitic power dissipation resulting from the leakage current. Many variations and/or modifications can be made to embodiments of the disclosure.FIG.7is a cross-sectional view of a semiconductor device structure700, in accordance with some embodiments. In some embodiments, the conductive features602A,602B, and602C are not formed directly below the conductor212B. The conductive features602A,602B, and602C may be designed to be positioned at different positions. In some embodiments,FIG.7shows the cross-sectional view of the structure shown inFIG.2Ataken along the line J-J′. In some embodiments, the conductive features602A,602B, and602C formed for shorting the shielding element228and the source region206are formed at a position other than directly below the conductor212B. Many variations and/or modifications can be made to embodiments of the disclosure.FIG.8Ais a layout top view of a semiconductor device structure, in accordance with some embodiments.FIG.8Bis a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. In some embodiments,FIG.8Ashows the layout top view of the structure shown inFIG.8B. For clarity, some elements inFIG.8Bare not shown inFIG.8A. As shown inFIGS.8A and8B, a second shielding element228′ is formed, in accordance with some embodiments. The second shielding element228′ may be used to ensure no current leakage path is formed between the high-voltage device region R1and the low-voltage device region R2. In some embodiments, the second shielding element228′ is a ring structure. In some embodiments, the second shielding element228′ laterally surrounds the shielding element228which laterally surrounds the high-voltage device region R1and covers the periphery226between the high-voltage device region R1and the low-voltage device region R2. In some embodiments, the second shielding element228′ encircles the shielding element228. In some embodiments, the second shielding element228′ and the shielding element228are formed from patterning the same material layer. In these cases, the shielding elements228and228′ are made of the same material. In some embodiments, top surfaces of the shielding elements228and228′ are substantially as high as each other. In some embodiments, a dielectric layer229′ may be formed below the second shielding element228′. The dielectric layers229′ and229may be made of the same material. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, one or more shielding elements are formed to laterally surround or encircle the shielding elements228and228′ to ensure that no leakage current path is formed. Embodiments of the disclosure form a semiconductor device structure with a high-voltage device region and a low-voltage device region. One (or more) shielding element is formed to extend across an interface between the high-voltage device region and the low-voltage device region. High electrical field generated from the high-voltage device region is shielded by the shielding element to prevent leakage current path from being formed and passing through the interface of the high-voltage device region and the low-voltage device region. The reliability and performance of device elements in the high-voltage device region and the low-voltage device region are significantly improved. It may not be needed to design a forbidden area between the high-voltage device region and the low-voltage device region, which facilitates the scaling-down of the semiconductor device structure. In accordance with some embodiments, a high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region. In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a high-voltage device region and a low-voltage device region. The semiconductor device structure also includes a first well region in the high-voltage device region, and the first well region surrounds sides and bottoms of a drain region and a source region. The semiconductor device structure further includes a second well region in the low-voltage device region and adjacent to the second well region, and the second well region has a conductivity type opposite to that of the first well region. In addition, the semiconductor device structure includes a conductor electrically connected to the drain region and extending across an interface between the first well region and the second well region. The semiconductor device structure further includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring covers the interface between the first well region and the second well region. In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a high-voltage transistor including a source region in a first well region within a second well region and a drain region in the second well region. The semiconductor device structure also includes a low-voltage device including a doped region. The doped region has a conductivity type opposite to that of the second well region, and the doped region is adjacent to the second well region. The semiconductor device structure further includes a conductor electrically connected to the high-voltage transistor and extending across an interface between the doped region of the low-voltage device and the second well region of the high-voltage transistor. In addition, the semiconductor device structure includes a shielding element ring between the conductor and the doped region. The shielding element ring extends over and across the interface. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 43,683 |
11942544 | DETAILED DESCRIPTION Various embodiments of the present invention disclosure will be described below in more detail with reference to the accompanying drawings. The present invention disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention disclosure. It will be understood that when an element is referred to as being “coupled” or “connected” to another element, it may mean that the two are directly coupled or electrically connected to each other with another circuit intervening therebetween. Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way. The terms an upper end and a lower end of an element as used herein may include an upper and a lower part or portion of the element. Hereinafter, the diverse embodiments of the present invention disclosure will be described in detail with reference to the attached drawings. The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate certain features of the embodiments. When a first layer is referred to as being ‘on’ a second layer or ‘on’ a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate. FIGS.1A to14Billustrate a semiconductor device and a method for fabricating the semiconductor device in accordance with an embodiment of the present invention disclosure. Figures denoted as1A,2A, etc. are cross-sectional views taken along a line B-B′ of corresponding figures denoted as1B,2B, etc.FIGS.1B,2B, etc. are plan views illustrated at the height of a line A-A′ of corresponding figures denoted as1A,2A, etc. The semiconductor device of this embodiment may include a CMOS transistor having an NMOS transistor and/or a PMOS transistor. First, a method for fabricating a semiconductor device in accordance with an embodiment of the present invention disclosure is described. Referring toFIGS.1A and1B, a substrate100may be provided. The substrate100may include a semiconductor material, such as, for example, silicon. Subsequently, a first initial stacked structure110A and a second initial stacked structure110B may be formed over the substrate100. Each of the first and second initial stacked structures110A and110B may have a rectangular shape from the perspective of a plan view. For example, each of the first initial stacked structure110A and the second initial stacked structure110B may have a bar shape in which a side length in a first direction is longer than a side length in a second direction. The first and second directions may be orthogonal to each other and may define a plane perpendicular to the direction of stacking which is referred to also as a vertical or a third direction. Also, the first and second initial stacked structures110A and110B may be disposed to be spaced apart from each other in the second direction so that one side111A in the second direction of the first initial stacked structure110A and one side111B in the second direction of the second initial stacked structure110B face each other from the perspective of a plan view. The one side111A of the first initial stacked structure110A and the one side111B of the second initial stacked structure110B facing each other may be inclined. The first initial stacked structure110A may include a first lower dielectric layer112A, a first sacrificial layer114A, and a first upper dielectric layer116A that are stacked in the vertical direction. The second initial stacked structure110B may include a second lower dielectric layer112B, a second sacrificial layer114B, and a second upper dielectric layer116B that are stacked in the vertical direction. Here, the first and second sacrificial layers114A and114B may serve to provide a space in which first and second gate electrode layers, which will be described later, are to be formed. The first and second lower dielectric layers112A and112B may serve to electrically disconnect the first and second gate electrode layers from the substrate100and a lower electrode layer, which will be described later. The first and second upper dielectric layers116A and116B may serve to electrically disconnect the first and second gate electrode layers from the first and second upper electrode layers, which will be described later. The first and second initial stacked structures110A and110B may be formed by sequentially depositing a dielectric material for forming the first and second lower dielectric layers112A and112B, a sacrificial material for forming the first and second sacrificial layers114A and114B, and a dielectric material for forming the first and second upper dielectric layers116A and116B over the substrate100, and then selectively etching them. Since the first and second sacrificial layers114A and114B are replaced by the first and second gate electrode layers in a subsequent process, the first and second sacrificial layers114A and114B may be formed of a material whose etch rate is different from those of the first and second lower dielectric layers112A and112B and the first and second upper dielectric layers116A and116B. For example, the first and second sacrificial layers114A and114B may include SiON (silicon oxynitride) or SiN (silicon nitride), and the first and second lower dielectric layers112A and112B and the first and second upper dielectric layers116A and116B may include SiCN (silicon carbon nitride), SiBCN (silicon boron carbon nitride), or SiCO (silicon carbon oxide). Subsequently, a conductive layer120may be formed over the substrate100to fill the remaining spaces except for the first and second initial stacked structures110A and110B. The conductive layer120may be used for forming a common electrode of an NMOS transistor and a PMOS transistor, for example, a lower electrode layer that functions as a common source electrode. The conductive layer120may be formed by depositing a conductive material having a thickness sufficient to cover the first and second initial stacked structures110A and110B while filling the space between the first and second initial stacked structures110A and110B over the substrate100, and performing a planarization process, for example, a Chemical Mechanical Polishing (CMP) process, until the upper surfaces of the first and second initial stacked structures110A and110B are exposed. The conductive layer120may include diverse conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo) and the like, a compound of the metal, or an alloy of the metal. Referring toFIGS.2A and2B, a conductive layer pattern120′ may be formed by removing a portion of the conductive layer120through an etch-back process or the like. In the vertical direction, the upper surface of the conductive layer pattern120′ may be positioned at a height that is equal to or lower than the upper surfaces of the first and second lower dielectric layers112A and112B. For the sake of convenience in description, in the plan view ofFIG.2B, the shape of the conductive layer pattern120′, which is not seen at the height of the line A-A′ ofFIG.2A, is illustrated by dotted lines. Subsequently, over the conductive layer pattern120′ and the first and second initial stacked structures110A and110B, a material layer130may be formed along the lower profile, that is, the upper surface of the conductive layer pattern120′, the sides of the first and second initial stacked structures110A and110B protruding above the conductive layer pattern120′, and the upper surfaces of the first and second initial stacked structures110A and110B. The material layer130may be provided for forming a channel of an NMOS transistor and a PMOS transistor. The material layer130may be conformally formed to have a thin thickness that does not completely fill the space between the first initial stacked structure110A and the second initial stacked structure110B. That is, the material layer130may be in a form of a thin film. For example, the material layer130may include a semiconductor material that is not doped with an impurity. In an embodiment, the material layer130may be an undoped silicon thin film. Referring toFIGS.3A and3B, a mask pattern M may be formed to extend in the first direction while overlapping with the space between the first initial stacked structure110A and the second initial stacked structure110B over the process result ofFIGS.2A and2B. Accordingly, the mask pattern M may cover the conductive layer pattern120′ and the material layer130between the first initial stacked structure110A and the second initial stacked structure110B, and may expose the conductive layer pattern120′ and the material layer130in the other region. Furthermore, although not illustrated, the mask pattern M may further overlap with at least a portion of the upper surfaces of the first and second initial stacked structures110A and110B. Referring toFIGS.4A and4B, a material layer pattern130′ and a lower electrode layer120″ may be formed by removing the material layer130and the conductive layer pattern120′ exposed by the mask pattern M by an etching method or the like. The lower electrode layer120″ may have a line shape which is positioned below the material layer pattern130′ between the first initial stacked structure110A and the second initial stacked structure110B and extends in the first direction. For the sake of convenience in description, in the plan view ofFIG.4B, the shape of the lower electrode layer120″ that is not seen in the cross section taken at the height of the line A-A′ ofFIG.4Ais illustrated by a dotted line. As described above, the lower electrode layer120″ may function as a common electrode of the NMOS transistor and the PMOS transistor. The material layer pattern130′ may be formed along the lower profile over one side111A of the first initial stacked structure110A, one side111B of the second initial stacked structure110B, and the upper surface of the lower electrode layer120″. Furthermore, although not illustrated, the material layer pattern130′ may further extend onto at least a portion of the upper surfaces of the first and second initial stacked structures110A and110B according to the shape of the above-described mask pattern M. After the material layer pattern130′ and the lower electrode layer120″ are formed, the mask pattern M may be removed. Referring toFIGS.5A and5B, a first doped layer132A may be formed by doping an impurity of a first conductivity type onto the material layer pattern130′ on one side111A of the first initial stacked structure110A. For example, the first doped layer132A may serve as a channel of an NMOS transistor, and to this end, a high-concentration N-type impurity may be doped. The N-type impurity may be doped by a tilt implantation method slanting toward one side111A of the first initial stacked structure110A (see arrow {circle around (1)}). The angle of the tilt implantation may be adjusted in such a manner that the N-type impurity is doped onto the entire material layer pattern130′ on one side111A of the first initial stacked structure110A. In this case, since the N-type impurity is doped to the lowermost portion of the material layer pattern130′, the lower end of the first doped layer132A may contact the lower electrode layer120″ to be electrically connected to the lower electrode layer120″. Referring toFIGS.6A and6B, a second doped layer132B may be formed by doping an impurity of a second conductivity type onto the material layer pattern130′ on one side111B of the second initial stacked structure110B. For example, the second doped layer132B may serve as a channel of a PMOS transistor, and for this purpose, a high-concentration P-type impurity may be doped. The P-type impurity may be doped by a tilt implantation method slanting toward one side111B of the second initial stacked structure110B (refer to the arrow {circle around (2)}). The angle of the tilt implantation may be adjusted in such a manner that the P-type impurity is doped onto the entire material layer pattern130′ on one side111B of the second initial stacked structure110B. In this case, since the P-type impurity is doped to the lowermost portion of the material layer pattern130′, the lower end of the second doped layer132B may contact the lower electrode layer120″ to be electrically connected to the lower electrode layer120″. The embodiment of the present invention disclosure illustrates a case where the portion between the lower end of the first doped layer132A and the lower end of the second doped layer132B (see130′ inFIG.6A) is not doped with any impurity and thus an undoped semiconductor material is maintained. However, the present invention disclosure is not limited thereto, and the lower end of the first doped layer132A and the lower end of the second doped layer132B may contact each other (not shown), or a mixed region (not show) of an N-type impurity and a P-type impurity may exist between the lower end of the first doped layer132A and the lower end of the second doped layer132B. Meanwhile, the order of the process of forming the first doped layer132A and the process of forming the second doped layer132B may be reversed. In other words, the second doped layer132B may be formed first, and then the first doped layer132A may be formed later. The conductivity types of the impurities doped onto the first doped layer132A and the second doped layer132B may also be reversed. In other words, the first doped layer132A may be a P-type doped layer, and the second doped layer132B may be an N-type doped layer. Referring toFIGS.7A and7B, after forming a dielectric material having a thickness sufficient to cover the process results ofFIGS.6A and6Bover the substrate100, a first initial inter-layer dielectric material140may be formed by performing a planarization process, such as Chemical Mechanical Polishing (CMP) until the upper surfaces of the first and second initial stacked structures110A and110B are exposed. The first initial inter-layer dielectric material140may include a dielectric material, e.g., SiO2, having an etch rate which is different from those of the first and second sacrificial layers114A and114B, the first and second lower dielectric layers112A and112B, and the first and second upper dielectric layers116A and116B. In this process, a portion of the first and second doped layers132A and132B protruding above the first and second initial stacked structures110A and110B may be removed. When the first and second doped layers132A and132B further extend onto the upper surfaces of the first and second initial stacked structures110A and110B, a portion of the first and second doped layers132A and132B over the upper surfaces of the first and second initial stacked structures110A and110B may be removed in this process. Subsequently, a first inter-layer dielectric layer140′ may be formed by removing a portion of the first initial inter-layer dielectric material140through an etch-back process or the like. In the vertical direction, the upper surface of the first inter-layer dielectric layer140′ may be positioned below the upper surfaces of the first and second initial stacked structures110A and110B and above the upper surfaces of the first and second sacrificial layers114A and114B. As a result, an upper portion of the first doped layer132A and an upper portion of the second doped layer132B may be exposed and not covered by the first inter-layer dielectric layer140′. The process of forming the first inter-layer dielectric layer140′ may be performed to decrease the contact resistance by increasing the contact area between the first and second upper electrode layers and the first and second channel layers, which will be described later, and/or to properly control the height of the lower surfaces of first and second additionally doped layers when first and second additionally doped layers are formed. This process may be omitted. Referring toFIGS.8A and8B, the first additionally doped layer134A may be formed by additionally doping an impurity whose conductivity type is the same as that of the impurity of the first doped layer132A, for example, an N-type impurity, onto the upper surface of the first doped layer132A which is exposed by the process ofFIGS.7A and7B. As the first additionally doped layer134A is formed, the first doped layer132A which is positioned below the first additionally doped layer134A and is not additionally doped with an impurity may be denoted by a reference numeral132A′. The concentration of the impurity of the first additionally doped layer134A may be higher than the concentration of the impurity of the first doped layer132A′. Since a heat treatment for activation after impurity doping is an essential process, the lower surface of the first additionally doped layer134A may be lowered to a predetermined extent from the upper surface of the first inter-layer dielectric layer140′. Even in this case, too, the lower surface of the first additionally doped layer134A may be controlled to be positioned at a height equal to the upper surface of the first sacrificial layer114A or higher than the upper surface of the first sacrificial layer114A. Doping of the impurity for forming the first additionally doped layer134A may be performed through a tilt implantation method slanting toward one side111A of the first initial stacked structure110A (see arrow {circle around (3)}). The angle of the tilt implantation may be smaller than the angle of the tilt implantation ofFIGS.5A and5Bbased on a horizontal plane, for example, the surface of the substrate100. The first additionally doped layer134A and the first doped layer132A′ may be referred to as a first channel layer136A hereinafter. The first channel layer136A may correspond to a channel of an NMOS transistor. The first additionally doped layer134A may function to reduce the contact resistance with the first upper electrode layer, which will be described later. In an embodiment, the first additionally doped layer134A may be omitted. When the process of forming the first additionally doped layer134A is omitted, the first doped layer132A ofFIGS.7A and7Bmay function as a channel of the NMOS transistor. Referring toFIGS.9A and9B, a second additionally doped layer134B may be formed by additionally doping an impurity whose conductivity type is the same as that of the impurity of the second doped layer132B, for example, a P-type impurity, onto the upper portion of the second doped layer132B which is exposed by the process ofFIGS.7A and7B. As the second additionally doped layer134B is formed, the second doped layer132B which is positioned below the second additionally doped layer134B and which is not additionally doped with an impurity may be denoted by a reference numeral132B′. The concentration of the impurity of the second additionally doped layer134B may be higher than the concentration of the impurity of the second doped layer132B′. Since a heat treatment for activation after impurity doping is an essential process, the lower surface of the second additionally doped layer134B may be lowered to a predetermined extent from the upper surface of the first inter-layer dielectric layer140′. Even in this case, too, the lower surface of the second additionally doped layer134B may be controlled to be positioned at a height of equal to or higher than the upper surface of the second sacrificial layer114B. The doping of an impurity for forming the second additionally doped layer134B may be performed through a tilt implantation method slanting toward one side111B of the second initial stacked structure110B (refer to arrow {circle around (4)}). The angle of the tilt implantation may be smaller than the angle of the tilt implantation ofFIGS.6A and6Bbased on the horizontal plane, for example, the surface of the substrate100. The second additionally doped layer134B and the second doped layer132B′ will be referred to as a second channel layer136B, hereinafter. The second channel layer136B may correspond to a channel of a PMOS transistor. The second additionally doped layer134B may function to reduce the contact resistance with the second upper electrode layer, which will be described later. In an embodiment, the second additionally doped layer134B may be omitted. When the process of forming the second additionally doped layer134B is omitted, the second doped layer132B ofFIGS.7A and7Bmay function as a channel of the PMOS transistor. Meanwhile, the order of the processes of forming the first and second additionally doped layers134A and134B may be reversed. For example, the second additionally doped layer134B may be formed first and then the first additionally doped layer134A may be formed later. Referring toFIGS.10A and10B, first and second upper electrode layers150A and150B may be formed over the process results ofFIGS.9A and9B. The first and second upper electrode layers150A and150B may be formed to respectively contact the first and second channel layers136A and136B. The first and second upper electrode layers150A and150B may be electrically connected to the first and second channel layers136A and136B. When the lower electrode layer120″ functions as a common source electrode of an NMOS transistor and a PMOS transistor, the first upper electrode layer150A and the second upper electrode layer150B may serve as a drain electrode of an NMOS transistor and a drain electrode of a PMOS transistor, respectively. For the sake of convenience in description, in the plan view ofFIG.10B, the shapes of the first and second upper electrode layers150A and150B, which are not seen at the height of the line A-A′ofFIG.10A, are shown by dotted lines. From the perspective of a plan view, the first and second upper electrode layers150A and150B may have a rectangular shape respectively overlapping with the first and second channel layers136A and136B. For example, each of the first and second upper electrode layers150A and150B may have a bar shape whose side length in the first direction is longer than the side length in the second direction. Furthermore, from the perspective of a plan view, each of the first and second upper electrode layers150A and150B may have a width which is equal to or greater than the widths of the first and second channel layers136A and136B in the second direction. From the perspective of a cross section, the first upper electrode layer150A may extend from the upper surface of the first channel layer136A to a portion of the upper surface of the first initial stacked structure110A which is disposed adjacent thereto and extend to the side of the upper portion of the first channel layer136A protruding from the first inter-layer dielectric layer140′. Also, from the perspective of a cross section, the second upper electrode layer150B may extend from the upper surface of the second channel layer136B to a portion of the upper surface of the second initial stacked structure110B which is positioned adjacent thereto and extend to the side of the upper portion of the second channel layer136B protruding from the first inter-layer dielectric layer140′. As a result, since the first upper electrode layer150A covers the upper surface and a portion of the side of the first channel layer136A, the contact area between the first upper electrode layer150A and the first channel layer136A may be increased, which decreases contact resistance. Also, since the second upper electrode layer150B covers the upper surface and a portion of the side of the second channel layer136B, the contact area between the second upper electrode layer150B and the second channel layer136B may be increased, which decreases the contact resistance. Furthermore, since the first upper electrode layer150A contacts the first additionally doped layer134A having a higher impurity concentration than the first doped layer132A′ of the first channel layer136A and the second upper electrode layer150B contacts the second additionally doped layer134B having a higher impurity concentration than the second doped layer132B′ of the second channel layer136B, the contact resistance between the first upper electrode layer150A and the first channel layer136A and the contact resistance between the second upper electrode layer150B and the second channel layer136B may be further reduced. These first and second upper electrode layers150A and150B may be formed by depositing and patterning a conductive material over the process results ofFIGS.9A and9B, and they may include diverse conductive materials, for example, metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo) and the like, compounds of these metals, and/or alloys of these metals. Referring toFIGS.11A and11B, a second inter-layer dielectric layer160covering the structure that results from the process ofFIGS.10A and10Bmay be formed. The second inter-layer dielectric layer160may include a dielectric material, e.g., SiO2, having a different etch rate from those of the first and second sacrificial layers114A and114B, the first and second lower dielectric layers112A and112B, and the first and second upper dielectric layers116A and116B. Subsequently, by selectively etching the second inter-layer dielectric layer160and the first inter-layer dielectric layer140′, a first contact hole CA may be formed exposing a first side111A of the first initial stacked structure110A and at least a portion of a second side111A′ which is opposite to the first side111A, in particular, a second side of the first sacrificial layer114A. From the perspective of the vertical direction, the first contact hole CA may be formed to have a depth that the lower surface of the first contact hole CA is positioned at a height equal to or lower than the lower surface of the first sacrificial layer114A. For example, the first contact hole CA may be formed to a depth exposing the substrate100as illustrated in the drawing. Also, from the perspective of a plan view, the first contact hole CA is illustrated to have a bar shape in which the length in the first direction is longer than the length in the second direction and the length in the first direction is slightly shorter than the side length of the first initial stacked structure110A in the first direction. However, the present invention disclosure is not limited thereto, and the shape and/or size of the first contact hole CA on a plane may be diversely modified as long as the first contact hole CA exposes the first sacrificial layer114A in the second side111A′ of the first initial stacked structure110A to remove the first sacrificial layer114A. Subsequently, the first sacrificial layer114A exposed by the first contact hole CA may be removed. The space formed by the removal of the first sacrificial layer114A may be referred to as a first groove portion GA, hereinafter. The first sacrificial layer114A may be removed by an isotropic etching process. Since the first inter-layer dielectric layer140′, the second inter-layer dielectric layer160, the first lower dielectric layer112A, and the first upper dielectric layer116A may be formed of a material having a different etch rate from that of the first sacrificial layer114A, these layers140′,160,112A, and116A may be maintained when the first sacrificial layer114A is removed. Subsequently, a first gate dielectric layer172A may be formed along the inner walls of the first contact hole CA and the first groove portion GA. The first gate dielectric layer172A may be conformally formed to have a thin thickness that does not completely fill the first contact hole CA and the first groove portion GA. Subsequently, a first gate electrode layer174A may be formed along the surface of the first gate dielectric layer172A in the first contact hole CA and the first groove portion GA in which the first gate dielectric layer172A is formed. In an embodiment, the first gate electrode layer174A may be conformally formed to have a thickness that completely fills the first groove portion GA and does not completely fill the first contact hole CA. However, the present invention disclosure is not limited thereto. In another embodiment, the first gate electrode layer174A may be formed to have a thickness that completely fills the first contact hole CA and the first groove portion GA. In yet another embodiment, the first gate electrode layer174A may be formed to have a thickness that fills a portion of the first contact hole CA and a portion of the first groove portion GA. The first gate electrode layer174A may function as a gate electrode of an NMOS transistor, and thus it may include a metal-containing material having an effective work function appropriate for an NMOS transistor. The metal-containing material may include a metal, a compound of the metal, or an alloy of the metal. When the first channel layer136A is doped with a high-concentration N-type impurity, the first gate electrode layer174A may include a metal-containing material having a relatively large work function, such as TaN (Tantalum Nitride) or TiN (Titanium Nitride), so that a portion of the first channel layer136A facing the first gate electrode layer174A may become a depletion region to reduce the off current of the NMOS transistor. Subsequently, a first metal-containing layer176A may be formed to fill the remaining space of the first contact hole CA in which the first gate electrode layer174A is formed. The first metal-containing layer176A may be a metal-containing material having a lower resistance than the first gate electrode layer174A, for example, a metal such as tungsten (W), molybdenum (Mo), ruthenium (Ru), a compound of the metal, or an alloy of the metal. The first metal-containing layer176A may have a lower resistance than the first gate electrode layer174A, and thus may serve to facilitate the transfer of current/voltage to the first gate electrode layer174A. In another embodiment in which the first gate electrode layer174A completely fills the first contact hole CA and the first groove portion GA, the first metal-containing layer176A may be omitted. In yet another embodiment in which the first gate electrode layer174A does not completely fill the first contact hole CA and the first groove portion GA, the first metal-containing layer176A may be formed to completely fill the remaining spaces of the first contact hole CA and the first groove portion GA in which the first gate dielectric layer172A and the first gate electrode layer174A are formed. Among the first gate dielectric layer172A, the first gate electrode layer174A, and/or the first metal-containing layer176A, a portion buried in the first groove portion GA may be referred to as a first horizontal gate structure GPA, and a portion filling the first contact hole CA may be referred to as a first vertical gate structure CPA. The first horizontal gate structure GPA may include the first gate electrode layer174A, and the first gate dielectric layer172A which surrounds the upper surface of the first gate electrode layer174A, the lower surface of the first gate electrode layer174A, and a side of the first gate electrode layer174A facing the first side111A. As a result, the first gate dielectric layer172A may be interposed between the first gate electrode layer174A and the first channel layer136A. The first vertical gate structure CPA may include the first metal-containing layer176A having a columnar shape, the first gate electrode layer174A surrounding the side and lower surface of the first metal-containing layer176A while extending from the first horizontal gate structure GPA, and the first gate dielectric layer172A surrounding the side and lower surface of the first gate electrode layer174A of the first vertical gate structure CPA while extending from the first horizontal gate structure GPA. Since the first horizontal gate structure GPA fills the first groove portion GA, it may have substantially the same plane and cross-sectional shape as those of the first sacrificial layer114A, which is described above. Since the first vertical gate structure CPA is buried in the first contact hole CA, it may have substantially the same plane and cross-sectional shape as those of the first contact hole CA, which is described above. Also, a stacked structure of the first lower dielectric layer112A, the first horizontal gate structure GPA, and the first upper dielectric layer116A formed by replacing the first sacrificial layer114A with the first horizontal gate structure GPA may be referred to as a first stacked structure110A′, hereinafter. As a result, an NMOS transistor including the first horizontal gate structure GPA, the first channel layer136A, the lower electrode layer120″, and the first upper electrode layer150A may be fabricated. Referring toFIGS.12A and12B, the second inter-layer dielectric layer160and the first inter-layer dielectric layer140′ may be selectively etched to form a second contact hole CB that exposes the first side111B of the second initial stacked structure110B and at least a portion of the second side111B′ which is opposite to the first side111B, in particular, the second side of the second sacrificial layer114B. In the vertical direction, the second contact hole CB may be formed to have a depth that makes the lower surface of the second contact hole CB positioned at a height equal to or lower than the lower surface of the second sacrificial layer114B. For example, the second contact hole CB may be formed to have a depth that exposes the substrate100as illustrated in the drawing. Also, from the perspective of a plan view, the second contact hole CB is illustrated to have a bar shape in which the length in the first direction is longer than the length in the second direction and the length in the first direction is slightly shorter than the side length of the second initial stacked structure110B in the first direction. However, the present invention disclosure is not limited thereto, and the shape or size of the second contact hole CB on a plane may be diversely modified as long as the removal of the second sacrificial layer114B is possible by exposing the second sacrificial layer114B on the second side111B′ of the second initial stacked structure110B. Subsequently, the second sacrificial layer114B exposed by the formation of the second contact hole CB may be removed. The space formed by the removal of the second sacrificial layer114B may, hereinafter, be referred to as a second groove portion GB. Subsequently, a second gate dielectric layer172B may be formed along the inner walls of the second contact hole CB and the second groove portion GB. The second gate dielectric layer172B may be conformally formed to have a thin thickness that does not completely fill the second contact hole CB and the second groove portion GB. Subsequently, a second gate electrode layer174B may be formed along the surface of the second gate dielectric layer172B in the second contact hole CB and the second groove portion GB where the second gate dielectric layer172B is formed. For example, the second gate electrode layer174B may be conformally formed to have a thickness that does not completely fill the second contact hole CB while completely filling the second groove portion GB. However, the present invention disclosure is not limited thereto. In another embodiment of the present invention, the second gate electrode layer174B may be formed to have a thickness that completely fills the second groove portion GB and the second contact hole CB. Alternatively, yet in another embodiment, the second gate electrode layer174B may be formed to have a thickness that fills a portion of the second contact hole CB and a portion of the second groove portion GB. The second gate electrode layer174B may function as a gate electrode of a PMOS transistor. The second gate electrode layer174B may include a metal-containing material having an effective work function appropriate for a PMOS transistor. For example, when the second channel layer136B is doped with a high-concentration P-type impurity, the second gate electrode layer174B may include a metal-containing material, e.g., TiAl or TiC, having a relatively small work function so that a portion of the second channel layer136B facing the second gate electrode layer174B may be depleted and, thus, the off current of the PMOS transistor may be reduced. Subsequently, a second metal-containing layer176B may be formed to fill the remaining space of the second contact hole CB in which the second gate electrode layer174B is formed. The second metal-containing layer176B may include a metal-containing material having a lower resistance than the second gate electrode layer174B, for example, a metal such as tungsten (W), molybdenum (Mo) and ruthenium (Ru), a compound of the metal, or an alloy of the metal. As the second metal-containing layer176B has a lower resistance than that of the second gate electrode layer174B, it may serve to facilitate the transfer of current/voltage to the second gate electrode layer174B. In another embodiment, when the second gate electrode layer174B completely fills the second contact hole CB and the second groove portion GB, the second metal-containing layer176B may be omitted. Alternatively, yet in another embodiment, when the second gate electrode layer174B does not completely fill the second contact hole CB and the second groove portion GB, the second metal-containing layer176B may be formed to completely fill the remaining space of the second contact hole CB and the second groove portion GB in which the second gate dielectric layer172B and the second gate electrode layer174B are formed. Among the second gate dielectric layer172B, the second gate electrode layer174B, and/or the second metal-containing layer176B, a portion filling the second groove portion GB may be referred to as a second horizontal gate structure GPB, and a portion filling the second contact hole CB will be referred to as a second vertical gate structure CPB. The second horizontal gate structure GPB may include the second gate electrode layer174B, and the second gate dielectric layer172B which surrounds the upper surface of the second gate electrode layer174B, the lower surface of the second gate electrode layer174B, and the side of the second gate electrode layer174B facing the first side111B. Accordingly, the second gate dielectric layer172B may be interposed between the second gate electrode layer174B and the second channel layer136B. The second vertical gate structure CPB may include the column-shaped second metal-containing layer176B, the second gate electrode layer174B which extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second metal-containing layer176B, and the second gate dielectric layer172B which extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second gate electrode layer174B of the second vertical gate structure CPB. Since the second horizontal gate structure GPB fills the second groove portion GB, it may have substantially the same plane and cross-sectional shape as those of the above-described second sacrificial layer114B. Since the second vertical gate structure CPB is buried in the second contact hole CB, it may have substantially the same plane and cross-sectional shape as those of the above-described second contact hole CB. Also, a stacked structure of the second lower dielectric layer112B, the second horizontal gate structure GPB, and the second upper dielectric layer116B which is formed by replacing the second sacrificial layer114B with the second horizontal gate structure GPB may be referred to as a second stacked structure110B′, hereinafter. As a result, a PMOS transistor including the second horizontal gate structure GPB, the second channel layer136B, the lower electrode layer120″, and the second upper electrode layer150B may be formed. Furthermore, a CMOS transistor including an NMOS transistor and a PMOS transistor that share the lower electrode layer120″ may be formed. After formation, the CMOS transistor may be electrically connected to the lower electrode layer120″, the first and second upper electrode layers150A and150B, and the first and second horizontal gate structures GPA and GPB. Diverse wiring structures may be formed to control them. This will be described below with reference toFIGS.13A to14B. Referring toFIGS.13A and13B, a third inter-layer dielectric layer180may be formed over the structure resulting from the process ofFIGS.12A and12B. The third inter-layer dielectric layer180may include diverse dielectric materials, such as SiO2. Subsequently, a lower electrode contact182may be formed to be coupled to the lower electrode layer120″ and may pass through the third inter-layer dielectric layer180, the second inter-layer dielectric layer160, and the first inter-layer dielectric layer140′. In the first direction, the lower electrode contact182may not be positioned between the first stacked structure110A′ and the second stacked structure110B′ but positioned outside the space between the first stacked structure110A′ and the second stacked structure110B′. This is because when the space between the first stacked structure110A′ and the second stacked structure110B′ is narrow, it is difficult to form the lower electrode contact182. As an example, the two lower electrode contacts182may be positioned on first sides111A and111B and second sides111A′ and111B′ of the first and second initial stacked structures110A and110B in the first direction. However, the present invention disclosure is not limited thereto, and the number of and the arrangement of the lower electrode contacts182may be diversely modified based on the assumption that they may overlap with and be coupled to the lower electrode layer120″. For the sake of convenience in description, in the cross-sectional view ofFIG.13A, the shape of the lower electrode contact182, which is not seen on the line B-B′ ofFIG.13B, is shown by a dotted line. Also, in the cross-sectional view ofFIG.13B, the lower electrode contacts182are shown as dots. The lower electrode contact182may be formed by selectively etching the third inter-layer dielectric layer180, the second inter-layer dielectric layer160, and the first inter-layer dielectric layer140′ so as to form a contact hole that exposes the lower electrode layer120″ and then filling the contact hole with a conductive material, including but not limited to metal. Subsequently, a lower electrode line184extending in one direction may be formed over the third inter-layer dielectric layer180while overlapping with and coupled to the lower electrode contact182. When the two lower electrode contacts182are arranged in the first direction as shown in this embodiment of the present invention disclosure, the lower electrode line184may extend in the first direction so as to overlap with and couple to both of the two lower electrode contacts182. The lower electrode line184may be electrically connected to the lower electrode layer120″ through the lower electrode contact182, and thus it may function as a common source line that drives the lower electrode layer120″. For the sake of convenience in description, in the plan view ofFIG.13B, the lower electrode line184, which is not seen at the height of the line A-A′ ofFIG.13A, is illustrated by a solid line. Referring toFIGS.14A and14B, a fourth inter-layer dielectric layer190may be formed over the structure resulting from the process ofFIGS.13A and13B. The fourth inter-layer dielectric layer190may have a thickness which is sufficiently thick to cover the lower electrode line184. As shown inFIG.14A, the fourth inter-layer dielectric layer190may have a thickness which is greater than the thickness of the lower electrode line184. The fourth inter-layer dielectric layer190may be made of any suitable dielectric material, including, for example, SiO2. Subsequently, first and second upper electrode contacts192A and192B may be formed through the fourth inter-layer dielectric layer190, the third inter-layer dielectric layer180, and the second inter-layer dielectric layer160. The first and second upper electrode layers150A and150B may be respectively coupled to the first and second upper electrode contacts192A and192B. According to an embodiment of the present invention disclosure, a plurality of first upper electrode contacts192A may be arranged in a line along the first direction while being coupled to the first upper electrode layer150A, and a plurality of second upper electrode contacts192B may be arranged in a line along the first direction while being coupled to the second upper electrode layer150B. However, the present invention disclosure is not limited thereto, and the number and arrangement of the first and second upper electrode contacts192A and192B may be diversely modified as long as they overlap with and are coupled to the first and second upper electrode layers150A and150B, respectively. The first and second upper electrode contacts192A and192B may be formed by a method of selectively etching the fourth inter-layer dielectric layer190, the third inter-layer dielectric layer180, and the second inter-layer dielectric layer160so as to form a contact hole exposing the first and second upper electrode layers150A and150B, and then filling the contact hole with a suitable conductive material, including, for example, a metal. Subsequently, first and second upper electrode lines194A and194B extending in one direction while respectively overlapping with and coupled to the first and second upper electrode contacts192A and192B may be formed over the fourth inter-layer dielectric layer190. When the first upper electrode contacts192A are arranged in a line along the first direction in this embodiment of the present invention disclosure, the first upper electrode line194A may extend in the first direction. Likewise, when the second upper electrode contacts192B are arranged in a line along the first direction, the second upper electrode line194B may extend in the first direction. As the first upper electrode line194A is electrically connected to the first upper electrode layer150A through the first upper electrode contact192A, the first upper electrode line194A may function as a first bit line that drives the first upper electrode layer150A. The second upper electrode line194B may function as a second bit line that drives the second upper electrode layer150B, as the second upper electrode line194B is electrically connected to the second upper electrode layer150B through the second upper electrode contact192B. Also, a first gate contact196A and a second gate contact196B may be formed penetrating the fourth inter-layer dielectric layer190and the third inter-layer dielectric layer180to be coupled to the first vertical gate structure CPA and the second vertical gate structure CPB, respectively. In the embodiment of the present invention disclosure, a plurality of first gate contacts196A may be arranged in a line along the first direction while being coupled to the first vertical gate structure CPA, and a plurality of second gate contacts196B may be arranged in a line along the first direction while being coupled to the second vertical gate structure CPB. The number and arrangement of the first and second gate contacts196A and196B may be diversely modified as long as they overlap with and are coupled to the first and second vertical gate structures CPA and CPB. The first and second gate contacts196A and196B may be formed by selectively etching the fourth inter-layer dielectric layer190and the third inter-layer dielectric layer180so as to form a contact hole that exposes the first and second vertical gate structures CPA and CPB and then filling the contact hole with a suitable conductive material, including, for example, a metal. The process of forming the first and second gate contacts196A and196B and the process of forming the first and second upper electrode contacts192A and192B may be performed simultaneously. Subsequently, first and second gate lines198A and198B extending in one direction while overlapping with and coupled to the first and second gate contacts196A and196B, respectively, may be formed over the fourth inter-layer dielectric layer190. When the first gate contacts196A are arranged in a line along the first direction according to an embodiment of the present invention disclosure, the first gate line198A may extend in the first direction. Likewise, when the second gate contacts196B are arranged in a line along the first direction, the second gate line198B may extend in the first direction. As the first gate line198A is electrically connected to the first horizontal gate structure GPA through the first gate contact196A and the first vertical gate structure CPA, it may function as a first word line that drives the first horizontal gate structure GPA. As the second gate line198B is electrically connected to the second horizontal gate structure GPB through the second gate contact196B and the second vertical gate structure CPB, it may function as a second word line that drives the second horizontal gate structure GPB. The process of forming the first and second gate lines198A and198B and the process of forming the first and second upper electrode lines194A and194B may be performed simultaneously. For the sake of convenience in description, in the plan view ofFIG.14B, the first and second upper electrode contacts192A and192B which are not visible at the height of line A-A′ ofFIG.14A, the first and second upper electrode lines194A and194B, the first and second gate contacts196A and196B, and the first and second gate lines198A and198B are shown by dotted and solid lines. Illustrated in this embodiment of the present invention disclosure is a case where the lower electrode line184is positioned below the first and second upper electrode lines194A and194B and the first and second gate lines198A and198B in the vertical direction. This is because when the lower electrode line184and the first and second upper electrode lines194A and194B are positioned at the same level, an electrical shortage may occur due to a narrow gap between them. Also, in this embodiment of the present invention disclosure, a case where the first and second upper electrode lines194A and194B and the first and second gate lines198A and198B are positioned at the same level in the vertical direction is illustrated. This is because a sufficient gap may be secured between them. However, the present invention disclosure is not limited thereto. The positions of the lower electrode line184, the first and second upper electrode lines194A and194B, and the first and second gate lines198A and198B in the vertical direction may be diversely modified. By the fabrication method described above, the semiconductor device of this embodiment may be fabricated. Referring back toFIGS.14A and14B, the semiconductor device according to various embodiments of the present invention disclosure may include: a substrate100, a first stacked structure110A′ which is disposed over the substrate100and includes a first lower dielectric layer112A, a first horizontal gate structure GPA, and a first upper dielectric layer116A that are stacked in the vertical direction, a second stacked structure110B′ which is disposed over the substrate100to have a first side111B facing a first side111A of the first stacked structure110A′ and includes a second lower dielectric layer112B, a second horizontal gate structure GPB, and a second upper dielectric layer116B that are stacked in the vertical direction, a first channel layer136A which is formed to face at least the first horizontal gate structure GPA on the first side111A of the first stacked structure110A′, a second channel layer136B which is formed to face at least the second horizontal gate structure GPB on the first side111B of the second stacked structure110B′, a lower electrode layer120″ which is disposed between the first stacked structure110A′ and the second stacked structure110B′ and commonly coupled to the lower ends of the first and second channel layers136A and136B, a first upper electrode layer150A which is coupled to the upper end of the first channel layer136A, and a second upper electrode layer150B which is coupled to the upper end of the second channel layer136B. Also, over the substrate100, a first vertical gate structure CPA extending in the vertical direction while being coupled to the first horizontal gate structure GPA in the second side111A′ positioned in opposite to the first side111A of the first stacked structure110A′, and a second vertical gate structure CPB extending in the vertical direction while being coupled to the second horizontal gate structure GPB on the second side111B′ disposed in opposite to the first side111B of the second stacked structure110B′ may be formed. The lower electrode layer120″, the first and second vertical gate structures CPA and CPB, and the first and second upper electrode layers150A and150B may be driven by diverse shapes of wiring structures, for example, the lower electrode contact182, the lower electrode line184, the first and second gate contacts196A and196B, the first and second gate lines198A and198B, the first and second upper electrode contacts192A and192B, and the first and second upper electrode lines194A and194B, which are illustrated in the drawing. Since the details of the constituent elements of the semiconductor device according to an embodiment of the present invention disclosure have already been described in the process of describing the fabrication method, they will be omitted. According to the above-described semiconductor device and the method of fabricating the same, the following effects may be obtained. First, the first and second channel layers136A and136B functioning as channels of an NMOS transistor and a PMOS transistor extend in the vertical direction and, thus, the distance between the first channel layer136A and the second channel layer136B in the horizontal direction may be reduced. As a result, the planar area of the semiconductor device and the parasitic capacitance originating from the first and second channel layers136A and136B may both be reduced also. Furthermore, by forming the first and second channel layers136A and136B by doping an impurity on a thin-film material layer130, the thickness of the first and second channel layers136A and136B may be reduced, improving the controllability of a transistor. However, in this case, driving current may be decreased, but this may be compensated by increasing the width and/or length of the first and second channel layers136A and136B in the first direction. Also, differently from a typical planar-type transistor in which a gate electrode faces a source/drain contact and thereby produces much parasitic capacitance, there may be a few contacts or no contacts facing the first and second horizontal gate structures GPA and GPB and the first and second vertical gate structures CPA and CPB. For example, in an embodiment of the present invention disclosure, the lower electrode contact182and the first and second upper electrode contacts192A and192B may not face the first and second horizontal gate structures GPA and GPB and first and second vertical gate structures CPA and CPB, or may face a portion of the first and second horizontal gate structures GPA and GPB and first and second vertical gate structures CPA and CPB. As a result, the parasitic capacitance may be further reduced compared to a planar transistor. FIGS.15and16are cross-sectional views illustrating a semiconductor device and a method for fabricating the semiconductor device in accordance with another embodiment of the present invention disclosure. In particular,FIG.15shows an intermediate process step that may be performed between the process ofFIGS.5A and5Band the process ofFIGS.7A and7B, andFIG.16shows an intermediate process step that may be performed between the process ofFIGS.6A and6Band the process ofFIGS.7A and7B. Referring toFIG.15, after the formation of the first doped layer132A, an impurity of a conductivity type, e.g., a P-type impurity, that is different from that of the impurity of the first doped layer132A may be counter-doped on a region L1 of the first doped layer132A facing the first sacrificial layer114A. As an example, the region L1 may be a region of the first doped layer132A that is substantially at the same or similar level with the first sacrificial layer114A. The concentration of the counter-doped P-type impurity may be lower than the concentration of the N-type impurity in the first doped layer132A. In this case, in the region L1, the concentration of the N-type impurity may decrease while the N type is maintained so that the off current of the NMOS transistor may be reduced. When the first sacrificial layer114A is replaced with a gate electrode layer in the subsequent process, a metal-containing material having a relatively small work function, such as TiAl (Titanium Aluminide) or TiC (Titanium carbide), may be used as a gate electrode layer. This is because, unlike the above-described embodiment of the present invention disclosure, since the N-type impurity of the region L1 of the first doped layer132A has a relatively low concentration, a separate process of forming a depletion region is not required. The doping of an impurity for forming the region L1 may be performed using a tilt implantation method slanting toward a first side111A of the first initial stacked structure110A (refer to arrow {circle around (5)}). The angle of the tilt implantation may be smaller than the angle of the tilt implantation ofFIGS.5A and5Band may be greater than the angle of the tilt implantation ofFIGS.8A and8Bbased on a horizontal plane, for example, the surface of the substrate100. The angle of the tilt implantation as this term is used here is the angle formed between the direction of the implantation and the horizontal plane. Referring toFIG.16, after the formation of the second doped layer132B, an impurity of a conductivity type, e.g., an N-type impurity, that is different from that of the impurity of the second doped layer132B may be counter-doped on a region L2 of the second doped layer132B facing the second sacrificial layer114B. As an example, the region L2 may be a region of the second doped layer132B which is substantially at the same or similar level with the second sacrificial layer114B. The concentration of the counter-doped N-type impurity may be lower than the concentration of the P-type impurity in the second doped layer132B. In this case, the concentration of the P-type impurity may decrease in the region L2 while the P type is maintained, thereby reducing the off-state current of a PMOS transistor. When the second sacrificial layer114B is replaced with a gate electrode layer in a subsequent process, a metal-containing material having a relatively large work function, such as TaN or TiN, may be used as a gate electrode layer. Unlike the above-described embodiment of the present invention disclosure, since the concentration of the P-type impurity of the region L2 of the second doped layer132B is relatively low, a separate process for forming a depletion region is not required. The doping of an impurity for forming the region L2 may be performed using a tilt implantation method slanting toward a first side111B of the second initial stacked structure110B (refer to arrow {circle around (6)}). The angle of the tilt implantation may be smaller than the angle of the tilt implantation ofFIGS.6A and6Band may be greater than the angle of the tilt implantation ofFIGS.9A and9Bbased on a horizontal plane, for example, the surface of the substrate100. Since the subsequent processes are substantially the same as those described in the above-described embodiment of the present invention disclosure, detailed descriptions on them will be omitted. Meanwhile, although the above embodiments are directed to a semiconductor device including a CMOS transistor and a method for fabricating the same, the present invention disclosure is not limited thereto. A semiconductor device including an NMOS transistor or a semiconductor device including a PMOS transistor may be fabricated according to an embodiment of the present invention disclosure. This will be described below with reference toFIGS.17A and17B. FIGS.17A and17Bare views illustrating a semiconductor device and a method for fabricating the semiconductor device in accordance with another embodiment of the present invention disclosure.FIG.17Ais a cross-sectional view taken along a line B-B′ ofFIG.17B, andFIG.17Bis a plan view illustrated at the height of a line A-A′. However, certain constituent elements that are not seen at the height of the line A-A′ ofFIG.17Amay be illustrated as dotted lines, solid lines or dots, etc., inFIG.17B, or constituent elements that are not seen at the height of the line B-B′ ofFIG.17Bmay be illustrated as dotted lines inFIG.17A. Description will be made focusing on the differences from the above-described embodiments of the present invention disclosure. Referring toFIGS.17A and17B, first and second stacked structures210A and210B may be formed over the substrate200. The first stacked structure210A may include a first lower dielectric layer212A, a first horizontal gate structure GPA, and a first upper dielectric layer216A that are stacked over the substrate200in the vertical direction. The second stacked structure210B may include a second lower dielectric layer212B, a second horizontal gate structure GPB, and a second upper dielectric layer216B that are stacked over the substrate200in the vertical direction. A first side211B of the second stacked structure210B is facing a first side211A of the first stacked structure210A. The first horizontal gate structure GPA may include a first gate electrode layer274A and a first gate dielectric layer272A surrounding an upper surface and a lower surface of the first gate electrode layer274A and a side facing the first side211A. Also, the second horizontal gate structure GPB may include a second gate dielectric layer274B, and a second gate dielectric layer272B surrounding the upper surface and the lower surface of the second gate electrode layer274B, and a side facing the first side211B. A lower electrode layer220″ may be disposed between the first stacked structure210A and the second stacked structure210B over the substrate200. The lower electrode layer220″ may have an upper surface disposed at a height equal to or lower than the upper surface of the first and second lower dielectric layers212A and212B to be spaced apart from the first and second horizontal gate structures GPA and GPB, in particular, the first and second gate electrode layers274A and274B. A first channel layer236A and a second channel layer236B may be formed over the first side211A of the first stacked structure210A and the first side211B of the second stacked structure210B, respectively. Also, a lower end of the first channel layer236A and a lower end of the second channel layer236B may be commonly coupled to the lower electrode layer220″. Here, both of the first channel layer236A and the second channel layer236B may be doped with an impurity of the same conductivity type. For example, when the first and second channel layers236A and236B are doped with an N-type impurity, the first and second channel layers236A and236B may function as channels of an NMOS transistor. When the first channel layer236A includes a first doped layer232A′ and a first additionally doped layer234A and the second channel layer236B includes a second doped layer232B′ and a second additionally doped layer234B, all of the first doped layer232A′, the first additionally doped layer234A, the second doped layer232B′, and the second additionally doped layer234B may include an N-type impurity. Alternatively, as another example, when the first and second channel layers236A and236B are doped with a P-type impurity, the first and second channel layers236A and236B may function as channels of a PMOS transistor. When the first channel layer236A includes a first doped layer232A′ and a first additionally doped layer234A, and the second channel layer236B includes a second doped layer232B′ and a second additionally doped layer234B, all of the first doped layer232A′, the first additionally doped layer234A, the second doped layer232B′, and the second additionally doped layer234B may include a P-type impurity. In this case, the first and second gate electrode layers274A and274B may be formed of a material having the same work function. An undoped material layer pattern230′ may exist between the lower end of the first channel layer236A and the lower end of the second channel layer236B. First and second upper electrode layers250A and250B may be formed on the first and second channel layers236A and236B to contact and electrically connect to the first and second channel layers236A and236B. When there is a first inter-layer dielectric layer240′ whose upper surface is lower than the upper surfaces of the first channel layer236A and the second channel layer236B between the first channel layer236A and the second channel layer236B, the first upper electrode layer250A may surround the upper surface and a portion of the side of the first channel layer236A which protrudes above the first inter-layer dielectric layer240′, and the second upper electrode layer250B may surround the upper surface and a portion of the side of the second channel layer236B which protrudes above the first inter-layer dielectric layer240′. Also, a first vertical gate structure CPA extending in the vertical direction while being coupled to the first horizontal gate structure GPA on the second side211A′ which is positioned in opposite to the first side211A of the first stacked structure210A may be formed. Also, a second vertical gate structure CPB extending in the vertical direction while being coupled to the second horizontal gate structure GPB on the second side211B′ which is positioned in opposite to the first side211B of the second stacked structure210B may be formed over the substrate200. The first vertical gate structure CPA may include a column-shaped first metal-containing layer276A, a first gate electrode layer274A that extends from the first horizontal gate structure GPA and surrounds the side and lower surface of the first metal-containing layer276A, and a first gate dielectric layer272A that extends from the first horizontal gate structure GPA and surrounds the side and lower surface of the first gate electrode layer274A of the first vertical gate structure CPA. The second vertical gate structure CPB may include a column-shaped second metal-containing layer276B, a second gate electrode layer274B that extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second metal-containing layer276B, and a second gate dielectric layer272B that extends from the second horizontal gate structure GPB and surrounds the side and lower surface of the second gate electrode layer274B of the second vertical gate structure CPB. The lower electrode contact282may be formed to pass through the third inter-layer dielectric layer280, the second inter-layer dielectric layer260, and the first inter-layer dielectric layer240′ to be coupled to the lower electrode layer220″. The lower electrode line284may be formed to extend in the first direction while overlapping with and coupled to the lower electrode contact282over the third inter-layer dielectric layer280. The first and second upper electrode contacts292A and292B may be formed to pass through a fourth inter-layer dielectric layer290, the third inter-layer dielectric layer280, and the second inter-layer dielectric layer260to be coupled to the first and second upper electrode layers250A and250B, respectively, and the first and second upper electrode lines294A and294B may be formed to extend in the first direction while overlapping with and coupled to the first and second upper electrode contacts292A and292B, respectively, over the fourth inter-layer dielectric layer290. In this case, the first upper electrode line294A and the second upper electrode line294B may be coupled to each other by a first coupling pattern295. The first coupling pattern295may extend in the second direction at the same level of the first upper electrode line294A and the second upper electrode line294B and between the first upper electrode line294A and the second upper electrode line294B. The number of the first coupling patterns295may be diversely modified as long as the number is one or more. The first and second gate contacts296A and296B may be formed to pass through the fourth inter-layer dielectric layer290and the third inter-layer dielectric layer280to be coupled to the first and second vertical gate structures CPA and CPB, respectively, and the first and second gate lines298A and298B may be formed to extend in the first direction while overlapping with and coupled to the first and second gate contacts296A and296B over the fourth inter-layer dielectric layer290. In this case, the first gate line298A and the second gate line298B may be coupled to each other by a second coupling pattern299. The second coupling pattern299may extend in the second direction at the same level of the first gate line298A and the second gate line298B and between the first gate line298A and the second gate line298B. The number of the second coupling patterns299may be diversely modified as long as the number is one or more. Furthermore, the second coupling pattern299may be formed at a position that does not overlap with the first coupling pattern295. Even in the case of this embodiment, substantially the same effects as those of the above-described embodiments may be obtained. In other words, it may be possible to reduce the size of a semiconductor device, reduce parasitic capacitance, and improve operation characteristics. The embodiments described above may be applicable to all semiconductor devices including an NMOS transistor, a PMOS transistor, or a CMOS transistor, and a method for fabricating the same. For example, the above-described embodiments may also be applied to diverse semiconductor devices, which include non-volatile memories such as a flash memory, a Resistive Random-Access Memory (RRAM), a Phase-change Random-Access Memory (PRAM), and a Magneto-resistive Random-Access Memory (MRAM), volatile memories such as a Dynamic Random-Access Memory (DRAM) and a Static Random-Access Memory (SRAM), non-memories such as logic circuits, and CIS (CMOS Image Sensor). According to an embodiment of the present invention disclosure, disclosed are a semiconductor device having reduced parasitic capacitance and improved operation characteristics while having a reduced size of the semiconductor device, and a method for fabricating the semiconductor device. While the present invention disclosure has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention disclosure as defined in the following claims. | 72,164 |
11942545 | DETAILED DESCRIPTION A semiconductor device of an embodiment includes: a substrate; a first electrode; a second electrode, the first electrode provided between the substrate and the second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode, the oxide semiconductor layer being in contact with the first electrode, the oxide semiconductor layer containing zinc (Zn) and at least one first element selected from the group consisting of indium (ln), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and a chemical composition of the oxide semiconductor layer being different from a chemical composition of the first electrode and the second electrode; a conductive layer provided between the oxide semiconductor layer and the second electrode, the conductive layer being in contact with the second electrode, the conductive layer containing oxygen (O) and at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti), and a chemical composition of the conductive layer being different from a chemical composition of the first electrode, the second electrode, and the oxide semiconductor layer; a gate electrode; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The following is a description of embodiments, with reference to the accompanying drawings. In the description below, like or similar components are denoted by like reference numerals, and explanation of components described once may not be repeated. In the present specification, the terms “upper” and “lower” may be used for convenience. The terms “upper” and “lower” are terms that indicate a relative positional relationship in the drawings, and do not define the positional relationship with respect to gravity. The qualitative analysis and the quantitative analysis of the chemical compositions of the members constituting a semiconductor device and a semiconductor memory device in the present specification can be conducted by secondary ion mass spectroscopy (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RES), for example. The thicknesses of the members constituting a semiconductor device and a semiconductor memory device, the distances between the members, the crystal grain size, and the like can be measured with a transmission electron microscope (TEM), for example. Further, the carrier concentration in the members constituting a semiconductor device and a semiconductor memory device can be measured with a scanning spreading resistance microscope (SSRM), for example. First Embodiment A semiconductor device of a first embodiment includes: a substrate; a first electrode; a second electrode, the first electrode provided between the substrate and the second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode, the oxide semiconductor layer being in contact with the first electrode, the oxide semiconductor layer containing zinc (Zn) and at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and a chemical composition of the oxide semiconductor layer being different from a chemical composition of the first electrode and the second electrode; a conductive layer provided between the oxide semiconductor layer and the second electrode, the conductive layer being in contact with the second electrode, the conductive layer containing oxygen (O) and at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti), and a chemical composition of the conductive layer being different from a chemical composition of the first electrode, the second electrode, and the oxide semiconductor layer; a gate electrode; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. FIGS.1and2are schematic cross-sectional views of a semiconductor device of a first embodiment.FIG.2is a cross-sectional view taken along the A-A′ line defined inFIG.1. InFIG.1, the vertical direction is referred to as a first direction. InFIG.1, the horizontal direction is referred to as a second direction. The second direction is perpendicular to the first direction. The semiconductor device of the first embodiment is a transistor100. The transistor100is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor100is a so-called surrounding gate transistor (SGT) in which a gate electrode is provided so as to surround an oxide semiconductor layer in which a channel is formed. The transistor100is a so-called vertical transistor. The transistor100includes a silicon substrate10, a lower electrode12, an upper electrode14, a channel layer16, a contact layer18, a gate electrode20, a gate insulating layer22, and an interlayer insulating layer24. The gate insulating layer.22includes a first region22aand a second region22b. The silicon substrate10is an example of the substrate. The lower electrode12is an example of the first electrode. The upper electrode14is an example of the second electrode. The channel layer16is an example of the oxide semiconductor layer. The contact layer18is an example of the conductive layer. The silicon substrate10is a single-crystal silicon substrate, for example. The silicon substrate10is an example of the substrate. The substrate is not necessarily a silicon substrate. The substrate may be a semiconductor substrate other than a silicon substrate, for example. The substrate may be an insulating substrate, for example. The lower electrode12is disposed above the silicon substrate10. The interlayer insulating layer24is disposed between the silicon substrate10and the lower electrode12. The lower electrode12is an example of the first electrode. The lower electrode12functions as a source electrode or a drain electrode of the transistor100. The lower electrode12is a conductor. The lower electrode12contains an oxide semiconductor or a metal, for example. The lower electrode12is an oxide semiconductor containing indium (In) and tin (Sn), for example. The lower electrode12is a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta), for example. The lower electrode12may have a stacked structure formed with a plurality of conductors, for example. The upper electrode14is disposed above the silicon substrate10. The upper electrode14is disposed above the lower electrode12. The lower electrode12is disposed between the silicon substrate10and the upper electrode14. The upper electrode14is an example of the second electrode. The direction from the upper electrode14toward the lower electrode12is the first direction. The upper electrode14functions as a source electrode or a drain electrode of the transistor100. The upper electrode14is a conductor. The upper electrode14contains an oxide semiconductor or a metal, for example. The upper electrode14is an oxide semiconductor containing indium (Tn) and tin (Sn), for example. The upper electrode14is a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta), for example. The upper electrode14may have a stacked structure formed with a plurality of conductors, for example. The channel layer16is disposed above the silicon substrate10. The channel layer16is disposed between the lower electrode12and the upper electrode14. The channel layer16is in contact with the lower electrode12. The channel layer16is an example of the oxide semiconductor layer. A channel that serves as a current path during an on-operation of the transistor100is formed in the channel layer16. The channel layer16is an oxide semiconductor. The channel layer16is an amorphous layer, for example. The channel layer16contains zinc (Zn). The channel layer16contains at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn). The channel layer16contains indium (ln), gallium (Ga), and zinc (Zn), for example. The atomic concentration of the zinc (Zn) in the channel layer16is not lower than 5 atomic % and not higher than 20 atomic %, for example. The channel layer16has a different chemical composition from the chemical composition of the lower electrode12and the chemical composition of the upper electrode14. At least part of the channel layer16is an n-type semiconductor. The channel layer16contains oxygen deficiency. The oxygen deficiency may be called oxygen vacancy. The oxygen deficiency in the channel layer16function as donors. The length of the channel layer16in the first direction is not smaller than 80 nm and not greater than 200 nm, for example. The width of the channel layer16in the second direction is not smaller than 20 nm and not greater than 100 nm, for example. The contact layer18is disposed between the channel layer16and the upper electrode14. The contact layer18is in contact with the upper electrode14. The contact layer18is in contact with the channel layer16, for example. The contact layer18is an example of the conductive layer. The contact layer18has a function to lower the electrical resistance between the channel layer16and the upper electrode14. The contact layer18is an oxide semiconductor, for example. The contact layer18contains oxygen (O). The contact layer18contains at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sri), zinc (Zn), and titanium (Ti). The contact layer18contains an oxide. The contact layer18is an oxide containing indium (In), tin (Sn), and zinc (Zn), for example. The contact layer18has a different chemical composition from the chemical composition of the lower electrode12, the chemical composition of the upper electrode14, and the chemical composition of the channel layer16. The contact layer18is an n-type semiconductor, for example. The contact layer18contains oxygen deficiency. The oxygen deficiency in the contact layer18function as donors. The thickness of the contact layer18in the first direction is not smaller than 5 nm and not greater than 20 m, for example. The density of the oxygen deficiency in the contact layer18is higher than the density of the oxygen deficiency in the channel layer16, for example. The carrier concentration in the contact layer18is higher than the carrier concentration in the channel layer16, for example. The electrical resistivity of the contact layer18is lower than the electrical resistivity of the channel layer16, for example. The atomic concentration of the tin (Sn) contained in the contact layer18is higher than the atomic concentration of the tin (Sn) contained in the channel layer16, for example. The atomic concentration of the indium (In) contained in the contact layer18is higher than the atomic concentration of the indium (In) contained in the channel layer16, for example. The gate electrode20is disposed so as to surround the channel layer16. The gate electrode20is disposed around the channel layer16. The gate electrode20is a metal, a metal compound, or a semiconductor, for example. The gate electrode20contains tungsten (W), for example. The gate length of the gate electrode20is not smaller than 20 nm and not greater than 100 nm, for example. The gate length of the gate electrode20is the length of the gate electrode20in the first direction. The gate insulating layer22is disposed between the channel layer16and the gate electrode20. The gate insulating layer22is disposed so as to surround the channel layer16. The gate insulating layer22is in contact with the lower electrode12, for example. The gate insulating layer22is in contact with the contact layer18, for example. The gate insulating layer22includes a first region22aand a second region22b. The channel layer16is disposed between the first region22aand the second region22b. The gate insulating layer22is an oxide or an oxynitride, for example. The gate insulating layer22contains a silicon oxide or an aluminum oxide, for example. The thickness of the gate insulating layer22is not smaller than 2 nm and not greater than 10 nm, for example. Note that an oxide layer (not shown) formed with a different material from the gate insulating layer22can be provided between the channel layer16and the gate insulating layer22. The interlayer insulating layer24is disposed between the silicon substrate10and the lower electrode12. The interlayer insulating layer24is disposed around the lower electrode12, the upper electrode14, and the gate electrode20. The interlayer insulating layer24is an oxide, a nitride, or an oxynitride, for example. The interlayer insulating layer24contains a silicon oxide, a silicon nitride, or a silicon oxynitride, for example. When the transistor100is manufactured, the channel layer16, the contact layer18, and the upper electrode14are formed in this order, after the lower electrode32is formed above the silicon substrate10. In the description below, the functions and the effects of the semiconductor device of the first embodiment are explained. An oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer has excellent characteristics that the channel leakage current during an off-operation is extremely small. Because of the characteristics, application of an oxide semiconductor transistor to a switching transistor of a DRAM memory cell is being considered, for example. In a case where an oxide semiconductor transistor is applied to a switching transistor of a memory cell, for example, the oxide semiconductor transistor is subjected to a heat treatment accompanying the formation of wiring lines formed in an upper layer. Therefore, an oxide semiconductor transistor having stable characteristics that hardly fluctuate during the heat treatment is expected to be provided. FIG.3is a schematic cross-sectional view of a semiconductor device of a comparative example.FIG.3is a diagram corresponding toFIG.1showing the semiconductor device of the first embodiment. The semiconductor device of the comparative example is a transistor900. The transistor900is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor900differs from the transistor100of the first embodiment in not including the contact layer18. The transistor900of the comparative example has characteristics that fluctuate due to the heat treatment performed after the formation of the transistor structure. Particularly, in a case where the heat treatment is performed in an oxygen-containing atmosphere, the asymmetry of the on-current becomes a problem. The on-current asymmetry means that there is a difference in the magnitude of the on-current between a case where the current flows from the upper electrode14toward the lower electrode12and a case where the current flows from the lower electrode12toward the upper electrode14. More specifically, the on-current in the direction from the lower electrode12toward the upper electrode14is smaller than the on-current in the direction from the upper electrode14toward the lower electrode12. FIGS.4A and4Bare diagrams for explaining the functions and the effects of the semiconductor device of the first embodiment.FIG.4Ais a band diagram showing the vicinity of the interface between the upper electrode14and the channel layer16of the transistor900of the comparative example.FIG.4Bis a band diagram showing the vicinity of the interface between the upper electrode14and the contact layer18of the transistor100of the first embodiment.FIGS.4A and4Bare band diagrams showing the situations after a heat treatment is performed in an oxygen-containing atmosphere after the formation of the transistor structure. As shown inFIG.4A, a Schottky barrier is formed at the interface between the upper electrode14and the channel layer16. In other words, a Schottky diode is formed between the upper electrode14and the channel layer16. In a case where the transistor900is subjected to a heat treatment in an oxygen-containing atmosphere, oxygen diffuses into the channel layer16from the atmosphere, so that the density of the oxygen deficiency in the channel layer16in the vicinity of the upper electrode14drops. As a result, the carrier concentration in the channel layer16in the vicinity of the upper electrode14drops. As the carrier concentration in the channel layer.16in the vicinity of the upper electrode14becomes lower, the width of the Schottky barrier becomes wider. On the other hand, the amount of oxygen diffusing in the channel layer16in the vicinity of the lower electrode12is smaller than the amount of oxygen diffusing in the channel layer16in the vicinity of the upper electrode14. Therefore, the decrease in the carrier concentration in the channel layer16in the vicinity of the lower electrode12is small. Accordingly, the change in the width of the Schottky barrier between the channel layer16and the lower electrode12is small. Because of this, the on-current in the direction from the channel layer16toward the upper electrode14is smaller than the on-current in the direction from the upper electrode14toward the channel layer16. In the transistor100of the first embodiment, the contact layer18is disposed between the upper electrode14and the channel layer16. As shown inFIG.4B, in the case of the transistor100of the first embodiment, a Schottky barrier is also formed at the interface between the upper electrode14and the contact layer18. In other words, a Schottky diode is formed between the upper electrode14and the contact layer18. The carrier concentration in the contact layer18is higher than the carrier concentration in the channel layer16. Therefore, even if the heat treatment is performed in an oxygen-containing atmosphere, and oxygen diffuses into the contact layer18, the carrier concentration in the contact layer18does not greatly change. Since the carrier concentration in the contact layer18is high, the Schottky barrier width at the interface between the upper electrode14and the contact layer18is smaller than that in the transistor900of the comparative example. Accordingly, it becomes easier for electrons to tunnel through the Schottky barrier from the upper electrode14toward the contact layer18. In other words, the current in the direction from the channel layer16toward the upper electrode14flows easier than that in the transistor900of the comparative example. As a result, even in a case where the heat treatment is performed in an oxygen-containing atmosphere, a difference is not easily generated in the magnitude of the on-current between a case where the current flows from the upper electrode14toward the lower electrode12and a case where the current flows from the lower electrode12toward the upper electrode14. Thus, the on-current asymmetry caused by the heat treatment is reduced. As the on-current asymmetry is reduced, the fluctuations in the transistor characteristics are also reduced. Thus, with the transistor100, the asymmetry of the on-current after the heat treatment is reduced, and an oxide semiconductor transistor having stable characteristics is obtained. To make the carrier concentration in the contact layer18higher than the carrier concentration in the channel layer16, the atomic concentration of the tin (Sn) contained in the contact layer18is preferably higher than the atomic concentration of the tin (Sn) contained in the channel layer16. To make the carrier concentration in the contact layer18higher than the carrier concentration in the channel layer16, the atomic concentration of the indium (In) contained in the contact layer18is preferably higher than the atomic concentration of the indium (In) contained in the channel layer16, for example. (First Modification) FIG.5is a schematic cross-sectional view of a first modification of the semiconductor device of the first embodiment.FIG.5is a diagram corresponding toFIG.1showing the semiconductor device of the first embodiment. The first modification of the semiconductor device of the first embodiment is a transistor110. The transistor110differs from the transistor100of the first embodiment in that the channel layer16is disposed between the contact layer18and the interlayer insulating layer24. In the transistor110of the first modification, the resistance between the contact layer18and the channel layer16is lowered, and the on-current becomes greater than that in the transistor100of the first embodiment. (Second Modification) FIG.6is a schematic cross-sectional view of a second modification of the semiconductor device of the first embodiment.FIG.6is a diagram corresponding toFIG.1showing the semiconductor device of the first embodiment. The second modification of the semiconductor device of the first embodiment is a transistor120. The transistor120differs from the transistor100of the first embodiment in that the contact layer18is interposed or surrounded by the gate insulating layer22. (Third Modification) FIG.7is a schematic cross-sectional view of a third modification of the semiconductor device of the first embodiment.FIG.7is a diagram corresponding toFIG.2showing the semiconductor device of the first embodiment. The third modification of the semiconductor device of the first embodiment is a transistor130. The transistor130differs from the transistor100of the first embodiment in that the first region22aand the second region22bof the gate insulating layer22are separated from each other. In the transistor130, the gate electrode20is also divided into different regions on the right and left sides. As described above, the first embodiment and its modifications reduce the asymmetry of the on-current after the heat treatment, and provide an oxide semiconductor transistor having stable characteristics. Second Embodiment A semiconductor device of a second embodiment differs from the semiconductor device of the first embodiment in that, in a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, a first distance between the first region and the second region in a second direction perpendicular to the first direction at a first position is smaller than a second distance between the first region and the second region in the second direction at a second position, a distance between the first electrode and the second position in the first direction is greater than a distance between the first electrode and the first position in the first direction. In the description below, some explanation of the same aspects as those of the first embodiment may not be repeated. FIG.8is a schematic cross-sectional view of a semiconductor device of the second embodiment. The semiconductor device of the second embodiment is a transistor200. The transistor200is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor200is a so-called SGT in which a gate electrode is disposed so as to surround the oxide semiconductor layer in which the channel is formed. The transistor200is a so-called vertical transistor. The transistor200includes a silicon substrate10, a lower electrode12, an upper electrode14, a channel layer16, a contact layer18, a gate electrode20, a gate insulating layer22, and an interlayer insulating layer24. The gate insulating layer22includes a first region22aand a second region22b. The silicon substrate10is an example of the substrate. The lower electrode12is an example of the first electrode. The upper electrode14is an example of the second electrode. The channel layer16is an example of the oxide semiconductor layer. The contact layer18is an example of the conductive layer. In the transistor200, in a cross-section that is parallel to the first direction from the lower electrode12toward the upper electrode14and includes the channel layer16, the first distance (d1inFIG.8) between the first region22aand the second region22bat the first position (P1inFIG.8) is smaller than the second distance (d2inFIG.8) between the first region22aand the second region22bat the second position (P2inFIG.8) at which the distance from the lower electrode12is greater than the distance between the lower electrode12and the first position P1. The width of the channel layer16in the second direction is greater at a position closer to the upper electrode14, and is smaller at a position closer to the lower electrode12. The side surface of the channel layer16has a forward tapered shape. For example, when the transistor200is manufactured, the lower electrode12, the gate electrode20, and the interlayer insulating layer24are formed, and a hole pattern for filling the gate insulating layer22and the channel layer16is then formed. When the hole pattern is formed, the etching is controlled so that the diameter of the lower portion of each hole becomes smaller. Thus, the above structure can be formed. As described above, like the first embodiment, the second embodiment reduces the asymmetry of the on-current after the heat treatment, and provides an oxide semiconductor transistor having stable characteristics. Third Embodiment A semiconductor device of a third embodiment differs from the semiconductor device of the first embodiment in further including an insulating layer that is disposed between the first electrode and the second electrode, and is surrounded by an oxide semiconductor layer. In the description below, some explanation of the same aspects as those of the first embodiment may not be repeated. FIGS.9and10are schematic cross-sectional views of the semiconductor device of the third embodiment.FIG.10is a cross-sectional view taken along the B-B′ line defined inFIG.9. InFIG.9, the vertical direction is referred to as the first direction. InFIG.9, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first direction. The semiconductor device of the third embodiment is a transistor300. The transistor300is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor300is a so-called SGT in which a gate electrode is disposed so as to surround the oxide semiconductor layer in which the channel is formed. The transistor300is a so-called vertical transistor. The transistor300includes a silicon substrate10, a lower electrode12, an upper electrode14, a channel layer16, a contact layer18, a gate electrode20, a gate insulating layer22, an interlayer insulating layer24, and a core insulating layer26. The gate insulating layer22includes a first region22aand a second region22b. The silicon substrate10is an example of the substrate. The lower electrode12is an example of the first electrode. The upper electrode14is an example of the second electrode. The channel layer16is an example of the oxide semiconductor layer. The contact layer18is an example of the conductive layer. The core insulating layer26is an example of the insulating layer. The core insulating layer26is disposed between the lower electrode12and the upper electrode14. The core insulating layer26is surrounded by the channel layer16. Part of the channel layer16is disposed between the lower electrode12and the core insulating layer26, for example. The core insulating layer26is an oxide, a nitride, or an oxynitride, for example. The core insulating layer26contains a silicon oxide, a silicon nitride, or a silicon oxynitride, for example. As the core insulating layer26is provided in the transistor300, the thickness of the channel layer16in the second direction becomes smaller, for example. As the channel layer16becomes thinner, the gate electrode20has an improved controllability on the electric potential of the channel layer16. Thus, the cutoff characteristics of the transistor300are improved, for example. (Modification) FIG.11is a schematic cross-sectional view of a modification of the semiconductor device of the third embodiment.FIG.11is a diagram corresponding toFIG.9showing the semiconductor device of the third embodiment. The modification of the semiconductor device of the third embodiment is a transistor310. The transistor310differs from the transistor300of the third embodiment in that the channel layer16is disposed between the contact layer18and the interlayer insulating layer24. In the transistor310of the modification, the resistance between the contact layer18and the channel layer16is lowered, and the on-current becomes greater than that in the transistor300of the third embodiment. As described above, like the first embodiment, the third embodiment and its modification reduce the asymmetry of the on-current after the heat treatment, and provide an oxide semiconductor transistor having stable characteristics. Fourth Embodiment A semiconductor memory device of a fourth embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode, the oxide semiconductor layer being in contact with the first electrode, the oxide semiconductor layer containing zinc (Zn) and at least one first element selected from the group consisting of indium (ln), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and a chemical composition of the oxide semiconductor layer being different from a chemical composition of the first electrode and the second electrode; a conductive layer provided between the oxide semiconductor layer and the second electrode, the conductive layer being in contact with the second electrode, the conductive layer containing oxygen (O) and at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti), and a chemical composition of the conductive layer being different from a chemical composition of the first electrode, the second electrode, and the oxide semiconductor layer; a gate electrode; a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; and a capacitor electrically connected to the first electrode. The semiconductor memory device of the fourth embodiment is a semiconductor memory400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory400uses the transistor100of the first embodiment as a switching transistor of a DRAM memory cell. In the description below, part of the explanation of the same aspects as those of the first embodiment will not be repeated. FIG.12is an equivalent circuit diagram of the semiconductor memory device of the fourth embodiment. AlthoughFIG.12illustrates an example case where one memory cell MC is provided, a plurality of memory cells MC may be provided. The semiconductor memory400includes a memory cell MC, a word line WL, a bit line BL, and a plate line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. The region surrounded by a dashed line inFIG.12is the memory cell MC. The word line WL is electrically connected to the gate electrode of the switching transistor TR. The bit line BL is electrically connected to one of the source/drain electrodes of the switching transistor TR. One electrode of the capacitor CA is electrically connected to the other one of the source/drain electrodes of the switching transistor TR. The other electrode of the capacitor CA is connected to the plate line PL. The memory cell MC stores data by accumulating electric charge in the capacitor CA. The switching transistor TR is made to perform an on-operation, to write and read data. For example, while a desired voltage is being applied to the bit line BL, the switching transistor TR is made to perform an on-operation, so that data is written into the memory cell MC. Also, the switching transistor TR is made to perform an on-operation, so that a voltage change in the bit line BL depending on the amount of the electric charge stored in the capacitor is detected, and the data in the memory cell MC is read out, for example. FIG.13is a schematic cross-sectional view of the semiconductor memory device of the fourth embodiment.FIG.13shows a cross-section of the memory cell MC of the semiconductor memory400. The semiconductor memory400includes a silicon substrate10, the switching transistor TR, the capacitor CA, and an interlayer insulating layer24. The silicon substrate10is an example of the substrate. The switching transistor TR includes a lower electrode12, an upper electrode14, a channel layer16, a contact layer18, a gate electrode20, and a gate insulating layer22. The lower electrode12is an example of the first electrode. The upper electrode14is an example of the second electrode. The channel layer16is an example of the oxide semiconductor layer. The contact layer18is an example of the conductive layer. The switching transistor TR has the same structure as that of the transistor100of the first embodiment. The capacitor CA is disposed between the silicon substrate10and the switching transistor TR. The capacitor CA is disposed between the silicon substrate10and the lower electrode12. The capacitor CA is electrically connected to the lower electrode12. The capacitor CA includes a cell electrode71, a plate electrode72, and a capacitor insulating film73. The cell electrode71is electrically connected to the lower electrode12. The cell electrode71is in contact with the lower electrode12, for example. The cell electrode71and the plate electrode72are made of a titanium nitride, for example. The capacitor insulating film73has a stacked structure of a zirconium oxide, an aluminum oxide, and a zirconium oxide, for example. The gate electrode20is electrically connected to the word line WL (not shown), for example. The upper electrode14is electrically connected to the bit line BL (not shown), for example. The plate electrode72is connected to the plate line PL (not shown), for example. When the semiconductor memory400is manufactured, the switching transistor TR is formed after the capacitor CA is formed on the silicon substrate10. When the switching transistor TR is formed, the channel layer16, the contact layer18, and the upper electrode14are formed in this order, after the formation of the lower electrode12. In the semiconductor memory400, an oxide semiconductor transistor having an extremely small channel leakage current during an off-operation is used as the switching transistor TR. Thus, a DRAM having excellent charge retention characteristics is obtained. Further, the switching transistor TR of the semiconductor memory400has the contact layer18between the channel layer16and the upper electrode14. Accordingly, the on-current asymmetry caused by the heat treatment is reduced. Thus, the characteristics of the switching transistor TR become stable, and the characteristics of the semiconductor memory400also become stable. As described above, the fourth embodiment reduces the asymmetry of the on-current after the heat treatment of a switching transistor, and provides a semiconductor memory having stable characteristics. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, semiconductor devices and semiconductor memory devices described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 36,070 |
11942546 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. Integrated Circuit (IC) devices have been evolving rapidly over the last several decades. A typical IC chip may include numerous active devices such as transistors and passive devices such as resistors, inductors, and capacitors. As the transistor size is scaled down, continuously scaling down of voltage (e.g., power supply) is a target for ultra-low power devices. However, voltage scaling down will meet the bottleneck of physical limitation of subthreshold swing (SS) with 60 mV/decade, which is accompanied with a higher off-state leakage current. An NC-FET, which introduces negative capacitance to a gate stack of MOSFET, will overcome the problem. The negative-capacitance may result from the ferroelectricity of a dielectric layer (also called ferroelectric layer) in the gate stack. Ferroelectric (FE) Hf-based oxide gate integrated with transistors as FeFET (Ferroelectric FETs) has promising solution for low power consumption with two naturally major characteristics of hysteresis and steep-SS for negative capacitance (NC) concept, due to CMOS compatible process and scaling down ability. Pursuing steep SS with accompanying hysteresis is a challenge for NC-FET development, as well as the issue of asymmetric SS of bi-directional sweep. Moreover, the reduced NC onset voltage is another challenge to boost steep SS at low operation bias. Aspects of the present disclosure provide an NC-FET having a quasi-antiferroelectric (interchangeably referred to as QAFE) material, wherein the QAFE material allows the NC-FET operates at steep subthreshold swing (e.g., lower than 60 mV/decade) but has no hysteresis or negligible hysteresis. Although the NC-FET described herein is manufactured in a front end of line (FEOL), it is noted that the NC-FET described can also be manufactured in a back end of line (BEOL). FIG.1illustrates a perspective view of an example NC-FET100in accordance with some embodiments of the present disclosure. The NC-FET100includes a substrate110, source/drain regions120formed in the substrate110, an interfacial layer130over the substrate110, a QAFE layer140over the interfacial layer130and a gate electrode150over the QAFE layer140. The interfacial layer130, the QAFE layer140and the gate electrode150can be in combination referred to as a gate structure GS. In some embodiments, the substrate110may include group IV semiconductor material, e.g., Si, Ge, SiGe, or SiC, or other suitable materials. In certain embodiments, the substrate110includes doped Si, such as Si doped with p-type dopant (e.g., boron) or n-type dopant (e.g., phosphorus) Alternatively, the substrate110may include a III-V material, e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GalnAs, InAs, GaInP, InP, InSb, and/or GaInAsP; or a combination thereof. In some embodiments, the substrate110may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Also alternatively, the substrate110may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or another appropriate method. In some embodiments, the substrate110may include one or more transition metal dichalcogenide (TMD) material layers. A TMD material may include a compound of a transition metal and a group VIA element. The transition metal may include tungsten (W), molybdenum (Mo), Ti, or the like, while the group VIA element may comprise sulfur (S), selenium (Se), tellurium (Te), or the like. For example, the substrate110may include MoS2, MoSe2, WS2, WSe2, combinations thereof, or the like. The source/drain regions120are doped regions in the substrate110and located on opposite sides of the gate structure GS. In some embodiments, the source/drain regions120include p-type dopants such as boron for formation of p-type FETs. In some other embodiments, the source/drain regions120include n-type dopants such as phosphorus for formation of n-type FETs. In some embodiments, the source/drain regions120may be epitaxial structures doped with p-type dopants or n-type dopants. The source/drain regions120are spaced apart by a channel region110cin the semiconductor substrate110. The interfacial layer130may include a dielectric material such as silicon oxide (SiO2), Al2O3, HfO2, ZrO2. In some embodiments, the interfacial layer130may include high-k dielectric material. In some embodiments, the thickness of the interfacial layer130is in a range from about 0.1 nm to about 10 nm. In the depicted embodiments, the interfacial layer130extends along a top surface of the channel region110cand past opposite edges of the channel region110cto reach the source/drain regions120. In some embodiments, portions of the source/drain regions120are vertically below the QAFE layer140. The QAFE layer140is between the interfacial layer130and the gate electrode150to provide a negative capacitance effect. In some embodiments, the QAFE layer140may include high-k dielectric material, such as HfZrO2(HZO), HAO (Al-Doped HfO2), HSO (Si-Doped HfO2), lead-zirconate-titanate (PZT), strontium bismuth tantalite (SBT). In some embodiments, the thickness of the QAFE layer140is in a range from about 1 nm to about 15 nm. In certain embodiments, the QAFE layer140is about 10 nm. In some embodiments, the QAFE layer140is formed of quasi-antiferroelectric Hf1-xZrxO2(also called QAFE-HZO in this context, wherein 0.5<x<1). In some embodiments, the zirconium atomic percentage of the QAFE layer140is greater than about 50% and is lower than about 99%. In certain embodiments, the QAFE layer140is Hf0.25Zr0.75O2(i.e., zirconium atomic percentage is 75% relative to hafnium atomic percentage). The QAFE-HZO material exhibits a mixture of ferroelectricity (FE) and antiferroelectricity (AFE) with small but not zero remnant polarization (Pr) and coercive voltage (Vc) while applied low bias. This benefits reduced NC onset voltage and non-hysteretic possibility as well as the low charge balance for steep SS. In some embodiments, the remnant polarization (Pr) of the QAFE layer140is in a range from about 0.5 μC/cm2to about 5 μC/cm2when a sweep voltage 3 V is applied, and the coercive voltage (Vc) of the QAFE layer140is in a range from about 0.1 V to about 0.5 V when a sweep voltage 3 V is applied. The crystalline structure of the QAFE layer140is a mixture of tetragonal phase and orthorhombic phase. In some embodiments, the ratio of the tetragonal phase to the orthorhombic in the QAFE layer140is in a range from about 1/10 to about 10:1. In some embodiments, if the ratio is too small (e.g., much lower than 1/10), this indicates that orthorhombic phase is dominant over the tetragonal phase, and the property would be close to ferroelectricity. On the other hand, if the ratio is too large (e.g., higher than 10), this indicates that tetragonal phase is dominant over the orthorhombic phase, and the property would be close to antiferroelectricity. The gate electrode150may be conductive material, such as metal. In some embodiments, the gate electrode150includes TaN, TiN, W, Pt, Mo, Ta, Ti, Silicide, or the like. In some embodiments, the gate electrode150may include one or more metals or their alloy. In some embodiments, the thickness of the gate electrode150is in a range from about 1 nm to about 1000 nm. In certain embodiments, the gate electrode150is about 120 nm. As illustrated, the polarization transition is shown from FE to QAFE with increasing doped Zr. For example, the loop at zero voltage (e.g., 0 V) is narrowing, and remnant polarization (Pr) and coercive voltage (Vc) are closer to zero for Zr=75% sample. Here, the term “remnant polarization (Pr)” may be defined as the magnitude of polarization at V=0. On the other hand, the term “coercive voltage (Vc)” may be defined as the magnitude of voltage at polarization=0. Note that Zr=75% is a mixture of FE and AFE due to Pr& Vcare small (but not equal to zero). For example, the exact antiferroelectric (AFE) ought to be pure ZrO2. For comparison, Zr=50% can be regarded as FE-HZO. FIG.2shows polarization-voltage (P-V) loop of HZO (Hf1-xZrxO2) with Zr=25%, 50% and 75% in some embodiments of the present disclosure. InFIG.2, the loop C1represents a P-V loop of Hf0.75Zr0.25O2(i.e., zirconium atomic percentage is 25%), the loop C2represents a P-V loop of Hf0.5Zr0.5O2(i.e., zirconium atomic percentage is 50%), and the loop C3represents a P-V curve of Hf0.25Zr0.75O2(i.e., zirconium atomic percentage is 75%). The P-V loop C1is obtained from a capacitor stack formed of a lower titanium nitride layer, a Hf0.75Zr0.25O2layer over the lower titanium nitride layer, and an upper titanium nitride layer over the Hf0.75Zr0.25O2layer, wherein the Hf0.75Zr0.25O2layer has a thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nm). The P-V loop C2is obtained from a capacitor stack formed of a lower titanium nitride layer, a Hf0.5Zr0.5O2layer over the lower titanium nitride layer, and an upper titanium nitride layer over the Hf0.5Zr0.5O2layer, wherein the Hf0.5Zr0.5O2layer has a thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nm). The P-V loop C3is obtained from a capacitor stack formed of a lower titanium nitride layer, a Hf0.25Zr0.75O2layer over the lower titanium nitride layer, and an upper titanium nitride layer over the Hf0.25Zr0.75O2layer, in which the Hf0.75Zr0.25O2layer has a thickness in a range from about 8 nm to about 12 nm (e.g., about 10 nm). Comparing the P-V loop C3with the P-V loops C1and C2, it is observed that the polarization transition is shown from FE to QAFE with increasing zirconium atomic concentration increasing from 25% to 75%. The P-V loop C3at zero voltage is narrowing, and the remnant polarization (Pr) and coercive voltage (Vc) are closer to zero for Zr=75%. Here, the term “remnant polarization (Pr)” may be defined as the magnitude of polarization at V=0. On the other hand, the term “coercive voltage (Vc)” may be defined as the magnitude of voltage at polarization=0. It is noted that Hf0.25Zr0.75O2composition exhibits a mixture of ferroelectricity and antiferroelectricity due to the remnant polarization (Pr) and coercive voltage Vc) are small (but not equal to zero) and this unique property different from exact ferroelectricity and exact antiferroelectricity is denoted as quasi-antiferroelectricity in this context. For example, the exact antiferroelectric (AFE) ought to be pure ZrO2. For comparison, Zr=50% can be regarded as FE-HZO. FIG.3illustrates a GI-XRD (Grazing incidence X-ray diffraction) of FE (Hf0.5Zr0.5O2) and QAFE (Hf0.25Zr0.75O2). The FE and AFE characteristics of the HZO film after annealing is believed to be a result of orthorhombic and tetragonal phase, respectively. The peak position of Hf0.5Zr0.5O2and Hf0.25Zr0.75O2are about 30.5° and about 30.7°, respectively, and this indicates more tetragonal phase as the Zr concentration increases. The crystalline sizes are about 11.7 nm and 15.5 nm by Scherrer equation. FIG.4illustrates transfer characteristics (e.g., forward and reverse IDS-VGScurves) of a FE-HZO FET (i.e., a transistor including a Hf0.5Zr0.5O2layer formed between gate and channel region) with VDSin a range from about 0.1 V to about 0.3 V (e.g., about 0.2 V) and double sweep VGSincreasing range, in accordance with some embodiments of the present disclosure.FIG.5illustrates transfer characteristics (e.g., forward and reverse IDS-VGScurves) of a QAFE-HZO FET (i.e., a transistor including a Hf0.25Zr0.75O2layer formed between gate and channel region) with VDSin a range from about 0.1 V to about 0.3 V (e.g., about 0.2 V) and double sweep VGSincreasing range, in accordance with some embodiments of the present disclosure.FIG.6illustrates transfer characteristics (e.g., forward and reverse IDS-VGScurves) of a non-ferroelectric FET (i.e., a transistor including a HfO2layer formed between gate and channel region) with VDSin a range from about 0.1 V to about 0.3 V (e.g., about 0.2 V) and double sweep VGSincreasing range, in accordance with some embodiments of the present disclosure. As illustrated inFIG.4, the transfer characteristics of FE-HZO FET presents wide hysteresis and steep SS in reverse (backward) curve with sweep VGSrange to about |2.75 V|, and SS lower than 60 mV/decade would be obtained in the reverse curve with sweep VGSrange to about |3 V|. On the other hand, as illustrated inFIG.5, the transfer characteristics of QAFE-HZO FET presents the SS lower than 60 mV/decade in both forward and reverse curves with sweep VGSrange to about |1.5 V|, and no or negligible hysteresis (ΔVt<1 mV, where ΔVtis defined as Vt,forward−Vt,reverse) of double sweep with the sweep VGSrange to about |2 V|. Moreover,FIG.5further shows that the gate leakage current is significant lower than the drain current IDS. On the other hand,FIG.6shows that the transfer characteristics of non-ferroelectric FET present SS higher than 60 mV/decade. Based onFIGS.4-6, it is observed that as compared to FE-HZO FET and non-ferroelectric FET, QAFE-HZO FET advantageously presents bi-directional sub-60 mV/decade (e.g., SSforwardin a range from about 50 mV/decade to about 52 mV/decade, such as about 51 mV/decade, and SSreversein a range from about 52 mV/decade to about 54 mV/decade, such as about 53 mV/decade), no or negligible hysteresis (ΔVt<1 mV), and reduced onset voltage. FIGS.7and8illustrate summarized SSmin(mV/dec) and ΔVTof FE-HZO and QAFE-HZO, respectively. For FE-HZO, the NC onset voltage (e.g., voltage where SSmin is lower than about 60 mV/decade) is larger than hysteresis onset (e.g., voltage where ΔVTis about 0). This indicates the improvement on SS accompanied with a non-negligible hysteresis for FE-HZO. However, the NC onset voltage is smaller than hysteresis onset for QAFE-HZO, i.e. there is an operation window for steep SS without hysteresis. FIG.9illustrates measured P-V and calculated S-shape by L-K model with MOS load line for FE-HZO.FIG.10illustrates measured P-V and calculated S-shape by L-K model with MOS load line for QAFE-HZO. The FET load line and M/FE/M & M/QAFE/M polarization are presented, and the charge balance is the solution. Here, the term “M/FE/M” indicates a metal-FE layer-metal stack capacitor, and the term “M/FE/M” indicates a metal-QAFE layer-metal stack capacitor. InFIG.9, as the voltage drop on FE-HZO increases to open the polarization loop, and the S-shape RL1 is added and intersects with FET load line GL1 at positive capacitance (PC) region (dP/dV>0), with the hysteresis loop spreading with VFEincreasing, the charge balance would be occurred at dP/dV<0 region as for NC effect (intersection of BL1 and GL1). Therefore, the bias for FE-FET hysteresis (ferroelectric characteristics) is smaller than steep SS (NC effect). That is, the improvement on SS with non-negligible hysteresis is occurred for FE-HZO. On the other hand, inFIG.10, the S-shape (RL2) for small VFEis crossover with load line (GL2) at NC region (dP/dV<0) for QAFE-HZO, and then, the PC region is occurred with VFEincreasing (intersection of BL2 and GL2). InFIG.10, the Prof QAFE is restricted with increasing applied voltage and S-shape would be spreaded in voltage/E-field direction (i.e., lateral direction inFIG.10). This leads to a window of charge balance solution for steep SS without hysteresis. FIGS.11to19illustrate a method in various stages of fabricating a NC-FET in accordance with some embodiments of the present disclosure. Reference is made toFIG.11. A substrate110is shown. In some embodiments, the substrate110may include silicon (Si). In certain embodiments, the substrate110includes doped Si, such as Si doped with p-type dopant (e.g., boron). Alternatively, the substrate110may include germanium (Ge), silicon germanium (SiGe), a III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GalnAs, InAs, GaInP, InP, InSb, and/or GaInAsP; or a combination thereof) or other appropriate semiconductor materials. In some embodiments, the substrate110may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Also alternatively, the substrate110may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or another appropriate method. Reference is made toFIG.12. A cleaning process CP is performed to the substrate110. In some embodiments, for example, if the substrate110is exposed to the air, a native oxide layer115may naturally grow on the top surface of the substrate110. The cleaning process CP is performed to the substrate110to prepare it for the formation of gate stacks in a later process. In more detail, to ensure good quality of the gate stacks, native oxide formed on the surfaces of the substrate110is removed. The cleaning process CP is configured to remove such native oxide, such as the native oxide layer115. In some embodiments, the cleaning process CP includes applying diluted hydrofluoric acid (HF) to the surfaces of the substrate110. In some embodiments, the duration of the cleaning process is in a range from about 50 s to about 70 s (e.g., 60 s). Reference is made toFIG.13. An interfacial layer130is formed over the substrate110. In some embodiments, the interfacial layer130may be a dielectric layer, and may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some embodiments where the interfacial layer130is made of silicon oxide (SiO2), the interfacial layer130may be formed by atomic layer deposition (ALD), wet cleaning, thermal oxidation, and/or other suitable process. In some embodiments where the interfacial layer130is made of HfSiO or silicon oxynitride (SiON), the interfacial layer130may be formed by ALD, CVD, PVD, and/or other suitable processes. Next, a QAFE layer140is formed over the interfacial layer130. In some embodiments, the QAFE layer140may be formed by atomic layer deposition (ALD), physical vapor deposition PVD), or other suitable deposition processes. FIG.14illustrates a method for forming the QAFE layer140. In greater detail,FIG.14illustrates a method for forming the QAFE layer140made of Hf0.25Zr0.75O2using an ALD process. In block S101, a first vacuum break process is performed in an ALD chamber. The vacuum break process indicates a process in which a space (e.g., the chamber) is controlled under the atmospheric pressure. In some embodiments, a vacuum controlled break valve (not shown) may be provided to control of gas (e.g., air) entering the chamber, such that the chamber is in under the atmospheric pressure. In block S102, a substrate is loaded into the ALD chamber. For example, the substrate may be the substrate110shown inFIG.13with the interfacial layer130formed thereon. In block S103, the ALD chamber is vacuumized. In greater detail, after the substrate is loaded into the ALD chamber, the chamber, in which the ALD deposition takes place, is maintained under vacuum using a suitable vacuum pump (not shown). In some embodiments, a vacuum port is provided for evacuating air from the chamber. In block S104, an ALD deposition is performed. In some embodiments, each ALD deposition cycle includes several sub-cycles. For example, as shown in block S104, each ALD deposition cycle includes a first sub-cycle SC1, a second sub-cycle SC2, and a third sub-cycle SC3, in which the second sub-cycle SC2 is performed after the first sub-cycle SC1, and the third sub-cycle SC3 is performed after the second sub-cycle SC2. The first sub-cycle SC1 includes an ALD deposition by supplying precursors of H2O and tetrakis(dimethylamino)zirconium (Zr[N(CH3)2]4; TDMAZr) into the ALD chamber. In some embodiments, the first sub-cycle SC1 may be performed under temperature in a range from about 200° C. to about 300° C., a pressure of H2O in a range from about 1 mtorr to about 120 mtorr, and a pressure of TDMAZr in a range from about 1 mtorr to about 60 mtorr. The second sub-cycle SC2 includes an ALD deposition by supplying precursors of H2O and tetrakis(dimethylamino)hafnium (Hf[N(CH3)2]4; TDMAHf) into the ALD chamber. In some embodiments, the second sub-cycle SC2 may be performed under temperature in a range from about 200° C. to about 300° C., a pressure of H2O in a range from about 1 mtorr to about 120 mtorr, and a pressure of TDMAHf in a range from about 1 mtorr to about 60 mtorr. The third sub-Cycle SC3 includes an ALD deposition by supplying precursors of H2O and tetrakis(dimethylamino)zirconium (Zr[N(CH3)2]4; TDMAZr) into the ALD chamber. In some embodiments, the third sub-cycle SC3 may be performed under temperature in a range from about 200° C. to about 300° C., a pressure of H2O in a range from about 1 mtorr to about 120 mtorr, and a pressure of TDMAZr in a range from about 1 mtorr to about 60 mtorr. In some embodiments, the first sub-cycle SC1 and the third sub-cycle SC3 have substantially the same precursors and may be performed under similar condition. In some embodiments, the first sub-cycle SC1 and the third sub-cycle SC3 are the same. The first sub-cycle SC1 and the third sub-cycle SC3 have different precursors from the second sub-cycle SC2. For example, the precursors of the first sub-cycle SC1 and the third sub-cycle SC3 include zirconium (Zr) and do not include hafnium (Hf), while the precursors of the second sub-cycle SC2 includes hafnium (Hf) and does not include zirconium (Zr). In each ALD deposition cycle, the first sub-cycle SC1 is performed X time(s), the second sub-cycle SC2 is performed Y time(s), and the third sub-cycle SC3 is performed Z time(s). In some embodiments, X:Y:Z is 2:1:1. That is, each ALD cycle includes performing the first sub-cycle SC1 for two times, performing the second sub-cycle SC2 for one time after performing the first sub-cycle SC1 for two times, and performing the third sub-cycle SC3 for one time after performing the second sub-cycle SC2. Stated another way, X is greater than Y and Z, and, Y is equal to Z. In some embodiments, X+Z:Y is 3:1. In some other embodiments, X:Y:Z is 1:1:2. That is, each ALD cycle includes performing the first sub-cycle SC1 for one time, performing the second sub-cycle SC2 for one time after performing the first sub-cycle SC1 for one time, and performing the third sub-cycle SC3 for two times after performing the second sub-cycle SC2. Stated another way, Z is greater than X and Y, and X is equal to Y. In some embodiments, X+Z:Y is 3:1. In some embodiments, the ALD deposition includes performing ALD deposition cycle for K times to achieve a desired thickness of the QAFE layer140. In some embodiments, K is in a range from about 20 to 30 (e.g.,25), and the resulting thickness of the QAFE layer140is in a range from about 8 nm to about 12 nm (e.g., about 10 nm). In block S105, after the ALD deposition, a second vacuum break process is performed. That is, the pressure in the chamber is adjusted from vacuum to the atmospheric pressure. Reference is made toFIG.15. A gate electrode150is formed over the QAFE layer140. In some embodiments, the gate electrode150may be formed by may be formed using PVD, CVD, ALD, plating, a combination thereof, or other suitable technology. In some embodiments, the gate electrode150may be formed in-situ in the ALD chamber the same as forming the QAFE layer140, and the substrate110may be moved out from the ALD chamber after the gate electrode150is formed. Reference is made toFIG.16. A photoresist layer160is formed over the gate electrode150. In some embodiments, the photoresist layer160may be formed by spin-on coating a liquid polymeric material over the QAFE layer140. In some embodiments, the photoresist layer160includes a photosensitive chemical, a polymeric material having one or more acid labile groups (ALG), and a solvent. The photosensitive chemical may be a photo-acid generator (PAG) that produces an acid upon radiation. The acid cleaves the ALGs off the polymeric material in a chemical amplification reaction. In some embodiments, the photoresist layer160may be further treated with a soft baking process and a hard baking process. In some embodiments, the photoresist layer160is sensitive to a radiation, such as an I-line light, a DUV light, a EUV light, an e-beam, an x-ray, and an ion beam. Reference is made toFIG.17. The photoresist layer160is patterned. Accordingly, portions of the top surface of the gate electrode150are exposed by the patterned photoresist layer. In some embodiments, the photoresist layer160may be formed by exposing the photoresist layer160to a radiation beam in a lithography system. For example, some portions of the photoresist layer160are exposed by the radiation beam, and other portions of the photoresist layer160remain unexposed. The radiation beam may be an I-line light (365 nm), a DUV radiation such as KrF excimer laser (248 nm) or ArF excimer laser (193 nm), a EUV radiation (e.g., 13.5 nm), an e-beam, an x-ray, an ion beam, or other suitable radiations. In some embodiments, the radiation beam is patterned with a mask, such as a transmissive mask or a reflective mask. The mask includes various patterns for forming IC features in or on the substrate. Reference is made toFIG.18. The gate electrode150, the QAFE layer140, and the interfacial layer130are etched by using the patterned photoresist layer160as an etch mask, thereby transferring the pattern from the patterned photoresist layer160to the gate electrode150, the QAFE layer140, and the interfacial layer130. In some embodiments, the etching process may include dry (plasma) etching, a wet etching, or other suitable etching methods. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. Reference is made toFIG.19. Source/drain regions120are formed in portions of the substrate110exposed by the gate electrode150, the QAFE layer140, and the interfacial layer130. Next, the patterned photoresist layer160is stripped off, leaving the patterned gate electrode150, the patterned QAFE layer140, and the patterned interfacial layer130over the substrate110. In some embodiments, the source/drain regions120may be formed by an ion implantation process to drive dopants into the substrate110, and then performing an annealing process to activate dopants. In some embodiments, the annealing process may utilize rapid thermal annealing (RTA), laser spike annealing (LSA), furnace annealing, microwave annealing, flash annealing, or the like. In some embodiments where the annealing process is a RTA process, the pressure in the RTA chamber is in a range from about 0.001 atm to about 1 atm, the temperature is in a range from about 500° C. to about 1000° C. In some embodiments, the annealing gas is selected from gas that would not react with the material on the substrate110, such as N2, Ar, He, Ne, Kr, Xe, Rn, or the like. In some embodiments, the source/drain dopants are implanted into the substrate110at a tilted angle, which allows for the source/drain regions120laterally extending to directly below the interfacial layer130. In that case, the interfacial layer130, the QAFE layer140and the gate electrode150overlap partial regions of the source/drain regions120. In some other embodiments where the source/drain regions120are epitaxy structures, the source/drain regions120may be formed by epitaxial growing processes, such as CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. FIGS.20to26illustrate a method in various stages of fabricating a NC-FET in accordance with some embodiments of the present disclosure. It is noted that some elements discussed inFIGS.20to26are similar to those discussed above with respect toFIGS.1to19, and thus relevant details will not be repeated for simplicity. Reference is made toFIG.20. A substrate210is shown. The substrate210includes a semiconductor fin215protruding from the top surface of the substrate210. A plurality of isolation structures205are disposed over the substrate210and laterally surrounding the semiconductor fin215. In some embodiments, the semiconductor fin215may be formed by patterning the substrate210, such as removing a portion of the substrate210by an etching process, and a remaining portion of the substrate210protruding from the top surface of the substrate210can be referred to as the semiconductor fin215. In some embodiments, the isolation structures205, which act as a shallow trench isolation (STI) around the semiconductor fin215, may be formed by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. In some embodiments, the isolation structures205may include dielectric material, such a silicon oxide, silicon nitride, or combinations thereof. Reference is made toFIG.21. A gate dielectric layer220and a dummy gate layer225are formed over the semiconductor fin215. In some embodiments, the gate dielectric layer220and the dummy gate layer225can be collectively referred to as dummy gate structure DG. The gate dielectric layer225may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. In some other embodiments, the gate dielectric layer220may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process. The dummy gate layer225may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gate layer225may be doped poly-silicon with uniform or non-uniform doping. The dummy gate layer225may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process. Next, gate spacers230are formed on opposite sidewalls of the dummy gate structure DG. The gate spacers230may be formed by, for example, depositing a spacer layer blanket over the dummy gate structure DG, followed by an anisotropic etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on sidewalls of the dummy gate structure DG. In some embodiments, the gate spacers230may be formed by CVD, SACVD, flowable CVD, ALD, PVD, or other suitable process. Reference is made toFIG.22. Source/drain structures240are formed in the semiconductor fin215exposed by the dummy gate structure DG and the gate spacers230. For example, the exposed portions of the semiconductor fin215exposed by the dummy gate structure DG and the gate spacers230are recessed by suitable process, such as etching. Afterwards, the source/drain structures240are formed respectively over the exposed surfaces of the remaining semiconductor fin215. The source/drain structures240may be formed by performing an epitaxial growth process that provides an epitaxy material over the semiconductor fin215. Reference is made toFIG.23. An interlayer dielectric (ILD) layer245is formed over the source/drain structures240and laterally surrounding the dummy gate structure DG. For example, an ILD material may be deposited over the substrate210, and performing a CMP process to remove excessive ILD material until the top surface of the dummy gate structure DG is exposed. The ILD layer245may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques. In some embodiments, the ILD layer245may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, a contact etch stop layer (not shown), which includes silicon nitride, silicon oxynitride or other suitable materials, may be formed over the source/drain structure240prior to forming the ILD layer. Reference is made toFIG.24. The dummy gate structure DG is removed to from a gate trench GT between the gate spacers230. In some embodiments, the dummy gate structure DG may be removed by suitable process, such as an etching process. In some embodiments, a cleaning process, such as the cleaning process CP discussed inFIG.12may be performed to the semiconductor fin215to remove native oxide from the exposed surface of the semiconductor fin215. Reference is made toFIG.25. An interfacial layer250, a QAFE layer260, and a gate electrode270are sequentially formed in the gate trench GT and over the semiconductor fin215. In some embodiments, the material and the formation method of the interfacial layer250, a QAFE layer260, and a gate electrode270may be similar to the material and the formation method of the interfacial layer130, a QAFE layer140, and a gate electrode150as discussed above with respect toFIGS.1to19. In particular, the QAFE layer260may be formed by the method discussed inFIG.14. Reference is made toFIG.26. A CMP process is performed to the QAFE layer260and the gate electrode270until the top surface of the ILD layer245is exposed. In some embodiments, the remaining portions of the interfacial layer250, the QAFE layer260, and the gate electrode270are referred to as metal gate structure GS. FIGS.27to36illustrate a method in various stages of fabricating a NC-FET in accordance with some embodiments of the present disclosure. It is noted that some elements discussed inFIGS.27to36are similar to those discussed above with respect toFIGS.1to19andFIGS.20to26, and thus relevant details will not be repeated for simplicity. Reference is made toFIG.27. A substrate310is shown. The substrate310includes a protruding portion310P protruding from the top surface of the substrate310. A plurality of first semiconductor layers320and second semiconductor layers322are alternately stacked over the protruding portion310P of the substrate310. A plurality of isolation structures305are disposed over the substrate310and laterally surrounding the protruding portion310P of the substrate310. Because the second semiconductor layers322are suspended over the semiconductor layers320and form a wire-like or a sheet-like structure, the semiconductor layers322can also be referred to as “nanowires” or “nanosheets” in this content. In some embodiments, the first semiconductor layers320, the second semiconductor layers322, and the protruding portion310P may be formed by, for example, alternately depositing first semiconductor materials and second semiconductor materials over the substrate310, forming a patterned mask (not shown) that defines positions of the first semiconductor layers320and the second semiconductor layers322over the topmost second semiconductor material, and performing an etching process to remove portions of the first semiconductor materials, the second semiconductor materials, and the substrate310. The remaining portions of the first semiconductor materials, the second semiconductor materials, and the substrate310are referred to as the first semiconductor layers320, the second semiconductor layers322, and the protruding portion310P. In some embodiments, the first semiconductor layers320, the second semiconductor layers322, and the protruding portion310P form a fin-like structure, and thus the first semiconductor layers320, the second semiconductor layers322, and the protruding portion310P can be referred to as a “fin structure.” The first semiconductor layers320and the second semiconductor layers322have different materials and/or components, such that the first semiconductor layers320and the second semiconductor layers322have different etching rates. In some embodiments, the first semiconductor layers320are made from SiGe. The germanium percentage (atomic percentage concentration) of the first semiconductor layers320is in the range between about 10 percent and about 20 percent, while higher or lower germanium percentages may be used. It is appreciated, however, that the values recited throughout the description are examples, and may be changed to different values. For example, the first semiconductor layers320may be Si0.8Ge0.2or Si0.9Ge0.1, the proportion between Si and Ge may vary from embodiments, and the disclosure is not limited thereto. The second semiconductor layers322may be pure silicon layers that are free from germanium. The second semiconductor layers322may also be substantially pure silicon layers, for example, with a germanium percentage lower than about 1 percent. In some embodiments, the first semiconductor layers320have a higher germanium atomic percentage concentration than the second semiconductor layers322. In some other embodiments, the second semiconductor layers322and the substrate100may be made from the same material or different materials. The first semiconductor layers320and the second semiconductor layers322may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable process(es). In some embodiments, the first semiconductor layers320and the second semiconductor layers322are formed by an epitaxy growth process, and thus the first semiconductor layers320and the second semiconductor layers322can also be referred to as epitaxial layers in this content. Reference is made toFIG.28. A gate dielectric layer330and a dummy gate layer335are formed over the topmost second semiconductor layer322. In some embodiments, the gate dielectric layer330and the dummy gate layer335may be collectively referred to as dummy gate structure DG. Next, gate spacers340are formed on opposite sidewalls of the dummy gate structure DG. Reference is made toFIG.29. An etching process is performed to remove portions of the first semiconductor layers320, the second semiconductor layers322, and the protruding portion310P, so as to form recesses R1on opposite sides of the dummy gate structure DG. After the etching process, sidewalls of the first semiconductor layers320and the second semiconductor layers322are exposed by the recesses R1. In some embodiments, the etching process includes dry etch, wet etch, or combinations thereof. In some embodiments, the etchants for etching the first semiconductor layers320and the second semiconductor layers322may include a hydro fluoride (HF), fluoride (F2), ammonium hydroxide (NH4OH), or combinations thereof. Reference is made toFIG.30. The first semiconductor layers320are horizontally recessed to form a plurality of recesses R2between the second semiconductor layers322. In some embodiments, the first semiconductor layers320are etched to narrower the first semiconductor layers320in the horizontal direction. In some embodiments, the etching process has etching selectivity to the semiconductor layers320and322. For example, the second semiconductor layers322have higher etching resistance to the etching process than the first semiconductor layers320. Stated another way, the etching process etches the first semiconductor layers320at a faster rate than etching the second semiconductor layers322. When the first semiconductor layers320are Ge or SiGe and the second semiconductor layers322are Si, the first semiconductor layers320can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. Reference is made toFIG.31. Inner spacers345are formed in the recesses R2. In some embodiments, the material of the inner spacers345may be low-k material, such as SiO, SiN, SiON, SiCN, SiOC, SiOCN, or the like. The inner spacers345can be formed by ALD or other suitable methods. In some embodiments, the inner spacers345may be formed by, for example, conformally depositing an inner spacer layer in the recesses R1and fills the recesses R2, and performing an etching process to remove portions of the inner spacer layer outside the recesses R2, such that portions of the inner spacer layer in the recesses R2remain after the etching process. Reference is made toFIG.32. Source/drain structures350are formed in the recesses R1. Afterwards, an interlayer dielectric (ILD) layer355is formed over the source/drain structures350and laterally surrounding the dummy gate structure DG. Reference is made toFIG.33. The dummy gate structure DG is removed to from a gate trench GT between the gate spacers340. After the dummy gate structure DG is removed, the first semiconductor layers320and second semiconductor layers322are exposed. Reference is made toFIG.34. The first semiconductor layers320are removed through the gate trench GT, so as to form gaps GP between the second semiconductor layers322and between the bottommost second semiconductor layer320and the protruding portion310P of the substrate310. In some embodiments, the etching process has etching selectivity to the semiconductor layers320and322. For example, the second semiconductor layers322have higher etching resistance to the etching process than the first semiconductor layers320. Stated another way, the etching process etches the first semiconductor layers320at a faster rate than etching the second semiconductor layers322. Reference is made toFIG.35. An interfacial layer360, a QAFE layer370, and a gate electrode380are sequentially formed in the gate trench GT and in the gaps GP. In some embodiments, the material and the formation method of the interfacial layer360, a QAFE layer370, and a gate electrode380may be similar to the material and the formation method of the interfacial layer130, a QAFE layer140, and a gate electrode150as discussed above with respect toFIGS.1to19. In particular, the QAFE layer370may be formed by the method discussed inFIG.14. Reference is made toFIG.36. A CMP process is performed to the QAFE layer360and the gate electrode380until the top surface of the ILD layer355is exposed. In some embodiments, the remaining portions of the interfacial layer360, the QAFE layer370, and the gate electrode380are referred to as metal gate structure GS. In some embodiments, the QAFE layer360is in contact with sidewalls of the inner spacers345. Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that a QAFE layer is used in an NC-FET, and the QAFE material allows the NC-FET operates at steep subthreshold swing (e.g., lower than 60 mV/decade) but has no hysteresis or negligible hysteresis. In some embodiments of the present disclosure, a method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer. In some embodiments of the present disclosure, a method includes forming an interfacial layer over a substrate; forming a Hf1-xZrxO2layer over the interfacial layer, in which x is greater than 0.5, and forming the Hf1-xZrxO2layer comprises loading the substrate to an ALD chamber; performing a first deposition cycle by supplying H2O and a Zr-containing precursor into the ALD chamber; performing a second deposition cycle by supplying H2O and a Hf-containing precursor into the ALD chamber; and performing a third deposition cycle by supplying H2O and a Hf-containing precursor into the ALD chamber; forming a gate electrode over the Hf1-xZrxO2layer; and forming source/drain regions in the substrate and on opposite sides of the gate electrode. In some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer comprising Hf1-xZrxO2, in which x is greater than 0.5 and is lower than 1. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,873 |
11942547 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features, such that the first and second features are not in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The term “nominal” as used herein refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values is typically due to slight variations in manufacturing processes or tolerances. The term “substantially” as used herein indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “substantially” can indicate a value of a given quantity that varies within, for example, ±5% of a target (or intended) value. The term “about” as used herein indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 5-30% of the value (e.g., ±5%, ±10%, ±20%, or 30% of the value). The term “vertical,” as used herein, means nominally perpendicular to the surface of a substrate. The term “horizontal,” as used herein, means nominally parallel to the top surface of a substrate. The term “dielectric layer” or “dielectric material”, as used herein, refers to a layer or a material that functions as an electrical insulator. In integrated circuit (IC) fabrication, the source and drain regions of the field effect transistors (FETs) include one or more epitaxial layers grown on a portion of a semiconductor area. N-type FETs (NFETs) and p-type FETs (PFETs) can have different epitaxial layers in their source/drain regions. For example, PFETs can include source/drain regions with silicon germanium (SiGe) epitaxial layers, while NFETs can include source/drain regions with epitaxial layers having n-type dopants and carbon co-dopants. To promote a defect-free growth of the epitaxial source/drain layers on an underlying semiconductor surface, the epitaxial layer and the underlying semiconductor material need to have similar or comparable lattice constants (e.g., within a fraction of an angstrom or less). Since germanium (Ge) has a larger lattice constant than silicon (Si) (e.g., 5.66 Å for Ge as compared to 5.34 Å for Si), SiGe will have a lattice constant that is larger than that of Si and smaller than that of Ge. For example, depending on the concentration of Ge in the SiGe matrix, the lattice constant for SiGe can range from about 5.5 Å to about 5.6 Å. The growth behavior of epitaxial layers on dielectric materials, which can have either a polycrystalline or an amorphous microstructure, can also be challenging due to a lattice constant mismatch between the epitaxial material (e.g., SiGe) and the amorphous or polycrystalline material (e.g., silicon oxide, silicon nitride, silicon oxy-nitride, etc.). This is because amorphous or polycrystalline materials do not have a lattice constant. For example, amorphous or polycrystalline materials do not have a lattice or “long range” crystalline order like crystalline materials. The semiconductor areas in an IC are electrically isolated via isolation areas or regions filled with an amorphous dielectric material, such as silicon oxide. Some source/drain regions can be formed on an area of the semiconductor structure that borders with an isolation region. In these areas, a SiGe source/drain epitaxial layer can come in contact with a portion of the isolation region during growth. As such, the SiGe epitaxial layer grows on two surfaces with different respective microstructures—a crystalline surface (semiconductor area) and an amorphous surface (isolation region). As a result of this mismatch, the SiGe layer can develop one or more facets at the dielectric interface that can suppress the growth of the SiGe layer in certain crystallographic directions. As a result of the facet formation, the SiGe layer can grow thinner in the vicinity of the isolation region and thicker away from the isolation region. In other words, the thickness of the SiGe epitaxial layer across the source/drain region can vary. Further, the SiGe epitaxial layer can develop a “sloped” top surface due to the facet formation. The facet formation is random and can consequently lead to a SiGe thickness non-uniformity across the wafer. This in turn can narrow the etching process window for contact openings subsequently formed on the SiGe epitaxial layers. For timed etching processes, the depth of the contact openings may vary substantially for SiGe epitaxial layers with different thicknesses and top surface slopes. Consequently, some contact openings will reach the SiGe top surface, while others will not. The present disclosure is directed to a method that mitigates, or eliminates, the formation of facets during the SiGe epitaxial layer growth. This in turn produces SiGe epitaxial layers that are more uniform and have a horizontal top surface across the source/drain region. In some embodiments, this can be accomplished by forming a SiGe nanostructure at the interface of the semiconductor/isolation region. The SiGe nanostructure can be interposed between the grown SiGe epitaxial layer and the dielectric material in the isolation region. In some embodiments, the SiGe nanostructure can be used as a growth surface with reduced lattice mismatch for the SiGe epitaxial layers. In some embodiments, the Ge implant dose can range from about 1×1016atoms/cm2to about 1×1018atoms/cm2and the resulting Ge implanted area can have a width between about 5 nm and about 25 nm. FIG.1is a flow chart of an exemplary fabrication method100that describes the formation of a SiGe nanostructure between a SiGe source/drain region and an isolation region. In some embodiments, the SiGe nanostructure is formed in a portion of the isolation region to promote the formation of SiGe epitaxial layer with a substantial horizontal top surface and uniform thickness. In some embodiments, the SiGe nanostructure is formed by doping a selected area of the isolation region adjacent to the semiconductor layer with Ge dopants. This disclosure is not limited to this operational description. Other operations are within the spirit and scope of the present disclosure. It is to be appreciated that additional operations may be performed. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously, or in a different order than shown inFIG.1. In some implementations, one or more other operations may be performed in addition to or in place of the presently described operations. For illustrative purposes, fabrication method100is described with reference to the embodiments shown inFIGS.2through11. Fabrication method100begins with operation110, where isolation regions can be formed abutting a semiconductor layer with a gate structure formed thereon. By way of example and not limitation,FIG.2is a cross sectional view of isolation regions200abutting a semiconductor layer210with a gate structure220formed on semiconductor layer210. In some embodiments, isolation regions200can be, for example, shallow trench isolation (STI) regions filled with an amorphous dielectric material, such as silicon oxide (SiOx). Semiconductor layer210can be an oxide defined (OD) region—for example, a semiconductor structure surrounded (“defined”) by isolation regions200. In some embodiments, top surfaces200Tof isolation regions200are not coplanar with top surface210Tof semiconductor layer210. For example, top surface210rcan be below the level of top surface200T, as shown inFIG.2. However, this is not limiting, and top surfaces200Tand210Tcan be coplanar. Further, top surfaces200Tand210Tare horizontal surfaces, e.g., nominally parallel to the x-y plane and nominally parallel to a top surface of a substrate (not shown inFIG.2). Semiconductor layer210can be an active region on which one or more FETs can be formed. For example, semiconductor layer210can be doped, un-doped, or include one or more doped regions. By way of example and not limitation, semiconductor layer210can be a semiconductor fin on which one or more FETs can be formed. In some embodiments, semiconductor layer210can include (i) silicon, (ii) a compound semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), silicon germanium (SiGe), (iii) an alloy semiconductor including, gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or (iv) combinations thereof. For example purposes, semiconductor layer210and isolation regions200in fabrication method100will be described in the context of a crystalline silicon layer and amorphous silicon oxide, respectively. Based on the disclosure herein, other materials, as discussed above, can be used. These materials are within the spirit and scope of this disclosure. In some embodiments, gate structure220is a sacrificial gate structure that can be replaced with a metal gate structure in a subsequent operation. Gate structure220can include a gate electrode230and gate dielectric240. In some embodiments, gate electrode230includes polycrystalline silicon (“poly”) and gate dielectric240includes a dielectric, such as silicon oxide grown directly over semiconductor layer210. Further, gate electrode230of gate structure220can be capped (e.g., covered) with a hard mask layer245, as shown inFIG.1. In some embodiments, hard mask layer245is an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a stack that includes an oxide and a nitride. In some embodiments, hard mask layer245protects gate structure220from a subsequent etching process. In operation120of fabrication method100, photoresist structures can be formed to mask the gate structure and a portion of the isolation regions from an implant operation. By way of example and not limitation, the photoresist structures can be formed by patterning a photoresist layer disposed over the structure. As shown inFIG.2, photoresist structures250mask (e.g., cover) gate structure220and partially mask isolation regions200. In other words, photoresist structures250partially overlap with top surface200rof isolation region200so that exposed portions of isolation regions200with a width260are formed. According to some embodiments, width260can range from about 5 nm to about 25 nm (e.g., from about 5 nm to about 10 nm, from about 8 nm to about 15 nm, from about 12 nm to about 20 nm, from about 18 nm to about 25 nm, etc.). In some embodiments, width260defines the width of a Ge-doped region that will be formed in isolation region200in a subsequent operation of fabrication method100. As shown inFIG.2, the exposed portions of isolation regions200are immediately adjacent to semiconductor layer210. In some embodiments, the width of photoresist structure250over gate structure220is larger than the width of gate structure220, as shown inFIG.2. For example, each side of the photoresist structure250extends beyond the edges of gate structure220by an overlay width255. Since each photoresist structure250is an implant mask, the width of each photoresist structure250can define the areas of semiconductor layer210and isolation regions200that can be implanted with Ge dopants. Referring toFIG.1, fabrication method100continues with operation130, where the unmasked, or exposed, portions of semiconductor layer210and isolation regions200are implanted with Ge dopants. A purpose of operation130is to form Ge-doped regions in the semiconductor layer that extend from the semiconductor layer to a portion of the isolation region. For example,FIG.3shows Ge-doped regions300formed in semiconductor layer210and isolation regions200after the implant process of operation130. In the example ofFIG.3, photoresist structures250have been removed with an etching process (e.g., wet etching process).FIG.4is a top view of the structure depicted inFIG.3. In some embodiments,FIG.3is a cross-sectional view ofFIG.4along dotted line AB. As shown inFIG.4, gate structure220may extend over isolation region200in the y-direction. Further, isolation region200surrounds semiconductor layer210in the x-y plane. It is noted that the dimensions and relative position of gate structure220and semiconductor layer210are not limited to the example ofFIG.4. Therefore, alternative dimensions and placement of gate structure220and semiconductor layer210are possible. Further, multiple gate structures and semiconductor layers are possible. In some embodiments, the implant dose during the implant process of operation130can range from about 1×1016ions/cm2to about 1×1018ions/cm2. An optional rapid thermal annealing process or another thermal treatment at a temperature between about 600° C. and about 1100° C. can “activate” the Ge dopants (e.g., allow the Ge dopants to diffuse and chemically bond with the silicon atoms). Referring toFIGS.3and4, doped region300can extend from the edges of semiconductor layer210into isolation region200from about 5 nm to about 25 nm. In other words, Ge-doped regions300can extend into isolation region200by a width310that is substantially equal or greater than width260ofFIG.2. This is because the Ge dopants can diffuse into isolation region200from their implanted position during the annealing process. Therefore, width310can be equal or greater than width260, according to some embodiments. Further, width310may depend on width260, the implant conditions (e.g., implant direction and implant energy), and the annealing conditions of the dopant activation process (e.g., annealing temperature and duration). In some embodiments, thermal activation of the Ge dopants at temperatures between about 600° C. and 1100° C. results in the formation of SiGe and Ge “nanostructures” in isolation regions200. For example, a SiGe crystalline nanostructure can be formed when Ge dopants diffuse and bond with silicon atoms in isolation regions200. In some embodiments, the SiGe nanostructures include oxygen atoms. The formed SiGe and Ge nanostructures may have a lattice constant that is closer matched to the lattice constant of epitaxially grown SiGe and Ge layers (e.g., between about 5.5 Å and about 5.66 Å), however their exact lattice constant value within isolation regions200can be difficult to predict. According to some embodiments, width310can range from about 5 nm to about 25 nm. In some embodiments, for widths310that are narrower than about 5 nm, a SiGe microstructure may not be formed due to the limited availability of Ge-dopants and silicon atoms or the formed SiGe/Ge nanostructures may not be large enough to provide a growth surface for the epitaxial SiGe layers. On the other hand, for widths310that are larger than about 25 nm, the formed SiGe microstructure can be detrimental to the dielectric properties of isolation regions200and cause electrical shorts between adjacent semiconductor layers210—for example, when a pitch between semiconductor layers210is comparable to width310(e.g., between about 30 and about 35 nm). In some embodiments, and referring toFIG.4, the placement of Ge-doped region300is such that a distance400between gate structure220and Ge-doped region300is maintained at about 40 nm or greater (e.g., ≥40 nm). This is to prevent leakage current between a channel region (not shown inFIG.4) formed in semiconductor layer210(e.g., below gate structure220) and the Ge-doped region300. In some embodiments, distance400is controlled through overlay width255between photoresist structure250and gate structure220, as shown inFIG.2. In some embodiments, distance400is equal to the total thickness of spacers600on the sidewalls of gate structure220. In referring toFIG.5, an oxide layer500and a nitride layer510can be conformally deposited over gate structure220, semiconductor layer210, and isolation regions200. By way of example and not limitation, oxide layer500can include silicon oxide (SiOx) deposited from tetraethyl orthosilicate (TEOS), and nitride layer510can include silicon nitride (SiNx). In referring toFIG.1and operation140, photoresist structures can be formed to mask isolation regions200in preparation for a subsequent etching operation. In some embodiments, the photoresist structures are etch mask structures that protect the underlying portions of isolation regions200from being etched during an etching operation (e.g., dry etching process). Referring toFIG.5, photoresist structures520are formed over isolation regions200so that the inner sidewall surfaces520Sof photoresist structures520are aligned to the upper sidewall surfaces200Sof the underlying isolation regions200. Meanwhile, the portions of Ge-doped region300within semiconductor layer210are not masked by photoresist structures520and can be exposed to the etching chemistry of the subsequent etching operation. In some embodiments, photoresist structures520are formed by exposing and developing (e.g., patterning) a photoresist layer disposed over gate structure220, isolation regions200, and semiconductor layer210. In referring toFIG.1and operation150of fabrication method100, portions of Ge-doped regions300in semiconductor layer210are etched away to form respective openings in semiconductor layer210. According to some embodiments,FIG.6shows the structure ofFIG.5after the etching process of operation150. In some embodiments, the etching process can include multiple etching steps. Further, these etching steps may not be limited to a single etching chemistry. By way of example and not limitation, a first etching step can be configured to preferentially remove nitride layer510and oxide layer500from the horizontal surfaces of the structure shown inFIG.5(e.g., the top surfaces of gate structure220, semiconductor layer200, and isolation regions200). At the same time, the first etching step can partially etch nitride layer510and oxide layer500from vertical surfaces, such as the sidewalls of gate structure220. Consequently, spacers600are formed on the sidewalls of gate structure220, as shown inFIG.6. By way of example and not limitation the first etching step can be an anisotropic dry etching process configured to exhibit directional etching along the z-direction (e.g., perpendicular to the top surface of gate structure220and semiconductor layer210). The first etching step exposes hard mask layer245over gate structure220and the top surfaces of semiconductor layer210and isolation regions200. Subsequently, a second etching step can etch away portions of Ge-doped regions300in semiconductor layer200to form respective openings610. In some embodiments, the second etching step is an anisotropic dry etching process configured to preferentially etch Ge-doped regions300in semiconductor layer210over the dielectric material with Ge dopants in isolation regions200and nitride layer510on the sidewalls of gate structure220. In some embodiments, the dry etching process can be end-pointed when, for example, Ge-doped regions300in semiconductor layer210are removed and the underlying substantially “Ge-free” semiconductor layer210is exposed. The term “Ge-free” semiconductor layer210, as used herein, refers to semiconductor layer210that is substantially free from Ge-dopants but can be doped with other types of dopants or can be un-doped. In some embodiments, the drying etching process is a timed process or a combination of timed and end-pointed processes. By way of example and not limitation, the etching chemistry can etch Ge-doped semiconductor layer210faster than Ge-free semiconductor layer210. Hence, a slow etching rate during the etching process can signal the removal of doped region300from semiconductor layer210. In some embodiments, the etching process is configured so that depth d1of opening610is equal or greater than depth d2of SiGe nanostructure (e.g., Ge-doped region300) in isolation region200(e.g., d1≥d2). In some embodiments, Ge-doped regions300in isolation region200are not etched (e.g., removed) during operation150, as shown inFIG.6. As discussed above, this is because photoresist structures520(e.g., shown inFIG.5) mask (e.g., protect) the Ge-doped regions in isolation structures200during the etching process of operation150, and further because the second etching step of the etching process in operation150can be selected so that it can preferentially remove Ge-doped semiconductor layer210as opposed to the Ge-doped dielectric material in isolation regions200. In referring toFIG.1and operation160of fabrication method100, a SiGe stack can be epitaxially grown in each opening610. In some embodiments, each epitaxially grown SiGe stack features a substantially horizontal top surface and a substantially uniform thickness. In referring toFIG.7, SiGe stack700can have a top surface700Tand a bottom surface700Bthat are substantially parallel to “horizontal” plane x-y. In some embodiments, the x-y plane is parallel to a top surface of a substrate, which is not shown inFIG.7for simplicity. According to some embodiments, the resulting top surface700′ can be slope-free because the SiGe nanostructure (e.g., in Ge-doped region300) of each isolation region200can act as a “growth surface” with a “reduced” lattice mismatch. In other words, the SiGe and Ge nanostructures in doped region300can act as an interface layer (e.g., buffer layer) between the silicon oxide in isolation region200and SiGe stack700. As a result, SiGe and Ge nanostructures in isolation regions200can suppress the formation of facets in the SiGe stack700that are responsible for the formation of a sloped top surface and thickness non-uniformities in SiGe stack700. In some embodiments, SiGe stacks700can include two or more epitaxial layers, which are not individually shown inFIG.7for simplicity. The epitaxial layers can be grown in succession in openings610and feature different Ge atomic percentages (atomic %) and B dopant concentrations. By way of example and not limitation, the first layer can have a Ge atomic % that ranges from 0 to about 40%, and a B dopant concentration that ranges from about 5×1019atoms/cm3to about 1×1021atoms/cm3. The second epitaxial layer can have a Ge atomic % that ranges from about 20% to about 80%, and a B dopant concentration that ranges from about 3×1020atoms/cm3to about 5×1021atoms/cm3. Finally, the third epitaxial layer is a capping layer that can have similar Ge atomic % and B dopant concentrations as the first layer (e.g., 0 to about 40% for Ge, and about 5×1019atoms/cm3to about 1×1021atoms/cm3for B dopant). The thickness of these layers can vary depending on the device performance requirements. For example, the first epitaxial layer can have a thickness range between about 10 nm and about 20 nm, the second epitaxial layer can have a thickness range between about 30 nm to about 60 nm, and the third epitaxial layer (capping layer) can have a thickness range between 0 nm and about 10 nm. The aforementioned concentration and thickness ranges are exemplary and are not intended to be limiting. In some embodiments, the SiGe epitaxial growth process can be performed at high temperatures ranging from about 450° C. to about 740° C. During the epitaxial growth, the process pressure can range between about 1 Torr and about 100 Torr, and the reactant gasses may include silane (SiH4), disilane (Si2He), germane (GeH4), diborane (B2H6), hydrochloric acid (HCl), in which one or more of these reactant gases can be combined with hydrogen (H2), nitrogen (N2), or argon (Ar). The aforementioned ranges and types of gasses are exemplary and are not intended to be limiting. In some embodiments and referring toFIG.7, contact openings710can be formed in an interlayer dielectric (ILD) layer720over SiGe stacks700. Contact openings710are formed by etching ILD layer720(e.g., with a dry etching process) until the top surface of each SiGe stack700is exposed as shown inFIG.8. In some embodiments, contact openings710are formed after the replacement of gate structure220with a metal gate structure (not shown inFIG.7). Since top surfaces700rof SiGe stacks700are grown parallel to the horizontal plane x-y, the etching process window for contact openings710can be improved, which is further described with respect toFIG.8. In the exemplary structure ofFIG.8, contact opening710is formed over “an ideal” SiGe stack700that has a top surface710rparallel to horizontal plane x-y, and contact opening800is formed over a “non-ideal” SiGe stack810that has a sloped top surface810T. According to some embodiments, the sloped top surface810rof SiGe stack810is attributed to the absence of a SiGe nanostructure in isolation region200abutting SiGe stack810, and the horizontal top surface700Tof SiGe stack700is attributed to the presence of a SiGe nanostructure in Ge-doped region300of isolation region200abutting SiGe stack700. In the example ofFIG.8, both contact openings710and800are formed concurrently during the same etching operation. However, contact opening800will have to be formed taller than contact opening710due to the sloped geometry of top surface810T of SiGe stack810. Therefore, if the etching process is timed—e.g., based on the time required by the etching process to form contact opening710on an ideal SiGe stack700—contact opening800may not be completely formed on a less ideal SiGe stack810, as shown inFIG.8. Further, if the etching process is designed to end-point when, for example, SiGe is exposed, contact opening800may not be formed because contact opening710will first expose SiGe stack700and signal the end of the etching process. Therefore, an “over-etch” process will be required so that both contact openings800and710are formed. However, if an over-etch process is used, SiGe stack700will be subjected to additional etching for the duration of the over-etch process—e.g., while contact opening800is being formed. The over-etch process can damage the epitaxial layers of SiGe stack700. Further, the slope of top surface810T may vary from SiGe stack to SiGe stack. For example, non-ideal SiGe stacks (e.g., like stack810) can have top surfaces that form a different slope angle with the horizontal x-y plane. Consequently, determining an over-etch process window for the formation of contact openings on non-ideal SiGe stacks with varying degrees of sloped top surfaces can be challenging. This in turn can cause ambiguity in the contact etching process and can lead to un-etched contact openings across the substrate. In contrast, the formation of SiGe nanostructures in Ge-doped regions300of isolation regions200, according to fabrication method100, can reduce the appearance of facets and the growth of less ideal SiGe stacks like SiGe stack810. In some embodiments,FIG.9is a top view ofFIG.8. The embodiments described herein are not limited to the exemplary layout ofFIG.9and additional layouts with different gate structure and semiconductor layer arrangements are within the spirit and scope of this disclosure. For example,FIGS.10and11provide additional layouts where additional gate structures and semiconductor layers are provided in different arrangements, according to some embodiments. In each of these arrangements shown inFIGS.10and11, Ge-doped regions300are surrounding respective SiGe stacks700. FIG.12is a flow chart of an exemplary fabrication method1200according to some embodiments of the present disclosure. Fabrication method1200describes the formation of a SiGe nanostructure adjacent to the isolation region and within the semiconductor layer. In some embodiments, the SiGe nanostructure is formed by doping a selected area of the semiconductor layer adjacent to the isolation region with Ge dopants. The SiGe nanostructure disposed in the semiconductor layer between the isolation region and the SiGe epitaxial layer promotes the formation of SiGe epitaxial layers with a substantial horizontal top surface and uniform thickness. This disclosure is not limited to this operational description. Rather, other operations are within the spirit and scope of the present disclosure. It is to be appreciated that additional operations may be performed. Moreover, not all operations may be needed to perform the disclosure provided herein. Additionally, some of the operations may be performed simultaneously, or in a different order than shown inFIG.12. In some implementations, one or more other operations may be performed in addition to or in place of the presently described operations. For illustrative purposes, fabrication method1200is described with reference to the embodiments shown inFIGS.13through21. Fabrication method1200begins with operation1210, where isolation regions can be formed abutting a semiconductor layer with a gate structure formed on the semiconductor layer. By way of example and not limitation,FIG.13, similarly toFIG.2, is a cross sectional view of isolation regions200abutting a semiconductor layer210with a gate structure220formed thereon. In some embodiments, isolation regions200can be STI regions filled with an amorphous dielectric material, such as silicon oxide. Semiconductor layer210can be an OD region. In some embodiments, top surfaces200Tof isolation regions200are not coplanar with top surface210Tof semiconductor layer210. For example, top surface210Tcan be below the level of top surface200T, as shown inFIG.13. However, this is not limiting, and top surfaces200Tand210Tcan be coplanar. Further200Tand210rare horizontal surfaces, e.g., nominally parallel to the x-y plane and nominally parallel to a top surface of a substrate (not shown inFIG.13). For example purposes, semiconductor layer210and isolation regions200in fabrication method100will be described in the context of a crystalline silicon layer and amorphous silicon oxide, respectively. Based on the disclosure herein, other materials, as discussed above, can be used. These materials are within the spirit and scope of this disclosure. As discussed above, gate structure220is a sacrificial gate structure that can be replaced with a metal gate structure in a later operation. Gate structure220can further include a gate electrode230and gate dielectric240. In some embodiments, gate electrode230includes polycrystalline silicon (“poly”), and gate dielectric240includes a dielectric, such as silicon oxide grown over semiconductor layer210. Further, gate electrode230of gate structure220can be capped with a hard mask layer245, as shown inFIG.13. In some embodiments, hard mask layer245is an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a stack that includes an oxide and a nitride. In some embodiments, hard mask layer245protects gate structure220from a subsequent etching process. In operation1220of fabrication method1200, photoresist structures can be formed to mask the gate structure and the isolation regions from a subsequent implant operation. By way of example and not limitation, the photoresist structures can be formed by patterning a photoresist layer. As shown inFIG.13, photoresist structures1300mask gate structure220and isolation regions200. In other words, photoresist structures250overlap with top surface200Tof isolation region200so that the inner sidewall surfaces1300Sof photoresist structures1300are aligned to the upper sidewall surfaces200Sof the underlying isolation regions200. In some embodiments, the width of photoresist structure1300over gate structure220is larger than the width of gate structure220, as shown inFIG.13. For example, on each side of the photoresist structure250extends beyond the edges of gate structure220by an overlay width255. Since each photoresist structure1300is an implant mask, openings between the photoresist structures define the areas that can be implanted with Ge dopants. Referring toFIG.12, fabrication method1200continues with operation1230, where the unmasked, or exposed, portions of semiconductor layer210are implanted with Ge dopants. A purpose of operation1230is to form Ge-doped regions in the semiconductor layer. For example,FIG.14shows Ge-doped regions1400formed in semiconductor layer210after the implant process of operation1230. In the example ofFIG.14, photoresist structures1300have been removed with an etching process (e.g., wet etching process).FIG.15is a top view of the structure depicted inFIG.14. In some embodiments,FIG.14is a cross-sectional view ofFIG.15along dotted line CD. As mentioned above, the dimensions and relative position of gate structure220and semiconductor layer210are not limited to the example ofFIG.15. Therefore, alternative dimensions and placement of gate structure220and semiconductor layer210are possible. Further, multiple gate structures and semiconductor layers are possible. In some embodiments, the implant dose during the implant process of operation1230can range from about 1×1016to about 1×1018ions per cm2. An optional rapid thermal annealing process or another thermal treatment can activate the Ge dopants (e.g., allow the Ge dopants to diffuse and chemically bond with the silicon atoms). Referring toFIGS.14and15, doped region1400in semiconductor layer210can extend to the interface with isolation region200. In some embodiments, thermal activation of the Ge dopants at temperatures between about 600° C. and 1100° C. results in the formation of SiGe nanostructures in semiconductor layer210. For example, a SiGe crystalline nanostructure can be formed when Ge dopants diffuse and bond with the silicon atoms in semiconductor layer210. The formed SiGe nanostructures may have a lattice constant that is closer matched to the lattice constant of the epitaxially grown SiGe layers (e.g., between about 5.5 Å and about 5.6 Å) In some embodiments and referring toFIG.15, the placement of Ge-doped region1400is such that a distance400between gate structure220and Ge-doped region1400is maintained at about 40 nm or greater (e.g., ≥40 nm) to prevent leakage current between a channel region (not shown inFIG.15) formed in semiconductor layer210(e.g., below gate structure220) and the Ge-doped region1400. In some embodiments, distance400is controlled through overlay width255between photoresist structure1300and gate structure220, as shown inFIG.13. In some embodiments, distance400is equal to the total thickness of spacers600on the sidewalls of gate structure220. In referring toFIG.16, an oxide layer500and a nitride layer510can be conformally deposited over gate structure220, semiconductor layer210, and isolation regions200. By way of example and not limitation, oxide layer500can include silicon oxide (SiOx) deposited from TEOS, and nitride layer510can include silicon nitride (SiNx). In referring toFIG.12and operation1240, photoresist structures can be formed to mask isolation regions200and a portion of semiconductor layer210in preparation for a subsequent etching operation. In some embodiments, the photoresist structures are etch mask structures that protect the underlying portions of isolation regions200and semiconductor layer210from being etched during an etching process (e.g., dry etching process). Referring toFIG.16, photoresist structures1600are formed over isolation regions200and a portion of semiconductor layer210, so that the inner sidewall surfaces1600Sof photoresist structures1600are extending over semiconductor layer210by a width1610. In other words the distance between the upper sidewall surface200Sof isolation region200and the sidewall surface1600Sof photoresist structure1600is equal to width1610. Therefore, the portion of Ge-doped region1400that is masked by photoresist structure1600has width1610, as shown inFIG.16. The portions of Ge-doped region1400within semiconductor layer210not masked by photoresist structures1600are exposed to the etching chemistry of the subsequent etching operation. In some embodiments, photoresist structures1600are formed by exposing and developing (e.g., patterning) a photoresist layer that is disposed over gate structure220, isolation regions200, and semiconductor layer210. In referring toFIG.12and operation1250of fabrication method1200, unmasked portions of Ge-doped regions1400in semiconductor layer210are etched to form respective openings. According to some embodiments,FIG.17shows the structure ofFIG.16after the etching process of operation1250. In some embodiments, the etching process can include multiple etching steps. Further, these etching steps may not be limited to the same etching chemistry because they are designed to remove different types of materials (e.g., oxides, nitrides, silicon, etc.). By way of example and not limitation, a first etching step can be configured to preferentially remove nitride layer510and oxide layer500from the horizontal surfaces of the structure shown inFIG.16(e.g., the top surfaces of gate structure220, semiconductor layer200and isolation regions200). At the same time, the first etching step can partially etch nitride layer510and oxide layer500from vertical surfaces, such as the sidewalls of gate structure220. Consequently, spacers600are formed on the sidewalls of gate structure220, as shown inFIG.17. By way of example and not limitation the first etching step can be an anisotropic dry etching process configured to exhibit a directional etching along the z-direction (e.g., perpendicular to the top surface of gate structure220and semiconductor layer210). Once the top surface of semiconductor layer210is exposed, a second etching step can etch away the unmasked portions of Ge-doped regions1400in semiconductor layer210to form respective openings1700. In some embodiments, the second etching step is an anisotropic dry etching process configured to preferentially etch Ge-doped regions1400in semiconductor layer210. In some embodiments, the dry etching process can be end-pointed when, for example, Ge-doped regions1400in semiconductor layer210are removed and the underlying substantially Ge-free semiconductor layer210is exposed. As discussed above, the term “Ge-free”, as used herein, refers to semiconductor layer210that is substantially free from Ge-dopants but can be doped with other types of dopants (e.g., boron, phosphorous, arsenic, etc.) or can be un-doped. In some embodiments, the drying etching process is a timed process or a combination of timed and end-pointed processes. By way of example and not limitation, the etching chemistry of the etching process can etch Ge-doped semiconductor layer210faster than Ge-free semiconductor layer210. Hence, a slow etching rate in the etching process can signal the end of the etching process and the removal of Ge-doped regions1400. In some embodiments the etching process is configured so that depth d3of opening610is equal or greater than depth d4of SiGe nanostructure (e.g., Ge-doped region1400) in isolation region200(e.g., d3≥d4). In some embodiments, the masked portion of Ge-doped regions1400in semiconductor layer210are not etched (e.g., removed) during operation1250, as shown inFIG.17. As discussed above, this is because photoresist structures1600(e.g., shown inFIG.16) partially mask, by width1610, the Ge-doped regions in semiconductor layer210during the etching process of operation1250. Consequently, the width of the un-etched portions of Ge-doped regions1400can be substantially equal to width1610. In some embodiments, due to the implant process variation and subsequent annealing process, Ge implants may diffuse beyond the semiconductor layer/isolation region interface into isolation region200. However, the diffusion length can be limited by the annealing temperature of the annealing process. Therefore, in some embodiments, the width of the un-etched Ge-doped regions1400can be larger than width1610(e.g., within about 1 nm or less). Regardless, the extension of Ge-doped regions1400into isolation regions200is not a limitation for fabrication method1200. In referring toFIG.12and operation1260of fabrication method1200, a SiGe stack can be epitaxially grown in each opening1700. In some embodiments, each epitaxially grown SiGe stack features a substantially horizontal top surface (e.g., slope-free) and uniform thickness. In referring toFIG.18, SiGe stack1800can have a top surface1800Tand a bottom surface1800Bthat are substantially parallel to horizontal plane x-y. In some embodiments, the x-y plane is parallel to a top surface of a substrate, which is not shown inFIG.18for simplicity. According to some embodiments, the resulting top surface1800Tcan be slope-free because the SiGe nanostructure in semiconductor layer210can act as a “reduced” lattice mismatch “growth surface” for SiGe stack1800. As a result, SiGe nanostructures in semiconductor layer210can suppress the formation of facets in SiGe stack1800that are responsible for the formation of a sloped top surface in SiGe stack1800. In some embodiments, contact openings710can be formed in an interlayer dielectric (ILD) layer720over SiGe stacks700, as shown inFIG.18. In some embodiments, contact openings710are formed after the replacement of gate structure220with a metal gate structure (not shown inFIG.18). Contact openings710are formed by etching ILD layer720(e.g., with a dry etching process) until the top surface of each SiGe stack1800is exposed as shown inFIG.18. Since top surfaces1800Tof SiGe stacks1800are grown parallel to the horizontal plane x-y, the etching process window for contact openings710can improve as discussed above. In some embodiments,FIG.19is a top view ofFIG.18. The embodiments described herein are not limited to the exemplary layout ofFIG.19and additional layouts with different gate structure and semiconductor layer arrangements are within the spirit and scope of this disclosure. For example,FIGS.20and21provide additional layouts, where additional gate structures and semiconductor layers are provided in different arrangements, according to some embodiments. In each of these arrangements shown inFIGS.20and21, Ge-doped regions1400are interposed between respective SiGe stacks1800and isolation region200. The present disclosure is directed to a method that mitigates, or eliminates, the formation of facets in source/drain SiGe epitaxial layers. As a result, the SiGe epitaxial layers can be grown with a horizontal top surface across the source/drain region to improve the etching process window during the contact opening formation. In some embodiments, this can be accomplished by forming a SiGe nanostructure at the interface of the semiconductor/isolation region. For example, the SiGe nanostructure can be either formed in the semiconductor layer or in the isolation region. In some embodiments, the SiGe nanostructure can be used as a growth surface with reduced lattice mismatch for the SiGe epitaxial layers in the source/drain region. In some embodiments, the Ge implant dose can range from about 1015atoms/cm2to about 1016atoms/cm2and the resulting Ge implanted area can have a width between about 5 nm and about 25 nm. Further, the distance between a gate structure and the SiGe nanostructures can be equal to or greater than about 40 nm. In some embodiments, a semiconductor structure includes a semiconductor layer over a substrate; an isolation region abutting the semiconductor layer, wherein the isolation region comprises a silicon germanium (SiGe) structure; and an epitaxial stack, in the semiconductor layer, comprising at least one common sidewall with the SiGe structure. In some embodiments, a semiconductor structure includes a semiconductor layer over a substrate, wherein the semiconductor layer comprises a silicon germanium (SiGe) structure; an epitaxial stack partially disposed in the semiconductor layer and in contact with the SiGe structure; and an isolation region surrounding the semiconductor layer, wherein the SiGe structure is interposed between the isolation region and the epitaxial stack. In some embodiments, a method includes forming an isolation region around a semiconductor layer, forming a gate structure partially over the semiconductor layer and the isolation region; disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer; doping, with Ge, exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region; etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings includes at least one common sidewall with the Ge-doped regions in the isolation region; and growing a silicon germanium (SiGe) epitaxial stack in the openings. It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way. The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,394 |
11942548 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It is also noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a P-type metal-oxide-semiconductor device or an N-type metal-oxide-semiconductor multi-gate device. Specific examples may be presented and referred to herein as FINFET, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanowire) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. Illustrated inFIG.1is a method100of semiconductor fabrication including fabrication of multi-gate devices. As used herein, the term “multi-gate device” is used to describe a device (e.g., a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a “nanowire,” which as used herein includes channel regions of various geometries (e.g., cylindrical, bar-shaped) and various dimensions. FIGS.2-11,12A, and13-16are isometric views of an embodiment of a semiconductor device200according to various stages of the method100ofFIG.1.FIGS.12B,17, and18are cross-section views, corresponding to respective isometric views listed above, of an embodiment of the semiconductor device200according to various stages of the method100ofFIG.1. As with the other method embodiments and exemplary devices discussed herein, it is understood that parts of the semiconductor device200may be fabricated by a CMOS technology process flow, and thus some processes are only briefly described herein. Further, the exemplary semiconductor devices may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. In some embodiments, the exemplary devices include a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of method100, including any descriptions given with reference toFIGS.2-19, as with the remainder of the method and exemplary figures provided in this disclosure, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow. The method100begins at block102where a substrate is provided. Referring to the example ofFIG.2, in an embodiment of block102, a substrate202is provided. In some embodiments, the substrate202may be a semiconductor substrate such as a silicon substrate. The substrate202may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate202may include various doping configurations depending on design requirements as is known in the art. For example, different doping profiles (e.g., n wells, p wells) may be formed on the substrate202in regions designed for different device types (e.g., n-type field effect transistors (NFET), p-type field effect transistors (PFET)). The suitable doping may include ion implantation of dopants and/or diffusion processes. The substrate202typically has isolation features (e.g., shallow trench isolation (STI) features) interposing the regions providing different device types. The substrate202may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate202may include a compound semiconductor and/or an alloy semiconductor. Further, the substrate202may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features. In an embodiment of the method100, in block102, an anti-punch through (APT) implant is performed. The APT implant may be performed in a region underlying the channel region of a device for example, to prevent punch-through or unwanted diffusion. In some embodiments, a first photolithography (photo) step is performed to pattern a P-type APT region and a second photo step is performed to pattern an N-type APT region. For example, in some embodiments, performing the first photo step may include forming a photoresist layer (resist) over the substrate202, exposing the resist to a pattern (e.g., P-type APT implant mask), performing post-exposure bake processes, and developing the resist to form a patterned resist layer. By way of example, a P-type dopant implanted via the ion implantation process to form the P-type APT region may include boron, aluminum, gallium, indium, or other P-type acceptor material. Thereafter, in some embodiments, the second photo step may be performed, where the second photo step may include forming a resist layer over the substrate202, exposing the resist to a pattern (e.g., N-type APT implant mask), performing post-exposure bake processes, and developing the resist to form a patterned resist layer. By way of example, an N-type dopant implanted via the ion implantation process into the N-type APT region may include arsenic, phosphorous, antimony, or other N-type donor material. Additionally, in various embodiments, an APT implant may have a high dopant concentration, for example, of between about 1×1018cm−3and 1×1019cm−3. In some embodiments, such a high APT dopant concentration may be advantageously used, as described below, because of the presence of a subsequently formed isolation layer over the APT-implanted substrate, which can serve as a dopant diffusion barrier. The APT implant is illustrated inFIG.2as an implant204. Returning toFIG.1, the method100then proceeds to block104where one or more epitaxial layers are grown on the substrate. With reference to the example ofFIG.3, in an embodiment of block104, an epitaxial stack302is formed over the APT-implanted substrate202. The epitaxial stack302includes epitaxial layers304of a first composition interposed by epitaxial layers306of a second composition. The first and second composition can be different. In an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon. However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates. For example, in various embodiments, the epitaxial layer304has a first oxidation rate, and the epitaxial layer306has a second oxidation rate less than the first oxidation rate. In some embodiments, the epitaxial layer304includes SiGe and where the epitaxial layer306includes Si, the Si oxidation rate of the epitaxial layer306is less than the SiGe oxidation rate of the epitaxial layer304. During a subsequent oxidation process, as discussed below, the portions the epitaxial layer304may be fully oxidized, while only the epitaxial layer306may be non-oxidized, or in some embodiments oxidized only slightly (e.g., sidewalls). It is noted that the bottom-most epitaxial layer is denoted304A for ease of reference in later process steps. In embodiments however, epitaxial layer304A is substantially similar material to the epitaxial layers304formed over the epitaxial layer304A. In an embodiment, the epitaxial layer304A is SiGe and the epitaxial layers304may also be SiGe. In other embodiments, the epitaxial layer304A has a different composition that epitaxial layers304and/or epitaxial layers306. The thickness of the epitaxial layer304A may be greater than that of the overlying epitaxial layers304. The epitaxial layers306or portions thereof may form a channel region of the multi-gate device200. For example, the epitaxial layers306may be referred to as “nanowires” used to form a channel region of a multi-gate device200such as a GAA device. These “nanowires” are also used to form a portions of the source/drain features of the multi-gate device200as discussed below. Again, as the term is used herein, “nanowires” refers to semiconductor layers that are cylindrical in shape as well as other configurations such as, bar-shaped. The use of the epitaxial layers306to define a channel or channels of a device is further discussed below. It is noted that three (3) layers of each of epitaxial layers304(including304A) and306are illustrated inFIG.3, this is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack302; the number of layers depending on the desired number of channels regions for the device200. In some embodiments, the number of epitaxial layers306is between 2 and 10. In some embodiments, the epitaxial layer304has a thickness range of about 2-6 nanometers (nm). The epitaxial layers304(provided above the layer304A) may be substantially uniform in thickness. In some embodiments, the epitaxial layer304A has a thickness of approximately 8 to 15 nm. In some embodiments, the epitaxial layer306has a thickness range of about 6-12 nm. In some embodiments, the epitaxial layers306of the stack are substantially uniform in thickness. As described in more detail below, the epitaxial layer306may serve as channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations. The epitaxial layer304may serve to define a gap distance between adjacent channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations. By way of example, epitaxial growth of the layers of the stack302may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the layers306include the same material as the substrate202. In some embodiments, the epitaxially grown layers304,306include a different material than the substrate202. As stated above, in at least some examples, the epitaxial layer304includes an epitaxially grown silicon germanium (SiGe) layer and the epitaxial layer306includes an epitaxially grown silicon (Si) layer. In some embodiments, epitaxial layer304A is also SiGe. Alternatively, in some embodiments, either of the epitaxial layers304,306may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers304,306may be chosen based on providing differing oxidation, etch selectivity properties. In various embodiments, the epitaxial layers304,306are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed during the epitaxial growth process. As also shown in the example ofFIG.3, a hard mask (HM) layer308may be formed over the epitaxial stack302. In some embodiments, the HM layer308includes an oxide layer (e.g., a pad oxide layer that may include SiO2) and nitride layer (e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer. In some examples, the HM layer308includes thermally grown oxide, CVD-deposited oxide, and/or ALD-deposited oxide. In some embodiments, the HM layer308includes a nitride layer deposited by CVD or other suitable technique. The HM layer308may be used to protect portions of the substrate202and/or epitaxial stack302and/or used to define a pattern (e.g., fin elements) illustrated below. The method100then proceeds to block106where fin elements are patterned and formed. With reference to the example ofFIG.4, in an embodiment of block106, a plurality of fin elements402extending from the substrate202are formed. In various embodiments, each of the fin elements402includes a substrate portion formed from the substrate202, portions of each of the epitaxial layers of the epitaxial stack including epitaxial layers304/304A and306, and an HM layer portion from the HM layer308. The fins402may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the substrate202(e.g., over the HM layer308ofFIG.3), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate202, and layers formed thereupon, while an etch process forms trenches404in unprotected regions through the HM layer306, through the epitaxial stack302, and into the substrate202, thereby leaving the plurality of extending fins402. The trenches404may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable processes. Numerous other embodiments of methods to form the fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack302in the form of the fin402. In some embodiments, forming the fins402may include a trim process to decrease the width of the fins402. The trim process may include wet or dry etching processes. The method100then proceeds to block108where an oxidation process is performed to form an isolation region within the fin element(s). With reference to the example ofFIG.5, in an embodiment of block108, the device200is exposed to an oxidation process that fully oxidizes the epitaxial layer portion304A of each of the plurality of fin elements402. The epitaxial layer portion304A is transformed into an oxidized layer502, which provides an isolation region/layer. In some embodiments, the oxidized layer502has a thickness range of about 5 to about 25 nanometers (nm). In an embodiment, the oxidized layer502may include an oxide of silicon germanium (SiGeOx). The oxidation process of block108may include forming and patterning various masking layers such that the oxidation is controlled to the epitaxial layer304A. In other embodiments, the oxidation process is a selective oxidation due to the composition of epitaxial layer304A. In some examples, the oxidation process may be performed by exposing the device200to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the device200is exposed to a wet oxidation process using water vapor or steam as the oxidant, at a pressure of about 1 ATM, within a temperature range of about 400-600° C., and for a time from about 0.5-2 hours. It is noted that the oxidation process conditions provided herein are merely exemplary, and are not meant to be limiting. As described above, in some embodiments, the first epitaxial layer portion304A may include a material having a first oxidation rate, and the second epitaxial layer portion306may include a material having a second oxidation rate less than the first oxidation rate. By way of example, in embodiments where the first epitaxial layer portion304A includes SiGe, and where the second epitaxial layer portion306includes Si, the faster SiGe oxidation rate (i.e., as compared to Si) ensures that the SiGe layer (i.e., the epitaxial layer portion304A) becomes fully oxidized while minimizing or eliminating the oxidization of other epitaxial layers304. It will be understood that any of the plurality of materials discussed above may be selected for each of the first and second epitaxial layer portions that provide different suitable oxidation rates. The resultant oxidized layer502of each of the fin elements402can serve as a diffusion barrier to APT dopants previously implanted into the substrate202, and which may be present in the substrate202directly below the oxidized layer502. Thus, in various embodiments, the oxidized layer502serves to prevent APT dopants within the substrate portion202from diffusing for example, into the overlying epitaxial layer(s)306, which can serve as a channel region for a subsequently formed multi-gate device. In other embodiments, the oxidized layer502is omitted. The method100then proceeds to block110where shallow trench isolation (STI) features are formed between the fin elements. With reference to the example ofFIG.6, STI features602are disposed between the fins402. By way of example, in some embodiments, a dielectric layer is first deposited over the substrate202, filling the trenches404with the dielectric material. In some embodiments, the dielectric layer may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, after deposition of the dielectric layer, the device200may be annealed, for example, to improve the quality of the dielectric layer. In some embodiments, the dielectric layer (and subsequently formed STI features602) may include a multi-layer structure, for example, having one or more liner layers. In forming the STI features, after deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process. The CMP process may planarize the top surface thereby forming STI features602. As illustrated inFIG.6, in some embodiments, the CMP process used to planarize the top surface of the device200and form the STI features602may also serve to remove the HM layer308from each of the plurality of fin elements402. In some embodiments, removal of the HM layer308may alternately be performed by using a suitable etching process (e.g., dry or wet etching). Continuing with block110of the method100, the STI features interposing the fin elements are recessed. Referring to the example ofFIG.7, the STI features602are recessed providing the fins402extending above the STI features602. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height ‘H’ of the exposed upper portion of the fin elements402. The height ‘H’ exposes each of the layers of the epitaxy stack302. WhileFIG.7illustrates the recess of the STI feature602being substantially coplanar with a top surface of the isolation region502, in other embodiments this may not be required. The method100then proceeds to block112where sacrificial layers/features are formed. In some embodiments, a dummy dielectric layer and/or a dummy gate structure is formed. For example, block112may include a dummy oxide deposition followed by a dummy gate structure. While the present discussion is directed to a replacement gate process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible. With reference toFIG.8, a dielectric layer802is formed on the substrate202. In some embodiments, the dielectric layer802may include SiO2, silicon nitride, a high-K dielectric material or other suitable material. In various examples, the dielectric layer802may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. By way of example, the dielectric layer802may be used to prevent damage to the fin elements402by subsequent processing (e.g., subsequent formation of the dummy gate stack). Additional dummy (e.g., sacrificial) layers including those comprising the dummy gate structure902ofFIG.9may also be deposited as discussed below. Referring now to the example ofFIG.9, in a further embodiment of block112, fabrication and processing of the dummy gate stack is performed. Using the example ofFIG.9, a gate stack902is formed. In an embodiment, the gate stack902is a dummy (sacrificial) gate stack that is subsequently removed as discussed with reference to block122of the method100. (However, as referenced above, in some embodiments of the method100, the gate stack902or portions thereof may be maintained, for example, may be a high-K/metal gate stack. In such an embodiment, certain steps of the method100would be performed prior to the formation of the high-K metal gate stack such as step122.) Thus, in some embodiments using a gate-last process, the gate stack902is a dummy gate stack and will be replaced by the final gate stack at a subsequent processing stage of the device200. In particular, the gate stack902may be replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as discussed below. In some embodiments, the gate stack902is formed over the substrate202and is at least partially disposed over the fin elements402. The portion of the fin elements402underlying the gate stack902may be referred to as the channel region. The gate stack902may also define a source/drain region of the fin elements402, for example, the regions of the fin and epitaxial stack302adjacent and on opposing sides of the channel region. In some embodiments, the gate stack902includes the dielectric layer802, an electrode layer904, and a hard mask906which may include multiple layers908and910(e.g., an oxide layer908and a nitride layer910). In some embodiments, the dielectric layer802is not included in the gate stack902, for example, being removed prior to the deposition of the gate stack902. In some embodiments, an additional dummy gate dielectric layer is included in the gate stack in addition or in lieu of dielectric layer802. In some embodiments, the gate stack902is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. Exemplary layer deposition processes includes CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In forming the gate stack for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. As indicated above, the gate stack902may include an additional gate dielectric layer. For example, the gate stack902may include silicon oxide. Alternatively or additionally, the gate dielectric layer of the gate stack902may include silicon nitride, a high-K dielectric material or other suitable material. In some embodiments, the electrode layer904of the gate stack902may include polycrystalline silicon (polysilicon). In some embodiments, the hard mask layer906includes an oxide layer908such as a pad oxide layer that may include SiO2. In some embodiments, hard mask layer906includes the nitride layer910such as a pad nitride layer that may include Si3N4, silicon oxynitride or alternatively include silicon carbide. As illustrated inFIG.9, in some embodiments, after formation of the dummy gate902, the dielectric layer802is removed from the exposed regions of the substrate including fins402not covered by the gate902. The method100then proceeds to block114where select epitaxial layers of the epitaxy stack are removed from the source/drain region of the fin element(s) (e.g., the region of the fin adjacent the channel region underlying the gate stack). As illustrated inFIG.10, the epitaxial layers304have been removed from the substrate202in the source/drain region of the fins402.FIG.10illustrates gaps1002in the place of the epitaxial layers304(FIG.9). The gaps1002may be filled with the ambient environment (e.g., air, N2). In an embodiment, the epitaxial layers304are removed by a selective wet etching process. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by a SiGeOx removal. For example, the oxidation may be provided by O3clean and then SiGeOx remove by an etchant such as NH4OH. In an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon allowing for the selective removal of the epitaxial layers304. The method100then proceeds to block116where a spacer layer is deposited on the substrate. The spacer layer may be a conformal dielectric layer formed on the substrate. The spacer layer may form spacer elements on the sidewalls of the gate structure. The spacer layer may also fill the gaps provided by the removal of the epitaxial layers described in block114above. Referring toFIG.11, the spacer layer1102is disposed on the substrate202including filling the gaps (gaps1002ofFIG.10) between epitaxial layers in the source/drain region of the fin elements402. The spacer layer1102may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer layer1102includes multiple layers, such as main spacer walls, liner layers, and the like. By way of example, the spacer layer1102may be formed by depositing a dielectric material over the gate stack902using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In certain embodiments, the deposition may be followed by an etching back (e.g., anisotropically) the dielectric material. In some embodiments, prior to forming the sidewall spacers1102, an ion implantation process may be performed to form lightly-doped drain (LDD) features within the semiconductor device200. In some embodiments, with reference to the example ofFIGS.12A and12B, after formation of the spacer layer1102, the spacer layer1102may be etched-back to expose portions of the fin elements402adjacent to and not covered by the gate structure902(e.g., source/drain regions). The spacer layer material may remain on the sidewalls of the gate structure902forming spacer elements. In some embodiments, etching-back of the spacer layer1102may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. While the spacer layer1102may be removed from a top surface of the exposed epitaxial stack302and the lateral surfaces of the exposed epitaxial stack302, as illustrated inFIG.12A/12B, the spacer layer1102remains interposing the epitaxial layers306of the epitaxial stack302in the source/drain region.FIG.12Billustrates the partial cross-section corresponding toFIG.12A. The spacer layer1102between the epitaxial layers306may be between approximately 2-6 nm in thickness. The method100then proceeds to block118where source/drain features are formed. The source/drain features may be formed by performing an epitaxial growth process that provides an epitaxy material cladding the portions of the epitaxy layers remaining in the fins' source/drain regions. Referring to the example ofFIG.13, source/drain features1302are formed on the substrate202in/on the fin402adjacent to and associated with the gate stack902. The source/drain features1302include material1302A formed by epitaxially growing a semiconductor material on the exposed epitaxial layer306. In other words, the material1302A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. In various embodiments, the grown semiconductor material1302A may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. In some embodiments, the material1302A may be in-situ doped during the epi process. For example, in some embodiments, epitaxially grown material1302A may be doped with boron. In some embodiments, epitaxially grown material1302A may be doped with carbon to form Si:C source/drain features, phosphorous to form Si:P source/drain features, or both carbon and phosphorous to form SiCP source/drain features. In an embodiment, the epitaxial layer602is silicon and the epitaxially grown material1302A also is silicon. In some embodiments, the layers602and1302A may comprise a similar material, but be differently doped. In other embodiments, the epitaxy layer602includes a first semiconductor material, the epitaxially grown material1302A includes a second semiconductor different than the first semiconductor material. In some embodiments, the epitaxially grown material1302A is not in-situ doped, and, for example, instead an implantation process is performed to dope the epitaxially grown material1302A. As described above, the isolation layer502which remains present beneath the gate stack902, can block potential unwanted diffusion. Thus, the source/drain features1302associated with the gate902include the epitaxy material306and/or the epitaxially grown material1302A. It is noted that these features may be formed without recessing the fin402. Dielectric material from the spacer layer1102interposes the epitaxy material306. Each of the epitaxial material306(e.g., nanowires) extends into the channel region, thereby forming a multi-channel, multi-source/drain region device. The spacer layer1102between epitaxy layers306in the source/drain region may be approximately 2 to 6 nm in thickness. The method100then proceeds to block120where an inter-layer dielectric (ILD) layer is formed. In certain embodiments, after forming the ILD layer the dummy gate stack is removed (as discussed below). Referring to the example ofFIG.14, in an embodiment of block120, an ILD layer1402is formed over the substrate202. In some embodiments, a contact etch stop layer (CESL) is also formed over the substrate202prior to forming the ILD layer1402. In some examples, the CESL includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. The CESL may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. A CESL layer1702is illustrated inFIG.17. In some embodiments, the CESL layer1702is deposited after the epitaxially grown material1302A and prior to the formation of the ILD layer1402. In some embodiments, the ILD layer1402includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer1402may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer1402, the semiconductor device200may be subject to a high thermal budget process to anneal the ILD layer. As described above, the insulating layer502can block some potential diffusion of APT dopants from within the substrate regions into the device channel region during such high thermal budget processing. In some examples, after depositing the ILD (and/or CESL), a planarization process may be performed to expose a top surface of the gate stack902. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer1402(and CESL layer, if present) overlying the gate stack902and planarizes a top surface of the semiconductor device200. In addition, the CMP process may remove the hard mask906overlying the gate stack902to expose the electrode layer904, such as a polysilicon electrode layer. Thereafter, in some embodiments, the remaining previously formed gate stack902features (e.g., the dielectric layer802and the electrode layer904) may be removed from the substrate. In some embodiments, the electrode layer904may be removed while the dielectric layer (e.g.,802) is not removed. The removal of the electrode layer904(or the electrode layer904and dielectric layer802) from the gate stack902results in a trench1404illustrated inFIG.14. A final gate structure (e.g., including a high-K dielectric layer and metal gate electrode) may be subsequently formed in the trench1404, as described below. The removal of the dummy gate stack features may be performed using a selective etch process such as a selective wet etch, a selective dry etch, or a combination thereof. The method100then proceeds to block122where a selective removal of the epitaxial layer(s) in the channel region of the device is provided. In embodiments, the selected epitaxial layer(s) are removed in the of the fin elements within the trench provided by the removal of the dummy gate electrode (e.g., the region of the fin on and over which the gate structure will be formed, or the channel region). Referring to the example ofFIG.15, the epitaxy layers304are removed from the channel region of the substrate202and within the trench1404. In some embodiments, the epitaxial layers304are removed by a selective wet etching process. In some embodiments, the selective wet etching includes HF. In an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon allowing for the selective removal of the SiGe epitaxial layers304. It is noted that during the interim processing stage of block122(e.g.,FIG.15), gaps1502are provided between the adjacent nanowires in the channel region (e.g., gaps1502between epitaxy layers306). The gaps1502may be filled with the ambient environment conditions (e.g., air, nitrogen, etc). It is noted that as illustrated in the accompanying figures the epitaxy layers306(e.g., nanowires) have a substantially rounded shape (e.g., cylindrical). The epitaxy layers306(e.g., nanowires) have a substantially bar-shaped shape in the source drain region. In some embodiments, this difference in the shape of the epitaxy layer306is due to the quantity and nature of the processing in each region. For example, in the channel region the dummy oxide removal and/or high-k dielectric deposition processes may provide for rounded shape. In some embodiments, the shape may be substantially similar in each region. The method100then proceeds to block124where a gate structure is formed. The gate structure may be the gate of a multi-gate transistor. The final gate structure may be a high-K/metal gate stack, however other compositions are possible. In some embodiments, the gate structure forms the gate associated with the multi-channels provided by the plurality of nanowires (now having gaps there between) in the channel region. Referring to the example ofFIG.16, in an embodiment of block124, a high-K/metal gate stack1602is formed within the trench1404of the device200. In various embodiments, the high-K/metal gate stack1602includes an interfacial layer, a high-K gate dielectric layer1604formed over the interfacial layer, and/or a metal layer1606formed over the high-K gate dielectric layer1604. High-K gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The metal layer used within high-K/metal gate stack may include a metal, metal alloy, or metal silicide. Additionally, the formation of the high-K/metal gate stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials and thereby planarize a top surface of the semiconductor device200. In some embodiments, the interfacial layer of the gate stack1602may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The gate dielectric layer1604of the gate stack1602may include a high-K dielectric layer such as hafnium oxide (HfO2). Alternatively, the gate dielectric layer1604of the gate stack1602may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The high-K gate dielectric layer1604may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. The gate dielectric layer1604of the gate stack1602is illustrated inFIGS.16,17,18and19. The metal layer of the high-K/metal gate stack1602may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the metal layer of gate stack1602may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. In various embodiments, the metal layer of the gate stack1602may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the metal layer of the gate stack1602may be formed separately for N-FET and P-FET transistors which may use different metal layers. In various embodiments, a CMP process may be performed to remove excessive metal from the metal layer of the gate stack1602, and thereby provide a substantially planar top surface of the metal layer of the gate stack1602. The metal layer1606of the gate stack1602is illustrated inFIGS.16,17, and18. In addition, the metal layer may provide an N-type or P-type work function, may serve as a transistor (e.g., FINFET) gate electrode, and in at least some embodiments, the metal layer of the gate stack1602may include a polysilicon layer. The device200may perform as a gate-all-around (GAA) device, the gate structure1602being formed on multiple sides of the nanowire (epitaxy layer306). The multi-gate device200is illustrated in isometric view inFIG.16and corresponding cross-sectional views inFIG.17(cross-sectional cut A),FIG.18(cross-sectional cut C through the gate structure1602),FIG.19(cross-sectional cut B through the source/drain). The ILD layer1402is removed for ease of reference inFIGS.17,18, and18. As illustrated inFIGS.17and18, the gate dielectric layer1604is disposed below the epitaxial layer306(e.g., nanowire). However, in other embodiments, other portions of the gate structure1602(e.g., gate electrode1606) may also be disposed under the epitaxy layer306. In some embodiments, the device200may be a FINFET device having a gate formed on at least two-sides of the channel region (e.g., top and two sidewalls) and/or have other configurations known in the art. The device200inFIG.19illustrates the source/drain feature1302having the epitaxially grown cladding layer1302A disposed on multiple surfaces of the epitaxy layer306(e.g., nanowire), while dielectric1102is disposed between epitaxy layers306. The semiconductor device200may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method100. Illustrated inFIG.20is a method2000of semiconductor fabrication including fabrication of multi-gate devices. The method2000may be substantially similar to the method100ofFIG.1, except with some differences highlighted below. However, the description of similar processes provide above with reference to the method100apply equally herein unless specifically noted otherwise. FIGS.21-29,30A, and31-34are isometric views of an embodiment of a semiconductor device2100according to various stages of the method2000ofFIG.20.FIGS.30B,35,36, and37are cross-section views, corresponding to respective isometric views listed above, of an embodiment of the semiconductor device2100according to various stages of the method2000ofFIG.20. The method2000begins at block2002where a substrate is provided. Block2002may be substantially similar to block102of the method100described above. Referring to the example ofFIG.21, in an embodiment of block102, a substrate202is provided. The substrate202may be substantially similar to as discussed above with reference toFIG.2. Also as described above with reference toFIGS.1and2, an APT implant204may be performed. Returning toFIG.20, the method2000then proceeds to block104where one or more epitaxial layers are grown on the substrate. With reference to the example ofFIG.22, in an embodiment of block104, an epitaxial stack2202is formed over the APT-implanted substrate202. The epitaxial stack2202includes epitaxial layers304of a first composition interposed by epitaxial layers306of a second composition. The first and second composition can be different. In an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon. However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch rates. In various embodiments, the epitaxial layer304has a first oxidation rate, and the epitaxial layer306has a second oxidation rate less than the first oxidation rate. For example, in some embodiments, the epitaxial layer304is SiGe and the epitaxial layer306is Si, the Si oxidation rate being is less than the SiGe oxidation rate. During a subsequent oxidation process, as discussed below, the portions the epitaxial layer304may be fully oxidized, while only the epitaxial layer306may be non-oxidized, or in some embodiments oxidized only slightly (e.g., sidewalls). Thus, the epitaxial stack2202(and epitaxial layers304,306) is similar to that described above with reference to block104of the method100and epitaxial stack302ofFIG.3, except that the epitaxial stack2202does not include an epitaxial layer that is subsequently formed into an isolation region (compare epitaxial layer304A). As such, each layer304of the epitaxial stack2202may be substantially the same thickness (e.g., within 10%). In an embodiment, each epitaxial layer304of the epitaxial stack2202has a thickness of about 2-6 nm. In an embodiment, each epitaxial layer306of the epitaxial stack2202has a thickness of about 6 to 12 nm. As described in more detail below, the epitaxial layer306may serve as channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations. The epitaxial layer304may serve to define a gap distance between adjacent channel region(s) for a subsequently-formed multi-gate device and its thickness chosen based on device performance considerations. It is noted that three (3) layers of each of epitaxial layers304and306in the epitaxial stack2202are illustrated inFIG.22, this is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack2202; the number of layers depending on the desired number of channels of for the device2100. In some embodiments, the number of epitaxial layers306is between 2 and 10. As also shown in the example ofFIG.22, a hard mask (HM) layer308may be formed over the epitaxial stack2202, substantially similar to as discussed above with reference to the HM layer308ofFIG.3. The method2000then proceeds to block2006where fin elements are formed. With reference to the example ofFIG.23, in an embodiment of block2006, a plurality of fin elements402extending from the substrate202are formed. In various embodiments, each of the fin elements402includes a substrate portion formed from the substrate202, portions of each of the epitaxial layers of the epitaxial stack302including epitaxial layers304and306, and an HM layer portion from the HM layer308. The fin elements402may be formed substantially similar to as discussed above with reference to block106of the method100and/orFIG.4. The method2000then proceeds to block2008where shallow trench isolation (STI) features are formed between the fin elements. With reference to the example ofFIGS.24and25, STI features602are disposed between the fins402and subsequently recessed. The STI features602may be substantially similar to as discussed above with reference to block110of the method100and/or the example ofFIGS.6and7. Referring to the example ofFIG.25, the STI features602are recessed providing the fins402extending above the STI features602. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height ‘H’ of the exposed upper portion of the fin elements402. The height ‘H’ exposes layers of the epitaxy stack302. The method2000then proceeds to block2010where sacrificial layers including a dummy gate structure are formed. Block2010may be substantially similar to block112of the method100. With reference toFIG.26andFIG.27, a dielectric layer802and a gate structure902(e.g., dummy gate structure) are formed on the device2100. The dielectric layer802and/or the gate structure902may be substantially similar to as discussed above including with reference to block112andFIGS.8and9. The method2000then proceeds to block2012where select epitaxial layers of the epitaxy stack are removed from the fin region adjacent the gate stack, also referred to as the source/drain region of the fin as it is the portion of the fin that will later be formed into the source/drain feature associated with the multi-gate device2100. As illustrated inFIG.28, the epitaxial layers304have been removed from the substrate202in the source/drain region of the fins402providing gaps1002in the place of the epitaxial layers304(FIG.27). The gaps1002may be filled with the ambient environment (e.g., air, N2). Block2012and the gaps1002may be substantially similar to block114and gaps1002described above with reference toFIGS.1and10respectively. The method2000then proceeds to block2014where a spacer layer is deposited on the substrate. Block2014may be substantially similar to block116of the method100, described above with reference toFIGS.1and11. The spacer layer may be any dielectric layer including dielectric materials including silicon as discussed above. ExemplaryFIG.29illustrates the spacer layer1102disposed on the fins402including filling in the gaps1002. In some embodiments, with reference to the example ofFIGS.30A and30B, after formation of the spacer layer1102, the spacer layer1102may be etched-back to expose portions of the fin elements402adjacent to and not covered by the gate structure902(e.g., source/drain regions). ExemplaryFIGS.30A and30Bmay be substantially similar to as discussed above with reference toFIGS.12A and12B. As discussed above, while the spacer layer1102may be removed from a top surface of the epitaxial stack2202and the lateral surfaces of the epitaxial stack2202, as illustrated inFIG.30A/30B, the spacer layer1102remains interposing the epitaxial layers306of the epitaxial stack302in the source/drain region.FIG.30Billustrates the partial cross-section corresponding toFIG.30A. The spacer layer1102between the epitaxial layers306may be between approximately 2-6 nm in thickness. In addition, as illustrated inFIG.30A, after the spacer layer1102is etched-back the STI features602may be slightly recessed further such that a top surface of the STI features602is below, or substantially aligned with a bottom surface of, the bottommost epitaxial layer304(e.g., the bottommost SiGe layer). The method2000then proceeds to block2016where source/drain features are formed. Block2016may be substantially similar to block118of the method100, described above with reference toFIG.1. As discussed above, the source/drain features may be formed by performing an epitaxial growth process that provides an epitaxy material cladding the exposed portions of the epitaxy layers in the fins' source/drain regions. For example, the epitaxy material may be cladding the epitaxy layers or nanowires of the source/drain region except where the dielectric spacer material is disposed between the epitaxy layers (or nanowires). Referring to the example ofFIG.31, source/drain features1302are formed on the substrate202on the fin402adjacent the gate stack902. The source/drain features1302include material1302A formed by epitaxially growing a semiconductor material layer on the region of the epitaxial layer306adjacent the gate structure902. In other words, the material1302A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. The source/drain features1302including epitaxial material1302A may be substantially similar to as discussed above with reference toFIG.13. The method2000then proceeds to block2018where an inter-layer dielectric (ILD) layer is formed. In some embodiments, a CESL layer may also be formed. In some embodiments, the gate structure may subsequently be removed from the substrate. Block2018may be substantially similar to block120of the method100, discussed above with reference toFIG.1and the example ofFIG.14. Referring to the example ofFIG.32, an ILD layer1402is formed over the substrate202. As illustrated inFIG.32, the removal of the electrode layer904(or the electrode layer904and dielectric layer802) from the gate stack902results in a trench1404. WhileFIG.32illustrates an interim process wherein the dielectric layer802is disposed in the trench1404, in other embodiments, the dielectric layer802is also removed. The method2000then proceeds to block2020where a selective removal of the epitaxial layer(s) in the channel region of the device is provided. In embodiments, the selected epitaxial layer(s) are removed in the region of the fin on and over which the gate structure will be formed. Block2020may be substantially similar to block122of the method100ofFIG.1and/or the example ofFIG.15. Referring to the example ofFIG.33, the epitaxy layers304are removed from the channel region of the substrate202within the trench1404. As discussed above, in an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon allowing for the selective removal of the SiGe epitaxial layers304. It is noted that during block2020(e.g.,FIG.33), gaps1502are provided between the adjacent nanowires in the channel region (e.g., gaps1502between epitaxy layers306). The method2000then proceeds to block2022where a gate structure is formed. Block2022may be substantially similar to block124of the method100, described above with reference toFIG.1and/or the examples of16,17,18, and19. Referring to the example ofFIG.34, in an embodiment of block2022, a high-K/metal gate stack1602is formed within the trench1404of the device2100. The gate stack1602may be substantially similar to as discussed above. Thus, the device2100may perform as a multi-gate device including a gate-all-around (GAA) device, the gate structure1602being formed on multiple sides of the nanowire (epitaxy layer304). The multi-gate device2100is illustrated in isometric view inFIG.34and corresponding cross-sectional views inFIG.35(cross-sectional cut A),FIG.36(cross-sectional cut C through the gate structure1602),FIG.37(cross-sectional cut B through the source/drain). The ILD layer1402is removed for ease of reference inFIGS.35,36, and37. As illustrated inFIGS.35and36, the gate dielectric layer1604is disposed below the epitaxial layer306(e.g., nanowire) in the channel region. However, in other embodiments, other portions of the gate structure1602(e.g., gate electrode1606) may also be disposed under the epitaxy layer306. In some embodiments, the device2100may be a FINFET device having a gate formed on at least two-sides of the channel region (e.g., top and two sidewalls) and/or have other configurations known in the art. The device2100differs from the device200, for example, in the omission of an isolation region (see isolation layer502) present in device200. This may provide advantages in production steps and timing. In some embodiments, the performance considerations of the multi-gate device do not necessitate isolation layers. Also as described above with reference to the method100and the exemplary device200further processing may be performed with reference to the method2000and the device2100. Illustrated inFIG.38is a method3800of semiconductor fabrication including fabrication of multi-gate devices. The method3800may be substantially similar to many aspects of the method100ofFIG.1and/or the method2000ofFIG.20, except with some differences highlighted below. Thus, the description of similar processes provided above with reference to the method100and/or the method2000apply equally herein unless noted otherwise.FIG.38also illustrates concurrent stages of fabrication of both types of devices, n-type and p-type transistors, which may be formed on the same substrate. FIGS.21,22,23,24,25,26, and27are isometric views of an embodiment of the semiconductor device2100that also apply to various stages of the method3800. (These figures can be applied to processing of both types of devices concurrently and/or substantially similarly.) Following the stage illustrated inFIG.27,FIGS.39A,39B,40A,40B,41A,41B,42A,42B,43A,43B,44A,44B,45A,45B,46A,46B,47A, and47B, corresponds to various stages of the method3800ofFIG.38.FIGS.48A,48B,49A,49B,50A, and50Bare cross-section views, corresponding to respective isometric views listed above. It is noted that the FIG. designated “A” (e.g.,FIG.39Arepresents a first type of device (e.g., p-type field effect transistor) and the FIG. designated “B” represents a second type of device (e.g., n-type FET) at the corresponding stage. Each device type, e.g., that represented by the “A” figure and that represented by the “B” figure may be formed on the same substrate (e.g., substrate202). One or more isolation features (e.g., STI) may interpose the devices of a first type from those of a second type. The method3800begins at block3802where a substrate is provided. Block3802may be substantially similar to block2002of the method2000described above with reference toFIG.20andFIG.21, which are exemplary of providing the substrate202. The method3800then proceeds to block3804where one or more epitaxial layers are grown on the substrate. Block3802may be substantially similar to block2004of the method2000, described above with reference toFIG.20.FIG.22is exemplary of an epitaxial stack2202and HM layer308is formed over the substrate202. The method3800then proceeds to block3806where fin elements are formed. Block3806may be substantially similar to block2006of the method2000, described above with reference toFIG.20.FIG.23is likewise exemplary of a plurality of fin elements402extending from the substrate202. The method3800then proceeds to block3808where shallow trench isolation (STI) features are formed between the fin elements. Block3808may be substantially similar to block2008of the method2000, described above with reference toFIG.20.FIGS.24and25are likewise exemplary of STI features602disposed between the fins402and subsequently recessed. The method3800then proceeds to block3810where sacrificial or dummy layers including a dummy gate structure are formed on the substrate. In an embodiment, a dummy dielectric (e.g., oxide) and a dummy gate structure are formed on the fins. Block3810may be substantially similar to block2020of the method2000.FIG.26andFIG.27are illustrative and include forming a dielectric layer802and a gate structure902(e.g., dummy gate structure). The method3800then proceeds to block3812where select epitaxial layers of the epitaxy stack on device(s) of a second type are oxidized, while the fins of the device(s) of a first type are protected by a masking layer. In an embodiment, the fins or fin regions corresponding to a PFET are covered by the masking layer such as a hard mask. In some embodiments, the masking layer includes a hard mask having an oxide layer (e.g., a pad oxide layer that may include SiO2) and/or nitride layer (e.g., a pad nitride layer that may include Si3N4). In some examples, the masking layer includes thermally grown oxide, CVD-deposited oxide, and/or ALD-deposited oxide. In some embodiments, the masking layer includes a nitride layer deposited by CVD or other suitable technique. While the fins of the device(s) of a first type are protected, an oxidation process is performed such that select epitaxial layers of the fins of the device(s) of the second type are oxidized. In some embodiments, the SiGe epitaxial layers of the epitaxial stack of the second type of devices are oxidized (e.g., fully oxidized). The substrate including the devices of each of the first and second types can be subjected to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the device(s) are exposed to a wet oxidation process using water vapor or steam as the oxidant. Referring to the example ofFIG.39Aof block3812, a device of a first type (e.g., PFET) has a hard mask layer3902disposed thereon. While the HM layer3902is disposed on the device of the first type, an oxidation process is performed on the epitaxial layers304of the source/drain region of the fins of the device(s) of the second type (e.g., NFET) as illustrated inFIG.39B. The oxidation process provides oxidized layers3904. In some embodiments, the materials of the epitaxial layers304,306have different oxidation rates allowing for a selective oxidation process. For example, in some embodiments, the epitaxial layers304are SiGe and the epitaxial layers306are Si. The SiGe can oxidize at a much higher rate than the Si. Again usingFIG.39Aas an example, in an embodiment, the epitaxial layers304are SiGe and result in an oxidized layer3904of SiGeOx. In some embodiments, the epitaxial layers306are not oxidized. In some embodiments, the epitaxial layers304are fully oxidized to form the oxidized layer3904. In some embodiments, the thickness of the epitaxial layer304in the source/drain region is between approximately 2 and 6 nm, for example, as illustrated inFIGS.22-27. Upon oxidation of the epitaxial layer304, the layer may expand to provide a thickness of the oxidized layer3904, for example, in some embodiments, the oxidized layer3904has a thickness between approximately 5 and 25 nanometers. This expansion can provide for a stress (e.g., resulting in a bending of adjacent layers), which is applied to the epitaxial layers306of the source drain region of the fins402. This is illustrated in cross-sectional illustration inFIG.48B. InFIG.48B, because of the increase in thickness of the oxidized layer3904, the epitaxial layers306are no longer coplanar or collinear between the channel region (under the gate) and the source/drain region. It is noted that the epitaxial layers306remain a substantially consistent thickness between the source/drain region and the channel region (e.g., between 6 and 12 nanometers). This can provide for a strain enhancement of the device which may be beneficial, for example, for NMOS devices. As discussed above, in some embodiments, the second device type (illustrated by figures “B”) is an NFET. In some embodiments, block3810continues to provide for the removal of the hard mask layer on the first device type. Using the example ofFIGS.40A/40B, the hard mask layer3902is removed from the substrate202. The method3800then proceeds to block3814where select epitaxial layers of the epitaxy stack are removed from the fin element source/drain region in the fins of the device(s) of a first type (e.g., PFET). As illustrated inFIG.41A/41B, the epitaxial layers304have been removed in the source/drain region of the fins402for the first device type (FIG.41A). The second device type (FIG.41B) remains substantially unchanged. As the exposed epitaxial layer304in the second device type has been oxidized to form oxidized layers3904, an etch may be selective to the epitaxial layer304causing its removal in the first device type. In other embodiments, appropriate patterning and masking steps are performed.FIG.41Aillustrates gaps1002in the place of the removed epitaxial layers304(FIG.40A). The gaps1002may be filled with the ambient environment (e.g., air, N2). Block3814and the gaps1002may be substantially similar to block114and gaps1002described above with reference toFIGS.1and10respectively. The method3800then proceeds to block3816where a spacer layer is deposited on the substrate over the fins of both device types.FIGS.42A/42B illustrate a spacer layer1102disposed on the fins402. With respect to devices of the first type,FIG.42Aillustrates the spacer layer1102is formed on the fins including in the gaps1002. Block3816may be substantially similar to block116of the method100, described above with reference toFIGS.1and11, and/or block2014of the method2000described above with reference toFIG.20. In some embodiments, with reference to the example ofFIGS.43A/43B, after formation of the spacer layer1102, the spacer layer1102may be etched-back to expose portions of the fin elements402adjacent to and not covered by the gate structure902(e.g., source/drain regions). The example ofFIG.43Amay be substantially similar to as discussed above with reference toFIGS.12A and12B. As discussed above, while the spacer layer1102may be removed from a top surface of the epitaxial stack2202and the lateral surfaces of the epitaxial stack2202, as illustrated inFIG.43A, the spacer layer1102remains interposing the epitaxial layers306of the epitaxial stack302in the source/drain region of the first type of device. The spacer layer1102between the epitaxial layers306in the fin elements402of the device(s) of the first type may be between approximately 2-6 nm in thickness. Meanwhile with reference to devices of the second type,FIG.43Bis illustrative of the spacer layer1102being etched-back such that it remains on the sidewalls of the gate structure902forming spacer elements. The method3800then proceeds to block3818where source/drain features are formed in the source/drain regions of each device type. Block3818may be substantially similar to block2016of the method2000, described above with reference toFIGS.20and31, and/or may be substantially similar to block118of the method100, described above with reference toFIGS.1and13. As discussed above, the source/drain features may be formed by performing an epitaxial growth process that provides an epitaxy material cladding the portions of the epitaxy layers in the fins' source/drain regions. The epitaxial material grown in block3818may be the same or different than the epitaxial material of the layer on which it is grown (e.g., epitaxial layer306). Referring to the example ofFIG.44A/44B, source/drain features4402and4404are formed on the fin elements402adjacent the gate stack902for each device type. Referring to exampleFIG.44A, the source/drain features4402include material4402A formed by epitaxially growing a semiconductor material layer on the region of the epitaxial layer306adjacent the gate structure902. In other words, the material4402A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. The source/drain features including epitaxial material4402A may be substantially similar to the epitaxial source/drain material1302A as discussed above with reference toFIG.13. The epitaxial material4402A may be suitably doped to provide a source/drain feature for a first device type (e.g., PFET). Referring to the example ofFIG.44B, the source/drain features4404include material4404A formed by epitaxially growing a semiconductor material layer on the region of the epitaxial layer306adjacent the gate structure902. In other words, the material4404A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. The source/drain features including epitaxial material4404A may be substantially similar to the epitaxial source/drain material1302A as discussed above with reference toFIG.13. The materials for4404A and4204A may be of a suitable composition and/or doping with respect to the associated device type (n-type, p-type). Thus, in embodiments, the materials4404A and4204A are different in at least one of composition or doping. For example, in some embodiments, the epitaxial materials4204A provide a source/drain material suitable for a PFET device; the epitaxial materials4404A provide a source/drain material suitable for an NFET device. Thus, the source/drain features4402and4404may be formed in the same or in different processes. The method3800then proceeds to block3820where an inter-layer dielectric (ILD) layer is formed. In some embodiments, a CESL layer may also be formed. In some embodiments, the gate structure may also be subsequently removed from the substrate. Block3820may be substantially similar to block120of the method100, discussed above with reference toFIG.1and the example ofFIG.14, and/or substantially similar to block2018of the method2000ofFIG.20and the example ofFIG.32. Referring to the example ofFIGS.45A/45B, an ILD layer1402is formed over the substrate202. As illustrated inFIGS.45A/45B, the removal of the electrode layer904(or the electrode layer904and dielectric layer802) from the gate stack902results in a trench1404. WhileFIG.45Aillustrates an interim process wherein the dielectric layer802is disposed in the trench1404, in other embodiments, the dielectric layer802is also removed. The method3800then proceeds to block3822where a selective removal of the epitaxial layer(s) in the channel region of the device(s) is provided. In embodiments, the selected epitaxial layer(s) are removed in the region of the fin element upon and over which the gate structure will be formed, in other words, the channel region. This selective removal may be performed for both types of devices concurrently, or in separate steps including suitable masking elements. Block3822may be substantially similar to block2020of the method200ofFIG.20and/or the example ofFIG.33, and/or be substantially similar to block122of the method100ofFIG.1and/or the example ofFIG.15. Referring to the example ofFIGS.46A/46B, the epitaxy layers304are removed from the channel region of the substrate202and within the trench1404for both types of devices (n-type and p-type). As discussed above, in an embodiment, the epitaxial layers304are SiGe and the epitaxial layers306are silicon allowing for the selective removal of the SiGe epitaxial layers304. It is noted that during the processing stage of block3822(e.g.,FIGS.46A/B), gaps1502are provided between the adjacent nanowires in the channel region (e.g., gaps1502between epitaxy layers306). The method3800then proceeds to block3824where one or more gate structures are formed. The gate structures formed may include high-K/metal gate stacks. Block3824may be substantially similar to block2022of the method2000described above with reference toFIGS.20,34,35,36, and37and/or may be substantially similar to block124of the method100, described above with reference toFIG.1and/or the examples of16,17,18, and19. The gate structures formed for the first device type may be different in composition, configuration, number of layers, and the like than those gate structures for the second device type as each provides a relevant work function. Referring to the example ofFIG.47A, in an embodiment of block3824, a gate stack4702is formed within the trench1404of the device of the first type. The gate stack4702may include interfacial layers, gate dielectric (e.g., high-k) layers4706, and gate electrode (e.g., metal gate)4710. Referring to the example ofFIG.47B, in an embodiment of block3824, a gate stack4704is formed within the trench1404of the device of the second type. The gate stack4704may include interfacial layers, gate dielectric (e.g., high-k) layers4706, and gate electrode (e.g., metal gate)4712. The gate stacks4702and4704may include different compositions and/or be formed in during different processes for each of the interfacial layer, high-k layer, and gate electrode. The gate stack4702provides a suitable work function for a first device type (e.g., PFET). The gate stack4704provides a suitable work function for a second device type (e.g., NFET). For example, a metal layer of gate stacks4702and4704may include the same or different compositions including those selected from the group consisting of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. Thus, the method3800provides in some embodiments a device4700of a first type. In some embodiments, the device4700is a PFET device. The method3800provides in some embodiments a device4710of a second type. In some embodiments, the device4710is a NFET device. The device4700and4710may be provided on the same substrate and function together to form an integrated circuit. As discussed above, an advantage of some embodiments of the method3800and/or the device4710is a strain enhancement provided by the oxidized layer interposing the cladded epitaxial source/drain, see oxidized layer3904. The devices4700and/or4710may perform as a gate-all-around (GAA) device, the respective gate structure4702/4704being formed on multiple sides of the nanowire (epitaxy layer306) in the channel region. The multi-gate device4700is illustrated in isometric view inFIG.47Aand corresponding cross-sectional views inFIG.48A(cross-sectional cut A),FIG.49A(cross-sectional cut B through the gate structure4702),FIG.50A(cross-sectional cut C through the source/drain). The multi-gate device4710is illustrated in isometric view inFIG.47Band corresponding cross-sectional views inFIG.48B(cross-sectional cut A),FIG.49B(cross-sectional cut B through the gate structure4702),FIG.50B(cross-sectional cut C through the source/drain). The ILD layer1402is removed for ease of reference inFIGS.48A,49A,50A. As illustrated inFIGS.48A,49A,48B,49B, the gate dielectric layer4706is disposed below the epitaxial layer306(e.g., nanowire). However, in other embodiments, other portions of the respective gate structure4702,4704(e.g., gate electrode4710,4712) may also be disposed under the epitaxy layer306. In some embodiments, the device4700and/or4710may be a FINFET device having a gate formed on at least two-sides of the channel region (e.g., top and two sidewalls) and/or have other configurations known in the art. The device4700and4710inFIG.50A,50Billustrates the source/drain feature4402,4404having the epitaxially grown cladding layer4402A,4404A disposed on multiple surfaces of the epitaxy layer306(e.g., nanowire) while dielectric materials (spacer1102and oxidized layer3904respectively) interpose the epitaxy layers306in the source/drain region. The semiconductor devices4710and4700may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In some embodiments, interconnect features electrically connect the devices4710and4700. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method3800, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method3800. Illustrated inFIG.51is a method5100of semiconductor fabrication including fabrication of multi-gate devices. The method5100may be substantially similar to many aspects of the method100ofFIG.1, the method2000ofFIG.20, and/or the method3800ofFIG.38, except with some differences highlighted below. However, the description of similar processes and elements (as illustrated by the common numerical indicators) provided above with reference to the method100, the method2000, and/or the method3800apply equally herein unless noted otherwise. Like the method3800above, the method5100illustrates concurrent processing stages for devices of a first and second type. However, the method5100also provides in some embodiments for the formation of an isolation layer underlying the channel and source/drain regions of the fin to provide blocking of unwanted diffusion in either or both of the device types. FIGS.2-9are isometric views of an embodiment a semiconductor device that also apply to various stages of the method5100. (These figures can be applied to processing of both types of devices concurrently and/or substantially similarly.) Following the stage ofFIG.9,FIGS.52A,52B,53A,53B,54A,54B,55A,55B,56A,56B,57A,57B,58A,58B,59A,59B,60A, and60B, corresponds to various stages of the method5100ofFIG.51.FIGS.61A,61B,62A,62B,63A, and63Bare cross-sectional views, corresponding to respective isometric views listed above. These figures provide for a method of implementing teachings of the method5100with respect to devices of a different type (e.g., n-type and p-type) formed on a semiconductor substrate. It is noted again that the FIG. designated “A” (e.g.,FIG.52Arepresents a first type of device (e.g., p-type FET) and the FIG. designated “B” (e.g.,52B) represents a second type of device (e.g., n-type FET) at the corresponding stage. Each device type, e.g., that represented by the “A” figure and that represented by the “B” figure may be formed on the same substrate (e.g., substrate202). One or more isolation features may interpose the devices of a first type from those of a second type. The method5100begins with blocks5202,5204,5206,5208,5210, and5212where a substrate is provided and steps including forming epitaxial stacks, fin elements, an oxidation layer, shallow trench isolation features, and dummy gates. Each of these blocks5202,5204,5206,5208,5210, and5212are substantially similar to the respective blocks102,104,106,108,110and112of the method100, described above with reference toFIG.1andFIGS.2,3,4,5,6,7,8, and9, respectively. While a single exemplary device is illustrated, the processing of one or more of these blocks may be concurrently performed for a device of a first type and a device of a second type. Similar to as described above with reference to the method100at block108, the method5100, at block5108, provides for formation of an insulating layer formed in a fin(s). This insulating layer, illustrated as oxidized layer502, can serve as a diffusion barrier to APT dopants previously implanted into the substrate202, and which may be present in the substrate202directly below the oxidized layer502. Thus, in various embodiments, the oxidized layer502serves to prevent APT dopants within the substrate portion202from diffusing for example, into the overlying epitaxial layer(s)306, which can serve as a channel region for a subsequently formed multi-gate device. It is noted that as illustrated the oxidized layer502is formed for each device type (n-type and p-type). However, in other embodiments, the oxidized layer502may be provided only on a single device type while the other device type may be processed without an oxidized layer (e.g., as illustrated in the method2000and/or3800described above with reference toFIGS.20and38respectively. In some embodiments, the oxidized layer (see, e.g.,FIG.6) formed in the method5100at block108is between approximately 5 and 15 nm. After the method5100performs block5112, the method5100proceeds to block5114where select epitaxial layers of the epitaxy stack on device(s) of a second type are oxidized, while the fins of the device(s) of a first type are protected by a masking layer. In an embodiment, the fins or fin regions corresponding to a PFET are covered by the masking layer, while select epitaxial layers of the source/drain region of the NFET are oxidized. In some embodiments, the masking layer includes a hard mask having an oxide layer (e.g., a pad oxide layer that may include SiO2) and/or nitride layer (e.g., a pad nitride layer that may include Si3N4). In some examples, the masking layer includes thermally grown oxide, CVD-deposited oxide, and/or ALD-deposited oxide. In some embodiments, the masking layer includes a nitride layer deposited by CVD or other suitable technique. While the fins of the device(s) of a first type are protected, an oxidation process is performed on select epitaxial layers of the fins of the device(s) of the second type. In some embodiments, the SiGe epitaxial layers of the epitaxial stack on the fins in the region having the second type of devices are oxidized (e.g., fully oxidized). The substrate including the devices of each of the first and second types can be subjected to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, the device(s) are exposed to a wet oxidation process using water vapor or steam as the oxidant. Referring to the example ofFIG.52A, a device of a first type (e.g., PFET) has a hard mask layer3902disposed thereon. While the HM layer3902is disposed on the device of the first type, an oxidation process is performed on the epitaxial layers304of the source/drain region of the fins of the device(s) of the second type as illustrated inFIG.52B. In some embodiments, the materials of the epitaxial layers304,306have different oxidation rates therefore allowing for a selective oxidation process. For example, in some embodiments, the epitaxial layers304are SiGe and the epitaxial layers306are Si. The SiGe can oxidize at a much higher rate than the Si. UsingFIG.52Aas an example, in an embodiment, the epitaxial layers304are SiGe and result in an oxidized layer3904of SiGeOx. In some embodiments, the epitaxial layers306are not oxidized. As described above, in some embodiments, the bottom epitaxy layer304in the second device type was previously oxidized to form oxidized layer502. In some embodiments, oxidized layer502has a greater thickness than oxidized layers3904. In some embodiments, both oxidized layer502and oxidized layer3904are SiGeOx. In an embodiment, the thickness of the epitaxial layer304in the source/drain region is between approximately 2 and 6 nm, for example, as illustrated inFIGS.2-9. Upon oxidation of the epitaxial layer304in the source/drain region of the second type of device, the layer may expand to provide a thickness of the oxidized layer3904between approximately 5 and 15 nanometers. This expansion can provide for a stress (e.g., resulting in a bending) applied to the epitaxial layers306of the source drain region of the fins402of the device of the second type. This is illustrated inFIG.62Bwhere the epitaxial layers306are no longer coplanar (or collinear) between the channel region (under the gate) and the source/drain region. It is noted that the epitaxial layers306remain a substantially consistent thickness between the source/drain region and the channel region (e.g., between 6 and 12 nanometers). This can provide for a strain enhancement of the device which may be beneficial for example for NMOS devices. The bottom layer, oxidized layer502, in the second device region may be thicker that the oxidized layers3904. In some embodiments, the oxidized layer502in the second device region is between approximately 5 nm and 25 nm. In some embodiments, block5114continues to provide for the removal of the hard mask layer on the first device type. Using the example ofFIGS.53A/53B, the hard mask layer3902is removed from the substrate202. The method5100then proceeds to block5116where select epitaxial layers of the epitaxy stack are removed from the fin region adjacent the gate stack, source/drain region, in the fins of the device(s) of a first type (e.g., PFET). Block5116may be substantially similar to block3814of the method3800, described above with reference toFIG.38, block114of the method100ofFIG.1, and/or block2012of the method2000ofFIG.20. As illustrated inFIG.54A/54B, the epitaxial layers304have been removed from the substrate202in the source/drain region of the fins402for the first device type (FIG.54A). The second device type (FIG.54B) remains substantially unchanged.FIG.54Aillustrates gaps1002in the place of the epitaxial layers304(FIG.53A). The gaps1002may be filled with the ambient environment (e.g., air, N2). In some embodiments, the selectivity between the epitaxial layer304and the oxidized layer3904(oxidized epitaxial layer304) allows for selective removal of the epitaxial layer304from the first device type. The method5100proceeds to block5118where a spacer layer is deposited on the substrate over the fins of both device types. Block5100may be substantially similar to block3816of the method3800, described above with reference toFIG.38andFIGS.39A/39B, block116of the method100, described above with reference toFIGS.1and11, and/or block2014of the method2000described above with reference toFIG.20.FIGS.55A/55B illustrate a spacer layer1102disposed on the fins402. With respect to devices of the first type,FIG.55Aillustrates the spacer layer1102is formed including filling in the gaps1002. In some embodiments, with reference to the example ofFIGS.56A/56B, after formation of the spacer layer1102, the spacer layer1102may be etched-back to expose portions of the fin elements402adjacent to and not covered by the gate structure902(e.g., source/drain regions). The example ofFIG.56Amay be substantially similar to as discussed above with reference toFIGS.12A and12B. As discussed above, while the spacer layer1102may be removed from a top surface of the epitaxial stack2202and the lateral surfaces of the epitaxial stack2202, as illustrated inFIG.56A, the spacer layer1102remains interposing the epitaxial layers306of the epitaxial stack302in the source/drain region of the first type of device and on the sidewalls of the gate. The spacer layer1102between the epitaxial layers306in the fins402of the device(s) of the first type may be between approximately 2-6 nm in thickness. Meanwhile with reference to devices of the second type,FIG.56Bis illustrative of the spacer layer1102being etched-back such that it remains on the sidewalls of the gate structure902forming spacer elements. The method5100then proceeds to block5120where source/drain features are formed. Block5120may be substantially similar to block3818of the method3800, described above with reference toFIGS.38,44A,44B, block2016of the method2000, described above with reference toFIGS.20and31, and/or may be substantially similar to block118of the method100, described above with reference toFIG.1. As discussed above, the source/drain features may be formed by performing an epitaxial growth process that provides an epitaxy material cladding the portions of the epitaxy layers in the fins' source/drain regions. Referring to the example ofFIG.57A/57B, source/drain features4402and4404are formed on the fin element402adjacent the gate structure902for each device type. Referring toFIG.57A, the source/drain features4402include material4402A formed by epitaxially growing a semiconductor material layer on the region of the epitaxial layer306adjacent the gate structure902. In other words, the material4402A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. The source/drain features including epitaxial material4402A may be substantially similar to as discussed above with reference toFIG.44A, and/or substantially similar to the epitaxial source/drain material1302A as discussed above with reference toFIG.13. Referring toFIG.57B, the source/drain features4404include material4404A formed by epitaxially growing a semiconductor material layer on the region of the epitaxial layer306adjacent the gate structure902. In other words, the material4404A is formed around the nanowire (e.g., epitaxy layer306) adjacent the gate; this may be referred to as forming a “cladding” around the nanowire. The source/drain features including epitaxial material4404A may be substantially similar to as described above with reference toFIG.44B, and/or substantially similar to the epitaxial source/drain material1302A as discussed above with reference toFIG.13. The materials for4404A and4204A may be of a suitable composition and/or doping with respect to the associated device type (n-type, p-type). Thus, in embodiments, the materials4404A and4204A are different in at least one of composition or doping. For example, in some embodiments, the epitaxial materials4204A provide a source/drain material suitable for a PFET device; the epitaxial materials4404A provide a source/drain material suitable for an NFET device. Thus, the source/drain4402and4404may be formed in the same or in different processes. The method5100then proceeds to block5122where an ILD layer is formed and/or the gate structure is removed. Block5122may be substantially similar to block3820of the method300, block2018of the method200, and/or block120fthe method100. Referring to the example ofFIGS.58A/58B, an ILD layer1402is formed over the substrate202. As illustrated inFIGS.59A/59B, the removal of the electrode layer904(or the electrode layer904and dielectric layer802) results in a trench1404. The method5100then proceeds to block5124where a selective removal of the epitaxial layer(s) in the channel region of the device(s) is provided. In embodiments, the selected epitaxial layer(s) are removed in the region of the fin element on and over which the gate structure will be formed, in other words, the channel region. This selective removal may be performed for both types of devices concurrently, or in different processing steps that provide for suitable masking. Block5124may be substantially similar to block3822of the method3800, block2020of the method200ofFIG.20and/or the example ofFIG.33, and/or block122of the method100ofFIG.1and/or the example ofFIG.15. Referring to the example ofFIGS.59A/59B, the epitaxy layers304are removed from the channel region of the substrate202and within the trench1404for both types of devices (n-type and p-type). As discussed above, in some embodiments, the epitaxial layers304are SiGe and the epitaxial layers306are silicon allowing for the selective removal of the SiGe epitaxial layers304. It is noted that during the interim processing stage of block5124(e.g.,FIGS.59A/59B), gaps1502are provided between the adjacent nanowires in the channel region (e.g., gaps1502between epitaxy layers306). The method5100then proceeds to block5126where gate structures are formed. Block5126may be substantially similar to block3824of the method3800, block2022of the method2000described above with reference toFIGS.20,34,35,36, and37and/or may be substantially similar to block124of the method100, described above with reference toFIG.1and/or the examples of16,17,18, and19. Referring to the example ofFIG.60A, in an embodiment of block5126, a gate stack4702is formed within the trench1404of the device of the first type. Referring to the example ofFIG.60B, in an embodiment of block3824, a gate stack4704is formed within the trench1404of the device of the second type. The gate stacks4702and4704may include different compositions and/or be formed in during processes. Either or both of the gate stacks4702and4704may be high-K/metal gate stacks. The gate stack4702provides a suitable work function for a first device type (e.g., PFET). The gate stack4704provides a suitable work function for a second device type (e.g., NFET). For example, a metal layer of gate stacks4702and4704may include the same or different compositions including those selected from the group consisting of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or a combination thereof. Thus, the method5100provides in some embodiments a device6000of a first type. In some embodiments, the device6000is a PFET device. The method5100provides in some embodiments a device6010of a second type. In some embodiments, the device6010is a NFET device. The device6000and6010may be provided on the same substrate and function together to form an integrated circuit. As discussed above, an advantage of some embodiments of the method5100and/or the device6110is a strain enhancement provided by the increased thickness of the oxidized layer interposing the cladded epitaxial source/drain, see oxidized layer3904. In some embodiments, an advantage of the device6000is the presence of an oxidized layer502under the channel and/or source/drain regions. In some embodiments, an advantage of the device6010is the presence of an oxidized layer502under the channel and/or source/drain regions. The devices6000and/or6010may perform as a gate-all-around (GAA) device, the gate structure4702/4704being formed on multiple sides of the nanowire (epitaxy layer306). The multi-gate device6000is illustrated in isometric view inFIG.60Aand corresponding cross-sectional views inFIG.61A(cross-sectional cut A),FIG.62A(cross-sectional cut B through the gate structure4702),FIG.63A(cross-sectional cut C through the source/drain). The multi-gate device6010is illustrated in isometric view inFIG.60Band corresponding cross-sectional views inFIG.61B(cross-sectional cut A),FIG.62B(cross-sectional cut B through the gate structure4702),FIG.63B(cross-sectional cut C through the source/drain). The ILD layer1402is removed for ease of reference inFIGS.61A/B,62A/B,63A/B. As illustrated inFIGS.61A,62A,61B,62B, the gate dielectric layer4706is disposed below the epitaxial layer306(e.g., nanowire). However, in other embodiments, other portions of the respective gate structure4702,4704(e.g., gate electrode4710,4712) may also be disposed under the epitaxy layer306. In some embodiments, the device6000and/or6010may be a FINFET device having a gate formed on at least two-sides of the channel region (e.g., top and two sidewalls) and/or have other configurations known in the art. The device6000and6010inFIGS.63A,63Billustrates the source/drain feature4402,4404having the epitaxially grown cladding layer4402A,4404A disposed on multiple surfaces of the epitaxy layer306(e.g., nanowire) while dielectric material (spacer layer1102and oxidized layer3904respectively) interposes the epitaxy layers306. The semiconductor devices6000and6010may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method5100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method5100. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. Thus, in one of the broader embodiments, a method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature. In an embodiment, a method is presented for fabricating a multi-gate device. The method includes growing an epitaxial layer stack including first, second, and third epitaxial layers. The epitaxial layer stack is patterned to form a fin element. A dummy gate structure is formed over the fin element. The second epitaxial layer in a first region and a second region of the fin is transformed to a dielectric layer. The first and second regions are interposed by a third region of the fin that underlies the dummy gate structure. The dummy gate structure is removed after transforming the second epitaxial layer, thereby forming a trench. A metal gate structure is formed in the trench, wherein the metal gate is disposed on multiple sides of each of the first and third epitaxial layers. In some further embodiments the second epitaxial layer is transformed by oxidizing the second epitaxial layer. In some further embodiments, the second epitaxial layer is transformed by removing the second epitaxial layer to form a gap and filling the gap with a dielectric material. In another of the embodiments, a multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer. | 99,720 |
11942549 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments will now be described with respect to a particular embodiment in which an isolation structure is formed with multiple layers. The embodiments describe herein, however, are not intended to be limited to the precise embodiments described, and the ideas may be implemented in a wide variety of uses. All such uses are fully intended to be included within the scope of the embodiments. FIG.1illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring isolation regions56. Although the isolation regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring isolation regions56. A gate dielectric layer92is along sidewalls and over a top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions82are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions82of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, a current flow between the source/drain regions82of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET. Subsequent figures refer to these reference cross-sections for clarity. Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like. FIGS.2through22Bare cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2through13illustrate reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.14A,15A,16A,17A,18A,19A,20A,21A and22Aare illustrated along reference cross-section A-A illustrated inFIG.1, andFIGS.14B,15B,16B,17B,18B,19B,20B,21B and22B are illustrated along a similar cross-section B-B illustrated inFIG.1, except for multiple fins/FinFETs.FIGS.16C and16Dare illustrated along reference cross-section C-C illustrated inFIG.1, except for multiple fins/FinFETs. InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon dioxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has an n-type region SON and a p-type region50P. The n-type region SON can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region SON may be physically separated from the p-type region50P (as illustrated by divider51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region SON and the p-type region50P. InFIG.3, fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by first depositing a first mask layer53(e.g., silicon dioxide) and a second mask layer55(e.g., silicon nitride), patterning the first mask layer53and the second mask layer55, and then using the first mask layer53and the second mask layer55to etch trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. However, the fins52may be patterned by any suitable method. For example, the fins52may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins52. FIG.4illustrates a deposition of a first liner401over the fins52which is utilized to help block any oxidation of a channel region located within the fins52. In an embodiment the first liner401may be a material such as silicon, silicon dioxide, or silicon nitride, deposited along the sidewalls of the fins52and, in some embodiments, not over the first mask layer53and the second mask layer55, using a process such as epitaxial growth, chemical vapor deposition, atomic layer deposition, combinations of these, or the like. However, any suitable material and any suitable deposition process (e.g., a blanket deposition process) may be utilized. Additionally, the first liner401may be formed to have a density of between about 2 g/cm3and about 4 g/cm3and to have a thickness of less than about 20 Å, such as about 13 Å. If the first liner401is formed to have a thickness that is greater than 20 Å, the device will be negatively impacted, while if the thickness is too thin (or if the first liner401is not present), there is an increased risk of oxidation of the channel region within the fin52. FIG.5illustrates a deposition of a second liner501over the first liner401. In an embodiment the second liner501is utilized to help separate the fins52from subsequently deposited layers (described further below). As such, in some embodiments the second liner501may be a material such as silicon dioxide blanket deposited over the fins52, the first mask layer53and the second mask layer55, using a process such as chemical vapor deposition, atomic layer deposition, sputtering, combinations of these, or the like. Additionally, the second liner501may be formed to have a density of between about 2 g/cm3and about 2.6 g/cm3and to have a thickness of between about 10 Å and about 50 Å, such as about 27.5 Å. If the second liner501is formed to have a thickness that is greater than 50 Å, excess oxidation may occur in surrounding structures (e.g., the fins52), while if the thickness is less than about 10 Å, there is an increased risk of impact to the device. FIGS.6A-6Billustrate a deposition of a third liner601over the second liner501. In an embodiment the third liner601is a different material from the second liner501and which may also be transformed in a subsequent process (described further below). As such, the third liner601may be a material such as silicon oxynitride (SiON), SiOCN, SiN, combinations of these, or the like. However, any suitable material may be utilized. FIG.6Billustrates a deposition system731which may be utilized to receive precursor materials in order to help deposit the third liner601. In an embodiment the deposition system731receives precursor materials from a plurality of precursor delivery systems, such as a first precursor delivery system702, a second precursor delivery system703, a third precursor delivery system705, a fourth precursor delivery system735, a fifth precursor delivery system737, and a sixth precursor delivery system739, and form layers of materials onto the substrate50within a deposition chamber733. In an embodiment the first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739may work in conjunction with one another to supply the one or more different precursor materials to the deposition chamber733wherein one or more of the substrates50are placed. However, the first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739may have physical components that are similar with each other. For example, the first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739may each include a gas supply709and a flow controller711. In an embodiment in which the first precursor is stored in a gaseous state, the gas supply709may supply the first precursor to the deposition chamber733. The gas supply709may be a vessel, such as a gas storage tank, that is located either locally to the deposition chamber733or else may be located remotely from the deposition chamber733. Alternatively, the gas supply709may be a facility that independently prepares and delivers the first precursor to the flow controller711. Any suitable source for the first precursor may be utilized as the gas supply709, and all such sources are fully intended to be included within the scope of the embodiments. The gas supply709may supply the desired precursor to the flow controller711. The flow controller711may be utilized to control the flow of the precursor to one or more precursor gas controllers713and, eventually, to the deposition chamber733, thereby also helping to control the pressure within the deposition chamber733. The flow controller711may be, e.g., a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like. However, any suitable method for controlling and regulating the flow of the first precursor may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiments. Additionally, in an embodiment in which the first precursor is stored in a solid or liquid state, the gas supply709may store a carrier gas and the carrier gas may be introduced into a precursor canister or vaporizer, which stores the first precursor in the solid or liquid state. The carrier gas is then used to push and carry the first precursor as it either evaporates or sublimates into a gaseous section of the precursor canister before being sent to the precursor gas controller713. Any suitable method and combination of units may be utilized to provide the first precursor, and all such combination of units is fully intended to be included within the scope of the embodiments. The first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739may supply their individual precursor materials into one or more of a series of precursor gas controllers713. The precursor gas controllers713connect and isolate the first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739from the deposition chamber733in order to deliver the desired precursor materials to the deposition chamber733. The precursor gas controller713may include such devices as valves, flow meters, sensors, and the like to control the delivery rates of each of the precursors and may be controlled by instructions received from a control unit715. The precursor gas controllers713, upon receiving instructions from the control unit715, may open and close valves so as to connect one or more of the first precursor delivery system702, the second precursor delivery system703, the third precursor delivery system705, the fourth precursor delivery system735, the fifth precursor delivery system737, and the sixth precursor delivery system739to the deposition chamber733and direct a desired precursor material through one or more manifolds717, into the deposition chamber733, and to one or more injection units719. The injection units719may be utilized to disperse the chosen precursor material(s) into the deposition chamber733and may be designed to evenly disperse the precursor material in order to minimize undesired process conditions that may arise from uneven dispersal. In a particular embodiment the injection units719may be formed, for example, from coiled tubing including a plurality of holes distributed throughout the tubing allowing for uniform dispersal of the precursor material in the deposition chamber733. However, any suitable shape may be utilized. However, as one of ordinary skill in the art will recognize, the introduction of precursor materials to the deposition chamber733through a single unit as described above is intended to be illustrative only and is not intended to be limiting to the embodiments. Any number of separate and independent injectors, such as three separate and independent injectors, or other openings to introduce precursor materials into the deposition chamber733may be utilized. All such combinations and other points of introduction are fully intended to be included within the scope of the embodiments. The deposition chamber733may receive the desired precursor materials and expose the precursor materials to the substrates50, and the deposition chamber733may be any desired shape that may be suitable for dispersing the precursor materials and contacting the precursor materials with the substrates50. In the embodiment illustrated inFIG.6B, the deposition chamber733has a cylindrical sidewall and a bottom. However, the deposition chamber733is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be utilized. Furthermore, the deposition chamber733may be surrounded by a housing723made of material that is inert to the various process materials. As such, while the housing723may be any suitable material that can withstand the chemistries and pressures involved in the deposition process, in an embodiment the housing723may be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, or the like. Within the deposition chamber733a plurality of the substrates50may be placed within a rack on a mounting rack725in order to position and control the substrates50during the deposition processes. The mounting rack725may include heating mechanisms in order to heat the substrates50during the deposition processes as well as rotation mechanisms in order to rotate the substrates50during the deposition process. Furthermore, while a mounting rack725is illustrated inFIG.6B, a single mounting platform for supporting a single wafer may be included within the deposition chamber733. In addition, the deposition chamber733may include heating elements and/or heating lamps configured to control the temperatures of precursor gases (e.g., the first precursor) entering the deposition chamber733and the exhaust gases exiting the deposition chamber733. According to embodiments, as the precursors enter the manifold717the heating elements either maintain or else raise the temperature of the precursors to a process temperature above a boiling point of the precursors to ensure that the precursor remains in a gas-phase and maintain a suitable flow rate of the precursors at the injection unit719. Furthermore, as the exhaust gases are evacuated from the deposition chamber733, the heating elements maintain or raise the temperature of the exhaust gases at the exhaust outlet727to a temperature above a boiling point of the exhaust gases to maintain a suitable evacuation rate of the exhaust. The deposition chamber733further comprises cooling elements and a coolant source, according to some embodiments. The cooling elements are located within the housing723adjacent the injection unit719and the mounting rack725. The control unit715controls the valve at the coolant source to release coolant into the cooling elements. As such, the temperatures of the precursor gases are controlled to a desired process temperature as they exit the injection unit719and at the locations of the substrates50during the deposition process. One or more vacuum pumps729(e.g., two vacuum pumps729, with different vacuum pumps being utilized to remove different precursors) may be connected to an exhaust outlet727of the deposition chamber733in order to help evacuate the exhaust gases. The exhaust outlet727, under control of the control unit715, may also be utilized to reduce and control the pressure within the deposition chamber733to a desired pressure and may also be utilized to evacuate precursor materials from the deposition chamber733in preparation for the introduction of the next precursor material. The control unit715may be utilized to control the precursor gas controller713, the vacuum pump729, the heating elements, the coolant source, and/or the cooling elements. The control unit715may be any form of computer processor that can be used in an industrial setting for controlling process machines. In an embodiment the control unit715may comprise a processing unit, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a particular application. The control unit715may be equipped with a display and one or more input/output components, such as instruction outputs, sensor inputs, a mouse, a keyboard, printer, combinations of these, or the like. The processing unit may include a central processing unit (CPU), memory, a mass storage device, a video adapter, an I/O interface, and/or a network interface connected to a bus. The bus may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU may comprise any type of electronic data processor, and the memory may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). The mass storage device may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus. The mass storage device may comprise, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive. The video adapter and the I/O interface provide interfaces to couple external input and output devices to the processing unit. Examples of input and output devices include, but are not limited to, the display coupled to the video adapter and the I/O component, such as a mouse, keyboard, printer, and the like, coupled to the I/O interface. Other devices may be coupled to the processing unit and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The network interface couples the processing unit to external networks to facilitate network communications and to provide network access to external resources via one or more wired and/or wireless links (e.g., local area network (LAN) and/or wide area network (WAN)). The network access and network communications may use one or more circuit switched networks and/or packet switched networks. In an embodiment the control unit715may be a system that is locally connected via one or more wired and/or wireless connections to the precursor gas controllers713and/or the vacuum pumps729. In another embodiment the control unit715may be a system that is remote from the precursor gas controller713and/or the vacuum pump729, and may connect and control the precursor gas controller713and vacuum pump729via a remote wired and/or wireless connection. In an embodiment, the control unit715may be a distributed system comprising one or more processing units of one or more network servers and/or may employ one or more network services for controlling the precursor gas controller713and/or the vacuum pump729. It should be noted that the control unit715may include other components. For example, the control unit715may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown inFIG.6B, are considered part of the control unit715. To begin the deposition process for the third liner601, a first precursor material may be placed into one or more of the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. In an embodiment in which the third liner601is silicon oxynitride (SiON), the first precursor material may be a silicon comprising precursor such as hexachlorodisilane (HCD), dichlorosilane (DCS), MS, combinations of these, or the like. However, any suitable precursor for any suitable material may be utilized. A second precursor material may be placed into another one of the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. In the embodiment in which the third liner601is silicon oxynitride (SiON) and the first precursor material is hexachlorodisilane, the second precursor material may be an oxygen comprising precursor such as oxygen (O2), H2O, O3, combinations of these, or the like. However, any suitable precursor for any suitable material may be utilized. A third precursor material may be placed into yet another one of the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. In the embodiment in which the third liner601is silicon oxynitride (SiON), the first precursor material is hexachlorodisilane, and the second precursor material is oxygen, the third precursor material may be a nitrogen containing precursor such as ammonia (NH3), diazene (N2H2), nitrogen (N2), combinations of these, or the like. However, any suitable precursor for any suitable material may be utilized. Once the first precursor material, the second precursor material, and the third precursor material have been placed into the first precursor delivery system702, the second precursor delivery system703, and the third precursor delivery system705, respectively, the formation of the third liner601may be initiated by placing one or more of the substrates50(e.g.,100substrates50) into the mounting rack725(e.g., a wafer boat) and then raising the mounting rack725into the deposition chamber733. Once the mounting rack725has been placed, a pressure within the deposition chamber733may be adjusted to the desired process pressures. In an embodiment the pressure may be adjusted to be between about 931 Pa and about 5000 Pa, such as about 4660 Pa. Additionally, the temperature within the deposition chamber733may be ramped up to the desired process temperature, such as ramping the temperature to the desired process temperature of between about 500° C. and about 750° C., such as about 550° C. In a very particular embodiment the process temperature may be ramped up from a temperature of about 450° C. to a process temperature of about 550° C. or about 630° C. However, any suitable process conditions may be utilized. Then, after a vacuum check (VC) and a leak check, the atomic layer deposition cycle may be initiated by the control unit715sending an instruction to the precursor gas controller713to connect the first precursor delivery system702to the deposition chamber733. Once connected, the first precursor delivery system702can deliver the first precursor material to the injection unit719through the precursor gas controller713and the manifold717. The injection unit719can then disperse the first precursor material into the deposition chamber733, wherein the first precursor material can be adsorbed and react with each of the exposed surfaces. In one embodiment in which the third liner601is silicon oxynitride, the first precursor material (e.g., hexachlorodisilane) may be flowed into the deposition chamber733at a flow rate of between about 0.2 slm and about 6 slm, such as about 0.45 slm, and a flow pressure of between about 10 Pa and about 300 Pa, such as about 110 Pa, for a time of between about 3 seconds and about 80 seconds, such as about 20 seconds. However, any suitable flow rate may be utilized. FIG.6Cillustrates a close-up view of a surface of the second liner501and illustrates that, in the embodiment in which a layer of silicon oxynitride is desired to be formed using hexachlorodisilane, under these process conditions the hexachlorodisilane will react with the exposed surfaces (e.g., the second liner501) in order to provide a surface wherein silicon is chemically bonded to the underlying surface while the opposite surface is terminated with chlorine atoms which are exposed to the ambient atmosphere within the deposition chamber733. Additionally, the reaction of the hexachlorodisilane with the underlying structures will be self-limiting, providing a single layer of molecules once this step is completed. After the self-limiting reaction has finished, the deposition chamber733may be purged off the first precursor material with a first purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the first precursor delivery system702(containing the first precursor material to be purged from the deposition chamber733) and to connect a purge gas delivery system707to deliver a purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may be a gaseous tank or other facility that provides a purge gas such as nitrogen, argon, xenon, or other gas to the deposition chamber733, for a purge flow pressure of about 66 Pa for a time period of about 13 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the first precursor material. The purge gas, along with the vacuum pump729, may purge the first precursor material from the deposition chamber733. After the purge of the first precursor material has been completed, the introduction of the second precursor material (e.g., oxygen) to the deposition chamber733may be initiated by the control unit715sending an instruction to the precursor gas controller713to disconnect the purge gas delivery system707and to connect the second precursor delivery system703(containing the second precursor material) to the deposition chamber733. Once connected, the second precursor delivery system703can deliver the second precursor material to the injection unit719. The injection unit719can then disperse the second precursor material into the deposition chamber733. In the embodiment discussed above to form a layer of silicon oxynitride with hexachlorodisilane as the first precursor material and oxygen as the second precursor material, the second precursor material may be introduced into the deposition chamber733at a flow rate of between about 0.2 slm and about 8 slm, such as about 5 slm, with a flow pressure of between about 200 Pa and about 4500 Pa, such as about 1200 Pa, for at time of between about 3 seconds and about 120 seconds, such as about 59 seconds. However, as one of ordinary skill in the art will recognize, these flow rates are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. FIG.6Dillustrates a close-up view of the surface of the second liner501and illustrates that, in the embodiment in which a layer of silicon oxynitride is desired to be formed using hexachlorodisilane as the first precursor material and oxygen as the second precursor material, under these process conditions the oxygen will react with the exposed surfaces (e.g., the product of the reaction of the first precursor material) in order to provide a surface wherein oxygen is chemically bonded to the underlying surface (e.g., silicon). After the reaction of the second precursor material has finished, the deposition chamber733may be purged off the second precursor material with a second purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the second precursor delivery system703(containing the second precursor material to be purged from the deposition chamber733) and to connect the purge gas delivery system707to deliver the purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may deliver the purge gas at a flow pressure of about 66 Pa for a time period of about 12 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the second precursor material. The purge gas, along with the vacuum pump729, may purge the second precursor material from the deposition chamber733. After the purge of the second precursor material has been completed, the introduction of the third precursor material (e.g., ammonia) to the deposition chamber733may be initiated by the control unit715sending an instruction to the precursor gas controller713to disconnect the purge gas delivery system707and to connect the third precursor delivery system705(containing the third precursor material) to the deposition chamber733. Once connected, the third precursor delivery system705can deliver the third precursor material to the injection unit719. The injection unit719can then disperse the third precursor material into the deposition chamber733. In the embodiment discussed above to form a layer of silicon oxynitride with hexachlorodisilane as the first precursor material, oxygen as the second precursor material, and ammonia as the third precursor material, the third precursor material may be introduced into the deposition chamber733at a flow rate of between about 0.2 slm and about 8 slm, such as about 4.5 slm, with a flow pressure of between about 10 Pa and about 1500 Pa, such as about 931 Pa, for a time period of between about 2 seconds and about 80 seconds, such as about 18 seconds. However, as one of ordinary skill in the art will recognize, these flow rates are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. After the reaction of the third precursor material has finished, the deposition chamber733may be purged off the third precursor material with a third purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the third precursor delivery system705(containing the third precursor material to be purged from the deposition chamber733) and to connect the purge gas delivery system707to deliver the purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may deliver the purge gas at a flow pressure of about 66 Pa for a time period of about 3 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the third precursor material. The purge gas, along with the vacuum pump729, may purge the third precursor material from the deposition chamber733. After the deposition chamber733has been purged using the third purge process, a first cycle for the formation of the third liner601has been completed, and a second cycle similar to the first cycle may be started. For example, the repeated cycle may introduce the first precursor material, purge with the purge gas, pulse with the second precursor material, purge with the purge gas, pulse with the third precursor material, and purge with the purge gas. Each cycle of the first precursor material, the second precursor material, and the third precursor material can deposit another layer of the desired material for the third liner601(e.g., SiON) at a rate of about 2 Å per cycle. Additionally, each cycle also resets the exposed surface so that the exposed surface is prepared to receive the next cycle of the first precursor material, the second precursor material, and the third precursor material. These cycles may be repeated between about 5 times and about 100 times to form the third liner601to a thickness of between about 10 Å and about 50 Å, such as about 40 Å. Once the depositions cycles have been finished, a removal process may be performed to remove the substrates50from the deposition system731. In one embodiment the removal process may include a gas line purge, a post purge (using, e.g., the third precursor material of ammonia), a ramp down of the temperature from, e.g., 550° C. to about 450° C. or about 400° C., and a back filling of the ambient within the deposition chamber to ambient atmosphere. Once this has been performed, the substrates50may be removed from the deposition systems731. FIG.6Eillustrates a close up view of the surface of the second liner501and illustrates that, in the embodiment in which a layer of silicon oxynitride is desired to be formed using hexachlorodisilane as the first precursor material, oxygen as the second precursor material, and ammonia as the third precursor material, under these process conditions, multiple monolayers of the desired material (e.g., SiON) can be built up to cover the surface of the second liner501. By utilizing the process as described above, the third liner601may be formed with a desired first composition. For example, using the times and temperatures as described above, the third liner601may be formed with a nitrogen composition of greater than 0% and less than 10%. If the nitrogen concentration is greater than about 10%, there will be a negative impact to the device. Additionally, the third liner601may be formed with a silicon composition of between about 25%-atomic and about 40%-atomic, and an oxygen concentration of between about 40%-atomic and about 70%-atomic. Additionally, the third liner601may be formed with a density of between about 2 g/cm3and about 3 g/cm3. However, any suitable compositions may be utilized. FIG.6Aadditionally illustrates a first annealing process (represented inFIG.6Aby the wavy lines labeled603) which may be utilized after deposition of the third liner601in order to remove some of or all of the nitrogen (although the third liner601may still have a nitrogen concentration of between greater than 0% and less than 10%) and transform the material of the third liner601. In an embodiment the first annealing process603may comprise a multi-step anneal which includes a first wet annealing process, a second wet annealing process, and a dry annealing process. For example, the first wet annealing process may be an anneal wherein the third liner601is heated in a moisture containing environment (e.g., water environment) at a temperature of between about 300° C. and about 500° C. for a time of between about 0.5 hours and about 2 hours. However, any suitable process parameters may be utilized. During the first wet annealing process, the moisture in the environment will penetrate into the deposited material of the third liner601(e.g., the SiON) and react with the material of the third liner601. For example, in an embodiment in which the third liner601is SiON, the moisture will react to replace some of the nitrogen groups within the material of the third liner601with hydroxyl groups. As such, a transformation of the third liner601to another material (e.g., silicon dioxide) may be begun. Once the first wet annealing process has been completed, the transformation may be continued using a second wet annealing process. In an embodiment the second wet annealing process may be an anneal wherein the third liner601is heated in a moisture containing environment (e.g., water environment) at a temperature greater than the first wet annealing process, such as a temperature of between about 500° C. and about 650° C. for a time of between about 0.5 hours and about 4 hours. By utilizing a second wet annealing process, at a higher temperature, a fuller conversion of the material of the third liner601can be achieved. However, any suitable process parameters may be utilized. FIG.6Fillustrates a result of the first wet annealing process and the second wet annealing process. As can be seen, in the embodiments described above the original material of the third liner601(e.g., SiON) is reacted with water to remove at least some of the nitrogen. However, hydroxyl groups are still located within the material of the third liner601. As such, once the second wet annealing process has been completed, the first dry annealing process may be utilized in order to remove any excess moisture from the structure and to remove the hydroxyl groups. In an embodiment the first dry annealing process may be an anneal wherein the material of the third liner601is heated in a dry environment at a temperature of between about 600° C. and about 750° C. for a time of between about 0.5 hours and about 2 hours. However, any suitable process parameters may be utilized. FIG.6Gillustrates a result of the first dry annealing process. In particular, in the first wet annealing process the moisture in the environment will penetrate into the deposited material of the third liner601(e.g., the SiON) and react to replace some of the nitrogen groups within the material of the third liner601with hydroxyl groups. In the first dry annealing process the increased temperature causes the hydroxyl groups to decompose, leaving behind silicon dioxide as the final material of the third liner601. FIG.6Hillustrates a composition of the material of the third liner601as deposited (represented by the line labeled605) at a temperature of 550° C., the material of the third liner601after the first wet annealing process (represented by the line labeled607) and before the second wet annealing process, and the material of the third liner601after the first dry annealing process (represented by the line labeled609). Additionally illustrated inFIG.6H, are a first line611which illustrates the location of Si—NH2bonds, a second line613which illustrates the location of Si—O—Si bonds, and a third line615which illustrates the location of N—H bonds. As can be seen, the number of nitrogen bonds decreases from the as deposited composition through the first wet annealing process, to after the first dry annealing process. Similarly, the number of silicon to oxygen bonds increases from the as deposited composition through the first wet annealing process, to after the first dry annealing process. As such, the transformation of the material of the third liner601is achieved. FIG.6Iillustrates a composition of the material of the third liner601as deposited (represented by the line labeled605) at a temperature of 630° C., the material of the third liner601after the first wet annealing process (represented by the line labeled607) and before the second wet annealing process, and the material of the third liner601after the first dry annealing process (represented by the line labeled609). As can be seen again, the number of nitrogen bonds decreases from the as deposited composition through the first wet annealing process, to after the first dry annealing process. Similarly, the number of silicon to oxygen bonds increases from the as deposited composition through the first wet annealing process, to after the first dry annealing process. As such, the transformation of the material of the third liner601is achieved. By depositing the third liner601as one material and then transforming the deposited material into a second material, the material of the third liner601can have different properties at different points in the manufacturing process. For example, by depositing the third liner601as a first material (e.g., SiON), the benefits of using the first material during the deposition process, such as a reduced amount of oxidation of the underlying fin52, may be achieved. However, by subsequently changing the first material to a second material (e.g., SiO2), better stiffness and device performance can be achieved to help prevent the fins52from bending during subsequent processes. As such, an overall better device performance can be obtained. FIG.7illustrates a deposition of a fourth liner701over the third liner601. In an embodiment the fourth liner701may be utilized to help ensure an adequate gap fill of the materials between the fins52. As such, in some embodiments the fourth liner701may be an oxide material (e.g., silicon dioxide) that is deposited using a flowable process, such as a flowable CVD process. However, any suitable material and method of deposition may be utilized. In an embodiment the fourth liner701may be deposited to a thickness of between about 10 Å and about 50 Å. Additionally, the fourth liner701may be formed to a density of between about 1.2 g/cm3and about 2.5 g/cm3. However, any suitable thickness and density may be utilized. In a particular embodiment, the fourth liner701may be deposited using a system that is similar to the deposition system described above with respect toFIG.6B, although with different precursors placed into the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. To begin the deposition process, a first precursor may be placed into one or more of the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. In an embodiment in which the fourth liner701is desired to be silicon dioxide, the first precursor may be a higher order silane (SinH2n+2for n>3) such as tetrasilane (Si4H10) (including n-Si4H10and iso-S4H10), pentasilane (Si5H12) (including n-Si5H12, iso-Si5H12, and neo-Si5H12), cyclopentasilane (Si5H10), hexasilane (Si6H14) (including n-Si6H14and iso-Si6H14), cyclo-Si6H12, heptasilane (Si7H16) (including n-Si7H16), combinations, or the like. However, any suitable precursor for any suitable material may be utilized. Additionally, a second precursor may be placed into another one of the first precursor delivery system702, the second precursor delivery system703, and/or the third precursor delivery system705. In an embodiment in which the fourth liner701is desired to be silicon dioxide and the first precursor is a high order silane, the second precursor may be a precursor such as oxygen (O2), H2O, O3, combinations of these, or the like. During the deposition process, the first precursor and the second precursor are introduced into the deposition chamber733as vapors (maintained by, e.g., the heating elements). However, as the first precursor flows over the substrates50, the cooling elements remove heat and cause the first precursor to cool down below a transition temperature, causing the first precursor to condense onto the exposed surface of the substrates100. Further, condensing as a liquid causes the first precursor to further flow into and fill the trenches between the fins52without voids. Additionally, once in place on the surface, the first precursor will react with the second precursor to form the material that is desired to be deposited (e.g., silicon dioxide) without voids and without seams. FIG.8Aillustrates formation of a capping layer801over the fourth liner701. In an embodiment the capping layer801is formed in order to help prevent undesired bending of the fins52during subsequent processing. As such, in some embodiments the capping layer801may be deposited as a material such as silicon oxycarbonitride (SiOCN), ammonia doped silicon carbon nitride (SiCN), SiON, combinations of these or the like. However, any suitable materials may be utilized. In an embodiment in which the capping layer801is deposited as SiOCN, the capping layer801may be formed using a similar system as the deposition system731described above with respect toFIG.6B, and in some particular embodiments the capping layer801may be formed in the same deposition system731used to form the third liner601. In such an embodiment a fourth precursor material may be placed into the fourth precursor delivery system735that can be used along with the first precursor material (e.g., hexachlorodisilane) and the second precursor material (e.g., oxygen) in order to form the material of the capping layer801(e.g., SiOCN). For example, in some embodiments the fourth precursor material may be a material such as triethylamine (N(C2H5)3), Si2CH2Cl6, combinations of these, or the like. However, any suitable precursor material may be utilized. Once the first precursor material, the second precursor material, and the fourth precursor material have been placed into the first precursor delivery system702, the second precursor delivery system703, and the fourth precursor delivery system735, respectively, the formation of the capping layer801may be initiated by placing one or more of the substrates50(e.g.,120substrates50) into the mounting rack725(e.g., a wafer boat) and then raising the mounting rack725into the deposition chamber733. Once the mounting rack725has been placed, a pressure within the deposition chamber733may be adjusted to the desired process pressures. In an embodiment the pressure may be adjusted to be between about 2000 Pa and about 5000 Pa, such as about 4660 Pa. Additionally, the temperature within the deposition chamber733may be ramped up to the desired process temperature, such as ramping the temperature to the desired process temperature from about 450° C. to be between about 500° C. and about 750° C., such as about 630° C. In a very particular embodiment the process temperature may be ramped up from a temperature of about 450° C. to a process temperature of about 630° C. However, any suitable process conditions may be utilized. Then, after a vacuum check (VC) and a leak check, the atomic layer deposition cycle may be initiated by the control unit715sending an instruction to the precursor gas controller713to connect the first precursor delivery system702to the deposition chamber733. Once connected, the first precursor delivery system702can deliver the first precursor material to the injection unit719through the precursor gas controller713and the manifold717. The injection unit719can then disperse the first precursor material into the deposition chamber733, wherein the first precursor material can be adsorbed and react with each of the exposed surfaces. In one embodiment in which the capping layer801is silicon oxycarbonitride, the first precursor material (e.g., hexachlorodisilane) may be flowed into the deposition chamber733at a flow rate of between about 0.2 slm and about 6 slm, such as about 0.45 slm, with a flow pressure of between about 10 Pa and about 300 Pa, such as about 110 Pa, for a time of between about 2 seconds and about 60 seconds, such as about 20 seconds. However, any suitable flow rate may be utilized. FIG.8Billustrates a close-up view of a surface of the fourth liner701and illustrates that, in the embodiment in which a layer of silicon oxycarbonitride is desired to be formed using hexachlorodisilane, under these process conditions the hexachlorodisilane will react with the exposed surfaces (e.g., the fourth liner701) in order to provide a surface wherein silicon is chemically bonded to the underlying surface while the opposite surface is terminated with chlorine atoms which are exposed to the ambient atmosphere within the deposition chamber733. Additionally, the reaction of the hexachlorodisilane with the underlying structures will be self-limiting, providing a single layer of molecules once this step is completed. After the self-limiting reaction has finished, the deposition chamber733may be purged off the first precursor material with a fourth purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the first precursor delivery system702(containing the first precursor material to be purged from the deposition chamber733) and to connect the purge gas delivery system707to deliver the purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may deliver a purge flow pressure of about 66 Pa for a time period of between about 13 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the first precursor material. The purge gas, along with the vacuum pump729, may purge the first precursor material from the deposition chamber733. After the purge of the first precursor material has been completed, the introduction of the fourth precursor material (e.g., triethylamine) to the deposition chamber733may be initiated by the control unit715sending an instruction to the precursor gas controller713to disconnect the purge gas delivery system707and to connect the fourth precursor delivery system735(containing the fourth precursor material) to the deposition chamber733. Once connected, the fourth precursor delivery system735can deliver the fourth precursor material to the injection unit719. The injection unit719can then disperse the fourth precursor material into the deposition chamber733. In the embodiment discussed above to form a layer of silicon oxycarbonitride with hexachlorodisilane as the first precursor material and triethylamine as the fourth precursor material, the fourth precursor material may be introduced into the deposition chamber733at a flow rate of between about 0.2 slm and about 6 slm, such as about 0.8 slm, with a flow pressure of between about 10 Pa and about 1500 Pa, such as about 931 Pa, for at time of between about 2 seconds and about 80 seconds, such as about 20 seconds. However, as one of ordinary skill in the art will recognize, these flow rates are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. FIG.8Cillustrates a close-up view of the surface of the fourth liner701and illustrates that, in the embodiment in which a layer of silicon oxycarbonitride is desired to be formed using hexachlorodisilane as the first precursor material and triethylamine as the fourth precursor material, under these process conditions the triethylamine will react with the exposed surfaces (e.g., the product of the reaction of the first precursor material) in order to provide a surface wherein nitrogen is chemically bonded to the underlying surface (e.g., silicon) while the opposite surface is terminated with ethyl groups which are exposed to the ambient atmosphere within the deposition chamber733. Additionally, the reaction of the triethylamine with the underlying structures will be self-limiting, providing a single layer of molecules once this step is completed. After the reaction of the fourth precursor material has finished, the deposition chamber733may be purged off the fourth precursor material with a fifth purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the fourth precursor delivery system735(containing the fourth precursor material to be purged from the deposition chamber733) and to connect the purge gas delivery system707to deliver the purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may deliver the purge gas at a flow pressure of about 66 Pa for a time period of between about 12 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the fourth precursor material. The purge gas, along with the vacuum pump729, may purge the fourth precursor material from the deposition chamber733. After the purge of the fourth precursor material has been completed, the introduction of the second precursor material (e.g., oxygen) to the deposition chamber733may be initiated by the control unit715sending an instruction to the precursor gas controller713to disconnect the purge gas delivery system707and to connect the second precursor delivery system703(containing the second precursor material) to the deposition chamber733. Once connected, the second precursor delivery system703can deliver the second precursor material to the injection unit719. The injection unit719can then disperse the second precursor material into the deposition chamber733. In the embodiment discussed above to form a layer of silicon oxycarbonitride with hexachlorodisilane as the first precursor material, oxygen as the second precursor material, and triethylamine as the fourth precursor material, the second precursor material may be introduced into the deposition chamber733at a flow rate of between about 0.2 slm and about 80 slm, such as about 5 slm, with a flow pressure of between about 200 Pa and about 4600 Pa, such as about 1200 Pa, for a time period of between about 3 seconds and about 120 seconds, such as about 55 seconds. However, as one of ordinary skill in the art will recognize, these flow rates are only intended to be illustrative, as any suitable process conditions may be utilized while remaining within the scope of the embodiments. FIG.8Dillustrates a close up view of the surface of the fourth liner701and illustrates that, in the embodiment in which a layer of silicon oxycarbonitride is desired to be formed using hexachlorodisilane as the first precursor material, oxygen as the second precursor material, and triethylamine as the fourth precursor material, under these process conditions the oxygen will react with the exposed surfaces in order to provide a surface wherein oxygen is chemically bonded to the underlying surfaces (e.g., silicon) while the opposite surface is still partially terminated with ethyl groups along with the oxygen atoms which are exposed to the ambient atmosphere within the deposition chamber733. After the reaction of the second precursor material has finished, the deposition chamber733may be purged off the second precursor material with a sixth purge process. For example, the control unit715may instruct the precursor gas controller713to disconnect the second precursor delivery system703(containing the second precursor material to be purged from the deposition chamber733) and to connect the purge gas delivery system707to deliver the purge gas to the deposition chamber733. In an embodiment the purge gas delivery system707may deliver the purge gas at a flow pressure of about 66 Pa for a time period of between about 3 seconds. Additionally, the control unit715may also initiate the vacuum pump729in order to apply a pressure differential to the deposition chamber733to aid in the removal of the second precursor material. The purge gas, along with the vacuum pump729, may purge the second precursor material from the deposition chamber733. After the deposition chamber733has been purged using the sixth purge process, a first cycle for the formation of the capping layer801has been completed, and a second cycle similar to the first cycle may be started. For example, the repeated cycle may introduce the first precursor material, purge with the purge gas, pulse with the fourth precursor material, purge with the purge gas, pulse with the second precursor material, and purge with the purge gas. As can be seen, each cycle of the first precursor material, the fourth precursor material, and the second precursor material can deposit another layer of the desired material for the capping layer801(e.g., silicon oxycarbonitride (SiOCN)) at a rate of about 0.6 Å per cycle, as can be seen inFIG.8E, which illustrates the structure after two such cycles. Additionally, each cycle also resets the exposed surface so that the exposed surface is prepared to receive the next cycle of the first precursor material, the fourth precursor material, and the second precursor material. These cycles may be repeated to form the capping layer801to a thickness that is either larger than or smaller than the thickness of the third liner601, such as a thickness of between about 10 Å and about 70 Å. Additionally, the capping layer801may be formed to have a density of between about 2 g/cm3 and about 2.6 g/cm3. However, any suitable thickness and density may be utilized. Once the depositions cycles have been finished, a removal process may be performed to remove the substrates50from the deposition system731. In one embodiment the removal process may include a gas line purge, a post purge (using, e.g., the third precursor material of ammonia), a ramp down of the temperature from, e.g., 640° C. to about 300° C., and a back filling of the ambient within the deposition chamber to ambient atmosphere. Once this has been performed, the substrates50may be removed from the deposition systems731. By utilizing the process as described above, the capping layer801may be formed with a desired second composition. For example, using the times and temperatures as described above, the capping layer801may be formed with a nitrogen composition of greater than 0% and less than 10%. Additionally, the capping layer801may be formed with a carbon concentration of greater than 0% and less than about 10%. If the nitrogen concentration is greater than about 10% or the carbon concentration is greater than about 10%, adjacent fins52may bend inwardly, causing gap fill problems with subsequent depositions. Additionally, the capping layer801may be formed with a silicon composition of between about 25% and about 40%, and an oxygen concentration of between about 40% and about 70%. Additionally, the capping layer801may be formed with a density of between about 2 g/cm3and about 3 g/cm3. However, any suitable compositions may be utilized. FIG.8Aadditionally illustrates that, once the capping layer801has been deposited, a second annealing process (represented inFIG.8Aby the wavy lines labeled803) may be utilized to transform the material of the capping layer801to another material by removing some or all of the nitrogen and carbon within the material of the capping layer801, although the capping layer801may still have a concentration of nitrogen greater than 0% and less than 10% and may still have a concentration of carbon that is greater than 0% and less than 10%. In a particular embodiment in which the material of the capping layer801is deposited as SiOCN, the second annealing process803may be similar to the first annealing process603(described above with respect toFIG.6A). For example, the second annealing process803may comprise the first wet annealing process, the second wet annealing process, and the first dry annealing process. However, any suitable annealing processes may be utilized. FIG.8Fillustrates the structures of the capping layer801after the first wet annealing process and the second wet annealing process of the second annealing process803. As can be seen, the moisture will react with the material of the capping layer801and at least partially or completely replace the carbon with hydroxyl groups. Further,FIG.8Gillustrates the material of the capping layer801after the first dry annealing process of the second annealing process803. As can be seen, the first dry annealing process of the second annealing process803will cause the hydroxyl groups to decompose and leave behind oxygen to silicon bonds. As such, the original material of the capping layer801(e.g., SiOCN) is transformed to silicon dioxide. Additionally, while the above description utilizes both the first annealing process603(described above with respect toFIG.6A) along with the second annealing process803to transform the third liner601and the capping layer801immediately after these materials have been deposited, this is intended to be illustrative and is not intended to limit the embodiments. Any suitable rearrangement of the order of steps or even the consolidation of the process steps, may also be utilized. For example, in certain particular embodiments, the first annealing process603and the second annealing process803are consolidated into a single annealing process. As a single annealing process, the single annealing process would be performed after the deposition of the material for the capping layer801. As such, a single process may be utilized to transform the material for both the capping layer801and the third liner601. Any suitable combination of process steps may be utilized. By depositing the capping layer801as a first material and then transforming the capping layer801to a second material, the capping layer801will expand after deposition. Additionally, the expansion helps to modulate any bending of the fins52which may affect subsequent deposition processes (e.g., deposition of the dummy gate layer62) and allows for a better gap fill during the deposition processes. Optionally, in some embodiments a capping liner (not separately illustrated) may be deposited over the capping layer801. In some embodiments the capping liner may be similar to the second liner501(e.g., silicon dioxide). In such an embodiment the capping layer801may be deposited to a thickness of about 20 Å and the capping liner may have a thickness of between about 17.5 Å and about 40 Å. In another embodiment the capping layer801may be deposited to a thickness of about 50 Å and the capping liner may have a thickness of between about 17.5 Å and about 20 Å. However, any suitable material and thicknesses may be utilized. InFIG.9a dielectric cap901is formed over the capping layer801and between neighboring fins52. The dielectric cap901may be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the dielectric cap901is silicon dioxide formed by a FCVD process. In an embodiment the dielectric cap901may be formed to a thickness of between about 10 Å and about 50 Å and to a density of between about 2 g/cm3 and about 2.6 g/cm3. If the dielectric cap901is formed below about 10 Å, there is an impact of the device's isolation, while if the dielectric cap901has been formed thicker than about 50 Å, there is an impact to the hybrid film. InFIG.10, a removal process is applied to the dielectric cap901to remove excess dielectric cap901over the fins52. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins52such that top surfaces of the fins52and the dielectric cap901are level after the planarization process is complete. In embodiments in which the first mask layer53and the second mask layer55remain on the fins52, the planarization process may expose the mask or remove the first mask layer53and the second mask layer55such that top surfaces of the first mask layer53, the second mask layer55, or the fins52, respectively, and the dielectric cap901are level after the planarization process is complete. FIG.11illustrates formation of dielectric fins903within the dielectric cap901in order to help electrically separate adjacent fins52from each other. In an embodiment an opening may be formed within the dielectric cap901using, e.g., a photolithographic masking and etching process. Once the opening has been formed, the opening may be filled with one or more dielectric materials to form the dielectric fins903, such as silicon dioxide, silicon nitride, silicon carbon nitride, combinations of these, or the like, using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, combinations of these, or the like. Once deposited, the materials of the dielectric fins903may be planarized using a process such as chemical mechanical polishing. InFIG.12, the dielectric cap901, the capping layer801, the fourth liner701, the third liner601, the second liner501, and the first liner401are recessed to form Shallow Trench Isolation (STI) regions56(wherein for clarity dielectric cap901, the capping layer801, the fourth liner701, the third liner601, the second liner501, and the first liner401are illustrated in dashed lines inFIG.12but as a single structure for a remainder of the application). The dielectric cap901, the capping layer801, the fourth liner701, the third liner601, the second liner501, and the first liner401are recessed using one more etching processes such that upper portions of fins52and the dielectric fin903in the n-type region50N and in the p-type region50P protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etches. The STI regions56may be recessed using one or more acceptable etching processes, such as processes that are selective to the materials of the dielectric cap901, the capping layer801, the fourth liner701, the third liner601, the second liner501, and the first liner401(e.g., etches the material of the dielectric cap901at a faster rate than the material of the fins52and the dielectric fin903). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. By utilizing the processes described herein, the fins52can be prevented from bending while still being able to prevent excess oxidation. As such, the spacing between fins52(e.g., without a dielectric fin903being located between fins52) can be kept to a first spacing S1of between about 5 nm and about 30 nm. Additionally, a second spacing S2between the fins52and the dielectric fin903can be kept to be between about 5 nm and about 30 nm. If the fins52bend so that these spacings are undesirably reduced, subsequent depositions of materials between adjacent fins52or between the fins52and the dielectric fins903can have gap fill problems. The process described with respect toFIGS.2through12is just one example of how the fins52may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, prior to formation of the STI regions56, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be removed. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins52. For example, the fins52inFIG.10can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins52comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be removed. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., an NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins52may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like. Further inFIG.12, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a P well may be formed in the n-type region50N, and an N well may be formed in the p-type region50P. In some embodiments, a P well or an N well are formed in both the n-type region50N and the p-type region50P. In the embodiments with different well types, the different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins52and the STI regions56in the n-type region50N. The photoresist is patterned to expose the p-type region50P of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1016cm−3and about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following the implanting of the p-type region50P, a photoresist is formed over the fins52and the STI regions56in the p-type region50P. The photoresist is patterned to expose the n-type region50N of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1018cm−3, such as between about 1016cm−3and about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.13, a dummy dielectric layer60is formed on the fins52and the dielectric fin903. The dummy dielectric layer60may be, for example, silicon dioxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer62is formed over the dummy dielectric layer60, and a mask layer64is formed over the dummy gate layer62. The dummy gate layer62may be deposited over the dummy dielectric layer60and then planarized, such as by a CMP. The mask layer64may be deposited over the dummy gate layer62. The dummy gate layer62may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer62may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions56and/or the dummy dielectric layer60. The mask layer64may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer62and a single mask layer64are formed across the n-type region50N and the p-type region50P. It is noted that the dummy dielectric layer60is shown covering only the fins52for illustrative purposes only. In some embodiments, the dummy dielectric layer60may be deposited such that the dummy dielectric layer60covers the STI regions56, extending over the STI regions and between the dummy gate layer62and the STI regions56. FIGS.14A through22Billustrate various additional steps in the manufacturing of embodiment devices.FIGS.14A through22Billustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated inFIGS.14A through22Bmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure. InFIGS.14A and14B, the mask layer64(seeFIG.13) may be patterned using acceptable photolithography and etching techniques to form masks74. The pattern of the masks74then may be transferred to the dummy gate layer62. In some embodiments (not illustrated), the pattern of the masks74may also be transferred to the dummy dielectric layer60by an acceptable etching technique to form dummy gates72. The dummy gates72cover respective channel regions58of the fins52. The pattern of the masks74may be used to physically separate each of the dummy gates72from adjacent dummy gates. The dummy gates72may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins52. Further inFIGS.14A and14B, gate seal spacers80can be formed on exposed surfaces of the dummy gates72, the masks74, and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers80. The gate seal spacers80may be formed of silicon dioxide, silicon nitride, silicon oxynitride, or the like. After the formation of the gate seal spacers80, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above inFIG.12, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 1015cm−3to about 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. InFIGS.15A and15B, gate spacers86are formed on the gate seal spacers80along sidewalls of the dummy gates72and the masks74. The gate spacers86may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers86may be silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers80may not be etched prior to forming the gate spacers86, yielding “L-shaped” gate seal spacers, spacers may be formed and removed, and/or the like). Furthermore, the n-type and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers80while the LDD regions for p-type devices may be formed after forming the gate seal spacers80. InFIGS.16A and16Bepitaxial source/drain regions82are formed in the fins52. The epitaxial source/drain regions82are formed in the fins52such that each dummy gate72is disposed between respective neighboring pairs of the epitaxial source/drain regions82. In some embodiments the epitaxial source/drain regions82may extend into, and may also penetrate through, the fins52. In some embodiments, the gate spacers86are used to separate the epitaxial source/drain regions82from the dummy gates72by an appropriate lateral distance so that the epitaxial source/drain regions82do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions82may be selected to exert stress in the respective channel regions58, thereby improving performance. The epitaxial source/drain regions82in the n-type region50N may be formed by masking the p-type region50P and etching source/drain regions of the fins52in the n-type region50N to form recesses in the fins52. Then, the epitaxial source/drain regions82in the n-type region50N are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the n-type region50N may include materials exerting a tensile strain in the channel region58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions82in the n-type region50N may have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions82in the p-type region50P may be formed by masking the n-type region50N and etching source/drain regions of the fins52in the p-type region50P to form recesses in the fins52. Then, the epitaxial source/drain regions82in the p-type region50P are epitaxially grown in the recesses. The epitaxial source/drain regions82may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions82in the p-type region50P may comprise materials exerting a compressive strain in the channel region58, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions82in the p-type region50P may have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions82and/or the fins52may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 1019cm−3and about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions82may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions82in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent source/drain regions82of a same FinFET to merge as illustrated byFIG.16C. In other embodiments, adjacent source/drain regions82remain separated after the epitaxy process is completed as illustrated byFIG.16D. In the embodiments illustrated inFIGS.16C and16D, gate spacers86are formed covering a portion of the sidewalls of the fins52that extend above the STI regions56thereby blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers86may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region56. InFIGS.17A and17B, a first interlayer dielectric (ILD)88is deposited over the structure illustrated inFIGS.16A and16B. The first ILD88may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)87is disposed between the first ILD88and the epitaxial source/drain regions82, the masks74, and the gate spacers86. The CESL87may comprise a dielectric material, such as, silicon nitride, silicon dioxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD88. InFIGS.18A and18B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD88with the top surfaces of the dummy gates72or the masks74. The planarization process may also remove the masks74on the dummy gates72, and portions of the gate seal spacers80and the gate spacers86along sidewalls of the masks74. After the planarization process, top surfaces of the dummy gates72, the gate seal spacers80, the gate spacers86, and the first ILD88are level. Accordingly, the top surfaces of the dummy gates72are exposed through the first ILD88. In some embodiments, the masks74may remain, in which case the planarization process levels the top surface of the first ILD88with the top surfaces of the masks74. InFIGS.19A and19B, the dummy gates72, and the masks74if present, are removed in an etching step(s), so that recesses90are formed. Portions of the dummy dielectric layer60in the recesses90may also be removed. In some embodiments, only the dummy gates72are removed and the dummy dielectric layer60remains and is exposed by the recesses90. In some embodiments, the dummy dielectric layer60is removed from recesses90in a first region of a die (e.g., a core logic region) and remains in recesses90in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates72are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates72with little or no etching of the first ILD88or the gate spacers86. Each recess90exposes and/or overlies a channel region58of a respective fin52. Each channel region58is disposed between neighboring pairs of the epitaxial source/drain regions82. During the removal, the dummy dielectric layer60may be used as an etch stop layer when the dummy gates72are etched. The dummy dielectric layer60may then be optionally removed after the removal of the dummy gates72. InFIGS.20A and20B, gate dielectric layers92and gate electrodes94are formed for replacement gates.FIG.20Cillustrates a detailed view of region89ofFIG.20B. Gate dielectric layers92may be formed on one or more layers deposited in the recesses90, such as on the top surfaces and the sidewalls of the fins52and on sidewalls of the gate seal spacers80/gate spacers86. The gate dielectric layers92may also be formed on the top surface of the first ILD88. In some embodiments, the gate dielectric layers92comprise one or more dielectric layers, such as one or more layers of silicon dioxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers92include an interfacial layer of silicon dioxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The gate dielectric layers92may include a dielectric layer having a k value greater than about 7.0. The formation methods of the gate dielectric layers92may include Molecular-Beam Deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer60remains in the recesses90, the gate dielectric layers92include a material of the dummy dielectric layer60(e.g., SiO2). The gate electrodes94are deposited over the gate dielectric layers92, respectively, and fill the remaining portions of the recesses90. The gate electrodes94may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode94is illustrated inFIG.20B, the gate electrode94may comprise any number of liner layers94A, any number of work function tuning layers94B, and a fill material94C as illustrated byFIG.20C. After the filling of the recesses90, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers92and the material of the gate electrodes94, which excess portions are over the top surface of the ILD88. The remaining portions of material of the gate electrodes94and the gate dielectric layers92thus form replacement gates of the resulting FinFETs. The gate electrodes94and the gate dielectric layers92may be collectively referred to as a “gate stack.” The gate and the gate stacks may extend along sidewalls of a channel region58of the fins52. The formation of the gate dielectric layers92in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectric layers92in each region are formed from the same materials, and the formation of the gate electrodes94may occur simultaneously such that the gate electrodes94in each region are formed from the same materials. In some embodiments, the gate dielectric layers92in each region may be formed by distinct processes, such that the gate dielectric layers92may be different materials, and/or the gate electrodes94in each region may be formed by distinct processes, such that the gate electrodes94may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. InFIGS.21A and21B, a gate mask96is formed over the gate stack (including a gate dielectric layer92and a corresponding gate electrode94), and the gate mask may be disposed between opposing portions of the gate spacers86. In some embodiments, forming the gate mask96includes recessing the gate stack so that a recess is formed directly over the gate stack and between opposing portions of gate spacers86. A gate mask96comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD88. As also illustrated inFIGS.21A and21B, a second ILD108is deposited over the first ILD88. In some embodiments, the second ILD108is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD108is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. The subsequently formed gate contacts110(FIGS.22A and22B) penetrate through the second ILD108and the gate mask96to contact the top surface of the recessed gate electrode94. InFIGS.22A and22B, gate contacts110and source/drain contacts112are formed through the second ILD108and the first ILD88in accordance with some embodiments. Openings for the source/drain contacts112are formed through the first and second ILDs88and108, and openings for the gate contact110are formed through the second ILD108and the gate mask96. The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD108. The remaining liner and conductive material form the source/drain contacts112and gate contacts110in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions82and the source/drain contacts112. The source/drain contacts112are physically and electrically coupled to the epitaxial source/drain regions82, and the gate contacts110are physically and electrically coupled to the gate electrodes106. The source/drain contacts112and gate contacts110may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts112and gate contacts110may be formed in different cross-sections, which may avoid shorting of the contacts. FIG.23Aillustrates an embodiment in which the capping layer801is initially deposited as an ammonia doped SiCN (instead of SiON as described above with respect toFIG.8A). In this embodiment, the deposition process may use two precursors such as ammonia and trichloro[(trichlorosilyl)methyl]silane. In such an embodiment, the ammonia is pulsed in first in order to react with hydroxyl groups and replace them with nitrogen groups. After the ammonia has been pulsed, the trichloro[(trichlorosilyl)methyl]silane may be pulsed in to react with the nitrogen groups to complete a cycle. The cycle may then be repeated to build up the material of the capping layer801, with the result of two such cycles being illustrated inFIG.23A. FIG.23Billustrates the resulting structure that, once the material for the capping layer801in this embodiment has been deposited, the second annealing process803may be performed in order to transform the deposited material of the capping layer801(e.g., ammonia doped SiCN in this embodiment) to SiOCN, cause an expansion in the material and close any seams, and help prevent etching damage by lowering the etch rate. In this embodiment, however, the second annealing process803is an anneal in an oxygen containing ambient, such as a water containing ambient or an oxygen containing ambient such as oxygen in order to replace some nitrogen groups with oxygen. However, any suitable annealing process may be utilized. The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety. By depositing the third liner601as a first material (e.g., SiON), the benefits of using the first material during the deposition process, such as a reduced amount of oxidation of the underlying fin52, may be achieved. However, by subsequently changing the first material to a second material (e.g., SiO2), better stiffness and device performance can be achieved to help prevent the fins52from bending during subsequent processes, helping to ease the gap fill of subsequently deposited materials. Using a similar process for the deposition of the capping layer801may also achieve the benefits of a first material during deposition and another material during subsequent processing. As such, reduced oxidation and reduced bending of the fins52can be obtained, leading fewer defects and an increased ability to fill the region between the fins52. In accordance with an embodiment, a method of manufacturing a semiconductor device, the method including: forming a recess between a first semiconductor fin and a second semiconductor fin; depositing a first liner to line the recess, the first liner comprising a first material; annealing the first liner to transform the first material to a second material; depositing a second liner to line the recess, the second liner comprising a third material; and annealing the second liner to transform the third material to a fourth material. In an embodiment the first material comprises silicon oxynitride and the second material comprises silicon dioxide. In an embodiment the third material comprises silicon oxycarbonitride and the fourth material comprises silicon dioxide. In an embodiment the annealing the first liner includes: performing a first wet anneal at a first temperature; performing a second wet anneal at a second temperature different from the first temperature; and performing a first dry anneal. In an embodiment the annealing the second liner includes: performing a third wet anneal at a third temperature; performing a fourth wet anneal at a fourth temperature different from the third temperature; and performing a second dry anneal. In an embodiment the depositing the first liner includes: pulsing hexachlorodisilane onto the first semiconductor fin; pulsing oxygen onto the first semiconductor fin after the pulsing the hexachlorodisilane; and pulsing ammonia onto the first semiconductor fin after the pulsing the oxygen. In an embodiment the depositing the second liner includes: pulsing hexachlorodisilane onto the first semiconductor fin; pulsing triethylamine onto the first semiconductor fin after the pulsing the hexachlorodisilane; and pulsing oxygen onto the first semiconductor fin after the pulsing the triethylamine. In accordance with another embodiment, a semiconductor device includes: a first semiconductor fin and a second semiconductor fin over a semiconductor substrate; a first liner adjacent to both the first semiconductor fin and the second semiconductor fin; a second liner over the first liner; a third liner over the second liner, the third liner comprising nitrogen at a percentage of less than about 10%; a fourth liner over the third liner; a capping layer over the fourth liner, the capping layer comprising carbon at a percentage of less than about 10%; and a dielectric cap over the capping layer, wherein the first semiconductor fin extends further away from the semiconductor substrate than the dielectric cap. In an embodiment, the capping layer has a thickness of between about 10 Å and about 70 Å. In an embodiment, the third liner has a thickness of between about 10 Å and about 50 Å. In an embodiment, the second liner comprises silicon dioxide. In an embodiment, the capping layer comprises silicon dioxide. In an embodiment, the first liner is silicon. In accordance with yet another embodiment, a semiconductor device includes: a first semiconductor fin adjacent to a second semiconductor fin, the first semiconductor fin over a semiconductor substrate; a first isolation region extending from a first sidewall of the first semiconductor fin to a second sidewall of the second semiconductor fin, the first isolation region including: a first liner extending from the first semiconductor fin to the second semiconductor fin, the first liner comprising a first material; a second liner over the first liner, the second liner comprising a second material; a third liner over the second liner, the third liner comprising a third material, the third material have nitrogen at a percentage of less than about 10%; a fourth liner over the third liner, the fourth liner comprising a fourth material; a capping layer over the fourth liner, the capping layer comprising a capping material, the capping material comprising carbon at a percentage of less than about 10%; and a dielectric cap over the capping layer, wherein the first isolation region has a top surface closer to the semiconductor substrate than the first semiconductor fin; and a second isolation region adjacent to the first semiconductor fin, the second isolation region including: a fifth liner adjacent to the first semiconductor fin, the fifth liner comprising the first material; a sixth liner over the fifth liner, the sixth liner comprising the second material; a seventh liner over the sixth liner, the seventh liner comprising the third material; an eighth liner over the seventh liner, the eighth liner comprising the fourth material; a second capping layer over the eighth liner, the second capping layer comprising the capping material; a second dielectric cap over the second capping layer; and a dielectric fin extending into at least the second dielectric cap, a portion of the dielectric fin being planar with the first semiconductor fin, wherein there is no dielectric fin extending into the first isolation region. In an embodiment the capping layer has a thickness of between about 10 Å and about 70 Å. In an embodiment the third liner has a thickness of between about 10 Å and about 50 Å. In an embodiment the second liner comprises silicon dioxide. In an embodiment the capping layer comprises silicon dioxide. In an embodiment the first liner is silicon. In an embodiment the first semiconductor fin is separated from the second semiconductor fin by a distance of between about 5 nm and about 30 nm. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 103,227 |
11942550 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “on,” “above,” “over,” “downwardly,” “upwardly,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIG.1illustrates a schematic view of a nanosheet semiconductor device in accordance with some embodiments. A nanosheet FET semiconductor device1includes a plurality of source/drain regions10, a plurality of channel regions20, a plurality of gate structures30, and a plurality of contact plugs40. The source/drain regions10and the channel regions20are formed on a substrate5(for example but not limited to a silicon substrate). Two adjacent ones of the source/drain regions10are separated from each other by a corresponding one of the channel regions20. The source/drain regions10are formed by growing an epitaxial layer along nanosheets21(for example but not limited to silicon nanhosheets) of the channel regions20. In addition, the source/drain regions10may be doped with germanium (Ge), boron (B), phosphorus (P), or arsenic (As). For example, in some embodiments, the epitaxial layer is grown along the nanosheets21of the channel regions20through an epitaxial growth process with, for example, phosphorus doping when the source/drain regions10to be formed are n-FET source/drain regions. In some embodiments, the epitaxial layer is grown along the nanosheets21of the channel regions20through an epitaxial growth process with, for example, geranium doping when the source/drain regions10to be formed are p-FET source/drain regions. Each of the gate structures30includes a top gate portion disposed over a corresponding one of the channel regions20and a lower gate portion surrounding the nanosheets21of the channel regions20. Each of the gate structure30includes a gate dielectric layer31and a metal filling layer32surrounded by the gate dielectric layer31. The contact plugs40extend through an interlayer dielectric (ILD) layer50and a contact etch stop layer (CESL)60to contact the source/drain regions10. The gate dielectric layer31of the upper gate portion of each of the gate structures30is separated from the ILD layer50by dummy spacers70. The gate dielectric layer31of the lower gate portion of each of the gate structures30is separated from corresponding ones of the source/drain regions10by inner spacers80. FIG.2illustrates a method100for manufacturing a nanosheet semiconductor device in accordance with some embodiments.FIGS.3to20illustrate schematic views of a nanosheet semiconductor device200during various stages of the method100ofFIG.2. The method100and the nanosheet semiconductor device200are collectively described below. However, additional steps can be provided before, after or during the method100, and some of the steps described herein may be replaced by other steps or be eliminated. Similarly, further additional features may be present in the nanosheet semiconductor device200, and/or features present may be replaced or eliminated in additional embodiments. Referring toFIG.2, the method100begins at block102, where a gate dielectric layer, a polysilicon layer, and a hard mask layer are deposited sequentially on a nanosheet stack. Referring to the example illustrated inFIG.3, a gate dielectric layer230, a polysilicon layer240, and a hard mask layer250are deposited sequentially on a nanosheet stack220. The nanosheet stack220is formed on a substrate210, and includes a plurality of first nanosheets221and a plurality of second nanosheets222, which are alternately stacked on the substrate210. In some embodiments, the substrate210may include, for example but not limited to, silicon (Si). The first nanosheet221may include, for example but not limited to, silicon germanium (SiGe). The second nanosheet222may include, for example but not limited to, silicon (Si). The gate dielectric layer230is formed to have a suitable thickness over the nanosheet stack220by a suitable process, which includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), plating, other suitable methods, and combinations thereof. The gate dielectric layer230may be made of, for example but not limited to, silicon oxide, silicon oxynitride, silicon nitride, spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide, BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), XEROGEL, AEROGEL, amorphous fluorinated carbon, Parlyene, BCB (bis-benzocyclobutenes), SILK® (Dow Chemical, Midland, Mich.), polyimide, other suitable dielectric materials, or combinations thereof. In addition, the gate dielectric layer230may includes a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or combinations thereof. The gate dielectric layer230may further include an interfacial layer, which comprises a grown silicon oxide layer (e.g., thermal oxide or chemical oxide) or silicon oxynitride (SiON). The polysilicon layer240may be formed to have a suitable thickness over the gate dielectric layer230by a suitable process, which includes CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, plating, other suitable methods, and combinations thereof. In some embodiments, the polysilicon layer240may be formed by CVD using silane (SiH4) as a chemical gas to form the polysilicon layer240. The polysilicon layer240may include a thickness ranging from about 400 angstrom (Å) to about 800 Å. In some embodiments, the gate dielectric layer230and the polysilicon layer240may be sacrificial layers and will be removed by a replacement step. In some embodiments, the hard mask layer250may include, for example but not limited to, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), spin-on glass (SOG), a low-k film, tetraethyl orthosilicate (TEOS), plasma enhanced CVD oxide, high-aspect-ratio-process (HARP) formed oxide, amorphous carbon material, tetraethylorthosilicate (TEOS), other suitable materials, or combinations thereof. The hard mask layer250may be formed using methods such as, for example but not limited to, CVD, PVD, ALD, spin-on coating, or the like, and may have a thickness ranging from about 300 Å to about 800 Å. Referring toFIG.2, the method100then proceeds to block104, where a plurality of poly gates are formed. Referring to the example illustrated inFIGS.3and4, the hard mask layer250is patterned using photolithography and photoresist developing technology as known to those skilled in the art of semiconductor fabrication. For example, the hard mask layer250may be patterned by 193 nm immersion lithography or extreme ultraviolet (EUV) lithography. The pattern formed in the hard mask layer250is then transferred to the polysilicon layer240and the gate dielectric layer230by an etching process (for example but not limited to, wet etching, dry etching, or a combination thereof) to form a plurality of poly gates260, each of which includes the gate dielectric layer230disposed on the nanosheet stack220, the polysilicon layer240disposed on the gate dielectric layer230, and the hard mask layer250disposed on the polysilicon layer240. Referring toFIG.2, the method100then proceeds to block106, where a dummy spacer layer is conformally deposited on the poly gates. Referring to the example illustrated inFIG.5, a dummy spacer layer270is conformally deposited to cover the poly gates260and the nanosheet stack220. The conformal deposition may be implemented by a suitable deposition process as known to those skilled in the art of semiconductor fabrication, for example but not limited to, PVD, CVD, PECVD, ALD, plasma-enhanced atomic layer deposition (PEALD), etc., or combinations thereof. Examples of a material suitable for forming the dummy spacer layer270include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof, but are not limited thereto. Referring toFIG.2, the method100then proceeds to block108, where the dummy spacer layer is formed into a plurality of dummy spacers to laterally cover the poly gates. Referring to the example illustrated inFIGS.5and6, the dummy spacer layer270is anisotropically etched to etch away the horizontal portions of the dummy spacer layer270to form a plurality of dummy spacers271extending upwardly from the nanosheet stack220and laterally covering the poly gates260. Referring toFIG.2, the method100then proceeds to block110, where the nanosheet stack is recesses to form a plurality of source/drain recesses. Referring to the example illustrated inFIGS.6and7, the nanosheet stack220are recessed by an anisotropic etching process to form a plurality of source/drain recesses290and a plurality of channel regions280. Adjacent two of the channel regions280are separated from each other by a corresponding one of the source/drain recesses290. The anisotropic etching process may be a suitable anisotropic etching as known to those skilled in the art of semiconductor fabrication, for example but not limited to, anisotropic dry etching. Referring toFIG.2, the method100then proceeds to block112, where the first nanosheets are laterally etched. Referring to the example illustrated inFIG.8, the first nanosheets221are laterally recessed by an isotropic etching process to remove side portions of the first nanosheets221based on a relatively high etching selectivity of the first nanosheets221with respect to the second nanosheets222, so as to form first lateral recesses281. Referring toFIG.2, the method100then proceeds to block114, where an inner spacer layer is conformally deposited. Referring to the example illustrated inFIG.9, an inner spacer layer300is conformally deposited to cover the poly gates260, the dummy spacers271, the channel regions280, and the substrate210. As described above, the conformal deposition may be implemented by a suitable deposition process as known to those skilled in the art of semiconductor fabrication, for example but not limited to, PVD, CVD, PECVD, ALD, PEALD, etc., or combinations thereof. Examples of a material suitable for forming the inner spacer layer300may include silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof, but are not limited thereto. Referring toFIG.2, the method100then proceeds to block116, where the inner spacer layer is formed into a plurality of inner spacers to laterally cover the first nanosheets. Referring to the example illustrated inFIGS.9and10, the inner spacer layer300is subjected to an isotropic etching process to form a plurality of inner spacers301in the first lateral recesses281to laterally cover the first nanosheets221. The isotropic etching process may be dry isotropic etching, wet isotropic etching, or a combination thereof. Referring toFIG.2, the method100then proceeds to block118, where the second nanosheets are laterally etched. Referring to the example illustrated inFIG.11, the second nanosheets222are laterally recessed by isotropic etching to perform a proximity push process to remove side portions of the second nanosheets222based on a relatively high etching selectivity of the second nanosheets222with respect to the inner spacers301and the dummy spacers271, so as to form second lateral recesses282. The second lateral recesses282are spatially communicated with the source/drain recesses290. Referring toFIG.2, the method100then proceeds to block120, where source/drain regions are formed in the source/drain recesses. Referring to the example illustrated inFIGS.11and12, source/drain regions310are formed by growing an epitaxial layer in the source/drain recesses290along the inner spacers301and the second nanosheets222through epitaxial growth. In some embodiments, the technique for the epitaxial growth may include a low pressure CVD (LPCVD) process, an atomic layer CVD (ALCVD) process, an ultrahigh vacuum CVD (UHVCVD) process, a reduced pressure CVD (RPCVD) process, a molecular beam epitaxy (MBE) process, a metalorganic vapor phase epitaxy (MOVPE) process, and combinations thereof, but may not be limited thereto. In some embodiments, the technique for the epitaxial growth may include a cyclic deposition-etch (CDE) epitaxy process, a selective epitaxial growth (SEG) process, and the like, but may not be limited thereto. The source/drain regions310may be doped with germanium (Ge), boron (B), phosphorus (P), or arsenic (As). For example, in some embodiments, the epitaxial layer is grown in the source/drain recesses290along the inner spacers301and the second nanosheets222through an epitaxial growth process with, for example, phosphorus doping when the source/drain regions310to be formed are n-FET source/drain regions. In some embodiments, the epitaxial layer is grown in the source/drain recesses290along the inner spacers301and the second nanosheets222through an epitaxial growth process with, for example, geranium doping when the source/drain regions310to be formed are p-FET source/drain regions. Referring toFIG.2, the method100then proceeds to block122, where a contact etch stop layer is formed. Referring to the example illustrated inFIG.13, a contact etch stop layer (CESL)320is conformally deposited to cover the source/drain regions310, the dummy spacers271, and the poly gates260. Examples of a material suitable for forming the CESL320may include silicon nitride, carbon-doped silicon nitride, and the like, but are not limited thereto. The CESL320may have a suitable thickness. In some embodiments, the CESL320may have a thickness in the range of about 180 Å to about 220 Å. In some embodiments, the CESL320may be deposited using, for example but not limited to, CVD, HDPCVD, sub-atmospheric CVD (SACVD), molecular layer deposition (MLD), sputtering, or other suitable methods. For example, in some embodiments, the MLD process is generally carried out under a pressure less than 10 mTorr and in a temperature ranging from about 350° C. to about 500° C. In some embodiments, the silicon nitride is deposited by reacting a silicon source compound and a nitrogen source. The silicon source compound provides silicon for the deposited silicon nitride and may be silane (SiH4), tetrathoxysilane (TEOS), or the like. The nitrogen source provides nitrogen for the deposited silicon nitride and may be ammonia (NH3), nitrogen gas (N2), or the like. In some embodiments, the carbon-doped silicon nitride is deposited by reacting a carbon source compound, a silicon source compound, and a nitrogen source. The carbon source compound may be an organic compound, such as a hydrocarbon compound, e.g., ethylene (C2H4). Referring toFIG.2, the method100then proceeds to block124, where an interlayer dielectric layer is formed. Referring to the example illustrated inFIG.14, an interlayer dielectric (ILD) layer330is deposited over the CESL320. Because the semiconductor device pitch is scaling down, the material of the ILD layer330needs to have good gap-fill capability to fill the spaces among the poly gates260. The ILD layer330is made of a dielectric material. In some embodiments, examples of the the dielectric material may includes silicon oxide, silicon nitride, silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB (bis-benzocyclobutenes), Flare, SILK® (Dow Chemical, Midland, Mich.), polyimide, and combinations thereof, but are not limited thereto. In some embodiments, the ILD layer330may be deposited over the CESL320to a suitable thickness by, for example but not limited to, CVD, HDPCVD, SACVD, spin-on, sputtering, or other suitable methods. In some embodiments, the ILD layer330may have a thickness in the range from about 3000 Å to about 4500 Å. Referring toFIG.2, the method100then proceeds to block126, where the nanosheet semiconductor device is planarized. Referring to the example illustrated inFIGS.14and15, the nanosheet semiconductor device200is subjected to a planarization process (for example but not limited to, chemical mechanical planarization (CMP)) to remove an excess portion of the ILD layer330, portions of the CESL320, portions of the dummy spacers271, and the hard mask layer250until a top surface of the polysilicon layer240of each of the poly gates260is exposed. Referring toFIG.2, the method100then proceeds to block128, where the poly gates and the first nanosheets are removed. Referring to the example illustrated inFIGS.15and16, the polysilicon layer240, the gate dielectric layer230, and the first nanosheets221are removed by one or more etching processes (for example but not limited to, wet etching, dry etching, or a combination thereof) to form first voids241defined by the dummy spacers271and second voids223defined by the inner spacers301and the second nanosheets222. In some embodiments, the polysilicon layer240and the gate dielectric layer230are first removed to form the first voids241, and the first nanosheets221are then removed to form the second voids223. Referring toFIG.2, the method100then proceeds to block130, where a gate dielectric layer and a metal filling layer are sequentially formed. Referring to the example illustrated inFIGS.16and17, a gate dielectric layer340and a metal filling layer350are sequentially formed in the first voids241and the second voids223, and over the ILD layer330, the CESL320, and the dummy spacers271through a deposition process, such as, for example but not limited to, CVD, HDPCVD, SACVD, MLD, PVD, sputtering, etc. The gate dielectric layer340may include a sub-layer of an interlayer dielectric material and a sub-layer of a high dielectric constant (k) material. Examples of the interlayer dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto. The metal filling layer350may include a barrier sub-layer, a work function sub-layer, and a filling material sub-layer. The barrier sub-layer may prevent diffusion of metal into the gate dielectric layer340. Examples of a material suitable for the work function sub-layer may include titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, and combinations thereof, but are not limited thereto. Examples of a material suitable for the filling material sub-layer may include aluminum, tungsten, copper, and other conductive metals, but are not limited thereto. Referring toFIG.2, the method100then proceeds to block132, where an excess portion of the metal filling layer and top portions the gate dielectric layer are removed. Referring to the example illustrated inFIGS.17and18, an excess portions of the metal filling layer350and top portions of the gate dielectric layer340over the ILD layer330, the CESL320, and the dummy spacers271are removed trough a planarization process such as, for example but not limited to, CMP to form gate structures360, each of which includes a top gate portion disposed over a corresponding one of the channel regions280and a lower gate portion surrounding the second nanosheets222. Each of the inner spacers301laterally covers the lower gate portion of a corresponding one of the gate structures360to separate the lower gate portion of the corresponding one of the gate structures360from a corresponding one of the source/drain regions310. Referring toFIG.2, the method100then proceeds to block134, where the ILD layer and the CESL are etched to form contact openings. Referring to the example illustrated inFIG.19, a part of the ILD layer330and a part of the CESL320are etched through a patterned photoresist (not shown) to form contact openings331. The contact openings331are formed to expose the source/drain regions310. Formation of the contact openings331may be implemented using a suitable etching process known in the art, for example but not limited to, a dry etching process, a wet etching process, or a combination thereof. Referring toFIG.2, the method100then proceeds to block136, where contact plugs are formed. Referring to the example illustrated inFIGS.19and20, a conductive material is filled in the contact openings331by a suitable deposition method known in the art, for example but not limited to, ALD or the like to form contact plugs370, which extend through the ILD layer330and the CESL320to contact the source/drain regions310. In some embodiments, the conductive material suitable for the contact plugs370may include, for example but not limited to, tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN). other metal(s) or metal alloys, or the like. Referring toFIGS.21and22, which illustrates schematic views for comparing epitaxial widths between the nanosheet semiconductor device1in accordance with some embodiments without implementation of the proximity push process and the nanosheet semiconductor device200in accordance with some embodiments with implementation of the proximity push process. As shown inFIG.21, the nanosheet semiconductor device1has an epitaxial width, as shown with a reference “a” inFIG.21. The epitaxial width (a) is defined by a distance between the nanosheets21at two opposite sides of a corresponding one of the source/drain regions10. As shown inFIG.22, the nanosheet semiconductor device200has an epitaxial width, as shown with a reference “b” inFIG.22. Similarly, the epitaxial width (b) is defined by a distance between the second nanosheets222at two opposite sides of a corresponding one of the source/drain regions310. It is apparent that the epitaxial width (b) in the source/drain regions310of the nanosheet semiconductor device200is greater than the epitaxial width (a) in the source/drain regions10of the nano sheet semiconductor device1. It indicates that the epitaxial width (b) in the source/drain regions310of the nanosheet semiconductor device200is increased with implementation of the proximity push process. In other words, the volume of the source/drain regions310of the nanosheet semiconductor device200is increased as compared to the volume of the source/drain regions10of the nanosheet semiconductor device1. Therefore, a channel strain in the channel regions280of the nanosheet semiconductor device200can be boosted accordingly, so that the carrier mobility for the nanosheet semiconductor device200can be enhanced. FIGS.23and24, illustrate schematic views for comparing a proximity and an inner spacer lateral thickness of the nanosheet semiconductor device1without implementation of the proximity push process, in which the proximity is defined by a distance between a first reference line L1and a second reference line L2. The first reference line L1is defined by an interface between the nanosheet21and a corresponding one of the source/drain regions10. The second reference line L2is defined by an interface between the gate structure30and the inner spacer80. In the nanosheet semiconductor device1, the proximity is greater than the inner spacer lateral thickness because the proximity push process is not implemented. FIGS.25and26illustrate schematic views for comparing a proximity and an inner spacer lateral thickness of the nanosheet semiconductor device200with implementation of the proximity push process, in which the proximity is defined by a distance between a first reference line L1and a second reference line L2. Similarly, the first reference line L1is defined by an interface between the nanosheet222and a corresponding one of the source/drain regions310. The second reference line L2is defined by an interface between the gate structure360and the inner spacer301. In the nanosheet semiconductor device200, the proximity is less than the inner spacer lateral thickness due to that the proximity push process is implemented. In other words, the nanosheet222includes a lateral surface contacting the corresponding one of the source/drain regions310. The inner spacer301includes a lateral surface contacting the corresponding one of the source/drain regions310and opposite to the gate structure360. The lateral surface of the nanosheet222is indented relative to the lateral surface of the inner spacer301. FIG.27illustrates a schematic view specifically showing an interface between a nanosheet and a corresponding one of source/drain regions in a nanosheet semiconductor device in accordance with some embodiment.FIG.28is a plot showing how to define the interface. In some embodiments in which the nanosheet is a silicon nanosheet and the source/drain regions are SiGe source/drain regions, the interface between a nanosheet and a corresponding one of the source/drain regions in the nanosheet semiconductor device may be defined to be at a location where an image intensity is a half of a difference between maximum and minimum image intensities in a plot obtained from a Z-contrast image (an atomic number contrast image) of transmission electron microscopy (TEM). Referring toFIG.29, in some embodiments in which the nanosheet222are silicon nanosheets and the source/drain regions310are SiB source/drain regions (i.e., source/drain regions doped with boron (B)), the interface between the nanosheet222and a corresponding one of the source/drain regions310in the nanosheet semiconductor device200may be defined to be at a location where an image intensity is a half of a difference between maximum and minimum image intensities in a plot obtained from electron energy loss spectroscopy (EELS). Referring toFIG.30, in some embodiment in which the nanosheets222are silicon nanosheets and the source/drain regions310are SiAs source/drain regions (i.e., source/drain regions doped with arsenic (As)), the interface between the nanosheet222and a corresponding one of the source/drain regions310in the nanosheet semiconductor device200may be defined to be at a location where an image intensity is a half of a difference between maximum and minimum image intensities in a plot obtained from energy dispersive X-ray spectroscopy (EDX). Referring toFIG.31, which illustrates a schematic view specifically showing inner spacers in a nanosheet semiconductor device in accordance with some embodiment, the inner spacer lateral thickness may be may be determined by a location where an image intensity is a half of a difference between maximum and minimum image intensities in a plot obtained from EDX. Referring toFIGS.32and33, which illustrate schematic views specifically showing the proximity and the inner spacer lateral thickness of the nanosheet semiconductor device1in accordance with some embodiment without implementation of the proximity push process, the proximity is greater than 8 nanometers (nm). Referring toFIGS.34to37, which illustrate schematic views specifically showing the proximity and the inner spacer lateral thickness of the nanosheet semiconductor device200in accordance with some embodiment with implementation of the proximity push process, the proximity can be reduced to a range from 0 nm to 8 nm by the proximity push process. Referring toFIGS.38to42, the lateral surfaces of the second nanosheets222of the nanosheet semiconductor device200in accordance with some embodiment may be, for example but not limited to, a smooth convex as shown inFIG.38, a convex with a pointed tip as shown inFIG.39, a flat surface shown inFIG.40, a concave with a pointed bottom as shown inFIG.41, a smooth concave as shown inFIG.42, or the like. Referring toFIGS.43and44, in addition to the nanosheet semiconductor device200shown inFIGS.38to42, in which the number of the second nanosheets222surrounded by the lower gate portion of the gate structure360in each of the channel regions280is three, the number of the second nanosheets222surrounded by the lower gate portion of the gate structure360in each of the channel regions280may be four as shown inFIG.43, five as shown inFIG.44, or more. In the method for manufacturing the nanosheet semiconductor device200in accordance with some embodiments, the second nanosheets222are laterally recessed to implement the proximity push process to remove the side portions of the second nanosheets222, so as to form the second lateral recesses282spatially communicated with the source/drain recesses290. Therefore, the epitaxial width (b) in the source/drain regions310of the nanosheet semiconductor device200can be increased. In other words, the volume for forming the source/drain regions310of the nanosheet semiconductor device200is increased as compared to the volume for forming the source/drain regions10of the nanosheet semiconductor device1without implementation of the proximity push process. A channel strain in the channel regions280of the nanosheet semiconductor device200can be boosted accordingly, so that the carrier mobility for the nanosheet semiconductor device200can be enhanced. In accordance with some embodiments of the present disclosure, a method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet. In accordance with some embodiments of the present disclosure, a nanosheet semiconductor device includes a channel region, a first source/drain region, a second source/drain region, a gate structure, and an inner spacer. The channel region includes at least one nanosheet. The first and second source/drain regions are separated from each other by the channel region. The gate structure includes an upper gate portion disposed over the channel region and a lower gate portion surrounding the at least one nanosheet. The inner spacer laterally covers the lower gate portion of the gate structure. The at least one nanosheet includes a lateral surface contacting a corresponding one of the first and second source/drain regions. The inner spacer includes a lateral surface contacting the corresponding one of the first and second source/drain regions. The lateral surface of the at least one nanosheet is indented relative to the lateral surface of the inner spacer. In accordance with some embodiments of the present disclosure, a nanosheet semiconductor device includes a channel region, a first source/drain region, a second source/drain region, a gate structure, and an inner spacer. The channel region includes at least one nanosheet. The first and second source/drain regions are separated from each other by the channel region. The gate structure includes an upper gate portion disposed over the channel region and a lower gate portion surrounding the at least one nanosheet. The inner spacer laterally covers the lower gate portion of the gate structure. An interface between the at least one nanosheet and a corresponding one of the first and second source/drain regions defines a first reference line. An interface between the inner spacer and the lower gate portion of the gate structure defines a second reference line. A distance between the first and second reference lines is less than a lateral thickness of the inner spacer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 33,769 |
11942551 | DETAILED DESCRIPTION In the drawings of a semiconductor device according to some exemplary embodiments, a transistor including nanowires or nano-sheets, a multi-bridge channel field-effect transistor (MBCFET™), and a fin-shaped field-effect transistor (FinFET) including a channel region having a fin-shaped pattern are illustratively shown, but the present disclosure is not limited thereto. The semiconductor device according to some exemplary embodiments may include a tunneling field-effect transistor (tunneling FET), a three-dimensional (3D) transistor, or a two-dimensional (2D) material-based transistor (2D material-based FET), and a heterostructure thereof. In addition, the semiconductor device according to some example exemplary embodiments may also include a bipolar junction transistor, a laterally-diffused metal-oxide semiconductor (LDMOS) transistor, or the like. Referring toFIGS.1to12, a semiconductor device according to some exemplary embodiments will be described. FIG.1is an exemplary plan view for describing the semiconductor device according to some exemplary embodiments.FIGS.2to4are cross-sectional views taken along lines A-A, B-B, and C-C ofFIG.1, respectively.FIG.5is a view for describing a shape of a first sheet pattern ofFIG.2.FIG.6is an exemplary view for describing a three-dimensional shape of a semiconductor liner layer ofFIG.2.FIG.7is an exemplary view for describing a three-dimensional shape of each of a lower semiconductor insertion layer and an upper semiconductor insertion layer ofFIG.2.FIGS.8to10are cross-sectional views taken along lines D-D, E-E, and F-F ofFIG.2, respectively.FIGS.11and12are schematic views illustrating a germanium fraction along a scan line ofFIG.2. For reference,FIG.2is a cross-sectional view taken along a first lower pattern BP1extending in a first direction D1.FIGS.8to10are cross-sectional views respectively shown on a D1-D2plane.FIG.1is a plan view illustrated on the D1-D2plane, and thusFIGS.8to10may be cross-sectional views each illustrated in a plan view.FIG.8is a cross-sectional view taken along a first sheet pattern NS1.FIGS.9and10may each be a cross-sectional view taken along a space between the first sheet patterns NS1adjacent to each other in a third direction D3. FIG.1is a simplified view excluding a first gate insulating layer130, an etch stop layer185, an interlayer insulating layer190, and the like. Referring toFIGS.1to12, the semiconductor device according to some exemplary embodiments may include a first active pattern AP1, a plurality of first gate structures GS1, and a first source/drain pattern150. The semiconductor device may include a substrate100. The substrate100may be bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate100may be a silicon substrate or may include another material such as silicon germanium, a silicon-germanium on insulator (SGOI), indium antimonide, a lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The present disclosure is not limited to these examples. The first active pattern AP1may be on the substrate100. The first active pattern AP1may be elongated in the first direction D1. For example, the first active pattern AP1may be in a region in which a p-type metal-oxide-semiconductor (PMOS) is formed. The first active pattern AP1may be, for example, a multi-channel active pattern. In the semiconductor device according to some exemplary embodiments, the first active pattern AP1may include the first lower pattern BP1and a plurality of first sheet patterns NS1. The first lower pattern BP1may protrude from the substrate100. The first lower pattern BP1may be elongated in the first direction D1. The plurality of first sheet patterns NS1may be on an upper surface BP1_US of the first lower pattern BP1. The plurality of first sheet patterns NS1may be spaced apart from the first lower pattern BP1in the third direction D3, as best seen inFIG.3. The first sheet patterns NS1may be spaced apart from each other in the third direction D3. Each of the first sheet patterns NS1may include an upper surface NS1_US and a lower surface NS1_BS. The upper surface NS1_US of one of the first sheet patterns is a surface opposite to the lower surface NS1_BS of the one first sheet pattern in the third direction D3. Each of the first sheet patterns NS1may include first sidewalls NS1_SW1opposite to each other in the first direction D1and second sidewalls NS1_SW2opposite to each other in a second direction D2. The upper surface NS1_US of the first sheet pattern may be connected to the lower surface NS1_BS of the first sheet pattern through the first sidewalls NS1_SW1and the second sidewalls NS1_SW2of the first sheet pattern. The first sidewall NS1_SW1of the first sheet pattern is connected to and in contact with the first source/drain pattern150to be described below. The first sidewall NS1_SW1of the first sheet pattern may be an end of the first sheet pattern NS1. InFIG.8, the first sidewall NS1_SW1of the first sheet pattern is illustrated as having a curved surface, but the present disclosure is not limited thereto. Unlike that illustrated in the drawings, in some embodiments, the first sidewall NS1_SW1of the first sheet pattern may include a planar portion and a curved portion. In some embodiments, the entire first sidewall NS1_SW1of the first sheet pattern may be planar. In addition, inFIGS.3and5, the second sidewall NS1_SW2of the first sheet pattern is illustrated as being a combination of a curved portion and a planar portion, but the present disclosure is not limited thereto. That is, the entire second sidewall NS1_SW2of the first sheet pattern may be a curved surface, or may be planar. The third direction D3may be a direction crossing the first direction D1and the second direction D2. For example, the third direction D3may be a thickness direction of the substrate100. The first direction D1may be a direction crossing the second direction D2. The third direction D3may be a vertical direction and the first and second directions D1and D2may be horizontal directions. It is illustrated in the drawing that three first sheet patterns NS1are spaced apart from each other in the third direction D3, but this is only for convenience of description, and the present disclosure is not limited thereto. The first lower pattern BP1may be formed by etching a portion of the substrate100and may include an epitaxial layer grown from the substrate100. The first lower pattern BP1may include silicon or germanium, which is an elemental semiconductor material. In addition, the first lower pattern BP1may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element in the binary or ternary compound. The group III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, and a quaternary compound, which is formed by a combination of at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element, with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group V element. The first sheet pattern NS1may include one of silicon or germanium, which is an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each of the first sheet patterns NS1may include the same material as the first lower pattern BP1and may include a material different from that of the first lower pattern BP1. In the semiconductor device according to some exemplary embodiments, the first lower pattern BP1may be a silicon lower pattern including silicon, and the first sheet pattern NS1may be a silicon sheet pattern including silicon. A width of each the first sheet patterns NS1in the second direction D2may increase or decrease in proportion to a width of the first lower pattern BP1in the second direction D2. For example, it is illustrated in the figures that the widths in the second direction D2of the first sheet patterns NS1, which are stacked in the third direction D3, are the same, but this is only for convenience of description, and the present disclosure is not limited thereto. In some embodiments, unlike that illustrated in the drawings, the widths of the first sheet patterns NS1in the second direction D2, which are stacked in the third direction D3, may be reduced as a distance from the first lower pattern BP1increases. A field insulating layer105may be formed on the substrate100. The field insulating layer105may be on a sidewall of the first lower pattern BP1. The field insulating layer105may be absent from the upper surface BP1_US of the first lower pattern. In some embodiments, the field insulating layer105may entirely cover the sidewall of the first lower pattern BP1. In some embodiments, unlike that illustrated in the drawings, the field insulating layer105may cover a portion of the sidewall of the first lower pattern BP1. In this case, a portion of the first lower pattern BP1may protrude further than an upper surface of the field insulating layer105in the third direction D3. Each of the first sheet patterns NS1may be arranged higher than the upper surface of the field insulating layer105. The field insulating layer105may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. The field insulating layer105is illustrated as being a single layer, but this is only for convenience of description, and the present disclosure is not limited thereto. The plurality of first gate structures GS1may be on the substrate100. Each of the first gate structures GS1may extend in the second direction D2. The first gate structures GS1may be arranged to be spaced apart from each other in the first direction D1. The first gate structures GS1may be adjacent to each other in the first direction D1. The first gate structures GS1may be on the first active pattern AP1. The first gate structures GS1may intersect or cross the first active pattern AP1. The first gate structures GS1may intersect or cross the first lower pattern BP1. The first gate structures GS1may surround the respective first sheet patterns NS1. The first gate structure GS1may include, for example, a first gate electrode120, the first gate insulating layer130, a first gate spacer140, and a first gate capping pattern145. The first gate electrode120may be formed on the first lower pattern BP1. The first gate electrode120may intersect the first lower pattern BP1. The first gate electrode120may surround the first sheet pattern NS1. A portion of the first gate electrode120may be between the first sheet patterns NS1adjacent to each other in the third direction D3. When the semiconductor device includes a first of the first sheet patterns and a second of the first sheet patterns, which are adjacent to each other, a portion of the first gate electrode120may be between the upper surface NS1_US of the first of the sheet patterns and the lower surface NS1_BS of the second of the first sheet patterns facing each other. The first gate electrode120may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode120may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminide (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination of any of the above, but the present disclosure is not limited thereto. The conductive metal oxide and the conductive metal oxynitride may be included in an oxidized form of the above-described materials, but the present disclosure is not limited thereto. The first gate electrodes120may be on both sides of the first source/drain pattern150to be described below. The first gate structures GS1may be on both sides of the first source/drain pattern150in the first direction D1. In some embodiments, all of the first gate electrodes120on both sides of the first source/drain pattern150may be normal gate electrodes used as a gate of a transistor. In some embodiments, the first gate electrode120on one side of the first source/drain pattern150may be used as a gate of the transistor, but the first gate electrode120on the other side of the first source/drain pattern150may be a dummy gate electrode. The first gate insulating layer130may extend along the upper surface of the field insulating layer105and the upper surface BP1_US of the first lower pattern. The first gate insulating layer130may surround the plurality of first sheet patterns NS1. The first gate insulating layer130may be along a circumference of each of the first sheet patterns NS1. The first gate electrode120may be on the first gate insulating layer130. The first gate insulating layer130may be between the first gate electrode120and the first sheet patterns NS1. A portion of the first gate insulating layer130may be between the first sheet patterns NS1adjacent to each other in the third direction D3. When the semiconductor device includes the first of the first sheet patterns and the second of the first sheet patterns adjacent to each other, a portion of the first gate insulating layer130may extend along the upper surface NS1_US of the first of the first sheet patterns and the lower surface NS1_BS of the second of the first sheet patterns facing each other. The first gate insulating layer130may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant (high-k) material having a higher dielectric constant than silicon oxide. The high-k material may include, as non-limiting examples, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead-zinc niobate. The first gate insulating layer130is illustrated as being a single layer, but this is only for convenience of description, and the present disclosure is not limited thereto. The first gate insulating layer130may include a plurality of layers. The first gate insulating layer130may include an interfacial layer between the first sheet pattern NS1and the first gate electrode120, and a high-k insulating layer. The semiconductor device according to some exemplary embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the first gate insulating layer130may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties. The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the sum of the capacitances of the two or more capacitors is less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the sum of the capacitances of the two or more capacitors may have a positive value and may be greater than the absolute value of each individual capacitance. When a ferroelectric material layer having a negative capacitance and a paraelectric material layer having a positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series may increase. Using the fact that the total capacitance value increases, a transistor including the ferroelectric material layer may have a subthreshold swing (SS) of less than 60 mV/decade at room temperature. The ferroelectric material layer of the first gate insulating layer130may have ferroelectric properties. The ferroelectric material layer may include, as non-limiting examples, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In some embodiments, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In some embodiments, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O). The ferroelectric material layer may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on the type of ferroelectric material included in the ferroelectric material layer. When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material layer may include 3 to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material layer may include 2 to 10 at % of silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 to 10 at % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1 to 7 at % of gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 to 80 at % of zirconium. The paraelectric material layer of the first gate insulating layer130may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the present disclosure is not limited thereto. The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer has ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer both include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer may differ from that of the hafnium oxide included in the paraelectric material layer. The ferroelectric material layer may have a thickness enough to have ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, in a range of 0.5 to 10 nm, but the present disclosure is not limited thereto. The thickness of the ferroelectric material layer may vary depending on the type of ferroelectric material because the critical thickness representing the ferroelectric properties may vary for each ferroelectric material. In an example, the first gate insulating layer130may include one ferroelectric material layer. In another example, the first gate insulating layer130may include a plurality of ferroelectric material layers spaced apart from each other. The first gate insulating layer130may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked. The first gate spacer140may be on a sidewall of the first gate electrode120. The first gate spacer140may be absent from between the first lower pattern BP1and the first sheet pattern NS1and from between the first sheet patterns NS1adjacent to each other in the third direction D3. The first gate spacer140may include an inner sidewall140_ISW2and a connection sidewall140_ISW1. The inner sidewall140_ISW2of the first gate spacer may face the sidewall of the first gate electrode120extending in the second direction D2. The inner sidewall140_ISW2of the first gate spacer may extend in the second direction D2. The inner sidewall140_ISW2of the first gate spacer may be a surface opposite to the outer sidewall facing the interlayer insulating layer190. The connection sidewall140_ISW1of the first gate spacer may be connected to the inner sidewall140_ISW2of the first gate spacer. The connection sidewall140_ISW1of the first gate spacer may extend in the first direction D1. The first gate spacer140may include a spacer hole140_H extending in the third direction D3. The spacer hole140_H may be defined by the first lower pattern BP1and the connection sidewall140_ISW1of the first gate spacer. It is illustrated in the drawing that a portion of the first sheet pattern NS1passes through the spacer hole140_H and is arranged inside the spacer hole140_H, but the present disclosure is not limited thereto. In some embodiments, unlike that illustrated in the drawings, the first sheet pattern NS1may not include a portion overlapping the first gate spacer140in the second direction D2. The first sheet pattern NS1may be connected to the first source/drain pattern150through the spacer hole140_H. The first gate insulating layer130may extend along the inner sidewall140_ISW2of the first gate spacer. The first gate insulating layer130may be in contact with the inner sidewall140_ISW2of the first gate spacer. The first gate spacer140may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbide (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. The first gate spacer140is illustrated as being a single layer, but this is only for convenience of description, and the present disclosure is not limited thereto. The first gate capping pattern145may be on the first gate electrode120and the first gate spacer140. An upper surface of the first gate capping pattern145may be coplanar with an upper surface of the interlayer insulating layer190. Unlike that illustrated in the drawings, the first gate capping pattern145may be between the first gate spacers140. The first gate capping pattern145may include, as non-limiting examples, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof. The first gate capping pattern145may include a material having an etch selectivity with respect to the interlayer insulating layer190. The first source/drain pattern150may be formed on the first active pattern AP1. The first source/drain pattern150may be on the first lower pattern BP1. The first source/drain pattern150may be connected to the first sheet patterns NS1. The first source/drain pattern150may be in contact with the first sheet patterns NS1. The first source/drain pattern150may be on a side surface of the first gate structure GS1. The first source/drain pattern150may be between the first gate structures GS1adjacent to each other in the first direction D1. For example, the first source/drain patterns150may be on both sides of the first gate structure GS1. In some embodiments, unlike that illustrated in the drawings, the first source/drain pattern150may be on one side of the first gate structure GS1and may be absent from the other side of the first gate structure GS1. The first source/drain pattern150may be included in a source/drain of the transistor using the first sheet pattern NS1as a channel region. The first source/drain pattern150may be in a first source/drain recess150R. The first source/drain recess150R may extend in the third direction D3. The first source/drain recess150R may be defined between the first gate structures GS1adjacent to each other in the first direction D1. A bottom surface of the first source/drain recess150R may be defined by the first lower pattern BP1. A sidewall of the first source/drain recess150R may be defined by the first sheet pattern NS1and the first gate structure GS1. In the first gate structure GS1, the first gate insulating layer130and the first gate spacer140may define a portion of the first source/drain recess150R. InFIGS.8to10, the first source/drain recess150R includes the connection sidewall140_ISW1of the first gate spacer. It is illustrated in the drawing that a width of an upper portion of the sidewall of the first source/drain recess150R in the first direction D1decreases as increases in distance from the first lower pattern BP1, but the present disclosure is not limited thereto. A portion of the first source/drain pattern150may pass through the spacer hole140_H. The first source/drain pattern150may fill at least a portion of the spacer hole140_H. The first source/drain pattern150may be in contact with the first sheet pattern NS1through the spacer hole140_H. A portion of the first source/drain pattern150may be in contact with the connection sidewall140_ISW1of the first gate spacer. The first gate spacer140may be absent from between the first source/drain pattern150and the first gate electrode120between the adjacent first sheet patterns NS1. The first gate insulating layer130may be in contact with the first source/drain pattern150. Between the first sheet pattern NS1at the lowermost portion and the first lower pattern BP1, a boundary between the first gate insulating layer130and the first lower pattern BP1may be the upper surface BP1_US of the first lower pattern. In other words, inFIG.2, the first gate structure GS1may include the first lower pattern BP1and a lowermost sub-gate structure between the first sheet patterns NS1arranged at the lowermost portion. The lowermost sub-gate structure may include a portion of the first gate electrode120and a portion of the first gate insulating layer130. The upper surface BP1_US of the first lower pattern may be a boundary between the lowermost sub-gate structure and the first lower pattern BP1. At this point, the bottom surface of the first source/drain recess150R may be lower in height than the upper surface BP1_US of the first lower pattern. The first source/drain pattern150may include a semiconductor liner layer151, at least one or more semiconductor insertion layers152and153, a semiconductor filling layer154, and a semiconductor capping layer155. The at least one or more semiconductor insertion layers152and153may be between the semiconductor liner layer151and the semiconductor filling layer154. In the semiconductor device according to some exemplary embodiments, the first source/drain pattern150may include a lower semiconductor insertion layer152and an upper semiconductor insertion layer153. The semiconductor liner layer151may extend along the first source/drain recess150R. The semiconductor liner layer151may be in contact with the first gate insulating layer130, the first sheet pattern NS1, and the first lower pattern BP1. InFIG.6, the semiconductor liner layer151may have a U-shape. In the cross-sectional view taken along the first direction D1, the semiconductor liner layer151may have a U-shape. The semiconductor liner layer151may include an outer sidewall151_OSW and an inner sidewall151_ISW. The outer sidewall151_OSW of the semiconductor liner layer is in contact with the first gate insulating layer130, the first sheet pattern NS1, and the first lower pattern BP1. The outer sidewall151_OSW of the semiconductor liner layer is directly connected to the first sidewall NS1_SW1of the first sheet pattern. The outer sidewall151_OSW of the semiconductor liner layer may represent a profile of the first source/drain recess150R. The inner sidewall151_ISW of the semiconductor liner layer may be a surface opposite to the outer sidewall151_OSW of the semiconductor liner layer. As the semiconductor liner layer151increases in distance from the outer sidewall151_OSW, a width of the inner sidewall151_ISW of the semiconductor liner layer in the second direction D2may be reduced. InFIGS.8to10, the inner sidewall151_ISW of the semiconductor liner layer may include a facet portion151_ISW1and a connection portion151_ISW2. The facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer may extend from the connection sidewall140_ISW1of the first gate spacer. The facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer may form an acute angle with the connection sidewall140_ISW1of the first gate spacer. The connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer may extend in the second direction D2. The connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer may include a curved portion. The semiconductor liner layer151may include, for example, silicon-germanium. The semiconductor liner layer151may include a silicon-germanium layer. The semiconductor liner layer151may include doped p-type impurities. For example, the p-type impurities may include boron (B), but the present disclosure is not limited thereto. The lower semiconductor insertion layer152and the upper semiconductor insertion layer153may each have a three-dimensional saddle structure. Each of the lower semiconductor insertion layer152and the upper semiconductor insertion layer153may include a saddle point SP, a first saddle region SR1, and a second saddle region SR2. The first saddle region SR1may be a region located in the second direction D2of the saddle point SP. The first saddle region SR1may extend in the third direction D3close to the first lower pattern BP1. The second saddle region SR2may be a region located in the first direction D1of the saddle point SP. The second saddle region SR2may extend in the third direction D3away from the first lower pattern BP1. In the cross-sectional view taken along the first direction D1, the lower semiconductor insertion layer152and the upper semiconductor insertion layer153may each have a U-shape. In the cross-sectional view taken along the second direction D2through the saddle point SP, the lower semiconductor insertion layer152and the upper semiconductor insertion layer153may each have an inverted U-shape. It is illustrated inFIG.7that the thickness is the same throughout the lower semiconductor insertion layer152and the upper semiconductor insertion layer153each having a saddle structure, but this is only for convenience of description, and the present disclosure is not limited thereto. The lower semiconductor insertion layer152may be arranged on the semiconductor liner layer151. The lower semiconductor insertion layer152may be arranged on the inner sidewall151_ISW of the semiconductor liner layer. For example, the lower semiconductor insertion layer152may be in contact with the semiconductor liner layer151. The lower semiconductor insertion layer152may cover at least a portion of the inner sidewall151_ISW of the semiconductor liner layer. The lower semiconductor insertion layer152may cover the facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer and the connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer. The lower semiconductor insertion layer152may include, for example, silicon-germanium. The lower semiconductor insertion layer152may include a silicon-germanium layer. The lower semiconductor insertion layer152may include doped p-type impurities. The upper semiconductor insertion layer153may be on the lower semiconductor insertion layer152. The upper semiconductor insertion layer153may be in contact with the lower semiconductor insertion layer152. InFIG.2, the upper semiconductor insertion layer153may include a sidewall portion153SP extending along the sidewall of the first source/drain recess150R and a bottom portion153BP extending along the bottom surface of the first source/drain recess150R. For example, a thickness t11of the bottom portion153BP of the upper semiconductor insertion layer may be equal to a thickness t12of the sidewall portion153SP of the upper semiconductor insertion layer. The upper semiconductor insertion layer153may extend along at least a portion of a profile of the lower semiconductor insertion layer152. In some embodiments, the upper semiconductor insertion layer153may include silicon-germanium. The upper semiconductor insertion layer153may include a silicon-germanium layer. In some embodiments, the upper semiconductor insertion layer153may include silicon. The upper semiconductor insertion layer153may include a silicon layer. The upper semiconductor insertion layer153may include doped p-type impurities. The semiconductor filling layer154is on the upper semiconductor insertion layer153. The semiconductor filling layer154may be in contact with the upper semiconductor insertion layer153. A bottom surface of the semiconductor filling layer154facing the upper semiconductor insertion layer153may have a saddle shape. The semiconductor filling layer154may include, for example, silicon-germanium. The semiconductor filling layer154may include a silicon-germanium layer. The semiconductor filling layer154may include doped p-type impurities. The semiconductor capping layer155is arranged on the semiconductor filling layer154. The semiconductor capping layer155may be in contact with the semiconductor filling layer154. In some embodiments, the semiconductor capping layer155may include silicon. The semiconductor capping layer155may include a silicon layer. In another example, the semiconductor capping layer155may include silicon-germanium. When the semiconductor capping layer155includes silicon-germanium, a germanium fraction of the semiconductor capping layer155may be less than a germanium fraction of the semiconductor liner layer151, but the present disclosure is not limited thereto. The semiconductor capping layer155may include doped p-type impurities, but the present disclosure is not limited thereto. In some embodiments, unlike that illustrated in the drawings, the first source/drain pattern150may not include the semiconductor capping layer155. InFIG.11, when the upper semiconductor insertion layer153includes silicon-germanium, a germanium fraction of the upper semiconductor insertion layer153may be less than a germanium fraction of the lower semiconductor insertion layer152and a germanium fraction of the semiconductor filling layer154. The germanium fraction of the upper semiconductor insertion layer153may be less than the germanium fraction of the semiconductor liner layer151. In some embodiments, unlike that illustrated in the drawings, the germanium fraction of the upper semiconductor insertion layer153may be equal to the germanium fraction of the semiconductor liner layer151. InFIG.12, the upper semiconductor insertion layer153may include a silicon layer. The germanium fraction of the upper semiconductor insertion layer153may be less than the germanium fraction of the semiconductor liner layer151, the germanium fraction of the lower semiconductor insertion layer152, and the germanium fraction of the semiconductor filling layer154. The germanium fraction of the lower semiconductor insertion layer152may be greater than the germanium fraction of the semiconductor liner layer151and may be less than the germanium fraction of the semiconductor filling layer154. For example, the germanium fraction of the upper semiconductor insertion layer153may be less than or equal to 5%. Since the germanium fraction of the upper semiconductor insertion layer153may be less than the germanium fraction of the lower semiconductor insertion layer152and the germanium fraction of the semiconductor filling layer154, a defect such as a stacking fault may occur in the semiconductor filling layer154when the thickness of the upper semiconductor insertion layer153increases. In order to prevent this, the upper semiconductor insertion layer153may have, for example, a thickness of 1 nm to 3 nm. The first source/drain pattern150may fill at least a portion of the spacer hole140_H. The semiconductor liner layer151, the lower semiconductor insertion layer152, and the upper semiconductor insertion layer153are illustrated as being arranged in the spacer hole140_H, but the present disclosure is not limited thereto. The layers included in the first source/drain pattern150shown in the spacer hole140_H may vary depending on the position at which the first gate spacer140is cut. Since each of the lower semiconductor insertion layer152and the upper semiconductor insertion layer153has a saddle structure, the shape of the first source/drain pattern150cut in the D1-D2plane may be changed depending on the cutting position. In other words, in a plan view, the shape of the first source/drain pattern150may vary depending on the cutting position. FIGS.10A and10Bare cross-sectional views taken along the vicinity of the saddle point SP of the upper semiconductor insertion layer153.FIGS.8and9are cross-sectional views taken along a portion above the saddle point SP of the upper semiconductor insertion layer153. The lower semiconductor insertion layer152and the upper semiconductor insertion layer153ofFIG.10may be the first saddle region SR1of the saddle structure. The lower semiconductor insertion layer152and the upper semiconductor insertion layer153ofFIGS.8and9may be the second saddle region SR2of the saddle structure. InFIGS.8to10B, the lower semiconductor insertion layer152may entirely cover the inner sidewall151_ISW of the semiconductor liner layer. The lower semiconductor insertion layer152may entirely cover the facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer and the connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer. InFIGS.8and9, the entire upper semiconductor insertion layer153may extend along the profile of the lower semiconductor insertion layer152. The upper semiconductor insertion layer153may entirely cover the lower semiconductor insertion layer152. The upper semiconductor insertion layer153may entirely cover the facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer and the connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer. The upper semiconductor insertion layer153may be in contact with the connection sidewall140_ISW1of the first gate spacer. The upper semiconductor insertion layer153may extend along a portion of the connection sidewall140_ISW1of the first gate spacer. The lower semiconductor insertion layer152, the upper semiconductor insertion layer153, and the semiconductor filling layer154may be sequentially stacked on the inner sidewall151_ISW of the semiconductor liner layer in the first direction D1. InFIGS.10A and10B, the lower semiconductor insertion layer152may extend in the first direction D1from the inner sidewall151_ISW of the semiconductor liner layer. In a plan view, the lower semiconductor insertion layer152may connect the inner sidewalls151_ISW of the semiconductor liner layers, which are adjacent to each other in the first direction D1. The lower semiconductor insertion layer152may separate the semiconductor filling layer154into two portions. The upper semiconductor insertion layer153may extend along at least a portion of a boundary between the lower semiconductor insertion layer152and the semiconductor filling layer154. The upper semiconductor insertion layer153may extend along at least a portion of the profile of the lower semiconductor insertion layer152. InFIG.10A, the upper semiconductor insertion layer153may be arranged entirely along the boundary between the lower semiconductor insertion layer152and the semiconductor filling layer154. InFIG.10B, the upper semiconductor insertion layer153may be arranged along a portion of the boundary between the lower semiconductor insertion layer152and the semiconductor filling layer154. In the cross-sectional view of the first source/drain pattern150, not only the shape of the first source/drain pattern150, but also the shape of the first source/drain pattern150below the cut surface may be shown on the cut surface. That is, the shape of the first source/drain pattern150cut in the D1-D2plane may be viewed as that in eitherFIG.10A or10B. Since the upper semiconductor insertion layer153entirely covers the facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer, the upper semiconductor insertion layer153may prevent the semiconductor filling layer154from being etched by an etchant that penetrates through the vicinity of the connection sidewall140_ISW1of the first gate spacer. In the following descriptions, the drawing taken along line F-F ofFIG.2will be described with reference toFIG.10A. The etch stop layer185may be on a sidewall of the first gate structure GS1, an upper surface of the first source/drain pattern150, and a sidewall of the first source/drain pattern150. Although not shown in the drawings, the etch stop layer185may be arranged on the upper surface of the field insulating layer105. The etch stop layer185may include a material having an etch selectivity with respect to the interlayer insulating layer190to be described below. The etch stop layer185may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and a combination thereof. The interlayer insulating layer190may be arranged on the etch stop layer185. The interlayer insulating layer190may be on the first source/drain pattern150. The interlayer insulating layer190may not cover the upper surface of the first gate capping pattern145. For example, the upper surface of the interlayer insulating layer190may be coplanar with the upper surface of the first gate capping pattern145. The interlayer insulating layer190may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant (low-k) material. For example, the low-k material may include fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethyleyclotetrasiloxane (OMCTS), hexamethyl disiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilil phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazene (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams (e.g., polypropylene oxide), carbon-doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination of any of the above materials, but the present disclosure is not limited thereto. FIGS.13and14are views for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. For reference,FIGS.13and14may be cross-sectional views taken along lines E-E and F-F ofFIG.2, respectively. Referring toFIGS.13and14, in the semiconductor device according to some exemplary embodiments, a lower semiconductor insertion layer152may cover a portion of an inner sidewall151_ISW of a semiconductor liner layer. In a plan view, the lower semiconductor insertion layer152may cover a portion of the inner sidewall151_ISW of the semiconductor liner layer. The lower semiconductor insertion layer152may extend along a portion of the inner sidewall151_ISW of the semiconductor liner layer. The lower semiconductor insertion layer152may entirely cover a connection portion151_ISW2of the inner sidewall151_ISW of the semiconductor liner layer. At least a portion of a facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer may be free from coverage by the lower semiconductor insertion layer152. In a plan view, an upper semiconductor insertion layer153may be in contact with the inner sidewall151_ISW of the semiconductor liner layer in the facet portion151_ISW1of the inner sidewall151_ISW of the semiconductor liner layer. FIG.15is a view for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. Referring toFIG.15, in the semiconductor device according to some exemplary embodiments, a thickness t11of a bottom portion153BP of an upper semiconductor insertion layer is different from a thickness t12of a sidewall portion153SP of the upper semiconductor insertion layer. As seen inFIG.15, which is taken along a first lower pattern BP1extending in the first direction D1, the thickness t11of the bottom portion153BP of the upper semiconductor insertion layer may be less than the thickness t12of the sidewall portion153SP of the upper semiconductor insertion layer. The thickness t12of the sidewall portion153SP of the upper semiconductor insertion layer may be a thickness in the vicinity of a center portion of the sidewall portion153SP of the upper semiconductor insertion layer extending in the third direction D3. For example, the thickness t12of the sidewall portion153SP of the upper semiconductor insertion layer may increase and then decrease as it moves away from the first lower pattern BP1. In the vicinity of an upper surface NS1_US of a first sheet pattern arranged at the uppermost portion, the thickness of the sidewall portion153SP of the upper semiconductor insertion layer may be less than the thickness t11of the bottom portion153BP of the upper semiconductor insertion layer. FIGS.16and17are views for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. For reference,FIG.16may be a cross-sectional view taken along line A-A ofFIG.1.FIG.17may be a cross-sectional view taken along line F-F ofFIG.16. Referring toFIGS.16and17, in the semiconductor device according to some exemplary embodiments, a semiconductor liner layer151may include a sidewall portion151SP extending along a sidewall of a first source/drain recess150R and a bottom portion151BP extending along the bottom surface of the first source/drain recess150R. The sidewall portion151SP of the semiconductor liner layer may include a pinning region151_PIN. In the pinning region151_PIN, a thickness of the sidewall portion151SP of the semiconductor liner layer may decrease suddenly. In the pinning region151_PIN, the thickness of the sidewall portion151SP of the semiconductor liner layer may decrease and then may increase as it increases in distance from the first lower pattern BP1. In a plan view, an inner sidewall151_ISW of the semiconductor liner layer in the pinning region151_PIN includes a portion recessed toward an outer sidewall151_OSW of the semiconductor liner layer. In a plan view, the inner sidewall151_ISW of the semiconductor liner layer in the pinning region151_PIN may be separated into two portions. For example, in the pinning region151_PIN, the inner sidewall151_ISW of the semiconductor liner layer may meet the outer sidewall151_OSW of the semiconductor liner layer. In some embodiments, unlike that illustrated in the drawings, in the pinning region151_PIN, the inner sidewall151_ISW of the semiconductor liner layer may be spaced apart from the outer sidewall151_OSW of the semiconductor liner layer in the first direction D1. On the basis of the upper surface BP1_US of the first lower pattern, the pinning region151_PIN is illustrated as being formed at a height similar to a height of a saddle point SP of an upper semiconductor insertion layer153, but the present disclosure is not limited thereto. The pinning region151_PIN is illustrated as being formed at a position overlapping a first gate electrode120, which is between first sheet patterns NS1in the first direction D1, but the present disclosure is not limited thereto. It is illustrated inFIGS.16and17that one semiconductor liner layer151includes one pinning region151_PIN, but the present disclosure is not limited thereto. Of course, one semiconductor liner layer151may include a plurality of pinning regions151_PIN. It is illustrated inFIGS.16and17that a portion of a first source/drain pattern150includes the pinning region151_PIN and the remaining portion of the first source/drain pattern150does not include the pinning region151_PIN, but the present disclosure is not limited thereto. FIG.18is a view for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. Referring toFIG.18, in the semiconductor device according to some exemplary embodiments, a sidewall of a first source/drain recess150R may have an uneven shape. A semiconductor liner layer151may include a sidewall portion151SP extending along the sidewall of the first source/drain recess150R and a bottom portion151BP extending along a bottom surface of the first source/drain recess150R. The sidewall portion151SP of the semiconductor liner layer may include a protruding region151_PR. The protruding region151_PR may be located in a region that overlaps a first gate electrode120in the first direction D1. The protruding region151_PR may protrude in the first direction D1toward the first gate electrode120. In other words, a portion of the semiconductor liner layer151may be recessed in the first direction D1between first sheet patterns NS1adjacent to each other in the third direction D3. FIG.19is a view for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. Referring toFIG.19, in the semiconductor device according to some exemplary embodiments, a first source/drain pattern150may not include an upper semiconductor insertion layer153between a lower semiconductor insertion layer152and a semiconductor filling layer154. The first source/drain pattern150includes a plurality of silicon-germanium layers on a first lower pattern BP1. As a distance from a first sheet pattern NS1increases, a germanium fraction of the silicon-germanium layer increases. For example, a germanium fraction of the lower semiconductor insertion layer152may be greater than a germanium fraction of a semiconductor liner layer151and may be less than a germanium fraction of the semiconductor filling layer154. The lower semiconductor insertion layer152has a three-dimensional saddle structure. FIGS.20and21are views for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. Referring toFIGS.20and21, the semiconductor device according to some exemplary embodiments may further include a source/drain contact180on a first source/drain pattern150. The source/drain contact180may be connected to the first source/drain pattern150. The source/drain contact180may be connected to the first source/drain pattern150through an interlayer insulating layer190and an etch stop layer185. A metal silicide layer175may be between the source/drain contact180and the first source/drain pattern150. InFIG.20, a bottom surface of the source/drain contact180may be higher than a lower surface NS1_BS of a first sheet pattern NS1at the uppermost portion of the first sheet pattern. InFIG.21, the bottom surface of the source/drain contact180may be located between the lower surface NS1_BS of the first sheet pattern at the lowermost portion of the first sheet pattern NS1and the lower surface NS1_BS of the first sheet pattern at the uppermost portion of the first sheet pattern NS1. The source/drain contact180is illustrated as being a single layer, but this is only for convenience of description, and the present disclosure is not limited thereto. The source/drain contact180may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material. The metal silicide layer175may include a metal silicide. FIGS.22to24are views for describing a semiconductor device according to some exemplary embodiments. For convenience of description, differences from those described with reference toFIGS.1to12will be mainly described. For reference,FIGS.23and24may be cross-sectional views taken along lines A-A and B-B ofFIG.22, respectively. Referring toFIGS.22to24, in the semiconductor device according to some exemplary embodiments, a first active pattern AP1may be a fin-type pattern elongated in the first direction D1. A portion of the first active pattern AP1protrudes further than an upper surface of a field insulating layer105in the third direction D3. A first gate insulating layer130may extend along a profile of the first active pattern AP1that protrudes further than the upper surface of the field insulating layer105. FIG.25is an exemplary plan view for describing a semiconductor device according to some exemplary embodiments.FIGS.26and27are cross-sectional views taken along line G-G ofFIG.25. For reference, a cross-sectional view taken along line A-A ofFIG.25may be the same as one ofFIGS.2,15,16,18, and19. In addition, a description of a first region I ofFIG.28may be substantially the same as that described with reference toFIGS.1to19. Thus, the following description will be made focusing on contents of a second region II ofFIG.25. Referring toFIGS.25to27, the semiconductor device according to some exemplary embodiments may include a first active pattern AP1, a plurality of first gate structures GS1, a first source/drain pattern150, a second active pattern AP2, a plurality of second gate structures GS2, and a second source/drain pattern250. A substrate100may include the first region I and the second region II. The first region I may be a region in which a PMOS is formed, and the second region II may be a region in which an NMOS is formed. The first active pattern AP1, the plurality of first gate structures GS1, and the first source/drain pattern150are arranged in the first region I of the substrate100. The second active pattern AP2, the plurality of second gate structures GS2, and the second source/drain pattern250are arranged in the second region II of the substrate100. The second active pattern AP2may include a second lower pattern BP2and a plurality of second sheet patterns NS2. The second lower pattern BP2may protrude from the substrate100. The second lower pattern BP2may be elongated in the first direction D1. The plurality of second sheet patterns NS2may be arranged on the second lower pattern BP2. The plurality of second sheet patterns NS2may be spaced apart from the second lower pattern BP2in the third direction D3. Each of the second lower patterns BP2and the second sheet patterns NS2may include one of silicon or germanium, which is an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. In the semiconductor device according to some exemplary embodiments, the second lower pattern BP2may be a silicon lower pattern including silicon, and the second sheet pattern NS2may be a silicon sheet pattern including silicon. When the first active pattern AP1and the second active pattern AP2are fin-type patterns, in an example, the first active pattern AP1and the second active pattern AP2may include the same semiconductor material. For example, the first active pattern AP1and the second active pattern AP2may each be a silicon fin-type pattern, but the present disclosure is not limited thereto. In some embodiments, the first active pattern AP1and the second active pattern AP2may include different semiconductor materials. For example, the first active pattern AP1may be a silicon-germanium fin-type pattern, and the second active pattern AP2may be a silicon fin-type pattern, but the present disclosure is not limited thereto. The plurality of second gate structures GS2may be arranged on the substrate100. Each of the second gate structures GS2may extend in the second direction D2. The adjacent second gate structures GS2may be spaced apart from each other in the first direction D1. The second gate structures GS2may be arranged on the second active pattern AP2. The second gate structures GS2may intersect the second active pattern AP2. The second gate structures GS2may intersect the second lower pattern BP2. The second gate structures GS2may surround the respective second sheet patterns NS2. Each of the second gate structures GS2may include, for example, a second gate electrode220, a second gate insulating layer230, a second gate spacer240, and a second gate capping pattern245. InFIG.26, the second gate spacer240may include an outer spacer241and an inner spacer242, unlike the first gate spacer140. The inner spacer242may be between the second sheet patterns NS2adjacent to each other in the third direction D3. The inner spacer242may be in contact with the second gate insulating layer230. The inner spacer242may define a portion of a second source/drain recess250R. InFIG.27, the second gate spacer240does not include an inner spacer like the first gate spacer140. That is, the second gate insulating layer230may be in contact with the second source/drain pattern250. Descriptions of the second gate electrode220, the second gate insulating layer230, the second gate spacer240, and the second gate capping pattern245are substantially the same as those of the first gate electrode120, the first gate insulating layer130, the first gate spacer140, and the first gate capping pattern145, and thus will be omitted in the following description. The second source/drain pattern250may be formed on the second active pattern AP2. The second source/drain pattern250may be formed on the second lower pattern BP2. The second source/drain pattern250may be connected to the second sheet pattern NS2. The second source/drain pattern250may be on a side surface of the second gate structure GS2. The second source/drain pattern250may be between the second gate structures GS2adjacent to each other in the first direction D1. For example, the second source/drain patterns250may be on both sides of the second gate structure GS2. In some embodiments, unlike that illustrated in the drawings, the second source/drain pattern250may be on one side of the second gate structure GS2and may not be on the other side of the second gate structure GS2. The second source/drain pattern250may be included in a source/drain of a transistor using the second sheet pattern NS2as a channel region. The second source/drain pattern250may be in the second source/drain recess250R. A bottom surface of the second source/drain recess250R may be defined by the second lower pattern BP2. A sidewall of the second source/drain recess250R may be defined by the second sheet pattern NS2and the second gate structure GS2. The second source/drain pattern250may include silicon doped with n-type impurities. The n-type impurities may include, for example, phosphorus (P) or arsenic (As), but the present disclosure is not limited thereto. When the second source/drain pattern250is in contact with the second gate insulating layer230as shown inFIG.27, unlike that described above, the second source/drain pattern250may include a silicon-germanium liner extending along a profile of the second source/drain recess250R. The second source/drain pattern250may include silicon doped with n-type impurities on the silicon-germanium liner. In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present inventive concepts. Therefore, the disclosed preferred embodiments of the inventive concepts are used in a generic and descriptive sense only and not for purposes of limitation. | 61,552 |
11942552 | DETAILED DESCRIPTION It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “being made of” may mean either “comprising” or “consisting of.” In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. One of the factors to determine device performance of a field effect transistor (FET), such as a fin FET (FinFET) and a gate-all-around (GAA) FET, is a shape of an epitaxial source/drain structure. In particular, when a source/drain region of a FinFET or a GAA FET is recessed and then an epitaxial source/drain layer is formed therein, the etching substantially defines the shape of the epitaxial source/drain structure. Further, when two adjacent fin structures are closer to each other, the epitaxial layers undesirably merge with each other. In the present disclosure, a wall fin structure (a dielectric dummy fin structure) is employed to physically and electrically separate adjacent source/drain epitaxial layers and to define the shape of the source/drain epitaxial layer. An optimal source/drain shape can improve a FinFET's and GAA FET's Ion/Ioff current ratio, and can improve device performance. In this disclosure, a source/drain refers to a source and/or a drain. It is noted that in the present disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same. FIG.1-21Cshow various stages of manufacturing a semiconductor GAA FET device according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1-21C, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. As shown inFIG.1, a first bottom semiconductor layer22is epitaxially formed on a semiconductor substrate10. In some embodiments, the semiconductor substrate10is a crystalline Si substrate. In other embodiments, the substrate10may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate10is a silicon layer of an SOI (silicon-on insulator) substrate. The first bottom semiconductor layer22is made of different material than the substrate10. When the substrate10is a Si substrate, the first bottom semiconductor layer22includes SiGe, where a Ge content is about 10 atomic % to about 60 atomic % (S0.9Ge0.1—S0.4Ge0.6) in some embodiments. The thickness of the first bottom semiconductor layer22is in a range from about 4 nm to about 30 nm in some embodiments, and is in a range from about 5 nm to about 25 nm in other embodiments. Further, a second bottom semiconductor layer23is epitaxially formed over the first bottom semiconductor layer22. The second bottom semiconductor layer23is made of different material than the first bottom semiconductor layer22. When the first bottom semiconductor layer22is made of SiGe, the second bottom semiconductor layer23includes Si or SiGe, where a Ge content is smaller than the first bottom semiconductor layer22and is more than 0 atomic % to about 10 atomic % in some embodiments. The thickness of the second bottom semiconductor layer23is in a range from about 40 nm to about 200 nm in some embodiments, and is in a range from about 50 nm to about 150 nm in other embodiments. Then, first semiconductor layers20and second semiconductor layers25are alternately formed over the second bottom semiconductor layer23. In some embodiments, the first and second bottom semiconductor layers are not formed, and the first semiconductor layers20and second semiconductor layers25are formed directly on the substrate10. The first semiconductor layers20and the second semiconductor layers25are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers20and the second semiconductor layers25are made of Si, a Si compound, SiGe, Ge or a Ge compound. In one embodiment, the first semiconductor layers20are Si1-xGex, where x is equal to or more than about 0.2 and equal to or less than about 0.6, and the second semiconductor layers25are Si or Si1-yGey, where y is smaller than x and equal to or less than about 0.1. In this disclosure, an “M” compound” or an “M based compound” means the majority of the compound is M. The thickness of the first semiconductor layers20may be equal to or smaller than that of the second semiconductor layers25, and is in a range from about 4 nm to about 30 nm in some embodiments, and is in a range from about 5 nm to about 20 nm in other embodiments. The thickness of the second semiconductor layers25is in a range from about 4 nm to about 30 nm in some embodiments, and is in a range from about 5 nm to about 20 nm in other embodiments. The thicknesses of the first semiconductor layers20may be the same as, or different from each other and the thicknesses of the second semiconductor layers25may be the same as, or different from each other. Although three first semiconductor layers20and three second semiconductor layers25are shown inFIG.1, the numbers are not limited to three, and can be 1, 2 or more than 3, and less than 10. Moreover, in some embodiments, a top semiconductor layer24is epitaxially formed over the stacked structure of the first semiconductor layers20and the second semiconductor layers25. In some embodiments, the top semiconductor layers24are Si1-zGez, where z is equal to or more than about 0.2 and equal to or less than about 0.7. In some embodiments, z=x. The thickness of the top semiconductor layer24is greater than that of each of the first semiconductor layers20and the second semiconductor layers25. In some embodiments, the thickness of the top semiconductor layer24is in a range from about 10 nm to about 100 nm, and is in a range from about 20 nm to about 50 nm in other embodiments. Further, in some embodiments, a cap semiconductor layer26made of a different material than the top semiconductor layer24is epitaxially formed on the top semiconductor layer24. In some embodiments, the cap semiconductor layer is made of Si and has a thickness in a range from about 0.5 nm to about 10 nm. The cap semiconductor layer26is used to control Ge out-diffusion from the top semiconductor layer24, and to maintain the quality of the surface of the top semiconductor layer24during a chemical mechanical polishing (CMP) process subsequently performed. Further, a hard mask layer15including one or more layers of an insulating material or an amorphous semiconductor material (e.g., a-Si) is formed over the cap semiconductor layer26. In some embodiments, the hard mask layer15includes a first hard mask layer15A and a second hard mask layer15B. In some embodiments, the first hard mask layer15A is silicon oxide having a thickness in a range from 1 nm to about 20 nm and the second hard mask layer15B is silicon nitride having a thickness in a range from about 10 nm to about 100 nm. After the stacked layers as shown inFIG.1are formed, fin structures are formed by using one or more lithography and etching operations, as shown inFIG.2. The fin structures may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the hard mask layer15. By using the patterned hard mask layer as an etching mask, the stacked semiconductor layers are patterned into fin structures29as shown inFIG.2. In some embodiments, the top semiconductor layer24and the cap semiconductor layer26are part of the hard mask layer and an etch stop layer for a CMP process subsequently performed. InFIG.2, the fin structures29extend in the Y direction and are arranged in the X direction. The number of the fin structures is not limited to two as shown inFIG.2, and may be as small as one and three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures29to improve pattern fidelity in the patterning operations. The width of the upper portion of the fin structure29along the Y direction is in a range from about 5 nm to about 40 nm in some embodiments, and is in a range from about 10 nm to about 30 nm in other embodiments. After the fin structures29are formed, one or more liner insulating layers18are formed over the fin structures29, and an insulating material layer30including one or more layers of insulating material is formed over the substrate so that the fin structures29with the liner layer18are fully embedded in the insulating layer30. The insulating material for the liner layer18and the insulating layer30are the same or different from each other, and include one or more of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiOC, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the liner layer18is made of silicon oxide or silicon nitride, and the insulating layer30is made of silicon oxide. The insulating material is formed by LPCVD (low pressure chemical vapor deposition), plasma-enhanced CVD (PECVD), flowable CVD and/or atomic layer deposition (ALD). An anneal operation may be performed after the formation of the insulating layer30. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the upper surface of the hard mask layer15(the second hard mask layer15B) is exposed from the insulating material layer30, as shown inFIG.3. Then, as shown inFIG.4, the insulating material layer is recessed to form an isolation insulating layer30so that the upper portions of the fin structures29are exposed. With this operation, the fin structures29are separated from each other by the isolation insulating layer30, which is also called a shallow trench isolation (STI). In some embodiments, the insulating material layer30is recessed until the upper portion of the second bottom semiconductor layer23is exposed. The first semiconductor layers20are sacrificial layers which are subsequently removed, and the second semiconductor layers25are subsequently formed into semiconductor wires or sheets as channel layers of a GAA FET. In some embodiments, during or after the recess etching of the insulating layer30, the liner layer18, the hard mask layer15and the cap semiconductor layer26are removed, thereby exposing the top semiconductor layer24, as shown inFIG.4. After the isolation insulating layer30is formed, a sacrificial cladding layer35is formed over the exposed portion of the fin structures29, as shown inFIG.5. The sacrificial cladding layer35includes one or more insulating materials or semiconductor materials. In some embodiments, the sacrificial cladding layer35includes amorphous or poly crystalline semiconductor material (e.g., Si, SiC, SiGe or Ge). In certain embodiments, the sacrificial cladding layer35is amorphous SiGe, having a Ge concentration in a range from about 20 atomic % to about 40 atomic %. In some embodiments, the Ge concentration of the sacrificial cladding layer35is the same as or similar to (difference within ±5%) the Ge concentration of the first semiconductor layer20. In some embodiments, the thickness of the sacrificial cladding layer35is in a range from about 5 nm to about 50 nm. If the thickness of the sacrificial cladding layer25is smaller than this range, a space for a metal gate formation is too small and some of the layers of the metal gate structure would not be properly formed. If the thickness of the sacrificial cladding layer25is larger than this range, electrical separation between adjacent fin structures would be insufficient. In some embodiments, before forming the sacrificial cladding layer35, a thin semiconductor layer is formed over the exposed portion of the fin structures29. In some embodiments, the thin semiconductor layer is non-doped Si. In some embodiments, the non-doped Si is crystalline Si. In some embodiments, the thickness of the thin semiconductor layer is in a range from about 2 nm to about 3 nm. The sacrificial cladding layer35is conformally formed by CVD or ALD in some embodiments. The deposition temperature of the sacrificial cladding layer35is less than or similar to the deposition temperature of the first semiconductor layers20, in some embodiments. In some embodiments, the deposition temperature of the sacrificial cladding layer35is in a range from about 500° C. to 650° C. The source gas includes a mixture of SiH4, GeH4, and HCl with H2or N2as a carrier gas. The sacrificial cladding layer35controls stress in the isolation area. Then, as shown inFIG.6, one or more etch-back operations are performed to remove horizontal portions of the sacrificial cladding layer35so as to expose the upper surface of the top semiconductor layer24and the upper surface of the isolation insulating layer30. In some embodiments, the etch-back operation includes a deposition-etching process. In some embodiments, the plasma generated from CH4is used for the deposition phase, and the plasma generated from HBr and He is used for the etching phase, which are repeated. In some embodiments, after the deposition-etching operation, a wet cleaning process to remove residuals is performed. Subsequently, a first dielectric layer40is formed over the fin structures, and a second dielectric layer45is formed over the first dielectric layer40such that the fin structures are fully embedded in the second dielectric layer45, as shown inFIG.7. The first dielectric layer40includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN or SiOCN, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or atomic layer deposition (ALD), or any other suitable film formation method. In certain embodiments, SiCN or SiOCN is used as the first dielectric layer40. In some embodiments, as shown inFIG.7, the first dielectric layer40is conformally formed over the fin structures such that a space is formed between adjacent fin structures. The thickness of the first dielectric layer40is in a range of about 2.5 nm to about 20 nm in some embodiments, and is in a range from about 5 nm to about 10 nm in other embodiments. The material of the second dielectric layer45is different from the material of the first dielectric layer40. In some embodiments, the second dielectric layer45includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, SiOC, SiCN or SiOCN formed by LPCVD, plasma-CVD or ALD, or any other suitable film formation method. In some embodiments, the second dielectric layer45is made of silicon nitride or silicon oxide. In some embodiments, the second dielectric layer45includes a first layer and a second layer. The first layer is silicon oxide formed by, for example, a flowable CVD process followed by a thermal annealing process at 400° C. to 800° C. in an inert gas ambient. The second layer is also silicon oxide formed by a plasma CVD process. The thickness of the second dielectric layer45is in a range of about 60 nm to about 500 nm in some embodiments. As shown inFIG.7, the second dielectric layer45fully fills the space between adjacent fin structures, in some embodiments. In other embodiments, a void is formed in the bottom part of the space. In some embodiments, one or more additional dielectric layers are formed between the first dielectric layer40and the second dielectric layer45. After the second dielectric layer45is formed, a planarization operation, such as an etch-back process or a chemical mechanical polishing (CMP) process, is performed to planarize the second dielectric layer45and to expose the upper surface of the top semiconductor layer24. In some embodiments, the top semiconductor layer24is slightly etched by about 5 nm to about 10 nm. Further, one or more additional etch-back operations are performed to recess the second dielectric layer45as shown inFIG.8. The second dielectric layer45is recessed to a level substantially equal (within ±5 nm) to the interface between the top semiconductor layer24and the uppermost one of the second semiconductor layers25. In some embodiments, subsequently, the first dielectric layer40is further trimmed (etched) to expose a part of the sacrificial cladding layer35. Next, as shown inFIGS.9A-9D, a third dielectric layer50is formed on the recessed second dielectric layer45.FIG.9Ais a cross sectional view along the X direction,FIG.9Bis a cross sectional view along the Y direction corresponding to line Y1-Y1ofFIG.9A,FIG.9Cis a cross sectional view along the Y direction corresponding to line Y2-Y2ofFIG.9A, andFIG.9Dis a isometric view. The material of the third dielectric layer50is different from the materials of the first dielectric layer40and the second dielectric layer45. In some embodiments, the third dielectric layer45includes a material having a lower etching rate than the second dielectric layer against a polysilicon or an amorphous SiGe etching. In some embodiments, the third dielectric layer50includes a high-k dielectric material. In some embodiments, the third dielectric layer50includes a dielectric material having a higher dielectric constant (k) than the second dielectric layer45and/or the first dielectric layer40. In some embodiments, the third dielectric layer50includes one or more of non-doped hafnium oxide (e.g., HfOx, 0<x≤2), hafnium oxide doped with one or more other elements (e.g., HfSiO, HfSiON, HfTaO, HfTiO or HfZrO), zirconium oxide, aluminum oxide, titanium oxide, and a hafnium dioxide-alumina (HfO2—Al2O3) alloy. In certain embodiments, hafnium oxide (HfOx) is used as the third dielectric layer50. The third dielectric layer50can be formed by LPCVD, plasma-CVD or ALD, or any other suitable film formation method. As shown inFIG.9A, the third dielectric layer50fully fills the space between adjacent fin structures. After the third dielectric layer50is formed to fully cover the fin structures, a planarization operation, such as an etch-back process or a CMP process, is performed to planarize the upper surface of the third dielectric layer50to expose the upper surface of the top semiconductor layer24, as shown inFIGS.9A-9D. In some embodiments, the thickness of the third dielectric layer50remaining on the top semiconductor layer24is in a range from about 5 nm to about 100 nm, the width of the third dielectric layer50at the top thereof is in a range from about 10 nm to about 80 nm, depending on device and/or process requirements. Accordingly, a wall fin structure is formed by layers40,45and50between adjacent fin structures. After the wall fin structure is formed, an annealing operation at a temperature of about 800° C. to about 1000° C. is performed for about 10 sec to about 60 sec, in some embodiments. Then, as shown inFIGS.10A-10C, the top semiconductor layer24is removed by one or more dry or wet etching operations. InFIGS.10A-10C to21A-21C, the “B” figures are cross sectional views along the Y direction corresponding to line Y1-Y1of the “A” figures, and the “C” figures are cross sectional view along the Y direction corresponding to line Y2-Y2of the “A” figures. As shown inFIG.10A, a groove having sidewalls formed by the cladding layers35is formed. After the top semiconductor layer24is removed, a sacrificial gate dielectric layer62is formed on the uppermost one of the second semiconductor layers25, the sidewalls of the first dielectric layer, and on the third dielectric layer50as shown inFIGS.10A-10C. The sacrificial gate dielectric layer62includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer62is in a range from about 1 nm to about 5 nm in some embodiments. Further, as shown inFIGS.11A-11C, a sacrificial (dummy) gate electrode layer64is formed, and a hard mask layer66is formed on the sacrificial gate electrode layer64. The sacrificial gate electrode layer64is blanket deposited on the sacrificial gate dielectric layer62and over the third dielectric layer50, such that the third dielectric layer50is fully embedded in the sacrificial gate electrode layer64. The sacrificial gate electrode layer64includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer64is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, the hard mask layer66is formed over the sacrificial gate electrode layer. The hard mask layer66includes one or more layers of silicon nitride or silicon oxide. Next, a patterning operation is performed on the hard mask layer66and the sacrificial gate electrode layer64is patterned into sacrificial gate electrodes, as shown inFIGS.12A-12C. In some embodiments, the width of the sacrificial gate electrode64is in a range from about 5 nm to about 30 nm and is in a range from about 10 nm to about 20 nm. Two or more sacrificial gate electrodes are arranged in the Y direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate electrodes are formed on both sides of the sacrificial gate electrodes to improve pattern fidelity. Further, sidewall spacers65are formed over the sacrificial gate electrodes64, as shown inFIGS.13A-13C. One or more insulating layers are deposited in a conformal manner to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate electrode and the sidewalls by the first dielectric layer40, respectively. Then, by using anisotropic etching, the sidewall spacers65are formed. In some embodiments, the sidewall spacer has a thickness in a range from about 3 nm to about 20 nm. The sidewall spacers65include one or more of silicon nitride, SiON, SiCN, SiCO, SiOCN or any other suitable dielectric material. In some embodiments, since the height of the third dielectric layer50is much smaller than the height of the sacrificial gate electrode layer64with the hard mask layer, the thickness of the sidewall spacers on sidewalls of the first dielectric layer which is on the third dielectric layer50is smaller than the thickness of the sidewall spacers on the sacrificial gate electrode64, or no sidewall spacer is formed on sidewalls of the first dielectric layer which is on the third dielectric layer50as shown inFIG.13D. Then, the stacked structure of the first semiconductor layers20and the second semiconductor layer25is etched down at the source/drain regions, by using one or more etching operations, thereby forming a source/drain space69, as shown inFIGS.14A-14B. In some embodiments, the second bottom semiconductor layer23is also partially etched. In some embodiments, during the etching, the sacrificial cladding layer35is partially or fully removed. In some embodiments, when no or thin sidewall spacer is formed on sidewalls of the first dielectric layer which is on the third dielectric layer50, the sacrificial cladding layer35is also removed during the etching to form the source/drain space69. Further, inner spacers are formed a shown inFIGS.15A-15C. The first semiconductor layers20are laterally etched in the Y direction within the source/drain space69, thereby forming cavities. The lateral amount of etching of the first semiconductor layer20is in a range from about 0.5 nm to about 10 nm in some embodiments, and is in a range from about 1 nm to about 5 nm in other embodiments. When the first semiconductor layers20are SiGe and the second semiconductor layers25are Si, the first semiconductor layers20can be selectively etched by isotropic etching, such as wet etching. A wet etchant includes a mixed solution of H2O2, CH3COOH and HF, followed by H2O cleaning in some embodiments. In some embodiments, the etching by the mixed solution and cleaning by water is repeated 10 to 20 times. The etching time using the mixed solution is in a range from about 1 min to about 2 min in some embodiments. The mixed solution is used at a temperature in a range from about 60° C. to about 90° C. in some embodiments. Then, a fourth dielectric layer is conformally formed on the etched lateral ends of the first semiconductor layers20and on end faces of the second semiconductor layers25in the source/drain space69. The fourth dielectric layer includes one of silicon nitride and silicon oxide, SiON, SiOC, SiCN and SiOCN, or any other suitable dielectric material. The fourth dielectric layer is made of a different material than the sidewall spacers65in some embodiments. The fourth dielectric layer can be formed by ALD or any other suitable methods. After the fourth dielectric layer is formed, an etching operation is performed to partially remove the fourth dielectric layer, thereby forming inner spacers70, as shown inFIG.15B. In some embodiments, the end face of the inner spacers70is recessed more than the end face of the second semiconductor layers25. The recessed amount is in a range from about 0.2 nm to about 3 nm and in in a range from about 0.5 nm to about 2 nm in other embodiments. In other embodiments, the recessed amount is less than 0.5 nm and may be equal to zero (the end face of the inner spacer70and the end face of the second semiconductor layers25are flush with each other). In some embodiments, before forming the fourth dielectric layer, an additional dielectric layer having a smaller thickness than the fourth dielectric layer is formed, and thus the inner spacers70have a two-layer structure. Subsequently, as shown inFIGS.16A-16C, a source/drain epitaxial layer is formed in the source/drain space69. The source/drain epitaxial layer includes one or more layers of SiP, SiAs, SiCP, SiPAs and/or SiC for an n-type FET, and SiGe, GeSn and/or SiGeSn for a p-type FET. For the p-type FET, the source/drain epitaxial layer is doped with B (boron) in some embodiments. In some embodiments, the source/drain epitaxial layer includes multiple layers. In some embodiments, the source/drain epitaxial layer of an n-type FET includes a first epitaxial layer82, a second epitaxial layer84and a third epitaxial layer86. In some embodiments, the first epitaxial layer82is made of SiP, SiAs or SiAs:P or combination thereof. In some embodiments, the P concentration of the first epitaxial layer82is in a range from about 0.5×1019atoms/cm3to about 5×1020atoms/cm3, and is in a range from about 0.8×1019atoms/cm3to about 2×1020atoms/cm3in other embodiments. In some embodiments, the second epitaxial layer84is made of SiP. In some embodiments, the P concentration of the second epitaxial layer84is higher than that of the first SiP epitaxial layer82, and is in a range from about 1×1021atoms/cm3to about 5×1021atoms/cm3, and is in a range from about 2×1021atoms/cm3to about 4×1021atoms/cm3in other embodiments. In some embodiments, the third epitaxial layer86is made of SiGeP. In some embodiments, the P concentration of the third epitaxial layer86is equal to or lower than that of the second SiP epitaxial layer84and higher than that of the first SiP epitaxial layer82, and is in a range from about 0.5×1021atoms/cm3to about 4×1021atoms/cm3, and is in a range from about 1×1021atoms/cm3to about 3×1021atoms/cm3in other embodiments. In some embodiments, the Ge concentration of the third epitaxial layer86is in a range from about 0.5 atomic % to 10 atomic %, and is in a range from about 1 atomic % to about 5 atomic % in other embodiments. In some embodiments, the source/drain epitaxial layer of a p-type FET includes a first epitaxial layer82, a second epitaxial layer84and a third epitaxial layer86. In some embodiments, the first epitaxial layer82is made of SiGe doped with B. In some embodiments, the Ge content is in a range from about 15 atomic % to about 30 atomic %. In some embodiments, the B concentration of the first epitaxial layer82is in a range from about 1×1019atoms/cm3to about 1×1021atoms/cm3, and is in a range from about 5×1019atoms/cm3to about 5×1020atoms/cm3in other embodiments. In some embodiments, the second epitaxial layer84is made of SiGe doped with B. In some embodiments, the Ge content of the second epitaxial layer84is in a range from about 20 atomic % to about 35 atomic % in some embodiments. In some embodiments, the B concentration of the second epitaxial layer84is equal to or higher than the largest B concentration of the first epitaxial layer82, and is in a range from about 0.5×1020atoms/cm3to about 1×1021atoms/cm3, and is in a range from about 1×1020atoms/cm3to about 5×1020atoms/cm3in other embodiments. In some embodiments, the third epitaxial layer86is made of SiGe doped with B. In some embodiments, the Ge content is in a range from 25 atomic % to about 60 atomic %. In some embodiments, the average Ge content of the third epitaxial layer is greater than the Ge content of the second epitaxial layer. In some embodiments, the B concentration of the third epitaxial layer86is in a range from about 5×1019atoms/cm3to about 5×1021atoms/cm3, and is in a range from about 1×1020atoms/cm3to about 3×1021atoms/cm3in other embodiments. The source/drain epitaxial layers are formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). After the source/drain epitaxial layers are formed, a fifth dielectric layer90is formed over the source/drain epitaxial layers, as shown inFIGS.17A-17C. The fifth dielectric layer90includes one of silicon nitride and silicon oxide, SiON, SiOC, SiCN and SiOCN, or any other suitable dielectric material. Then, one or more planarization operations, such as a CMP operation, are performed to expose the upper surface of the sacrificial gate electrode64as shown inFIGS.17B and17C. Then, the sacrificial gate electrode64and sacrificial gate dielectric layer62are removed as shown inFIGS.18A-18C. The fourth dielectric layer90protects the source/drain epitaxial layers during the removal of the sacrificial gate structures. The sacrificial gate structures can be removed using plasma dry etching and/or wet etching. When the sacrificial gate electrode64is polysilicon, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode64. The sacrificial gate dielectric layer62is thereafter removed using plasma dry etching and/or wet etching. After the sacrificial gate structures are removed, the sacrificial cladding layer35is removed by one or more dry and/or wet etching operations, as shown inFIGS.19A-19C. Then, the first semiconductor layers20are removed, thereby forming wires or sheets (channel regions) of the second semiconductor layers25, as shown inFIGS.20A-20C. The first semiconductor layers20can be removed or etched using an etchant that can selectively etch the first semiconductor layers20against the second semiconductor layers25. As shown inFIG.20B, since the inner spacers70are formed, the etching of the first semiconductor layers20stops at the inner spacers70. After the semiconductor wires or sheets (channel regions) of the second semiconductor layers25are released, a gate dielectric layer102is formed around each channel regions, and further, a gate electrode layer104is formed on the gate dielectric layer102, as shown inFIGS.21A-21C. In some embodiments, the structure and/or material of the gate electrode for the n-type GAA FET are different from the structure and/or material of the gate electrode for the p-type GAA FET.FIG.21Dshows the structure when no sidewall spacer is formed on sidewalls of the first dielectric layer which is on the third dielectric layer50. In certain embodiments, the gate dielectric layer102includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HffaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer102includes an interfacial layer (not shown) formed between the channel layers and the dielectric material. The gate dielectric layer102may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer102is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layers. The thickness of the gate dielectric layer102is in a range from about 1 nm to about 6 nm in one embodiment. The gate electrode layer104is formed on the gate dielectric layer102to surround each channel layer. The gate electrode104includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layer104may be formed by CVD, ALD, electro-plating, or other suitable method. The gate dielectric layer and the gate electrode layer are then planarized by using, for example, CMP, until the top surfaces of the fourth dielectric layer90and the third dielectric layer50are revealed. In some embodiments, after the planarization operation, the gate electrode layer104is recessed and a cap insulating layer (not shown) is formed over the recessed gate electrode104. The cap insulating layer includes one or more layers of a silicon nitride-based material, such as silicon nitride. The cap insulating layer can be formed by depositing an insulating material followed by a planarization operation. In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer102and the gate electrode104. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjustment layer may be formed separately for the n-channel FET and the p-channel FET which may use different metal layers. It is understood that the FET undergoes further CMOS processes to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc. According to the embodiments of the present disclosure, a wall fin structure is provided between two GAA FETs, which may be a p-type FET and an n-type FET, to more efficiently isolate one from the other. By employing a wall fin structure having at least two layers made of different material, it is easier to adjust the height of the wall fin structure. Further, by using a high-k dielectric material for the third dielectric layer, it is possible to protect the wall fin structure during the gate replacement operation and/or fin recess etching. FIGS.22A-22Cshow various views of a GAA FET according to an embodiment of the present disclosure. Materials, process, configurations and/or processes described with respect to the forgoing embodiments are employed in the following embodiments, and detailed description thereof may be omitted. In this embodiment, a buried power supply wiring110is formed under the wall fin structure. In some embodiments, the buried power supply wiring110is coupled to at least one of a source or a drain of the GAA FET to provide a potential, e.g., Vdd or Vss. FIGS.23A-25Bshow sequential manufacturing operations for fabricating a buried power supply wiring110according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.23A-25B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. InFIGS.23A-25B, the fin structures are illustrated as one layer for simplicity, but it should be understood that the fin structure may include multiple layers as shown inFIG.2. As shown inFIG.23A, one or more fin structures1020are formed over the semiconductor substrate1010. In some embodiments, the substrate1010is made of a suitable elemental semiconductor as explained above. Then, as shown inFIG.23B, an insulating layer for shallow trench isolation (STI) is formed to embed the fin structures1020therein. The insulating layer1030includes one or more layers of insulating materials, for example, silicon dioxide, silicon oxynitride and/or silicon nitride formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials instead of silicon oxide are deposited. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Usually, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation process. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal processes are conducted. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and/or phosphorous. The isolation insulating layer1030can be formed by one or more layers of SOG, SiO, SiON, SiOCN or fluorine-doped silicate glass (FSG) in some embodiments. Prior to forming the isolation insulating region1030, one or more liner layers (not shown) are formed over the substrate1010and sidewalls of the bottom part of the fin structures1020, in some embodiments. Next as shown inFIG.23C, trench openings1035are formed in the isolation insulating layer1030by using one or more lithography and etching operations. In some embodiments, after a liner insulating layer1040is formed in the trench opening, a conductive material1050is filled in the trench opening as shown inFIG.24A. The liner layer1040includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN or any other suitable material. The conductive material1050includes one or more conductive materials, such as doped poly silicon, W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Jr, Ru, Pt, and Zr, formed by ALD, PVD, CVD, plating or any other suitable methods. After the conductive material1050is formed a planarization operation, such as a chemical mechanical polishing (CMP) operation is performed. Subsequently, as shown inFIG.24B, the conductive material1050is recessed down to a given depth to form upper openings1045. The upper openings1045are filled with an insulating material1055as shown inFIG.24C. The insulating material1055includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN or any other suitable material. After the insulating material1055is formed, an etch back operation is performed to expose the upper portion of the fin structures1020. In some embodiments, the isolation insulating layer1030, the liner layer1040and the insulating material1055are recessed using a single etch process, or multiple etch processes, including a dry etch, a chemical etch, or a wet cleaning process. As shown inFIG.25A, part of the insulating material1055remains on the conductive material1050, which corresponds to a buried power supply wiring110. In some embodiments, insulating material layer1055does not remain on the buried power supply wiring1050.FIG.25Bshows a plan view after the buried power supply wirings1050(110) are formed. Subsequently, the operations explained with respect toFIGS.5-21Care performed. In some embodiments, the wall fin structure as set forth above is applicable to a FinFET as shown inFIGS.26A-26C. As shown inFIGS.26A-26C, a fin structure21made of, for example, Si, protrudes from the substrate10and an upper portion (channel region) protrudes from the isolation insulating layer30. A bottom portion of the fin structure21is embedded in the isolation insulating layer30and one or more fin liner layers18are formed on the bottom portion. The channel region is covered by a gate dielectric layer102and the gate dielectric layer102is covered by a gate electrode layer104. The source/drain epitaxial structure and a wall fin structure are the same as those in the above embodiments. It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages. In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure. In one or more of the foregoing or following embodiments, the first semiconductor layers are made of SiGe and the second semiconductor layers are made of Si. In one or more of the foregoing or following embodiments, the sacrificial cladding layer is made of SiGe. In one or more of the foregoing or following embodiments, the sacrificial cladding layer is amorphous or polycrystalline. In one or more of the foregoing or following embodiments, the hard mask layer includes a semiconductor layer and a dielectric layer. In one or more of the foregoing or following embodiments, the semiconductor layer of the hard mask layer is made of SiGe. In one or more of the foregoing or following embodiments, the first dielectric layer include at least one of SiOC, SiOCN or SiCN. In one or more of the foregoing or following embodiments, the second dielectric layer include at least one of silicon nitride, silicon oxide or SiON. In one or more of the foregoing or following embodiments, the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, fin structures are formed. Each of the fin structures includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed such that the first dielectric layer not fully filling a space between the fin structures. A second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer to fully fill the space between the fin structures. The second dielectric layer is recessed. A third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure. The hard mask layer is removed. A sacrificial gate structure is formed. Sidewall spacers are formed on sidewalls of the sacrificial gate structure and sidewalls of a part of the wall fin structure. A source/drain structure is formed. A fourth dielectric layer is formed. The sacrificial gate structure is removed. The sacrificial cladding layer is removed. The first semiconductor layers are removed. A metal gate structure is formed around the second semiconductor layers. In one or more of the foregoing or following embodiments, the sacrificial cladding layer is made of amorphous SiGe. In one or more of the foregoing or following embodiments, in the forming the sacrificial cladding layer, a layer for the sacrificial cladding layer is conformally formed over the exposed hard mask layer and stacked layer and on the isolation insulating layer, and a part of the layer on a top of the hard mask layer and on the isolation insulating layer are removed. In one or more of the foregoing or following embodiments, the hard mask layer includes a SiGe layer and a dielectric layer. In one or more of the foregoing or following embodiments, after the third dielectric layer is formed, an upper surface of the SiGe layer is exposed. In one or more of the foregoing or following embodiments, in the removing the hard mask layer, the SiGe layer is removed, thereby exposing a top of the sacrificial cladding layer and a top of an uppermost one of the second semiconductor layers. In one or more of the foregoing or following embodiments, in the forming the source/drain structure, source/drain regions of the fin structures are recessed, and one or more semiconductor epitaxial layers are formed. During the recessing, at least a part of the sacrificial cladding layer is removed. In one or more of the foregoing or following embodiments, in the forming the source/drain structure, after the recessing and before the forming one or more semiconductor epitaxial layers, ends of the first semiconductor layers are laterally recessed, and insulating inner spacers are formed on the recessed ends of the first semiconductor layers. In accordance with another aspect of the present disclosure, in a method of manufacturing a semiconductor device, fin structures are formed. Each of the fin structures has a semiconductor fin and a hard mask layer on the semiconductor fin, and an upper portion of each of the semiconductor fins protrudes from an isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the hard mask layer and the upper portion of each of the semiconductor fins. A first dielectric layer is formed to partially fill a space between the semiconductor fins. A second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer to fully fill the space. The second dielectric layer is recessed. A third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure between the fin structures. In one or more of the foregoing or following embodiments, the sacrificial cladding layer is made of amorphous or polycrystalline of SiGe. In one or more of the foregoing or following embodiments, the first dielectric layer include at least one of SiOC, SiOCN or SiCN, the second dielectric layer include at least one of silicon nitride, silicon oxide or SiON, and the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide. In accordance with another aspect of the present disclosure, a semiconductor device includes a first gate-all-around field effect transistor (GAA FET) and a second GAA FET, and a wall fin disposed between the first GAA FET and the second GAA FET and disposed on an isolation insulating layer. The wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer and a third dielectric layer, the first, second and third dielectric layers are made of different materials from each other, and the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers and the isolation insulating layer. In one or more of the foregoing or following embodiments, the first dielectric layer does not fully fill a space between the first GAA FET and the second GAA FET, and the second and third dielectric layers fully fill the space. In one or more of the foregoing or following embodiments, each of the first and second GAA FETs includes a source/drain epitaxial layer, and the first dielectric layer is disposed between the second dielectric layer and the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first dielectric layer includes at least one of SiOC, SiOCN or SiCN. In one or more of the foregoing or following embodiments, the second dielectric layer include at least one of silicon nitride, silicon oxide or SiON. In one or more of the foregoing or following embodiments, the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide. In one or more of the foregoing or following embodiments, a top of the wall fin is located above a top of the channel region of each of the first GAA FET and the second GAA FET. In one or more of the foregoing or following embodiments, a top of the wall fin is located above a top of the source/drain epitaxial layer of each of the first GAA FET and the second GAA FET. In one or more of the foregoing or following embodiments, the semiconductor device further includes a buried power supply wiring disposed below the wall fin. In accordance with another aspect of the present disclosure, a semiconductor device includes a first gate-all-around field effect transistor (GAA FET) and a second GAA FET, and a wall fin disposed between the first GAA FET and the second GAA FET and disposed on an isolation insulating layer. Each of the first GAA FET includes semiconductor wires or sheets, a gate dielectric layer wrapping around channel regions of the semiconductor wires or sheets, a gate electrode on the gate dielectric layer and a source/drain epitaxial layer, the wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer and a third dielectric layer, the first, second and third dielectric layers are made of different materials from each other, the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers and the isolation insulating layer, and a fourth dielectric layer different from the first, second and third dielectric layers is disposed on the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first dielectric layer does not fully fill a space between the first GAA FET and the second GAA FET, and the second and third dielectric layers fully fill the space. In one or more of the foregoing or following embodiments, the first dielectric layer is disposed between the second dielectric layer and the source/drain epitaxial layer. In one or more of the foregoing or following embodiments, the first dielectric layer include at least one of SiOC, SiOCN or SiCN. In one or more of the foregoing or following embodiments, the second dielectric layer include at least one of silicon nitride, silicon oxide or SiON. In one or more of the foregoing or following embodiments, the third dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide or titanium oxide. In one or more of the foregoing or following embodiments, the fourth dielectric layer include silicon oxide. In one or more of the foregoing or following embodiments, the semiconductor device further includes a buried power supply wiring disposed below the wall fin. In accordance with another aspect of the present disclosure, a semiconductor device includes a first semiconductor fin and a second semiconductor fin disposed over a semiconductor substrate, an isolation insulating layer disposed between the first semiconductor fin and the second semiconductor fin, a wall fin disposed on the isolation insulating layer, a gate structure disposed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin, a first source/drain epitaxial layer disposed over a source/drain region of the first semiconductor fin and a second source/drain epitaxial layer disposed over a source/drain region of the second semiconductor fin, and a first fin liner layer disposed on a bottom part of the first source/drain epitaxial layer, and a second fin liner layer disposed on a bottom part of the second source/drain epitaxial layer. The first source/drain epitaxial layer and the second source/drain epitaxial layer are separated by the wall fin, the wall fin includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer and a third dielectric layer, the first, second and third dielectric layers are made of different materials from each other, and the third dielectric layer includes a dielectric material having a dielectric constant higher than the first and second dielectric layers and the isolation insulating layer. In one or more of the foregoing or following embodiments, the third dielectric layer includes doped or non-doped hafnium oxide. In one or more of the foregoing or following embodiments, the first dielectric layer include SiOC, and the second dielectric layer include silicon oxide. The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 58,238 |
11942553 | DETAILED DESCRIPTION FIG.1Ais a layout view of a thin film transistor according to an example embodiment, andFIG.1Bis a cross sectional view cut in Line I-I′; Referring toFIGS.1A and1B, a substrate10may be provided. The substrate10may be a semiconductor, metal, glass, or polymer substrate. A gate electrode20may be formed to extend, e.g., in a first or y-direction, on the substrate10. The gate electrode20may be formed by using Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof. A gate insulating film30may be formed on the gate electrode20. The gate insulating film30may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or a combination film thereof. A metal oxide channel layer45(patterned so as to lie, e.g., in a second or x-direction, across an upper portion of the gate electrode20) may be formed on the gate insulating film30. The metal oxide channel layer45may be, e.g., an In—Ga oxide layer, an In—Zn oxide layer, or an In—Ga—Zn oxide layer, and may be in an amorphous state as deposited or patterned. The metal oxide channel layer45may be formed by using various suitable methods, and e.g., may be formed by using a physical deposition method such as sputtering, or a chemical deposition method such as chemical vapor deposition and atomic layer deposition or the like, and further, may be patterned by using various suitable methods. The metal oxide channel layer45may be formed to a thickness, e.g., in a third or z-direction, of ones to dozens of nm, e.g., 10 to 50 nm, for example 10 to 30 nm. Formation of the metal oxide channel layer45by using the atomic layer deposition may be performed by using an In source, an oxidant, and a Ga source and/or a Zn source, for example. For example, Trimethyl Indium (In(CH3)3; TMIn) or the like may be used as an In source, Trimethyl Gallium (Ga(CH3)3; TMGa) or the like may be used as a Ga source, and Diethyl Zinc (Zn(C2H5)2; DEZ), Dimethyl Zinc (Zn(CH3)2; DMZ) or the like may be used as a Zn source. Further, at least one of oxygen (O2), ozone (O3), vapor (H2O), N2O, CO2or the like may be used as oxidant, for example. When the metal oxide channel layer45is In—Ga—Zn oxide (IGZO), a number of atoms of In may be about 20 to 80 at %, e.g., about 30 to 70 at %, compared to a number of atoms in a total of In, Ga and Zn. Within this range, In—Ga—Zn oxide (IGZO) may represent semiconductivity during an annealing process after being deposited to be described below. For example, an atomic ratio of In:Ga:Zn may be 1:1:1 or 2:2:1. A portion of a surface of the metal oxide channel layer45between the source electrode50S and the drain electrode50D, more specifically, an overlapping region with the metal oxide channel layer45and the gate electrode20, may be exposed by forming a source electrode50S and a drain electrode50D on end portions of both sides of the metal oxide channel layer45. The source electrode50S and the drain electrode50D may be formed by using at least one metal such as aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), or molybdenum (Mo), or an alloy including the same, or a metal oxide conductive film such as indium tin oxide (ITO). The substrate formed with the source/drain electrodes50S,50D may be post-deposition annealed. For example, after the deposition described above, annealing may be performed in an air atmosphere and at a temperature of about 300 to 500° C., e.g., about 350 to 450° C. In this case, the conductivity of the metal oxide channel layer45may be enhanced from a state near to insulative to semiconductive, and simultaneously, ohmic contact may be formed between the source/drain electrodes50S,50D and the metal oxide channel layer45. The patterned transition metal layer60may be formed, e.g., directly on the metal oxide channel layer45exposed between the source electrode50S and the drain electrode50D. The transition metal layer60may include a transition metal having a greater oxidation tendency compared to metals contained within the metal oxide channel layer45. For example, the transition metal layer60may be Ta layer, Ti layer, or Mo layer. As another example, the transition metal layer60may be a transition metal nitride film including a small amount of nitrogen (e.g., a contained amount of nitrogen may be 5 to 35 at %) that is enriched with transition metal. For example, it may be TiN layer enriched with Ti, TaN layer enriched with Ta, or MoN layer enriched with Mo. For example, when the metal oxide channel layer45is In—Ga—Zn oxide (IGZO), and the transition metal contained in the transition metal layer60is Ta, a Gibbs free energy (ΔGf) for formation of Ta2O5, which is an example of Ta oxide, may be lower than every Gibbs free energy for formation of In2O3, which is an example of In oxide, Ga2O3, which is an example of Ga oxide, and ZnO, which is an example of Zn oxide. Thus, the oxidation tendency of Ta is more than those of In, Ga, and Zn. Herein, the Gibbs free energy for formation of In2O3, Ga2O3, ZnO, and Ta2O5are respectively −830.7, −998.3, −348.1, and −1911.2 kJ/mol. The transition metal layer60may be formed to a thickness, e.g., in a the third or z-direction normal to an upper surface of the substrate10, of, e.g., 5 to 50 nm, e.g., 20 to 30 nm. A ratio of a thickness of the metal oxide channel layer45, e.g., in the third or z-direction, to a thickness of the transition metal layer60, e.g., in the third or z-direction, may be 2:1 to 1:2, e.g., 1:1 to 1:1.5, for uniform crystallization of the metal oxide channel layer45performed thereafter. Further, the transition metal layer60may be formed so as to overlap, e.g., in plan view, the gate electrode20formed below the metal oxide channel layer45. For example, the transition metal layer60may be formed to overlap a center of the gate electrode20or a center of a channel region of TFT. In an implementation, the transition metal layer60may be formed so as not to be in contact with the source/drain electrodes50S,50D. For example, as shown inFIG.1A, the transition metal layer60may have a length L60, e.g., in the first or x-direction, that is shorter than a channel length L45of TFT, i.e., the interval between the source/drain electrodes50S,50D, and may substantially centered relative thereto. Crystallization (described below) may be performed in an entire width, e.g., in the second or y-direction, of the transition metal layer60having a width Who, which may be as wide as or wider in the second or y-direction than a channel width of the TFT, i.e., a width W45of the metal oxide channel layer45. The resulting material may be crystallization-annealed after the transition metal layer60is formed. The crystallization-annealing may be performed in an oxygen or nitrogen atmosphere, and crystallization-annealing may be performed at about 150° C. to 500° C., e.g., about 200° C. to 400° C., and, e.g., about 250° C. to 400° C. or about 250° C. to 350° C. Without being bound by theory, it is believed that, during the crystallization-annealing process, oxygen species loosely bonded with metal atoms within the metal oxide channel layer45near to an interface between the transition metal layer60and the metal oxide channel layer45(e.g., interstitial oxygen, hydroxyl groups, or the like) may be removed or consumed by reacting with the metal of the transition metal layer60to form a transition metal oxide (MaOx, where Mais metal within the transition metal layer60). Simultaneously, electrons may be emitted into the metal oxide channel layer45as the transition metal oxide is formed within the transition metal layer60. The electrons supplied to the metal oxide channel layer45of an interface in contact with the transition metal layer60may be delivered to an antibonding orbital of a metal-oxygen bond in the metal oxide channel layer45such that the metal-oxygen bond of the interface may be weakened. Thus, the metal-oxygen bond may be broken and then rearranged from the interface. Such rearrangement may be transferred in an internal portion of the metal oxide channel layer45. Thus, the entire metal oxide channel layer45may be converted to be crystalline at a relatively lower temperature, e.g., polycrystalline. As a result, lattice fraction of metal-oxygen within the metal oxide channel layer45may be increased and crystallinity may be increased. Meanwhile, the crystallinity within the metal oxide channel layer45may become lower in a direction of an opposite surface to a surface in contact with the transition metal layer60, i.e., in a direction of the gate insulating film30. The crystallized metal oxide channel layer45may be converted into polycrystallized metal oxide channel layer45including crystallized grains of a C-axis. For example, the polycrystallized metal oxide channel layer45may be observed at a proximity to about 33° (2θ) in an XRD spectrum, and may present a recognizable diffraction peak (009) that indicates a crystal plane oriented in C-axis. The crystallized metal oxide channel layer45may be formed at least within at least a portion of an interface in contact with the gate insulating film30so that the crystallized grains in C-axis within the amorphous matrix may be partially formed to be isolated from each other. Accordingly, charge migration may be less interrupted as grain boundaries between the crystallized grains are limited or the grain boundaries are less clear. As a result, electrical characteristics of a device including the metal oxide channel layer45crystallized in C-axis may be enhanced. Further, the crystallized metal oxide channel layer45may not show peaks indicating the (014) plane and the (015) plane, which are diffraction peaks formed in the XRD spectrum that may appear simultaneously when grain boundaries are extensive. Further, the crystallized metal oxide channel layer45may not show peaks that may correspond to (002) plane of ZnO or (400) phase of bixbyite In2O3. When the crystallization-annealing is performed in an oxygen atmosphere, the transition metal layer60may be modified to a transition metal oxide layer (e.g., Ta oxide film, Ti oxide film, or Mo oxide film). The transition metal oxide layer is an insulating material as both a surface exposed to the oxygen atmosphere and an interface in contact with the metal oxide channel layer45are all oxidized. When the crystallization-annealing is performed in a nitrogen atmosphere, the transition metal layer60may be modified to a transition metal oxynitride layer (e.g., Ta oxynitride film, Ti oxynitride film, or Mo oxynitride film). The transition metal oxynitride layer is insulating material, as the transition metal layer60is oxidized near to an interface in contact with the metal oxide channel layer45and nitrified near to a surface exposed to the nitrogen atmosphere. FIG.2is a cross sectional view of a stage in a method of fabricating a thin film transistor according to an example embodiment. The fabricating method of the thin film transistor according to an example embodiment may be similar to the fabricating method of the thin film transistor described with reference toFIGS.1A and1Bexcept for as described below. Referring toFIG.2, the gate electrode20extending in a first direction on the substrate10may be formed and the gate insulating film30may be formed on the gate electrode20. The source electrode50S and the drain electrode50D may be formed on the gate insulating film30. At least a portion of the gate insulating film30that overlaps the gate electrode20, between the source electrode50S and the drain electrode50D, may be exposed such that the exposed gate insulating film30and the metal oxide channel layer45covering the source electrode50S and the drain electrode50D may be formed. The substrate10formed with the metal oxide channel layer45may be post-deposition annealed. The post-deposition annealing may be performed in the air atmosphere and at a temperature of about 300 to 500° C., e.g., about 350 to 450° C. In this case, the conductivity of the metal oxide channel layer45may be enhanced from a state near to insulative to semiconductive, and simultaneously, ohmic contact may be formed between the source/drain electrodes50S,50D and the metal oxide channel layer45. Then, the transition metal layer60may be formed on the metal oxide channel layer45. Then, the metal oxide channel layer45and the transition metal layer60, which are stacked and patterned in order on the gate insulating film30, may be formed by patterning the transition metal layer and the metal oxide channel layer in order. As a result, the patterned metal oxide channel layer45and the transition metal layer60may have substantially the same width and length. The metal oxide channel layer45may lie across on an upper portion of the gate electrode20, and further, may respectively connect to the source electrode50S and the drain electrode50D at both side end portions. Thus, the source electrode50S and the drain electrode50D may connect to the patterned metal oxide channel layer45on a lower portion of both side end portions of the metal oxide channel layer45. The resulting material may be crystallization-annealed in a state in which the transition metal layer60is deposited (patterned or not patterned). During the crystallization-annealing process, the metal oxide channel layer45may be crystallized as described above with reference toFIGS.1A and1B. FIGS.3A and3Bare cross sectional views of stages in a method of fabricating a thin film transistor according to an example embodiment. The fabricating method of the thin film transistor according to the present example embodiment may be performed in a similar manner to the fabricating method of the thin film transistor described with reference toFIGS.1A and1Bexcept for as described below. Referring toFIG.3A, a buffer layer15may be formed on the substrate10. The buffer layer15may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a composite film thereof. The transition metal layer60and the metal oxide channel layer45, which are stacked and patterned in order on the buffer layer15, may be formed as the transition metal layer and the metal oxide channel layer are formed in order on the buffer layer15and the metal oxide channel layer and the transition metal layer are patterned in order. As a result, the patterned metal oxide channel layer45and the transition metal layer60may have substantially the same width and length as each other. The resulting material may be crystallization-annealed in a state in which the metal oxide channel layer is deposited (patterned or not patterned). During the crystallization-annealing process, the metal oxide channel layer45may be crystallized as described above with reference toFIGS.1A and1B. However, while the crystallization-annealing process described above with reference toFIGS.1A and1Bmay be performed in oxygen or nitrogen atmosphere, the crystallization-annealing process according to an example embodiment may be performed in oxygen atmosphere, not in nitrogen atmosphere. Further, during the crystallization-annealing process, the conductivity of the metal oxide channel layer45may be enhanced from a state near to insulative to semiconductive, and simultaneously, may be crystallized by including crystallized grains in a C-axis. The above explanation with reference toFIGS.1A and1Bprovides explanation with respect to the crystallization-annealing. Referring toFIG.3B, the gate insulating film30may be formed on the metal oxide channel layer45. The gate electrode20across an upper portion of the metal oxide channel layer45may be formed on the gate insulating film30. An interlayer insulating film35covering the gate electrode20may be formed on the gate electrode20. The interlayer insulating film35may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a composite film thereof. Contact holes respectively exposing both side end portions of the metal oxide channel layer45may be formed within the interlayer insulating film35and the gate insulating film30thereunder, and the source electrode505and the drain electrode50D respectively connecting to both side end portions of the metal oxide channel layer45may be formed within the contact holes. Then, annealing to enhance ohmic contact between the metal oxide channel layer45and the source/drain electrodes50S,50D may be performed. FIGS.4A to4Fare cross sectional views of stages in a method of fabricating a vertical NAND flash memory device according to an example embodiment; Referring toFIG.4A, a lower insulating film113may be formed on the substrate100. A stack S, in which a plurality of control gate films115and a plurality of interlayer insulating films117are alternately stacked on the lower insulating film113, may be formed. For example, n pairs of the control gate film115and the interlayer insulating film117may be stacked to form a stack including L1, L2, . . . , Ln of unit layers. The substrate100may include an impurity region105enhanced in conductivity by being doped with impurities compared to a bulk substrate. In some example embodiments, the impurity region105may be referred to as a common source line105. The substrate100may be a semiconductor substrate, e.g., monocrystalline silicon, an IV-IV compound such as silicon-germanium, or silicon carbide, III-V compound, or II-VI compound substrate, or a semiconductor layer formed on any of these substrates. The control gate film115may include a semiconductor material, e.g., doped polysilicon, or a metal, e.g., tungsten, copper, aluminum, tantalum, titanium, cobalt, nitride titanium, or an alloy thereof. The lower insulating film113and the interlayer insulating film117may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a combination film thereof. Referring toFIG.4B, an opening portion H may be formed to penetrate through the stack (i.e., through a plurality of the control gate films115and a plurality of interlayer insulating films117which are alternately stacked) and the lower insulating film113, and may expose the substrate100, e.g., the impurity region105. Thereafter, grooves Ha may be formed (exposing control gate patterns115aon a side portion and the insulating films117,113on upper and lower portions) as the control gate films115exposed in a sidewall of the opening portion H are selectively recessed, thus forming the control gate patterns115adisposed between the interlayer insulating films117. Referring toFIG.4C, a blocking insulating film122may be conformally formed on an inner surface of the grooves Ha and a sidewall of the opening portion H. Then, a charge storage film125may be conformally formed on the blocking insulating film122, and then the charge storage film125and the blocking insulating film122may be anisotropic-etched in order. As a result, the blocking insulating film122conformally coating an inner surface of the grooves Ha and the charge storage film125filling the grooves Ha surface-coated with the blocking insulating film122may be formed. The blocking insulating film122, the charge storage film125, and the insulating film117,113may be exposed within a sidewall of the opening portion H. According to an example embodiment, the blocking insulating film122may be an Inter Gate Dielectric (IGD), and e.g., it may be a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film having a high-k dielectric constant. According to an example, embodiment, the charge storage film125may be a floating gate formed of, e.g., polysilicon. Referring toFIG.4D, a tunnel insulating film133may be formed to cover the charge storage film125on a sidewall of the opening portion H by, e.g., anisotropic etching after a tunnel insulating film material is conformally formed on a surface including a sidewall of the opening portion H. In another implementation, the tunnel insulating film133may be formed by oxidizing the charge storage film125exposed on a sidewall of the opening portion H. The tunnel insulating film133may be a silicon oxide film. The metal oxide channel layer135may conformally formed on a sidewall of the opening portion H formed with the tunnel insulating film133and the common source line105. The metal oxide channel layer135may be, e.g., an In—Ga oxide layer, an In—Zn oxide layer, or an In—Ga—Zn oxide layer in an amorphous state as deposited. The metal oxide channel layer135may be formed by using an atomic layer deposition. The metal oxide channel layer135may be formed by using an atomic layer deposition, e.g., by using In source, oxidant, and Ga source and/or Zn source. For example, Trimethyl indium (In(CH3)3; TMIn) or the like may be used as an In source, Trimethyl gallium (Ga(CH3)3; TMGa) or the like may be used as a Ga source, Diethyl Zinc (Zn(C2H5)2; DEZ), Dimethyl Zinc (Zn(CH3)2; DMZ) or the like may be used as a Zn source. Further, at least one of oxygen (O2), ozone (O3), vapor (H2O), N2O, CO2or the like may be used as oxidant, for example. When the metal oxide channel layer135is In—Ga—Zn oxide (IGZO), a number of atoms of In may be about 20 to 80 at %, e.g., about 30 to 70 at %, compared to a number of atoms in a total of In, Ga and Zn. Within this range, In—Ga—Zn oxide (IGZO) may provide semiconductivity during an annealing process after being deposited (described below). For example, atomic ratio of In:Ga:Zn may be 1:1:1 or 2:2:1. The substrate100formed with the metal oxide channel layer135may be post-deposition annealed. The above-described post-deposition annealing may be performed in the air atmosphere and at a temperature of about 300 to 500° C., e.g., about 350 to 450° C. In this case, the conductivity of the metal oxide channel layer135may be enhanced from a state near to insulative to semiconductive, and simultaneously, ohmic contact may be formed between the common source line105and the metal oxide channel layer135. The transition metal layer137may be conformally formed on the metal oxide channel layer135. The transition metal layer137may be formed by using an atomic layer deposition. The transition metal layer137is a layer containing transition metal, and the contained transition metal may be transition metal having a greater oxidation tendency compared to metal(s) contained within the metal oxide channel layer135. For example, the transition metal layer137may be a Ta layer, Ti layer, or Mo layer. As another example, the transition metal layer137may be a transition metal nitride film including a small amount of nitrogen (e.g., contained amount of nitrogen is 5 to 35 at %) enriched with transition metal. For example, it may be Ti enriched with a TiN layer, Ta enriched with TaN layer, or Mo enriched with MoN layer. For example, when the metal oxide channel layer135is In—Ga—Zn oxide (IGZO) and the transition metal contained in the transition metal layer137is Ta, a Gibbs free energy (ΔGf) for formation of Ta oxide, e.g., Ta2O5, may be lower than every Gibbs free energy for formation of In oxide, e.g., In2O3, Ga oxide, e.g., Ga2O3, and Zn oxide, e.g., ZnO, and this may indicate that Ta has greater oxidation tendency compared to In, Ga, and Zn. Herein, the Gibbs free energy for formation of In2O3, Ga2O3, ZnO, and Ta2O5are respectively −830.7, −998.3, −348.1, and −1911.2 kJ/mol. The transition metal layer137may be formed to a thickness of 5 to 50 nm and may be formed by an atomic layer deposition. The transition metal layer137may be formed to a thickness of 20 to 30 nm, for example. A ratio of a thickness of the metal oxide channel layer135to a thickness of the transition metal layer137may be 2:1 to 1:2, e.g., 1:1 to 1:1.5, for uniform crystallization of the metal oxide channel layer performed thereafter. The resulting material may be crystallization-annealed after the transition metal layer137is formed. The crystallization-annealing may be performed in an oxygen or nitrogen atmosphere and at about 150° C. to 500° C., e.g., about 200° C. to 400° C., more specifically, about 250° C. to 350° C. During the crystallization-annealing process, oxygen species loosely bonded with metal atoms within the metal oxide channel layer135near to an interface between the transition metal layer137and the metal oxide channel layer135(e.g., interstitial oxygen, hydroxyl group, or the like) may be removed or consumed by reacting with metal within the transition metal layer137and forming the transition metal oxide (MaOx, where Mais metal within the transition metal layer137), and electrons may be emitted into the metal oxide channel layer135as the transition metal oxide is formed within the transition metal layer137. The electrons supplied to the metal oxide channel layer135of an interface in contact with the transition metal layer137may be delivered to an antibonding orbital of a metal-oxygen bond in the metal oxide channel layer135such that the metal-oxygen bond of the interface is weakened. Thus, the metal-oxygen bond of the interface may be broken and then rearranged from the interface. Such rearrangement may be transferred in an internal portion of the metal oxide channel layer135, and the entire metal oxide channel layer135may be converted to be crystalline at a relatively lower temperature, e.g., polycrystalline. As a result, a lattice fraction of metal-oxygen within the metal oxide channel layer135may be increased and crystallinity may be increased. Crystallinity of the metal oxide channel layer135may be lower in a direction of an opposite surface to a surface in contact with the transition metal layer137, i.e., in a direction of the tunnel insulating film133. The crystallized metal oxide channel layer135may be converted into a polycrystallized metal oxide channel layer135including crystallized grains of a C-axis. For example, the polycrystallized metal oxide channel layer135may be observed at a proximity to about 33° (2θ) in an XRD spectrum, and may present a recognizable diffraction peak (009) that indicates a crystal plane oriented in a C-axis. The crystallized metal oxide channel layer135may be formed at least within at least a portion of an interface in contact with the tunnel insulating film133so that C-axis-crystallized grains within amorphous matrix may be partially formed to be isolated from each other. Accordingly, charge migration may be less interrupted as grain boundaries are limited between the crystallized grains or grain boundaries are less clear. As a result, electrical characteristics of a device including the metal oxide channel layer135crystallized in a C-axis may be enhanced. Further, the crystallized metal oxide channel layer135may not show peaks of the (014) plane and the (015) plane (which are diffraction peaks that may appear as grain boundaries become extensive) in the XRD spectrum. Further, the crystallized metal oxide channel layer135may not show peaks that may correspond to (002) plane of ZnO or (400) phase of bixbyite In2O3. When the crystallization-annealing is performed in an oxygen atmosphere, the transition metal layer137may be modified to a transition metal oxide layer (e.g., Ta oxide film, Ti oxide film, or Mo oxide film), which is an insulating material, as both a surface exposed to the oxygen atmosphere and an interface in contact with the metal oxide channel layer135are all oxidized. When the crystallization-annealing is performed in a nitrogen atmosphere, the transition metal layer137may be modified to a transition metal oxynitride layer (e.g., Ta oxynitride film, Ti oxynitride film, or Mo oxynitride film), which is insulating material, as the transition metal layer137is oxidized near to an interface in contact with the metal oxide channel layer135and nitrified near to a surface exposed to the nitrogen atmosphere. Referring toFIG.4E, the oxidized or oxynitrified transition metal layer137and the metal oxide channel layer135may be anisotropic-etched in to form the patterned metal oxide channel layer135′ and the oxidized or oxynitrified transition metal layer137′ (which are stacked in order on the tunnel insulating film133formed on a sidewall of the opening portion H) and simultaneously expose the common source line105within the opening portion H. After the patterned metal oxide channel layer135′ is formed, the oxidized or oxynitrified transition metal layer137′ may be additionally anisotropic-etched. As a result, a region where the metal oxide channel layer135′ is exposed may be produced without being covered with the transition metal layer137′ at a gate of the opening portion H. The crystallization-annealing described with reference toFIG.4Dmay be performed after the anisotropic-etching. As described above, the transition metal layer137′ may be oxidized or oxynitrified into insulating pattern in the crystallization-annealing process. Referring toFIG.4F, the opening portion H (formed with the metal oxide channel layer135′ and the oxidized or oxynitrified transition metal layer137′) may be filled with a buried insulating layer, and this buried insulating layer may be planarization-etched. Accordingly, an insulating pillar141aand an upper ending portion of the metal oxide channel layer135′ surrounding the insulating pillar141amay be exposed simultaneously when an upper plane of the stack S is exposed. Thus, an upper electrode155covering the insulating pillar141aand the metal oxide channel layer135′ may be formed. The upper electrode155may be a bit line or a conductive pad connecting to the bit line. InFIG.4F, a structure of a vertical non-volatile memory device according to an example embodiment is described. The vertical non-volatile memory device according to an example embodiment may include an insulating pillar141aextending in a direction of an upper portion of the substrate100. The interlayer insulating films117and the control gate patterns115amay be disposed to be stacked alternately on a side portion of the insulating pillar141a. There oxidized or oxynitrified transition metal layer137′ and the polycrystalline metal oxide channel layer135′ may be disposed to be stacked in order on the insulating pillar141abetween the insulating pillar141aand the control gate patterns115aand extend along the insulating pillar141a. For example, a sidewall of the insulating pillar141amay be disposed to be wrapped with the oxidized or oxynitrified transition metal layer137′, and the polycrystalline metal oxide channel layer135′ on the oxidized or oxynitrified transition metal layer137′ may be disposed to wrap a sidewall of the insulating pillar141a. The tunnel insulating film133, the charge storage film125, and the blocking insulating film122may be disposed in order between the polycrystalline metal oxide channel layer135′ and each of the control gate patterns115a. In an example embodiment, a horizontal width in parallel with a substrate surface of the control gate patterns115amay be narrower than a horizontal width of the interlayer insulating films117positioned on the upper and lower portion. Accordingly, grooves Ha (which expose the control gate pattern115aon a side portion and expose the interlayer insulating film117on the upper and lower portion) may be defined between the interlayer insulating films117. The blocking insulating film122may conformally coat an inner surface of the grooves Ha. The charge storage film125may fill the grooves Ha that are conformally coated with the blocking insulating film122. The tunnel insulating film133may cover the charge storage film125. FIGS.5A to5Dare cross sectional views of stages in a method of fabricating a vertical NAND flash memory device according to an example embodiment. The fabricating method of the device according to an example embodiment may be similar to the fabricating method of the device described above with reference toFIGS.4A to4Fexcept for as described below. Referring toFIG.5A, a lower insulating film113may be formed on the substrate100. A stack S, in which a plurality of control gate films115and a plurality of interlayer insulating films117are alternately stacked, may be formed on the lower insulating film113. For example, n pairs of the control gate film115and the interlayer insulating film117may be stacked to form a stack including L1, L2, . . . , Ln of unit layers. The substrate100may include an impurity region105enhanced in conductivity by being doped with impurities compared to a bulk substrate. The impurity region105may be a common source line. An opening portion H may be formed to penetrate through the stack (i.e., a plurality of the control gate films115and a plurality of interlayer insulating films117which are alternately stacked) and lower insulating films113and expose the substrate100, e.g., the impurity region105within a bottom surface. With formation of the opening portion H, the control gate pattern115ainterposed between the insulating films117,113may be defined, and the control gate pattern115amay be exposed within a sidewall of the opening portion H. Referring toFIG.5B, a blocking insulating film123, a charge storage film126, and the tunnel insulating film133may be conformally formed along a surface profile on the substrate100having the control gate pattern115aexposed within a sidewall of the opening portion H, and may be anisotropic-etched. As a result, the blocking insulating film123, the charge storage film126, and the tunnel insulating film133, which are stacked in order on a sidewall of the opening portion H, may be formed. According to an example embodiment, the charge storage film126may be a silicon nitride film. The blocking insulating film123may be a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film having a high-k dielectric constant. The tunnel insulating film133may be a silicon oxide film. The metal oxide channel layer135may be conformally formed on a sidewall of the opening portion H formed with the tunnel insulating film133and the common source line105. The substrate100formed with the metal oxide channel layer135may be post-deposition annealed. The transition metal layer137may be conformally formed on the metal oxide channel layer135. After the transition metal layer137is formed, the resulting material may be crystallization-annealed. The metal oxide channel layer135, the post-deposition annealing, the transition metal layer137, and the crystallization-annealing may be same as the described above with reference toFIG.4D. The metal oxide channel layer135may be crystallized with the above crystallization-annealing and may be modified to the polycrystalline metal oxide channel layer135including crystallized grains in a C-axis, and further, the transition metal layer137may be oxidized or oxynitrified and modified to transition metal oxide or transition metal oxynitride, which is an insulating material. Referring toFIG.5C, as the transition metal layer137and the metal oxide channel layer135are anisotropically etched, the patterned metal oxide channel layer135′ and the oxidized or oxynitrified transition metal layer137′ (which are stacked in order on the tunnel insulating film133formed on a sidewall of the opening portion H) may be formed simultaneously when the common source line105is exposed within the opening portion H. After the patterned metal oxide channel layer135′ is formed, the oxidized or oxynitrified transition metal layer137′ may be additionally anisotropically etched. As a result, a region where the metal oxide channel layer135′ is exposed may be produced without being covered with the transition metal layer137′ at a gate of the opening portion H. The crystallization-annealing described with reference toFIG.5Bmay be performed after the anisotropic etching. As described above, the transition metal layer137′ may be an oxidized or oxynitrified into insulating pattern in the crystallization-annealing process. Referring toFIG.5D, as the opening portion H (formed with the metal oxide channel layer135′ and the oxidized or oxynitrified transition metal layer137′) is filled with the buried insulating film and the buried insulating film is planarization-etched, an upper portion of the stack S may be exposed simultaneously when the insulating pillar141aand an upper ending portion of the metal oxide channel layer135′ surrounding the insulating pillar141aare exposed. Further, an upper electrode155, which covers the insulating pillar141aand the metal oxide channel layer135′ exposed with an upper portion as surrounding the insulating pillar, may be formed. The upper electrode155may be a bit line or a conductive pad connecting to the bit line. InFIG.5D, a structure of a vertical non-volatile memory device according to an example embodiment is described. The vertical non-volatile memory device according to an example embodiment may include an insulating pillar141aextending in a direction of an upper portion of the substrate100. The interlayer insulating films117and the control gate patterns115amay be disposed to be stacked alternately on a side portion of the insulating pillar141a. The oxidized or oxynitrified transition metal layer137′ and the polycrystalline metal oxide channel layer135′ may be disposed to be stacked in order on the insulating pillar141abetween the insulating pillar141aand the control gate patterns115a, and may extend along the insulating pillar141a. For example, a sidewall of the insulating pillar141amay be disposed to be wrapped with the oxidized or oxynitrified transition metal layer137′, and the polycrystalline metal oxide channel layer135′ on the oxidized or oxynitrified transition metal layer137′ may be disposed to wrap a sidewall of the insulating pillar141a. Between the polycrystalline metal oxide channel layer135′ and the control gate pattern115a, the tunnel insulating film133, the charge storage film126, and the blocking insulating film123may be disposed in order. The tunnel insulating film133, the charge storage film126, and the blocking insulating film123may be disposed to extend in a region between the polycrystalline metal oxide channel layer135′ and the interlayer insulating films117. Thus, the tunnel insulating film133, the charge storage film126, and the blocking insulating film123may be disposed to wrap a sidewall of the insulating pillar141aon the polycrystalline metal oxide channel layer135′. The following Examples and Comparative Examples are provided in order to highlight characteristics of one or more embodiments, but it will be understood that the Examples and Comparative Examples are not to be construed as limiting the scope of the embodiments, nor are the Comparative Examples to be construed as being outside the scope of the embodiments. Further, it will be understood that the embodiments are not limited to the particular details described in the Examples and Comparative Examples. Examples 1-8: TFT Fabrication A 100 nm SiO2layer was grown on a p-type of Si wafer by thermally oxidizing a p-type Si wafer. A 15 nm amorphous IGZO (In:Ga:Zn=1:1:1 at %) semiconductor pattern was deposited on the SiO2layer by RF sputtering in an Ar atmosphere and using a shadow mask. The RF power was 100 W, and a chamber pressure was 3 mTorr. ITO source/drain electrodes were formed on both side end portions of the semiconductor pattern by disposing a shadow mask on the semiconductor pattern, and depositing ITO in utilization of DC sputtering under Ar atmosphere. The DC power was 50 W, and operation pressure was 5 mTorr. A width of the semiconductor pattern was 1000 μm and an exposed length of the semiconductor pattern between the source/drain electrodes was 300 μm. Then, the post-deposition annealing (PDA) was performed in 02 atmosphere at 400° C. for one hour. A 20 nm of Ta layer was formed by sputtering using a shadow mask on the semiconductor pattern exposed between the source/drain electrodes. A width of Ta layer was 2300 μm (which was greater than a width of the semiconductor pattern), and a length of Ta layer was 150 μm (which was less than an exposed length of the semiconductor pattern between the source/drain electrodes). A plurality of such samples were fabricated and crystallization-annealed for one hour in different temperatures and atmospheres. Crystallization-annealing conditions of the samples are summarized in Table 1 below. Comparative Examples 1-4 TFTs were fabricated in the similar manner to the examples except for that a Ta layer was not formed, and the crystallization-annealing conditions are summarized in Table 1 below. Comparative Example 5 A TFT was fabricated in the similar manner to the examples except for that a Ta layer was not formed and the crystallization-annealing was not performed. TABLE 1CrystallizationCrystallizationFormation ofannealingannealingTa layeratmospheretemperatureExample 1◯O2200° C.Example 2◯O2300° C.Example 3◯O2400° C.Example 4◯O2500° C.Example 5◯N2200° C.Example 6◯N2300° C.Example 7◯N2400° C.Example 8◯N2500° C.ComparativeXO2400° C.Example 1ComparativeXO2700° C.Example 2ComparativeXN2400° C.Example 3ComparativeXN2700° C.Example 4ComparativeXSecond annealing not performedExample 5 In the Table 1, a small amount of the air may be included within the crystallization-annealing atmosphere. FIG.6Aillustrates X-ray diffraction (XRD) spectra with respect to Ta/IGZO/SiO2/Si stack portion of TFT according to Examples 1 to 4 and IGZO/SiO2/Si stack portion of TFT according to Comparative Examples 1 and 2. FIG.6Billustrates XRD spectra with respect to Ta/IGZO/SiO2/Si stack portion of TFT according to Examples 5 to 8 and IGZO/SiO2/Si stack portion of TFT according to Comparative Examples 3 and 4. XRD analysis was conducted in step scan mode in which step size (2θ) was 0.02°, and 0.3 second per step and Cu-Kα radiation (40 kV, 30 mA) were used. Referring toFIGS.6A and6B, an XRD peak at a proximity to 56°, which appears in every sample, is caused from Si substrate. An IGZO/SiO2/Si stack which is annealed in oxygen or nitrogen atmosphere at 400° C. according to Comparative Examples 1 and 3 shows broad pattern only, without a pointed diffraction peak at a proximity to about 33°, which indicates that the IGZO layer remained amorphous. The XRD spectrum of an IGZO/SiO2/Si stack annealed in oxygen or nitrogen atmosphere at 700° C. according to Comparative Examples 2 and 4 shows a recognizable diffraction peak (009), which indicates that IGZO layer is crystallized. Referring toFIG.6A, when annealing is performed at 200° C. (Example 1) among Ta/IGZO/SiO2/Si stack according to Examples 1 to 4 in which Ta layer is applied to the amorphous IGZO layer and annealing is performed at 200 to 500° C. in oxygen atmosphere, strong diffraction peaks appear at 33.7° and 38.5°, which respectively show (002) and (110) planes of a tetragonal β-Ta layer. Further, when 300° C. annealing (Example 2) was performed, the peaks showing a Ta layer are shifted at a lower angle (which indicates an increase of distance between lattices because of increased thermal stress within Ta layer) and clear peak is observed at a proximity to 33° (which may be caused when a (009) plane of IGZO which is crystalline plane oriented in a C-axis). From the above result, it may be analyzed that lattice arrangement and partial crystallization according to the lattice arrangement are generated on an interface of Ta/IGZO when 300° C.-annealing is performed (Example 2). In a state in which Ta layer is not formed, IGZO layer is not crystallized even after 400° C. annealing is performed (Comparative Example 1), and IGZO layer is crystallized at last after 700° C. annealing is performed (Comparative Example 2). Meanwhile, when Ta layer is formed on IGZO layer, it was confirmed that the IGZO layer was crystallized even at a lower temperature of 300° C., and from the result, it can be seen that when a Ta layer is formed on an IGZO layer, crystallization temperature of IGZO layer may be significantly lowered. Further, when a Ta layer is applied to the amorphous IGZO layer and annealed at 400° C. in oxygen atmosphere (Example 3), IGZO (014), (015) peaks appear together with a pointed IGZO (009) peak, which indicates that IGZO layer is in a well-defined crystalline state. Simultaneously, metal Ta peaks do not appear anymore, which indicates that Ta layer is oxidized as being annealed within 02 atmosphere and modified to TaOx layer. When Ta layer is applied to the amorphous IGZO layer and annealed at 500° C. (Example 4), the size of IGZO peaks decreases, and a pointed peak at 35° that can correspond to (002) plane of ZnO or (400) phase of bixbyite In2O3appears, which indicates that, at high annealing temperature, a bond between cations becomes weaker rather than rearrangement into crystalline grain of InGaZnO4, and small grains of ZnO or In2O3are formed. Referring toFIG.6Bagain, when annealing is performed at 200° C. (Example 5) among Ta/IGZO/SiO2/Si stack according to Examples 5 to 8 in which Ta layer is applied to the amorphous IGZO layer and annealing is performed at 200 to 500° C. in nitrogen atmosphere, a peak showing TaON (201) plane is confirmed. Further, when annealing is performed at 300° C. (Example 6), a peak, which is observed at a proximity to 33° together with a peak showing (201) plane of TaON and caused from (009) plane of IGZO, is confirmed. From this result, like when annealing is performed at 300° C. in an oxygen atmosphere (Example 2), when annealing is performed at 300° C. in a nitrogen atmosphere (Example 6), it may be seen that lattice arrangement at an interface of Ta/IGZO and partial crystallization thereof are generated. Further, generation of peaks showing TaON (201) plane from Ta layer when annealed in nitrogen atmosphere may be seen to be oxynitrification of Ta layer because of oxygen supplied from IGZO layer and the air and nitrogen supplied from the annealing atmosphere. As described above, when Ta layer is formed on IGZO layer, it is confirmed that the IGZO layer is crystallized even at a relatively lower temperature of 300° C. not only in oxygen atmosphere but also in nitrogen atmosphere, such that a crystallization temperature is significantly lowered with Ta layer. Further, when a Ta layer is applied to the amorphous IGZO layer and annealed at 400° C. in nitrogen atmosphere (Example 7), intensity of an IGZO (009) peak becomes greater, which means the IGZO layer is in a well-defined crystalline state. When a Ta layer is applied to the amorphous IGZO layer and annealed at 500° C. in nitrogen atmosphere (Example 8), a size of IGZO peaks decreases, and a pointed peak at 35° corresponding to (002) plane of ZnO or (400) phase of bixbyite In2O3appears, and this result represents that bond between cations becomes weak at high annealing temperature rather than rearrangement of crystalline grains of InGaZnO4, and small grains of ZnO or In2O3are formed. Simultaneously, TaON (201) peaks do not appear anymore, which indicates that the Ta layer is further nitrified as being annealed within N2atmosphere and modified to TaNxlayer. FIGS.7A,7B, and7Cillustrate cross sectional transmission electron microscopy (TEM) images and selected area electron diffraction (SAED) patterns of TaOx/IGZO/SiO2/Si stacks of TFT formed respectively according to Examples 1 to 3. Referring toFIG.7A, when annealing is performed at 200° C. (Example 1), a crystalline region is not observed anywhere of an interface A of TaOx/IGZO or a neighbored place B of a channel region which is IGZO/SiO2interface. Referring toFIG.7B, when annealing is performed at 300° C. (Example 2), small crystalline grains are formed in an entire IGZO layer, as well as TaOx/IGZO interface C and a neighboring place D of a channel region, which is an IGZO/SiO2interface. Thus, it is analyzed that IGZO layer is rearranged over an entire region while small crystalline grains are formed within the amorphous matrix. Herein, the small crystalline grains may be disposed to be isolated from each other. Referring toFIG.7C, when annealing is performed at 400° C. (Example 3), the size of crystalline grains becomes greater in an entire IGZO layer compared to the annealing performed at 300° C., and crystallinity of an interface F of IGZO/SiO2increases. Further, as crystallinity of an interface E of TaOx/IGZO is higher than the interface F of IGZO/SiO2, it is assumed that crystallization is performed in depth direction of IGZO layer, i.e., in a direction of SiO2(which is a gate insulating film) after crystallization by Ta starts in TaOx/IGZO interface therefrom. FIGS.8A and8Bare graphical representations respectively provided to illustrate atom composition profiles in a depth direction with respect to TaOx/IGZO/SiO2/Si stacks of TFT formed according to Examples 1 and 2. The above may be obtained by sputtering Ar+ion of 1 keV energy on a surface of the stacks with the X-ray photo electron spectroscopy method (XPS, SIGMA PROBE ThermoG, UK). Referring toFIGS.8A and8B, as a Ta layer is oxidized after being annealed and modified to TaOx layer, a TaOx/IGZO/SiO2stack is confirmed to be formed. InFIG.8B, as a fraction of In and Ga atoms slightly increases on an interface within Ta layer, it is assumed that oxygen atoms bonded with In and Ga react with Ta. FIG.9is a view provided to illustrate O 1s XPS spectrum within IGZO layer of resulting materials according to Example 1(b), Example 2(c) and Comparative Example 5(a); Referring toFIG.9, sub-peaks at 530.9 and 532.0 eV represent oxygen bonded with metal ions being completely coordinated (M-O lattice) and hydroxyl group-related oxygen bond, respectively. With respect to IGZO layer (Example 2, (c)) in which Ta layer is formed on an upper portion and annealing is performed at 300° C. in oxygen atmosphere compared to IGZO layer (Comparative Example 5, (a)) in which Ta layer is not formed and crystallization annealing is not performed, M-O lattice fraction greatly increases from 87% to 97% while hydroxyl group-related fraction greatly decreases from 13% to 3%. Accordingly, in consideration of decrease in hydroxyl group-related fraction, oxygen species loosely bonded with metal atom within IGZO layer, e.g., interstitial oxygen, hydroxyl group, or the like, are removed and consumed while TaOx is formed by reacting with Ta during the annealing process. Further, an increase in M-O lattice fraction indicates increase in a crystallization rate of IGZO, which is described below with reference toFIG.10. FIG.10is a schematic view provided to explain crystallization of IGZO by Ta. Referring toFIG.10, as an interface of a Ta layer on IGZO layer is oxidized into TaOx with oxygen species loosely bonded with metal atoms within IGZO layer, the Ta layer may emit electrons into the IGZO layer. Such electrons may be delivered to an antibonding orbital of a M-O bond, and accordingly, the M-O bond of an interface may become weak. Further, as M-O bond of the interface becomes weak during the annealing process, it may be rearranged from the interface after being broken and such rearrangement may be transferred within IGZO layer. Thus, an entire IGZO layer may be modified to be crystalline, e.g., polycrystalline, at a relatively low temperature. The following Table 2 shows field-effect electron mobility (μFe), subthreshold swing (SS), subthreshold voltage (VTH), and Ion/off of TFT according to Examples 1 to 3 and Comparative Example 5. TABLE 2μFE(cm2/Vs)SS (V/decade)VTH(V)(@ VDS= 0.1 V)(@ VDS= 0.1 V)(@ VDS= 5.1 V)Ion/offComparative18.1 ± 0.60.8 ± 0.10.9 ± 0.21.2 × 107Example 5Example 142.7 ± 2.70.4 ± 0.10.5 ± 0.23.4 × 107Example 254.0 ± 4.70.3 ± 0.10.2 ± 0.24.4 × 107Example 337.3 ± 1.10.5 ± 0.10.7 ± 0.32.2 × 107 Referring to Table 2, compared to a TFT according to Comparative Example 5 (in which Ta layer is not formed on IGZO layer and second annealing is not performed), TFTs according to Example 1, Example 2, and Example 3 (in which Ta layer is formed on IGZO layer and second annealing is performed at 200° C., 300° C., and 400° C.) show a high value and a low VTHvalue. With respect to Example 2 (in which annealing is performed at 300° C.), an enhanced μFEvalue of three times that of Comparative Example 5 is obtained. However, with respect to Example 3 in which annealing is performed at 400° C., a lower μFEvalue, i.e., lower electron mobility is obtained compared to Example 2. In consideration of the above results, it is assumed that crystallization advances too much and grain boundaries (which can operate as an energy barrier to electron conduction) are extensively formed with respect to Example 3. Meanwhile, with respect to Example 2, excellent electron mobility is obtained because crystallization advances in some degree, but grain boundaries are generated without excessiveness and/or crystalline grains do not grow up as much as a grain boundary is formed. FIG.11is graphical representation provided to illustrate an output characteristic (IDS-VDS) of TFTs according to Examples 1 to 3 and Comparative Example 5. Referring toFIG.11, while the output characteristic of TFT according to Example 1 is enhanced compared to TFT according to Comparative Example 5 and output characteristic of TFT according to Example 2 is enhanced, the output characteristic of TFT according to Example 3 is enhanced compared to Comparative Example 5 but reduced compared to Example 1. As described above with reference to Table 2, it is understood that, with respect to the TFT according to Example 4 in which grain boundary is extensive, the output characteristic is also lowered due to decrease in electron mobility. By way of summation and review, for a silicon film used as a semiconductor film of a transistor, an amorphous silicon film or a polycrystalline silicon film may be used. For example, with respect to a transistor included in a large display apparatus, an amorphous silicon film may be used in which film characteristics are relatively uniform even when formed as a large dimensional size. As another example, with respect to a device including a driving circuit or the like, a polycrystalline silicon film may be used to effect high field effect mobility. A method of annealing the amorphous silicon film at high temperature or treating with a laser beam may be used to form the polycrystalline silicon film. When an oxide semiconductor is used as a channel layer of a transistor, an amorphous oxide semiconductor layer may have disadvantages relative to electrical and chemical stability. Conversely, forming a crystalline oxide semiconductor layer from an amorphous layer may involve annealing at high temperature (e.g., more than 700 degrees C.) or performing an in-situ heating method. As described above, embodiments may provide a thin film transistor and a vertical NAND flash memory device including a polycrystalline oxide semiconductor thin film which is formed at relatively low temperature range and exhibits high field effect mobility. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims. | 55,697 |
11942554 | EMBODIMENT FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the following description, and the mode and details can be variously changed unless departing from the spirit and scope of the present invention. Accordingly, the present invention should not be interpreted as being limited to the content of the embodiments described below. Note that the position, size, range, or the like of each structure illustrated in the drawings and the like do not represent the actual position, size, and range in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like. In addition, the ordinal numbers such as “first”, “second”, and the like in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers in some cases. Therefore, for example, description can be made even when “first” is replaced with “second” or “third”, as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those which specify one embodiment of the present invention. Furthermore, in this specification, terms for describing placement, such as “over” and “under” are used for convenience in describing a positional relation between components with reference to drawings. In addition, the positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, description of the positional relation can be rephrased appropriately according to the situation, without being limited by the terms used in this specification. Furthermore, in describing the structure of the invention with reference to the drawings in this specification and the like, the same reference numerals denoting the same components are commonly used in different diagrams. Furthermore, in this specification and the like, a “semiconductor” includes characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. Also, an “insulator” in this specification and the like can be called a “semi-insulator” in some cases. Furthermore, in this specification and the like, a “semiconductor” includes characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification and the like can be called an “insulator” in some cases. Similarly, an “insulator” in this specification and the like can be called a “semiconductor” in some cases. Also, an “insulator” in this specification and the like can be called a “semi-insulator” in some cases. Furthermore, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. The transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. Note that in this specification and the like, a channel region refers to a region through which current mainly flows. Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be interchanged with each other in this specification and the like. Note that the channel length refers to, for example, the distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a plan view of the transistor. Note that, in one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Therefore, in this specification and the like, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. Note that, in one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification and the like, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. Furthermore, in this specification and the like, the term “electrically connected” includes the case where components are connected through “an object having any electric function”. Here, there is no particular limitation on “an object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring. Furthermore, a voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a ground potential (GND) or a source potential). Therefore, a voltage can also be referred to as potential. Furthermore, in this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases. Furthermore, unless otherwise specified, off-state current in this specification and the like refers to drain current of a transistor in an off state (also referred to as a non-conducting state and a cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that the voltage Vgs between its gate and source is lower than the threshold voltage Vth, and the off state of a p-channel transistor means that the voltage Vgs between its gate and source is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current at the time when the voltage Vgs between the gate and source is lower than the threshold voltage Vth. The off-state current of a transistor depends on Vgs in some cases. Thus, “the off-state current of a transistor is lower than or equal to I” may mean “there is a Vgs value with which the off-state current of the transistor becomes lower than or equal to I”. The off-state current of a transistor may refer to the off-state current in an off state at predetermined Vgs, in an off state at Vgs in a predetermined range, in an off state at Vgs with which sufficiently reduced off-state current is obtained, or the like. As an example, the assumption is made of an n-channel transistor where the threshold voltage Vth is 0.5 V and the drain current is 1×10−9A at a voltage Vgs of 0.5 V, 1×10−13A at a voltage Vgs of 0.1 V, 1×10−19A at a voltage Vgs of −0.5 V, and 1×10−22A at a voltage Vgs of −0.8 V. The drain current of the transistor is 1×10−19A or lower at Vgs of −0.5 V or at Vgs in the range of −0.5 V to −0.8 V; therefore, it can be said that the off-state current of the transistor is 1×10−19A or lower. Since there is Vgs at which the drain current of the transistor is 1×10−22A or lower, it can be said that the off-state current of the transistor is 1×10−22A or lower. In this specification and the like, the off-state current of a transistor with a channel width W is sometimes represented by a flowing current value per channel width W or by a flowing current value per given channel width (e.g., 1 μm). In the latter case, the off-state current may be expressed in the unit with the dimension of current per length (e.g., A/μm). The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like including the transistor is used (e.g., a temperature higher than or equal to 5° C. and lower than or equal to 35° C.). The description “an off-state current of a transistor is lower than or equal to I” may refer to a situation where there is a value Vgs at which the off-state current of the transistor is lower than or equal to I at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., a temperature higher than or equal to 5° C. and lower than or equal to 35° C.). The off-state current of a transistor depends on voltage Vds between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current might be an off-state current at Vds at which the reliability of a semiconductor device or the like including the transistor is ensured or Vds at which the semiconductor device or the like including the transistor is used. The description “an off-state current of a transistor is lower than or equal to I” may mean that there is a Vgs value at which the off-state current of the transistor is lower than or equal to I at Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, at Vds at which the reliability of a semiconductor device or the like including the transistor is ensured, or at Vds at which the semiconductor device or the like including the transistor is used. In the above description of off-state current, a drain may be replaced with a source. That is, the off-state current sometimes refers to a current that flows through a source of a transistor in the off state. Furthermore, in this specification and the like, the term “leakage current” may be used for the same meaning as “off-state current”. In addition, in this specification and the like, the off-state current sometimes refers to current that flows between a source and a drain of a transistor in the off state, for example. Furthermore, in this specification, “parallel” refers to a state in which two straight lines are placed at an angle of greater than or equal to −10° and less than or equal to 10°. Thus, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. In addition, “substantially parallel” refers to a state in which two straight lines are placed at an angle of greater than or equal to −30° and less than or equal to 30°. In addition, “perpendicular” refers to a state in which two straight lines are placed at an angle of greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. In addition, “substantially perpendicular” refers to a state in which two straight lines are placed at an angle of greater than or equal to 60° and less than or equal to 120°. Furthermore, in this specification, when a crystal is of trigonal or rhombohedral, it is expressed as a hexagonal system. Embodiment 1 In this embodiment, an example of a semiconductor device of one embodiment of the present invention and a manufacturing method of the semiconductor device will be described with reference toFIG.1toFIG.16. Structure Example 1 of Semiconductor Device FIG.1(A)is a top view of a transistor100included in a semiconductor device of one embodiment of the present invention. In addition,FIG.1(B)is a cross-sectional view taken along a dashed-dotted line X1-X2shown inFIG.1(A), andFIG.1(C)is a cross-sectional view taken along a dashed-dotted line Y1-Y2shown inFIG.1(A). Note that some components (e.g., a substrate102and an insulating film) of the transistor100are not illustrated inFIG.1(A)for simplicity. In some cases, the direction of the dashed-dotted line X1-X2inFIG.1(A)is referred to as the channel length (L) direction of the transistor100, and the direction of the dashed-dotted line Y1-Y2is referred to as the channel width (W) direction of the transistor100. The transistor100includes a conductive film106functioning as a first gate electrode (also referred to as bottom gate electrode) over a substrate102, an insulating film104over the substrate102and the conductive film110, an oxide semiconductor film108over the insulating film104, an insulating film110over the oxide semiconductor film108, an oxide semiconductor film112and a conductive film114functioning as a second gate electrode (also referred to as top gate electrode) over the insulating film110, and an insulating film116over the insulating film104, the oxide semiconductor film108, the oxide semiconductor film112, and the conductive film114. The oxide semiconductor film108includes a channel region108ioverlapping with the oxide semiconductor film112and the conductive film114and in contact with the insulating film110, a source region108sin contact with the insulating film116, and a drain region108din contact with the insulating film116. Furthermore, the transistor100includes an insulating film118over the insulating film116, a conductive film120selectrically connected to the oxide semiconductor film108in the source region108sthrough an opening141sprovided in the insulating films116and118, and a conductive film120delectrically connected to the oxide semiconductor film108in the drain region108dthrough an opening141dprovided in the insulating films116and118. Note that in this specification and the like, the insulating film104may be referred to as a first insulating film, the insulating film110may be referred to as a second insulating film, the insulating film116may be referred to as a third insulating film, and the insulating film118may be referred to as a fourth insulating film. Furthermore, in the transistor100, the insulating film104functions as a first gate insulating film, and the insulating film110functions as a second gate insulating film. Thus, in this specification and the like, the insulating film104may be referred to as a first gate insulating film, and the insulating film110may be referred to as a second gate insulating film. In addition, the conductive film120sfunctions as a source electrode, and the conductive film120dfunctions as a drain electrode. Thus, in this specification and the like, the conductive film120smay be referred to as a source electrode, and the conductive film120dmay be referred to as a drain electrode. The oxide semiconductor film112has a function of supplying oxygen to the insulating film110. The oxide semiconductor film112having a function of supplying oxygen to the insulating film110enables the insulating film110to contain excess oxygen. When the insulating film110includes an excess oxygen region, the excess oxygen can be supplied to the oxide semiconductor film108, more specifically, the channel region108i. Thus, a semiconductor device with high reliability can be provided. Note that, in order to supply excess oxygen to the oxide semiconductor film108, excess oxygen may be supplied to the insulating film104that is formed under the oxide semiconductor film108. However, in that case, oxygen contained in the insulating film104can also be supplied to the source region108sand the drain region108dof the oxide semiconductor film108. When excess oxygen is supplied to the source region108sand the drain region108d, the resistance of the source region108sand the drain region108dmight be increased. By contrast, the structure in which the insulating film110formed over the oxide semiconductor film108contains excess oxygen enables excess oxygen to be selectively supplied only to the channel region108i. Alternatively, after excess oxygen is supplied to the channel region108i, the source region108s, and the drain region108d, the carrier density in the source region108sand the drain region108dmay be selectively increased. The insulating film116contains at least one of nitrogen and hydrogen. When the insulating film116contains at least one of nitrogen and hydrogen, at least one of nitrogen and hydrogen can be supplied to the oxide semiconductor film108and the oxide semiconductor film112. As a result, the source region108sand the drain region108dcan be formed in the oxide semiconductor film108. In addition, after supplying oxygen to the insulating film110, the oxide semiconductor film112is supplied with at least one of nitrogen and hydrogen from the insulating film116or the conductive film114, whereby a donor level is formed in the vicinity of the conduction band and the carrier density is increased. In other words, the oxide semiconductor film112also functions as an oxide conductor (OC). Thus, the oxide semiconductor film112has a higher carrier density than at least the channel region108iof the oxide semiconductor film108. An oxide semiconductor generally transmits visible light because of its large energy gap. An oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Thus, the influence of absorption due to the donor level is small in an oxide conductor, and the oxide conductor has a visible light transmitting property comparable to that of an oxide semiconductor. Accordingly, it is preferable that the conductive film114be provided over the oxide semiconductor film112in order to prevent light from entering the oxide semiconductor film112. The conductive film114is preferably a material having a light-shielding property. In addition, a material with high conductivity is preferable, in other words, its sheet resistance is preferably low. Specifically, the sheet resistance of the conductive film114is preferably lower than or equal to 100 Ω/sq., and more preferably lower than or equal to 10 Ω/sq. Thus, the conductive film114preferably contains a metal. Furthermore, when the conductive film114has a function of excessively supplying at least one of nitrogen and hydrogen, there may be a case where at least one of nitrogen and hydrogen is supplied to the channel region108iof the oxide semiconductor film108. Thus, the function of supplying at least one of nitrogen and hydrogen of the conductive film114is preferably low. In addition, the function of allowing the passage of at least one of nitrogen and hydrogen of the conductive film114is preferably low. Furthermore, the source region108sand the drain region108dof the oxide semiconductor film108and the oxide semiconductor film112may each contain an element that forms an oxygen vacancy. Typical examples of the element that forms an oxygen vacancy include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas. Typical examples of the rare gas element are helium, neon, argon, krypton, and xenon. An impurity element added to the oxide semiconductor film cuts a bond between a metal element and oxygen in the oxide semiconductor film, so that an oxygen vacancy is formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to a metal element in the oxide semiconductor film is bonded to the impurity element, and the oxygen is released from the metal element, whereby an oxygen vacancy is formed. As a result, the oxide semiconductor film has a higher carrier density and thus the conductivity becomes higher. In addition, the transistor100preferably includes a region where a side end portion of the insulating film110, a side end portion of the oxide semiconductor film112, and a side end portion of the conductive film114are aligned. In other words, the transistor100has a structure in which an upper end portion of the insulating film110and an upper end portion of the oxide semiconductor film112are substantially aligned, and a structure in which the upper end portion of the oxide semiconductor film112and a lower end portion of the conductive film114are substantially aligned. The above structure can be obtained by processing the insulating film110with the use of the conductive film114as a mask, for example. In addition, the transistor100includes a region where the conductive film106and the conductive film114are in contact with each other through an opening143provided in the insulating film104, the insulating film110, and the oxide semiconductor film112, and the conductive film106and the conductive film114are electrically connected. Accordingly, the same potential is applied to the conductive film106and the conductive film114. In order to reduce power consumed by the transistor100or to stabilize the electrical characteristics of the transistor100, the contact resistance (contact resistance) or contact chain resistance between the conductive film106and the conductive film114is preferably low. As described above, the transistor100has a structure in which a conductive film functioning as a gate electrode is provided over and under the oxide semiconductor film108. «S-Channel Structure» As illustrated inFIG.1(C), the oxide semiconductor film108is sandwiched, with the first gate insulating film and the second gate insulating film positioned therebetween, between the conductive film106that functions as the first gate electrode and the oxide semiconductor film112and the conductive film114that function as the second gate electrode. The length of the conductive film106in the channel width direction is greater than the length of the oxide semiconductor film108in the channel width direction. Furthermore, the length of the oxide semiconductor film112in the channel width direction is greater than the length of the oxide semiconductor film108in the channel width direction. Furthermore, the length of the conductive film114in the channel width direction is greater than the length of the oxide semiconductor film108in the channel width direction. In addition, since the conductive film106and the conductive film114have regions where they are in contact with each other to be electrically connected through the opening143provided in the insulating film104, the insulating film110, and the oxide semiconductor film112, at least one of the side surfaces of the oxide semiconductor film108in the channel width direction faces the conductive film114with the insulating film110positioned therebetween. That is, the oxide semiconductor film108as a whole in the channel width direction is covered with the conductive film106and the conductive film114with the first gate insulating film and the second gate insulating film positioned therebetween. In other words, in the channel width direction of the transistor100, the conductive film106and the conductive film114surround the oxide semiconductor film108with the first gate insulating film and the second gate insulating film positioned therebetween. With such a structure, electric fields of the conductive film106functioning as the first gate electrode and the conductive film114functioning as the second gate electrode can electrically surround the oxide semiconductor film108included in the transistor100. A device structure of a transistor, like that of the transistor100, in which electric fields of a first gate electrode and a second gate electrode electrically surround an oxide semiconductor film where a channel region is formed can be referred to as a Surrounded channel (abbreviation: S-channel) structure. Since the transistor100has the S-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film108by the conductive film106and the conductive film114. Accordingly, the current drive capability of the transistor100is increased, so that high on-state current characteristics can be obtained. Furthermore, since the on-state current can be increased, the size of the transistor100can be reduced. Furthermore, since the transistor100has a structure enveloped by the conductive film106and the conductive film114, the mechanical strength of the transistor100can be increased. In addition, with the above structure, the region where carriers flow in the oxide semiconductor film108is increased to include the insulating film104side of the oxide semiconductor film108, the insulating film110side of the oxide semiconductor film108, and inside the oxide semiconductor film108; thus, the amount of carrier transfer in the transistor100is increased. As a result, the on-state current of the transistor100is increased, and the field-effect mobility is also increased to, for example, higher than or equal to 10 cm2/V·s. Note that here, the field-effect mobility is not an approximate value of the mobility as the physical property of the oxide semiconductor film but is an index of the current drive capability of the transistor in a saturation region and the apparent field-effect mobility. Note that, in the channel width direction of the transistor100, an opening different from the opening143may be formed on the opposite side of the portion where the opening143is formed across the oxide semiconductor film108. <Components of the Semiconductor Device> Components included in the semiconductor device of this embodiment will be described in detail below. «Oxide Semiconductor Film» An oxide semiconductor can be used for the oxide semiconductor film108in the transistor100of one embodiment of the present invention. An oxide semiconductor will be described below. An oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin, or the like is preferably contained. Furthermore, one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained. Here, the case where an oxide semiconductor contains indium, an element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that two or more of the above elements may be used in combination as the element M. First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to one embodiment of the present invention will be described with reference toFIG.14(A),FIG.14(B), andFIG.14(C). Note that the atomic proportion of oxygen is not illustrated inFIG.14. Furthermore, the terms of the atomic ratio of indium to the element M and zinc in the oxide semiconductor are denoted by [In], [M], and [Zn], respectively. InFIG.14(A),FIG.14(B), andFIG.14(C), broken lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−a):1(−1≤a≤1, a is greater than or equal to −1 and less than or equal to 1), a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−a):2, a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−a):3, a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−a):4, and a line where the atomic ratio [In]:[M]:[Zn] is (1+a):(1−a):5. Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β, (β≥0, beta is greater than or equal to 0), a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β. The oxide semiconductor illustrated inFIG.14with an atomic ratio of [In]:[M]:[Zn]=0:2:1 or in the neighborhood thereof is likely to have a spinel crystal structure. FIG.14(A)andFIG.14(B)illustrate examples of the preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to one embodiment of the present invention. As an example,FIG.15illustrates the crystal structure of InMZnO4in which [In]:[M]:[Zn] is 1:1:1. The crystal structure inFIG.15is InMZnO4observed from a direction parallel to the b-axis. Note that a metal element in a layer that contains the element M, zinc, and oxygen (hereinafter referred to as “(M,Zn) layer”) inFIG.15represents the element M or zinc. In that case, the proportion of the element M is equal to the proportion of zinc. The element M and zinc can be replaced with each other, and their arrangement is random. Note that InMZnO4has a layered crystal structure (also referred to as layered structure) and includes two (M,Zn) layers with respect to one layer that contains indium and oxygen (hereinafter referred to as In layer), as illustrated inFIG.15. Indium and the element M can be replaced with each other. Therefore, when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained. An oxide semiconductor whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. That is, as [Zn] is larger than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide semiconductor is crystallized. Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide semiconductor, the oxide semiconductor might have more than one kind of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case where [In]:[M]:[Zn] is 1:1:1.5, the oxide semiconductor may have a mix of a layered structure including one In layer for every two (M,Zn) layers and a layered structure including one In layer for every three (M,Zn) layers. For example, in the case where the oxide semiconductor is deposited by a sputtering apparatus, a film having an atomic ratio deviating from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition. Furthermore, more than one phase (e.g., two phases or three phases) might exist in the oxide semiconductor. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where more than one phase exists in the oxide semiconductor, a grain boundary might be formed between different crystal structures. In addition, the oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility). This is because in an oxide semiconductor containing indium, the element M, and zinc, the s orbital of heavy metal mainly contributes to carrier transfer, and a higher indium content in the oxide semiconductor enlarges a region where the s orbitals of indium atoms overlap; therefore, an oxide semiconductor with a high indium content has higher carrier mobility than an oxide semiconductor with a low indium content. By contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and in the neighborhood thereof (e.g., a region C inFIG.14(C)), the insulation performance becomes better. Accordingly, an oxide semiconductor according to one embodiment of the present invention preferably has an atomic ratio represented by a region A inFIG.14(A)with which carrier mobility is high and the layered structure tends to have fewer grain boundaries. A region B inFIG.14(B)represents an atomic ratio of [In]:[M]:[Zn]=4:2:3 to 4.1 and the neighborhood thereof. The neighborhood includes an atomic ratio of [In]:[M]:[Zn]=5:3:4. An oxide semiconductor with an atomic ratio represented by the region B is an excellent oxide semiconductor that has particularly high crystallinity and high carrier mobility. Note that conditions where a layered structure of an oxide semiconductor is formed are not uniquely determined by the atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, on the other hand, a layered structure might be or might not be formed depending on a formation condition. Therefore, the illustrated regions each represent an atomic ratio with which an oxide semiconductor has a layered structure, and boundaries of the regions A to C are not clear. Next, a structure in which the oxide semiconductor is used for a transistor will be described. Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; thus, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability. An oxide semiconductor with low carrier density is preferably used for a channel region of the transistor. For example, an oxide semiconductor whose carrier density is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, further preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3is used. Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources and thus can have a low carrier density. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases. Charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and may behave like fixed charge. Thus, the transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases. Accordingly, in order to obtain stable electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor in channel formation region. In addition, in order to reduce the concentration of impurities in the oxide semiconductor, the concentration of impurities in a film that is adjacent to the oxide semiconductor is preferably reduced. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like are given. Here, the influence of impurities in the oxide semiconductor is described. When silicon or carbon that is one of Group 14 elements is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon and carbon around an interface with the oxide semiconductor (the concentration measured by secondary ion mass spectrometry (SIMS)) is set lower than or equal to 2×1018atoms/cm3, and preferably lower than or equal to 2×1017atoms/cm3. When the oxide semiconductor contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated, in some cases. Thus, a transistor including an oxide semiconductor that contains alkali metal or alkaline earth metal in a channel region is likely to be normally-on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor in the channel region. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is set lower than or equal to 1×1018atoms/cm3, and preferably lower than or equal to 2×1016atoms/cm3. When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons functioning as carriers and an increase of carrier density. Thus, a transistor including an oxide semiconductor that contains nitrogen for a channel region is likely to have normally-on characteristics. Accordingly, nitrogen in the oxide semiconductor in the channel region is preferably reduced as much as possible; for example, the concentration of nitrogen in the oxide semiconductor measured by SIMS is lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, and still further preferably lower than or equal to 5×1017atoms/cm3. In addition, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus causes formation of an oxygen vacancy, in some cases. Entry of hydrogen into the oxygen vacancy generates an electron functioning as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron functioning as a carrier. Thus, a transistor including an oxide semiconductor that contains hydrogen for a channel region is likely to have normally-on characteristics. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, in the oxide semiconductor of the channel region, the hydrogen concentration measured by SIMS is set lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, still further preferably lower than 1×1018atoms/cm3. When an oxide semiconductor with sufficiently reduced impurity is used for a channel region in a transistor, the transistor can have stable electrical characteristics. The energy gap of the oxide semiconductor film is preferably 2 eV or more, 2.5 eV or more, or 3 eV or more. The thickness of the oxide semiconductor film is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 60 nm. When the oxide semiconductor film is an In-M-Zn oxide, as the atomic ratio of metal elements in a sputtering target used for formation of the In-M-Zn oxide, In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7, or the like is preferable. Note that the atomic ratios of metal elements in the formed oxide semiconductor films may each vary from the above atomic ratio of metal elements in the sputtering target within a range of approximately ±40%. For example, in the case where a sputtering target with an atomic ratio of In to Ga and Zn is 4:2:4.1, the atomic ratio of In to Ga and Zn in the formed oxide semiconductor film may be around 4:2:3. In the case where a sputtering target with an atomic ratio of In to Ga and Zn is 5:1:7 is used, the atomic ratio of In to Ga and Zn in the formed oxide semiconductor film may be around 5:1:6. On the other hand, the source region108sand the drain region108dare in contact with the insulating film116. Since the source region108sand the drain region108dare in contact with the insulating film116, at least one of hydrogen and nitrogen are added from the insulating film116to the source region108sand the drain region108d, so that the carrier densities are increased. Note that, without limitation to the above structure, a material with an appropriate composition is used for the oxide semiconductor film108in accordance with required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of a transistor. To obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor film be set appropriately. Furthermore, the oxide semiconductor film108may have a non-single-crystal structure. The non-single-crystal structure includes a c axis aligned crystalline oxide semiconductor (CAAC-OS), which will be described later, a polycrystalline structure, a microcrystalline structure, which will be described later, and an amorphous structure, for example. Among the non-single-crystal structure, the amorphous structure has the highest density of defect states, whereas CAAC-OS has the lowest density of defect states. Note that the oxide semiconductor film108may be a single-layer film or have a stacked-layer structure, including two or more of the following: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single-crystal structure. In the oxide semiconductor film108, the crystallinity of the channel region108imay be different from that of the source region108sand the drain region108d. Specifically, in the oxide semiconductor film108, the source region108sand the drain region108dmay have lower crystallinity than the channel region108i. This is because the source region108sand the drain region108dare damaged when an impurity element is added to the source region108sand the drain region108d, which results in a decrease in the crystallinity. The oxide semiconductor film112may be formed using materials and a manufacturing method similar to those of the oxide semiconductor film108described above. For example, an In oxide, an In—Sn oxide, an In—Zn oxide, an In—Ga oxide, a Zn oxide, an Al—Zn oxide, an In—Ga—Zn oxide, or the like can be used for the oxide semiconductor film112. It is particularly preferable to use an In—Sn oxide or an In—Ga—Zn oxide. Furthermore, for the oxide semiconductor film112, a material such as indium tin oxide (abbreviation: ITO) or indium tin oxide containing silicon (abbreviation: ITSO) can be used. Furthermore, when the oxide semiconductor film112and the oxide semiconductor film108include the same metal element, the manufacturing cost can be reduced. For example, in the case where an In-M-Zn oxide is used as the oxide semiconductor film112, a sputtering target used for forming the In-M-Zn oxide preferably includes a region where In is higher than or equal to M in the atomic ratio of metal elements. The atomic ratio of metal elements in such a sputtering target is In:M:Zn=2:1:3, In:M:Zn=3:1:2, InM:Zn=4:2:4.1, In:M:Zn=5:1:7, or the neighborhood thereof. Note that as the oxide semiconductor film112, the composition of the sputtering target is not limited to that described above. In addition, as the oxide semiconductor film112, a single-layer structure or a stacked-layer structure of two or more layers can be used. Note that an oxide semiconductor typified by an In—Ga—Zn oxide can be used as the oxide semiconductor film112. The oxide semiconductor can have a high carrier density when at least one of nitrogen and hydrogen are supplied from the insulating film116. In other words, the oxide semiconductor included in the oxide semiconductor film112functions as an oxide conductor (OC). Accordingly, the oxide semiconductor can be used as a gate electrode. In the case where the second gate electrode is a structure including the oxide semiconductor film112and the conductive film114, for example, a stacked-layer structure using the above-described oxide conductor (OC) for the oxide semiconductor film112and using a metal film as the conductive film114is preferable. In the case where a stacked-layer structure including an oxide semiconductor and a metal film with a light-shielding property is used as the second gate electrode, the channel region108iformed under the oxide semiconductor film112can be shielded from light, which is preferable. Furthermore, in the case a stacked-layer structure including an oxide semiconductor or an oxide conductor (OC) and a metal film with a light-shielding property is used as the oxide semiconductor film112, formation of a metal film (e.g., a titanium film or a tungsten film) over the oxide semiconductor or the oxide conductor (OC) causes any of the following: reduction in resistance due to the diffusion of constituent elements of the metal film to the oxide semiconductor or oxide conductor (OC) side; reduction in resistance due to damage (e.g., sputtering damage) during the formation of the metal film; and reduction in resistance due to the formation of an oxygen vacancy following the diffusion of oxygen in the oxide semiconductor or the oxide conductor (OC) into the metal film. «Insulating Film Functioning as First Gate Insulating Film» The insulating film104can be formed by appropriately using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. In addition, the insulating film104can be formed as a single layer or a stacked-layer of an oxide insulating film and a nitride insulating film, for example. Note that, in order to improve the properties of the interface with the oxide semiconductor film108, at least a region of the insulating film104which is in contact with the oxide semiconductor film108is preferably formed of an oxide insulating film. When an oxide insulating film that releases oxygen by being heated is used as the insulating film104, oxygen contained in the insulating film104can be moved to the oxide semiconductor film108by heat treatment. The thickness of the insulating film104can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film104, the amount of oxygen released from the insulating film104can be increased, and interface states at the interface between the insulating film104and the oxide semiconductor film108and oxygen vacancies included in the channel region108iof the oxide semiconductor film108can be reduced. The insulating film104can be formed as a single layer or a stacked layer using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn oxide, or the like, for example. In this embodiment, the insulating film104has a stacked-layer structure including a silicon nitride film and a silicon oxynitride film. With the insulating film104having such a stack-layer structure including a silicon nitride film as a lower layer and a silicon oxynitride film as an upper layer, oxygen can be efficiently introduced into the oxide semiconductor film108. Note that in this specification and the like, a silicon oxynitride refers to a material in which, as its composition, the proportion of oxygen is higher than that of nitrogen, preferably containing oxygen, nitrogen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic % inclusive, 1 atomic % to 20 atomic % inclusive, 25 atomic % to 35 atomic % inclusive, and 0.1 atomic % to 10 atomic % inclusive, respectively. Silicon nitride oxide refers to a material in which, as its composition, the proportion of nitrogen is higher than that of oxygen, preferably containing nitrogen, oxygen, silicon, and hydrogen in the ranges of 55 atomic % to 65 atomic % inclusive, 1 atomic % to 20 atomic % inclusive, 25 atomic % to 35 atomic % inclusive, and 0.1 atomic % to 10 atomic % inclusive, respectively. Note that at least a region of the insulating film104in contact with the oxide semiconductor film108is preferably an oxide insulating film and preferably includes a region (oxygen-excess region) that contains oxygen in excess of that in the stoichiometric composition. In other words, the insulating film104is an insulating film that is capable of releasing oxygen. Note that, in order to provide the oxygen-excess region in the insulating film104, the insulating film104is formed in an oxygen atmosphere, for example. Alternatively, oxygen may be added to the insulating film104after the formation. A method for adding oxygen to the insulating film104after the formation will be described later. For the insulating film104, a high-k material such as hafnium silicate (HfSiOx), hafnium silicate to which nitrogen is added (HfSixOyNz), hafnium aluminate to which nitrogen is added (HfAlxOyNz), hafnium oxide, or yttrium oxide can be suitably used. The material containing hafnium or yttrium has higher dielectric constant than silicon oxide and silicon oxynitride. Accordingly, the use of the above high-k materials for the insulating film104allows the film thickness to be increased as compared with a case where a silicon oxide film is used; therefore, leakage current due to tunnel current can be reduced. That is, it is possible to provide a transistor with low off-state current. Moreover, hafnium oxide with a crystal structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Thus, it is preferable to use hafnium oxide with a crystal structure in order to provide a transistor with low off-state current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. However, one embodiment of the present invention is not limited to the above examples. Note that, in this embodiment, the insulating film104is formed by stacking a silicon nitride film on the conductive film106side and a silicon oxide film on the oxide semiconductor film108side. A silicon nitride film has a higher dielectric constant than a silicon oxide film and needs a larger thickness for a capacitance equivalent to that of the silicon oxide film. Therefore, when the first gate insulating film of the transistor100includes a silicon nitride film, the physical thickness of the first gate insulating film can be large. This makes it possible to reduce a decrease in withstand voltage of the transistor100and furthermore to increase the withstand voltage, thereby reducing electrostatic discharge damage to the transistor100. «Insulating Film Functioning as Second Gate Insulating Film» The insulating film110functions as a gate insulating film of the transistor100. In addition, the insulating film110has a function of supplying oxygen to the oxide semiconductor film108, particularly to the channel region108i. The insulating film110can be formed as a single layer or a stacked layer of an oxide insulating film or a nitride insulating film, for example Note that, in order to improve the properties of the interface with the oxide semiconductor film108, a region of the insulating film110in contact with the oxide semiconductor film108is preferably formed using at least an oxide insulating film. Silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride may be used for the insulating film110, for example. The thickness of the insulating film110can be greater than or equal to 5 nm and less than or equal to 400 nm, greater than or equal to 5 nm and less than or equal to 300 nm, or greater than or equal to 10 nm and less than or equal to 250 nm. It is preferable that the insulating film110have few defects and typically have as few signals observed by electron spin resonance (ESR) spectroscopy as possible. As the above-mentioned signal, an E′ center observed at a g-factor of 2.001 can be given, for example. Note that the E′ center is due to the dangling bond of silicon. As the insulating film110, a silicon oxide film or a silicon oxynitride film whose spin density due to the E′ center is lower than or equal to 3×1017spins/cm3and preferably lower than or equal to 5×1016spins/cm3may be used. In addition to the above-described signal, a signal due to nitrogen dioxide (NO2) might be observed in the insulating film110. The signal is divided into three signals according to the N nuclear spin: one observed at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039 (which is a first signal), one observed at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003 (which is a second signal), and one observed at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 (which a third signal). It is suitable to use an insulating film whose spin density due to nitrogen dioxide (NO2) is higher than or equal to 1×1017spins/cm3and lower than 1×1018spins/cm3as the insulating film110, for example. Note that a nitrogen oxide (NOx) including a nitrogen dioxide (NO2) forms a level in the insulating film110. The level is positioned in the energy gap of the oxide semiconductor film108. Thus, when nitrogen oxide (NOx) is diffused to the interface between the insulating film110and the oxide semiconductor film108, an electron might be trapped by the level on the insulating film110side. As a result, the trapped electron remains in the vicinity of the interface between the insulating film110and the oxide semiconductor film108; thus, the threshold voltage of the transistor is shifted in the positive direction. Accordingly, the use of a film with a low nitrogen oxide content as the insulating film110can reduce a shift of the threshold voltage of the transistor. As an insulating film that releases a small amount of nitrogen oxide (NOx), for example, a silicon oxynitride film can be used. The silicon oxynitride film releases more ammonia than nitrogen oxide (NOx) in thermal desorption spectroscopy (TDS); the typical released amount of ammonia is greater than or equal to 1×1018cm−3and less than or equal to 5×1019cm−3. Note that the released amount of ammonia is the total amount at the temperature of heat treatment ranging from 50° C. to 650° C. inclusive or 50° C. to 550° C. inclusive in TDS. Since nitrogen oxide (NOx) reacts with ammonia and oxygen in heat treatment, the use of an insulating film that releases a large amount of ammonia reduces nitrogen oxide (NOx). Note that in the case where the insulating film110is analyzed by SIMS, nitrogen concentration in the film is preferably lower than or equal to 6×1020atoms/cm3. As the insulating film110, a high-k material such as hafnium silicate (HfSiOx), hafnium silicate to which nitrogen is added (HfSixOyNz), hafnium aluminate to which nitrogen is added (HfAlxOyNz), or hafnium oxide may be used. The use of such a high-k material can reduce gate leakage current of a transistor. The insulating film110may be formed by a CVD method using an organosilane gas. As the organosilane gas, any of the following silicon-containing compound can be used: tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4); tetramethylsilane (TMS: chemical formula Si(CH3)4); tetramethylcyclotetrasiloxane (TMCTS); octamethylcyclotetrasiloxane (OMCTS); hexamethyldisilazane (HMDS); triethoxysilane (SiH(OC2H5)3); trisdimethylaminosilane (SiH(N(CH3)2)3); or the like. The insulating film110having high coverage can be formed by a CVD method using an organosilane gas. «Third Insulating Film» The insulating film116contains at least one of nitrogen and hydrogen. The insulating film116is a nitride insulating film, for example. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The hydrogen concentration in the insulating film116is preferably higher than or equal to 1×1022atoms/cm3. Furthermore, the insulating film116is in contact with the source region108sand the drain region108dof the oxide semiconductor film108. In addition, the insulating film116has a region in contact with the oxide semiconductor film112. Therefore, the hydrogen concentrations in the source region108s, the drain region108d, and the oxide semiconductor film112in contact with the insulating film116are increased; thus, the carrier densities in the source region108s, the drain region108d, and the oxide semiconductor film112can be increased. Note that, since the source region108s, the drain region108d, and the oxide semiconductor film112are each in contact with the insulating film116, they have regions with the same hydrogen concentration in some cases. «Fourth Insulating Film» The insulating film118can be formed as a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. The insulating film118can be formed as a single layer or a stacked layer using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn oxide, or the like, for example. Furthermore, the insulating film118preferably functions as a barrier film against hydrogen, water, and the like from the outside. The thickness of the insulating film118can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm. «Conductive Films Functioning as First Gate Electrode and a Pair of Electrodes» The conductive film106and the conductive films120sand120dcan be formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. Each of the conductive film106and the conductive films120sand120dcan be formed using, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing these metal elements in combination; or the like. Metal elements selected from one or more of manganese and zirconium may also be used. The conductive film106and the conductive films120sand120dmay each have a single-layer structure or a stacked-layer structure of two or more layers. The examples include: a single-layer structure of an aluminum film containing silicon; a single-layer structure of a copper film containing manganese; a two-layer structure in which a titanium film is stacked over an aluminum film; a two-layer structure in which a titanium film is stacked over a titanium nitride film; a two-layer structure in which a tungsten film is stacked over a titanium nitride film; a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film; a two-layer structure in which a copper film is stacked over a copper film containing manganese; a two-layer structure in which a copper film is stacked over a titanium film; a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order; or a three-layer structure in which a copper film containing manganese, a copper film, and a copper film containing manganese are stacked in this order. Alternatively, an alloy film or a nitride film in which aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used. It is particularly suitable to use a material containing copper for the conductive film106and the conductive films120sand120d. The use of a material containing copper for the conductive films106,120s, and120dcan reduce the resistance. A signal delay or the like can be suppressed even in the case where a large-sized substrate is used as the substrate102, for example. It is also possible to use, for the conductive film106and the conductive films120sand120d, a conductive material having a light-transmitting property such as: an oxide containing indium and tin (abbreviation: ITO); an oxide containing tungsten and indium; an oxide containing tungsten, indium, and zinc; an oxide containing titanium and indium; an oxide containing titanium, indium, and tin; an oxide containing indium and zinc; an oxide containing indium, gallium, and zinc; and an oxide containing silicon, indium, and tin (abbreviation: ITSO). A stacked-layer structure including the above conductive material having a light-transmitting property and the above metal element can also be employed. The thicknesses of the conductive film106and the conductive films120sand120dcan each be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm. «Conductive Film114Functioning as Second Gate Electrode» The conductive film114functioning as the second gate electrode can be formed using materials and a manufacturing method similar to those of the conductive film106functioning as the first gate electrode and the conductive films120sand120dfunctioning as a pair of electrodes described above. Alternatively, a stacked-layer structure of these may be used. The function of supplying at least one of nitrogen and hydrogen of the conductive film114is preferably low. In addition, the function of allowing the passage of at least one of nitrogen and hydrogen of the conductive film114is preferably low. Specifically, copper, molybdenum, tungsten, titanium, and tantalum, or a nitride of these are preferable, for example. A nitride containing nitrogen and a metal, such as molybdenum nitride, tantalum nitride, or titanium nitride is preferable since it has high conductivity, has a high barrier property against copper or hydrogen, and is stable. «Substrate» As the substrate102, any of a variety of substrates can be used without particular limitation. Examples of the substrate include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a ceramic substrate, a sapphire substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, a laminate film, paper including a fibrous material, or a base film. Examples of the glass substrate include a barium borosilicate glass, an aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the laminate film, and the base film include the following. For example, plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES). Another example is a synthetic resin such as acrylic. Other examples are polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples are polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, and paper. Specifically, when a transistor is formed using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to form a transistor with few variations in characteristics, size, shape, or the like and with high current capability and a small size. By forming a circuit with use of such a transistor, power consumption of the circuit can be reduced or the circuit can be highly integrated. Note that, in the case where a glass substrate is used as the substrate102, use of a large-sized substrate such as the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm) enables a large-sized display device to be fabricated. A flexible substrate may also be used as the substrate102, and the transistor may be formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate102and the transistor. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is then separated from the substrate102and transferred onto another substrate. In such a case, the transistor can be transferred to even a substrate having low heat resistance or a flexible substrate. Note that, for the above separation layer, a stacked-layer structure including inorganic films, which are a tungsten film and a silicon oxide film, or a structure in which a resin film of polyimide or the like is formed over a substrate can be used, for example. Examples of a substrate to which a transistor is transferred include, in addition to the above substrates over which the transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (silk, cotton, or hemp), a synthetic fiber (nylon, polyurethane, or polyester), a regenerated fiber (acetate, cupra, rayon, or regenerated polyester), and the like), a leather substrate, and a rubber substrate. By using such a substrate, a transistor with excellent properties or a transistor with low power consumption can be formed, a device with high durability can be manufactured, heat resistance can be provided, or reduction in weight or thickness can be achieved. Structure Examples 2 to 6 Of Semiconductor Device Next, structures different from that of the semiconductor device illustrated inFIGS.1(A), (B), and (C) will be described with reference toFIG.2toFIG.7. Structure Example 2 of Semiconductor Device FIG.2(A)is a top view of a transistor100A,FIG.2(B)is a cross-sectional view taken along dashed-dotted line X1-X2inFIG.2(A), andFIG.2(C)is a cross-sectional view taken along dashed-dotted line Y1-Y2inFIG.2(A). The transistor100A illustrated inFIGS.2(A), (B), and (C) is different from the transistor100described above in the shape of the oxide semiconductor film112and the conductive film114. Specifically, lower end portions of the oxide semiconductor film112included in the transistor100A are positioned more on the inside than upper end portions of the insulating film110. In other words, side end portions of the insulating film110are positioned more on the outside than side end portions of the oxide semiconductor film112. The above structure can be obtained by processing the oxide semiconductor film112, the conductive film114, and the insulating film110with the use of the same mask, and processing the oxide semiconductor film112and the conductive film114by a wet etching method and the insulating film110by a dry etching method, for example. When the oxide semiconductor film112and the conductive film114have the above structure, regions108fare formed in the oxide semiconductor film108in some cases. The regions108fare formed between the channel region108iand the source region108sand between the channel region108iand the drain region108d. The regions108ffunction as either one of high-resistance regions or low-resistance regions. The high-resistance regions have the same level of resistance as the channel region108iand do not overlap with the oxide semiconductor film112and the conductive film114functioning as the gate electrode. In the case where the regions108fare high-resistance regions, the regions108ffunction as what we call offset regions. In the case where the regions108ffunction as the offset regions, in order to suppress a decrease in the on-state current of the transistor100A, the regions108fmay each be 1 μm or less in the channel length (L) direction. The low-resistance regions have a resistance lower than that of the channel region108iand higher than that of the source region108sand the drain region108d. In the case where the regions108fare low-resistance regions, the regions108ffunction as what we call lightly doped drain (LDD) regions. In the case where the regions108ffunction as the LDD regions, an electric field in the drain region can be relieved, thereby reducing a change in the threshold voltage of the transistor due to the electric field in the drain region. Note that, in the case where the regions108fare low resistance regions, the regions108fare formed by supplying at least one of hydrogen and nitrogen to the regions108ffrom the insulating film116, for example, or by adding an impurity element from above the conductive film114with the use of the insulating film110, the oxide semiconductor film112, and the conductive film114as masks so that the impurity element is added to the oxide semiconductor film108through the insulating film110. Structure Example 3 of Semiconductor Device Next, a modification example of the semiconductor device illustrated inFIGS.2(A), (B), and (C) will be described with reference toFIGS.3(A)and (B). FIGS.3(A)and (B) are cross-sectional views of a transistor100B. A top view of the transistor100B is similar to that of the transistor100A illustrated inFIG.2(A)and will be described with reference toFIG.2(A). The cross-sectional view inFIG.3(A)is taken along dashed-dotted line X1-X2inFIG.2(A), and the cross-sectional view inFIG.3(B)is taken along dashed-dotted line Y1-Y2inFIG.2(A). The transistor100B is different from the above-described transistor100A in that an insulating film122functioning as a planarization insulating film is provided. The other components are similar to those of the transistor100A described above, and similar effects can be obtained. The insulating film122has a function of covering unevenness and the like caused by the transistor or the like. The insulating film122has an insulating property and is formed using an inorganic material or an organic material. Examples of the inorganic material include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, and aluminum nitride. Examples of the organic material include photosensitive resin materials such as an acrylic resin or a polyimide resin. Note that although the shapes of openings in the insulating film122are smaller than those of the openings141sand141dinFIGS.3(A)and (B), the shapes are not limited thereto and may be the same as or larger than those of the openings141sand141d, for example. In addition, althoughFIGS.3(A)and (B) illustrate an example in which the conductive films120sand120dare provided over the insulating film122, the structure is not limited thereto and may be that in which the conductive films120sand120dare formed over the insulating film118and the insulating film122is provided over the conductive films120sand120d. Structure Example 4 of Semiconductor Device Next, modification examples of the semiconductor device illustrated inFIGS.1(A), (B), and (C) will be described with reference toFIG.4andFIG.5. FIGS.4(A)and (B) are cross-sectional views of a transistor100C. A top view of the transistor100C is similar to that of the transistor100inFIG.1(A)and will be described with reference toFIG.1(A). The cross-sectional view inFIG.4(A)is taken along dashed-dotted line X1-X2inFIG.1(A), and the cross-sectional view inFIG.4(B)is taken along dashed-dotted line Y1-Y2inFIG.1(A). The transistor100C is different from the transistor100described above in the shape of the insulating film110. The other components are similar to those of the transistor100described above, and similar effects can be obtained. The insulating film110included in the transistor100C is positioned more on the inside than the oxide semiconductor film112. In other words, side surfaces of the insulating film110are positioned more on the inside than lower end portions of the oxide semiconductor film112. The structure inFIGS.4(A)and (B) can be obtained by processing the oxide semiconductor film112and the conductive film114and then side-etching the insulating film110by wet etching with an etchant or the like, for example. Note that, when the insulating film110has the above structure, hollow regions147are formed under the oxide semiconductor film112. The hollow regions147contain air and function as part of a gate insulating film. Note that the dielectric constant of the hollow regions147is approximately one, like that of the air. Accordingly, in the case where a voltage is applied to the oxide semiconductor film112functioning as a gate electrode in the structure of the transistor100C, the voltage applied to the channel region108iunder the hollow regions147is lower than the voltage applied to the channel region108iunder the insulating film110. Thus, the channel region108iunder the hollow regions147effectively functions as overlap regions (also referred to as Lov regions). Note that the Lov regions overlap with the oxide semiconductor film112functioning as a gate electrode and have lower resistance than the channel region108i. FIGS.5(A)and (B) are cross-sectional views of a transistor100D. A top view of the transistor100D is similar to that of the transistor100inFIG.1(A)and will be described with reference toFIG.1(A). The cross-sectional view inFIG.5(A)is taken along dashed-dotted line X1-X2inFIG.1(A), and the cross-sectional view inFIG.5(B)is taken along dashed-dotted line Y1-Y2inFIG.1(A). The transistor100D is different from the transistor100described above in the shapes of the insulating film110and the insulating film116. The other components are similar to those of the transistor100described above, and similar effects can be obtained. The insulating film110included in the transistor100D is positioned more on the inside than the oxide semiconductor film112and the conductive film114. In other words, side surfaces of the insulating film110are positioned more on the inside than lower end portions of the oxide semiconductor film112. The structure illustrated inFIGS.5(A)and (B) can be obtained by processing the oxide semiconductor film112and the conductive film114and then side-etching the insulating film110by wet etching with an etchant or the like, for example. Furthermore, when the insulating film116is formed after the formation of the insulating film110having the above structure, the insulating film116also enters a space under the oxide semiconductor film112and is in contact with the oxide semiconductor film108under the oxide semiconductor film112. With the above structure, the source region108sand the drain region108dare positioned more on the inside than the lower end portions of the oxide semiconductor film112. Thus, the transistor100D includes Lov regions. With the structure including the Lov regions like the transistors100C and100D, no high-resistance region is formed between the channel region108iand the source and drain regions108sand108d; accordingly, the on-state current of the transistor can be increased. Structure Example 5 of Semiconductor Device Next, modification examples of the semiconductor device illustrated inFIGS.1(A), (B), and (C) will be described with reference toFIG.6andFIG.7. FIGS.6(A) and6(B)are cross-sectional views of a transistor100E. A top view of the transistor100E is similar to that of the transistor100illustrated inFIG.1(A)and will be described with reference toFIG.1(A). The cross-sectional view inFIG.6(A)is taken along the dashed-dotted line X1-X2inFIG.1(A), and the cross-sectional view inFIG.6(B)taken along the dashed-dotted line Y1-Y2inFIG.1(A). The transistor100E is different from the transistor100described above in the shape of the oxide semiconductor film108. The other components are similar to those of the transistor100described above, and similar effects can be obtained. The oxide semiconductor film108of the transistor100E includes an oxide semiconductor film108_1over the insulating film116, an oxide semiconductor film108_2over the oxide semiconductor film108_1, and an oxide semiconductor film108_3over the oxide semiconductor film108_2. The channel region108i, the source region108s, and the drain region108deach have a stacked-layer structure of three layers: the oxide semiconductor films108_1, the oxide semiconductor film108_2, and the oxide semiconductor film108_3. FIGS.7(A)and (B) are cross-sectional views of a transistor100F. A top view of the transistor100F is similar to that of the transistor100illustrated inFIG.1(A)and will be described with reference toFIG.1(A). The cross-sectional view inFIG.7(A)is taken along the dashed-dotted line X1-X2inFIG.1(A), and the cross-sectional view inFIG.7(B)is taken along the dashed-dotted line Y1-Y2inFIG.1(A). The transistor100F is different from the transistor100described above in the structure of the oxide semiconductor film108. The other components are similar to those of the transistor100described above, and similar effects can be obtained. The oxide semiconductor film108of the transistor100F includes an oxide semiconductor film108_2over the insulating film116, and an oxide semiconductor film108_3over the oxide semiconductor film108_2. The channel region108i, the source region108s, and the drain region108deach have a stacked-layer structure of two layers: the oxide semiconductor film108_2and the oxide semiconductor film108_3. The transistor100F has a stacked-layer structure of the oxide semiconductor film108_2and the oxide semiconductor film108_3in the channel region108i. «Band Structure» Here, the case where the oxide semiconductor has a two-layer structure or a three-layer structure is described. A band diagram of insulators that are in contact with a stacked-layer structure of an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3and a band diagram of insulators that are in contact with a stacked-layer structure of the oxide semiconductor S2and the oxide semiconductor S3are described with reference toFIG.16. Note that inFIG.16, oxide semiconductors included in the oxide semiconductor films108_1,108_2, and108_3are represented as the oxide semiconductors S1, S2, and S3, and insulators included in the insulating films104and110are represented as insulators I1and I2. FIG.16(A)is an example of a band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2in a thickness direction.FIG.16(B)is an example of a band diagram of a stacked-layer structure including the insulator I1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2in the thickness direction. Note that for easy understanding, the band diagrams show the energy level of the conduction band minimum (Ec) of each of the insulator I1, the oxide semiconductor S1, the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2. The energy level of the conduction band minimum of each of the oxide semiconductors S1and S3is closer to the vacuum level than that of the oxide semiconductor S2, and typically, a difference in energy level between the conduction band minimum of the oxide semiconductor S2and the conduction band minimum of each of the oxide semiconductors S1and S3is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. That is, it is preferable that the difference between the electron affinity of each of the oxide semiconductors S1and S3and the electron affinity of the oxide semiconductor S2be greater than or equal to 0.15 eV or greater than or equal to 0.5 eV, and less than or equal to 2 eV or less than or equal to 1 eV. As illustrated inFIG.16(A)andFIG.16(B), the energy level of the conduction band minimum of each of the oxide semiconductors S1, S2, and S3is gradually varied. In other words, the energy level of the conduction band minimum is continuously varied or continuously connected. In order to obtain such a band diagram, the density of defect states in a mixed layer formed at an interface between the oxide semiconductors S1and S2or an interface between the oxide semiconductors S2and S3is preferably made low. Specifically, when the oxide semiconductors S1and S2or the oxide semiconductors S2and S3contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide semiconductor S2is an In—Ga—Zn oxide semiconductor, it is preferable to use an In—Ga—Zn oxide semiconductor, a Ga—Zn oxide semiconductor, gallium oxide, or the like as each of the oxide semiconductors S1and S3. At this time, the oxide semiconductor S2functions as a main carrier path. Since the density of defect states at the interface between the oxide semiconductors S1and S2and the interface between the oxide semiconductors S2and S3can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained. When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, the threshold voltage of the transistor is shifted in a positive direction. The provision of the oxide semiconductors S1and S3can make the trap state apart from the oxide semiconductor S2. With this structure, the threshold voltage of the transistor can be prevented from shifting in a positive direction. A material whose conductivity is sufficiently lower than that of the oxide semiconductor S2is used for the oxide semiconductors S1and S3. In that case, the oxide semiconductor S2, the interface between the oxide semiconductors S2and S1, and the interface between the oxide semiconductors S2and S3mainly function as a channel region. An oxide semiconductor with the atomic ratio represented by the region C inFIG.14(C), which has high insulation performance, can be used as the oxide semiconductors S1and S3, for example. Note that the region C inFIG.14(C)represents the atomic ratio of [In]:[M]:[Zn]=0:1:0 or the neighborhood thereof. In particular, in the case where an oxide semiconductor with the atomic ratio represented by the region A is used as the oxide semiconductor S2, it is preferable to use an oxide semiconductor with [M]/[In] of greater than or equal to one, preferably greater than or equal to two, as each of the oxide semiconductors S1and S3. In addition, it is suitable to use an oxide semiconductor with [M]/([Zn]+[In]) of greater than or equal to one, with which sufficiently high insulation performance can be obtained, as the oxide semiconductor S3. <Method 1 for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the transistor100illustrated inFIG.1will be described with reference toFIG.8toFIG.11. Note thatFIG.8toFIG.11are cross-sectional views in the channel length (L) direction and the channel width (W) direction, illustrating a method for manufacturing the transistor100. First, a conductive film to be the conductive film106is formed over the substrate102, and then the conductive film is processed into an island shape, whereby the conductive film106is formed (seeFIG.8(A)). The conductive film106can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, as the conductive film110, a 100-nm-thick tungsten film is formed by a sputtering method. Alternatively, a 10-nm-thick tantalum nitride film and a 100-nm-thick copper film are formed by a sputtering method. Then, the insulating film104is formed over the substrate102and the conductive film110, and an oxide semiconductor film is formed over the insulating film104. After that, the oxide semiconductor film is processed into an island shape, whereby the oxide semiconductor film107is formed (seeFIG.8(B)). The insulating film104can be formed by a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. In this embodiment, as the insulating film104, a 400-nm-thick silicon nitride film and a 50-nm-thick silicon oxynitride film are formed with the use of a PECVD apparatus. After the insulating film104is formed, oxygen may be added to the insulating film104. As oxygen to be added to the insulating film104, an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, or the like may be used. As the method for adding oxygen, an ion doping method, an ion implantation method, a plasma treatment method, or the like may be used. Alternatively, a film that suppresses oxygen release may be formed over the insulating film, and then, oxygen may be added to the insulating film104through the film. The above film that suppresses oxygen release can be formed using a material with conductivity such as: a metal element selected from indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten; an alloy containing the metal element as a component; an alloy containing any of the metal elements in combination; a metal nitride containing the metal element; a metal oxide containing the metal element; a metal nitride oxide containing the metal element; or the like. In the case where oxygen is added by plasma treatment, exciting oxygen by a microwave to generate high-density oxygen plasma can increase the amount of oxygen added to the insulating film104. The oxide semiconductor film107can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Note that processing into the oxide semiconductor film107can be performed by forming a mask over the oxide semiconductor film through a lithography process and then by etching part of the oxide semiconductor film with the use of the mask. Alternatively, the isolated oxide semiconductor film107may be directly formed by a printing method. In the case where the oxide semiconductor film is formed by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be used as appropriate as a power supply device for generating plasma. As a sputtering gas for forming the oxide semiconductor film, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as appropriate. Note that, in the case where the mixed gas of a rare gas and oxygen is used, the proportion of oxygen to a rare gas is preferably increased. Note that, in the case where the oxide semiconductor film is formed by a sputtering method, for example, the crystallinity can be improved by depositing the oxide semiconductor film at a substrate temperature higher than or equal to 150° C. and lower than or equal to 750° C., higher than or equal to 150° C. and lower than or equal to 450° C., or higher than or equal to 200° C. and lower than or equal to 350° C. Note that in this embodiment, as the oxide semiconductor film107, a 40-nm-thick oxide semiconductor film is deposited with the use of a sputtering apparatus using an In—Ga—Zn metal oxide (In:Ga:Zn=4:2:4.1 [atomic ratio]) as a sputtering target. After the oxide semiconductor film107is formed, heat treatment may be performed so that the oxide semiconductor film107is subjected to dehydrogenation or dehydration. The temperature of the heat treatment is typically higher than or equal to 150° C. and lower than the strain point of the substrate, higher than or equal to 250° C. and lower than or equal to 450° C., or higher than or equal to 300° C. and lower than or equal to 450° C. The heat treatment can be performed in an inert gas atmosphere containing a rare gas such as helium, neon, argon, xenon, or krypton, or nitrogen. Furthermore, heating in an inert gas atmosphere may be followed by heating in an oxygen atmosphere. Note that it is preferable that the above inert gas atmosphere and oxygen atmosphere do not contain no hydrogen, water, or the like. The treatment time is longer than or equal to three minutes and shorter than or equal to 24 hours. An electric furnace, an RTA apparatus, or the like can be used for the heat treatment. The use of an RTA apparatus allows the heat treatment to be performed at a temperature higher than or equal to the strain point of the substrate as long as the heating time is short. Thus, the heat treatment time can be shortened. By forming the oxide semiconductor film while it is heated or performing heat treatment after the formation of the oxide semiconductor film, the hydrogen concentration in the oxide semiconductor film, which is measured by secondary ion mass spectrometry, can be 5×1019atoms/cm3or lower, 1×1019atoms/cm3or lower, 5×1018atoms/cm3or lower, 1×1018atoms/cm3or lower, 5×1017atoms/cm3or lower, or 1×1016atoms/cm3or lower. Next, an insulating film110_0is formed over the insulating film104and the oxide semiconductor film107(seeFIG.8(C)). As the insulating film110_0, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method. In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide. A silicon oxynitride film having few defects can be formed as the insulating film110_0by a PECVD method setting the flow rate of the oxidizing gas to more than 20 times and less than 100 times, or more than or equal to 40 times and less than or equal to 80 times the flow rate of the deposition gas and setting the pressure in a treatment chamber to lower than 100 Pa or lower than or equal to 50 Pa. Furthermore, as the insulating film110_0, a silicon oxide film or a silicon oxynitride film that is dense can be formed as the insulating film110_0under the conditions where the substrate placed in a vacuum-evacuated treatment chamber of a PECVD apparatus is held at a temperature higher than or equal to 280° C. and lower than or equal to 400° C., the pressure in the treatment chamber into which a source gas is introduced is set to be higher than or equal to 20 Pa and lower than or equal to 250 Pa, preferably higher than or equal to 100 Pa and lower than or equal to 250 Pa, and a high-frequency power is supplied to an electrode provided in the treatment chamber. The insulating film110_0may be formed by a plasma CVD method using a microwave. A microwave refers to a wave in the frequency range of 300 MHz to 300 GHz. In a microwave, electron temperature is low and electron energy is low. Furthermore, in supplied power, the proportion of power used for acceleration of electrons is low, and therefore, power can be used for dissociation and ionization of more molecules; thus, plasma with high density (high-density plasma) can be excited. Accordingly, plasma damage to the deposition surface or a deposit is small, so that the insulating film110_0having few defects can be formed. The insulating film110_0can also be formed by a CVD method using an organosilane gas. As the organosilane gas, silicon-containing compounds such as tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), and trisdimethylaminosilane (SiH(N(CH3)2)3) can be used. By a CVD method using an organosilane gas, the insulating film110_0having high coverage can be formed. In this embodiment, as the insulating film110_0, a 150-nm-thick silicon oxynitride film is formed with the use of a PECVD apparatus. Next, an oxide semiconductor film112_0is formed over the insulating film110_0. Note that in the formation of the oxide semiconductor film112_0, oxygen is added from the oxide semiconductor film112_0to the insulating film110_0(seeFIG.8D). The oxide semiconductor film112_0is preferably formed by a sputtering method as the formation method, in an atmosphere containing an oxygen gas at the time of the formation. When the oxide semiconductor film112_0is formed in an atmosphere that contains an oxygen gas, oxygen can be added to the insulating film110_0well. Note that inFIG.8(D), oxygen added to the insulating film110_0is schematically depicted by arrows. Note that, for the oxide semiconductor film112_0, a material similar to that of the oxide semiconductor film107described above can be used. In this embodiment, as the oxide semiconductor film112_0, a 20-nm-thick oxide semiconductor film is deposited with the use of a sputtering apparatus using an In—Ga—Zn metal oxide (In:Ga:Zn=5:1:7 [atomic ratio]) as a sputtering target. Next, a mask is formed by lithography in a desired position over the oxide semiconductor film112_0, and then, the oxide semiconductor film112_0, the insulating film110_0, and the insulating film104are partly etched, so that the opening143reaching the conductive film106is formed (seeFIG.9A). As a method for forming the opening143, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment, the opening143is formed by using a dry etching method. Next, a conductive film114_0is formed over the oxide semiconductor film112_0so as to cover the opening143. When the conductive film114_0is formed so as to cover the opening143, the conductive film106and the conductive film114_0are electrically connected to each other (seeFIG.9(B)). Next, a mask140is formed by a lithography process in a desired position over the conductive film114_0(seeFIG.9(C)). Next, the conductive film114_0, the oxide semiconductor film112_0, and the insulating film110_0are processed by performing etching from above the mask140, and then, the mask140is removed, so that the island-shaped conductive film114, the island-shaped oxide semiconductor film112, and the island-shaped insulating film110are formed (seeFIG.9(D)). In this embodiment, a dry etching method is used for processing the conductive film114_0, the oxide semiconductor film112_0, and the insulating film110_0. Note that, at the time of processing the conductive film114, the oxide semiconductor film112, and the insulating film110, the thickness of the oxide semiconductor film107in a region not overlapping with the conductive film114is decreased in some cases. In some other cases, at the time of processing conductive film114, the oxide semiconductor film112, and the insulating film110, the thickness of the insulating film104in a region not overlapping with the oxide semiconductor film107is decreased. Next, an impurity element145is added from above the insulating film104, the oxide semiconductor film107, the oxide semiconductor film112, and the conductive film114(seeFIG.10(A)). Examples of the method for adding the impurity element145include an ion doping method, an ion implantation method, and a plasma treatment method. In a plasma treatment method, an impurity element can be added by performing plasma treatment by generating plasma in a gas atmosphere containing the impurity element to be added. A dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used as an apparatus for generating the plasma. As a source gas of the impurity element145, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, and a rare gas can be used. Alternatively, one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2, which are diluted with a rare gas, can be used. When one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2, which are diluted with a rare gas, are used to add the impurity element145to the oxide semiconductor films107and112, one or more of the rare gas, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, and chlorine can be added to the oxide semiconductor films107and112. Alternatively, after a rare gas is added, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2may be added to the oxide semiconductor films107and112. Alternatively, after at least one of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, and H2are added, a rare gas may be added to the oxide semiconductor films107and112. The addition of the impurity element145is controlled by appropriately setting the implantation conditions such as the accelerating voltage and the dose. For example, in the case where argon is added by an ion implantation method, the accelerating voltage is set higher than or equal to 10 kV and lower than or equal to 100 kV and the dose is set greater than or equal to 1×1013ions/cm2and less than or equal to 1×1016ions/cm2, for example, 1×1014ions/cm2. In the case where phosphorus ions are added by an ion implantation method, the accelerating voltage is set 30 kV and the dose is set greater than or equal to 1×1013ions/cm2and less than or equal to 5×1016ions/cm2, for example, 1×1015ions/cm2. Although in this embodiment an example in which the impurity element145is added after the mask140is removed is described, the impurity element145may be added with the mask140left, for example, without being limited to this embodiment. Furthermore, in this embodiment, argon is added as the impurity element145to the oxide semiconductor films107and112with the use of a doping apparatus. Note that in this embodiment an example in which argon is added as the impurity element145is described, nitrogen may be added, for example, without being limited to this embodiment. In addition, the step of adding the impurity element145need not necessarily be performed, for example. Next, the insulating film116is formed over the insulating film104, the oxide semiconductor film107, the oxide semiconductor film112, and the conductive film114. Note that the formation of the insulating film116causes the oxide semiconductor film107in contact with the insulating film116to become the source region108sand the drain region108d. In addition, the oxide semiconductor film107not in contact with the insulating film116, i.e., the oxide semiconductor film107in contact with the insulating film110becomes the channel region108i. In this manner, the oxide semiconductor film108including the channel region108i, the source region108s, and the drain region108dis formed (seeFIG.10(B)). The insulating film116can be formed using the material that can be used for the insulating film116. In this embodiment, as the insulating film116, a 100-nm-thick silicon nitride film is formed with the use of a PECVD apparatus. When a silicon nitride film is used as the insulating film116, hydrogen in the silicon nitride film enters the oxide semiconductor film112, the source region108s, and the drain region108din contact with the insulating film116, whereby the carrier densities in the oxide semiconductor film112, the source region108s, and the drain region108dcan be increased. Next, the insulating film118is formed over the insulating film116(seeFIG.10(C)). The insulating film118can be formed using the material that can be used for the insulating film118. In this embodiment, as the insulating film118, a 300-nm-thick silicon oxynitride film is formed with the use of a PECVD apparatus. Next, a mask is formed by lithography in a desired position of the insulating film118, and then, the insulating film118and the insulating film116are partly etched, so that the opening141sreaching the source region108sand the opening141dreaching the drain region108dare formed (seeFIG.11(A)). As a method for etching the insulating film118and the insulating film116, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment, the insulating film118and the insulating film116are processed by using a dry etching method. Next, the conductive film120is formed over the insulating film118so as to cover the openings141sand141d(seeFIG.11(B)). The conductive film120can be formed using the material that can be used for the conductive films120sand120d. In this embodiment, as the conductive film120, a stacked-layer film including a 50-nm-thick titanium film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film is formed with the use of a sputtering apparatus. Next, a mask is formed by a lithography process in a desired position over the conductive film120, and then, the conductive film120is partly etched, so that the conductive films120sand120dare formed (seeFIG.11(C)). As a method for processing the conductive film120, a wet etching method and/or a dry etching method can be used as appropriate. In this embodiment, the conductive film120is processed by using a dry etching method to form the conductive films120sand120d. Through the above process, the transistor100inFIG.1can be manufactured. Note that the films that constitute the transistor100(the insulating film, the oxide semiconductor film, the conductive film, and the like) can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method. They can also be formed by a coating method or a printing method. Although a sputtering method and a plasma-enhanced chemical vapor deposition (PECVD) method are typical examples of the film formation method, a thermal CVD method may also be used. As an example of a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method can be given. In a thermal CVD method, the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and a source gas and an oxidizer are supplied to the chamber at a time to react with each other in the vicinity of the substrate or over the substrate, whereby a film is deposited over the substrate. Thus, the thermal CVD method, which is a film formation method without plasma generation, has an advantage that no defect due to plasma damage is caused. In an ALD method, the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, and source gases for reaction are introduced into the chamber and reacted, which is repeated to perform the film formation. An inert gas (argon, nitrogen, or the like) may be introduced as a carrier gas with the source gases. Two or more kinds of source gases may be sequentially supplied to the chamber, for example. In that case, an inert gas is introduced after the reaction of a first source gas, and then a second source gas is introduced, so that the source gases are not mixed. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate and reacted to form a first layer, and the second source gas introduced after that is adsorbed and reacted, whereby a second layer is stacked over the first layer, so that a thin film is formed. The sequence of the gas introduction is controlled and repeated a plurality of times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetition times of the gas introduction, accurate adjustment of the film thickness is possible and thus it is suitable for manufacturing a minute FET. A thermal CVD method such as an MOCVD method can form the films such as the conductive films, the insulating films, the oxide semiconductor films, and the metal oxide films which are described above; for example, in the case where an In—Ga—Zn—O film is formed, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Without limitation to the above combination, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. In the case where a hafnium oxide film is formed by a deposition apparatus using ALD, for example, two kinds of gases, i.e., ozone (O3) as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor (hafnium alkoxide or a hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide)hafnium) are used. In the case where an aluminum oxide film is formed by a deposition apparatus using ALD, for example, two kinds of gases, i.e., H2O as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) or the like) are used. Examples of another material include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). In the case where a silicon oxide film is formed by a deposition apparatus using ALD, for example, hexachlorodisilane is adsorbed on a surface where a film is to be formed, and radicals of an oxidizing gas (O2, dinitrogen monoxide) are supplied to react with an adsorbate. In the case where a tungsten film is formed by a deposition apparatus using ALD, for example, a WF6gas and a B2H6gas are sequentially introduced to form an initial tungsten film, and then a tungsten film is formed using a WF6gas and an H2gas. Note that an SiH4gas may be used instead of a B2H6gas. In the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a deposition apparatus using ALD, for example, an In(CH3)3gas and an O3gas are used to form an In—O layer, a Ga(CH3)3gas and an O3gas are used to form a GaO layer, and then, a Zn(CH3)2gas and an O3gas are used to form a ZnO layer. Note that the order of these layers is not limited to this example. Furthermore, a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by using these gases. Note that although an H2O gas which is obtained by bubbling water with an inert gas such as Ar may be used instead of an O3gas, it is preferable to use an O3gas, which does not contain H. <Method 2 for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the transistor100B illustrated inFIG.3will be described with reference toFIG.12andFIG.13. Note thatFIG.12andFIG.13are cross-sectional views in the channel length (L) direction and the channel width (W) direction describing a method for manufacturing the transistor100B. First, in a manner similar to the manufacturing method of the transistor100described above, the conductive film110, the insulating film104, the oxide semiconductor film107, the oxide semiconductor film112_0, and the conductive film114_0are formed over the substrate102(seeFIG.8, andFIGS.9(A)and (B)). Next, the mask140is formed by a lithography process in a desired position over the conductive film114_0(seeFIG.9(C)). Next, the conductive film114_0and the oxide semiconductor film112_0are processed by performing etching from above the mask140, so that the island-shaped conductive film114and the island-shaped oxide semiconductor film112are formed (seeFIG.12(A)). In this embodiment, the conductive film114_0and the oxide semiconductor film112_0are processed by using a wet etching method. The etching is continuously performed from above the mask140to process the insulating film110_0, so that the island-shaped insulating film110is formed (seeFIG.12(B)). In this embodiment, the insulating film110_0is processed by using a dry etching method. Next, the mask140is removed, and then, the impurity element145is added from above the insulating film104, the oxide semiconductor film107, the oxide semiconductor film112, and the conductive film114(seeFIG.12(C)). Note that at the time of adding the impurity element145, a large number of impurities are added to the regions in which the surface of the oxide semiconductor film107is exposed (regions to be the source region108sand the drain region108dlater). In contrast, the impurity element145is added to regions of the oxide semiconductor film107which do not overlap with the oxide semiconductor film112but overlap with the insulating film110(regions to be the regions108flater) through the insulating film110, so that the amount of the impurity element145added thereto is smaller than that in the source region108sand the drain region108d. In this embodiment, argon is added as the impurity element145to the oxide semiconductor films107and112with the use of a doping apparatus. Note that although an example in which argon is added as the impurity element145is described in this embodiment, nitrogen may be added, for example, without being limited to this embodiment. In addition, the step of adding the impurity element145need not necessarily be performed, for example. In the case where the step of adding the impurity element145is not performed, the regions108fhave the same level of impurity concentration as the channel region108i. Next, the insulating film116is formed over the insulating film104, the oxide semiconductor film107, the insulating film110, the oxide semiconductor film112, and the conductive film114. Note that the formation of the insulating film116causes the oxide semiconductor film107in contact with the insulating film116to become the source region108sand the drain region108d. The oxide semiconductor film107not in contact with the insulating film116, i.e., the oxide semiconductor film107in contact with the insulating film110becomes the channel region108i. In this manner, the oxide semiconductor film108including the channel region108i, the source region108s, and the drain region108dis formed (seeFIG.12(D)). Note that the regions108fare formed between the channel region108iand the source region108sand between the channel region108iand the drain region108d. Next, the insulating film118is formed over the insulating film116(seeFIG.13(A)). Next, a mask is formed by lithography in a desired position over the insulating film118, and then, the insulating film118and the insulating film116are partly etched, so that the opening141sreaching the source region108sand the opening141dreaching the drain region108dare formed (seeFIG.13(B)). Next, the insulating film122is formed over the insulating film118(seeFIG.13(C)). Note that the insulating film122has a function of a planarization insulating film. Furthermore, the insulating film122has openings in positions overlapping with the opening141sand the opening141d. In this embodiment, as the insulating film122, a photosensitive acrylic-based resin is applied with the use of a spin coater apparatus, and then, desired regions of the acrylic-based resin are exposed to light, whereby the insulating film122having the openings is formed. Next, the conductive film120is formed over the insulating film122to cover the openings141sand141d(seeFIG.13(D)). Next, a mask is formed by a lithography process in a desired position over the conductive film120, and then, the conductive film120is partly etched, so that the conductive films120sand120dare formed. In this embodiment, the conductive film120is processed by a dry etching method. At the time of processing the conductive film120, an upper portion of the insulating film122is partly removed is some cases. Through the above steps, the transistor100B illustrated inFIG.3can be manufactured. Note that, in the manufacture of the above-described transistor100B, the insulating film104, the oxide semiconductor film107, the insulating film110_0, the oxide semiconductor film112_0, the conductive film114, the impurity element145, the insulating film116, the insulating film118, the openings141sand141d, and the conductive film120can be formed by referring to the description in <1-4. Method 1 for manufacturing semiconductor device>. Furthermore, although an example in which the transistor includes an oxide semiconductor film is described in this embodiment, one embodiment of the present invention is not limited to this example. In one embodiment of the present invention, the transistor need not necessarily include an oxide semiconductor film. For example, a channel region, the vicinity of the channel region, a source region, or a drain region of the transistor may be formed using a material containing S1(silicon), Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or the like. The structures and methods described in this embodiment above can be used in appropriate combination with the structures and methods described in the other embodiments. Embodiment 2 In this embodiment, the structure and the like of an oxide semiconductor will be described with reference toFIG.17toFIG.21. <Structure of Oxide Semiconductor> Oxide semiconductors can be classified into a single crystal oxide semiconductor and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include a CAAC-OS (c-axis-aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. From another perspective, oxide semiconductors can be classified into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS. An amorphous structure is generally said to be isotropic and have no non-uniform structure, to be metastable and not to have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example. This means that a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. By contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a pore (also referred to as a void). In point of being unstable, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties. <CAAC-OS> First, a CAAC-OS will be described. A CAAC-OS is a type of oxide semiconductors which has a plurality of c-axis aligned crystal parts (also referred to as pellets). A case where a CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when the structure of a CAAC-OS including an InGaZnO4crystal, which is classified into the space group R-3m, is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown inFIG.17(A). This peak is derived from the (009) plane of the InGaZnO4crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film. Note that a peak sometimes appears at a 2θ of around 36° in addition to the peak at a 2θ of around 31°. The peak at a 2θ of around 36° is derived from a crystal structure classified into the space group Fd-3m. Therefore, it is preferred that the CAAC-OS do not show the peak. On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO4crystal. When analysis (ϕ scan) is performed with 2θ fixed at around 56° while the sample is rotated around a normal vector to the sample surface as an axis (ϕ axis), as shown inFIG.17(B), a peak is not clearly observed. By contrast, in the case where single-crystal InGaZnO4is subjected to ϕ scan with 2θ fixed at around 56°, as shown inFIG.17(C), six peaks that are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4crystal in the direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) inFIG.17(D)appears in some cases. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in the direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,FIG.17(E)shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in the direction perpendicular to the sample surface. InFIG.17(E), a ring-like diffraction pattern is observed. Thus, the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have orientation. The first ring inFIG.17(E)is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO4crystal. In addition, the second ring inFIG.17(E)is considered to be derived from the (110) plane and the like. In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a crystal grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the crystal grain boundary is less likely to occur. A high-resolution TEM image of a cross section of the CAAC-OS layer which is observed from a direction substantially parallel to the sample surface is shown inFIG.18(A). For observation of the high-resolution TEM image, a spherical aberration corrector (Spherical Aberration Corrector) function was used. The high-resolution TEM image using a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. FromFIG.18(A), pellets in which metal atoms are arranged in a layered manner can be seen. It can be seen that the size of a pellet is greater than or equal to 1 nm, or greater than or equal to 3 nm. Accordingly, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis Aligned nanocrystals). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS. In addition,FIG.18(B)andFIG.18(C)show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.FIG.18(D)andFIG.18(E)are images obtained by processing images ofFIG.18(B)andFIG.18(C), respectively. The method of image processing is as follows. First, the image inFIG.18(B)is subjected to fast Fourier transform (FFT) to obtain an FFT image. Then, mask processing is performed such that a range of from 2.8 nm−1to 5.0 nm−1from the origin in the obtained FFT image remains. Next, the FFT image after the mask processing is processed by inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is called an FFT filtering image. The FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted, and shows a lattice arrangement. InFIG.18(D), portions in which the lattice arrangement is broken are shown by dashed lines. A region surrounded by a dashed line corresponds to one pellet. The portion denoted with the dashed line is a junction of pellets. The dashed line draws a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases. InFIG.18(E), a dotted line denotes a boundary between a region with a regular lattice arrangement and another region with a regular lattice arrangement. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of the atomic arrangement in an a-b plane direction, the interatomic bond distance changed by substitution of a metal element, and the like. As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a CAA crystal (c-axis-aligned a-b-plane-anchored crystal). The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor; thus, it can be said that the CAAC-OS is an oxide semiconductor with small amounts of impurities and defects (e.g., oxygen vacancies). Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element having higher strength of bonding to oxygen than a metal element that constitutes an oxide semiconductor, such as silicon, extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. <nc-OS> Next, an nc-OS is described. A case where an nc-OS is analyzed by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, for example, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation. Furthermore, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of a thinned nc-OS including an InGaZnO4crystal in the direction parallel to the formation surface, for example, a ring-like diffraction pattern (nanobeam electron diffraction pattern) shown inFIG.19(A)is observed. In addition,FIG.19(B)shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. FromFIG.19(B), a plurality of spots are observed in a ring-like region. Accordingly, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm. When an electron beam with a probe diameter of 1 nm is incident on a region with a thickness less than 10 nm, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape as shown inFIG.19(C)is observed in some cases. This means that an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions. FIG.19(D)shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed in the direction substantially parallel to the formation surface. In a high-resolution TEM image, an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines, and a region in which a crystal part is not clearly observed. In many cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or specifically, greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. As described above, in the nc-OS, a microscopic region (for example, a region greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. Furthermore, there is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. Note that, since there is no regularity of crystal orientation between the pellets (nanocrystals), the nc-OS can also be referred to as an oxide semiconductor including RANC (random aligned nanocrystals) or an oxide semiconductor including NANC (non-aligned nanocrystals). The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. However, there is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the nc-OS has a higher density of defect states than the CAAC-OS. <a-like OS> An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor. FIG.20shows high-resolution cross-sectional TEM images of an a-like OS. Here,FIG.20(A)is the high-resolution cross-sectional TEM image of the a-like OS at the start of the electron irradiation.FIG.20(B)is the high-resolution cross-sectional TEM image of the a-like OS after the irradiation with electrons (e) at 4.3×108e−/nm2.FIG.20(A)andFIG.20(B)show that stripe-like bright regions extending longitudinally are observed in the a-like OS from the start of the electron irradiation. It can also be found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region. The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below. An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide. First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. It is known that a unit cell of an InGaZnO4crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value), and the value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4in the following description. Note that each of lattice fringes corresponds to the a-b plane of the InGaZnO4crystal. FIG.21is an example of examining the average size (average crystal size) of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.FIG.21indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose (Cumulative electron dose) in obtaining TEM images, for example. As shown inFIG.21, a crystal part with a size of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e) dose of 4.2×108e−/nm2. By contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108e−/nm2. As shown inFIG.21, the crystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For the electron beam irradiation and TEM observation, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of electron beam irradiation were as follows: the accelerating voltage was 300 kV; the current density was 6.7×105e−/(nm2·s); and the diameter of the irradiation region was 230 nm. In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation in some cases. By contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. That is, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. Furthermore, the a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. An oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor is difficult to be deposited as a film. For an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], for example, the density of single crystal InGaZnO4with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, for the oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], for example, the density of the a-like OS is higher than or equal to 5.0 g/cm3and lower than 5.9 g/cm3. In addition, for the oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], for example, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3and lower than 6.3 g/cm3. Note that in the case where a single crystal oxide semiconductor having the same composition does not exist, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to estimate the density. As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked-layer film including two or more kinds selected from an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example. <Carrier Density of Oxide Semiconductor> Next, the carrier density of an oxide semiconductor will be described below. Examples of a factor affecting the carrier density of an oxide semiconductor include oxygen vacancies (VO) in the oxide semiconductor or impurities in the oxide semiconductor. As the number of oxygen vacancies in the oxide semiconductor increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VOH). The density of defect states also increases with an increase in the number of impurities in the oxide semiconductor. Hence, the carrier density of an oxide semiconductor can be controlled by controlling the density of defect states in the oxide semiconductor. A transistor using the oxide semiconductor in a channel region is considered below. The carrier density of the oxide semiconductor is preferably reduced in the case where suppression of the negative shift of the threshold voltage of the transistor or reduction in the off-state current of the transistor is intended. In the case where the carrier density of the oxide semiconductor is reduced, the impurity concentration in the oxide semiconductor is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. The carrier density of a highly purified intrinsic oxide semiconductor is lower than 8×1015cm−3, preferably lower than 1×1011cm−3, and further preferably lower than 1×1010cm−3and is higher than or equal to 1×10−9cm−3. By contrast, the carrier density of the oxide semiconductor is preferably increased in the case where improvement in the on-state current of the transistor or improvement in the field-effect mobility of the transistor is intended. In the case where the carrier density of the oxide semiconductor is increased, the impurity concentration or the density of defect states in the oxide semiconductor is slightly increased. Alternatively, the bandgap of the oxide semiconductor is narrowed. For example, an oxide semiconductor that has a slightly high impurity concentration or a slightly high density of defect states in the range where an on/off ratio is obtained in the Id-Vg characteristics of the transistor can be regarded as substantially intrinsic. Furthermore, an oxide semiconductor that has a high electron affinity and thus has a narrow bandgap so as to increase the density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with higher electron affinity is used, the transistor has lower threshold voltage. The oxide semiconductor with an increased carrier density has somewhat n-type conductivity; thus, it can be referred to as a “Slightly-n” oxide semiconductor. The carrier density of a substantially intrinsic oxide semiconductor is preferably higher than or equal to 1×105cm−3and lower than 1×1018cm−3, further preferably higher than or equal to 1×107cm−3and lower than or equal to 1×1017cm−3, still further preferably higher than or equal to 1×109cm−3and lower than or equal to 5×1016cm−3, yet further preferably higher than or equal to 1×1010cm−3and lower than or equal to 1×1016cm3, and yet still preferably higher than or equal to 1×1011cm3and lower than or equal to 1×1015cm−3. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 3 In this embodiment, an example of a display device that includes any of the transistors described in the above embodiments will be described below with reference toFIG.22toFIG.32. FIG.22is a top view showing an example of a display device. A display device700shown inFIG.22includes a pixel portion702provided over a first substrate701, a source driver circuit portion704and a gate driver circuit portion706that are provided over the first substrate701, a sealant712provided to surround the pixel portion702, the source driver circuit portion704, and the gate driver circuit portion706, and a second substrate705provided to face the first substrate701. Note that the first substrate701and the second substrate705are sealed with the sealant712. That is, the pixel portion702, the source driver circuit portion704, and the gate driver circuit portion706are sealed with the first substrate701, the sealant712, and the second substrate705. Although not illustrated inFIG.22, a display element is provided between the first substrate701and the second substrate705. In the display device700, an FPC terminal portion708(FPC: flexible printed circuit) electrically connected to each of the pixel portion702, the source driver circuit portion704, and the gate driver circuit portion706is provided in a region different from the region which is surrounded by the sealant712over the first substrate701. Furthermore, an FPC716is connected to the FPC terminal portion708, and a variety of signals and the like are supplied to the pixel portion702, the source driver circuit portion704, and the gate driver circuit portion706through the FPC716. Furthermore, a signal line710is connected to each of the pixel portion702, the source driver circuit portion704, the gate driver circuit portion706, and the FPC terminal portion708. Through the signal line710, a variety of signals and the like are supplied from the FPC716to the pixel portion702, the source driver circuit portion704, the gate driver circuit portion706, and the FPC terminal portion708. A plurality of gate driver circuit portions706may be provided in the display device700. An example of the display device700in which the source driver circuit portion704and the gate driver circuit portion706are formed over the first substrate701where the pixel portion702is also formed is described; however, the structure is not limited thereto. For example, only the gate driver circuit portion706may be formed over the first substrate701or only the source driver circuit portion704may be formed over the first substrate701. In this case, a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (e.g., a driver circuit board formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate701. Note that there is no particular limitation on the method for connecting the separately prepared driver circuit board, and a COG (chip on glass) method, a wire bonding method, or the like can be used. The pixel portion702, the source driver circuit portion704, and the gate driver circuit portion706included in the display device700include a plurality of transistors, and any of the transistors that are the semiconductor devices of embodiments of the present invention can be used. The display device700can include any of a variety of elements. As examples of the elements, electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting transistor element (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, an electronic ink element, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a MEMS (micro electro mechanical systems) display (e.g., a grating light valve (GLV), a digital micromirror device (DMD), a digital micro shutter (DMS) element, or an interferometric modulator display (IMOD) element), and a piezoelectric ceramic display can be given. An example of a display device including an EL element is an EL display or the like. An example of a display device including an electron emitter is a field emission display (FED), an SED-type flat panel display (SED: Surface-conduction Electron-emitter Display), or the like. An example of a display device including a liquid crystal element is a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display) or the like. An example of a display device having electronic ink or an electrophoretic element is electronic paper or the like. In the case of making a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. Furthermore, in such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. In this manner, the power consumption can be further reduced. As a display method in the display device700, a progressive method, an interlace method, or the like can be employed. Furthermore, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R stands for red, G stands for green, and B stands for blue). For example, four pixels of the R pixel, the G pixel, the B pixel, and a W (white) pixel may be included. Alternatively, a color element may be composed of two colors among R, G, and B as in PenTile layout, and the two colors to be selected may differ depending on the color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Note that the size of a display region may be different depending on respective dots of the color components. However, the disclosed invention can also be applied to a display device for monochrome display, unless being limited to a display device for color display. Furthermore, in order for a display device to perform full-color display using white light emission (W) for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp), a coloring layer (also referred to as a color filter) may be used. As the coloring layer, red (R), green (G), blue (B), yellow (Y), or the like may be combined as appropriate, for example. With the use of the coloring layer, higher color reproducibility can be obtained than in the case without the coloring layer. In this case, by providing a region with the coloring layer and a region without the coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without the coloring layer, a decrease in luminance due to the coloring layer can be suppressed, and approximately 20% to 30% of power consumption can be reduced in some cases when an image is displayed brightly. Note that in the case where full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements may emit light of their respective colors R, G, B, Y, and W. By using a self-luminous element, power consumption can be further reduced as compared to the case of using the coloring layer in some cases. As a coloring system, any of the following systems may be used: the above-described system (color filter system) in which part of white light emission is converted into red light, green light, and blue light through color filters; a system (three-color system) in which red light, green light, and blue light are used; and a system (color conversion system or quantum dot system) in which part of blue light emission is converted into red light or green light. In this embodiment, a structure including a liquid crystal element and an EL element as display elements is described with reference toFIG.23andFIG.24. Note thatFIG.23is a cross-sectional view taken along the dashed-dotted line Q-R inFIG.22and illustrates a structure including a liquid crystal element as a display element.FIG.24is a cross-sectional view taken along the dashed-dotted line Q-R inFIG.22and illustrates a structure including an EL element as a display element. Common portions betweenFIG.23andFIG.24are described first, and then different portions are described below. <Common Portions in Display Devices> The display device700illustrated inFIG.23andFIG.24include a lead wiring portion711, the pixel portion702, the source driver circuit portion704, and the FPC terminal portion708. The lead wiring portion711includes the signal line710. The pixel portion702includes a transistor750and a capacitor790. The source driver circuit portion704includes a transistor752. The transistor750and the transistor752each have a structure similar to that of the transistor100described above. Note that the transistor750and the transistor752may each have the structure of any of the other transistors described in the above embodiments. The transistors used in this embodiment each include an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. Such transistors can have low off-state current. Accordingly, an electrical signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption. In addition, the transistor used in this embodiment can have relatively high field-effect mobility and thus is capable of high speed operation. For example, with such a transistor that can operate at high speed used for a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor in a driver circuit portion can be formed over one substrate. That is, a semiconductor device formed using a silicon wafer or the like is not additionally needed as a driver circuit, by which the number of components of the semiconductor device can be reduced. In addition, the transistor that can operate at high speed can be used also in the pixel portion, whereby a high-quality image can be provided. The capacitor790includes a lower electrode that is formed through a step of processing the same oxide semiconductor film as the oxide semiconductor film included in the transistor750, and an upper electrode that is formed through a step of processing the same conductive film as a conductive film functioning as a source electrode and a drain electrode of the transistor750. Between the lower electrode and the upper electrode, an insulating film formed through a step of forming the same insulating film as a third insulating film and a fourth insulating film included in the transistor750is provided. That is, the capacitor790has a stacked-layer structure in which the insulating films functioning as a dielectric are positioned between the pair of electrodes. InFIG.23andFIG.24, a planarization insulating film770is provided over the transistor750, the transistor752, and the capacitor790. The planarization insulating film770can be formed using an organic material having heat resistance, such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the planarization insulating film770may be formed by stacking a plurality of insulating films formed from these materials. Alternatively, a structure without the planarization insulating film770may be employed. AlthoughFIG.23andFIG.24each illustrate an example in which the transistor750included in the pixel portion702and the transistor752included in the source driver circuit portion704have the same structure, one embodiment is not limited thereto. For example, in the pixel portion702and the source driver circuit portion704, different transistors may be used. In the case where different transistors are used in the pixel portion702and the source driver circuit portion704, any of the staggered transistors described in Embodiment 1 and an inverted staggered transistor may be used in combination. Specifically, a structure in which a staggered transistor is used in the pixel portion702and an inverted staggered transistor is used in the source driver circuit portion704, or a structure in which an inverted staggered transistor is used in the pixel portion702and a staggered transistor is used in the source driver circuit portion704may be given. Note that the term “source driver circuit portion704” can be replaced by the term “gate driver circuit portion”. Furthermore, an inverted staggered transistor may have a channel-etched structure or a channel-protective structure. In addition, an inverted staggered transistor also preferably has a structure with the s-channel structure described above. Furthermore, these transistor structures may freely be combined and used. The signal line710is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors750and752. Note that the signal line710may be formed using a conductive film that is formed through a process different from the process of forming the source electrodes and the drain electrodes of the transistors750and752; for example, an oxide semiconductor film formed through the same process as an oxide semiconductor film functioning as a gate electrode may be used. In the case where the signal line710is formed using a material including a copper element, for example, signal delay or the like due to wiring resistance is reduced, which enables display on a large screen. The FPC terminal portion708includes a connection electrode760, an anisotropic conductive film780, and the FPC716. Note that the connection electrode760is formed through the same process as the conductive films functioning as source electrodes and drain electrodes of the transistors750and752. The connection electrode760is electrically connected to a terminal included in the FPC716through the anisotropic conductive film780. As the first substrate701and the second substrate705, glass substrates can be used, for example. A flexible substrate may be used as the first substrate701and the second substrate705. Examples of the flexible substrate include a plastic substrate. A structure body778is provided between the first substrate701and the second substrate705. The structure body778is a columnar spacer obtained by selectively etching an insulating film and provided to control the distance (cell gap) between the first substrate701and the second substrate705. Note that a spherical spacer may also be used as the structure body778. Furthermore, a light-shielding film738functioning as a black matrix, a coloring film736functioning as a color filter, and an insulating film734in contact with the light-shielding film738and the coloring film736are provided on the second substrate705side. <Structure Example of Display Device Using Liquid Crystal Element> The display device700illustrated inFIG.23includes a liquid crystal element775. The liquid crystal element775includes a conductive film772, a conductive film774, and a liquid crystal layer776. The conductive film774is provided on the second substrate705side and has a function of a counter electrode. The display device700inFIG.23is capable of displaying an image in such a manner that light transmission or non-transmission is controlled by change in the alignment state of the liquid crystal layer776depending on a voltage applied to the conductive film772and the conductive film774. The conductive film772is connected to the conductive film that functions as a source electrode and a drain electrode included in the transistor750. The conductive film772is formed over the planarization insulating film770and functions as a pixel electrode, i.e., one electrode of the display element. The conductive film772has a function of a reflective electrode. The display device700inFIG.23is what is called a reflective color liquid crystal display device in which external light is utilized and light is reflected by the conductive film772to display an image through the coloring film736. A conductive film that transmits visible light or a conductive film that reflects visible light can be used for the conductive film772. As the conductive film that transmits visible light, for example, a material including one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that reflects visible light, for example, a material including aluminum or silver may be used. In this embodiment, the conductive film that reflects visible light is used as the conductive film772. In the display device700inFIG.23, projections and depressions are provided in part of the planarization insulating film770of the pixel portion702. The projections and depressions can be formed in the following manner, for example the planarization insulating film770is formed using a resin film, and projections and depressions are formed on the surface of the resin film. The conductive film772functioning as a reflective electrode is formed along the projections and depressions. Therefore, when external light is incident on the conductive film772, the light is reflected diffusely at the surface of the conductive film772, whereby visibility can be improved. Note that although the display device700inFIG.23is a reflective color liquid crystal display device, one embodiment is not limited thereto; it may be a transmissive color liquid crystal display device in which a conductive film that transmits visible light is used for the conductive film772. For a transmissive color liquid crystal display device, a structure without projections and depressions provided on the planarization insulating film770may be employed. Here, an example of a transmissive color liquid crystal display device is illustrated inFIG.25.FIG.25is a cross-sectional view taken along dashed-dotted line Q-R inFIG.22and illustrates the structure using a liquid crystal element as a display element. The display device700illustrated inFIG.25is an example of the structure employing a horizontal electric field mode (e.g., an FFS mode) as a driving mode of the liquid crystal element. In the structure illustrated inFIG.25, an insulating film773is provided over the conductive film772functioning as a pixel electrode, and the conductive film774is provided over the insulating film773. In such a case, the conductive film774has a function of a common electrode, and an electric field generated between the conductive film772and the conductive film774through the insulating film773can control the alignment state in the liquid crystal layer776. Although not illustrated inFIG.23andFIG.25, either one or each of the conductive film772or the conductive film774may be provided with an alignment film on a side in contact with the liquid crystal layer776. In addition, although not illustrated inFIG.23andFIG.25, an optical member (optical substrate) or the like, such as a polarizing member, a retardation member, or an anti-reflection member, may be provided as appropriate. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a side light, or the like may be used as a light source. In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. In the case where a horizontal electric field mode is employed, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material is mixed to account for several wt % or more is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition that includes liquid crystal exhibiting a blue phase and a chiral material has a short response time, and is optically isotropic, so that the alignment process is unnecessary. Since an alignment film does not need to be provided and rubbing treatment is thus not necessary, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. Moreover, the liquid crystal material which exhibits a blue phase has a small viewing angle dependence. In the case where a liquid crystal element is used as the display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, or the like can be used. Furthermore, a normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode may also be used. There are some examples of a vertical alignment mode; for example, an MVA (multi-domain vertical alignment) mode, a PVA (patterned vertical alignment) mode, an ASV mode, or the like can be employed. <Display Device Using Light-Emitting Element> The display device700illustrated inFIG.24includes a light-emitting element782. The light-emitting element782includes a conductive film784, an EL layer786, and a conductive film788. The display device700illustrated inFIG.24is capable of displaying an image by light emission from the EL layer786of the light-emitting element782. Note that the EL layer786contains an organic compound or an inorganic compound such as a quantum dot. Examples of materials that can be used for an organic compound include a fluorescent material or a phosphorescent material. Examples of materials that can be used for a quantum dot include a colloidal quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material. Furthermore, a material containing elements belonging to Groups 12 and 16, elements belonging to Groups 13 and 15, or elements belonging to Groups 14 and 16, may be used. Alternatively, a quantum dot material containing an element such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), or aluminum (Al) may be used. The conductive film784is connected to the conductive film that functions as a source electrode and a drain electrode included in the transistor750. The conductive film784is formed over the planarization insulating film770and functions as a pixel electrode, i.e., one electrode of the display element. As the conductive film784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material including one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film that reflects visible light, for example, a material including aluminum or silver may be used. In the display device700inFIG.24, an insulating film730is provided over the planarization insulating film770and the conductive film784. The insulating film730covers part of the conductive film784. Note that the light-emitting element782has a top emission structure. Therefore, the conductive film788has a light-transmitting property and transmits light emitted from the EL layer786. Although the top-emission structure is described as an example in this embodiment, one embodiment is not limited thereto. A bottom-emission structure in which light is emitted to the conductive film784side, or a dual-emission structure in which light is emitted to both the conductive film784side and the conductive film788side may be employed, for example. The coloring film736is provided in a position overlapping with the light-emitting element782, and the light-shielding film738is provided in a position overlapping with the insulating film730, in the lead wiring portion711, and in the source driver circuit portion704. The coloring film736and the light-shielding film738are covered with the insulating film734. A space between the light-emitting element782and the insulating film734is filled with a sealing film732. Although a structure with the coloring film736is described as the structure of the display device700inFIG.24, the structure is not limited thereto. In the case where the EL layer786is formed by a separate coloring method, for example, a structure without the coloring film736provided may be employed. <Structure Example of Display Device Provided with Input/Output Device> An input/output device may be provided in the display device700illustrated inFIG.24andFIG.25. As an example of the input/output device, a touch panel or the like can be given. FIG.26andFIG.27illustrate structures where a touch panel791is provided in the display device700inFIG.24andFIG.25. FIG.26is a cross-sectional view of the structure in which the touch panel791is provided in the display device700illustrated inFIG.24, andFIG.27is a cross-sectional view of the structure in which the touch panel791is provided in the display device700illustrated inFIG.25. First, the touch panel791illustrated inFIG.26andFIG.27is described below. The touch panel791illustrated inFIG.26andFIG.27is what is called an in-cell touch panel provided between the substrate705and the coloring film736. The touch panel791is formed on the substrate705side before the light-shielding film738and the coloring film736are formed. The touch panel791includes the light-shielding film738, an insulating film792, an electrode793, an electrode794, an insulating film795, an electrode796, and an insulating film797. A change in the mutual capacitance between the electrode793and the electrode794can be sensed when an object such as a finger or a stylus approaches, for example. A portion in which the electrode793intersects with the electrode794is illustrated in the upper portion of the transistor750illustrated inFIG.26andFIG.27. Through openings in the insulating film795, the electrode796is electrically connected to the two electrodes793between which the electrode794is positioned. Note that a structure in which a region where the electrode796is provided is provided in the pixel portion702is illustrated inFIG.26andFIG.27as an example; however, one embodiment is not limited thereto, and the region where the electrode796is provided may be provided in the source driver circuit portion704. The electrodes793and794are provided in a region overlapping with the light-shielding film738. As illustrated inFIG.26, it is preferable that the electrode793do not overlap with the light-emitting element782. As illustrated inFIG.27, it is preferable that the electrode793do not overlap with the liquid crystal element775. In other words, the electrode793has an opening in a region overlapping with the light-emitting element782and the liquid crystal element775. That is, the electrode793has a mesh shape. With this structure, the electrode793does not block light emitted from the light-emitting element782or light transmitted through the liquid crystal element775. Thus, since reduction in luminance, which is caused by provision of the touch panel791, is very small, a display device with high visibility and reduced power consumption can be achieved. Note that the electrode794can have a similar structure. In addition, since the electrodes793and794do not overlap with the light-emitting element782, a metal material with low visible light transmittance can be used for the electrodes793and794. Furthermore, since the electrodes793and794do not overlap with the liquid crystal element775, a metal material with low visible light transmittance can be used for the electrodes793and794. Accordingly, the resistance of the electrodes793and794can be reduced as compared with an electrode using an oxide material with high visible light transmittance, so that the sensitivity of the touch panel can be increased. For example, conductive nanowires may be used for the electrodes793,794, and796. The nanowires may have a mean diameter of greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 25 nm. As the nanowire, a carbon nanotube or a metal nanowire such as an Ag nanowire, a Cu nanowire, or an Al nanowire may be used. In the case where an Ag nanowire is used for any one of or all of the electrodes664,665, and667, for example, the transmittance of visible light can be greater than or equal to 89% and the sheet resistance value can be greater than or equal to 40 Ω/sq. and less than or equal to 100 Ω/sq. Although the structure of the in-cell touch panel is illustrated inFIG.26andFIG.27, one embodiment is not limited thereto. For example, what is called an on-cell touch panel, which is formed over the display device700, or what is called an out-cell touch panel, which is attached to the display device700, may be employed. In this manner, the display device of one embodiment of the present invention can be combined with various types of touch panels and used. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 4 In this embodiment, a display device including a semiconductor device of one embodiment of the present invention is described with reference toFIG.28. <Circuit Configuration of Display Device> A display device illustrated inFIG.28(A)includes a region including pixels of display elements (hereinafter referred to as a pixel portion502), a circuit portion that is provided outside the pixel portion502and includes a circuit for driving the pixels (hereinafter, the circuit portion is referred to as a driver circuit portion504), circuits having a function of protecting elements (hereinafter, the circuits are referred to as protection circuits506), and a terminal portion507. Note that the protection circuits506are not necessarily provided. Part or the whole of the driver circuit portion504is preferably formed over a substrate over which the pixel portion502is formed. Thus, the number of components and the number of terminals can be reduced. When part or the whole of the driver circuit portion504is not formed over the substrate over which the pixel portion502is formed, the part or the whole of the driver circuit portion504can be mounted by COG or TAB (tape automated bonding). The pixel portion502includes a plurality of circuits for driving display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) (hereinafter, such circuits are referred to as pixel circuits501). The driver circuit portion504includes driver circuits such as a circuit for outputting a signal (scan signal) to select a pixel (hereinafter, the circuit is referred to as a gate driver504a) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (hereinafter, the circuit is referred to as a source driver504b). The gate driver504aincludes a shift register or the like. A signal for driving the shift register is input through the terminal portion507to the gate driver504a, and the gate driver504aoutputs a signal. For example, a start pulse signal, a clock signal, or the like is input to the gate driver504a, and the gate driver504aoutputs a pulse signal. The gate driver504ahas a function of controlling the potentials of wirings supplied with scan signals (hereinafter, such wirings are referred to as scan lines GL_1to GL_X). Note that a plurality of gate drivers504amay be provided, and the scan lines GL_1to GL_X may be controlled separately by the plurality of gate drivers504a. The gate driver504aalso has a function of supplying an initialization signal. Without being limited thereto, the gate driver504acan also supply another signal. The source driver504bincludes a shift register or the like. A signal (image signal) from which a data signal is derived, as well as a signal for driving the shift register is input to the source driver504bthrough the terminal portion507. The source driver504bhas a function of generating a data signal to be written to the pixel circuit501which is based on the image signal. In addition, the source driver504bhas a function of controlling output of a data signal in response to a pulse signal produced by input of a start pulse signal, a clock signal, or the like. Furthermore, the source driver504bhas a function of controlling the potentials of wirings supplied with data signals (hereinafter such wirings are referred to as data lines DL_1to DL_Y). The source driver504balso has a function of supplying an initialization signal. Without being limited thereto, the source driver504bcan also supply another signal. The source driver504bis formed with use of a plurality of analog switches, for example. The source driver504bcan output, as the data signals, signals obtained by time-dividing the image signal by sequentially turning on the plurality of analog switches. The source driver504bmay be formed with use of a shift register or the like. A pulse signal and a data signal are input to each of the plurality of pixel circuits501through one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Writing and holding of data of the data signal in each of the plurality of pixel circuits501are controlled by the gate driver504a. For example, to the pixel circuit501in the m-th row and the n-th column, a pulse signal is input from the gate driver504athrough the scan line GL_m (in is a natural number of less than or equal to X), and a data signal is input from the source driver504bthrough the data line DL_n (n is a natural number of less than or equal to Y) in accordance with the potential of the scan line GL_m. The protection circuit506inFIG.28(A)is connected to, for example, the scan line GL between the gate driver504aand the pixel circuit501. Alternatively, the protection circuit506is connected to the data line DL between the source driver504band the pixel circuit501. Alternatively, the protection circuit506can be connected to a wiring between the gate driver504aand the terminal portion507. Alternatively, the protection circuit506can be connected to a wiring between the source driver504band the terminal portion507. Note that the terminal portion507refers to a portion having terminals for inputting power, control signals, and image signals to the display device from external circuits. The protection circuit506is a circuit that electrically connects a wiring connected to the protection circuit to another wiring when a potential out of a certain range is applied to the wiring connected to the protection circuit. As illustrated inFIG.28(A), the protection circuits506provided for each of the pixel portion502and the driver circuit portion504can improve the resistance of the display device to overcurrent generated by ESD (Electro Static Discharge: electrostatic discharge) or the like. Note that the configuration of the protection circuits506is not limited to that, and for example, the protection circuit506may be configured to be connected to the gate driver504aor the protection circuit506may be configured to be connected to the source driver504b. Alternatively, the protection circuit506may be configured to be connected to the terminal portion507. Although inFIG.28(A)an example in which the gate driver504aand the source driver504bconstitute the driver circuit portion504is illustrated, one embodiment is not limited to this example. For example, only the gate driver504amay be formed and a separately prepared substrate where a source driver circuit is formed (e.g., a driver circuit substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted. The plurality of pixel circuits501inFIG.28(A)can each have the configuration illustrated inFIG.28(B), for example. The pixel circuit501inFIG.28(B)includes a liquid crystal element570, a transistor550, and a capacitor560. As the transistor550, the transistors described in the above embodiments, for example, can be used. The potential of one of a pair of electrodes of the liquid crystal element570is set in accordance with the specifications of the pixel circuit501as appropriate. The alignment state of the liquid crystal element570depends on written data. A common potential may be applied to one of the pair of electrodes of the liquid crystal element570included in each of the plurality of pixel circuits501. Furthermore, the potential applied to one of the pair of electrodes of the liquid crystal element570in the pixel circuit501may be different row by row. As a driving method of the display device including the liquid crystal element570, for example, a TN mode, an STN mode, a VA mode, an ASM (axially symmetric aligned micro-cell) mode, an OCB (optically compensated birefringence) mode, an FLC (ferroelectric liquid crystal) mode, an AFLC (antiferroelectric liquid crystal) mode, an MVA mode, a PVA (patterned vertical alignment) mode, an IPS mode, an FFS mode, a TBA (transverse bend alignment) mode, and the like may be used. Examples of a driving method of the display device include, in addition to the above driving methods, an ECB (electrically controlled birefringence) mode, a PDLC (polymer dispersed liquid crystal) mode, a PNLC (polymer network liquid crystal) mode, and a guest-host mode. However, not limited to the above, a variety of liquid crystal elements and the driving methods thereof can be used. In the pixel circuit501in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor550is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element570. A gate electrode of the transistor550is electrically connected to the scan line GL_m. The transistor550has a function of controlling writing of data of a data signal. One of a pair of electrodes of the capacitor560is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element570. The potential value of the potential supply line VL is set in accordance with the specifications of the pixel circuit501as appropriate. The capacitor560has a function of a storage capacitor for storing written data. In the display device including the pixel circuits501inFIG.28(B), for example, the gate driver504ainFIG.28(A)sequentially selects the pixel circuits501row by row to turn on the transistors550, and data of data signals is written. When the transistors550are turned off, the pixel circuits501in which the data has been written are brought into a holding state. This operation is sequentially performed row by row; thus, an image can be displayed. Each of the plurality of pixel circuits501inFIG.28(A)can have the configuration illustrated inFIG.28(C), for example. The pixel circuit501inFIG.28(C)includes transistors552and554, a capacitor562, and a light-emitting element572. Transistors described in the above embodiments, for example, can be used as one or both of the transistors552and554. One of a source electrode and a drain electrode of the transistor552is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). A gate electrode of the transistor552is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scan line GL_m). The transistor552has a function of controlling writing of data of a data signal. One of a pair of electrodes of the capacitor562is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor552. The capacitor562has a function of a storage capacitor for storing written data. One of a source electrode and a drain electrode of the transistor554is electrically connected to the potential supply line VL_a. Furthermore, a gate electrode of the transistor554is electrically connected to the other of the source electrode and the drain electrode of the transistor552. One of an anode and a cathode of the light-emitting element572is electrically connected to a potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor554. As the light-emitting element572, an organic electroluminescent element (also referred to as an organic EL element) can be used, for example. However, the light-emitting element572is not limited to this; an inorganic EL element formed of an inorganic material may be used. Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other. In the display device that includes the pixel circuits501inFIG.28(C), the gate driver504ainFIG.28(A)sequentially selects the pixel circuits501row by row to turn on the transistors552, and data of data signals is written. When the transistors552are turned off, the pixel circuits501in which the data has been written are brought into a holding state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor554is controlled in accordance with the potential of the written data signal, and the light-emitting element572emits light with luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image is displayed. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 5 In this embodiment, a circuit configuration example to which the transistors described in the above embodiments can be applied will be described with reference toFIG.29toFIG.32. Note that in this embodiment, the transistor that includes an oxide semiconductor described in the above embodiment will be referred to as an OS transistor in the following description. <Configuration Example of Inverter Circuit> InFIG.29(A), a circuit diagram of an inverter that can be used for a shift register, a buffer, or the like included in the driver circuit is illustrated. An inverter800outputs a signal whose logic is inverted from the logic of a signal supplied to an input terminal IN to an output terminal OUT. The inverter800includes a plurality of OS transistors. A signal SBGcan switch electrical characteristics of the OS transistors. FIG.29(B)illustrates an example of the inverter800. The inverter800includes OS transistors810and820. The inverter800can be formed using only n-channel transistors; thus, the inverter800can be formed at lower cost than an inverter formed using a CMOS (Complementary Metal Oxide Semiconductor) (i.e., a CMOS inverter). Note that the inverter800that includes the OS transistors can be provided over a CMOS that is made up of S1transistors. Since the inverter800can be provided so as to overlap with the CMOS circuit, an increase in the circuit area for adding the inverter800can be suppressed. The OS transistors810and820include a first gate functioning as a front gate, a second gate functioning as a back gate, a first terminal functioning as one of a source and a drain, and a second terminal functioning as the other of the source and the drain. The first gate of the OS transistor810is connected to its second terminal. The second gate of the OS transistor810is connected to a wiring that supplies the signal SBG. The first terminal of the OS transistor810is connected to a wiring which applies a voltage VDD. The second terminal of the OS transistor810is connected to the output terminal OUT. The first gate of the OS transistor820is connected to the input terminal IN. The second gate of the OS transistor820is connected to the input terminal IN. The first terminal of the OS transistor820is connected to the output terminal OUT. The second terminal of the OS transistor820is connected to a wiring which applies a voltage VSS. FIG.29(C)is a timing chart for illustrating the operation of the inverter800. The timing chart inFIG.29(C)illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, a signal waveform of the signal SBG, and the threshold voltage of the OS transistor810. The signal SBGis supplied to the second gate of the OS transistor810, whereby the threshold voltage of the OS transistor810can be controlled. The signal SBGincludes a voltage BBG_Afor shifting the threshold voltage in the negative direction and a voltage VBG_Bfor shifting the threshold voltage in the positive direction. The threshold voltage of the OS transistor810can be shifted in the negative direction to be a threshold voltage VTH_Awhen the voltage VBG_Ais applied to the second gate. The threshold voltage of the OS transistor810can be shifted in the positive direction to be a threshold voltage VTH_Bwhen the voltage VBG_Bis applied to the second gate. To visualize the above description,FIG.30(A)shows an Id-Vg curve, which is one of the electrical characteristics of a transistor. When the voltage of the second gate is increased, like the voltage VBG_A, the electrical characteristics of the OS transistor810can be shifted to the curve shown by a dashed line840inFIG.30(A). When the voltage of the second gate is decreased, like the voltage VBG_B, the electrical characteristics of the OS transistor810can be shifted to the curve shown by a solid line841inFIG.30(A). As shown inFIG.30(A), switching the signal SBGbetween the voltage VBG_Aand the voltage VBG_Benables the threshold voltage of the OS transistor810to be shifted in the positive direction or the negative direction. By shifting the threshold voltage in the positive direction toward the threshold voltage VTH_B, a state in which current is less likely to flow in the OS transistor810can be made.FIG.30(B)visualizes this state. As illustrated inFIG.30B, a current Is that flows in the OS transistor810can be extremely low. Thus, when a signal supplied to the input terminal IN is at a high level and the OS transistor820is on (ON), the voltage of the output terminal OUT can drop sharply. Since a state in which current is less likely to flow in the OS transistor810as illustrated inFIG.30(B)can be obtained, a signal waveform831of the output terminal in the timing chart inFIG.29(C)can be made steep. Since shoot-through current between the wiring that applies the voltage VDD and the wiring that applies the voltage VSS can be low, operation with lower power consumption can be carried out. By shifting the threshold voltage in the negative direction toward the threshold voltage VTH_A, a state in which current easily flows in the OS transistor810can be made.FIG.30(C)visualizes this state. As illustrated inFIG.30(C), a current IAflowing at this time can be higher than at least the current IB. Thus, when a signal supplied to the input terminal IN is at a low level and the OS transistor820is off (OFF), the voltage of the output terminal OUT can be increased sharply. Since a state in which current easily flows in the OS transistor810as illustrated inFIG.30(C)can be obtained, a signal waveform832of the output terminal in the timing chart inFIG.29(C)can be made steep. Note that the threshold voltage of the OS transistor810is preferably controlled by the signal SBGbefore the state of the OS transistor820is switched, i.e., before Time T1or T2. For example, as inFIG.29(C), it is preferable that the threshold voltage of the OS transistor810be switched from the threshold voltage VTH_Ato the threshold voltage VTH_Bbefore time T1at which the level of the signal supplied to the input terminal IN is switched to a high level. Moreover, as inFIG.29(C), it is preferable that the threshold voltage of the OS transistor810be switched from the threshold voltage VTH_Bto the threshold voltage VTH_Abefore time T2at which the level of the signal supplied to the input terminal IN is switched to a low level. Although the timing chart inFIG.29(C)illustrates the configuration in which the signal SBGis switched in accordance with the signal supplied to the input terminal IN, a different configuration may be employed. For example, voltage for controlling the threshold voltage may be held by the second gate of the OS transistor810in a floating state.FIG.31(A)illustrates an example of a circuit configuration that can achieve such a configuration. InFIG.31(A), an OS transistor850is included in addition to the circuit configuration inFIG.29(B). A first terminal of the OS transistor850is connected to the second gate of the OS transistor810. A second terminal of the OS transistor850is connected to a wiring which applies the voltage VBG_B(or the voltage VBG_A). A first gate of the OS transistor850is connected to a wiring which supplies a signal SF. A second gate of the OS transistor850is connected to the wiring which applies the voltage VBG_B(or the voltage VBG_A). The operation ofFIG.31(A)is described with reference to a timing chart inFIG.31(B). The voltage for controlling the threshold voltage of the OS transistor810is applied to the second gate of the OS transistor810before Time T3at which the level of the signal supplied to the input terminal IN is changed to a high level. The signal SF is set to a high level and the OS transistor850is turned on, so that the voltage VBG_Bfor controlling the threshold voltage is applied to a node NBG. The OS transistor850is turned off after the voltage of the node NBGbecomes VBG_B. Since the off-state current of the OS transistor850is extremely low, the voltage VBG_Bheld once by the node NBGcan be retained by keeping the off state of the OS transistor850. Therefore, the number of times of operation of applying the voltage VBG_Bto the second gate of the OS transistor850can be reduced and accordingly the power consumed to rewrite the voltage VBG_Bcan be reduced. AlthoughFIG.29(B)andFIG.31(A)each illustrate the configuration where the voltage is applied to the second gate of the OS transistor810by control from the outside, a different configuration may be employed. For example, a configuration in which voltage for controlling the threshold voltage is generated on the basis of the signal supplied to the input terminal IN and applied to the second gate of the OS transistor810may be employed.FIG.32(A)illustrates an example of a circuit configuration that can achieve such a configuration. InFIG.32(A), the circuit configuration inFIG.29(B)also includes a CMOS inverter860between the input terminal IN and the second gate of the OS transistor810. An input terminal of the CMOS inverter860is connected to the input terminal IN. An output terminal of the CMOS inverter860is connected to the second gate of the OS transistor810. The operation ofFIG.32(A)is described with reference to a timing chart inFIG.32(B). The timing chart inFIG.32(B)illustrates changes of a signal waveform of the input terminal IN, a signal waveform of the output terminal OUT, an output waveform IN_B of the CMOS inverter860, and a threshold voltage of the OS transistor810. The output waveform IN_B which corresponds to a signal whose logic is inverted from the logic of the signal supplied to the input terminal IN can be used as a signal that controls the threshold voltage of the OS transistor810. Thus, the threshold voltage of the OS transistor810can be controlled as described with reference toFIG.30AtoFIG.30C. For example, the signal supplied to the input terminal IN is at a high level and the OS transistor820is turned on at time T4inFIG.32(B). At this time, the output waveform IN_B is at a low level. Accordingly, a state in which current is less likely to flow in the OS transistor810can be obtained; thus, the voltage increase of the output terminal OUT can be sharply decreased. Moreover, the signal supplied to the input terminal IN is at a low level and the OS transistor820is turned off at time T5inFIG.32(B). At this time, the output waveform IN_B is at a high level. Accordingly, a state in which current easily flows in the OS transistor810can be obtained; thus, a rise in the voltage of the output terminal OUT can be made steep. As described above, in the structure of this embodiment, the voltage of the back gate in the inverter that includes the OS transistor is switched in accordance with the logic of the signal of the input terminal IN. In such a structure, the threshold voltage of the OS transistor can be controlled. The control of the threshold voltage of the OS transistor by the signal supplied to the input terminal IN can cause a steep change in the voltage of the output terminal OUT. Moreover, shoot-through current between the wirings that apply power supply voltages can be reduced. Thus, power consumption can be reduced. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 6 In this embodiment, an example of a semiconductor device in which the transistor that includes an oxide semiconductor (OS transistor) described in the above embodiments is used in a plurality of circuits will be described with reference toFIG.33toFIG.36. <Circuit Configuration Example of Semiconductor Device> FIG.33(A)is a block diagram of a semiconductor device900. The semiconductor device900includes a power supply circuit901, a circuit902, a voltage generation circuit903, a circuit904, a voltage generation circuit905, and a circuit906. The power supply circuit901is a circuit that generates a voltage VORGwhich is a reference. The voltage VORGis not necessarily one voltage and can be a plurality of voltages. The voltage VORGcan be generated on the basis of a voltage V0applied from the outside of the semiconductor device900. The semiconductor device900can generate the voltage VORGon the basis of one power supply voltage applied from the outside. Thus, the semiconductor device900can operate without application of a plurality of power supply voltages from the outside. The circuits902,904, and906are circuits that operate with different power supply voltages. The power supply voltage of the circuit902, for example, is a voltage applied by the voltage VORGand the voltage VSS(VORG>VSS). The power supply voltage of the circuit904, for example, is a voltage applied by the voltage VPOGand the voltage VSS(VPOG>VORG). The power supply voltage of the circuit906, for example, is a voltage applied by the voltage VORGand the voltage VNEG(VORG>VSS>VNEG). When the voltage VSSis equal to a ground (GND), the kinds of voltages generated in the power supply circuit901can be reduced. The voltage generation circuit903is a circuit that generates the voltage VPOG. The voltage generation circuit903can generate the voltage VPOGon the basis of the voltage VORGapplied from the power supply circuit901. Thus, the semiconductor device900including the circuit904can operate on the basis of one power supply voltage applied from the outside. The voltage generation circuit905is a circuit that generates the voltage VNEG. The voltage generation circuit905can generate the voltage VNEGon the basis of the voltage VORGapplied from the power supply circuit901. Thus, the semiconductor device900including the circuit906can operate on the basis of one power supply voltage applied from the outside. FIG.33(B)illustrates an example of the circuit904that operates with the voltage VPOGandFIG.33(C)illustrates an example of a waveform of a signal for operating the circuit904. FIG.33(B)illustrates a transistor911. A signal supplied to a gate of the transistor911is generated on the basis of, for example, the voltage VPOGand the voltage VSS. The signal is the voltage VPOGat the time when the transistor911is turned on and is the voltage VSSat the time when the transistor911is turned off. As illustrated inFIG.33(C), the voltage VPOGis higher than the voltage VORG. Therefore, the transistor911can perform more securely an operation for bringing a source (S) and a drain (D) into a conduction state. As a result, the frequency of malfunction of the circuit904can be reduced. FIG.33(D)illustrates an example of the circuit906that operates with the voltage VNEGandFIG.33(E)illustrates an example of a waveform of a signal for operating the circuit906. FIG.33(D)illustrates a transistor912having a back gate. A signal supplied to a gate of the transistor912is generated on the basis of, for example, the voltage VORGand the voltage VSS. The signal is the voltage VORGat the time when the transistor911is turned on and is the voltage VSSat the time when the transistor911is turned off. A voltage applied to the back gate of the transistor912is generated on the basis of the voltage VNEG. As illustrated inFIG.33(E), the voltage VNEGis lower than the voltage VSS(GND). Therefore, the threshold voltage of the transistor912can be controlled so as to shift in the positive direction. Thus, the transistor912can more securely be turned off and the current flowing between the source (S) and the drain (D) can be small. As a result, the frequency of malfunction of the circuit906can be reduced and the power consumption thereof can be reduced. Note that a structure in which the voltage VNEGis directly applied to the back gate of the transistor912may be employed. A structure in which a signal supplied to the gate of the transistor912is generated on the basis of the voltage VORGand the voltage VNEGand the generated signal is supplied to the back gate of the transistor912may also be employed. FIGS.34(A)and (B) illustrate a modification example ofFIGS.33(D)and (E). In a circuit diagram illustrated inFIG.34(A), a transistor922whose conduction state can be controlled by a control circuit921is provided between the voltage generation circuit905and the circuit906. The transistor922is an n-channel type OS transistor. A control signal SBGoutput from the control circuit921is a signal for controlling the conduction state of the transistor922. Transistors912A and912B included in the circuit906are OS transistors like the transistor922. A timing chart inFIG.34(B)shows the control signal SBG, and changes in a potential of the node NBG, which indicate the states of potentials of back gates of the transistors912A and912B. When the control signal SBGis at a high level, the transistor922is turned on and the node NBGbecomes the voltage VNEG. Then, when the control signal SBGis at a low level, the node NBGbecomes electrically floating. Since the transistor922is an OS transistor, its off-state current is small. Accordingly, even when the node NBGis electrically floating, the voltage VNEGwhich has been applied once can be held. FIG.35(A)illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit903. The voltage generation circuit903illustrated inFIG.35(A)is a five-stage charge pump including diodes D1to D5, capacitors C1to C5, and an inverter INV. A clock signal CLK is supplied to the capacitors C1to C5directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage applied by the voltage VORGand the voltage VSS, the voltage VPOG, which has been increased to a positive voltage quintuple the voltage VORGby the clock signal CLK, can be obtained. Note that a forward voltage of the diodes D1to D5is 0 V. Furthermore, a desired voltage VPOGcan be obtained when the number of stages of the charge pump is changed. FIG.35(B)illustrates an example of a circuit configuration applicable to the above-described voltage generation circuit905. The voltage generation circuit905illustrated inFIG.35(B)is a four-stage charge pump including the diodes D1to D5, the capacitors C1to C5, and the inverter INV. A clock signal CLK is supplied to the capacitors C1to C5directly or through the inverter INV. When a power supply voltage of the inverter INV is a voltage applied by the voltage VORGand the voltage VSS, the voltage VNEG, which has been reduced from ground, i.e., the voltage VSS, to a negative voltage quadruple the voltage VORGby the clock signal CLK, can be obtained. Note that a forward voltage of the diodes D1to D5is 0 V. Furthermore, a desired voltage VNEGcan be obtained when the number of stages of the charge pump is changed. The circuit configuration of the voltage generation circuit903is not limited to the configuration of the circuit diagram illustrated inFIG.35(A). For example, modification examples of the voltage generation circuit903are illustrated inFIG.36(A)toFIG.36(C). Note that modification examples of the voltage generation circuit903can be achieved by changing voltages applied to wirings or arrangement of elements in voltage generation circuits903A to903C illustrated inFIG.36(A)toFIG.36(C). The voltage generation circuit903A illustrated inFIG.36(A)includes transistors M1to M10, capacitors C11to C14, and an inverter INV1. The clock signal CLK is supplied to gates of the transistors M1to M10directly or through the inverter INV1. By the clock signal CLK, the voltage VPOG, which has been increased to a positive voltage quadruple the voltage VORG, can be obtained. Note that a desired voltage VPOGcan be obtained when the number of stages is changed. In the voltage generation circuit903A inFIG.36(A), off-state current can be small when the transistors M1to M10are OS transistors, and leakage of charge held in the capacitors C11to C14can be suppressed. Accordingly, efficient voltage increase from the voltage VORGto the voltage VPOGis possible. The voltage generation circuit903B illustrated inFIG.36(B)includes transistors M11to M14, capacitors C15and C16, and an inverter INV2. The clock signal CLK is supplied to gates of the transistors M11to M14directly or through the inverter INV2. By the clock signal CLK, the voltage VPOG, which has been increased to a positive voltage twice the voltage VORGcan be obtained. In the voltage generation circuit903B inFIG.36(B), off-state current can be small when the transistors M11to M14are OS transistors, and leakage of charge held in the capacitors C15and C16can be suppressed. Accordingly, efficient voltage increase from the voltage VORGto the voltage VPOGis possible. A voltage generation circuit903C illustrated inFIG.36Cincludes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17. The conduction state of the transistor M15is controlled by a control signal EN. Owing to the control signal EN, the voltage VPOGwhich is obtained by increasing the voltage VORGcan be obtained. Since the voltage generation circuit903C inFIG.36(C)increases the voltage using the inductor Ind1, the voltage can be increased with high conversion efficiency. As described above, in the structures of this embodiment, a voltage required for circuits included in a semiconductor device can be internally generated. Thus, in the semiconductor device, the number of power supply voltages applied from the outside can be reduced. The structures and the like described in this embodiment above can be used in appropriate combination with the structure described in any of the other embodiments. Embodiment 7 In this embodiment, a display module and electronic devices, each of which includes a semiconductor device of one embodiment of the present invention, will be described with reference toFIG.37toFIG.40. <Display Module> In a display module7000illustrated inFIG.37, a touch panel7004connected to an FPC7003, a display panel7006connected to an FPC7005, a backlight7007, a frame7009, a printed board7010, and a battery7011are provided between an upper cover7001and a lower cover7002. The semiconductor device of one embodiment of the present invention can be used for the display panel7006, for example. The shapes and sizes of the upper cover7001and the lower cover7002can be changed as appropriate in accordance with the sizes of the touch panel7004and the display panel7006. As the touch panel7004, a resistive type or capacitive type touch panel which is placed to overlap with the display panel7006can be used. It is also possible to provide a touch panel function to a counter substrate (sealing substrate) of the display panel7006. It is also possible to provide a photosensor in each pixel of the display panel7006to form an optical touch panel. The backlight7007includes a light source7008. Although a structure in which the light source7008is provided over the backlight7007is illustrated inFIG.37, one embodiment is not limited to the structure. For example, a structure in which the light source7008is provided at an end portion of the backlight7007and a light diffusion plate is further provided may be employed. Note that a structure without the backlight7007may be employed in the case where a self-luminous light-emitting element such as an organic EL element is used or in the case where a reflective panel or the like is employed. The frame7009has, in addition to a function of protecting the display panel7006, a function of an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board7010. The frame7009may also have a function of a radiator plate. The printed board7010includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. A power source for supplying power to the power supply circuit may be an external commercial power source or the separately provided battery7011. The battery7011can be omitted in the case where a commercial power source is used. The display module7000may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet. <Electronic Device1> Next,FIG.38(A)toFIG.38(E)each illustrate an example of electronic devices. FIG.38(A)is an external view of a camera8000in a state where a finder8100is attached. The camera8000includes a housing8001, a display portion8002, an operation button8003, a shutter button8004, and the like. Furthermore, a detachable lens8006is attached to the camera8000. Although the camera8000has a structure where the lens8006can be detached from the housing8001for replacement, the lens8006and the housing may constitute one body. Images can be taken with the camera8000at the press of the shutter button8004. In addition, the display portion8002may have a function of a touch panel so that images can be taken at the touch on the display portion8002. The housing8001of the camera8000includes a mount including an electrode, so that the finder8100, a stroboscope, or the like can be connected to the housing8001. The finder8100includes a housing8101, a display portion8102, a button8103, and the like. The housing8101includes a mount for engagement with the mount of the camera8000so that the finder8100can be connected to the camera8000. The mount includes an electrode, and an image or the like received from the camera8000through the electrode can be displayed on the display portion8102. The button8103has a function of a power supply button. With the button8103, display on the display portion8102can be switched between on and off. A display device of one embodiment of the present invention can be used in the display portion8002of the camera8000and the display portion8102of the finder8100. Although inFIG.38(A)the camera8000and the finder8100are separate electronic devices which are configured to be detachable from each other, the housing8001of the camera8000may include a finder having a display device. FIG.38(B)is an external view of a head-mounted display8200. The head-mounted display8200includes a mounting portion8201, a lens8202, a main body8203, a display portion8204, a cable8205, and the like. The mounting portion8201includes a battery8206. The cable8205supplies power from the battery8206to the main body8203. The main body8203includes a wireless receiver or the like, and can display video data such as received image data on the display portion8204. Furthermore, the movement of the eyeball and the eyelid of a user is captured by a camera in the main body8203and then coordinates of the viewpoint of the user are calculated based on the data, whereby the viewpoint of the user can be utilized as an input means. The mounting portion8201may include a plurality of electrodes at the positions in contact with the user. The main body8203may have a function of sensing current flowing through the electrodes with the movement of the user's eyeball to recognize the viewpoint of the user. In addition, the main body8203may have a function of sensing current flowing through the electrodes to monitor the user's pulse. Furthermore, the mounting portion8201may include sensors such as a temperature sensor, a pressure sensor, or an acceleration sensor, and may have a function of displaying the user's biological information on the display portion8204. In addition, the movement of the user's head or the like may be sensed so as to change an image displayed on the display portion8204in synchronization with the movement. The display device of one embodiment of the present invention can be used in the display portion8204. FIGS.38(C), (D), and (E) are external views of a head-mounted display8300. The head-mounted display8300includes a housing8301, a display portion8302, band-like fixing means8304, and a pair of lenses8305. A user can see display on the display portion8302through the lenses8305. Note that it is favorable if the display portion8302is curved. When the display portion8302is curved, a user can feel high realistic sensation. The display device of one embodiment of the present invention can be used in the display portion8302. The display device including the semiconductor device of one embodiment of the present invention can have an extremely high resolution; thus, even when an image is magnified using the lenses8305as illustrated inFIG.38(E), a more realistic image can be displayed without pixels being perceived by the user. <Electronic Device2> Next,FIG.39(A)toFIG.39(G)each illustrate an example of electronic devices that are different from those illustrated inFIG.38(A)toFIG.38(E). Electronic devices illustrated inFIG.39(A)toFIG.39(G)each include a housing9000, a display portion9001, a speaker9003, an operation key9005(including a power switch or an operation switch), a connection terminal9006, a sensor9007(a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared ray), a microphone9008, or the like. The electronic devices illustrated inFIG.39(A)toFIG.39(G)have a variety of functions. For example, they can have a function of displaying a variety of data (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of controlling a process with a variety of software (programs), a wireless communication function, a function of being connected to a variety of computer networks with a wireless communication function, a function of transmitting and receiving a variety of data with a wireless communication function, a function of reading a program or data stored in a memory medium and displaying the program or data on the display portion, and the like. Note that functions that the electronic devices illustrated inFIG.39(A)toFIG.39(G)can have are not limited thereto, and they can have a variety of functions. Furthermore, although not illustrated inFIG.39(A)toFIG.39(G), the electronic devices may each have a plurality of display portions. The electronic devices may be provided with a camera or the like, and may have a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a memory medium (an external memory medium or a memory medium incorporated in the camera), a function of displaying the taken image on the display portion, or the like. The electronic devices inFIG.39(A)toFIG.39(G)are described in detail below. FIG.39(A)is a perspective view illustrating a television device9100. The television device9100can include the display portion9001, the display portion9001having a large screen size of, for example, 50 inches or more, or 100 inches or more. FIG.39(B)is a perspective view of a portable information terminal9101. The portable information terminal9101has a function of, for example, one or more selected from a telephone set, a notebook, and an information browsing system. Specifically, it can be used as a smartphone. Note that the portable information terminal9101may include the speaker9003, the connection terminal9006, the sensor9007, or the like. Furthermore, the portable information terminal9101can display characters and image information on its plurality of surfaces. For example, three operation buttons9050(also referred to as operation icons, or simply, icons) can be displayed on one surface of the display portion9001. Furthermore, information9051indicated by dashed rectangles can be displayed on another surface of the display portion9001. Examples of the information9051include display indicating reception of an incoming email, SNS (social networking service), call, and the like; the title of an email, SNS, and the like; the sender of an email, SNS, and the like; the date; the time; remaining battery; and the reception strength of an antenna. Instead of the information9051, the operation buttons9050or the like may be displayed on the position where the information9051is displayed. FIG.39(C)is a perspective view of a portable information terminal9102. The portable information terminal9102has a function of displaying information on three or more surfaces of the display portion9001. Here, information9052, information9053, and information9054are displayed on different surfaces. For example, a user of the portable information terminal9102can see the display (here, the information9053) with the portable information terminal9102put in a breast pocket of his/her clothes. Specifically, a caller's phone number, name, or the like of an incoming call is displayed in a position that can be seen from above the portable information terminal9102. Thus, the user can see the display without taking out the portable information terminal9102from the pocket and decide whether to answer the call. FIG.39(D)is a perspective view of a watch-type portable information terminal9200. The portable information terminal9200is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and computer games. Furthermore, the display surface of the display portion9001is bent, and images can be displayed on the bent display surface. Furthermore, the portable information terminal9200can employ near field communication conformable to a communication standard. For example, mutual communication between the portable information terminal9200and a headset capable of wireless communication enables hands-free calling. Furthermore, the portable information terminal9200includes the connection terminal9006, and data can be directly exchanged with another information terminal via a connector. Power charging through the connection terminal9006is also possible. Note that the charging operation may be performed by wireless power feeding without using the connection terminal9006. FIGS.39(E), (F), and (G) are perspective views of a foldable portable information terminal9201.FIG.39(E)is a perspective view of the portable information terminal that is in the opened state,FIG.39(F)is a perspective view of the portable information terminal that is shifted from the opened state to the folded state or from the folded state to the opened state, andFIG.39(G)is a perspective view of the portable information terminal that is in the folded state. The portable information terminal9201is highly portable when folded; and when opened, its seamless large display region is highly browsable. The display portion9001of the portable information terminal9201is supported by three housings9000joined together by hinges9055. By folding two housings9000with the hinges9055therebetween, the portable information terminal9201can be reversibly changed in shape from the opened state to the folded state. For example, the portable information terminal9201can be bent with a radius of curvature of greater than or equal to 1 mm and less than or equal to 150 mm. In addition,FIGS.40(A)and (B) are perspective views of a display device including a plurality of display panels. Note thatFIG.40(A)is a perspective view of a state in which the plurality of display panels are wound, andFIG.40(B)are a perspective view of a state in which the plurality of display panels are unwound. A display device9500illustrated inFIGS.40(A)and (B) includes a plurality of display panels9501, a shaft portion9511, and a bearing portion9512. In addition, the plurality of display panels9501each include a display region9502and a light-transmitting region9503. Each of the plurality of display panels9501is flexible. Two adjacent display panels9501are provided so as to partly overlap with each other. For example, the light-transmitting regions9503of the two adjacent display panels9501can be overlapped each other. A display device having a large screen can be obtained with the use of the plurality of display panels9501. Furthermore, the display device is highly versatile because the display panels9501can be wound depending on its use. Moreover, although a state in which the display regions9502are separated from each other in the adjacent display panels9501is illustrated inFIGS.40(A)and (B), without limitation to this structure, the display regions9502of the adjacent display panels9501may overlap with each other without any space so that a continuous display region9502is obtained, for example. The electronic devices described in this embodiment each include the display portion for displaying some sort of data. However, the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not have a display portion. The structure described in this embodiment can be used in appropriate combination with the structure described in any of the other embodiments. Example 1 In this example, the measurement results of the sheet resistance and contact resistance of materials that can be used for a gate electrode of the transistor of one embodiment of the present invention will be described. A method for fabricating the samples used in this example is described below. Thin films were formed, for Sample A1 and Sample A2, using materials that can be used as a second gate electrode, and the sheet resistance of the films was measured. In addition, stacked-layer films were formed, for Sample A3 to Sample A5, using materials that can be used as a first gate electrode (also referred to as bottom gate electrode or BGE) and materials that can be used as a second gate electrode (also referred to as top gate electrode or TGE), and the contact chain resistance of the stacked-layer films was measured. Note that the contact chain resistance in this specification and the like corresponds to the resistance value of an element in which 100 contact structures (contact holes) between conductive films are serially connected in a form of a chain (contact chain). The structures of Samples A1 to A5 are listed below. TABLE 1Oxide semi-ConductiveFilmSubstrateconductor filmfilmReference numeral102112114Sample A1GlassIGZO(4, 2, 4.1)W\TiSample A2— TABLE 2FilmSub-ConductiveOxide semi-ConductiveReferencestratefilmconductor filmfilmnumeral102106112114Sample A3GlassTi\Cu—W\TiSample A4IGZO(4, 2, 4.1)Sample A5— <Fabrication of Samples A1 to A5> For Sample A1, an oxide semiconductor film corresponding to the oxide semiconductor film112was formed over a glass substrate. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a conductive film that corresponds to the conductive film114was formed over the oxide semiconductor film. As the conductive film, a tungsten film with a thickness of 50 nm and a titanium film with a thickness of 100 nm were formed in this order using a sputtering apparatus. For Sample A2, an oxide semiconductor film corresponding to the oxide semiconductor film112was formed over a glass substrate. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. For Sample A3, conductive films each corresponding to the conductive film106were formed over a glass substrate. As each of the conductive films, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were formed in this order using a sputtering apparatus. Then, an insulating film was formed over the conductive films, and an oxide semiconductor film that corresponds to the oxide semiconductor film112was formed over the insulating film. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, openings (contact holes) each corresponding to the opening143were formed in the insulating film and oxide semiconductor film. Note that 100 holes, each of which is 2.5 μm in diameter, were formed as the openings (contact holes). Then, conductive films each corresponding to the conductive film114were formed over the insulating film and oxide semiconductor film having the openings. As each of the conductive films, a tungsten film with a thickness of 50 nm and a titanium film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Sample A3 has a structure having a region where the conductive films each corresponding to the conductive film106and the conductive films each corresponding to the conductive film114are serially connected via the 100 openings (contact holes). For Sample A4, conductive films each corresponding to the conductive film106were formed over a glass substrate. As each of the conductive films, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were formed in this order using a sputtering apparatus. Then, an insulating film was formed over the conductive films, and openings (contact holes) each corresponding to the opening143were formed in the insulating film. Note that 100 holes, each of which is 2.5 μm in diameter, were formed as the openings (contact holes). Then, oxide semiconductor films each corresponding to the oxide semiconductor film112were formed over the insulating film having the openings. As the oxide semiconductor films, oxide semiconductor films with a thickness of 10 nm were formed. Note that for forming the oxide semiconductor films, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, conductive films each corresponding to the conductive film114were formed over the oxide semiconductor films. As each of the conductive films, a tungsten film with a thickness of 15 nm and a titanium film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Sample A4 has a structure having a region where the conductive films each corresponding to the conductive film106and the oxide semiconductor films each corresponding to the oxide semiconductor film112are serially connected in the 100 openings (contact holes). For Sample A5, conductive films each corresponding to the conductive film106were formed over a glass substrate. As each of the conductive films, a titanium film with a thickness of 10 nm and a copper film with a thickness of 200 nm were formed in this order using a sputtering apparatus. Then, an insulating film was formed over the conductive films, and openings (contact holes) each corresponding to the opening143were formed in the insulating film. Note that 100 holes, each of which is 2.5 μm in diameter, were formed as the openings (contact holes). Then, oxide semiconductor films each corresponding to the oxide semiconductor film112were formed over the insulating film having the openings. As the oxide semiconductor films, oxide semiconductor films with a thickness of 100 nm were formed. Note that for forming the oxide semiconductor films, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Sample A5 has a structure having a region where the conductive films each corresponding to the conductive film106and the conductive films each corresponding to the oxide semiconductor film112are serially connected in the 100 openings (contact holes). <Measurement of Sheet Resistance and Contact Chain Resistance> The sheet resistance of each of the fabricated Sample A1 and Sample A2 was measured. The measurement results are shown inFIG.41. The sheet resistances of Sample A1 and Sample A2 were 2.41 Ω/sq. and 508 Ω/sq., respectively. That is, Sample A1 has sheet resistance lower than that of Sample A2. In this manner, it was indicated that the use of a structure in which the oxide semiconductor film corresponding to the oxide semiconductor film112and the conductive film corresponding to the conductive film114are stacked as the second gate electrode can reduce the sheet resistance of the second gate electrode. In addition, the contact chain resistance in each of the fabricated Samples A3 to A5 was measured. The measurement results are shown inFIG.42. The contact chain resistances of Sample A3, Sample A4, and Sample A5 were 3.0×102Ω, 5.6×107Ω, and 1.9×108Ω, respectively. That is, Sample A3 has contact chain resistance lower than that of Sample A4 and that of Sample A5. In this manner, it was indicated that when a region where the first gate electrode and the second gate electrode are in contact with each other has a structure having a region where the conductive film corresponding to the conductive film106and the conductive film corresponding to the conductive film114are in contact with each other, the contact chain resistance between the first gate electrode and the second gate electrode can be reduced. The structure described in this example above can be used in appropriate combination with any of the other embodiments or examples. Example 2 In this example, samples that correspond to transistors of one embodiment of the present invention were fabricated, the electrical characteristics of the transistors were measured, and the cross-sectional shapes were observed. A method for fabricating the samples used in this example will be described below. In this example, Sample B1 that corresponds to the transistor100B illustrated inFIGS.3(A)and (B) was fabricated. In the description below, the same reference numerals are used for structures having functions similar to those in the transistor100B illustrated inFIGS.3(A)and (B). For comparison, as illustrated inFIGS.43(A)and (B), Sample B2 that corresponds to a transistor100G having a structure where the second gate electrode does not include the conductive film114was also fabricated. Note that, in the description ofFIGS.43(A)and (B), the same reference numerals are used for structures having functions similar to those in the transistor100B illustrated inFIGS.3(A)and (B). <Fabrication Method of Transistor> «Fabrication of Sample B1» As the substrate102over which Sample B1 was to be fabricated, a glass substrate was used. The conductive film106was formed over the substrate102. As the conductive film10, a tantalum nitride film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Next, the insulating film104was formed over the substrate102and the conductive film106. Note that in this example, as the insulating film104, the insulating film104_1, the insulating film104_2, the insulating film104_3, and the insulating film104_4were successively formed in this order using a PECVD apparatus in a vacuum. A silicon nitride film with a thickness of 50 nm was formed as the insulating film104_1. A silicon nitride film with a thickness of 300 nm was formed as the insulating film104_2. A silicon nitride film with a thickness of 50 nm was formed as the insulating film104_3. A silicon oxynitride film with a thickness of 50 nm was formed as the insulating film104_4. Next, an oxide semiconductor film was formed over the insulating film104, and the oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film108was formed. An oxide semiconductor film with a thickness of 40 nm was formed as the oxide semiconductor film108. Note that for forming the oxide semiconductor film108, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. A wet etching method was used for processing of the oxide semiconductor film108. Next, an insulating film to be the insulating film110later was formed over the insulating film104and the oxide semiconductor film108. As the insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 100 nm, and a silicon oxynitride film with a thickness of 20 nm were successively formed using a PECVD apparatus in a vacuum. Next, heat treatment was performed. The heat treatment was performed under a mixed gas atmosphere of nitrogen and oxygen, at 350° C. for one hour. Next, an oxide semiconductor film to be the oxide semiconductor film112later was formed over the insulating film. An oxide semiconductor film with a thickness of 20 nm was formed as the oxide semiconductor film. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=5:1:7 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a mask was formed over the oxide semiconductor film, and the opening143was formed, using the mask, in the oxide semiconductor film, the insulating film that is in contact with the lower side of the oxide semiconductor film, and the insulating film104. Note that a dry etching apparatus was used for processing of the opening143. Next, a conductive film to be the conductive film114later was formed over the oxide semiconductor film to be the oxide semiconductor film112later. As the conductive film, a tungsten film with a thickness of 15 nm and a titanium film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Next, the formed conductive film and oxide semiconductor film were processed into an island shape, whereby the conductive film114and the oxide semiconductor film112were formed. Furthermore, following the formation of the conductive film114and the oxide semiconductor film112, the insulating film that is in contact with the lower side of the oxide semiconductor film112was processed, whereby the insulating film110was formed. Note that a wet etching method was used for processing of the conductive film114and the oxide semiconductor film112, and a dry etching method was used for processing of the insulating film110. Next, an impurity element was added from above the insulating film104, the oxide semiconductor film108, the insulating film110, the oxide semiconductor film112, and the conductive film114. A doping apparatus was used for the impurity element addition treatment, in which argon was used as the impurity element. Next, the insulating film116was formed over the insulating film104, the oxide semiconductor film108, the insulating film110, the oxide semiconductor film112, and the conductive film114. As the insulating film116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus. Next, the insulating film118was formed over the insulating film116. As the insulating film118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus. Next, a mask was formed over the insulating film118, and the openings141aand141bwere formed, using the mask, in the insulating films116and118. Note that a dry etching apparatus was used for processing of the openings141aand141b. Next, the insulating film122was formed over the insulating film118. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film122. Note that openings were provided in regions of the insulating film122that overlap with the openings141aand141b. Next, a conductive film was formed over the insulating film122so as to fill the openings141aand141b, and the conductive film was processed into island shapes, whereby the conductive films120sand120dwere formed. As each of the conductive films120sand120d, a copper film containing manganese with a thickness of 50 nm and a copper film with a thickness of 100 nm were successively formed using a sputtering apparatus in a vacuum. Through the above steps, Sample B1 that corresponds to the transistor100B illustrated inFIGS.3(A)and (B) was fabricated. Note that in this example, the channel width W of Sample B1 that corresponds to the transistor100B was 50 μm, while the channel width L was varied between 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. «Fabrication of Sample B2» For Sample B2, in a similar manner to Sample B1, the conductive film110, the insulating film104, and the oxide semiconductor film108were formed over the substrate102. Next, an insulating film to be the insulating film110later was formed over the insulating film104and the oxide semiconductor film108. As the insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 100 nm, and a silicon oxynitride film with a thickness of 20 nm were successively formed using a PECVD apparatus in a vacuum. Next, heat treatment was performed. The heat treatment was performed under a mixed gas atmosphere of nitrogen and oxygen, at 350° C. for one hour. Then, a mask was formed over the insulating film, and the opening143was formed, using the mask, in the insulating film and the insulating film104. Note that a dry etching apparatus was used for processing of the opening143. Next, an oxide semiconductor film to be the oxide semiconductor film112later was formed over the insulating film. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=5:1:7 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Next, the formed oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film112was formed. Furthermore, following the formation of the oxide semiconductor film112, the insulating film that is in contact with the lower side of the oxide semiconductor film112was processed, whereby the insulating film110was formed. Note that a wet etching method was used for processing of the oxide semiconductor film112, and a dry etching method was used for processing of the insulating film110. Next, an impurity element was added from above the insulating film104, the oxide semiconductor film108, the insulating film110, and the oxide semiconductor film112. A doping apparatus was used for the impurity element addition treatment, in which argon was used as the impurity element. Next, the insulating film116was formed over the insulating film104, the oxide semiconductor film108, the insulating film110, and the oxide semiconductor film112. As the insulating film116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus. Next, the insulating film118was formed over the insulating film116. As the insulating film118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus. Next, a mask was formed over the insulating film118, and the openings141aand141bwere formed, using the mask, in the insulating films116and118. Note that a dry etching apparatus was used for processing of the openings141aand141b. Next, the insulating film122was formed over the insulating film118. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film122. Note that openings were provided in regions of the insulating film122that overlap with the openings141aand141b. Next, a conductive film was formed over the insulating film122so as to fill the openings141aand141b, and the conductive film was processed into island shapes, whereby the conductive films120sand120dwere formed. As each of the conductive films120sand120d, a copper film containing manganese with a thickness of 50 nm and a copper film with a thickness of 100 nm were successively formed using a sputtering apparatus in a vacuum. Through the above steps, Sample B2 that corresponds to the transistor100G illustrated inFIGS.43(A)and (B) was fabricated. Note that in this example, the channel width W of Sample B2 that corresponds to the transistor100G was 50 μm, while the channel width L was varied between 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. <Evaluation of Electrical Characteristics of Transistors> InFIG.44andFIG.45, drain current-gate voltage (Id-Vg) characteristics of Samples B1 and B2 fabricated in this example are shown, respectively. Note thatFIG.44corresponds to measurement results of Sample B1, andFIG.45corresponds to measurement results of Sample B2. Furthermore,FIG.44(A)andFIG.45(A)are characteristics of the sample whose size is 50 μm in channel width and 2.0 μm in channel length;FIG.44(B)andFIG.45(B)are characteristics of the sample whose size is 50 μm in channel width and 3.0 μm in channel length; andFIG.44(C)andFIG.45(C)are characteristics of the sample whose size is 50 μm in channel width and 6.0 μm in channel length. In addition, inFIG.44andFIG.45, the first vertical axis represents Id (A), the second vertical axis represents field-effect mobility (μFE (cm2/Vs)), and the horizontal axis represents Vg (V). Note that, as the measurement conditions of the Id-Vg characteristics of the transistor, voltages of −15 V to +20 V in increments of 0.25 V were applied as a voltage applied to the conductive film106functioning as the first gate electrode of the transistor (hereinafter, the voltage is also referred to as gate voltage (Vg)) and a voltage applied to the oxide semiconductor film112and the conductive film114functioning as the second gate electrode also referred to as voltage (Vbg)). Furthermore, a voltage applied to the conductive film120sfunctioning as a source electrode (hereinafter, the voltage is also referred to as a source voltage (Vs)) was 0 V (comm), and a voltage applied to the conductive film120dfunctioning as a drain electrode (hereinafter, the voltage is also referred to as a drain voltage (Vd)) was 1 V or 10 V. As shown inFIG.44andFIG.45, it was indicated that the electrical characteristics of Sample B1 and Sample B2 fabricated in this example were favorable regardless of the channel length (L). <Evaluation of Reliability Based on Gate BT Test> Next, the reliability of the fabricated Sample B1 and Sample B2 whose size is 50 μm in channel width and 6.0 μm in channel length was evaluated. The reliability was evaluated by a gate BT (Bias Temperature) test in which stress voltage was applied to the gate electrodes. Note that the following four test methods were employed as the gate BT test. «PBTS: Positive Bias Temperature Stress» The gate voltage (Vg) was +30 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a dark environment. In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was higher (applied more on the positive side) than the potential of the source electrode and the drain electrode. «NBTS: Negative Bias Temperature Stress» The gate voltage (Vg) was −30 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a dark environment. In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was lower (applied more on the negative side) than the potential of the source electrode and the drain electrode. «PBITS: Positive Bias Illumination Temperature Stress» The gate voltage (Vg) was +30 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a photo environment (approximately 10000 1× with a white LED). In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was higher (applied more on the positive side) than the potential of the source electrode and the drain electrode. «NBITS: Negative Bias Illumination Temperature Stress» The gate voltage (Vg) was −30 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a photo environment (approximately 10000 1× with a white LED). In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was lower (applied more on the negative side) than the potential of the source electrode and the drain electrode. Note that the gate BT test is one kind of accelerated test and can evaluate change in characteristics, caused by long-term usage, of transistors in a short time. In particular, the amount of change in threshold voltage (ΔVth) of a transistor between before and after the gate BT test is an important indicator for examining the reliability. The smaller the amount of change in threshold voltage (ΔVth) between before and after the gate BT test is, the higher the reliability is. Note that ΔVth refers to the amount of change in threshold voltage (Vth), and corresponds to the value obtained from subtracting Vth before stress from Vth after the stress. The results of the gate BT test of Sample B1 and Sample B2 are shown inFIG.46. From the results inFIG.46, it was found that a change in the NBITS test is smaller for Sample B1 than for Sample B2. This is because Sample B1 includes the conductive film114so that the channel region of the oxide semiconductor film108was prevented from being irradiated with light. Accordingly, a structure that includes the conductive film114as the second gate electrode is preferable. <Examination of Electrical Characteristics of Transistor Under Light Irradiation> Next, the electrical characteristics of the transistors of the fabricated Sample B1 and Sample B2 whose size is 6 μm in channel length and 50 μm in channel width were measured under light irradiation. As the electrical characteristics of the transistors, drain current (Id)-gate voltage (Vg) characteristics were measured. As the environment for measurement of the electrical characteristics under light irradiation, the stress temperature was 60° C. and the light irradiation was performed at approximately 10000 1× with the use of a white LED. The electrical characteristics of the transistors of Sample B1 and Sample B2 are shown inFIG.47andFIG.48.FIG.47andFIG.48show the results of applying gate voltages (Vg and Vbg) from −15 V to +15 V in increments of 0.25 V with the source electrode (Vs) being 0 V (comm) and the drain voltage (Vd) being 1 V and 10 V. Furthermore, in each ofFIG.47andFIG.48, the vertical axis represents the drain current (Id), and the horizontal axis represents the gate voltage (Vg). Furthermore,FIG.47is the measurement results for Sample B1 andFIG.48is the measurement results for Sample B2. In addition,FIG.47(A)andFIG.48(A)show the electrical characteristics of the transistors under light irradiation, andFIG.47(B)andFIG.48(B)show the electrical characteristics of the transistors without light irradiation. According to the results of electrical characteristics shown inFIG.47andFIG.48, the result in which the electrical characteristics of the transistor of Sample B2 under light irradiation were electrical characteristics with the threshold voltage being negative (also referred to as normally-on characteristics) was obtained. By contrast, the result in which the electrical characteristics of the transistor of Sample B1 were electrical characteristics with the threshold voltage being positive (also referred to as normally-off characteristics) even under light irradiation was obtained. That is, a structure that includes the conductive film114as the second gate electrode is preferable. As described above, it can be said that the transistor of one embodiment of the present invention is a transistor with small change in electrical characteristics even under light irradiation and less power consumption. <Cross-Sectional Observation of Transistor> Next, the cross section of the fabricated transistor whose size is 50 μm in channel width and 2.0 μm in channel length was observed. The results of the cross-sectional observation of the transistor are shown inFIGS.49(A)and (B). Note that a transmission electron microscope (TEM: Transmission Electron Microscope) was used for the cross-sectional observation. FIG.49(A)is the cross section of Sample B1 andFIG.49(B)is the cross section of Sample B2, each of which corresponds to the cross section in the direction of dashed-dotted line X1-X2shown inFIG.2(A). Note that common reference numerals are put for the elements corresponding toFIG.3(A)orFIG.43(A). As shown inFIGS.49(A)and (B), Samples B1 and B2 fabricated in this example had favorable cross-sectional shapes. Furthermore, the second gate electrode width (TGE width) of Sample B1 was 1.70 μm. Furthermore, the second gate electrode width (TGE width) of Sample B2 was 1.75 μm. The structure described in this example above can be used in appropriate combination with the structures described in any of the other embodiments. Example 3 In this example, the results of evaluating the amount of hydrogen and oxygen released from a conductive film that can be used for the second gate electrode of the transistor of one embodiment of the present invention will be described. As a method for evaluating the amount of hydrogen and oxygen released from the conductive film that can be used for the second gate electrode, a thermal desorption spectrometry (TDS) was used. In the TDS analysis of the conductive film, the amount of hydrogen molecules released from the conductive film and the amount of oxygen molecules released from an insulating film under the conductive film were measured and evaluated. First, in order to evaluate the amount of hydrogen released from the conductive film, the following Sample C1 to Sample C4 were fabricated. <Fabrication of Samples C1 to C4> For Sample C1, a tungsten film with a thickness of 30 nm was formed over a glass substrate using a sputtering apparatus. For Sample C2, a titanium film with a thickness of 30 nm was formed over a glass substrate using a sputtering apparatus. For Sample C3, a tantalum nitride film with a thickness of 30 nm was formed over a glass substrate using a sputtering apparatus. For Sample C4, a titanium nitride film with a thickness of 30 nm was formed over a glass substrate using a sputtering apparatus. <Evaluation 1 of Released Amount of Hydrogen by TDS Analysis> In order to evaluate the amount of hydrogen molecules released from the fabricated Sample C1 to Sample C4, TDS analysis was conducted. The results of the TDS analysis are shown inFIGS.50(A)to (D). From the results of the TDS analysis shown inFIGS.50(A)to (D), the amount of hydrogen molecules released from the various conductive films can be evaluated. As shown inFIGS.50(A), (C), and (D), release of hydrogen from the tungsten film, the tantalum nitride film, and the titanium nitride film was hardly observed. By contrast, as shown inFIG.50(B), release of many hydrogen molecules from the titanium film was found. There is a possibility that excessive release of hydrogen causes an oxide semiconductor film in a channel region to have n-type conductivity. Thus, it can be said that tungsten, tantalum nitride, and titanium nitride are preferable as the materials used for the conductive film114. Next, in order to evaluate the amount of hydrogen passing through the conductive film, the following Sample C5 to Sample C9 were fabricated. <Fabrication of Samples C5 to C9> For Sample C5, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. For Sample C6, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a tungsten film with a thickness of 30 nm was formed over the silicon nitride film using a sputtering apparatus. For Sample C7, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a titanium film with a thickness of 30 nm was formed over the silicon nitride film using a sputtering apparatus. For Sample C8, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a tantalum nitride film with a thickness of 30 nm was formed over the silicon nitride film using a sputtering apparatus. For Sample C9, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a titanium nitride film with a thickness of 30 nm was formed over the silicon nitride film using a sputtering apparatus. <Evaluation 2 of Released Amount of Hydrogen by TDS Analysis> In order to evaluate the amount of hydrogen molecules released from the fabricated Samples C5 to C9, TDS analysis was conducted. The results of the TDS analysis are shown inFIGS.51(A)to (D). From the results of the TDS analysis shown inFIG.51, the amount of hydrogen molecules released from the silicon nitride film under the varied conductive film can be evaluated. In other words, in the case where the amount of hydrogen molecules released from the silicon nitride film is small, the conductive film is found to be capable of blocking the hydrogen. As shown inFIGS.51(A)to (D), release of hydrogen molecules from Sample C5 (the silicon nitride film) was found at 350° C. or higher. By contrast, as shown inFIG.51(A), release of hydrogen molecules from Sample C6 (the tungsten film over the silicon nitride film) was not found at 350° C. to 480° C. inclusive. In other words, it was indicated that the formation of a tungsten film over a silicon nitride film can block hydrogen molecules released from the silicon nitride. In addition, as shown inFIGS.51(C)and (D), it was found that release of hydrogen molecules from Sample C8 (the tantalum nitride film over the silicon nitride film) and Sample C9 (the titanium nitride film over the silicon nitride film) is small in amount even at 350° C. or higher. In other words, it was indicated that the formation of a tantalum nitride film or a titanium nitride film over a silicon nitride film can block hydrogen molecules released from the silicon nitride. However, as shown inFIG.51(B), release of many hydrogen molecules at 250° C. or higher, in addition to hydrogen release from the titanium film, from Sample C7 (the titanium film over the silicon nitride film) was found. In other words, it was indicated that the formation of a tungsten film, a tantalum nitride film, or a titanium nitride film over a silicon nitride film can block hydrogen molecules released from the silicon nitride. Accordingly, it can be said that tungsten, tantalum nitride, and titanium nitride are preferable as materials used for the conductive film114. Next, in order to evaluate the amount of oxygen absorbed by the conductive film, the following Samples C10 and C11-1 to Sample C14-2 were fabricated. <Fabrication of Samples C10 and C11-1 to C14-2> For Sample C10, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. For Sample C11-1, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a tungsten film was formed over the silicon nitride oxide film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the tungsten film was removed using a wet etching method to expose the silicon nitride oxide film. For Sample C11-2, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, an oxide semiconductor film with a thickness of 10 nm was formed over the silicon nitride oxide film using a sputtering apparatus. For forming the oxide semiconductor film, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a tungsten film was formed over the oxide semiconductor film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the oxide semiconductor film and the tungsten film were removed using a wet etching method to expose the silicon nitride oxide film. For Sample C12-1, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a titanium film was formed over the silicon nitride oxide film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the titanium film was removed using a wet etching method to expose the silicon nitride oxide film. For Sample C12-2, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, an oxide semiconductor film with a thickness of 10 nm was formed over the silicon nitride oxide film using a sputtering apparatus. For forming the oxide semiconductor film, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a titanium film was formed over the oxide semiconductor film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the oxide semiconductor film and the titanium film were removed using a wet etching method to expose the silicon nitride oxide film. For Sample C13-1, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a tantalum nitride film was formed over the silicon nitride oxide film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the tantalum nitride film was removed using a wet etching method to expose the silicon nitride oxide film. For Sample C13-2, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, an oxide semiconductor film with a thickness of 10 nm was formed over the silicon nitride oxide film using a sputtering apparatus. For forming the oxide semiconductor film, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a tantalum nitride film was formed over the oxide semiconductor film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the oxide semiconductor film and the tantalum nitride film were removed using a wet etching method to expose the silicon nitride oxide film. For Sample C14-1, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a titanium nitride film was formed over the silicon nitride oxide film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the titanium nitride film was removed using a wet etching method to expose the silicon nitride oxide film. For Sample C14-2, a silicon nitride oxide film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, an oxide semiconductor film with a thickness of 10 nm was formed over the silicon nitride oxide film using a sputtering apparatus. For forming the oxide semiconductor film, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a titanium nitride film was formed over the oxide semiconductor film using a sputtering apparatus. Then, after heat treatment at 250° C. for one hour was performed, the oxide semiconductor film and the titanium nitride film were removed using a wet etching method to expose the silicon nitride oxide film. <Evaluation of Released Amount of Oxygen by TDS Analysis> In order to evaluate the amount of oxygen molecules released from the fabricated Sample C10 and Samples C11-1 to C14-2, TDS analysis was conducted. The results of the TDS analysis are shown inFIGS.52(A)to (E). From the results of the TDS analysis shown inFIG.52, the amount of oxygen molecules released from the silicon nitride oxide film can be evaluated. In other words, in the case where the amount of oxygen molecules released from the silicon nitride oxide film is small, the conductive film is found to have absorbed oxygen contained in the silicon nitride oxide film. As shown inFIG.52(A), release of oxygen molecules from Sample C10 (the silicon nitride oxide film) was found. In addition, as shown inFIGS.52(B)to (E), release of oxygen molecules from the silicon nitride oxide film was also found, similarly to Sample C10, from Sample C11-2, Sample C12-2, Sample C13-2, and Sample C14-2 in each of which the varied conductive film was formed after the formation of the oxide semiconductor film over the silicon nitride oxide film. By contrast, oxygen molecules from the silicon nitride oxide film was hardly found from Sample C11-1, Sample C12-1, Sample C13-1, and Sample C14-1 in each of which the varied conductive film was formed directly over the silicon nitride oxide film. In other words, it was indicated that forming an oxide semiconductor film over a silicon nitride oxide film and forming a conductive film over the oxide semiconductor film can inhibit the conductive film from absorbing oxygen contained in silicon nitride oxide. When sufficiently containing oxygen, the insulating film110can supply oxygen to the oxide semiconductor film in the channel region and reduce oxygen vacancies in the channel region. In other words, an insulating film used as the insulating film110preferably releases a large amount of oxygen. Thus, it can be said that a structure that includes an oxide semiconductor film and a conductive film is preferable as the second gate electrode formed over the insulating film110. The structure described in this example above can be used in appropriate combination with any of the other embodiments or examples. Example 4 In this example, deposition damage to an insulating film at the time of depositing a conductive film that can be used as the second gate electrode of the transistor of one embodiment of the present invention was evaluated. For evaluating deposition damage to an insulating film at the time of depositing a conductive film, electron spin resonance (Electron Spin Resonance, abbreviation: ESR) measurement was used. A method for fabricating the samples used in this example is described below. In addition, the structures of Sample D1-1 to Sample D6-2 are listed below. TABLE 3OxideOxidesemi-In-semi-Con-FilmSub-conductorsulatingconductorductiveReferencestratefilmfilmfilmfilmnumeral102108110112114Sample D1-1QuartzIGZOSiON——Sample D1-2(4, 2, 4.1)IGZO (4, 2, 4.1)—Sample D2-1—WSample D2-2IGZO (4, 2, 4.1)WSample D3-1—TiSample D3-2IGZO (4,2,4.1)TiSample D4-1—TaNSample D4-2IGZO (4, 2, 4.1)TaNSample D5-1—TNSample D5-2IGZO (4, 2, 4.1)TNSample D6-1—CuSample D6-2IGZO (4, 2, 4.1)Cu <Fabrication of Samples D1-1 to D6-2> For Sample D1-1 and Sample D1-2, an oxide semiconductor film that corresponds to the oxide semiconductor film108was formed over a quartz substrate. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 40 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, an insulating film that corresponds to the insulating film110was formed over the oxide semiconductor film. As the insulating film, a silicon oxynitride film with a thickness of 100 nm was formed. Then, an oxide semiconductor film that corresponds to the oxide semiconductor film112was formed over the insulating film. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 10 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Through the above steps, Sample D1-2 was fabricated. In addition, Sample D1-1 was obtained by removing the deposited oxide semiconductor film that corresponds to the oxide semiconductor film112by a wet etching method. Sample D2-1 and Sample D2-2 were fabricated by forming a conductive film that corresponds to the conductive film114over Sample D1-1 and Sample D1-2, respectively. As the conductive film, a tungsten film was formed using a sputtering apparatus. Sample D3-1 and Sample D3-2 were fabricated by forming a conductive film that corresponds to the conductive film114over Sample D1-1 and Sample D1-2, respectively. As the conductive film, a titanium film was formed using a sputtering apparatus. Sample D4-1 and Sample D4-2 were fabricated by forming a conductive film that corresponds to the conductive film114over Sample D1-1 and Sample D1-2, respectively. As the conductive film, a tantalum nitride film was formed using a sputtering apparatus. Sample D5-1 and Sample D5-2 were fabricated by forming a conductive film that corresponds to the conductive film114over Sample D1-1 and Sample D1-2, respectively. As the conductive film, a titanium nitride film was formed using a sputtering apparatus. Sample D6-1 and Sample D6-2 were fabricated by forming a conductive film that corresponds to the conductive film114over Sample D1-1 and Sample D1-2, respectively. As the conductive film, a copper film was formed using a sputtering apparatus. <ESR Measurement> The fabricated Samples D1-1 to D6-2 were subjected to ESR measurement. For the ESR measurement, the measurement temperature was 85 K, the high-frequency power (microwave power) of 8.92 GHz was 10 mW, and the direction of a magnetic field was parallel to the film surface of the fabricated sample. Note that the lower detection limit of the spin density of a signal attributable to NOxwas 1.0×1016spins/cm3. The smaller the number of spins is, the smaller the number of defects in the insulating film is. The measured ESR signals are shown inFIG.53. Note that, in the case where the insulating film contains a nitride oxide (NOx), a signal having characteristic three peaks that are attributable to NOxis sometimes observed. The signal having three peaks is observed with a first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, a second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and a third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966. The first to third signals are attributable to NOxand understood to be a signal with a hyperfine structure arising from the nuclear spin of N. In addition, the signal attributable to NOxhas anisotropic spin species and thus the waveform is asymmetrical. The measurement results of the spin density of the signal having three peaks attributable to NOxfor Sample D1-1 to Sample D6-2 are shown inFIG.54. Note that shown here are the spin densities each obtained by converting the number of measured spins into that per unit volume. It can be seen that Sample D4-1 and Sample D5-1, each of which contains no oxide that corresponds to the oxide semiconductor film112and contains tantalum nitride or titanium nitride as the conductive film, have a high spin density of the signal having three peaks and thus are insulating films with a large number of defects. This is probably because NOxwas generated when the conductive film was formed by reactive sputtering using nitrogen. By contrast, for Samples D1-2, D2-2, D3-2, D4-2, D5-2, and D6-2, each of which contains oxide semiconductor that corresponds to the oxide semiconductor film112, the spin densities of the signal attributable to NOxwere low, being equal to or lower than the lower measurement limit. The above indicates that the formation of the oxide semiconductor film that corresponds to the oxide semiconductor film112over the insulating film that corresponds to the insulating film110can suppress damage to the insulating film, which is generated at the time of forming the conductive film. Accordingly, it can be said that a structure that includes the oxide semiconductor film112and the conductive film114as the second gate electrode is preferable. The structure described in this example above can be used in appropriate combination with any of the other embodiments or examples. Example 5 In this example, the results of evaluating the amount of hydrogen and oxygen released from a conductive film that can be used for the second gate electrode of the transistor of one embodiment of the present invention will be described. As a method for evaluating the amount of hydrogen and oxygen released from the conductive film that can be used for the second gate electrode, a thermal desorption spectrometry (TDS) was used. In the TDS analysis of the conductive film, the amount of hydrogen molecules released from the conductive film and the amount of oxygen molecules released from an insulating film under the conductive film were measured and evaluated. First, in order to evaluate the amount of hydrogen released from the conductive film, Sample E1 was fabricated. <Fabrication of Sample E1> For Sample E1, a copper film with a thickness of 50 nm was formed over a glass substrate using a sputtering apparatus. <Evaluation 3 of Released Amount of Hydrogen by TDS Analysis> In order to evaluate the amount of hydrogen molecules released from the fabricated Sample E1, TDS analysis was conducted. The result of the TDS analysis is shown inFIG.55. According to the results of the TDS analysis shown inFIG.55, release of hydrogen from the copper film was hardly observed. There is a possibility that excessive release of hydrogen causes an oxide semiconductor film in a channel region to have n-type conductivity. Thus, it can be said that copper is preferable as the material used as the conductive film114. Next, in order to evaluate the amount of hydrogen passing through the conductive film, the following Sample E2 to Sample E6 were fabricated. <Fabrication of Samples E2 to E6> For Sample E2, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. For Sample E3, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a copper film with a thickness of 100 nm was formed over the silicon nitride film using a sputtering apparatus. For Sample E4, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a copper film with a thickness of 100 nm was formed over the silicon nitride film using a sputtering apparatus. Then, a titanium film with a thickness of 50 nm was formed over the copper film using a sputtering apparatus. For Sample E5, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a copper film with a thickness of 100 nm was formed over the silicon nitride film using a sputtering apparatus. Then, a tungsten film with a thickness of 50 nm was formed over the copper film using a sputtering apparatus. For Sample E6, a silicon nitride film with a thickness of 100 nm was formed over a glass substrate using a PECVD apparatus. Then, a copper film with a thickness of 100 nm was formed over the silicon nitride film using a sputtering apparatus. Then, a titanium nitride film with a thickness of 50 nm was formed over the copper film using a sputtering apparatus. <Evaluation 4 of Released Amount of Hydrogen by TDS Analysis> In order to evaluate the amount of hydrogen molecules released from the fabricated Samples E2 to E6, TDS analysis was conducted. The results of the TDS analysis are shown inFIG.56andFIG.57. From the results of the TDS analysis shown inFIG.56andFIG.57, the amount of hydrogen molecules released from the silicon nitride film under the varied conductive film can be evaluated. In other words, in the case where the amount of hydrogen molecules released from the silicon nitride film is small, the conductive film is found to be capable of blocking the hydrogen. As shown inFIG.56, release of hydrogen molecules from Sample E2 (the silicon nitride film) was found at 250° C. or higher. By contrast, release of hydrogen molecules from Sample E3 (the copper film over the silicon nitride film) was not found up to approximately 350° C. In other words, it was indicated that the formation of a copper film over a silicon nitride film can block hydrogen molecules released from the silicon nitride. In addition, as shown inFIGS.57(B)and (C), it was found that release of hydrogen molecules from Sample E5 (the copper film and the tungsten film over the silicon nitride film) and Sample E6 (the copper film and the titanium nitride film over the silicon nitride film) is small in amount up to approximately 350° C. In other words, it was indicated that the formation of a copper film over a silicon nitride film and the formation of a tungsten film or a titanium nitride film over the copper film can block hydrogen molecules released from the silicon nitride. However, as shown inFIG.57(A), release of many hydrogen molecules at 250° C. or higher, in addition to hydrogen release from the titanium film, from Sample E4 (the copper film and the titanium film over the silicon nitride film) was found. In other words, it was indicated that the formation of a copper film, a tungsten film, and a titanium nitride film over a silicon nitride film can block hydrogen molecules released from the silicon nitride. Accordingly, it can be said that copper, tungsten, and titanium nitride are preferable as materials used for the conductive film114. The structure described in this example above can be used in appropriate combination with any of the other embodiments or examples. Example 6 In this example, samples that correspond to transistors of one embodiment of the present invention were fabricated, the electrical characteristics of the transistors were measured, and the cross-sectional shapes were observed. A method for fabricating the samples used in this example will be described below. In this example, Sample F1 and Sample F2 that correspond to the transistor100B illustrated inFIGS.3(A)and (B) were fabricated. In the description below, the same reference numerals are used for structures having functions similar to those in the transistor100B illustrated inFIGS.3(A)and (B). For comparison, Sample F3 that corresponds to the transistor100G having a structure where the second gate electrode does not include the conductive film114, as illustrated inFIGS.43(A)and (B), and Sample F4 and Sample F5 that correspond to a transistor100H having a structure where the second gate electrode does not include the oxide semiconductor film112, as illustrated inFIGS.58(A)and (B), were also fabricated. Note that, in the description ofFIGS.58(A)and (B), the same reference numerals are used for structures having functions similar to those in the transistor100B illustrated inFIGS.3(A)and (B). <Fabrication Method of Transistor> «Fabrication of Sample F» As the substrate102over which Sample F1 was to be fabricated, a glass substrate was used. The conductive film106was formed over the substrate102. As the conductive film110, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Next, the insulating film104was formed over the substrate102and the conductive film106. Note that in this example, as the insulating film104, the insulating film104_1, the insulating film104_2, the insulating film104_3, and the insulating film104_4were successively formed in this order using a PECVD apparatus in a vacuum. A silicon nitride film with a thickness of 50 nm was formed as the insulating film104_1. A silicon nitride film with a thickness of 300 nm was formed as the insulating film104_2. A silicon nitride film with a thickness of 50 nm was formed as the insulating film104_3. A silicon oxynitride film with a thickness of 50 nm was formed as the insulating film104_4. Next, an oxide semiconductor film was formed over the insulating film104, and the oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film108was formed. An oxide semiconductor film with a thickness of 40 nm was formed as the oxide semiconductor film108. Note that for forming the oxide semiconductor film108, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. A wet etching method was used for processing of the oxide semiconductor film108. Next, an insulating film to be the insulating film110later was formed over the insulating film104and the oxide semiconductor film108. As the insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 20 nm were successively formed using a PECVD apparatus in a vacuum. Next, heat treatment was performed. The heat treatment was performed under a mixed gas atmosphere of nitrogen and oxygen, at 350° C. for one hour. Next, an oxide semiconductor film to be the oxide semiconductor film112later was formed over the insulating film. An oxide semiconductor film with a thickness of 10 nm was formed as the oxide semiconductor film. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Then, a mask was formed over the oxide semiconductor film, and the opening143was formed, using the mask, in the oxide semiconductor film, the insulating film that is in contact with the lower side of the oxide semiconductor film, and the insulating film104. Note that a dry etching apparatus was used for processing of the opening143. Next, a conductive film to be the conductive film114later was formed over the oxide semiconductor film to be the oxide semiconductor film112later. As the conductive film, a titanium nitride film with a thickness of 50 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Next, the formed conductive film and oxide semiconductor film were processed into an island shape, whereby the conductive film114and the oxide semiconductor film112were formed. Furthermore, following the formation of the conductive film114and the oxide semiconductor film112, the insulating film that is in contact with the lower side of the oxide semiconductor film112was processed, whereby the insulating film110was formed. Note that a wet etching method was used for processing of the conductive film114and the oxide semiconductor film112, and a dry etching method was used for processing of the insulating film110. Next, an impurity element was added from above the insulating film104, the oxide semiconductor film108, the insulating film110, the oxide semiconductor film112, and the conductive film114. A doping apparatus was used for the impurity element addition treatment, in which argon and nitrogen were used as the impurity elements. Next, the insulating film116was formed over the insulating film104, the oxide semiconductor film108, the insulating film110, the oxide semiconductor film112, and the conductive film114. As the insulating film116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus. Next, the insulating film118was formed over the insulating film116. As the insulating film118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus. Next, a mask was formed over the insulating film118, and the openings141aand141bwere formed, using the mask, in the insulating films116and118. Note that a dry etching apparatus was used for processing of the openings141aand141b. Next, the insulating film122was formed over the insulating film118. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film122. Note that openings were provided in regions of the insulating film122that overlap with the openings141aand141b. Next, a conductive film was formed over the insulating film122so as to fill the openings141aand141b, and the conductive film was processed into island shapes, whereby the conductive films120sand120dwere formed. As each of the conductive films120sand120d, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were successively formed using a sputtering apparatus in a vacuum. Through the above steps, Sample F1 that corresponds to the transistor100B illustrated inFIGS.3(A)and (B) was fabricated. Note that in this example, the channel width W of Sample F1 that corresponds to the transistor100B was 50 μm, while the channel width L was varied between 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. «Fabrication of Sample F2» Sample F2 is different from Sample F1 only in the material for forming the conductive film114, and is similar to Sample F1 in the other steps. As a conductive film to be the conductive film114of Sample F2, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Note that in this example, the channel width W of Sample F2 that corresponds to the transistor100B was 50 μm, while the channel width L was varied between 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. «Fabrication of Sample F3» For Sample F3, in a similar manner to Sample F1, the conductive film110, the insulating film104, and the oxide semiconductor film108were formed over the substrate102. Next, an insulating film to be the insulating film110later was formed over the insulating film104and the oxide semiconductor film108. As the insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 20 nm were successively formed using a PECVD apparatus in a vacuum. Next, heat treatment was performed. The heat treatment was performed under a mixed gas atmosphere of nitrogen and oxygen, at 350° C. for one hour. Then, a mask was formed over the insulating film, and the opening143was formed, using the mask, in the insulating film and the insulating film104. Note that a dry etching apparatus was used for processing of the opening143. Next, an oxide semiconductor film to be the oxide semiconductor film112later was formed over the insulating film. As the oxide semiconductor film, an oxide semiconductor film with a thickness of 100 nm was formed. Note that for forming the oxide semiconductor film, a sputtering apparatus was used, a metal oxide of In:Ga:Zn=4:2:4.1 [atomic ratio] was a sputtering target, and an AC power supply was used as the power supply to be applied to the sputtering target. Next, the formed oxide semiconductor film was processed into an island shape, whereby the oxide semiconductor film112was formed. Furthermore, following the formation of the oxide semiconductor film112, the insulating film that is in contact with the lower side of the oxide semiconductor film112was processed, whereby the insulating film110was formed. Note that a wet etching method was used for processing of the oxide semiconductor film112, and a dry etching method was used for processing of the insulating film110. Next, an impurity element was added from above the insulating film104, the oxide semiconductor film108, the insulating film110, and the oxide semiconductor film112. A doping apparatus was used for the impurity element addition treatment, in which argon and nitrogen were used as the impurity elements. Next, the insulating film116was formed over the insulating film104, the oxide semiconductor film108, the insulating film110, and the oxide semiconductor film112. As the insulating film116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus. Next, the insulating film118was formed over the insulating film116. As the insulating film118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus. Next, a mask was formed over the insulating film118, and the openings141aand141bwere formed, using the mask, in the insulating films116and118. Note that a dry etching apparatus was used for processing of the openings141aand141b. Next, the insulating film122was formed over the insulating film118. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film122. Note that openings were provided in regions of the insulating film122that overlap with the openings141aand141b. Next, a conductive film was formed over the insulating film122so as to fill the openings141aand141b, and the conductive film was processed into island shapes, whereby the conductive films120sand120dwere formed. As the conductive films120sand120d, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were successively formed using a sputtering apparatus in a vacuum. Through the above steps, Sample F3 that corresponds to the transistor100G illustrated inFIGS.43(A)and (B) was fabricated. Note that in this example, the channel width W of Sample F3 that corresponds to the transistor100G was 50 μm, while the channel width L was varied between 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. «Fabrication of Sample F4» For Sample F4, in a similar manner to Sample F1, the conductive film110, the insulating film104, and the oxide semiconductor film108were formed over the substrate102. Next, an insulating film to be the insulating film110later was formed over the insulating film104and the oxide semiconductor film108. As the insulating film, a silicon oxynitride film with a thickness of 30 nm, a silicon oxynitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 20 nm were successively formed using a PECVD apparatus in a vacuum. Next, heat treatment was performed. The heat treatment was performed under a mixed gas atmosphere of nitrogen and oxygen, at 350° C. for one hour. Then, a mask was formed over the insulating film, and the opening143was formed, using the mask, in the insulating film and the insulating film104. Note that a dry etching apparatus was used for processing of the opening143. Next, a conductive film to be the conductive film114later was formed over the insulating film. As the conductive film, a titanium nitride film with a thickness of 50 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Next, the formed conductive film was processed into an island shape, whereby the conductive film114was formed. Furthermore, following the formation of the conductive film114, the insulating film that is in contact with the lower side of the conductive film114was processed, whereby the insulating film110was formed. Note that a wet etching method was used for processing of the conductive film114, and a dry etching method was used for processing of the insulating film110. Next, an impurity element was added from above the insulating film104, the oxide semiconductor film108, the insulating film110, and the conductive film114. A doping apparatus was used for the impurity element addition treatment, in which argon and nitrogen were used as the impurity elements. Next, the insulating film116was formed over the insulating film104, the oxide semiconductor film108, the insulating film110, and the conductive film114. As the insulating film116, a silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus. Next, the insulating film118was formed over the insulating film116. As the insulating film118, a silicon oxynitride film with a thickness of 300 nm was formed using a PECVD apparatus. Next, a mask was formed over the insulating film118, and the openings141aand141bwere formed, using the mask, in the insulating films116and118. Note that a dry etching apparatus was used for processing of the openings141aand141b. Next, the insulating film122was formed over the insulating film118. A 1.5-μm-thick acrylic-based photosensitive resin film was used as the insulating film122. Note that openings were provided in regions of the insulating film122that overlap with the openings141aand141b. Next, a conductive film was formed over the insulating film122so as to fill the openings141aand141b, and the conductive film was processed into island shapes, whereby the conductive films120sand120dwere formed. As the conductive films120sand120d, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were successively formed using a sputtering apparatus in a vacuum. Through the above steps, Sample F4 that corresponds to the transistor100H illustrated inFIGS.58(A)and (B) was fabricated. Note that in this example, the channel width W of Sample F4 that corresponds to the transistor100H was 50 μm, while the channel width L was varied between 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. «Fabrication of Sample F5» Sample F5 is different from Sample F3 only in the material for forming the conductive film114, and is similar to Sample F4 in the other steps. As a conductive film to be the conductive film114of Sample F5, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed in this order using a sputtering apparatus. Note that in this example, the channel width W of Sample F5 that corresponds to the transistor100H was 50 μm, while the channel width L was varied between 1.5 μm, 2.0 μm, 3.0 μm, and 6.0 μm. Note that as each type of transistor with a different channel width L, 20 transistors were formed over a substrate. <Evaluation of Electrical Characteristics of Transistors> InFIG.59toFIG.63, drain current-gate voltage (Id-Vg) characteristics of Samples F1 to F5 fabricated in this example are shown, respectively. Note thatFIG.59corresponds to measurement results of Sample F1,FIG.60corresponds to measurement results of Sample F2,FIG.61corresponds to measurement results of Sample F3,FIG.62corresponds to measurement results of Sample F4, andFIG.63corresponds to measurement results of Sample F5. Furthermore,FIG.59(A),FIG.60(A),FIG.61(A),FIG.62(A), andFIG.63(A)are characteristics of the samples whose size is 50 μm in channel width and 1.5 μm in channel length;FIG.59(B),FIG.60(B),FIG.61(B),FIG.62(B), andFIG.63(B)are characteristics of the samples whose size is 50 μm in channel width and 2.0 μm in channel length;FIG.59(C),FIG.60(C),FIG.61(C),FIG.62(C), andFIG.63(C)are characteristics of the samples whose size is 50 μm in channel width and 3.0 μm in channel length; andFIG.59(D),FIG.60(D),FIG.61(D),FIG.62(D), andFIG.63(D)are characteristics of the samples whose size is 50 μm in channel width and 6.0 μm in channel length. In addition, inFIG.59toFIG.63, the first vertical axis represents Id (A), the second vertical axis represents field-effect mobility (μFE (cm2/Vs)), and the horizontal axis represents Vg (V). Note that, as the measurement conditions of the Id-Vg characteristics of the transistor, voltages of −15 V to +20 V in increments of 0.25 V were applied as a voltage applied to the conductive film106functioning as the first gate electrode of the transistor (hereinafter, the voltage is also referred to as gate voltage (Vg)) and a voltage applied to the oxide semiconductor film112and the conductive film114functioning as the second gate electrode also referred to as voltage (Vbg)). Furthermore, a voltage applied to the conductive film120sfunctioning as a source electrode (hereinafter, the voltage is also referred to as a source voltage (Vs)) was 0 V (comm), and a voltage applied to the conductive film120dfunctioning as a drain electrode (hereinafter, the voltage is also referred to as a drain voltage (Vd)) was 1 V or 10 V. As shown inFIG.59toFIG.63, it was indicated that the electrical characteristics of Sample F1 to Sample F3 fabricated in this example were favorable regardless of the channel length (L). By contrast, the results were obtained in which Sample 4 and Sample F5 with small channel lengths of 1.5 μm and 2 μm have electrical characteristics with large variation and the threshold voltage being negative (also referred to as normally-on characteristics). Accordingly, it can be said that the structure of one embodiment of the present invention, which includes the oxide semiconductor film112as the second gate electrode, is preferable. <Evaluation of Reliability Based on Gate BT Test> Next, the reliability of the fabricated Sample F1 to Sample F3 whose size is 50 μm in channel width and 3.0 μm in channel length was evaluated. The reliability was evaluated by a gate BT (Bias Temperature) test in which stress voltage was applied to the gate electrodes. Note that the following four test methods were employed as the gate BT test. «PBTS: Positive Bias Temperature Stress» The gate voltage (Vg) was +20 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a dark environment. In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was higher (applied more on the positive side) than the potential of the source electrode and the drain electrode. «NBTS: Negative Bias Temperature Stress» The gate voltage (Vg) was −20 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a dark environment. In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was lower (applied more on the negative side) than the potential of the source electrode and the drain electrode. «PBITS: Positive Bias Illumination Temperature Stress» The gate voltage (Vg) was +20 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a photo environment (approximately 10000 1× with a white LED). In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was higher (applied more on the positive side) than the potential of the source electrode and the drain electrode. «NBITS: Negative Bias Illumination Temperature Stress» The gate voltage (Vg) was −20 V, the drain voltage (Vd) and the source voltage (Vs) were 0 V (COMMON), the stress temperature was 60° C., the stress application time was one hour, and the measurement environment was a photo environment (approximately 10000 1× with a white LED). In other words, a source electrode and a drain electrode of the transistor were set at the same potential, and a potential different from that of the source and drain electrodes was applied to a gate electrode of the transistor for a certain time. In addition, the potential applied to the gate electrode was lower (applied more on the negative side) than the potential of the source electrode and the drain electrode. Note that the gate BT test is one kind of accelerated test and can evaluate change in characteristics, caused by long-term usage, of transistors in a short time. In particular, the amount of change in threshold voltage (ΔVth) of a transistor between before and after the gate BT test is an important indicator for examining the reliability. The smaller the amount of change in threshold voltage (ΔVth) between before and after the gate BT test is, the higher the reliability is. Note that ΔVth refers to the amount of change in threshold voltage (Vth), and corresponds to the value obtained from subtracting Vth before stress from Vth after the stress. The results of the gate BT test of Sample F1 to Sample F3 are shown inFIG.64. From the results inFIG.64, it was found that a change in the varied gate BT test is small for Sample F1 to Sample F3. <Examination of Electrical Characteristics of Transistor Under Light Irradiation> Next, the electrical characteristics of the transistors of the fabricated Sample F1 to Sample F3 whose size is 3 μm in channel length and 50 μm in channel width were measured under light irradiation. As the electrical characteristics of the transistors, drain current (Id)-gate voltage (Vg) characteristics were measured. The light irradiation was performed at approximately 10000 1× with the use of a white LED. The electrical characteristics of the transistors of Sample F1 to Sample F3 are shown inFIG.65andFIG.67.FIG.65toFIG.67show the results of applying gate voltages (Vg and Vbg) from −15 V to +15 V in increments of 0.25 V with the source electrode (Vs) being 0 V (comm) and the drain voltage (Vd) being 1 V and 10 V. Furthermore, in each ofFIG.65toFIG.67, the vertical axis represents the drain current (Id), and the horizontal axis represents the gate voltage (Vg).FIG.65is the measurement results for Sample F1,FIG.66is the measurement results for Sample F2, andFIG.67is the measurement results for Sample F3. In addition,FIG.65(A),FIG.66(A), andFIG.67(A)show the electrical characteristics of the transistors under light irradiation, andFIG.65(B),FIG.66(B), andFIG.67(B)show the electrical characteristics of the transistors without light irradiation. As shown inFIG.67, the result in which the electrical characteristics of the transistor of Sample F3 under light irradiation were electrical characteristics with the threshold voltage being negative (also referred to as normally-on characteristics) was obtained. By contrast, as shown inFIG.65andFIG.66, the results in which the electrical characteristics of the transistors of Samples F1 and F2 were electrical characteristics with the threshold voltage being positive (also referred to as normally-off characteristics) even under light irradiation were obtained. That is, the structure of one embodiment of the present invention that includes the oxide semiconductor film112and the conductive film114is preferable as the second gate electrode. As described above, it can be said that the transistor of one embodiment of the present invention is a transistor with small change in electrical characteristics even under light irradiation and less power consumption. The structure described in this example above can be used in appropriate combination with the structure described in any of the other embodiments or any of the other examples. REFERENCE NUMERALS 100transistor100A transistor100B transistor100C transistor100D transistor100E transistor100F transistor100G transistor100H transistor102substrate104insulating film104_1insulating film104_2insulating film104_3insulating film104_4insulating film106conductive film107oxide semiconductor film108oxide semiconductor film108_1oxide semiconductor film108_2oxide semiconductor film108_3oxide semiconductor film108ddrain region108fregion108ichannel region108ssource region110insulating film110_0insulating film112oxide semiconductor film112_0oxide semiconductor film114conductive film114_0conductive film116insulating film118insulating film120conductive film120dconductive film120sconductive film122insulating film140mask141aopening141bopening141dopening141sopening143opening145impurity element147hollow region501pixel circuit502pixel portion504driver circuit portion504agate driver504bsource driver506protection circuit507terminal portion550transistor552transistor554transistor560capacitor562capacitor570liquid crystal element572light-emitting element664electrode665electrode667electrode700display device701substrate702pixel portion704source driver circuit portion705substrate706gate driver circuit portion708FPC terminal portion710signal line711wiring portion712sealant716FPC730insulating film732sealing film734insulating film736coloring film738light-shielding film750transistor752transistor760connection electrode770planarization insulating film772conductive film773insulating film774conductive film775liquid crystal element776liquid crystal layer778structure body780anisotropic conductive film782light-emitting element784conductive film786EL layer788conductive film790capacitor791touch panel792insulating film793electrode794electrode795insulating film796electrode797insulating film800inverter810OS transistor820OS transistor831signal waveform832signal waveform840dashed line841solid line850OS transistor860CMOS inverter900semiconductor device901power supply circuit902circuit903voltage generation circuit903A voltage generation circuit903B voltage generation circuit903C voltage generation circuit904circuit905voltage generation circuit906circuit911transistor912transistor912A transistor912B transistor921control circuit922transistor7000display module7001upper cover7002lower cover7003FPC7004touch panel7005FPC7006display panel7007backlight7008light source7009frame7010printed board7011battery8000camera8001housing8002display portion8003operation button8004shutter button8006lens8100finder8101housing8102display portion8103button8200head mounted display8201mounting portion8202lens8203main body8204display portion8205cable8206battery8300head mounted display8301housing8302display portion8304fixing means8305lens9000housing9001display portion9003speaker9005operation key9006connection terminal9007sensor9008microphone9050operation button9051information9052information9053information9054information9055hinge9100television device9101portable information terminal9102portable information terminal9200portable information terminal9201portable information terminal9500display device9501display panel9502display region9503region9511shaft portion9512bearing portion | 301,334 |
11942555 | DETAILED DESCRIPTION OF THE INVENTION Embodiments will be described in detail with reference to drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases. It is also to be noted that the same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases. Note that in this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Accordingly, without limiting to a predetermined connection relation, for example, a connection relation shown in drawings and texts, another element may be interposed between elements having the connection relation shown in the drawings and the texts. For example, in the case where X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) can be connected between X and Y. A switch is controlled to be turned on or off. That is, a switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not. Alternatively, the switch has a function of selecting and changing a current path. For example, in the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a DA converter circuit, an AD converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up circuit, and a step-down circuit) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, and a buffer circuit; a signal generation circuit; a memory circuit; or a control circuit) can be connected between X and Y. When a signal output from X is transmitted to Y, it can be said that X and Y are functionally connected even if another circuit is provided between X and Y. Note that an explicit description “X and Y are connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, the explicit description “A and B are electrically connected” is the same as the description “A and B are connected”. Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, “electrical connection” in this specification includes in its category such a case where one conductive film has functions of a plurality of components. Note that, for example, the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to one part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z2 and another part of Z2 is directly connected to Y, can be expressed by using any of the following expressions. The expressions include, for example, “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order”. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope. Note that these expressions are examples and there is no limitation on the expressions. Here, each of X, Y, Z1, and Z2 denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like). Note that in this specification and the like, a transistor can be formed using a variety of substrates. The type of a substrate is not limited to a certain type. As the substrate, a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, a base material film, or the like can be used. As examples of the glass substrate, a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, a soda lime glass substrate, and the like can be given. For the flexible substrate, a flexible synthetic resin such as plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES), or acrylic can be used, for example. For the attachment film, polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like can be used, for example. For the base material film, polyester, polyamide, polyimide, an inorganic vapor deposition film, paper, or the like can be used, for example. Specifically, when a transistor is formed using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, it is possible to form a transistor with few variations in characteristics, size, shape, or the like, with high current supply capability, and with a small size. By forming a circuit with the use of such a transistor, power consumption of the circuit can be reduced or the circuit can be highly integrated. Alternatively, a flexible substrate may be used as the substrate, and the transistor may be provided directly on the flexible substrate. Further alternatively, a separation layer may be provided between the substrate and the transistor. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate and transferred onto another substrate. In such a case, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate as well. For the above separation layer, a stack including inorganic films, which are a tungsten film and a silicon oxide film, or an organic resin film of polyimide or the like formed over a substrate can be used, for example. In other words, a transistor may be formed using one substrate, and then transferred to another substrate. Examples of a substrate to which a transistor is transferred include, in addition to the above-described substrates over which transistors can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), or the like), a leather substrate, a rubber substrate, and the like. With the use of such a substrate, a transistor with excellent properties, a transistor with low power consumption, or a device with high durability can be formed, high heat resistance can be provided, or a reduction in weight or thickness can be achieved. Embodiment 1 In this embodiment, a transistor of one embodiment of the present invention will be described with reference to drawings. In a transistor of one embodiment of the present invention, silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, an oxide semiconductor, or the like can be used for a channel formation region. It is particularly preferable to use an oxide semiconductor having a wider band gap than silicon for the channel formation region. For example, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). More preferably, the oxide semiconductor contains an oxide represented by an In-M-Zn-based oxide (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). In the description below, unless otherwise specified, transistors described as examples include an oxide semiconductor in their channel formation regions. FIGS.1A and1Bare a top view and a cross-sectional view of a transistor101of one embodiment of the present invention.FIG.1Ais the top view.FIG.1Billustrates a cross section in the direction of a dashed-dotted line A1-A2inFIG.1A. A cross section in the direction of a dashed-dotted line A3-A4inFIG.1Acorresponds toFIG.2A or2B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line A1-A2is referred to as a channel length direction, and the direction of the dashed-dotted line A3-A4is referred to as a channel width direction. Note that the channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. Note that the channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed. Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is higher than the proportion of a channel region formed in a top surface of a semiconductor in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view. In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, estimation of an effective channel width from a design value requires an assumption that the shape of a semiconductor is known. Therefore, without accurate information on the shape of a semiconductor, it is difficult to measure an effective channel width accurately. Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Further, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like. Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, a value different from the value obtained by calculation using an effective channel width is obtained in some cases. The transistor101includes an insulating layer120in contact with a substrate110, an oxide semiconductor layer130in contact with the insulating layer120, a gate insulating film160in contact with the oxide semiconductor layer130, a gate electrode layer170in contact with the gate insulating film160, an insulating layer175covering the oxide semiconductor layer130, the gate insulating film160, and the gate electrode layer170, an insulating layer180in contact with the insulating layer175, a source electrode layer140and a drain electrode layer150that are electrically connected to the oxide semiconductor layer130through openings provided in the insulating layers175and180, and an insulating layer185formed over the above-described components. An insulating layer190(planarization film) in contact with the insulating layer185or the like may be provided as necessary. Note that functions of a “source” and a “drain” of a transistor are sometimes replaced with each other when a transistor of opposite polarity is used or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be replaced with each other in this specification. In addition, the term “electrode layer” can be replaced with the term “wiring”. The gate electrode layer170includes two layers, a conductive layer171and a conductive layer172, in the drawing, but may also be a single layer or a stack of three or more layers. The source electrode layer140includes two layers, a conductive layer141and a conductive layer142, in the drawing, but may also be a single layer or a stack of three or more layers. Similarly, the drain electrode layer150, which includes a conductive layer151and a conductive layer152in the drawing, may be a single layer or a stack of three or more layers. In the case where the channel width is shortened, it is preferable that a top surface of the oxide semiconductor layer130have a curvature as illustrated inFIG.2A. The curvature of the top surface can improve coverage with a film formed over the top surface. However, in the case where the channel width is relatively long, the oxide semiconductor layer130may have a flat top region as illustrated inFIG.2B. Note that this description of the channel width can also apply to the other transistors disclosed in this specification. The transistor of one embodiment of the present invention has a self-aligned structure in which the gate electrode layer170overlaps with neither the source electrode layer140nor the drain electrode layer150. Since a transistor with a self-aligned structure has extremely small parasitic capacitance between a gate electrode layer and source and drain electrode layers, it is suitable for applications that require high-speed operation. In the transistor101, the oxide semiconductor layer130includes a region231(source region) and a region232(drain region) provided apart from each other, and a region233(channel region) that is provided between the region231and the region232and overlaps with the gate electrode layer170with the gate insulating film160placed therebetween. Here, the region231and the region232each includes a region in contact with the insulating layer175as illustrated inFIG.1B. When an insulating material containing hydrogen is used for the insulating layer175, the region231and the region232can have lower resistance. Specifically, by the steps up to and including the formation of the insulating layer175, the interaction between oxygen vacancies generated in the region231and the region232and hydrogen that diffuses into the region231and the region232from the insulating layer175changes the region231and the region232to n-type regions with low resistance. As the insulating material containing hydrogen, for example, a silicon nitride film, an aluminum nitride film, or the like can be used. Furthermore, an impurity for forming oxygen vacancies to increase conductivity may be added to the region231and the region232. As the impurity for forming oxygen vacancies in the oxide semiconductor layer, for example, one or more of the following can be used: phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon. As a method for adding the impurity, plasma treatment, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. When the above element is added as an impurity element to the oxide semiconductor layer, a bond between a metal element and oxygen in the oxide semiconductor layer is cut, whereby an oxygen vacancy is formed. Interaction between an oxygen vacancy in the oxide semiconductor layer and hydrogen that remains in the oxide semiconductor layer or is added to the oxide semiconductor layer later can increase the conductivity of the oxide semiconductor layer. As the method for adding the impurity, plasma treatment that can easily deal with large-area substrates is preferably employed. For example, a substrate on which a transistor is to be formed is placed on one (cathode) of a pair of electrodes so that bias is applied to the substrate, high-frequency power (e.g., 13.56 MHz) is applied between the pair of electrodes in a reduced-pressure argon atmosphere to generate argon plasma. At this time, part of the gate electrode layer170might be sputtered and deposited on an end portion of the gate insulating film160, which might bring about a short circuit between the regions231and232and the gate electrode layer170. Therefore, in the case of performing plasma treatment, it is preferable that a resist mask for forming patterns of the gate electrode layer170and the gate insulating film160be left over the gate electrode layer170during the plasma treatment. By leaving the resist mask over the gate electrode layer170during the plasma treatment, sputtering of the gate electrode layer170is suppressed, so that a short circuit between the regions231and232and the gate electrode layer170can be prevented and a gate leakage current can be reduced. Moreover, since part of the resist mask is sputtered, in the case of performing the treatment with argon plasma, argon and carbon can be added to the regions231and232. Since addition of carbon to the oxide semiconductor layer forms an oxygen vacancy as described above, the conductivity of the oxide semiconductor layer can be further increased. Thus, the regions231and232in the transistor101include an area having a higher concentration of the impurity that forms an oxygen vacancy than the region233. Since hydrogen enters the oxygen vacancy, the regions231and232include an area having a higher hydrogen concentration than the region233. In the transistor with this structure, the source region and the drain region can have lower resistance, whereby on-state current of the transistor can be increased. Note that elements which form oxygen vacancies in the oxide semiconductor layer are described as impurities (impurity elements). Typical examples of impurity elements are boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and rare gas elements. Typical examples of rare gas elements are helium, neon, argon, krypton, and xenon. When hydrogen is added to an oxide semiconductor in which oxygen vacancies are generated by addition of impurity elements, hydrogen enters oxygen vacant sites and forms a donor level in the vicinity of the conduction band. As a result, the conductivity of the oxide semiconductor is increased, so that the oxide semiconductor becomes a conductor. An oxide semiconductor having become a conductor can be referred to as an oxide conductor. An oxide semiconductor generally has a visible light transmitting property because of its large energy gap. An oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption due to the donor level is small, and an oxide conductor has a visible light transmitting property comparable to that of an oxide semiconductor. The temperature dependence of resistivity in a film formed using an oxide conductor (hereinafter, referred to as oxide conductor layer) is described with reference toFIG.57. Samples each including an oxide conductor layer were formed. As the oxide conductor layer, the following three layers were formed: an oxide conductor layer (OC_SiNx) formed by making an oxide semiconductor layer in contact with a silicon nitride film; an oxide conductor layer (OC_Ar dope+SiNx) obtained by adding argon to an oxide semiconductor layer with a doping apparatus and making the oxide semiconductor layer in contact with a silicon nitride film; and an oxide conductor layer (OC_Ar plasma+SiNx) obtained by exposing an oxide semiconductor layer to argon plasma with a plasma processing apparatus and making the oxide semiconductor layer in contact with a silicon nitride film. Note that the silicon nitride film contains hydrogen. A method for fabricating the sample including the oxide conductor layer (OC_SiNx) is as follows. A 400-nm-thick silicon oxynitride film was formed over a glass substrate by a plasma CVD method, and then exposed to oxygen plasma to add oxygen ions to the silicon oxynitride film, thereby forming a silicon oxynitride film from which oxygen is released by heating. Next, a 100-nm-thick In—Ga—Zn oxide film was formed over the silicon oxynitride film by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=5:5:6, and heat treatment at 450° C. in a nitrogen atmosphere and subsequently heat treatment at 450° C. in a mixed gas atmosphere of nitrogen and oxygen were performed. After that, a 100-nm-thick silicon nitride film was formed by a plasma CVD method. Then, heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen. A method for fabricating the sample including the oxide conductor layer (OC_Ar dope+SiNx) is as follows. A 400-nm-thick silicon oxynitride film was formed over a glass substrate by a plasma CVD method, and then exposed to oxygen plasma to add oxygen ions to the silicon oxynitride film, thereby forming a silicon oxynitride film from which oxygen is released by heating. Next, a 100-nm-thick In—Ga—Zn oxide film was formed over the silicon oxynitride film by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=5:5:6, and heat treatment at 450° C. in a nitrogen atmosphere and subsequently heat treatment at 450° C. in a mixed gas atmosphere of nitrogen and oxygen were performed. Then, by a doping apparatus, argon was added to the In—Ga—Zn oxide film with a dose of 5×1014/cm2at an acceleration voltage of 10 kV to form oxygen vacancies in the In—Ga—Zn oxide film. After that, a 100-nm-thick silicon nitride film was formed by a plasma CVD method. Then, heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen. A method for fabricating the sample including the oxide conductor layer (OC_Ar plasma+SiNx) is as follows. A 400-nm-thick silicon oxynitride film was formed over a glass substrate by a plasma CVD method, and then exposed to oxygen plasma, thereby forming a silicon oxynitride film from which oxygen is released by heating. Next, a 100-nm-thick In—Ga—Zn oxide film was formed over the silicon oxynitride film by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=5:5:6, and heat treatment at 450° C. in a nitrogen atmosphere and subsequently heat treatment at 450° C. in a mixed gas atmosphere of nitrogen and oxygen were performed. After that, in a plasma processing apparatus, argon plasma was generated and argon ions were accelerated to collide with the In—Ga—Zn oxide film, whereby oxygen vacancies were formed. Next, a 100-nm-thick silicon nitride film was formed by plasma CVD method. Then, heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen. FIG.57shows the measured resistivity of the samples. Here, the resistivity was measured by a four-probe van der Pauw method. InFIG.57, the horizontal axis represents measurement temperature, and the vertical axis represents resistivity. Furthermore, a square represents the measurement result of the oxide conductor layer (OC_SiNx); a triangle, the measurement result of the oxide conductor layer (OC_Ar plasma+SiNx); and a circle, the measurement result of the oxide conductor layer (OC_Ar dope+SiNx). Although not shown, the resistivity of an oxide semiconductor layer that is not in contact with a silicon nitride film was too high to measure. It is therefore found that the oxide conductor layer has lower resistivity than the oxide semiconductor layer. As is seen fromFIG.57, there is a small variation in the resistivity of the oxide conductor layer (OC_Ar dope+SiNx) and the oxide conductor layer (OC_Ar plasma+SiNx), each of which includes oxygen vacancies and hydrogen. Typically, the variation in the resistivity is less than ±20% at temperatures from 80 K to 290 K or less than ±10% at temperatures from 150 K to 250 K. In other words, the oxide conductor is a degenerate semiconductor and it is suggested that the conduction band edge agrees with or substantially agrees with the Fermi level. Thus, when the oxide conductor layer is used for a source region and a drain region of a transistor, an ohmic contact is made between the oxide conductor layer and conductive films functioning as a source electrode and a drain electrode, thereby reducing the contact resistance between the oxide conductor layer and the conductive films functioning as the source and drain electrodes. Since the temperature dependence of the resistivity of an oxide conductor is low, the amount of change in the contact resistance between the oxide conductor layer and the conductive films functioning as the source and drain electrodes is small; thus, a highly reliable transistor can be fabricated. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.3A and3B.FIG.3Ais a top view of a transistor102.FIG.3Billustrates a cross section in the direction of a dashed-dotted line B1-B2inFIG.3A. A cross section in the direction of a dashed-dotted line B3-B4inFIG.3Acorresponds to the cross section in the channel width direction of the transistor101inFIG.2A or2B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line B1-B2is referred to as a channel length direction, and the direction of the dashed-dotted line B3-B4is referred to as a channel width direction. The transistor102includes the insulating layer120in contact with the substrate110, the oxide semiconductor layer130in contact with the insulating layer120, the source electrode layer140and the drain electrode layer150that are electrically connected to the oxide semiconductor layer130, the gate insulating film160in contact with the oxide semiconductor layer130, the gate electrode layer170in contact with the gate insulating film160, the insulating layer175covering the oxide semiconductor layer130, the gate insulating film160, the source electrode layer140, the drain electrode layer150, and the gate electrode layer170, the insulating layer180in contact with the insulating layer175, and the insulating layer185formed over the above-described components. The insulating layer190(planarization film) in contact with the insulating layer185or the like may be provided as necessary. Note that the transistor102has the same structure as the transistor101except for the source electrode layer140and the drain electrode layer150that are formed directly over the oxide semiconductor layer130and the structures of the source region and the drain region. In the transistor102, the oxide semiconductor layer130includes a region331and a region332provided apart from each other, a region333that is provided between the region331and the region332and overlaps with the gate electrode layer170with the gate insulating film160placed therebetween, a region334provided between the region331and the region333, and a region335provided between the region332and the region333. In the transistor102, the region331includes a region in contact with the source electrode layer140, and the region332includes a region in contact with the drain electrode layer150. Accordingly, oxygen moves from the regions331and332to a metal material used in the source electrode layer140and the drain electrode layer150, so that oxygen vacancies are generated in the regions331and332, and the regions331and332are changed into n-type and reduced in resistance. Furthermore, the regions334and335are not in contact with the source electrode layer140or the drain electrode layer150but include a region in contact with the insulating layer175containing hydrogen. By the steps up to and including the formation of the insulating layer175, the interaction between oxygen vacancies generated in the regions334and335and hydrogen that diffuses into the regions334and335from the insulating layer175changes the regions334and335to n-type regions with low resistance. Accordingly, the regions331and334can function as a source region, and the regions332and335can function as a drain region. Note that the addition of an impurity for increasing oxygen vacancies may be subjected to the regions334and335, like the regions231and232of the transistor101. Here, in the case of adding the impurity by plasma treatment, since part of the gate electrode layer170might be sputtered and deposited on the end portion of the gate insulating film160, it is preferable that the resist mask be left over the gate electrode layer170during the plasma treatment, in a manner similar to that of the transistor101. By leaving the resist mask over the gate electrode layer170during the plasma treatment, sputtering of the gate electrode layer170is suppressed, so that a short circuit between the regions334and335and the gate electrode layer170can be prevented and a gate leakage current can be reduced. Moreover, since part of the resist mask is sputtered, in the case of performing the treatment with argon plasma, argon and carbon can be added to the regions334and335. Since addition of carbon to the oxide semiconductor layer forms an oxygen vacancy as described above, the conductivity of the oxide semiconductor layer can be further increased. Thus, the regions334and335in the transistor102include an area having a higher concentration of the impurity for forming an oxygen vacancy than the regions331,332, and333. Since hydrogen enters the oxygen vacancy, the regions334and335include an area having a higher hydrogen concentration than the region333. In the transistor with this structure, the source region and the drain region can have lower resistance, whereby on-state current of the transistor can be increased. In the case where the width of the regions334and335in the channel length direction is less than or equal to 100 nm, preferably less than or equal to 50 nm, a gate electric field contributes to preventing a significant decrease in on-state current; therefore, a structure other than the above-described structure for reducing the resistance can be employed. The transistor of one embodiment of the present invention may include the conductive layer172between the oxide semiconductor layer130and the substrate110as illustrated inFIGS.4A and4B. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be further increased and the threshold voltage can be controlled. In the cross section in the channel length direction illustrated inFIG.4A, the width of the conductive layer172may be shortened so that the conductive layer172may not overlap with the source electrode layer140, the drain electrode layer150, or the like. Moreover, the width of the conductive layer172may be further shortened so as to be shorter than the width of the gate electrode layer170. In order to increase the on-state current, for example, the gate electrode layer170and the conductive layer172may be set to have the same potential, and the transistor may be driven as a double-gate transistor. Furthermore, to control the threshold voltage, a fixed potential that is different from the potential of the gate electrode layer170may be supplied to the conductive layer172. To set the gate electrode layer170and the conductive layer172at the same potential, for example, as illustrated inFIG.4C, the gate electrode layer170and the conductive layer172may be electrically connected to each other through a contact hole. Note that although the examples illustrated inFIGS.4A to4Care variations of the transistor101, the structures of these examples can be applied to the transistor102illustrated inFIGS.3A and3B. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.5A and5B.FIG.5Ais a top view of a transistor103.FIG.5Billustrates a cross section in the direction of a dashed-dotted line C1-C2inFIG.5A. A cross section in the direction of a dashed-dotted line C3-C4inFIG.5Acorresponds toFIG.6AorFIG.6B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line C1-C2is referred to as a channel length direction, and the direction of the dashed-dotted line C3-C4is referred to as a channel width direction. The transistor103illustrated inFIGS.5A and5Bhas the same structure as the transistor101except that the oxide semiconductor layer130includes an oxide semiconductor layer130band an oxide semiconductor layer130cthat are provided in this order from the insulating layer120side. Oxide semiconductor layers having different compositions, for example, can be used as the oxide semiconductor layer130band the oxide semiconductor layer130c. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.7A and7B.FIG.7Ais a top view of a transistor104.FIG.7Billustrates a cross section in the direction of a dashed-dotted line D1-D2inFIG.7A. A cross section in the direction of a dashed-dotted line D3-D4inFIG.7Acorresponds toFIG.8AorFIG.8B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line D1-D2is referred to as a channel length direction, and the direction of the dashed-dotted line D3-D4is referred to as a channel width direction. The transistor104illustrated inFIGS.7A and7Bhas the same structure as the transistor103except that the oxide semiconductor layer130bis covered with the oxide semiconductor layer130e. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.9A and9B.FIG.9Ais a top view of a transistor105.FIG.9Billustrates a cross section in the direction of a dashed-dotted line E1-E2inFIG.9A. A cross section in the direction of a dashed-dotted line E3-E4inFIG.9Acorresponds to the cross section in the channel width direction of the transistor103inFIG.6AorFIG.6B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line E1-E2is referred to as a channel length direction, and the direction of the dashed-dotted line E3-E4is referred to as a channel width direction. The transistor105illustrated inFIGS.9A and9Bhas the same structure as the transistor102except that the oxide semiconductor layer130includes the oxide semiconductor layer130band the oxide semiconductor layer130cthat are provided in this order from the insulating layer120side. The oxide semiconductor layer130of the transistor105may have a structure in which the oxide semiconductor layer130bis covered with the oxide semiconductor layer130clike the transistor104. The transistor of one embodiment of the present invention may include the conductive layer172between the oxide semiconductor layer130and the substrate110as illustrated inFIGS.10A to10C. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be further increased and the threshold voltage can be controlled. In the cross section in the channel length direction illustrated inFIG.10A, the width of the conductive layer172may be shortened so that the conductive layer172may not overlap with the source electrode layer140, the drain electrode layer150, or the like. Moreover, the width of the conductive layer172may be further shortened so as to be shorter than the width of the gate electrode layer170. Note that although the examples illustrated inFIGS.10A to10Care variations of the transistor104, the structures of these examples can be applied to the transistors103and105. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.11A and11B.FIG.11Ais a top view of a transistor106.FIG.11Billustrates a cross section in the direction of a dashed-dotted line F1-F2inFIG.11A. A cross section in the direction of a dashed-dotted line F3-F4inFIG.11Acorresponds toFIG.12AorFIG.12B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line F1-F2is referred to as a channel length direction, and the direction of the dashed-dotted line F3-F4is referred to as a channel width direction. The transistor106illustrated inFIGS.11A and11Bhas the same structure as the transistor101except that the oxide semiconductor layer130includes an oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130cthat are provided in this order from the insulating layer120side. Oxide semiconductor layers having different compositions, for example, can be used as the oxide semiconductor layers130a,130b, and130c. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.13A and13B.FIG.13Ais a top view of a transistor107.FIG.13Billustrates a cross section in the direction of a dashed-dotted line G1-G2inFIG.13A. A cross section in the direction of a dashed-dotted line G3-G4inFIG.13Acorresponds toFIG.14AorFIG.14B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line G1-G2is referred to as a channel length direction, and the direction of the dashed-dotted line G3-G4is referred to as a channel width direction. The transistor107illustrated inFIGS.13A and13Bhas the same structure as the transistor106except that the oxide semiconductor layers130aand130bare covered with the oxide semiconductor layer130c. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.15A and15B.FIG.15Ais a top view of a transistor108.FIG.15Billustrates a cross section in the direction of a dashed-dotted line H1-H2inFIG.15A. A cross section in the direction of a dashed-dotted line H3-H4inFIG.15Acorresponds toFIG.16AorFIG.16B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line H1-H2is referred to as a channel length direction, and the direction of the dashed-dotted line H3-H4is referred to as a channel width direction. The transistor108illustrated inFIGS.15A and15Bhas the same structure as the transistor106except that the oxide semiconductor layers130aand130bare partly covered with the oxide semiconductor layer130e. Furthermore, the transistor of one embodiment of the present invention may have a structure ofFIGS.17A and17B.FIG.17Ais a top view of a transistor109.FIG.17Billustrates a cross section in the direction of a dashed-dotted line I1-I2inFIG.17A. A cross section in the direction of a dashed-dotted line13-14inFIG.17Acorresponds to the cross section in the channel width direction of the transistor108inFIG.16AorFIG.16B. In these drawings, some components are enlarged, reduced in size, or omitted for easy understanding. In some cases, the direction of the dashed-dotted line I1-I2is referred to as a channel length direction, and the direction of the dashed-dotted line13-14is referred to as a channel width direction. The transistor109illustrated inFIGS.17A and17Bhas the same structure as the transistor102except that the oxide semiconductor layer130includes the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130cthat are provided in this order from the insulating layer120side. The oxide semiconductor layer130of the transistor109may have a structure in which the oxide semiconductor layer130aand the oxide semiconductor layer130bare partly or entirely covered with the oxide semiconductor layer130c, like the transistors107and108. The transistor of one embodiment of the present invention may include the conductive layer172between the oxide semiconductor layer130and the substrate110as illustrated inFIGS.18A to18C. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be further increased and the threshold voltage can be controlled. In the cross section in the channel length direction illustrated inFIG.18A, the width of the conductive layer172may be shortened so that the conductive layer172may not overlap with the source electrode layer140, the drain electrode layer150, or the like. Moreover, the width of the conductive layer172may be further shortened so as to be shorter than the width of the gate electrode layer170. Note that although the examples illustrated inFIGS.18A to18Care variations of the transistor107, the structures of these examples can be applied to the transistors106,108, and109. In the transistor of one embodiment of the present invention (the transistors101to109), the gate electrode layer170electrically surrounds the oxide semiconductor layer130in the channel width direction, with the gate insulating film160positioned therebetween, whereby on-state current is increased. Such a structure of the transistor is referred to as a surrounded channel (s-channel) structure. In the transistor including the oxide semiconductor layers130aand130band the transistor including the oxide semiconductor layers130a,130b, and130c, selecting appropriate materials for the two or three layers forming the oxide semiconductor layer130allows current to flow in the oxide semiconductor layer130b. Since a current flows in the oxide semiconductor layer130b, the current is hardly influenced by interface scattering, leading to a high on-state current. Note that increasing the thickness of the oxide semiconductor layer130bcan increase on-state current. The thickness of the oxide semiconductor layer130bmay be, for example, 100 nm to 200 nm. A semiconductor device using a transistor having any of the above structures can have favorable electrical characteristics. This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 2 In this embodiment, components of the transistors described in Embodiment 1 are described in detail. The substrate110is not limited to a simple supporting substrate, and may be a substrate where another device such as a transistor is formed. In that case, one or more of the gate electrode layer170, the source electrode layer140, and the drain electrode layer150of the transistor may be electrically connected to the another device. As the substrate110, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used, for example. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, a silicon-on-insulator (SOI) substrate, or the like may be used. The insulating layer120can have a function of supplying oxygen to the oxide semiconductor layer130as well as a function of preventing diffusion of impurities from the substrate110. For this reason, the insulating layer120is preferably an insulating film containing oxygen, and further preferably an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. For this reason, the insulating layer120is a film in which the amount of released oxygen when converted into oxygen atoms is 1.0×1019atoms/cm3or more in TDS analysis. In the TDS analysis, heat treatment is performed at a temperature of a film surface of higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. In the case where the substrate110is a substrate where another device is formed as described above, the insulating layer120also has a function as an interlayer insulating film. In that case, planarization treatment such as chemical mechanical polishing (CMP) is preferably performed so as to form a flat surface. For example, the insulating layer120can be formed using an oxide insulating film including aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like, a nitride insulating film including silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like, or a mixed material of any of these. The insulating layer120may be a stack of any of the above materials. In this embodiment, detailed description is given mainly on the case where the oxide semiconductor layer130has a three-layer structure in which the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130care stacked in this order from the insulating layer120side as in the transistors106,107,108, and109. Note that in the case where the oxide semiconductor layer130is a single layer as in the transistors101and102, a layer corresponding to the oxide semiconductor layer130bis used. In the case where the oxide semiconductor layer130has a two-layer structure as in the transistors103,104, and105, a stack in which a layer corresponding to the oxide semiconductor layer130band a layer corresponding to the oxide semiconductor layer130care stacked in this order from the insulating layer120side is used. In such a case, the oxide semiconductor layer130band the oxide semiconductor layer130ccan be replaced with each other. In the case where the oxide semiconductor layer130has a stacked-layer structure of four or more layers, for example, a structure in which another oxide semiconductor layer is stacked over the three-layer stack of the oxide semiconductor layer130described in this embodiment or a structure in which another oxide semiconductor layer is inserted in any one of the interfaces in the three-layer stack can be employed. For the oxide semiconductor layer130b, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the oxide semiconductor layer130aand the oxide semiconductor layer130cis used. The electron affinity can be obtained by subtracting an energy difference between the conduction band minimum and the valence band maximum (what is called an energy gap) from an energy difference between the vacuum level and the valence band maximum (what is called an ionization potential). The oxide semiconductor layer130aand the oxide semiconductor layer130ceach contain one or more kinds of metal elements contained in the oxide semiconductor layer130b. For example, the oxide semiconductor layer130aand the oxide semiconductor layer130care preferably formed using an oxide semiconductor whose conduction band minimum is closer to a vacuum level than that of the oxide semiconductor layer130bby 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. In such a structure, when an electric field is applied to the gate electrode layer170, a channel is formed in the oxide semiconductor layer130bwhose conduction band minimum is the lowest in the oxide semiconductor layer130. Further, since the oxide semiconductor layer130acontains one or more kinds of metal elements contained in the oxide semiconductor layer130b, an interface state is unlikely to be formed at the interface between the oxide semiconductor layer130band the oxide semiconductor layer130a, compared with the interface between the oxide semiconductor layer130band the insulating layer120on the assumption that the oxide semiconductor layer130bis in contact with the insulating layer120. The interface state sometimes forms a channel; therefore, the threshold voltage of the transistor is changed in some cases. Thus, with the oxide semiconductor layer130a, fluctuations in electrical characteristics of the transistor, such as threshold voltage, can be reduced. Further, the reliability of the transistor can be improved. Furthermore, since the oxide semiconductor layer130ccontains one or more kinds of metal elements contained in the oxide semiconductor layer130b, scattering of carriers is unlikely to occur at the interface between the oxide semiconductor layer130band the oxide semiconductor layer130c, compared with the interface between the oxide semiconductor layer130band the gate insulating film160on the assumption that the oxide semiconductor layer130bis in contact with the gate insulating film160. Thus, with the oxide semiconductor layer130c, the field-effect mobility of the transistor can be increased. For the oxide semiconductor layer130aand the oxide semiconductor layer130c, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf at a higher atomic ratio than that in the oxide semiconductor layer130bcan be used. Specifically, an atomic ratio of any of the above metal elements in the oxide semiconductor layer130aand the oxide semiconductor layer130cis 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as much as that in the oxide semiconductor layer130b. Any of the above metal elements is strongly bonded to oxygen and thus has a function of suppressing generation of an oxygen vacancy in the oxide semiconductor layer130aand the oxide semiconductor layer130c. That is, an oxygen vacancy is less likely to be generated in the oxide semiconductor layer130aand the oxide semiconductor layer130cthan in the oxide semi conductor layer130b. An oxide semiconductor that can be used for the oxide semiconductor layers130a,130b, and130cpreferably contains at least indium (In) or zinc (Zn). Both In and Zn are preferably contained. In order to reduce fluctuations in electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to In and Zn. As a stabilizer, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like can be given. As another stabilizer, lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu) can be given. As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn oxide, a Sn—Zn oxide, an Al—Zn oxide, a Zn—Mg oxide, a Sn—Mg oxide, an In—Mg oxide, an In—Ga oxide, an In—Ga—Zn oxide, an In—Al—Zn oxide, an In—Sn—Zn oxide, a Sn—Ga—Zn oxide, an Al—Ga—Zn oxide, a Sn—Al—Zn oxide, an In—Hf—Zn oxide, an In—La—Zn oxide, an In—Ce—Zn oxide, an In—Pr—Zn oxide, an In—Nd—Zn oxide, an In—Sm—Zn oxide, an In—Eu—Zn oxide, an In—Gd—Zn oxide, an In—Tb—Zn oxide, an In—Dy—Zn oxide, an In—Ho—Zn oxide, an In—Er—Zn oxide, an In—Tm—Zn oxide, an In—Yb—Zn oxide, an In—Lu—Zn oxide, an In—Sn—Ga—Zn oxide, an In—Hf—Ga—Zn oxide, an In—Al—Ga—Zn oxide, an In—Sn—Al—Zn oxide, an In—Sn—Hf—Zn oxide, and an In—Hf—Al—Zn oxide. For example, “In—Ga—Zn oxide” means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain another metal element in addition to In, Ga, and Zn. Note that in this specification, a film containing the In—Ga—Zn oxide is also referred to as an IGZO film. A material represented by In/MO3(ZnO)m(m>0 is satisfied, and in is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, and Nd. Alternatively, a material represented by In2SnO5(ZnO)n(n>0, n is an integer) may be used. Note that when each of the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130cis an In-M-Zn oxide containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), and when the oxide semiconductor layer130ahas an atomic ratio of In to M and Zn which is x1:y1:z1, the oxide semiconductor layer130bhas an atomic ratio of In to M and Zn which is x2:y2:z2, and the oxide semiconductor layer130chas an atomic ratio of In to M and Zn which is x3:y3:z3, each of y1/x1and y3/x3is preferably larger than y2/x2. Each of y1/x1and y3/x3is 1.5 times or more, preferably 2 times or more, further preferably 3 times or more as large as y2/x2. At this time, when y2is greater than or equal to x2in the oxide semiconductor layer130b, the transistor can have stable electrical characteristics. However, when y2is 3 times or more as large as x2, the field-effect mobility of the transistor is reduced; accordingly, y2is preferably smaller than 3 times x2. In the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in each of the oxide semiconductor layer130aand the oxide semiconductor layer130care preferably less than 50 atomic % and greater than or equal to 50 atomic %, respectively, further preferably less than 25 atomic % and greater than or equal to 75 atomic %, respectively. In the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in the oxide semiconductor layer130bare preferably greater than or equal to 25 atomic % and less than 75 atomic %, respectively, further preferably greater than or equal to 34 atomic % and less than 66 atomic %, respectively. The indium content in the oxide semiconductor layer130bis preferably higher than those in the oxide semiconductor layers130aand130c. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide having a composition in which the proportion of In is higher than that of M has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of M. Thus, with the use of an oxide having a high content of indium for the oxide semiconductor layer130b, a transistor having high field-effect mobility can be obtained. The thickness of each of the oxide semiconductor layers130aand130cis greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm. The thickness of the oxide semiconductor layer130bis greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 150 nm, further preferably greater than or equal to 10 nm and less than or equal to 100 nm. In addition, the oxide semiconductor layer130bis preferably thicker than the oxide semiconductor layer130aand the oxide semiconductor layer130c. Note that in order that a transistor in which an oxide semiconductor layer serves as a channel have stable electrical characteristics, it is effective to reduce the concentration of impurities in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic (i-type) or substantially intrinsic. The term “substantially intrinsic” refers to the state where an oxide semiconductor layer has a carrier density lower than 1×1019/cm3, preferably lower than 1×1015/cm3, further preferably lower than 1×1013/cm3, still further preferably lower than 1×108/cm3and higher than or equal to 1×10−9/cm3. In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than main components of the oxide semiconductor layer are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density. In addition, silicon in the oxide semiconductor layer forms an impurity level. The impurity level serves as a trap and might cause deterioration of electrical characteristics of the transistor. Accordingly, in the oxide semiconductor layer130a, the oxide semi conductor layer130b, and the oxide semiconductor layer130cand at interfaces between these layers, the impurity concentration is preferably reduced. In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, in secondary ion mass spectrometry (SIMS), for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, further preferably lower than 1×1018atoms/cm3. Further, the concentration of hydrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than or equal to 2×1020atoms/cm3, preferably lower than or equal to 5×1019atoms/cm3, further preferably lower than or equal to 1×1019atoms/cm3, still further preferably lower than or equal to 5×1018atoms/cm3. Further, the concentration of nitrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3. In the case where the oxide semiconductor layer includes crystals, high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor layer. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the concentration of silicon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer may be lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, further preferably lower than 1×1018atoms/cm3. Further, the concentration of carbon at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer may be lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, further preferably lower than 1×1018atoms/cm3, for example. A transistor in which a highly purified oxide semiconductor film is used for a channel formation region as described above has an extremely low off-state current. For example, in the case where the voltage between the source and the drain is set to approximately 0.1 V, 5 V, or 10 V, the off-state current standardized on the channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer. Note that as the gate insulating film of the transistor, an insulating film containing silicon is used in many cases; thus, it is preferable that, as in the transistor of one embodiment of the present invention, a region of the oxide semiconductor layer, which serves as a channel, not be in contact with the gate insulating film for the above-described reason. In the case where a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, scattering of carriers occurs at the interface, whereby the field-effect mobility of the transistor is reduced in some cases. Also from the view of the above, it is preferable that the region of the oxide semiconductor layer, which serves as a channel, be separated from the gate insulating film. Accordingly, with the oxide semiconductor layer130having a stacked-layer structure including the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130c, a channel can be formed in the oxide semiconductor layer130b; thus, the transistor can have a high field-effect mobility and stable electrical characteristics. In a band structure, the conduction band minimums of the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130care continuous. This can be understood also from the fact that the compositions of the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130care close to one another and oxygen is easily diffused among the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130c. Thus, the oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130chave a continuous physical property although they have different compositions and form a stack. In the drawings of this specification, interfaces between the oxide semiconductor layers of the stack are indicated by dotted lines. The oxide semiconductor layer130in which layers containing the same main components are stacked is formed to have not only a simple stacked-layer structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which the conduction band minimums are continuous (U-shape well)). In other words, the stacked-layer structure is formed such that there exists no impurity that forms a defect level such as a trap center or a recombination center at each interface. If impurities exist between the stacked oxide semiconductor layers, the continuity of the energy band is lost and carriers disappear by a trap or recombination at the interface. For example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 can be used for the oxide semiconductor layer130aand the oxide semiconductor layer130c, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 2:1:3, 5:5:6, or 3:1:2, can be used for the oxide semiconductor layer130b. In each of the oxide semiconductor layers130a,130b, and130c, the proportion of each atom in the above atomic ratios may vary within a range of ±20% as an error. The oxide semiconductor layer130bof the oxide semiconductor layer130serves as a well, so that a channel is formed in the oxide semiconductor layer130bin a transistor including the oxide semiconductor layer130. Note that since the conduction band minimums are continuous, the oxide semiconductor layer130can also be referred to as a U-shaped well. Further, a channel formed to have such a structure can also be referred to as a buried channel. Note that trap levels due to impurities or defects might be formed in the vicinity of the interface between an insulating film such as a silicon oxide film and each of the oxide semiconductor layer130aand the oxide semiconductor layer130c. The oxide semiconductor layer130bcan be distanced away from the trap levels owing to the existence of the oxide semiconductor layer130aand the oxide semiconductor layer130c. However, when the energy differences between the conduction band minimum of the oxide semiconductor layer130band the conduction band minimum of each of the oxide semiconductor layer130aand the oxide semiconductor layer130care small, an electron in the oxide semiconductor layer130bmight reach the trap level by passing over the energy differences. When the electron causing a negative charge is trapped in the trap level, the threshold voltage of the transistor is shifted in the positive direction. Thus, to reduce fluctuations in the threshold voltage of the transistor, energy differences of at least certain values between the conduction band minimum of the oxide semiconductor layer130band the conduction band minimum of each of the oxide semiconductor layer130aand the oxide semiconductor layer130care necessary. Each of the energy differences is preferably greater than or equal to 0.1 eV, further preferably greater than or equal to 0.15 eV. The oxide semiconductor layer130a, the oxide semiconductor layer130b, and the oxide semiconductor layer130cpreferably include crystal parts. In particular, when crystals with c-axis alignment are used, the transistor can have stable electrical characteristics. Moreover, crystals with c-axis alignment are resistant to bending; therefore, using such crystals can improve the reliability of a semiconductor device using a flexible substrate. The gate insulating film160can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The gate insulating film160may be a stack of any of the above materials. The gate insulating film160may contain lanthanum (La), nitrogen, or zirconium (Zr) as an impurity. An example of a stacked-layer structure of the gate insulating film160will be described. The gate insulating film160includes, for example, oxygen, nitrogen, silicon, or hafnium. Specifically, the gate insulating film160preferably includes hafnium oxide and silicon oxide or silicon oxynitride. Hafnium oxide and aluminum oxide have higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, by using hafnium oxide or aluminum oxide, a physical thickness can be made larger than an equivalent oxide thickness; thus, even in the case where the equivalent oxide thickness is less than or equal to 10 nm or less than or equal to 5 nm, leakage current due to tunnel current can be low. That is, it is possible to provide a transistor with a low off-state current. Moreover, hafnium oxide with a crystalline structure has higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to provide a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples. A surface over which the hafnium oxide with a crystalline structure is formed might have interface states due to defects. The interface states might function as trap centers. Therefore, in the case where the hafnium oxide is provided close to the channel region of the transistor, the electrical characteristics of the transistor might deteriorate owing to the interface states. In order to reduce the adverse effect of the interface states, in some cases, it is preferable to separate the channel region of the transistor and the hafnium oxide from each other by providing another film therebetween. The film has a buffer function. The film having a buffer function may be included in the gate insulating film160or included in the oxide semiconductor film. That is, the film having a buffer function can be formed using silicon oxide, silicon oxynitride, an oxide semiconductor, or the like. Note that the film having a buffer function is formed using, for example, a semiconductor or an insulator having a larger energy gap than a semiconductor to be the channel region. Alternatively, the film having a buffer function is formed using, for example, a semiconductor or an insulator having lower electron affinity than a semiconductor to be the channel region. Further alternatively, the film having a buffer function is formed using, for example, a semiconductor or an insulator having higher ionization energy than a semiconductor to be the channel region. In some cases, the threshold voltage of the transistor can be controlled by trapping charge in the interface states (trap centers) at the surface over which the hafnium oxide with a crystalline structure is formed. In order that the charge stably exists, for example, an insulator having a larger energy gap than the hafnium oxide is provided between the channel region and the hafnium oxide. Alternatively, a semiconductor or an insulator having smaller electron affinity than the hafnium oxide is provided. The film having a buffer function may be formed using a semiconductor or an insulator having higher ionization energy than hafnium oxide. Use of such an insulator inhibits discharge of the charge trapped by the interface states, so that the charge can be retained for a long time. Examples of such an insulator include silicon oxide and silicon oxynitride. In order to make the interface states in the gate insulating film160trap charge, electrons are transferred from the oxide semiconductor layer130toward the gate electrode layer170. As a specific example, the potential of the gate electrode layer170is kept higher than the potential of the source or drain electrode under high temperature conditions (e.g., a temperature higher than or equal to 125° C. and lower than or equal to 450° C., typically higher than or equal to 150° C. and lower than or equal to 300° C.) for one second or longer, typically for one minute or longer. The threshold voltage of a transistor in which a predetermined amount of electrons are trapped in interface states in the gate insulating film160or the like shifts in the positive direction. The amount of electrons to be trapped (the amount of change in threshold voltage) can be controlled by adjusting the voltage of the gate electrode layer170or the time for which the voltage is applied. Note that a location in which charge is trapped is not necessarily limited to the inside of the gate insulating film160as long as charge can be trapped therein. A stacked film having a similar structure may be used as another insulating layer. For the gate electrode layer170, for example, a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, W, or the like can be used. It is also possible to use an alloy or a conductive nitride of any of these materials. It is also possible to use a stack of a plurality of materials selected from these materials, alloys of these materials, and conductive nitrides of these materials. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. It is also possible to use Cu or an alloy such as Cu—Mn, which has low resistance, or a stack of any of the above materials and Cu or an alloy such as Cu—Mn. In this embodiment, tantalum nitride is used for the conductive layer171and tungsten is used for the conductive layer172to form the gate electrode layer170. As the insulating layer175, a silicon nitride film, an aluminum nitride film, or the like containing hydrogen is preferably used. When an insulating film containing hydrogen is used as the insulating layer175, part of the oxide semiconductor layer can have n-type conductivity as described above. In addition, a nitride insulating film functions as a blocking film against moisture and the like and can improve the reliability of the transistor. Further, the insulating layer180is preferably formed over the insulating layer175. The insulating layer185can be formed using an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The oxide insulating layer may be a stack of any of the above materials. Here, like the insulating layer120, the insulating layer180preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer180can be diffused into the channel formation region in the oxide semiconductor layer130through the gate insulating film160, so that oxygen vacancies formed in the channel formation region can be filled with the oxygen. In this manner, stable electrical characteristics of the transistor can be achieved. As each of the source electrode layer140and the drain electrode layer150, for example, a single layer or a stacked layer formed using a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and alloys of any of these metal materials can be used. Typically, it is preferable to use Ti, which is particularly easily bonded to oxygen, or W, which has a high melting point and thus allows subsequent process temperatures to be relatively high. It is also possible to use a stack of any of the above materials and Cu or an alloy such as Cu—Mn, which has low resistance. In this embodiment, W is used for the conductive layers141and151and Cu is used for the conductive layers142and152to form the source electrode layer140and the drain electrode layer150. The above materials are capable of extracting oxygen from an oxide semiconductor film. Therefore, in a region of the oxide semiconductor layer that is in contact with any of the above materials, oxygen is released from the oxide semiconductor film and an oxygen vacancy is formed. Hydrogen slightly contained in the film enters the oxygen vacancy, whereby the region is markedly changed to an n-type region. Accordingly, the n-type regions can serve as a source or a drain region of the transistor. It is preferable to form the insulating layer185as a protective film for the source electrode layer140, the drain electrode layer150, and the insulating layer180. As the insulating layer185, an insulating film that is similar to the insulating layer175can be used. An aluminum oxide film can also be used as the insulating layer185. The aluminum oxide film has a high blocking effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can suitably function as a protective film that has effects of preventing entry of impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor, into the oxide semiconductor layer130, preventing release of oxygen, which is a main component of the oxide semiconductor layer130, from the oxide semiconductor layer, and preventing unnecessary release of oxygen from the insulating layer120. Further, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics of the transistor. A decrease in channel width causes a reduction in on-state current. In the transistors103to109of embodiments of the present invention, the oxide semiconductor layer130cis formed to cover the oxide semiconductor layer130bwhere a channel is formed; thus, a channel formation layer is not in contact with the gate insulating film. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating film can be reduced and the on-state current of the transistor can be increased. In the transistor of one embodiment of the present invention, as described above, the gate electrode layer170is formed to electrically surround the oxide semiconductor layer130in the channel width direction; accordingly, a gate electric field is applied to the oxide semiconductor layer130in the side surface direction in addition to the perpendicular direction. In other words, a gate electric field is applied to the entire channel formation layer and an effective channel width is increased, leading to a further increase in the on-state current. In the transistor106to the transistor109of one embodiment of the present invention, the oxide semiconductor layer130bwhere a channel is formed is provided over the oxide semiconductor layer130a, so that an interface state is less likely to be formed. In addition, since the oxide semiconductor layer130bis positioned at the middle of the three-layer structure, the influence of an impurity that enters from upper and lower layers on the oxide semiconductor layer130bis eliminated. Therefore, the transistor can achieve not only the increase in the on-state current of the transistor but also stabilization of the threshold voltage and a reduction in the S value (subthreshold value). Thus, Icut (current when gate voltage VG is 0 V) can be reduced and power consumption can be reduced. Further, the threshold voltage of the transistor becomes stable; thus, long-term reliability of the semiconductor device can be improved. In addition, the transistor of one embodiment of the present invention is suitable for a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization is reduced. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 3 In this embodiment, an oxide semiconductor film that can be used for a transistor of one embodiment of the present invention is described. Note that in this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system. <Structure of Oxide Semiconductor> A structure of an oxide semiconductor is described below. An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS. It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order. This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor. <CAAC-OS> First, a CAAC-OS is described. A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets). In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. A CAAC-OS observed with TEM is described below.FIG.19Ashows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. FIG.19Bis an enlarged Cs-corrected high-resolution TEM image of a region (1) inFIG.19A.FIG.19Bshows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS. As shown inFIG.19B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line inFIG.19C.FIGS.19B and19Cprove that the size of a pellet is approximately 1 nm to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets5100of a CAAC-OS over a substrate5120is illustrated by such a structure in which bricks or blocks are stacked (seeFIG.19D). The part in which the pellets are tilted as observed inFIG.19Ccorresponds to a region5161shown inFIG.19D. FIG.20Ashows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.FIGS.20B,20C, and20Dare enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) inFIG.20A, respectively.FIGS.20B,20C, and20Dindicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets. Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO4crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown inFIG.21A. This peak is derived from the (009) plane of the InGaZnO4crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when2θ is around 36°, in addition to the peak at2θ of around 31°. The peak at2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when2θ is around 31° and that a peak not appear when2θ is around 36°. On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO4crystal. In the case of the CAAC-OS, when analysis (ϕ scan) is performed with2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (ϕ axis), as shown inFIG.21B, a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO4, when ϕ scan is performed with2θ fixed at around 56°, as shown inFIG.21C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown inFIG.68Acan be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,FIG.68Bshows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown inFIG.68B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring inFIG.68Bis considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO4crystal. The second ring inFIG.68Bis considered to be derived from the (110) plane and the like. As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies). Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein. The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, lower than 8×1011/cm3, preferably lower than 1×1011/cm3, further preferably lower than 1×1019/cm3, and is higher than or equal to 1×10−9/cm3). Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics. <nc-OS> Next, an nc-OS will be described. An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases. Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC). The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. <a-like OS> An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor. In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. The a-like OS has an unstable structure because it includes a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below. An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide. First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO4crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4crystal. FIG.69shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.FIG.69indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) inFIG.69, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×108e−/nm2. In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108e−/nm2. Specifically, as shown by (2) and (3) inFIG.69, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose. In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor. For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3and lower than 6.3 g/cm3. Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density. As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example. This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 4 In this embodiment, a display device of one embodiment of the present invention will be described with reference to drawings. The “display device” in this specification means an image display device or a light source (including a lighting device). Further, the display device includes any of the following modules in its category: a module including a connector such as a flexible printed circuit (FPC), or tape carrier package (TCP); a module including TCP which is provided with a printed wiring board at the end thereof; and a module including a driver circuit which is directly mounted on a display element by a chip on glass (COG) method. FIG.22is a top view of a display device500that is one embodiment of the present invention. InFIG.22, some components are enlarged, reduced in size, made to be visible, or omitted for easy understanding. The display device500includes a pixel portion502over a substrate501, a circuit portion504and a circuit portion505configured to drive the pixel portion, a sealant512provided to surround the pixel portion502, the circuit portion504, and the circuit portion505, and a substrate507provided to face the substrate501. Note that a signal line driver circuit (source driver) and a scan line driver circuit (gate driver) can be used, for example, as the circuit portion504and the circuit portion505, respectively. The substrate501and the substrate507are bonded to each other with the sealant512. Although not shown inFIG.22, a display element is provided between the substrate501and the substrate507. In other words, the pixel portion502, the circuit portion504, the circuit portion505, and the display element are sealed with the substrate501, the sealant512, and the substrate507. Furthermore, in the display device500, an FPC terminal portion508(FPC: flexible printed circuit) that is electrically connected to the pixel portion502, the circuit portion504, and the circuit portion505is provided over the substrate501in a region different from a region surrounded by the sealant512. The FPC terminal portion508is connected to an FPC516, and a variety of signals are supplied to the pixel portion502, the circuit portion504, and the circuit portion505with the FPC516. In addition, signal lines510are connected to the pixel portion502, the circuit portion504, the circuit portion505, and the FPC terminal portion508. The variety of signals supplied from the FPC516are given to the pixel portion502, the circuit portion504, and the circuit portion505through the signal lines510. InFIG.22, the circuits for driving the pixel circuit portion502are positioned in two regions; however, the structure of the circuit is not limited thereto. For example, the circuit may be positioned in one region. Alternatively, the circuit may be divided into three or more parts. Further alternatively, only one of the circuit portion504and the circuit portion505may be provided over the substrate501, and the other circuit may be externally provided. Further, the circuit for driving the pixel portion502may be formed over the substrate501like a transistor included in the pixel portion502, or may be formed by mounting an IC chip on the substrate501by chip on glass (COG) or the like. Alternatively, the circuit may be connected to a TCP or the like. The pixel portion502, the circuit portion504, and the circuit portion505in the display device500include a plurality of transistors in which a channel formation region is formed using an oxide semiconductor layer. Since the transistor using an oxide semiconductor layer has high mobility, an area occupied by transistors can be made small, and the aperture ratio can be increased. With use of the transistor, the circuit portion504and the circuit portion505can be formed over the substrate provided with the pixel portion502. In addition, the transistor has extremely low off-state current and can hold a video signal or the like for a longer period; thus, the frame frequency can be lowered, and the power consumption of the display device can be reduced. The oxide semiconductor layer preferably includes a c-axis aligned crystal. In the case where the oxide semiconductor layer including the crystal is used for a channel formation region of the transistor, a crack or the like is less likely to occur in the oxide semiconductor layer when the display device500is bent, for example. As a result, the reliability can be improved. Thus, with use of the transistor using an oxide semiconductor layer, a display device that is superior to a display device including an amorphous silicon layer or a polycrystalline silicon layer can be formed, for example. As a display element included in the display device500, a liquid crystal element or a light-emitting element can be typically used. Next, a liquid crystal display device500ais described.FIG.23is a cross-sectional view along dashed-dotted line J1-J2inFIG.22in the case where a liquid crystal element is used for the display device500. In the liquid crystal display device500a, the substrate501, a first element layer, a second element layer, and the substrate507are stacked in this order. InFIG.23, the first element layer includes transistors550and552, a planarization insulating film570, a connection electrode560, a conductive film572, and the like. The second element layer includes a conductive film574, an insulating film534, a coloring layer536(color filter), a light-blocking layer538(black matrix), and the like. There is a case where some of the above components is not included or a component other than the above components is included in the first element layer and the second element layer. The first element layer and the second element layer are sealed with a liquid crystal layer576and the sealant512to form a liquid crystal element575. The liquid crystal display device500aincludes a lead wiring portion511, the pixel portion502, the circuit portion504, and the FPC terminal portion508. Note that the lead wiring portion511includes the signal line510. The liquid crystal display device500ahas a structure in which the transistor550and the transistor552are included in the pixel portion502and the circuit portion504, respectively. The structure of the transistor550and the transistor552is not limited to that illustrated inFIG.23. The sizes of the transistor550and the transistor552can be changed (in the channel length, the channel width, and the like) as appropriate, or the number of transistors can be changed. In addition, the circuit portion505(not shown inFIG.23) can have a structure similar to that of the circuit portion504. The signal line510included in the lead wiring portion511can be formed in a step of forming a source electrode layer and a drain electrode layer of the transistor550. The FPC terminal portion508includes the connection electrode560, an anisotropic conductive film580, and the FPC516. The connection electrode560can be formed in a step of forming the source electrode layer and the drain electrode layer of the transistor550. In addition, the connection electrode560is electrically connected to a terminal of the FPC516through the anisotropic conductive film580. A wiring containing a copper element is preferably used for the signal line connected to the transistor in the pixel portion and the transistor in the driver circuit portion. When the wiring containing a copper element is used, the signal delay due to the wiring resistance and the like can be suppressed. Further, inFIG.23, the planarization insulating film570is provided over the transistor550and the transistor552. The planarization insulating film570can be formed using a heat-resistant organic material, such as a polyimide resin, an acrylic resin, a polyimide amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the planarization insulating film570may be formed by stacking a plurality of insulating films formed from these materials. Alternatively, a structure without the planarization insulating film570may be employed. The conductive film572is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor550. The conductive film572functions as a pixel electrode formed over the planarization insulating film570, i.e., one electrode of the liquid crystal element. As the conductive film572, a conductive film having properties of transmitting visible light is preferably used. For example, a material including one of indium (In), zinc (Zn), and tin (Sn) is preferably used for the conductive film. The liquid crystal element575includes the conductive film572, the conductive film574, and the liquid crystal layer576. The conductive film574is provided on the substrate507side and functions as a counter electrode. In the liquid crystal display device500aillustrated inFIG.23, an orientation state of the liquid crystal layer576is changed by the voltage applied to the conductive film572and the conductive film574, so that transmission or non-transmission of light is changed and thus an image can be displayed. Although not shown inFIG.23, alignment films may be formed between the conductive film572and the liquid crystal layer576and between the conductive film574and the liquid crystal layer576. An optical member (an optical substrate) such as a polarizing member, a retardation member, or an anti-reflection member, and the like may be provided as appropriate. For example, circular polarization may be employed by using a polarizing substrate and a retardation substrate. In addition, a backlight, a sidelight, or the like may be used as a light source. A spacer578is provided between the substrate501and the substrate507. The spacer578is a columnar spacer obtained by selective etching of an insulating film and is provided in order to adjust the thickness (cell gap) of the liquid crystal layer576. Note that as the spacer578, a spherical spacer may be used. For the liquid crystal layer576, a liquid crystal material such as thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, or anti-ferroelectric liquid crystal can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. Alternatively, in the case of employing a horizontal electric field mode, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. A blue phase is one of liquid crystal phases, which is generated just before a cholesteric phase changes into an isotropic phase while temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which several weight percent or more of a chiral material is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal showing a blue phase and a chiral material has a short response time and optical isotropy, which makes the alignment process unneeded and the viewing angle dependence small. An alignment film does not need to be provided and rubbing treatment is thus not necessary; accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. In the case where the liquid crystal element is used as a display element, a twisted nematic (TN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optical compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, or the like can be used. A normally black liquid crystal display device such as a transmissive liquid crystal display device utilizing a vertical alignment (VA) mode is preferable. There are some examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, or the like can be employed. As a display method in the pixel portion502, a progressive method, an interlace method, or the like can be employed. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, a display unit may be composed of four pixels of the R pixel, the G pixel, the B pixel, and a W (white) pixel. Alternatively, a display unit may be composed of two of color elements among R, G, and B as in PenTile layout. The two colors may differ among display units. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Further, the size of a display region may be different depending on respective dots of the color components. Embodiments of the disclosed invention are not limited to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display. Next, an EL display device500bincluding a light-emitting element is described.FIG.24is a cross-sectional view along dashed-dotted line J1-J2inFIG.22in the case where a light-emitting element is used for the display device500. Note that the same description as that of the liquid crystal display device500ais omitted. In the EL display device500b, the substrate501, a first element layer610, a second element layer611, and the substrate507are stacked in this order. InFIG.24, the first element layer610includes the transistors550and552, the planarization insulating film570, the connection electrode560, a light-emitting element680, an insulating film530, the signal line510, and the connection electrode560. The second element layer611includes the insulating film534, the coloring layer536, and the light-blocking layer538. The first element layer610and the second element layer611are sealed with a sealing layer632and the sealant512. Note that there is a case where part of the above components is not included or a component other than the above components is included in the first element layer610and the second element layer611. The light-emitting element680includes a conductive film644, an EL layer646, and a conductive film648. The EL display device500benables an image to be displayed when the EL layer646in the light-emitting element680emits light. The insulating film530is provided over the conductive film644over the planarization insulating film570. The insulating film530partly covers the conductive film644. A conductive film with high properties of reflecting light emitted from the EL layer is used for the conductive film644, and a conductive film with high properties of transmitting light emitted from the EL layer is used for the conductive film648, whereby the light-emitting element680can have a top emission structure. Alternatively, a conductive film with high properties of transmitting the light is used for the conductive film644, and a conductive film with high properties of reflecting light is used for the conductive film648, whereby the light-emitting element680can have a bottom emission structure. Further alternatively, a conductive film with high properties of transmitting the light is used for both the conductive film644and the conductive film648, whereby a dual emission structure can be obtained. The coloring layer536is provided to overlap with the light-emitting element680, and the light-blocking layer538is provided to overlap with the insulating film530and to be included in the lead wiring portion511and in the circuit portion504. The coloring layer536and the light-blocking layer538are covered with the insulating film534. A space between the light-emitting element680and the insulating film534is filled with the sealing layer632. Although a structure with the coloring layer536is described as the EL display device500b, the structure is not limited thereto. In the case where the EL layer646is formed by a side-by-side method, the coloring layer536is not necessarily provided. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 5 In this embodiment, transistors included in a display device of one embodiment of the present invention will be described. The transistors included in the display device of one embodiment of the present invention do not necessarily have a uniform structure. For example, a transistor in a pixel portion in the display device and a transistor used in a driver circuit portion for driving the pixel portion have different structures; thus, the transistors can have electric characteristics appropriate to the respective portions, and the reliability of the display device can be improved. When the transistor included in the driver circuit has a double gate structure, the transistor can have high field-effect mobility. Furthermore, the transistor in the driver circuit portion and the transistor in the pixel portion may have different channel lengths. Typically, the channel length of the transistor in the driver circuit portion can be less than 2.5 μm, or greater than or equal to 1.45 μm and less than or equal to 2.2 μm. The channel length of the transistor in the pixel portion can be greater than or equal to 2.5 μm, or greater than or equal to 2.5 μm and less than or equal to 20 μm. When the channel length of the transistor in the driver circuit portion is less than 2.5 μm, preferably greater than or equal to 1.45 μm and less than or equal to 2.2 μm, as compared with the transistor in the pixel portion, the field-effect mobility can be increased, and the amount of on-state current can be increased. Consequently, a driver circuit portion capable of high-speed operation can be formed. When the transistor in the driver circuit portion has high field-effect mobility, the number of input terminals can be made small. The liquid crystal display device500aillustrated inFIG.23and the EL display device500billustrated inFIG.24are examples in which the transistor101illustrated inFIGS.1A and1Bis used as the transistor in the pixel portion, and the transistor104illustrated inFIGS.7A and7Bis used as the transistor in the driver circuit portion. For the transistor in the pixel portion, a transistor with high reliability for light irradiation from the backlight or an EL element is preferable. For example, an oxide semiconductor layer deposited by a sputtering method using a material with an atomic ratio In:Ga:Zn=1:1:1 or 5:5:6 as a target is used for a channel formation region, whereby a transistor with high reliability for light irradiation can be formed. In contrast, for the transistor in the driver circuit portion, a transistor with high field-effect mobility is preferable. For example, an oxide semiconductor layer deposited by a sputtering method using a material with an atomic ratio In:Ga:Zn=3:1:2 as a target is used for a channel formation region, whereby a transistor with high field-effect mobility can be formed. In this embodiment, a method by which the above two types of transistors can be easily formed over one substrate is described with reference toFIGS.25A to25DandFIGS.26A to26D. When one of the transistors has an oxide semiconductor layer with a stacked structure, the two types of transistors can be easily formed over one substrate. On the left side of the drawings, a cross section in the channel length direction of a transistor A whose structure is similar to that of the transistor101inFIGS.1A and1Bis shown, as the transistor in the pixel portion. On the right side of the drawings, a cross section in the channel length direction of a transistor B whose structure is similar to that of the transistor104inFIGS.7A and7Bis shown, as the transistor in the driver circuit portion. Note that the reference numerals common in the transistor A and the transistor B are given in only one of the transistors. First, the insulating layer120is formed over the substrate110. Embodiment 2 can be referred to for the kind of the substrate110and the material of the insulating layer120. Note that the insulating layer120can be formed by a sputtering method, a CVD method, an MBE method, or the like. Oxygen may be added to the insulating layer120by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen facilitates supply of oxygen from the insulating layer120to the oxide semiconductor layer130. In the case where a surface of the substrate110is made of an insulator and there is no influence of impurity diffusion to the oxide semiconductor layer130to be formed later, a structure without the insulating layer120can be employed. Next, over the insulating layer120, an oxide semiconductor film130B that is to be the oxide semiconductor layer130bin the driver circuit transistor is deposited by a sputtering method, a CVD method, an MBE method, or the like. Next, a resist mask821is formed in a driver circuit region by a lithography method (seeFIG.25A). Then, using the resist mask, the oxide semiconductor film130B is selectively etched to form the oxide semiconductor layer130b(seeFIG.25B). Next, an oxide semiconductor film130C is formed to cover the oxide semiconductor layer130b. The oxide semiconductor films are preferably formed with a multi-chamber deposition apparatus (e.g., a sputtering apparatus) provided with a load lock chamber. It is preferable that each chamber of the sputtering apparatus be able to be evacuated to a high vacuum (to about 5×10−7Pa to 1×10−4Pa) by an adsorption vacuum pump such as a cryopump and that the chamber be able to heat a substrate over which a film is to be deposited to 100° C. or higher, preferably 500° C. or higher so that water and the like acting as impurities of the oxide semiconductor are removed as much as possible. Alternatively, a combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas containing a carbon component, moisture, or the like from an exhaust system into the chamber. Alternatively, a combination of a turbo molecular pump and a cryopump may be used as an exhaust system. Not only high vacuum evacuation of the chamber but also high purity of a sputtering gas is necessary to obtain a highly purified intrinsic oxide semiconductor. As an oxygen gas or an argon gas used for a sputtering gas, a gas which is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, further preferably −100° C. or lower is used, whereby entry of moisture or the like into the oxide semiconductor film can be prevented as much as possible. For the oxide semiconductor film130B and the oxide semiconductor film130C, any of the materials of the oxide semiconductor layers130band130cdescribed in Embodiment 2 can be used. In this embodiment, for example, an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2 is used for the oxide semiconductor film130B, and an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1 or 5:5:6 is used for the oxide semiconductor film130C. In each of the oxide semiconductor films130B and130C, the proportion of each atom in the above atomic ratio may vary within a range of ±20% as an error. In the case where a sputtering method is used for deposition, the above materials can be used as a target. Note that the oxide semiconductor films are preferably formed by a sputtering method. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. After the oxide semiconductor film130C is formed, first heat treatment may be performed. The first heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced pressure atmosphere. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, in order to compensate desorbed oxygen. The first heat treatment can increase the crystallinity of the oxide semiconductor film130B and the oxide semiconductor film130C and remove impurities such as water and hydrogen from the insulating layer120, the oxide semiconductor film130B, and the oxide semiconductor film130C. Note that the first heat treatment may be performed after etching for forming the stacked layers of the oxide semiconductor layer130band the oxide semiconductor layer130cdescribed later. Next, a resist mask822is formed in a pixel region by a lithography method. In addition, a resist mask823is formed over the stacked layers of the oxide semiconductor layer130band the oxide semiconductor film130C in the driver circuit region (seeFIG.25C). Next, using the resist masks, the oxide semiconductor film130C is selectively etched to form the oxide semiconductor layer130cin the pixel region. In addition, stacked layers of the oxide semiconductor layer130band the oxide semiconductor layer130care formed in the driver circuit region (seeFIG.25D). At this time, the oxide semiconductor layer130cin the driver circuit region is formed to cover the oxide semiconductor layer130b. Next, an insulating film160ato be a gate insulating film is formed over the oxide semiconductor layer in the pixel region and the stacked layers of the oxide semiconductor layer130band the oxide semiconductor layer130cin the driver circuit region. The insulating film160acan be formed using a material that can be used for the gate insulating film160described in Embodiment 3. A sputtering method, a CVD method, an MBE method, or the like can be used for the formation of the insulating film160a. Then, a conductive film171aand a conductive film172ato be the gate electrode layer170are formed over the insulating film160a. The conductive film171aand the conductive film172acan be formed using a material that can be used for the gate electrode layer170described in Embodiment 2. A sputtering method, a CVD method, an MBE method, or the like can be used for the formation of the conductive film171aand the conductive film172a(seeFIG.26A). Next, a resist mask824is formed over the conductive film172a. Using the resist mask, the conductive film172a, the conductive film171a, and the insulating film160aare selectively etched, so that the gate electrode layer170and the gate insulating film160are formed. Then, with the resist mask824formed in the above step left, an impurity830for forming an oxygen vacancy is added to the region231and the region232to make the regions have lower resistance. Thus, a source region and a drain region are formed (seeFIG.26B). As the impurity830, argon is, for example, added by plasma treatment. Since the resist mask changes its quality because of argon plasma, oxygen ashing is preferably performed for removal. Next, the insulating layer175is formed over the above-described structure. Embodiment 2 can be referred to for the material of the insulating layer175. The insulating layer175can be formed by a sputtering method, a CVD method, an MBE method, or the like. Next, the insulating layer180is formed over the insulating layer175(seeFIG.26C). Embodiment 2 can be referred to for the material of the insulating layer180. The insulating layer180can be formed by a sputtering method, a CVD method, an MBE method, or the like. Next, a resist mask is formed over the insulating layer180. Using the resist mask, the insulating layer180and the insulating layer175are selectively etched to form contact holes reaching the region231and the region232. Then, a conductive film is formed to cover the contact holes and selectively etched, so that the source electrode layer140and the drain electrode layer150are formed. Embodiment 2 can be referred to for the material of the conductive film. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, or the like. Next, the insulating layer185is formed over the above-described structure (seeFIG.26D). Embodiment 3 can be referred to for the material of the insulating layer185. The insulating layer185can be formed by a sputtering method, a CVD method, an MBE method, or the like. Oxygen may be added to the insulating layer180and/or the insulating layer185by plasma treatment, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like. Adding oxygen facilitates supply of oxygen from the insulating layer180and/or the insulating layer185to the insulating layer185. Then, second heat treatment may be performed. The second heat treatment can be performed under conditions similar to those of the first heat treatment. By the second heat treatment, excess oxygen is easily released from the insulating layers120,180, and185, so that oxygen vacancies in the oxide semiconductor layer can be reduced. Through the above steps, the transistor including the oxide semiconductor layer with a single-layer structure and the transistor including the oxide semiconductor layer with a stacked structure can be easily formed over one substrate. In addition, a display device that can operate at high speed, less deteriorates due to light irradiation, and includes a pixel portion with excellent display quality can be formed. Although the variety of films such as the metal films, the semiconductor films, and the inorganic insulating films which are described in this embodiment can be typically formed by a sputtering method or a plasma CVD method, such films may be formed by another method, e.g., a thermal chemical vapor deposition (CVD) method. A metal organic chemical vapor deposition (MOCVD) method or an atomic layer deposition (ALD) method may be employed as an example of a thermal CVD method. A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for film formation. Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to the chamber at a time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate. Deposition by an ALD method is performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). For example, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as or after the introduction of the first gas so that the source gases are not mixed, and then a second source gas is introduced. Note that in the case where the first source gas and the inert gas are introduced at a time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the introduction of the second source gas. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer; then the second source gas is introduced to react with the first layer; as a result, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of the gas introduction is repeated a plurality of times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust the thickness and thus is suitable for manufacturing minute FETs. The variety of films such as the metal films, the semiconductor films, and the inorganic insulating films which have been disclosed in this embodiment can be formed by a thermal CVD method such as an MOCVD method or an ALD method. For example, in the case where an In—Ga—Zn—Ox(x>0) film is formed, trimethylindium, trimethylgallium, and dimethylzinc can be used. Note that the chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Without limitation to the above combination, triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc. For example, in the case where a hafnium oxide film is formed with a deposition apparatus employing ALD, two kinds of gases, i.e., ozone (O3) as an oxidizer and a source material gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor compound (a hafnium alkoxide solution, typically tetrakis(dimethylamide)hafnium (TDMAH)) are used. Note that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Examples of another material liquid include tetrakis(ethylmethylamide)hafnium. For example, in the case where an aluminum oxide film is formed using a deposition apparatus employing ALD, two kinds of gases, e.g., H2O as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) are used. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Examples of another material liquid include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). For example, in the case where a silicon oxide film is formed with a deposition apparatus employing ALD, hexachlorodisilane is adsorbed on a surface where a film is to be formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O2or dinitrogen monoxide) are supplied to react with the adsorbate. For example, in the case where a tungsten film is formed using a deposition apparatus employing ALD, a WF6gas and a B2H6gas are sequentially introduced a plurality of times to form an initial tungsten film, and then a WF6gas and an H2gas are introduced at a time, so that a tungsten film is formed. Note that an SiH4gas may be used instead of a B2H6gas. For example, in the case where an oxide semiconductor film, e.g., an In—Ga—Zn—Ox(x>0) film is formed using a deposition apparatus employing ALD, an In(CH3)3gas and an O3gas are sequentially introduced a plurality of times to form an In-0 layer, a Ga(CH3)3gas and an O3gas are introduced at a time to form a Ga—O layer, and then a Zn(CH3)2gas and an O3gas are introduced at a time to form a Zn—O layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing of these gases. Note that although an H2O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O3gas, it is preferable to use an O3gas, which does not contain H. Instead of an In(CH3)3gas, an In(C2H5)3gas may be used. Instead of a Ga(CH3)3gas, a Ga(C2H5)3gas may be used. Furthermore, a Zn(CH3)2gas may be used. This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 6 In this embodiment, configuration examples of a display device using a transistor of one embodiment of the present invention are described. [Configuration Example] FIG.27Ais a top view of the display device of one embodiment of the present invention.FIG.27Bis a circuit diagram illustrating a pixel circuit that can be used in the case where a liquid crystal element is used in a pixel in the display device of one embodiment of the present invention.FIG.27Cis a circuit diagram illustrating a pixel circuit that can be used in the case where an organic EL element is used in a pixel in the display device of one embodiment of the present invention. The transistor in the pixel portion can be formed in accordance with the above embodiment. The transistor can be easily formed as an n-channel transistor, and thus part of a driver circuit that can be formed using an n-channel transistor can be formed over the same substrate as the transistor of the pixel portion. With the use of any of the transistors described in the above embodiment for the pixel portion or the driver circuit in this manner, a highly reliable display device can be provided. FIG.27Aillustrates an example of a top view of an active matrix display device. A pixel portion701, a scan line driver circuit702, a scan line driver circuit703, and a signal line driver circuit704are formed over a substrate700of the display device. In the pixel portion701, a plurality of signal lines extended from the signal line driver circuit704are arranged and a plurality of scan lines extended from the scan line driver circuit702and the scan line driver circuit703are arranged. Note that pixels which include display elements are provided in a matrix in respective regions where the scan lines and the signal lines intersect with each other. The substrate700of the display device is connected to a timing control circuit (also referred to as a controller or a controller IC) through a connection portion such as a flexible printed circuit (FPC). InFIG.27A, the scan line driver circuit702, the scan line driver circuit703, and the signal line driver circuit704are formed over the substrate700where the pixel portion701is formed. Accordingly, the number of components which are provided outside, such as a driver circuit, can be reduced, so that a reduction in cost can be achieved. Furthermore, if the driver circuit is provided outside the substrate700, wirings would need to be extended and the number of wiring connections would increase. When the driver circuit is provided over the substrate700, the number of wiring connections can be reduced. Consequently, an improvement in reliability or yield can be achieved. [Liquid Crystal Display Device] FIG.27Billustrates an example of a circuit configuration of the pixel. Here, a pixel circuit which is applicable to a pixel of a VA liquid crystal display device is illustrated as an example. This pixel circuit can be applied to a structure in which one pixel includes a plurality of pixel electrode layers. The pixel electrode layers are connected to different transistors, and the transistors can be driven with different gate signals. Accordingly, signals applied to individual pixel electrode layers in a multi-domain pixel can be controlled independently. A gate wiring712of a transistor716and a gate wiring713of a transistor717are separated so that different gate signals can be supplied thereto. In contrast, a data line714is shared by the transistors716and717. The transistor described in any of the above embodiments can be used as appropriate as each of the transistors716and717. Thus, a highly reliable liquid crystal display device can be provided. The shapes of a first pixel electrode layer electrically connected to the transistor716and a second pixel electrode layer electrically connected to the transistor717are described. The first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V shape and the second pixel electrode layer is provided so as to surround the first pixel electrode layer. A gate electrode of the transistor716is connected to the gate wiring712, and a gate electrode of the transistor717is connected to the gate wiring713. When different gate signals are supplied to the gate wiring712and the gate wiring713, operation timings of the transistor716and the transistor717can be varied. As a result, alignment of liquid crystals can be controlled. Further, a storage capacitor may be formed using a capacitor wiring710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer. The multi-domain pixel includes a first liquid crystal element718and a second liquid crystal element719. The first liquid crystal element718includes the first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element719includes the second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Note that a pixel circuit of the present invention is not limited to that illustrated inFIG.27B. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be added to the pixel illustrated inFIG.27B. [Organic EL Display Device] FIG.27Cillustrates another example of a circuit configuration of the pixel. Here, a pixel structure of a display device using an organic EL element is shown. In an organic EL element, by application of voltage to a light-emitting element, electrons are injected from one of a pair of electrodes and holes are injected from the other of the pair of electrodes, into a layer containing a light-emitting organic compound; thus, current flows. The electrons and holes are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element. FIG.27Cillustrates an applicable example of a pixel circuit. Here, one pixel includes two n-channel transistors. Note that a metal oxide film of one embodiment of the present invention can be used for channel formation regions of the n-channel transistors. Further, digital time grayscale driving can be employed for the pixel circuit. The configuration of the applicable pixel circuit and operation of a pixel employing digital time grayscale driving are described. A pixel720includes a switching transistor721, a driver transistor722, a light-emitting element724, and a capacitor723. A gate electrode layer of the switching transistor721is connected to a scan line726, a first electrode (one of a source electrode layer and a drain electrode layer) of the switching transistor721is connected to a signal line725, and a second electrode (the other of the source electrode layer and the drain electrode layer) of the switching transistor721is connected to a gate electrode layer of the driver transistor722. The gate electrode layer of the driver transistor722is connected to a power supply line727through the capacitor723, a first electrode of the driver transistor722is connected to the power supply line727, and a second electrode of the driver transistor722is connected to a first electrode (a pixel electrode) of the light-emitting element724. A second electrode of the light-emitting element724corresponds to a common electrode728. The common electrode728is electrically connected to a common potential line formed over the same substrate as the common electrode728. As the switching transistor721and the driver transistor722, the transistor described in any of the other embodiments can be used as appropriate. In this manner, a highly reliable organic EL display device can be provided. The potential of the second electrode (the common electrode728) of the light-emitting element724is set to be a low power supply potential. Note that the low power supply potential is lower than a high power supply potential supplied to the power supply line727. For example, the low power supply potential can be GND, 0V, or the like. The high power supply potential and the low power supply potential are set to be higher than or equal to the forward threshold voltage of the light-emitting element724, and the difference between the potentials is applied to the light-emitting element724, whereby current is supplied to the light-emitting element724, leading to light emission. The forward voltage of the light-emitting element724refers to a voltage at which a desired luminance is obtained, and includes at least a forward threshold voltage. Note that gate capacitance of the driver transistor722may be used as a substitute for the capacitor723, so that the capacitor723can be omitted. The gate capacitance of the driver transistor722may be formed between the channel formation region and the gate electrode layer. Next, a signal input to the driver transistor722is described. In the case of a voltage-input voltage driving method, a video signal for sufficiently turning on or off the driver transistor722is input to the driver transistor722. In order for the driver transistor722to operate in a linear region, voltage higher than the voltage of the power supply line727is applied to the gate electrode layer of the driver transistor722. Note that voltage higher than or equal to voltage which is the sum of power supply line voltage and the threshold voltage Vth of the driver transistor722is applied to the signal line725. In the case of performing analog grayscale driving, a voltage greater than or equal to a voltage which is the sum of the forward voltage of the light-emitting element724and the threshold voltage Vth of the driver transistor722is applied to the gate electrode layer of the driver transistor722. A video signal by which the driver transistor722is operated in a saturation region is input, so that current is supplied to the light-emitting element724. In order for the driver transistor722to operate in a saturation region, the potential of the power supply line727is set higher than the gate potential of the driver transistor722. When an analog video signal is used, it is possible to supply current to the light-emitting element724in accordance with the video signal and perform analog grayscale driving. Note that the configuration of the pixel circuit of the present invention is not limited to that shown inFIG.27C. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated inFIG.27C. In the case where the transistor shown in any of the above embodiments is used for the circuit shown inFIGS.27A to27C, the source electrode (the first electrode) is electrically connected to the low potential side and the drain electrode (the second electrode) is electrically connected to the high potential side. Furthermore, the potential of the first gate electrode may be controlled by a control circuit or the like and the potential described above as an example, e.g., a potential lower than the potential applied to the source electrode, may be input to the second gate electrode through a wiring that is not illustrated. In this specification and the like, for example, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ a variety of modes or can include a variety of elements. The display element, the display device, the light-emitting element, or the light-emitting device includes at least one of an electroluminescence (EL) element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical system (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), MIRASOL (registered trademark), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element including a carbon nanotube, and the like. Other than the above, a display medium whose contrast, luminance, reflectance, transmittance, or the like is changed by electrical or magnetic action may be included. Note that examples of a display device including an EL element include an EL display. Examples of a display device including an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of a display device including a liquid crystal element include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device including electronic ink, Electronic Liquid Powder (registered trademark), or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 7 In this embodiment, a display module using a semiconductor device of one embodiment of the present invention will be described with reference toFIG.28. In a display module8000inFIG.28, a touch panel8004connected to an FPC8003, a display panel8006connected to an FPC8005, a backlight unit8007, a frame8009, a printed board8010, and a battery8011are provided between an upper cover8001and a lower cover8002. Note that the backlight unit8007, the battery8011, the touch panel8004, and the like are not provided in some cases. The semiconductor device of one embodiment of the present invention can be used for the display panel8006, for example. The shapes and sizes of the upper cover8001and the lower cover8002can be changed as appropriate in accordance with the sizes of the touch panel8004and the display panel8006. The touch panel8004can be a resistive touch panel or a capacitive touch panel and may be formed so as to overlap with the display panel8006. A counter substrate (sealing substrate) of the display panel8006can have a touch panel function. A photosensor may be provided in each pixel of the display panel8006to form an optical touch panel. An electrode for a touch sensor may be provided in each pixel of the display panel8006so that a capacitive touch panel is obtained. The backlight unit8007includes a light source8008. The light source8008may be provided at an end portion of the backlight unit8007and a light diffusing plate may be used. The frame8009protects the display panel8006and also functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board8010. The frame8009can function as a radiator plate too. The printed board8010is provided with a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the battery8011provided separately may be used. The battery8011can be omitted in the case of using a commercial power source. The display module8000may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet. This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 8 In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention is described with reference to drawings. [Cross-Sectional Structure] FIG.29Ais a cross-sectional view of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated inFIG.29Aincludes a transistor2200containing a first semiconductor material in a lower portion and a transistor2100containing a second semiconductor material in an upper portion. InFIG.29A, an example is described in which the transistor described in the above embodiment as an example is used as the transistor2100containing the second semiconductor material. A cross-sectional view of the transistors in a channel length direction is on the left side of a dashed-dotted line, and a cross-sectional view of the transistors in a channel width direction is on the right side of the dashed-dotted line. Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (examples of such a semiconductor material include silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor, such as single crystal silicon, can operate at high speed easily. In contrast, a transistor using an oxide semiconductor has low off-state current. The transistor2200may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor may be used in accordance with a circuit. Furthermore, the specific structure of the semiconductor device, such as the material or the structure used for the semiconductor device, is not necessarily limited to those described here except for the use of the transistor of one embodiment of the present invention which uses an oxide semiconductor. FIG.29Aillustrates a structure in which the transistor2100is provided over the transistor2200with an insulating film2201and an insulating film2207provided therebetween. A plurality of wirings2202are provided between the transistor2200and the transistor2100. Furthermore, wirings and electrodes provided over and under the insulating films are electrically connected to each other through a plurality of plugs2203embedded in the insulating films. An insulating film2204covering the transistor2100, a wiring2205over the insulating film2204, and a wiring2206formed by processing a conductive film that is also used for a pair of electrodes of the transistor2100are provided. The stack of the two kinds of transistors reduces the area occupied by the circuit, allowing a plurality of circuits to be highly integrated. Here, in the case where a silicon-based semiconductor material is used for the transistor2200provided in a lower portion, hydrogen in an insulating film provided in the vicinity of the semiconductor film of the transistor2200terminates dangling bonds of silicon; accordingly, the reliability of the transistor2200can be improved. Meanwhile, in the case where an oxide semiconductor is used for the transistor2100provided in an upper portion, hydrogen in an insulating film provided in the vicinity of the semiconductor film of the transistor2100becomes a factor of generating carriers in the oxide semiconductor; thus, the reliability of the transistor2100might be decreased. Therefore, in the case where the transistor2100using an oxide semiconductor is provided over the transistor2200using a silicon-based semiconductor material, it is particularly effective that the insulating film2207having a function of preventing diffusion of hydrogen is provided between the transistors2100and2200. The insulating film2207makes hydrogen remain in the lower portion, thereby improving the reliability of the transistor2200. In addition, since the insulating film2207suppresses diffusion of hydrogen from the lower portion to the upper portion, the reliability of the transistor2100can also be improved. The insulating film2207can be, for example, formed using aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ). Furthermore, a blocking film2208(corresponding to the insulating layer180in the transistors101to103) having a function of preventing diffusion of hydrogen is preferably formed over the transistor2100to cover the transistor2100including an oxide semiconductor film. For the blocking film2208, a material that is similar to that of the insulating film2207can be used, and in particular, an aluminum oxide film is preferably used. The aluminum oxide film has a high shielding (blocking) effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Thus, by using the aluminum oxide film as the blocking film2208covering the transistor2100, release of oxygen from the oxide semiconductor film included in the transistor2100can be prevented and entry of water and hydrogen into the oxide semiconductor film can be prevented. Note that the transistor2200can be a transistor of various types without being limited to a planar type transistor. For example, the transistor2200can be a fin-type transistor, a tri-gate transistor, or the like. An example of a cross-sectional view in this case is shown inFIG.29D. An insulating film2212is provided over a semiconductor substrate2211. The semiconductor substrate2211includes a projecting portion with a thin tip (also referred to a fin). Note that an insulating film may be provided over the projecting portion. The insulating film functions as a mask for preventing the semiconductor substrate2211from being etched when the projecting portion is formed. The projecting portion does not necessarily have the thin tip; a projecting portion with a cuboid-like projecting portion and a projecting portion with a thick tip are permitted, for example. A gate insulating film2214is provided over the projecting portion of the semiconductor substrate2211, and a gate electrode2213is provided over the gate insulating film2214. Source and drain regions2215are formed in the semiconductor substrate2211. Note that here is shown an example in which the semiconductor substrate2211includes the projecting portion; however, a semiconductor device of one embodiment of the present invention is not limited thereto. For example, a semiconductor region having a projecting portion may be formed by processing an SOI substrate. [Circuit Configuration Example] In the above structure, electrodes of the transistor2100and the transistor2200can be connected in a variety of ways; thus, a variety of circuits can be formed. Examples of circuit configurations which can be achieved by using a semiconductor device of one embodiment of the present invention are shown below. [CMOS Circuit] A circuit diagram inFIG.29Bshows a configuration of a so-called CMOS circuit in which the p-channel transistor2200and the n-channel transistor2100are connected to each other in series and in which gates of them are connected to each other. [Analog Switch] A circuit diagram inFIG.29Cshows a configuration in which sources of the transistors2100and2200are connected to each other and drains of the transistors2100and2200are connected to each other. With such a configuration, the transistors can function as a so-called analog switch. [Memory Device Example] An example of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown inFIGS.30A to30C. The semiconductor device illustrated inFIG.30Aincludes a transistor3200using a first semiconductor material, a transistor3300using a second semiconductor material, and a capacitor3400. Note that any of the above-described transistors can be used as the transistor3300. FIG.30Bis a cross-sectional view of the semiconductor device illustrated inFIG.30A. The semiconductor device in the cross-sectional view has a structure in which the transistor3300is provided with a back gate; however, a structure without a back gate may be employed. The transistor3300is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor3300is low, stored data can be retained for a long period. In other words, power consumption can be sufficiently reduced because a semiconductor memory device in which refresh operation is unnecessary or the frequency of refresh operation is extremely low can be provided. InFIG.30A, a wiring3001is electrically connected to a source electrode of the transistor3200. A wiring3002is electrically connected to a drain electrode of the transistor3200. A wiring3003is electrically connected to one of a source electrode and a drain electrode of the transistor3300. A wiring3004is electrically connected to a gate electrode of the transistor3300. A gate electrode of the transistor3200is electrically connected to the other of the source electrode and the drain electrode of the transistor3300and one electrode of the capacitor3400. A wiring3005is electrically connected to the other electrode of the capacitor3400. The semiconductor device inFIG.30Ahas a feature that the potential of the gate electrode of the transistor3200can be retained, and thus enables writing, retaining, and reading of data as follows. Writing and retaining of data are described. First, the potential of the fourth wiring3004is set to a potential at which the transistor3300is turned on, so that the transistor3300is turned on. Accordingly, the potential of the wiring3003is supplied to the gate electrode of the transistor3200and the capacitor3400. That is, a predetermined charge is supplied to the gate electrode of the transistor3200(writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring3004is set to a potential at which the transistor3300is turned off, so that the transistor3300is turned off. Thus, the charge supplied to the gate electrode of the transistor3200is held (retaining). Since the off-state current of the transistor3300is extremely low, the charge of the gate of the transistor3200is retained for a long time. Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the wiring3005while a predetermined potential (a constant potential) is supplied to the wiring3001, whereby the potential of the wiring3002varies depending on the amount of charge retained in the gate of the transistor3200. This is because in the case of using an n-channel transistor as the transistor3200, an apparent threshold voltage Vth_Hat the time when the high-level charge is given to the gate electrode of the transistor3200is lower than an apparent threshold voltage Vth_Lat the time when the low-level charge is given to the gate electrode of the transistor3200. Here, an apparent threshold voltage refers to the potential of the wiring3005which is needed to turn on the transistor3200. Thus, the potential of the wiring3005is set to a potential V0which is between Vth_Hand Vth_L, whereby charge supplied to the gate of the transistor3200can be determined. For example, in the case where the high-level charge is supplied to the gate electrode of the transistor3200in writing and the potential of the wiring3005is V0(>Vth_H), the transistor3200is turned on. In the case where the low-level charge is supplied to the gate electrode of the transistor3200in writing, even when the potential of the wiring3005is V0(<Vth_L), the transistor3200remains off. Thus, the data retained in the gate electrode of the transistor3200can be read by determining the potential of the wiring3002. Note that in the case where memory cells are arrayed to be used, it is necessary that only data of a desired memory cell be able to be read. In the case where such reading is not performed, the wiring3005may be supplied with a potential at which the transistor3200is turned off regardless of the state of the gate, that is, a potential lower than Vth H. Alternatively, the wiring3005may be supplied with a potential at which the transistor3200is turned on regardless of the state of the gate, that is, a potential higher than Vth_L. The semiconductor device illustrated inFIG.30Cis different from the semiconductor device illustrated inFIG.30Ain that the transistor3200is not provided. Also in this case, writing and retaining operation of data can be performed in a manner similar to the semiconductor device illustrated inFIG.30A. Next, reading of data is described. When the transistor3300is turned on, the wiring3003which is in a floating state and the capacitor3400are electrically connected to each other, and the charge is redistributed between the wiring3003and the capacitor3400. As a result, the potential of the wiring3003is changed. The amount of change in the potential of the wiring3003varies depending on the potential of a first terminal of the capacitor3400(or the charge accumulated in the capacitor3400). For example, the potential of the wiring3003after the charge redistribution is (CB×VB0+C×V)/(CB+C), where V is the potential of the first terminal of the capacitor3400, C is the capacitance of the capacitor3400, CBis the capacitance component of the wiring3003, and VB0is the potential of the wiring3003before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the first terminal of the capacitor3400is V1and V0(V1>V0), the potential of the wiring3003in the case of retaining the potential V1(=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the wiring3003in the case of retaining the potential V0(=(CB×VB0+C×V0)/(CB+C)). Then, by comparing the potential of the wiring3003with a predetermined potential, data can be read. In this case, a transistor including the first semiconductor material may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor material may be stacked over the driver circuit as the transistor3300. When including a transistor in which a channel formation region is formed using an oxide semiconductor and which has an extremely low off-state current, the semiconductor device described in this embodiment can retain stored data for an extremely long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed). Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing data and there is no problem of deterioration of elements. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of a gate insulating film hardly occurs. That is, the semiconductor device of the disclosed invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the state of the transistor (on or off), whereby high-speed operation can be easily achieved. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 9 In this embodiment, an RF tag that includes the transistor described in the above embodiments or the memory device described in the above embodiment is described with reference toFIG.31. The RF tag of this embodiment includes a memory circuit, stores necessary data in the memory circuit, and transmits and receives data to/from the outside by using contactless means, for example, wireless communication. With these features, the RF tag can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. Note that the RF tag is required to have extremely high reliability in order to be used for this purpose. A configuration of the RF tag will be described with reference toFIG.31.FIG.31is a block diagram illustrating a configuration example of an RF tag. As shown inFIG.31, an RF tag800includes an antenna804which receives a radio signal803that is transmitted from an antenna802connected to a communication device801(also referred to as an interrogator, a reader/writer, or the like). The RF tag800includes a rectifier circuit805, a constant voltage circuit806, a demodulation circuit807, a modulation circuit808, a logic circuit809, a memory circuit810, and a ROM811. A transistor having a rectifying function included in the demodulation circuit807may be formed using a material which enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress the phenomenon of a rectifying function becoming weaker due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag800described in this embodiment. Next, the structure of each circuit will be described. The antenna804exchanges the radio signal803with the antenna802which is connected to the communication device801. The rectifier circuit805generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna804and smoothing of the rectified signal with a capacitor provided in a later stage in the rectifier circuit805. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit805. The limiter circuit controls electric power so that electric power which is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high. The constant voltage circuit806generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit806may include a reset signal generation circuit. The reset signal generation circuit is a circuit which generates a reset signal of the logic circuit809by utilizing rise of the stable power supply voltage. The demodulation circuit807demodulates the input alternating signal by envelope detection and generates the demodulated signal. Further, the modulation circuit808performs modulation in accordance with data to be output from the antenna804. The logic circuit809analyzes and processes the demodulated signal. The memory circuit810holds the input data and includes a row decoder, a column decoder, a memory region, and the like. Further, the ROM811stores an identification number (ID) or the like and outputs it in accordance with processing. Note that the decision whether each circuit described above is provided or not can be made as appropriate as needed. Here, the memory device described in the above embodiment can be used as the memory circuit810. Since the memory circuit of one embodiment of the present invention can retain data even when not powered, the memory circuit can be favorably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention needs power (voltage) needed for data writing significantly lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. In addition, it is possible to suppress malfunction or incorrect writing which is caused by power shortage in data writing. Since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM811so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, it is possible to put identification numbers to only good products to be shipped. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 10 In this embodiment, a CPU that includes the memory device described in the above embodiment is described. FIG.32is a block diagram illustrating a configuration example of a CPU at least partly including any of the transistors described in the above embodiments as a component. The CPU illustrated inFIG.32includes, over a substrate1190, an arithmetic logic unit (ALU)1191, an ALU controller1192, an instruction decoder1193, an interrupt controller1194, a timing controller1195, a register1196, a register controller1197, a bus interface1198(BUS I/F), a rewritable ROM1199, and a ROM interface (ROM I/F)1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate1190. The ROM1199and the ROM interface1189may be provided over a separate chip. Needless to say, the CPU inFIG.32is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated inFIG.32or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example. An instruction that is input to the CPU through the bus interface1198is input to the instruction decoder1193and decoded therein, and then, input to the ALU controller1192, the interrupt controller1194, the register controller1197, and the timing controller1195. The ALU controller1192, the interrupt controller1194, the register controller1197, and the timing controller1195conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller1192generates signals for controlling the operation of the ALU1191. While the CPU is executing a program, the interrupt controller1194judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller1197generates an address of the register1196, and reads/writes data from/to the register1196in accordance with the state of the CPU. The timing controller1195generates signals for controlling operation timings of the ALU1191, the ALU controller1192, the instruction decoder1193, the interrupt controller1194, and the register controller1197. For example, the timing controller1195includes an internal clock generator for generating an internal clock signal CLK2based on a reference clock signal CLK1, and supplies the internal clock signal CLK2to the above circuits. In the CPU illustrated inFIG.32, a memory cell is provided in the register1196. For the memory cell of the register1196, any of the transistors described in the above embodiments can be used. In the CPU illustrated inFIG.32, the register controller1197selects operation of retaining data in the register1196in accordance with an instruction from the ALU1191. That is, the register controller1197selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register1196can be stopped. FIG.33is an example of a circuit diagram of a memory element that can be used as the register1196. A memory element1200includes a circuit1201in which stored data is volatile when power supply is stopped, a circuit1202in which stored data is nonvolatile even when power supply is stopped, a switch1203, a switch1204, a logic element1206, a capacitor1207, and a circuit1220having a selecting function. The circuit1202includes a capacitor1208, a transistor1209, and a transistor1210. Note that the memory element1200may further include another element such as a diode, a resistor, or an inductor, as needed. Here, the memory device described in the above embodiment can be used as the circuit1202. When supply of a power supply voltage to the memory element1200is stopped, a ground potential (0 V) or a potential at which the transistor1209in the circuit1202is turned off continues to be input to a gate of the transistor1209. For example, the first gate of the transistor1209is grounded through a load such as a resistor. Shown here is an example in which the switch1203is a transistor1213having one conductivity type (e.g., an n-channel transistor) and the switch1204is a transistor1214having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch1203corresponds to one of a source and a drain of the transistor1213, a second terminal of the switch1203corresponds to the other of the source and the drain of the transistor1213, and conduction or non-conduction between the first terminal and the second terminal of the switch1203(i.e., the on/off state of the transistor1213) is selected by a control signal RD input to a gate of the transistor1213. A first terminal of the switch1204corresponds to one of a source and a drain of the transistor1214, a second terminal of the switch1204corresponds to the other of the source and the drain of the transistor1214, and conduction or non-conduction between the first terminal and the second terminal of the switch1204(i.e., the on/off state of the transistor1214) is selected by the control signal RD input to a gate of the transistor1214. One of a source and a drain of the transistor1209is electrically connected to one of a pair of electrodes of the capacitor1208and a gate of the transistor1210. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor1210is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch1203(the one of the source and the drain of the transistor1213). The second terminal of the switch1203(the other of the source and the drain of the transistor1213) is electrically connected to the first terminal of the switch1204(the one of the source and the drain of the transistor1214). The second terminal of the switch1204(the other of the source and the drain of the transistor1214) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch1203(the other of the source and the drain of the transistor1213), the first terminal of the switch1204(the one of the source and the drain of the transistor1214), an input terminal of the logic element1206, and one of a pair of electrodes of the capacitor1207are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor1207can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor1207can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor1207is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor1208can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor1208can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor1208is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The capacitor1207and the capacitor1208are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized. A control signal WE is input to the first gate (first gate electrode) of the transistor1209. As for each of the switch1203and the switch1204, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state. Note that the transistor1209inFIG.33has a structure with a second gate (second gate electrode; back gate). The control signal WE can be input to the first gate and the control signal WE2can be input to the second gate. The control signal WE2is a signal having a constant potential. As the constant potential, for example, a ground potential GND or a potential lower than a source potential of the transistor1209is selected. The control signal WE2is a potential signal for controlling the threshold voltage of the transistor1209, and/cut of the transistor1209can be further reduced. The control signal WE2may be a signal having the same potential as that of the control signal WE. Note that as the transistor1209, a transistor without a second gate may be used. A signal corresponding to data retained in the circuit1201is input to the other of the source and the drain of the transistor1209.FIG.33illustrates an example in which a signal output from the circuit1201is input to the other of the source and the drain of the transistor1209. The logic value of a signal output from the second terminal of the switch1203(the other of the source and the drain of the transistor1213) is inverted by the logic element1206, and the inverted signal is input to the circuit1201through the circuit1220. In the example ofFIG.33, a signal output from the second terminal of the switch1203(the other of the source and the drain of the transistor1213) is input to the circuit1201through the logic element1206and the circuit1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch1203(the other of the source and the drain of the transistor1213) may be input to the circuit1201without its logic value being inverted. For example, in the case where the circuit1201includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch1203(the other of the source and the drain of the transistor1213) can be input to the node. InFIG.33, the transistors included in the memory element1200except for the transistor1209can each be a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate1190. For example, the transistor can be a transistor whose channel is formed in a silicon layer or a silicon substrate. Alternatively, all the transistors in the memory element1200may be a transistor in which a channel is formed in an oxide semiconductor layer. Further alternatively, in the memory element1200, a transistor in which a channel is formed in an oxide semiconductor layer can be included besides the transistor1209, and a transistor in which a channel is formed in a layer or the substrate1190including a semiconductor other than an oxide semiconductor can be used for the rest of the transistors. As the circuit1201inFIG.33, for example, a flip-flop circuit can be used. As the logic element1206, for example, an inverter or a clocked inverter can be used. In a period during which the memory element1200is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit1201by the capacitor1208which is provided in the circuit1202. The off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor1209, a signal held in the capacitor1208is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element1200. The memory element1200can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped. Since the above-described memory element performs pre-charge operation with the switch1203and the switch1204, the time required for the circuit1201to retain original data again after the supply of the power supply voltage is restarted can be shortened. In the circuit1202, a signal retained by the capacitor1208is input to the gate of the transistor1210. Therefore, after supply of the power supply voltage to the memory element1200is restarted, the signal retained by the capacitor1208can be converted into the one corresponding to the state (the on state or the off state) of the transistor1210to be read from the circuit1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor1208varies to some degree. By applying the above-described memory element1200to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption. Although the memory element1200is used in a CPU in this embodiment, the memory element1200can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency identification (RF-ID). This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 11 In this embodiment, modification examples of the transistor of one embodiment of the present invention will be described with reference toFIGS.34Ato34F,FIGS.35A to35F,FIGS.36A to36E,FIGS.37A to37C, andFIGS.38A to38D. Transistors illustrated inFIGS.34A to34Feach include an oxide semiconductor layer755over an insulating layer753over a substrate751, an insulating layer757in contact with the oxide semiconductor layer755, and a conductive layer759in contract with the insulating layer757and overlapping with the oxide semiconductor layer755. The insulating layer757functions a gate insulating layer, and the conductive layer759functions as a gate electrode layer. The transistors each include a nitride insulating layer765that is in contact with the oxide semiconductor layer755and an insulating layer767that is in contact with the nitride insulating layer765. Conductive layers768and769that are in contact with the oxide semiconductor layer755through openings in the nitride insulating layer765and the insulating layer767are also included. Note that the conductive layers768and769function as a source electrode layer and a drain electrode layer. In the transistor illustrated inFIG.34A, the oxide semiconductor layer755includes a channel region755aformed in a region overlapping with the conductive layer759and low-resistance regions755band755cbetween which the channel region755ais provided and which contain an impurity element. The conductive layers768and769are in contact with the low-resistance regions755band755c, respectively. Note that the conductive layers768and769function as wirings. Alternatively, as in the transistor illustrated inFIG.34B, the oxide semiconductor layer755may have a structure in which an impurity element is not added to regions755dand755ein contact with the conductive layers768and769. In this case, regions containing an impurity element, i.e., the low-resistance regions755band755care provided. The low-resistance region (755bor755c) is provided between the channel region755aand the region (755dor755e) in contact with the conductive film (768or769). The regions755dand755ehave conductivity when voltage is applied to the conductive layers768and769; thus, the regions755dand755efunction as a source region and a drain region. Note that the transistor illustrated inFIG.34Bcan be formed in such a manner that the conductive layers768and769are formed and then an impurity element is added to the oxide semiconductor layer using the conductive layer759and the conductive layers768and769as masks. An end portion of the conductive layer759may have a tapered shape. That is, an angle θ1formed between a surface where the insulating layer757and the conductive layer759are in contact with each other and a side surface of the conductive layer759may be less than 90°, greater than or equal to 30° and less than or equal to 85°, greater than or equal to 45° and less than or equal to 85°, or greater than or equal to 60° and less than or equal to 85°. When the angle θ1is less than 90°, greater than or equal to and less than or equal to 85°, greater than or equal to 45° and less than or equal to or greater than or equal to 60° and less than or equal to 85°, the coverage of the side surfaces of the insulating layer757and the conductive layer759with the nitride insulating layer765can be improved. Next, modification examples of the low-resistance regions755band755care described.FIGS.34C to34Fare each an enlarged view of the vicinity of the oxide semiconductor layer755illustrated inFIG.34A. The channel length L indicates a distance between a pair of low-resistance regions. As illustrated inFIG.34C, in a cross-sectional view in the channel length direction, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759with the insulating layer757provided therebetween. That is, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759, when seen from the above. Alternatively, as illustrated inFIG.34D, in a cross-sectional view in the channel length direction, the channel region755ahas a region that does not overlap with the conductive layer759. The region functions as an offset region. The length of the offset region in the channel length direction is referred to as Loff. Note that in the case where a plurality of offset regions are provided, Loffindicates the length of one offset region. Loffis included in the channel length L. Note that Loffis smaller than %, smaller than 10%, smaller than 5%, or smaller than 2% of the channel length L. Alternatively, as illustrated inFIG.34E, in a cross-sectional view in the channel length direction, the low-resistance regions755band755ceach have a region overlapping with the conductive layer759with the insulating layer757provided therebetween. This region functions as an overlap region. The overlap region in the channel length direction is referred to as Lov. Lovis smaller than 20%, smaller than 10% %, smaller than 5%, or smaller than 2% of the channel length L. Alternatively, as illustrated inFIG.34F, in a cross-sectional view in the channel length direction, a low-resistance region755fbetween the channel region755aand the low-resistance region755b, and a low-resistance region755gbetween the channel region755aand the low-resistance region755care provided. The low-resistance regions755fand755ghave lower impurity element concentrations and higher resistivity than the low-resistance regions755band755c. Although the low-resistance regions755fand755goverlap with the insulating layer757here, they may overlap with the insulating layer757and the conductive layer759. Note that inFIGS.34C to34F, the transistor illustrated inFIG.34Ais described; however, the transistor illustrated inFIG.34Bcan employ any of the structures inFIGS.34C to34Fas appropriate. In the transistor illustrated inFIG.35A, an end portion of the insulating layer757is positioned on an outer side than the end portion of the conductive layer759. In other words, the insulating layer757has such a shape that the end portion extends beyond the end portion of the conductive layer759. The nitride insulating layer765can be distanced from the channel region755a; thus, nitrogen, hydrogen, and the like contained in the nitride insulating layer765can be prevented from entering the channel region755a. In the transistor illustrated inFIG.35B, the insulating layer757and the conductive layer759each have a tapered shape, and the angles of the tapered shapes are different from each other. In other words, the angle θ1formed between a surface where the insulating layer757and the conductive layer759are in contact with each other and a side surface of the conductive layer759is different from an angle θ2formed between a surface where the oxide semiconductor layer755and the insulating layer757are in contact with each other and a side surface of the insulating layer757. The angle θ2may be less than 90°, greater than or equal to 30° and less than or equal to or greater than or equal to 45° and less than or equal to 70°. For example, when the angle θ2is smaller than the angle θ1, the coverage with the nitride insulating layer765is improved. In contrast, when the angle θ2is larger than the angle θ1, the nitride insulating layer765can be distanced from the channel region755a; thus, nitrogen, hydrogen, and the like contained in the nitride insulating layer765can be prevented from entering the channel region755a. Next, modification examples of the low-resistance regions755band755care described with reference toFIGS.35C to35F.FIGS.35C to35Fare each an enlarged view of the vicinity of the oxide semiconductor layer755illustrated inFIG.35A. As illustrated inFIG.35C, in a cross-sectional view in the channel length direction, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759with the insulating layer757provided therebetween. That is, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759, when seen from the above. Alternatively, as illustrated inFIG.35D, in a cross-sectional view in the channel length direction, the channel region755ahas a region that does not overlap with the conductive layer759. The region functions as an offset region. That is, when seen from the above, the end portions of the low-resistance regions755band755care aligned or substantially aligned with the end portions of the insulating layer757and do not overlap with the end portions of the conductive layer759. Alternatively, as illustrated inFIG.35E, in a cross-sectional view in the channel length direction, the low-resistance regions755band755ceach have a region overlapping with the conductive layer759with the insulating layer757provided therebetween. The region is referred to as an overlap region. That is, when seen from the above, the end portions of the low-resistance regions755band755coverlap with the conductive layer759. Alternatively, as illustrated inFIG.35F, in a cross-sectional view in the channel length direction, the low-resistance region755fbetween the channel region755aand the low-resistance region755b, and the low-resistance region755gbetween the channel region755aand the low-resistance region755care provided. The low-resistance regions755fand755ghave lower impurity element concentrations and higher resistivity than the low-resistance regions755band755c. Although the low-resistance regions755fand755goverlap with the insulating layer757here, they may overlap with the insulating layer757and the conductive layer759. Note that inFIGS.35C to35F, the transistor illustrated inFIG.35Ais described; however, the transistor illustrated inFIG.35Bcan employ any of the structures inFIGS.35C to35Fas appropriate. In the transistor illustrated inFIG.36A, the conductive layer759has a stacked-layer structure including a conductive layer759ain contact with the insulating layer757and a conductive layer759bin contact with the conductive layer759a. An end portion of the conductive layer759ais positioned on an outer side than an end portion of the conductive layer759b. In other words, the conductive layer759ahas such a shape that the end portion extends beyond the end portion of the conductive layer759b. Next, modification examples of the low-resistance regions755band755care described.FIGS.36B to36EandFIGS.37A and37Bare each an enlarged view of the vicinity of the oxide semiconductor layer755illustrated inFIG.36A. As illustrated inFIG.36B, in a cross-sectional view in the channel length direction, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759aincluded in the conductive layer759with the insulating layer757provided therebetween. That is, the boundaries between the channel region755aand the low-resistance regions755band755care aligned or substantially aligned with the end portions of the conductive layer759, when seen from the above. Alternatively, as illustrated inFIG.36C, in a cross-sectional view in the channel length direction, the channel region755ahas a region that does not overlap with the conductive layer759. The region functions as an offset region. That is, when seen from the above, the end portions of the low-resistance regions755band755cdo not overlap with the end portions of the conductive layer759. As illustrated inFIG.36D, in a cross-sectional view in the channel length direction, the low-resistance regions755band755ceach have a region overlapping with the conductive layer759, specifically the conductive layer759a. The region is referred to as an overlap region. That is, when seen from the above, the end portions of the low-resistance regions755band755coverlap with the conductive layer759a. Alternatively, as illustrated inFIG.36E, in a cross-sectional view in the channel length direction, the low-resistance region755fbetween the channel region755aand the low-resistance region755b, and the low-resistance region755gbetween the channel region755aand the low-resistance region755care provided. An impurity element is added to the low-resistance regions755fand755gthrough the conductive layer759a; thus, the low-resistance regions755fand755ghave lower concentrations of an impurity element and higher resistivity than the low-resistance regions755band755c. Although the low-resistance regions755fand755goverlap with the conductive layer759ahere, they may overlap with the conductive layer759aand the conductive layer759b. As illustrated inFIG.37A, in the cross-sectional view in the channel length direction, the end portion of the conductive layer759amay be positioned on an outer side than the end portion of the conductive layer759band the conductive layer759amay have a tapered shape. That is, an angle between a surface where the insulating layer757and the conductive layer759aare in contact with each other and a side surface of the conductive layer759amay be less than 90°, greater than or equal to 5° and less than or equal to 45°, or greater than or equal to 5° and less than or equal to 30°. Furthermore, the end portion of the insulating layer757may be positioned on an outer side than the end portion of the conductive layer759a. Furthermore, a side surface of the insulating layer757may be curved. The insulating layer757may have a tapered shape. That is, an angle formed between a surface where the oxide semiconductor layer755and the insulating layer757are in contact with each other and a side surface of the insulating layer757may be less than 90°, preferably greater than or equal to 30° and less than 90°. The oxide semiconductor layer755illustrated inFIG.37Aincludes the channel region755a, the low-resistance regions755fand755gbetween which the channel region755ais provided, low-resistance regions755hand755ibetween which the low-resistance regions755fand755gare provided, and the low-resistance regions755band755cbetween which the low-resistance regions755hand755iare provided. An impurity element is added to the low-resistance regions755f,755g,755h, and755ithrough the insulating layer757and the conductive layer759a; thus, the low-resistance regions755f,755g,755h, and755ihave lower concentrations of an impurity element and higher resistivity than the low-resistance regions755band755c. The oxide semiconductor layer755illustrated inFIG.37Bincludes the channel region755a, the low-resistance regions755hand755ibetween which the channel region755ais provided, and the low-resistance regions755band755cbetween which the low-resistance regions755hand755iare provided. An impurity element is added to the low-resistance regions755hand755ithrough the insulating layer757; thus, the low-resistance regions755hand755ihave lower concentrations of an impurity element and higher resistivity than the low-resistance regions755band755c. Note that in the channel length direction, the channel region755aoverlaps with the conductive layer759b. The low-resistance regions755fand755goverlap with the conductive layer759aprojecting outside the conductive layer759b. The low-resistance regions755hand755ioverlap with the insulating layer757projecting outside the conductive layer759a. The low-resistance regions755band755care positioned on outer sides than the insulating layer757. When the oxide semiconductor layer755includes the low-resistance regions755f,755g,755h, and755ihaving lower impurity element concentrations and higher resistivity than the low-resistance regions755band755cas illustrated inFIG.36EandFIGS.37A and37B, the electric field of the drain region can be relaxed. Thus, a shift of the threshold voltage of the transistor, can be prevented. FIG.37Cis an enlarged view of the vicinity of the end portion of the conductive layer759in the channel width direction of the transistors illustrated inFIGS.37A and37B. The transistor shown inFIG.38Aincludes the oxide semiconductor layer755including the channel region755aand the low-resistance regions755band755c. The low-resistance regions755band755ceach include a region with a thickness smaller than that of the channel region755a. Typically, the low-resistance regions755band755ceach include a region with a thickness smaller than that of the channel region755aby 0.1 nm or more and 5 nm or less. In the transistor shown inFIG.38B, at least one of the insulating layers753and757, which are in contact with the oxide semiconductor layer755, has a multilayer structure. For example, the insulating layer753includes an insulating layer753aand an insulating layer753bin contact with the insulating layer753aand the oxide semiconductor layer755. For example, the insulating layer757includes an insulating layer757ain contact with the oxide semiconductor layer755and an insulating layer757bin contact with the insulating layer757a. The insulating layers753band757acan be formed using an oxide insulating film with a low density of states of a nitrogen oxide between valence band maximum (Ev_os) and a conduction band minimum (Ec_os). As the oxide insulating film with a low density of states of a nitrogen oxide between Ev_osand Ec_os, a silicon oxynitride film that releases less nitrogen oxide, an aluminum oxynitride film that releases less nitrogen oxide, or the like can be used. The average thickness of each of the insulating layers753band757ais greater than or equal to 0.1 nm and less than or equal to 50 nm, or greater than or equal to 0.5 nm and less than or equal to 10 nm. Note that a silicon oxynitride film that releases less nitrogen oxide is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide in thermal desorption spectroscopy (TDS) analysis; the amount of released ammonia is typically greater than or equal to 1×1018molecules/cm3and less than or equal to 5×1019molecules/cm3. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of a film becomes higher than or equal to 50° C. and lower than or equal to 650° C., preferably higher than or equal to 50° C. and lower than or equal to 550° C. The insulating layers753aand757bcan be formed using an oxide insulating film that releases oxygen by being heated. Note that the average thickness of each of the insulating layers753aand757bis greater than or equal to 5 nm and less than or equal to 1000 nm, or greater than or equal to 10 nm and less than or equal to 500 nm. Typical examples of the oxide insulating film that releases oxygen by being heated include a silicon oxynitride film and an aluminum oxynitride film. Nitrogen oxide (NOx; x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2or NO, forms states in the insulating layer753, the insulating layer757, and the like. The states are positioned in the energy gap of the oxide semiconductor layer755. Therefore, when nitrogen oxide is diffused to the interfaces between the insulating layers753and757and the oxide semiconductor layer755, electrons might be trapped by the states on the insulating layer753side and the insulating layer757side. As a result, the trapped electrons remain in the vicinity of the interfaces between the insulating layers753and757and the oxide semiconductor layer755; thus, the threshold voltage of the transistor is shifted in the positive direction. Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating layers753aand757breacts with ammonia contained in the insulating layers753aand757bin heat treatment, nitrogen oxide contained in the insulating layers753aand757bis reduced. Therefore, electrons are hardly trapped at the interfaces between the insulating layers753and757and the oxide semiconductor layer755. By using the oxide insulating film with a low density of states of an nitrogen oxide between Ev_osand Ec_osas the insulating layers753band757a, a shift in the threshold voltage of the transistor can be reduced, which leads to a smaller change in electrical characteristics of the transistor. Note that in an ESR spectrum at 100 K or lower of the insulating layers753band757a, by heat treatment in a manufacturing process of the transistor, typically heat treatment at a temperature higher than or equal to 300° C. and lower than the strain point of the substrate, a first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, a second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and a third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 are observed. The split width of the first and second signals and the split width of the second and third signals that are obtained by ESR measurement using an X-band are each approximately 5 mT. The sum of the spin densities of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is lower than 1×1018spins/cm3, typically higher than or equal to 1×1017spins/cm3and lower than 1×1018spins/cm3. In the ESR spectrum at 100 K or lower, the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 correspond to signals attributed to nitrogen dioxide (NOx; x is greater than or equal to 0 and smaller than or equal to 2, preferably greater than or equal to 1 and smaller than or equal to 2). Typical examples of nitrogen oxide include nitrogen monoxide and nitrogen dioxide. In other words, the lower the total spin density of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is, the lower the content of nitrogen oxide in the oxide insulating layer is. After heat treatment in a manufacturing process of the transistor, typically heat treatment at a temperature higher than or equal to 300° C. and lower than the strain point of the substrate, the oxide insulating layer containing nitrogen and having a small amount of defects has a nitrogen concentration of 6×1020atoms/cm3or lower by secondary ion mass spectrometry (SIMS). By forming an oxide insulating layer containing nitrogen and having a small amount of defects by a plasma CVD method using silane and dinitrogen monoxide at a substrate temperature higher than or equal to 220° C., higher than or equal to 280° C., or higher than or equal to 350° C., a dense and hard film can be formed. The transistor shown inFIG.38Cincludes an insulating layer775between the nitride insulating layer765and the oxide semiconductor layer755, the insulating layer757, and the conductive layer759. The insulating layer775can be formed using the oxide insulating layer containing nitrogen and having a small amount of defects for the insulating layers753band757ashown inFIG.38B. Alternatively, in a cross-sectional view in the channel length direction, the low-resistance region755fbetween the channel region755aand the low-resistance region755b, and the low-resistance region755gbetween the channel region755aand the low-resistance region755care provided. The low-resistance regions755fand755ghave lower impurity element concentrations and higher resistivity than the low-resistance regions755band755c. Although the low-resistance regions755fand755goverlap with the insulating layer775that is in contact with side surfaces of the insulating layer757and the conductive layer759. Note that the low-resistance regions755fand755gmay overlap with the insulating layer757and the conductive layer759. Note that in the transistor illustrated inFIG.38D, the insulating layer757is in contact with the channel region755aof the oxide semiconductor layer755and is in contact with the low-resistance regions755band755c. Furthermore, in the insulating layer757, the thicknesses of regions in contact with the low-resistance regions755band755care smaller than the thickness of a region in contact with the channel region755a; the average thickness of the insulating layer757is typically greater than or equal to 0.1 nm and less than or equal to 50 nm, or greater than or equal to 0.5 nm and less than or equal to 10 nm. As a result, the impurity element can be added to the oxide semiconductor layer755through the insulating layer757, and in addition, hydrogen contained in the nitride insulating layer765can be moved to the oxide semiconductor layer755through the insulating layer757. Thus, the low-resistance regions755band755ccan be formed. Furthermore, the insulating layer753has a multilayer structure of the insulating layers753aand753b; for example, the insulating layer753ais formed using an oxide insulating layer that releases oxygen by being heated, and the insulating layer753bis formed using an oxide insulating layer containing nitrogen and having a small amount of defects. Furthermore, the insulating layer757is formed using an oxide insulating layer containing nitrogen and having a small amount of defects. That is, the oxide semiconductor layer755can be covered with the oxide insulating layer containing nitrogen and having a small amount of defects. As a result, the carrier trap at the interfaces between the oxide semiconductor layer755and the insulating layers753band757acan be reduced while oxygen contained in the insulating layer753ais moved to the oxide semiconductor layer755by heat treatment to reduce oxygen vacancies contained in the channel region755aof the oxide semiconductor layer755. Consequently, a shift in the threshold voltage of the transistor can be reduced, which leads to a smaller variation in electrical characteristics of the transistor. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 12 A band structure of the transistor of one embodiment of the present invention in an arbitrary cross section will be described. FIG.39Ais a cross-sectional view of a transistor according to one embodiment of the present invention. The transistor illustrated inFIG.39Aincludes an insulating layer401over a substrate400, a conductive layer404aover the insulating layer401, a conductive layer404bover the conductive layer404a, an insulating layer402aover the insulating layer401, the conductive layer404a, and the conductive layer404b, an insulating layer402bover the insulating layer402a, a semiconductor layer406aover the insulating layer402b, a semiconductor layer406bover the semiconductor layer406a, an insulating layer412over the semiconductor layer406b, a conductive layer414aover the insulating layer412, a conductive layer414bover the conductive layer414a, an insulating layer408over the insulating layer402b, the semiconductor layer406a, the semiconductor layer406b, the insulating layer412, the conductive layer414a, and the conductive layer414b, an insulating layer418over the insulating layer408, a conductive layer416a1and a conductive layer416b1over the insulating layer418, a conductive layer416a2and a conductive layer416b2respectively over the conductive layer416a1and the conductive layer416b1, and an insulating layer428over the insulating layer418, the conductive layer416a2, and the conductive layer416b2. In some cases, the insulating layer401has a function of suppressing entry of impurities to a channel formation region of the transistor. In the case where the conductive layer404bor the like includes an impurity for the semiconductor layer406aor406b, such as copper, for example, the insulating layer401has a function of blocking copper or the like in some cases. The stacked conductive layers404aand404bare collectively referred to as a conductive layer404. The conductive layer404has a function of a gate electrode of the transistor in some cases. The conductive layer404has a function of shielding the channel formation region of the transistor from light in some cases. The insulating layers402aand402bare collectively referred to as an insulating layer402. The insulating layer402has a function of a gate insulating layer of the transistor in some cases. Furthermore, in some cases, the insulating layer402ahas a function of suppressing entry of impurities to the channel formation region of the transistor. In the case where the conductive layer404bor the like includes an impurity for the semiconductor layer406aor406b, such as copper, for example, the insulating layer402ahas a function of blocking copper or the like in some cases. The semiconductor layers406aand406bare collectively referred to as a semiconductor layer406. In some cases, the semiconductor layer406has a function of the channel formation region of the transistor. The semiconductor layer406aincludes a region407a1and a region407b1which overlap with none of the insulating layer412, the conductive layer414a, the conductive layer414b, and the like. Furthermore, the semiconductor layer406bincludes a region407a2and a region407b2which overlap with none of the insulating layer412, the conductive layer414a, the conductive layer414b, and the like. The region407a1and the region407b1have lower resistance than the region overlapping with the insulating layer412, the conductive layer414a, the conductive layer414b, and the like in the semiconductor layer406a. The region407a2and the region407b2have lower resistance than the region overlapping with the insulating layer412, the conductive layer414a, the conductive layer414b, and the like in the semiconductor layer406b. Note that the region with low resistance can also be referred to as a region with high carrier density. The region407a1and the region407a2are collectively referred to as a region407a. The region407b1and the region407b2are collectively referred to as a region407b. The region407aand the region407bhave functions of the source region and the drain region of the transistor, in some cases. The conductive layers414aand414bare collectively referred to as a conductive layer414. The conductive layer414has a function of a gate electrode of the transistor in some cases. The conductive layer414has a function of shielding the channel formation region of the transistor from light in some cases. The insulating layer412has a function of a gate insulating layer of the transistor in some cases. In some cases, the insulating layer408has a function of suppressing entry of impurities to the channel formation region of the transistor. In the case where the conductive layer416a2, the conductive layer416b2, or the like includes an impurity for the semiconductor layer406aor406b, such as copper, for example, the insulating layer408has a function of blocking copper or the like in some cases. The insulating layer418has a function of an interlayer insulating layer of the transistor, in some cases. For example, parasitic capacitance between wirings of the transistor can be reduced by the insulating layer418in some cases. The conductive layers416a1and416a2are collectively referred to as a conductive layer416a. The conductive layers416b1and416b2are collectively referred to as a conductive layer416b. The conductive layer416aand the conductive layer416bhave functions of the source electrode and the drain electrode of the transistor, in some cases. In some cases, the insulating layer428has a function of suppressing entry of impurities to the channel formation region of the transistor. Here, a band structure in the K1-K2cross section including the channel formation regions of the transistor is illustrated inFIG.39B. Note that the semiconductor layer406ais assumed to have a narrower energy gap than the semiconductor layer406b. Furthermore, the insulating layer402a, the insulating layer402b, and the insulating layer412are assumed to have wider energy gaps than the semiconductor layer406aand the semiconductor layer406b. Furthermore, the Fermi levels (denoted by Ef) of the semiconductor layer406a, the semiconductor layer406b, the insulating layer402a, the insulating layer402b, and the insulating layer412are assumed to be equal to the intrinsic Fermi levels thereof (denoted by Ei). Furthermore, work functions of the conductive layer404and the conductive layer414are assumed equal to the Fermi levels. When a gate voltage is set to be higher than or equal to the threshold voltage of the transistor, an electron flows preferentially in the semiconductor layer406aowing to the difference between the energies of the conduction band minimums of the semiconductor layers406aand406b. That is, it is probable that an electron is embedded in the semiconductor layer406a. Note that the energy at the conduction band minimum is denoted by Ec, and the energy at the valence band maximum is denoted by Ev. Accordingly, in the transistor according to one embodiment of the present invention, the embedment of an electron reduces the influence of interface scattering. Therefore, the channel resistance of the transistor according to one embodiment of the present invention is low. Next,FIG.39Cshows a band structure in the L1-L2cross section including the source region or the drain region of the transistor. Note that the regions407a1,407b1,407a2, and407b2are assumed to be in a degenerate state. Furthermore, the Fermi level of the semiconductor layer406ais assumed to be approximately the same as the energy of the conduction band minimum in the region407b1. Furthermore, the Fermi level of the semiconductor layer406ais assumed to be approximately the same as the energy of the conduction band minimum in the region407b2. The same can apply to the regions407a1and407a2. At this time, an ohmic contact is made between the conductive layer416bfunctioning as a source electrode or a drain electrode and the region407b2because an energy barrier therebetween is sufficiently low. Furthermore, an ohmic contact is made between the region407b2and the region407b1. Similarly, an ohmic contact is made between the conductive layer416afunctioning as a source electrode or a drain electrode and the region407a2because an energy barrier therebetween is sufficiently low. Furthermore, an ohmic contact is made between the region407a2and the region407a1. Therefore, electron transfer is conducted smoothly between the conductive layers416aand416band the semiconductor layers406aand406b. As described above, the transistor according to one embodiment of the present invention is a transistor in which the channel resistance is low and electron transfer between the channel formation region and the source and the drain electrodes is conducted smoothly. That is, the transistor has excellent switching characteristics. This embodiment can be combined as appropriate with any of the other embodiments in this specification. Embodiment 13 In this embodiment, effects of an oxygen vacancy in an oxide semiconductor layer and hydrogen that enters the oxygen vacancy are described below. <(1) Ease of Formation and Stability of VoH> In the case where an oxide semiconductor film (hereinafter referred to as IGZO) is a complete crystal, H preferentially diffuses along the a-b plane at a room temperature. In heat treatment at 450° C., H diffuses along the a-b plane and in the c-axis direction. Here, description is made on whether H easily enters an oxygen vacancy Voif the oxygen vacancy Voexists in IGZO. A state in which H is in an oxygen vacancy Vois referred to as VoH. An InGaZnO4crystal model shown inFIG.40was used for calculation. The activation barrier (Ea) along the reaction path where H in VoH is released from Voand bonded to oxygen was calculated by a nudged elastic band (NEB) method. The calculation conditions are shown in Table 1. TABLE 1SoftwareVASPCalculation methodNEB methodFunctionalGGA-PBEPseudopotentialPAWCut-off energy500 eVK points2 × 2 × 3 In the InGaZnO4crystal model, there are oxygen sites 1 to 4 as shown inFIG.40which differ from each other in metal elements bonded to oxygen and the number of bonded metal elements. Here, calculation was made on the oxygen sites 1 and 2 in which an oxygen vacancy Vois easily formed. First, calculation was made on the oxygen site 1 in which an oxygen vacancy Vois easily formed, which is herein the oxygen site that was bonded to three In atoms and one Zn atom. FIG.41Ashows a model in the initial state andFIG.41Bshows a model in the final state.FIG.42shows the calculated activation barrier (Ea) in the initial state and the final state. Note that here, the initial state refers to a state in which H exists in an oxygen vacancy Vo(VoH), and the final state refers to a structure including an oxygen vacancy Voand a state in which H is bonded to oxygen bonded to one Ga atom and two Zn atoms (H—O). From the calculation results, bonding of H in an oxygen vacancy Voto another oxygen atom needs an energy of approximately 1.52 eV, while entry of H bonded to O into an oxygen vacancy V o needs an energy of approximately 0.46 eV. Reaction frequency (F) was calculated with use of the activation barriers (Ea) obtained by the calculation and Formula 1. In Formula 1, k B represents the Boltzmann constant and T represents the absolute temperature. Γ=vexp(-EakBT)[Formula1] The reaction frequency at 350° C. was calculated on the assumption that the frequency factor v=1013[1/sec]. The frequency of H transfer from the model shown inFIG.41Ato the model shown inFIG.41Bwas 5.52×100[1/sec], whereas the frequency of H transfer from the model shown inFIG.41Bto the model shown inFIG.41Awas 1.82×109[1/sec]. This suggests that H diffusing in IGZO is likely to faun VoH if an oxygen vacancy Voexists in the neighborhood, and H is unlikely to be released from the oxygen vacancy Voonce VoH is formed. Next, calculation was made on the oxygen site 2 in which an oxygen vacancy Vois easily formed, which is herein the oxygen site that was bonded to one Ga atom and two Zn atoms. FIG.43Ashows a model in the initial state andFIG.43Bshows a model in the final state.FIG.44shows the calculated activation barrier (Ea) in the initial state and the final state. Note that here, the initial state refers to a state in which H exists in an oxygen vacancy Vo(VoH), and the final state refers to a structure including an oxygen vacancy Voand a state in which H is bonded to oxygen bonded to one Ga atom and two Zn atoms (H—O). From the calculation results, bonding of H in an oxygen vacancy Voto another oxygen atom needs an energy of approximately 1.75 eV, while entry of H bonded to O in an oxygen vacancy Voneeds an energy of approximately 0.35 eV. Reaction frequency (F) was calculated with use of the activation barriers (Ea) obtained by the calculation and Formula 1. The reaction frequency at 350° C. was calculated on the assumption that the frequency factor v=1013[1/sec]. The frequency of H transfer from the model shown inFIG.43Ato the model shown inFIG.43Bwas 7.53×10−2[1/sec], whereas the frequency of H transfer from the model shown inFIG.43Bto the model shown inFIG.43Awas 1.44×1010[1/sec]. This suggests that H is unlikely to be released from the oxygen vacancy Voonce VoH is formed. From the above results, it was found that H in IGZO easily diffused in annealing and if an oxygen vacancy Voexisted, H was likely to enter the oxygen vacancy Voto be VoH. <(2) Transition Level of V0H> The calculation by the NEB method, which was described in <(1) Ease of formation and stability of VoH>, indicates that in the case where an oxygen vacancy Voand H exist in IGZO, the oxygen vacancy Voand H easily form VoH and VoH is stable. To determine whether VoH is related to a carrier trap, the transition level of VoH was calculated. The model used for calculation is an InGaZnO4crystal model (112 atoms). VoH models of the oxygen sites 1 and 2 shown inFIG.40were made to calculate the transition levels. The calculation conditions are shown in Table 2. TABLE 2SoftwareVASPMoldelInGaZnO4 crystal (112 atoms)FunctionalHSE06Ratio of exchange terms0.25PseudopotentialGGA-PBECut-off energy800 eVK points1 × 1 × 1 The ratio of exchange terms was adjusted to have a band gap close to the experimental value. As a result, the band gap of the InGaZnO4crystal model without defects was 3.08 eV that was close to the experimental value, 3.15 eV. The transition level (ε(qlq′)) of a model having defect D can be calculated by the following Formula 2. Note that ΔE(Dq) represents the formation energy of defect D at charge q, which is calculated by Formula 3. ε(q/q′)=ΔE(Dq)-ΔE(Dq′)q'-q[Formula2] ΔE(Dq)=Etot(Dq)-Etot(bulk)+∑iΔniμi+q(εVBM+ΔVq+EF)[Formula3] In Formulae 2 and 3, Etot(Dq) represents the total energy of the model having defect D at the charge q in, Etot(bulk) represents the total energy in a model without defects (complete crystal), Δnirepresents a change in the number of atoms i contributing to defects, μirepresents the chemical potential of atom i, εVBMrepresents the energy of the valence band maximum in the model without defects, ΔVqrepresents the correction term relating to the electrostatic potential, and EFrepresents the Fermi energy. FIG.45shows the transition levels of VoH obtained from the above formulae. The numbers inFIG.45represent the depth from the conduction band minimum. InFIG.45, the transition level of VoH in the oxygen site 1 is at 0.05 eV from the conduction band minimum, and the transition level of VoH in the oxygen site 2 is at eV from the conduction band minimum. Therefore, these VoH seems to be related to electron traps, that is, VoH seems to behave as a donor. Furthermore, IGZO including VoH has conductivity. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 14 The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable data appliances, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines.FIGS.46A to46Fillustrate specific examples of these electronic devices. FIG.46Aillustrates a portable game console including a housing901, a housing902, a display portion903, a display portion904, a microphone905, a speaker906, an operation key907, a stylus908, and the like. Although the portable game machine inFIG.46Ahas the two display portions903and904, the number of display portions included in a portable game machine is not limited to this. FIG.46Billustrates a portable data terminal including a first housing911, a second housing912, a first display portion913, a second display portion914, a joint915, an operation key916, and the like. The first display portion913is provided in the first housing911, and the second display portion914is provided in the second housing912. The first housing911and the second housing912are connected to each other with the joint915, and the angle between the first housing911and the second housing912can be changed with the joint915. An image on the first display portion913may be switched depending on the angle between the first housing911and the second housing912at the joint915. A display device with a position input function may be used as at least one of the first display portion913and the second display portion914. Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by provision of a photoelectric conversion element called a photosensor in a pixel portion of a display device. FIG.46Cillustrates a laptop personal computer, which includes a housing921, a display portion922, a keyboard923, a pointing device924, and the like. FIG.46Dillustrates a wrist-watch-type information terminal, which includes a housing931, a display portion932, a wristband933, and the like. The display portion932may be a touch panel. FIG.46Eillustrates a video camera, which includes a first housing941, a second housing942, a display portion943, operation keys944, a lens945, a joint946, and the like. The operation keys944and the lens945are provided for the first housing941, and the display portion943is provided for the second housing942. The first housing941and the second housing942are connected to each other with the joint946, and the angle between the first housing941and the second housing942can be changed with the joint946. Images displayed on the display portion943may be switched in accordance with the angle at the joint946between the first housing941and the second housing942. FIG.46Fillustrates an ordinary vehicle including a car body951, wheels952, a dashboard953, lights954, and the like. This embodiment can be combined with any of the other embodiments described in this specification as appropriate. Embodiment 15 In this embodiment, application examples of an RF tag of one embodiment of the present invention will be described with reference toFIGS.47A to47F. The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards, seeFIG.47A), vehicles (e.g., bicycles, seeFIG.47B), packaging containers (e.g., wrapping paper or bottles, seeFIG.47C), recording media (e.g., DVD or video tapes, seeFIG.47D), personal belongings (e.g., bags or glasses), foods, plants, animals, human bodies, clothing, household goods, medical supplies such as medicine and chemicals, and electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (seeFIGS.47E and47F). An RF tag4000of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag4000is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag4000of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag4000of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have higher security against theft or the like by being provided with the RF tag of one embodiment of the present invention. As described above, by using the RF tag of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Embodiment 16 <Deposition Model> Examples of deposition models of a CAAC-OS and nc-OS are described below. FIG.58Ais a schematic diagram of a deposition chamber illustrating a state where the CAAC-OS film is formed by a sputtering method. A target5130is attached to a backing plate. Under the target5130and the backing plate, a plurality of magnets are provided. The plurality of magnets cause a magnetic field over the target5130. A sputtering method in which the disposition speed is increased by utilizing a magnetic field of magnets is referred to as a magnetron sputtering method. The target5130has a polycrystalline structure in which a cleavage plane exists in at least one crystal grain. Note that the details of the cleavage plane are described later. A substrate5120is placed to face the target5130, and the distance d (also referred to as a target—substrate distance (T—S distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m. The deposition chamber is mostly filled with a deposition gas (e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at 50 vol % or higher) and controlled to higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa. Here, discharge starts by application of a voltage at a certain value or higher to the target5130, and plasma is observed. Note that the magnetic field over the target5130forms a high-density plasma region. In the high-density plasma region, the deposition gas is ionized, so that an ion5101is generated. Examples of the ion5101include an oxygen cation (O+) and an argon cation (Ar+). The ion5101is accelerated to the target5130side by an electric field, and collides with the target5130eventually. At this time, a pellet5100aand a pellet5100bwhich are flat-plate-like or pellet-like sputtered particles are separated and sputtered from the cleavage plane. Note that structures of the pellet5100aand the pellet5100bmay be distorted by an impact of collision of the ion5101. The pellet5100ais a flat-plate-like or pellet-like sputtered particle having a triangle plane, e.g., a regular triangle plane. The pellet5100bis a flat-plate-like or pellet-like sputtered particle having a hexagon plane, e.g., regular hexagon plane. Note that flat-plate-like or pellet-like sputtered particles such as the pellet5100aand the pellet5100bare collectively called pellets5100. The shape of a flat plane of the pellet5100is not limited to a triangle or a hexagon. For example, the flat plane may have a shape formed by combining greater than or equal to 2 and less than or equal to 6 triangles. For example, a square (rhombus) is formed by combining two triangles (regular triangles) in some cases. The thickness of the pellet5100is determined depending on the kind of the deposition gas and the like. The thicknesses of the pellets5100are preferably uniform; the reasons thereof are described later. In addition, the sputtered particle preferably has a pellet shape with a small thickness as compared to a dice shape with a large thickness. The pellet5100receives charge when passing through the plasma, so that side surfaces of the pellet5100are negatively or positively charged in some cases. The pellet5100includes an oxygen atom on its side surface, and the oxygen atom may be negatively charged. For example, a case in which the pellet5100aincludes, on its side surfaces, oxygen atoms that are negatively charged is illustrated inFIG.60. As in this view, when the side surfaces are charged in the same polarity, charges repel each other, and accordingly, the pellet can maintain a flat-plate shape. In the case where a CAAC-OS is an In—Ga—Zn oxide, there is a possibility that an oxygen atom bonded to an indium atom is negatively charged. There is another possibility that an oxygen atom bonded to an indium atom, a gallium atom, and a zinc atom is negatively charged. As shown inFIG.58A, the pellet5100flies like a kite in plasma and flutters up to the substrate5120. Since the pellets5100are charged, when the pellet5100gets close to a region where another pellet5100has already been deposited, repulsion is generated. Here, above the substrate5120, a magnetic field is generated in a direction parallel to a top surface of the substrate5120. A potential difference is given between the substrate5120and the target5130, and accordingly, current flows from the substrate5120toward the target5130. Thus, the pellet5100is given a force (Lorentz force) on the top surface of the substrate5120by an effect of the magnetic field and the current (seeFIG.61). This is explainable with Fleming's left-hand rule. In order to increase a force applied to the pellet5100, it is preferable to provide, on the top surface, a region where the magnetic field in a direction parallel to the top surface of the substrate5120is G or higher, preferably 20 G or higher, further preferably 30 G or higher, still further preferably 50 G or higher. Alternatively, it is preferable to provide, on the top surface, a region where the magnetic field in a direction parallel to the top surface of the substrate is 1.5 times or higher, preferably twice or higher, further preferably 3 times or higher, still further preferably 5 times or higher as high as the magnetic field in a direction perpendicular to the top surface of the substrate5120. Furthermore, the substrate5120is heated, and resistance such as friction between the pellet5100and the substrate5120is low. As a result, as illustrated in FIG.62A, the pellet5100glides above the surface of the substrate5120. The glide of the pellet5100is caused in a state where the flat plane faces the substrate5120. Then, as illustrated inFIG.62B, when the pellet5100reaches the side surface of another pellet5100that has been already deposited, the side surfaces of the pellets5100are bonded. At this time, the oxygen atom on the side surface of the pellet5100is released. With the released oxygen atom, oxygen vacancies in a CAAC-OS is filled in some cases; thus, the CAAC-OS has a low density of defect states. Further, the pellet5100is heated on the substrate5120, whereby atoms are rearranged, and the structure distortion caused by the collision of the ion5101can be reduced. The pellet5100whose structure distortion is reduced is substantially single crystal. Even when the pellets5100are heated after being bonded, expansion and contraction of the pellet5100itself hardly occur, which is caused by turning the pellet5100into substantially single crystal. Thus, formation of defects such as a grain boundary due to expansion of a space between the pellets5100can be prevented, and accordingly, generation of crevasses can be prevented. Further, the space is filled with elastic metal atoms and the like, whereby the elastic metal atoms have a function, like a highway, of jointing side surfaces of the pellets5100which are not aligned with each other. It is considered that as shown in such a model, the pellets5100are deposited over the substrate5120. Thus, a CAAC-OS film can be deposited even when a surface over which a film is formed (film formation surface) does not have a crystal structure, which is different from film deposition by epitaxial growth. For example, even when a surface (film formation surface) of the substrate5120has an amorphous structure, a CAAC-OS film can be formed. Further, it is found that in formation of the CAAC-OS, the pellets5100are arranged in accordance with a surface shape of the substrate5120that is the film formation surface even when the film formation surface has unevenness besides a flat surface. For example, in the case where the surface of the substrate5120is flat at the atomic level, the pellets5100are arranged so that flat planes parallel to the a-b plane face downwards; thus, a layer with a uniform thickness, flatness, and high crystallinity is formed. By stacking n layers (n is a natural number), the CAAC-OS can be obtained (seeFIG.58B). In the case where the top surface of the substrate5120has unevenness, a CAAC-OS where n layers (n is a natural number) in each of which the pellets5100are arranged along a convex surface are stacked is formed. Since the substrate5120has unevenness, a gap is easily generated between in the pellets5100in the CAAC-OS in some cases. Note that owing to intermolecular force, the pellets5100are arranged so that a gap between the pellets is as small as possible even on the unevenness surface. Therefore, even when the formation surface has unevenness, a CAAC-OS with high crystallinity can be formed (seeFIG.58C). As a result, laser crystallization is not needed for formation of a CAAC-OS, and a uniform film can be formed even over a large-sized glass substrate. Since the CAAC-OS film is deposited in accordance with such a model, the sputtered particle preferably has a pellet shape with a small thickness. Note that in the case where the sputtered particle has a dice shape with a large thickness, planes facing the substrate5120are not uniform and thus, the thickness and the orientation of the crystals cannot be uniform in some cases. According to the deposition model described above, a CAAC-OS with high crystallinity can be formed even on a film formation surface with an amorphous structure. Further, formation of a CAAC-OS can be described with a deposition model including a zinc oxide particle besides the pellet5100. The zinc oxide particle reaches the substrate5120before the pellet5100does because the zinc oxide particle is smaller than the pellet5100in mass. On the surface of the substrate5120, crystal growth of the zinc oxide particle preferentially occurs in the horizontal direction, so that a thin zinc oxide layer is formed. The zinc oxide layer has c-axis alignment. Note that c-axes of crystals in the zinc oxide layer are aligned in the direction parallel to a normal vector of the substrate5120. The zinc oxide layer serves as a seed layer that makes a CAAC-OS grow and thus has a function of increasing crystallinity of the CAAC-OS. The thickness of the zinc oxide layer is greater than or equal to 0.1 nm and less than or equal to 5 nm, mostly greater than or equal to 1 nm and less than or equal to 3 nm. Since the zinc oxide layer is sufficiently thin, a grain boundary is hardly observed. Thus, in order to deposit a CAAC-OS with high crystallinity, a target containing zinc at a proportion higher than that of the stoichiometric composition is preferably used. An nc-OS can be understood with a deposition model illustrated inFIG.59. Note that a difference betweenFIG.59andFIG.58Alies only in the fact that whether the substrate5120is heated or not. Thus, the substrate5120is not heated, and a resistance such as friction between the pellet5100and the substrate5120is high. As a result, the pellets5100cannot glide on the surface of the substrate5120and are stacked randomly, thereby forming an nc-OS. <Cleavage Plane> A cleavage plane that has been mentioned in the deposition model of the CAAC-OS will be described below. First, a cleavage plane of the target is described with reference toFIGS.63A and63B.FIGS.63A and63Bshow the crystal structure of InGaZnO4. Note thatFIG.63Ashows the structure of the case where an InGaZnO4crystal is observed from a direction parallel to the b-axis when the c-axis is in an upward direction. Furthermore,FIG.63Bshows the structure of the case where the InGaZnO4crystal is observed from a direction parallel to the c-axis. Energy needed for cleavage at each of crystal planes of the InGaZnO4crystal is calculated by the first principles calculation. Note that a “pseudopotential” and density functional theory program (CASTEP) using the plane wave basis are used for the calculation. Note that an ultrasoft type pseudopotential is used as the pseudopotential. Further, GGA/PBE is used as the functional. Cut-off energy is 400 eV. Energy of a structure in an initial state is obtained after structural optimization including a cell size is performed. Further, energy of a structure after the cleavage at each plane is obtained after structural optimization of atomic arrangement is performed in a state where the cell size is fixed. On the basis of the structure of the InGaZnO4crystal inFIGS.63A and63B, a structure cleaved at any one of a first plane, a second plane, a third plane, and a fourth plane is formed and subjected to structural optimization calculation in which the cell size is fixed. Here, the first plane is a crystal plane between a Ga—Zn—O layer and an In—O layer and is parallel to the (001) plane (or the a-b plane) (seeFIG.63A). The second plane is a crystal plane between a Ga—Zn—O layer and a Ga—Zn—O layer and is parallel to the (001) plane (or the a-b plane) (seeFIG.63A). The third plane is a crystal plane parallel to the (110) plane (seeFIG.63B). The fourth plane is a crystal plane parallel to the (100) plane (or the b-c plane) (seeFIG.63B). Under the above conditions, the energy of the structure at each plane after the cleavage is calculated. Next, a difference between the energy of the structure after the cleavage and the energy of the structure in the initial state is divided by the area of the cleavage plane; thus, cleavage energy which serves as a measure of easiness of cleavage at each plane is calculated. Note that the energy of a structure indicates energy obtained in such a manner that electronic kinetic energy of electrons included in the structure and interactions between atoms included in the structure, between the atom and the electron, and between the electrons are considered. As calculation results, the cleavage energy of the first plane was 2.60 J/m2, that of the second plane was 0.68 J/m2, that of the third plane was 2.18 J/m2, and that of the fourth plane was 2.12 J/m2(see Table 1). TABLE 3Cleavage energy [J/m2]First plane2.60Second plane0.68Third plane2.18Fourth plane2.12 From the calculations, in the structure of the InGaZnO4crystal inFIGS.63A and63B, the cleavage energy of the second plane is the lowest. In other words, a plane between a Ga—Zn—O layer and a Ga—Zn—O layer is cleaved most easily (cleavage plane). Therefore, in this specification, the cleavage plane indicates the second plane, which is a plane where cleavage is performed most easily. Since the cleavage plane is the second plane between the Ga—Zn—O layer and the Ga—Zn—O layer, the InGaZnO4crystals inFIG.63Acan be separated at a plane equivalent to two second planes. Therefore, in the case where an ion or the like is made to collide with a target, a wafer-like unit (we call this a pellet) which is cleaved at a plane with the lowest cleavage energy is thought to be blasted off as the minimum unit. In that case, a pellet of InGaZnO4includes three layers: a Ga—Zn—O layer, an 1n-0 layer, and a Ga—Zn—O layer. The cleavage energies of the third plane (crystal plane parallel to the (110) plane) and the fourth plane (crystal plane parallel to the (100) plane (or the b-c plane)) are lower than that of the first plane (crystal plane between the Ga—Zn—O layer and the In—O layer and plane that is parallel to the (001) plane (or the a-b plane)), which suggests that most of the flat planes of the pellets have triangle shapes or hexagonal shapes. Next, through classical molecular dynamics calculation, on the assumption of an InGaZnO4crystal having a homologous structure as a target, a cleavage plane in the case where the target is sputtered using argon (Ar) or oxygen (O) is examined.FIG.64Ashows a cross-sectional structure of an InGaZnO4crystal (2688 atoms) used for the calculation, andFIG.64Bshows a top structure thereof. Note that a fixed layer inFIG.64Aprevents the positions of the atoms from moving. A temperature control layer inFIG.64Ais a layer whose temperature is constantly set to fixed temperature (300 K). For the classical molecular dynamics calculation, Materials Explorer 5.0 manufactured by Fujitsu Limited. is used. Note that the initial temperature, the cell size, the time step size, and the number of steps are set to be 300 K, a certain size, 0.01 fs, and ten million, respectively. In calculation, an atom to which an energy of 300 eV is applied is made to enter a cell from a direction perpendicular to the a-b plane of the InGaZnO4crystal under the above-mentioned conditions. FIG.65Ashows atomic order when 99.9 picoseconds have passed after argon enters the cell including the InGaZnO4crystal inFIGS.64A and64B.FIG.65Bshows atomic order when 99.9 picoseconds have passed after oxygen enters the cell. Note that inFIGS.65A and65B, part of the fixed layer inFIG.64Ais omitted. According toFIG.65A, in a period from entry of argon into the cell to when 99.9 picoseconds have passed, a crack is formed from the cleavage plane corresponding to the second plane inFIG.63A. Thus, in the case where argon collides with the InGaZnO4crystal and the uppermost surface is the second plane (the zero-th), a large crack is found to be formed in the second plane (the second). On the other hand, according toFIG.65B, in a period from entry of oxygen into the cell to when 99.9 picoseconds have passed, a crack is found to be formed from the cleavage plane corresponding to the second plane inFIG.63A. Note that in the case where oxygen collides with the cell, a large crack is found to be formed in the second plane (the first) of the InGaZnO4crystal. Accordingly, it is found that an atom (ion) collides with a target including an InGaZnO4crystal having a homologous structure from the upper surface of the target, the InGaZnO4crystal is cleaved along the second plane, and a flat-plate-like sputtered particle (pellet) is separated. It is also found that the pellet formed in the case where oxygen collides with the cell is smaller than that formed in the case where argon collides with the cell. The above calculation suggests that the separated pellet includes a damaged region. In some cases, the damaged region included in the pellet can be repaired in such a manner that a defect caused by the damage reacts with oxygen. Here, difference in size of the pellet depending on atoms which are made to collide is studied. FIG.66Ashows trajectories of the atoms from 0 picosecond to 0.3 picoseconds after argon enters the cell including the InGaZnO4crystal inFIGS.64A and64B. Accordingly,FIG.66Acorresponds to a period fromFIGS.64A and64BtoFIG.65A. According toFIG.66A, when argon collides with gallium (Ga) of the first layer (Ga—Zn—O layer), gallium collides with zinc (Zn) of the third layer (Ga—Zn—O layer) and then, zinc reaches the vicinity of the sixth layer (Ga—Zn—O layer). Note that the argon which collides with the gallium is sputtered to the outside. Accordingly, in the case where argon collides with the target including the InGaZnO4crystal, a crack is thought to be formed in the second plane (the second) inFIG.64A. FIG.66Bshows trajectories of the atoms from 0 picosecond to 0.3 picoseconds after oxygen enters the cell including the InGaZnO4crystal inFIGS.64A and64B. Accordingly,FIG.66Bcorresponds to a period fromFIGS.64A and64BtoFIG.65A. On the other hand, according toFIG.66B, when oxygen collides with gallium (Ga) of the first layer (Ga—Zn—O layer), gallium collides with zinc (Zn) of the third layer (Ga—Zn—O layer) and then, zinc does not reach the fifth layer (In—O layer). Note that the oxygen which collides with the gallium is sputtered to the outside. Accordingly, in the case where oxygen collides with the target including the InGaZnO4crystal, a crack is thought to be formed in the second plane (the first) inFIG.64A. This calculation also shows that the InGaZnO4crystal with which an atom (ion) collides is separated from the cleavage plane. In addition, a difference in depth of a crack is examined in view of conservation laws. The energy conservation law and the law of conservation of momentum can be represented by the following Formula 4 and the following Formula 5. Here, E represents energy of argon or oxygen before collision (300 eV), mArepresents mass of argon or oxygen, vArepresents the speed of argon or oxygen before collision, v′Arepresents the speed of argon or oxygen after collision, mGarepresents mass of gallium, vGarepresents the speed of gallium before collision, and v′Garepresents the speed of gallium after collision. E=12mAvA2+12mGavGa2[Formula4] mAvA+mGavGa=mAv′A+mGav′Ga[Formula 5] On the assumption that collision of argon or oxygen is elastic collision, the relationship among vA, v′A, vGa, and v′Gacan be represented by the following Formula 3. v′A−v′Ga=−(vA−vGa) [Formula 6] From the formulae 4, 5, and 6, on the assumption that vGais 0, the speed of gallium v′Gaafter collision of argon or oxygen can be represented by the following Formula 7. vGa′=mAmA+mGa·22E[Formula7] In Formula 7, mass of argon or oxygen is substituted into mA, whereby the speeds after collision of the atoms are compared. In the case where the argon and the oxygen have the same energy before collision, the speed of gallium in the case where argon collides with the gallium was found to be 1.24 times as high as that in the case where oxygen collides with the gallium. Thus, the energy of the gallium in the case where argon collides with the gallium is higher than that in the case where oxygen collides with the gallium by the square of the speed. The speed (energy) of gallium after collision in the case where argon collides with the gallium is found to be higher than that in the case where oxygen collides with the gallium. Accordingly, it is considered that a crack is formed at a deeper position in the case where argon collides with the gallium than in the case where oxygen collides with the gallium. The above calculation shows that when sputtering is performed using a target including the InGaZnO4crystal having a homologous structure, separation occurs from the cleavage plane to form a pellet. On the other hand, even when sputtering is performed on a region having another structure of a target without the cleavage plane, a pellet is not formed, and a sputtered particle with an atomic-level size which is minuter than a pellet is formed. Because the sputtered particle is smaller than the pellet, the sputtered particle is thought to be removed through a vacuum pump connected to a sputtering apparatus. Therefore, a model in which particles with a variety of sizes and shapes fly to a substrate and are deposited hardly applies to the case where sputtering is performed using a target including the InGaZnO4crystal having a homologous structure. The model illustrated inFIG.58Awhere sputtered pellets are deposited to form a CAAC-OS is a reasonable model. The CAAC-OS deposited in such a manner has a density substantially equal to that of a single crystal OS. For example, the density of the single crystal OS film having a homologous structure of InGaZnO4is 6.36 g/cm3, and the density of the CAAC-OS film having substantially the same atomic ratio is approximately 6.3 g/cm3. FIGS.67A and67Bshow atomic order of cross sections of an In—Ga—Zn oxide (seeFIG.67A) that is a CAAC-OS deposited by sputtering and a target thereof (seeFIG.67B). For observation of atomic arrangement, a high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) is used. In the case of observation by HAADF-STEM, the intensity of an image of each atom is proportional to the square of its atomic number. Therefore, Zn (atomic number: 30) and Ga (atomic number: 31), whose atomic numbers are close to each other, are hardly distinguished from each other. A Hitachi scanning transmission electron microscope HD-2700 is used for the HAADF-STEM. WhenFIG.67AandFIG.67Bare compared, it is found that the CAAC-OS and the target each have a homologous structure and atomic order in the CAAC-OS correspond to that in the target. Thus, as illustrated in the deposition model inFIG.58A, the crystal structure of the target is transferred, whereby a CAAC-OS is formed. This embodiment can be combined as appropriate with any of the other embodiments and examples in this specification. Example 1 In this example, experimental results on plasma treatment for forming the source region and the drain region in the transistor of one embodiment of the present invention will be described. Note that as the structure of the transistor, the structure of the transistor101illustrated inFIGS.1A and1Bwas used. In this example, two kinds of transistors were fabricated; one of the transistors was fabricated without a resist mask on the gate electrode layer at plasma treatment, and the other of the transistors was fabricated with a resist mask left on the gate electrode layer at plasma treatment. The fabricating method is described in detail below. As the substrate, a glass substrate was used. As the base insulating film, a stacked film consisting of a 100-nm-thick silicon nitride film and a 400-nm-thick silicon oxynitride film was deposited over the glass substrate by a plasma CVD method. Then, heat treatment was performed on the base insulating film by rapid thermal annealing (RTA) at 650° C. for 6 minutes. Next, a 5-nm-thick tantalum nitride film was formed over the base insulating film, and oxygen was added to the base insulating film through the tantalum nitride film by oxygen plasma treatment. Next, a 50-nm-thick oxide semiconductor film was deposited by a sputtering method using an oxide target with a ratio of In:Ga:Zn=5:5:6. Then, heat treatment of the oxide semiconductor film was performed at 450° C., in a nitrogen atmosphere for 1 hour and in a mixed atmosphere of nitrogen and oxygen for 1 hour. Then, the oxide semiconductor film was selectively etched to form an oxide semiconductor layer. A 100-nm-thick silicon oxynitride film as a gate insulating film was deposited over the oxide semiconductor layer by a plasma CVD method. Next, as a gate electrode layer, a 30-nm-thick tantalum nitride film and a 150-nm-thick tungsten film were deposited over the gate insulating film by a sputtering method. Next, a resist mask was formed over the tungsten film. Then, the tungsten film, the tantalum nitride film, and the silicon oxynitride film were sequentially selectively etched, so that part of the oxide semiconductor layer (the first region and the second region) was exposed. Then, plasma treatment was performed on the samples under the same conditions, with or without the resist mask left. For the plasma treatment, a vacuum apparatus that can apply high-frequency power (13.56 MHz) between a pair of electrodes was used. A substrate was placed on the cathode side, and plasma was generated by application of high-frequency waves with a power density of 0.47 or 0.94 W/cm2in a 5 Pa argon reduced-pressure atmosphere at a substrate temperature of 20° C. The treatment was performed for 1 minute. Next, a 100-nm-thick silicon nitride film containing hydrogen was deposited over the above-described structure, and a 300-nm-thick silicon oxynitride film was deposited over the silicon nitride film. Both were deposited by a plasma CVD method. Then, contact holes reaching the first region and the second region of the oxide semiconductor layer were formed in the silicon nitride film and the silicon oxynitride film. Next, stacked layers of a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film were sequentially deposited by a sputtering method so as to cover the contact holes, and were selectively etched, so that the source electrode layer and the drain electrode layer were formed. Next, as a passivation film, a silicon nitride film was deposited over the above-described structure by a plasma CVD method, and then subjected to heat treatment at 350° C. in a mixed atmosphere of nitrogen and oxygen for 1 hour. By the above-described method, the transistors were fabricated. Note that the transistor fabricated by performing the plasma treatment after the resist mask removal is referred to as a transistor A, and the transistor fabricated by performing the plasma treatment before the resist mask removal is referred to as a transistor B. FIGS.48A and48Bare cross-sectional TEM images each showing an end portion of the channel region in the channel length direction of the transistor.FIG.48Ashows a cross section of the transistor A, andFIG.48Bshows a cross section of the transistor B. In the transistor A, a substance having the same color tone as the gate electrode layer is deposited on the end portion of the gate insulating film, while such a substance is not deposited in the transistor B. FIGS.49A and49Bare cross-sectional views in the channel length direction of samples for the analysis, which were fabricated by the same fabricating method as those of the above-described transistors.FIG.49Ashows a cross section of the sample corresponding to the transistor A, andFIG.49Bshows a cross section of the sample corresponding to the transistor B. The region surrounded by the rectangle located in the center in both of the cross-sectional images was subjected to energy dispersive X-ray spectroscopy (EDX), and the results are shown in Table 4. TABLE 4(At %)Plasma treatmentAfterBeforeCharacteristic X-raysresist mask removalresist mask removalCK14.5913.80NK26.1619.79OK21.4422.54FK2.713.47SiK28.3038.99CuK2.331.41WL2.14— From Table 4, the deposit on the end portion of the gate insulating film inFIG.48Acan be assumed to be tungsten. The deposit of tungsten results from sputtering of the tungsten film serving as the gate electrode layer. Since tungsten is not detected in the transistor B, the resist mask seems to prevent tungsten sputtering. FIGS.50A to50Cshow Id-Vg characteristics of fabricated transistors. The transistor inFIG.50Ais the transistor A fabricated by performing the plasma treatment at 0.94 W/cm2after the resist mask removal. The transistor inFIG.50Bis a transistor B1fabricated by performing the plasma treatment at 0.47 W/cm2before the resist mask removal. The transistor inFIG.50Cis a transistor B2fabricated by performing the plasma treatment at 0.94 W/cm2before the resist mask removal. As shown inFIG.50A, the transistor A shows an extremely large gate leakage current (Ig) because the tungsten deposit on the end portion of the gate insulating film as shown inFIG.48Aserves as a leakage path. Meanwhile inFIGS.50B and50C, the transistors B1and B2show sufficiently small gate leakage currents. This also indicates that the plasma treatment with the resist mask left prevents formation of the tungsten deposit on the end portion of the gate insulating film. Next, gate bias-temperature stress tests were performed on the fabricated transistors. The tests were performed in both dark and photo states at a substrate temperature of 60° C., by application of ±12 V to the gate for 1 hour setting the source and the drain at the common potential. Note that a white LED was used as a light source in the photo state, and the illuminance was set at 10000 1×. FIG.51shows the results of the gate bias-temperature stress tests, where ΔVth is a variation in threshold voltage, and Δshift is a variation in shift value. Note that the shift value is the voltage at the current rising edge in Id-Vg characteristics, and is defined as the gate voltage (Vg [V]) when a drain current (Id [A]) is 1×10−12A. In the negative gate bias test in the photo state, the transistor A had a large ΔVth and a large Δshift, while the transistor B1and the transistor B2each had a small ΔVth and a small Δshift. FIG.52shows the comparison results of the negative gate bias-temperature stress tests among the top-gate self-aligned (TGSA) transistor B2, the transistor that has the same TGSA structure as the transistor B2but is different in that argon is added to the source region and the drain region with an ion doping apparatus, and a channel-etched bottom-gate top-contact (BGTC) transistor. The vertical axis shows −ΔVth, and the horizontal axis shows stress time. The ion doping was performed at a dose of 5E14ions/cm2at an acceleration voltage of 10 kV. The BGTC transistor is different from the TGSA transistors in that the test was performed at a gate bias of −30 V and that the transistor had the following size: L/W is 6 μm/576 μm. As shown inFIG.52, the argon-plasma-treated transistor B2had a smaller variation in threshold voltage than the other transistors. FIGS.53A to53Dare comparison test results of transistors including a channel-protective bottom-gate (BGTC) transistor. The test was performed by alternately applying a positive bias and a negative bias to the gate in the dark state. Note that the channel-protective bottom-gate transistor had L/W of 10.2 μm/82.6 μm, and the gate bias thereto was set at ±30 V. As shown inFIGS.53A to53D, the argon-plasma-treated transistor B2had a small variation in threshold voltage though having a small L length. Therefore, a transistor whose source and drain regions are formed through argon plasma treatment can have favorable electric characteristics and reliability. This embodiment can be combined as appropriate with any of the other embodiments and example in this specification. Example 2 In this example, a sample corresponding to the transistor of one embodiment of the present invention was fabricated, and the region corresponding to the source region and the drain region and the region corresponding to the channel region in the sample were subjected to SIMS. The results are described below. First, an oxide semiconductor layer (IGZO), a gate insulating film (silicon oxynitride), and a gate electrode layer (tantalum nitride and tungsten) were deposited over a glass substrate according to the transistor fabricating method described in Example 1, so that the structure illustrated inFIG.54Awas formed. Then, as illustrated in the drawing, argon was added downward to the structure with an ion doping apparatus at 30 kV and a dose of 1.0E15ions/cm2. Note that this method is different from the transistor fabricating method of Example 1 in not forming the insulating layer between the glass substrate and the oxide semiconductor layer. As a reference transistor, a sample with the same structure except that argon was added was fabricated. Next, a silicon nitride film containing hydrogen was formed over the above structure according to the transistor fabricating method to form the structure illustrated inFIG.54B. Then, SIMS of hydrogen was performed on a region X (corresponding to the source region and the drain region) and a region Y (corresponding to the channel region). Note that the SIMS was performed from the glass substrate side. FIGS.55A and55Bshow hydrogen depth profiles of the region X in the sample to which argon was added and the sample to which argon was not added, respectively. The hydrogen concentration of the oxide semiconductor layer in the region X was higher than or equal to 4×1020in the sample to which argon was added and lower than 4×10 20 in the sample to which argon was not added. FIGS.56A and56Bshow hydrogen depth profiles of the region Y in the sample to which argon was added and the sample to which argon was not added, respectively. In the region Y, there is no difference in hydrogen depth profile depending on the argon addition. Furthermore, the region Y has a lower hydrogen concentration than the region X of the argon-added sample. These results reveal that argon-added source and drain regions have a higher hydrogen concentration than a channel region in the transistor structure. That is, the addition of argon forms oxygen vacancies in an oxide semiconductor layer, and hydrogen is diffused to the oxide semiconductor layer from a nitride insulating film containing hydrogen which is formed in contact with the oxide semiconductor layer. This embodiment can be combined as appropriate with any of the other embodiments and example in this specification. Note that a content (or may be part of the content) described in one embodiment may be applied to, combined with, or replaced by a different content (or may be part of the different content) described in the embodiment and/or a content (or may be part of the content) described in one or a plurality of different embodiments. Note that in each embodiment, a content described in the embodiment is a content described with reference to a variety of diagrams or a content described with a text described in this specification. Note that by combining a diagram (or may be part of the diagram) illustrated in one embodiment with another part of the diagram, a different diagram (or may be part of the different diagram) illustrated in the embodiment, and/or a diagram (or may be part of the diagram) illustrated in one or a plurality of different embodiments, much more diagrams can be formed. Note that contents that are not specified in any drawing or text in the specification can be excluded from one embodiment of the invention. Alternatively, when the range of a value that is defined by the maximum and minimum values is described, part of the range is appropriately narrowed and part of the range is removed, whereby one embodiment of the invention can be constituted excluding part of the range can be constructed. In this manner, it is possible to specify the technical scope of one embodiment of the present invention so that a conventional technology is excluded, for example. As a specific example, a diagram of a circuit including a first transistor to a fifth transistor is illustrated. In that case, it can be specified that the circuit does not include a sixth transistor in the invention. It can be specified that the circuit does not include a capacitor in the invention. It can be specified that the circuit does not include a sixth transistor with a particular connection structure in the invention. It can be specified that the circuit does not include a capacitor with a particular connection structure in the invention. For example, it can be specified that a sixth transistor whose gate is connected to a gate of the third transistor is not included in the invention. For example, it can be specified that a capacitor whose first electrode is connected to the gate of the third transistor is not included in the invention. As another specific example, a description of a value, “a voltage is preferably higher than or equal to 3 V and lower than or equal to 10 V” is given. In that case, for example, it can be specified that the case where the voltage is higher than or equal to −2 V and lower than or equal to 1 V is excluded from one embodiment of the invention. For example, it can be specified that the case where the voltage is higher than or equal to 13 V is excluded from one embodiment of the invention. Note that, for example, it can be specified that the voltage is higher than or equal to 5 V and lower than or equal to 8 V in the invention. For example, it can be specified that the voltage is approximately 9 V in the invention. For example, it can be specified that the voltage is higher than or equal to 3 V and lower than or equal to 10 V but is not 9 V in the invention. Note that even when the description “a value is preferably in a certain range” or “a value preferably satisfies a certain condition” is given, the value is not limited to the description. In other words, a description of a value that includes a term “preferable”, “preferably”, or the like does not necessarily limit the value. As another specific example, a description “a voltage is preferred to be 10 V” is given. In that case, for example, it can be specified that the case where the voltage is higher than or equal to −2 V and lower than or equal to 1 V is excluded from one embodiment of the invention. For example, it can be specified that the case where the voltage is higher than or equal to 13 V is excluded from one embodiment of the invention. As another specific example, a description “a film is an insulating film” is given to describe properties of a material. In that case, for example, it can be specified that the case where the insulating film is an organic insulating film is excluded from one embodiment of the invention. For example, it can be specified that the case where the insulating film is an inorganic insulating film is excluded from one embodiment of the invention. For example, it can be specified that the case where the insulating film is a conductive film is excluded from one embodiment of the invention. For example, it can be specified that the case where the insulating film is a semiconductor film is excluded from one embodiment of the invention. As another specific example, the description of a stacked structure, “a film is provided between an A film and a B film” is given. In that case, for example, it can be specified that the case where the film is a stacked film of four or more layers is excluded from the invention. For example, it can be specified that the case where a conductive film is provided between the A film and the film is excluded from the invention. Note that various people can implement one embodiment of the invention described in this specification and the like. However, different people may be involved in the implementation of the invention. For example, in the case of a transmission/reception system, the following case is possible: Company A manufactures and sells transmitting devices, and Company B manufactures and sells receiving devices. As another example, in the case of a light-emitting device including a TFT and a light-emitting element, the following case is possible: Company A manufactures and sells semiconductor devices including TFTs, and Company B purchases the semiconductor devices, provides light-emitting elements for the semiconductor devices, and completes light-emitting devices. In such a case, one embodiment of the invention can be constituted so that a patent infringement can be claimed against each of Company A and Company B. In other words, one embodiment of the invention can be constituted so that only Company A implements the embodiment, and another embodiment of the invention can be constituted so that only Company B implements the embodiment. One embodiment of the invention with which a patent infringement suit can be filed against Company A or Company B is clear and can be regarded as being disclosed in this specification or the like. For example, in the case of a transmission/reception system, even when this specification or the like does not include a description of the case where a transmitting device is used alone or the case where a receiving device is used alone, one embodiment of the invention can be constituted by only the transmitting device and another embodiment of the invention can be constituted by only the receiving device. Those embodiments of the invention are clear and can be regarded as being disclosed in this specification or the like. Another example is as follows: in the case of a light-emitting device including a TFT and a light-emitting element, even when this specification or the like does not include a description of the case where a semiconductor device including the TFT is used alone or the case where a light-emitting device including the light-emitting element is used alone, one embodiment of the invention can be constituted by only the semiconductor device including the TFT and another embodiment of the invention can be constituted by only the light-emitting device including the light-emitting element. Those embodiments of the invention are clear and can be regarded as being disclosed in this specification or the like. Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Further, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. In particular, in the case where the number of portions to which the terminal is connected might be plural, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected. Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the invention can be clear. Furthermore, it can be determined that one embodiment of the invention whose function is specified is disclosed in this specification and the like. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted. Note that in this specification and the like, in a diagram or a text described in one embodiment, it is possible to take out part of the diagram or the text and constitute an embodiment of the invention. Thus, in the case where a diagram or a text related to a certain portion is described, the context taken out from part of the diagram or the text is also disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. The embodiment of the invention is clear. Therefore, for example, in a diagram or text in which one or more active elements (e.g., transistors or diodes), wirings, passive elements (e.g., capacitors or resistors), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, or the like are described, part of the diagram or the text is taken out, and one embodiment of the invention can be constituted. For example, from a circuit diagram in which N circuit elements (e.g., transistors or capacitors; N is an integer) are provided, it is possible to constitute one embodiment of the invention by taking out M circuit elements (e.g., transistors or capacitors; M is an integer, where M<N). As another example, it is possible to constitute one embodiment of the invention by taking out M layers (M is an integer, where M<1V) from a cross-sectional view in which N layers (N is an integer) are provided. As another example, it is possible to constitute one embodiment of the invention by taking out M elements (M is an integer, where M<N) from a flow chart in which AT elements (AT is an integer) are provided. As another example, it is possible to take out some given elements from a sentence “A includes B, C, D, E, or F” and constitute one embodiment of the invention, for example, “A includes B and E”, “A includes E and F”, “A includes C, E, and F”, or “A includes B, C, D, and E”. Note that in the case where at least one specific example is described in a diagram or a text described in one embodiment in this specification and the like, it will be readily appreciated by those skilled in the art that a broader concept of the specific example can be derived. Therefore, in the diagram or the text described in one embodiment, in the case where at least one specific example is described, a broader concept of the specific example is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. The embodiment of the invention is clear. Note that in this specification and the like, a content described in at least a diagram (which may be part of the diagram) is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. Therefore, when a certain content is described in a diagram, the content is disclosed as one embodiment of the invention even when the content is not described with a text, and one embodiment of the invention can be constituted. In a similar manner, part of a diagram, which is taken out from the diagram, is disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. The embodiment of the invention is clear. This application is based on Japanese Patent Application serial no. 2014-020061 filed with Japan Patent Office on Feb. 5, 2014 and Japanese Patent Application serial no. 2014-041446 filed with Japan Patent Office on Mar. 4, 2014, the entire contents of which are hereby incorporated by reference. | 287,226 |
11942556 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. The present disclosure is related to integrated circuit structures and methods of forming the same. More particularly, some embodiments of the present disclosure are related to GAA devices including channels with different thickness. With such configuration, the driving currents passing through different channels can be tuned. FIGS.1-13Billustrate perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure100in accordance with some embodiments of the present disclosure. In addition to the integrated circuit structure,FIGS.1-4A,5A,6A, and7Adepict X-axis, Y-axis, and Z-axis directions. The formed transistors may include a p-type transistor (such as a p-type GAA FET) and/or an n-type transistor (such as an n-type GAA FET) in accordance with some exemplary embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.1-13B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIGS.1-4A,5A,6A, and7Aare perspective views of some embodiments of the integrated circuit structure100at intermediate stages during fabrication.FIGS.4B,5B,6B,7B-11A,12, and13Aare cross-sectional views of some embodiments of the integrated circuit structure100at intermediate stages during fabrication along a first cut (e.g., cut X-X inFIG.4A), which is along a lengthwise direction of the channel and perpendicular to a top surface of the substrate.FIG.11Bis a cross-sectional view of some embodiments of the integrated circuit structure100at intermediate stages during fabrication along a second cut (e.g., cut Y-Y inFIG.4A), which is in the gate region and perpendicular to the lengthwise direction of the channel.FIG.13Bis an enlarged view of area A inFIG.13A. Referring toFIG.1, an epitaxial stack120is formed over the substrate110. In some embodiments, the substrate110may include silicon (Si). Alternatively, the substrate110may include germanium (Ge), silicon germanium (SiGe), a III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and/or GaInAsP; or a combination thereof) or other appropriate semiconductor materials. In some embodiments, the substrate110may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Also alternatively, the substrate110may include a buried dielectric layer such as a buried oxide (BOX) layer, such as that formed by a method referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or another appropriate method. The epitaxial stack120includes epitaxial layers122of a first composition interposed by epitaxial layers124a,124b, and124cof a second composition. The first and second compositions can be different. In some embodiments, the epitaxial layers122are SiGe and the epitaxial layers124a,124b, and124care silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. In some embodiments, the epitaxial layers122include SiGe and where the epitaxial layers124a,124b, and124cinclude Si, the Si oxidation rate of the epitaxial layers124a,124b, and124cis less than the SiGe oxidation rate of the epitaxial layers122. The epitaxial layers124a,124b, and124cor portions thereof may form nanosheet channel(s) of the multi-gate transistor. The term nanosheet is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The use of the epitaxial layers124a,124b, and124cto define a channel or channels of a device is further discussed below. It is noted that three layers of the epitaxial layers122and three layers of the epitaxial layers124a,124b, and124care alternately arranged as illustrated inFIG.1, which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack120; the number of layers depending on the desired number of channels regions for the transistor. In some embodiments, the number of epitaxial layers124a,124b, and124cis between 2 and 10. As described in more detail below, the epitaxial layers124a,124b, and124cmay serve as channel region(s) for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. The epitaxial layers122in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel region(s) for a subsequently-formed multi-gate device and the thickness is chosen based on device performance considerations. Accordingly, the epitaxial layers122may also be referred to as sacrificial layers, and epitaxial layers124a,124b, and124cmay also be referred to as channel layers. By way of example, epitaxial growth of the layers of the epitaxial stack120may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the epitaxial layers124a,124b, and124cinclude the same material as the substrate110. In some embodiments, the epitaxially grown layers122and124a,124b, and124cinclude a different material than the substrate110. As stated above, in at least some examples, the epitaxial layers122include an epitaxially grown silicon germanium (SiGe) layer and the epitaxial layers124a,124b, and124cinclude an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers122and124a,124b, and124cmay include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers122and124a,124b, and124cmay be chosen based on providing differing oxidation and/or etching selectivity properties. In some embodiments, the epitaxial layers122and124a,124b, and124care substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1018cm−3), where for example, no intentional doping is performed during the epitaxial growth process. Each of the epitaxial layers122has a thickness T. The epitaxial layers122may have substantially constant thickness T. In some embodiments, the thickness T is in a range of about 2 nm to about 30 nm. The (bottom) epitaxial layer124ahas a thickness Ta, the (middle) epitaxial layer124bhas a thickness Tb, and the (top) epitaxial layer124chas a thickness Tc. In some embodiments, the thickness Ta has the highest thickness value among the thicknesses Ta, Tb, and Tc, and/or the thickness Tc has the lowest thickness value among the thicknesses Ta, Tb, and Tc. For example, the thickness Ta is greater than the thickness Tb and Tc, and/or the thickness Tb is greater than the thickness Tc. In some other embodiments, the thickness Ta is greater than the thicknesses Tb and Tc, and the thickness Tb is substantially the same as the thickness Ta. In still some other embodiments, the thickness Ta is substantially the same as the thickness Tb, and the thickness Tb is greater than the thickness Tc. Also, a thickness difference between two adjacent epitaxial layers122is lower than a thickness difference between two adjacent epitaxial layers124a,124band/or124b,124c. Embodiments fall within the present disclosure as long as the thickness Ta is greater than the thickness Tc. In some embodiments, the thicknesses Ta, Tb, and Tc can be controlled by tuning a deposition time/duration of the epitaxial growth processes. For example, a deposition time/duration for depositing the epitaxial layer124ais longer than a deposition time/duration for depositing the epitaxial layers124band/or124c. As the deposition time/duration increases, the thickness of the epitaxial layer increases. On the other hand, deposition times/durations for depositing the epitaxial layers122are substantially the same. Referring toFIG.2, a plurality of semiconductor fins130extending from the substrate110are formed. In various embodiments, each of the fins130includes a substrate portion112formed from the substrate110and portions of each of the epitaxial layers of the epitaxial stack including epitaxial layers122and124a,124b, and124c. The fins130may be fabricated using suitable processes including double-patterning or multi-patterning processes. In some embodiments, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins130by etching initial epitaxial stack120. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. In the illustrated embodiment as illustrated inFIGS.1and2, a hard mask (HM) layer910is formed over the epitaxial stack120prior to patterning the fins130. In some embodiments, the HM layer includes an oxide layer912(e.g., a pad oxide layer that may include SiO2) and a nitride layer914(e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer. The oxide layer912may act as an adhesion layer between the epitaxial stack120and the nitride layer914and may act as an etch stop layer for etching the nitride layer914. In some examples, the HM oxide layer912includes thermally grown oxide, chemical vapor deposition (CVD)-deposited oxide, and/or atomic layer deposition (ALD)-deposited oxide. In some embodiments, the HM nitride layer914is deposited on the HM oxide layer912by CVD and/or other suitable techniques. The fins130may subsequently be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the HM layer910, exposing the photoresist to a pattern, performing post-exposure bake processes, and developing the resist to form a patterned mask including the resist. In some embodiments, patterning the resist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process using light in EUV region, having a wavelength of, for example, about 1-200 nm. The patterned mask may then be used to protect regions of the substrate110, and layers formed thereupon, while an etch process forms trenches102in unprotected regions through the HM layer910, through the epitaxial stack120, and into the substrate110, thereby leaving the plurality of extending fins130. The trenches102may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or combination thereof. Numerous other embodiments of methods to form the fins on the substrate may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack120in the form of the fins130. Next, as illustrated inFIG.3, isolation regions140are formed interposing the fins130. The isolation regions140may include a liner oxide (not shown). The liner oxide may be formed of a thermal oxide formed through a thermal oxidation of a surface layer of the substrate110. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The isolation regions140may also include a dielectric material over the liner oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like. The isolation regions140are then recessed, so that the top portions of semiconductor strips120protrude higher than the top surfaces of the neighboring isolation regions140to form protruding fins120. The etching may be performed using a dry etching process, wherein NH3and NF3are used as the etching gases. During the etching process, plasma may be generated. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of the isolation regions140is performed using a wet etch process. The etching chemical may include diluted HF, for example. Reference is made toFIGS.4A and4B. Dummy gate structures150are formed over the substrate110and are at least partially disposed over the fins130. The portions of the fins130underlying the dummy gate structures150may be referred to as the channel region. The dummy gate structures150may also define source/drain (S/D) regions of the fins130, for example, the regions of the fins130adjacent and on opposing sides of the channel regions. Dummy gate formation operation first forms a dummy gate dielectric layer152over the fins130. Subsequently, a dummy gate electrode layer154and a hard mask which may include multiple layers156and158(e.g., an oxide layer156and a nitride layer158) are formed over the dummy gate dielectric layer152. The hard mask is then patterned, followed by patterning the dummy gate electrode layer152by using the patterned hard mask as an etch mask. In some embodiments, after patterning the dummy gate electrode layer154, the dummy gate dielectric layer152is removed from the S/D regions of the fins130. The etch process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to selectively etch the dummy gate dielectric layer152without substantially etching the fins130, the dummy gate electrode layer154, the oxide mask layer156and the nitride mask layer158. The gate dielectric layers152can be any acceptable dielectric layer, such as silicon oxide, silicon nitride, the like, or a combination thereof, and may be formed using any acceptable process, such as thermal oxidation, a spin process, CVD, or the like. The dummy gate electrodes154can be any acceptable electrode layer, such as comprising polysilicon, metal, the like, or a combination thereof. The gate electrode layer can be deposited by any acceptable deposition process, such as CVD, plasma enhanced CVD (PECVD), or the like. Each of dummy gate structures150crosses over a single one or a plurality of the fins130. Dummy gate structures150may have lengthwise directions perpendicular to the lengthwise directions of the respective fins130. After formation of the dummy gate structures150is completed, gate spacers160are formed on sidewalls of the dummy gate structures150. For example, a spacer material layer is deposited on the substrate110. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, a spacer material layer160is disposed conformally on top and sidewalls of the dummy gate structures150. The spacer material layer160may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer material layer160includes multiple layers, such as a first spacer layer162and a second spacer layer164(illustrated inFIG.4B) formed over the first spacer layer162. By way of example, the spacer material layer160may be formed by depositing a dielectric material over the gate structures150using suitable deposition processes. An anisotropic etching process is then performed on the deposited spacer material layer160to expose portions of the fins130not covered by the dummy gate structure150(e.g., in source/drain regions of the fins130). Portions of the spacer material layer directly above the dummy gate structure150may be completely removed by this anisotropic etching process. Portions of the spacer material layer on sidewalls of the dummy gate structure150may remain, forming gate sidewall spacers, which are denoted as the gate spacers160, for the sake of simplicity. It is noted that although the gate spacers160are multi-layer structures in the cross-sectional view ofFIG.4B, they are illustrated as single-layer structures in the perspective view ofFIG.4Afor the sake of simplicity. Next, as illustrated inFIGS.5A and5B, exposed portions of the semiconductor fins130that extend laterally beyond the gate spacers160(e.g., in source/drain regions of the fins130) are etched by using, for example, an anisotropic etching process that uses the dummy gate structure150and the gate spacers160as an etch mask, resulting in recesses R1into the semiconductor fins130and between corresponding dummy gate structures150. After the anisotropic etching, end surfaces of the epitaxial layers122and channel layers124a,124b, and124cand respective outermost sidewalls of the gate spacers160are substantially coterminous, due to the anisotropic etching. In some embodiments, the anisotropic etching may be performed by a dry chemical etch with a plasma source and a reaction gas. The plasma source may be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), the like, or combinations thereof. In some embodiments, the recesses R1have tapered sidewall profile due to the nature of anisotropic etching of the etching process. Therefore, the channel lengths (in the x-direction as shown inFIG.5B) of the epitaxial layers (or referred to as channel layers)124a,124b, and124cmay be slightly different. For example, the channel length of the epitaxial layer124ais longer than the channel length of the epitaxial layer124b, which is longer than the channel length of the epitaxial layer124c. However, in some other embodiments, the etching conditions of the etching process may be fined-tune to allow the recesses R1having vertical sidewall profile. Further, each of the recesses R1has a height H1and a width W1. Next, inFIGS.6A and6B, the epitaxial layers122are laterally or horizontally recessed by using suitable etch techniques, resulting in lateral recesses R2each vertically between corresponding channel layers124a,124b, and124c. This operation may be performed by using a selective etching process. By way of example and not limitation, the epitaxial layers122are SiGe and the channel layers124a,124b, and124care silicon allowing for the selective etching of the epitaxial layers122. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) that etches SiGe at a faster etch rate than it etches Si. In some embodiments, the selective etching includes SiGe oxidation followed by a SiGeOxremoval. For example, the oxidation may be provided by O3clean and then SiGeOxremoved by an etchant such as NH4OH that selectively etches SiGeOxat a faster etch rate than it etches Si. Moreover, because oxidation rate of Si is much lower (sometimes 30 times lower) than oxidation rate of SiGe, the channel layers124a,124b, and124cis not significantly etched by the process of laterally recessing the epitaxial layers122. As a result, the channel layers124a,124b, and124claterally extend past opposite end surfaces of the epitaxial layers122. InFIGS.7A and7B, inner spacer material layers170are formed to fill the recesses R2left by the lateral etching of the epitaxial layers122discussed above with reference toFIGS.6A and6B. The inner spacer material layer170may be a low-k dielectric material, such as SiO2, SiN, SiCN, or SiOCN, and may be formed by a suitable deposition method, such as ALD. After the deposition of the inner spacer material layer170, an anisotropic etching process may be performed to trim the deposited inner spacer material170, such that only portions of the deposited inner spacer material170that fill the recesses R2left by the lateral etching of the epitaxial layers122are left. After the trimming process, the remaining portions of the deposited inner spacer material are denoted as inner spacers170, for the sake of simplicity. The inner spacers170serve to isolate metal gates from source/drain regions formed in subsequent processing. In the example ofFIGS.7A and7B, sidewalls of the inner spacers170are aligned with sidewalls of the channel layers124a,124b, and124c. InFIG.8, source/drain epitaxial structures180are formed over the source/drain regions S/D of the semiconductor fins130. The source/drain epitaxial structures180may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins130. During the epitaxial growth process, the dummy gate structures150, gate sidewall spacers160and the inner spacers170limit the source/drain epitaxial structures180to the source/drain regions S/D. In some embodiments, the lattice constants of the epitaxy structures180are different from the lattice constant of the epitaxial layers124a,124b, and124c, so that the epitaxial layers124a,124b, and124ccan be strained or stressed by the epitaxy structures180to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the semiconductor fin104. In some embodiments, the source/drain epitaxial structures180may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures180may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures180are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures180. In some exemplary embodiments, the source/drain epitaxial structures180in an n-type transistor include SiP, while those in a p-type include GeSnB and/or SiGeSnB. In embodiments with different device types, a mask, such as a photoresist, may be formed over n-type device regions, while exposing p-type device regions, and p-type epitaxial structures may be formed on the exposed substrate portion112in the p-type device regions. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type device region while exposing the n-type device regions, and n-type epitaxial structures may be formed on the exposed substrate portion112in the n-type device region. The mask may then be removed. Once the source/drain epitaxial structures180are formed, an annealing process can be performed to activate the p-type dopants or n-type dopants in the source/drain epitaxial structures180. The annealing process may be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal annealing (MSA) process or the like. InFIG.9, an interlayer dielectric (ILD) layer210is formed on the substrate110. In some embodiments, a contact etch stop layer (CESL) is also formed prior to forming the ILD layer210. In some examples, the CESL includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other suitable materials having a different etch selectivity than the ILD layer210. The CESL may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer210includes materials such as tetraethylorthosilicate (TEOS)-formed oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials having a different etch selectivity than the CESL. The ILD layer210may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer210, the wafer may be subject to a high thermal budget process to anneal the ILD layer210. In some examples, after depositing the ILD layer210, a planarization process may be performed to remove excessive materials of the ILD layer210. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer210(and CESL layer, if present) overlying the dummy gate structures150and planarizes a top surface of the integrated circuit structure100. In some embodiments, the CMP process also removes hard mask layers156and158(as shown inFIG.8) and exposes the dummy gate electrode layer154. Thereafter, the dummy gate structures150(as shown inFIGS.8and9) are removed first, and then the epitaxial layers (i.e., sacrificial layers)122(as shown inFIG.9) are removed. The resulting structure is illustrated inFIG.10. In some embodiments, the dummy gate structures150are removed by using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the materials in dummy gate structures150at a faster etch rate than it etches other materials (e.g., gate sidewall spacers160and/or ILD layer210), thus resulting in gate trenches GT1between corresponding gate sidewall spacers160, with the epitaxial layers122exposed in the gate trenches GT1. Subsequently, the epitaxial layers122in the gate trenches GT1are removed by using another selective etching process that etches the epitaxial layers122at a faster etch rate than it etches the channel layers124a,124b, and124c, thus forming openings O1between neighboring epitaxial layers (i.e., channel layers)124a,124b, and124c. In this way, the epitaxial layers124a,124b, and124cbecome nanosheets suspended over the substrate110and between the source/drain epitaxial structures180. This operation is also called a channel release process. At this interim processing operation, the openings O1between the epitaxial layers (i.e., nanosheets)124a,124b, and124cmay be filled with ambient environment conditions (e.g., air, nitrogen, etc). In some embodiments, the epitaxial layers124a,124b, and124ccan be interchangeably referred to as nanowires, nanoslabs and nanorings, depending on their geometry. For example, in some other embodiments the epitaxial layers124a,124b, and124cmay be trimmed to have a substantial rounded shape (i.e., cylindrical) due to the selective etching process for completely removing the epitaxial layers122. In that case, the resultant epitaxial layers124a,124b, and124ccan be called nanowires. In some embodiments, the epitaxial layers122are removed by using a selective wet etching process. In some embodiments, the epitaxial layers122are SiGe and the epitaxial layers124a,124b, and124care silicon allowing for the selective removal of the epitaxial layers122. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal includes SiGe oxidation followed by a SiGeOxremoval. For example, the oxidation may be provided by O3clean and then SiGeOxremoved by an etchant such as NH4OH that selectively etches SiGeOxat a faster etch rate than it etches Si. Moreover, because oxidation rate of Si is much lower (sometimes 30 times lower) than oxidation rate of SiGe, the channel layers124a,124b, and124cmay not be significantly etched by the channel release process. It can be noted that both the channel release operation and the previous operation of laterally recessing sacrificial layers (the operation as shown inFIGS.6A and6B) use a selective etching process that etches SiGe at a faster etch rate than etching Si, and therefore these two operations may use the same etchant chemistry in some embodiments. In this case, the etching time/duration of channel release operation is longer than the etching time/duration of the previous operation of laterally recessing sacrificial layers, so as to completely remove the sacrificial SiGe layers. InFIGS.11A and11B, replacement gate structures220are respectively formed in the gate trenches GT1to surround each of the epitaxial layers124a,124b, and124csuspended in the gate trenches GT1. The gate structure220may be the final gate of a GAA FET. The final gate structure may be a high-k/metal gate stack, however other compositions are possible. In some embodiments, each of the gate structures220forms the gate associated with the multi-channels provided by the plurality of epitaxial layers124a,124b, and124c. For example, high-k/metal gate structures220are formed within the openings O1(as illustrated inFIG.11A) provided by the release of epitaxial layers124a,124b, and124c. In various embodiments, the high-k/metal gate structure220includes a gate dielectric layer222formed around the epitaxial layers124a,124b, and124c, a work function metal layer224formed around the gate dielectric layer222, and a fill metal226formed around the work function metal layer224and filling a remainder of gate trenches GT1. The gate dielectric layer222includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer224and/or fill metal layer226used within high-k/metal gate structures220may include a metal, metal alloy, or metal silicide. Formation of the high-k/metal gate structures220may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials. As illustrated in a cross-sectional view ofFIG.11Bthat is taken along a longitudinal axis of a high-k/metal gate structure220, the high-k/metal gate structure220surrounds each of the epitaxial layers124a,124b, and124c, and thus is referred to as a gate of a GAA FET. In some embodiments, the interfacial layer of the gate dielectric layer222may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer222may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer222may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitrides (SiON), and combinations thereof. The work function metal layer224may include work function metals to provide a suitable work function for the high-k/metal gate structures220. For an n-type FinFET, the work function metal layer224may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer134may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal226may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. InFIG.12, optionally, an etching back process is performed to etch back the replacement gate structures220, resulting in recesses over the etched-back gate structures220. In some embodiments, because the materials of the replacement gate structures220have a different etch selectivity than the gate spacers160, the top surfaces of the replacement gate structures220may be at a lower level than the top surfaces of the gate spacers160. Dielectric caps230are optionally formed over the etched-back gate structures220. The dielectric cap layer230includes SiNx, AlxOy, AlON, SiOxCy, SiCxNy, combinations thereof or the like, and is formed by a suitable deposition technique such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), combinations thereof or the like. A CMP process is then performed to remove the cap layer outside the recesses, leaving portions of the dielectric cap layer in the recesses to serve as dielectric caps230. InFIG.13A, source/drain contacts240are formed extending through the ILD layer210(and the CESL layer, if present). Formation of the source/drain contacts240includes, by way of example and not limitation, performing one or more etching processes to form contact openings extending though the ILD layer210to expose the source/drain epitaxy structures180, depositing one or more metal materials overfilling the contact openings, and then performing a CMP process to remove excessive metal materials outside the contact openings. In some embodiments, the one or more etching processes are selective etching that etches the ILD layer210at a faster etch rate than etching the dielectric caps230and the gate spacers160. As a result, the selective etching is performed using the dielectric caps230and the gate spacers160as an etch mask, such that the contact openings and hence the source/drain contacts240are formed self-aligned to the source/drain epitaxy structures180without using an additional photolithography process. In that case, the dielectric caps230allowing for forming the self-aligned contacts240can be called SAC caps230. FIG.13Bis an enlarged view of area A inFIG.13A. Reference is made toFIGS.13A and13B. The integrated circuit structure100includes the substrate110, the channel layers124a,124b, and124cover the substrate110, the gate structure220wraps each of the channel layers124a,124b, and124c, the source/drain epitaxy structures180connected to the channel layers124a,124b, and124c, and the source/drain contacts240respectively over the source/drain epitaxy structures180. The channel layer124cis closed to the source/drain contacts240, and the channel layer124ais far from the source/drain contacts240. When a voltage is applied to one of the source/drain contacts240(or the source contact), paths of driving currents Ia, Ib, and Ic are formed in the integrated circuit structure100. The driving current Ia passes through the channel layer124a, the driving current Ib passes through the channel layer124b, and the driving current Ic passes through the channel layer124c. As shown inFIG.13B, the path of the driving current Ic is shorter than the paths of the driving currents Ib and Ia. Since electrical resistance increases as the current path increases, the driving current Ic is greater than the driving currents Ib and Ia when the channel layers124a,124b, and124chave the same thickness. InFIG.13B, however, the thick channel layers124aand/or124blower the electrical resistance of the channel layers124aand/or124b, such that the driving currents Ib and Ia can be increased. For example, the channel layer124ahas the thickness Ta, the channel layer124bhas the thickness Tb, and the channel layer124chas the thickness Tc. In some embodiments, the thickness Ta has the highest thickness value among the thicknesses Ta, Tb, and Tc, and/or the thickness Tc has the lowest thickness value among the thicknesses Ta, Tb, and Tc. For example, the thickness Ta is greater than the thickness Tb and Tc, and/or the thickness Tb is greater than the thickness Tc. In some other embodiments, the thickness Ta is greater than the thicknesses Tb and Tc, and the thickness Tb is substantially the same as the thickness Ta. In still some other embodiments, the thickness Ta is substantially the same as the thickness Tb, and the thickness Tb is greater than the thickness Tc. Embodiments fall within the present disclosure as long as the thickness Ta is greater than the thickness Tc. In some embodiments, each of the thicknesses Ta, Tb, and Tc is in a range of about 2 nm to about 30 nm. If the thickness Ta (Tb, Tc) is lower than about 2 nm, the driving current Ia (Ib, Ic) may be too low; if the thickness Ta (Tb, Tc) is higher than about 30 nm, the threshold voltage of the gate to turn off the channels is too high. In some embodiments, a difference between the thicknesses Ta and Tc is greater than 0 nm and less than or equal to about 28 nm, e.g., in a range of about 1 nm to about 28 nm. If the difference between the thicknesses Ta and Tc is lower 0 nm, the driving current Ia may be much lower than the driving current Ic; if the difference between the thicknesses Ta and Tc is greater than about 28 nm, the total height of the epitaxial stack120(seeFIG.1) may be too high to form low-aspect-ratio recesses R1(seeFIG.5B). Similarly, in some embodiments, a difference between the thicknesses Ta and Tb is greater than 0 nm and less than or equal to about 28 nm, e.g., in a range of about 1 nm to about 28 nm, and/or a difference between the thicknesses Tb and Tc is greater than 0 nm and less than or equal to about 28 nm, e.g., in a range of about 1 nm to about 28 nm. In some embodiments, spaces between adjacent channel layers (between the channel layers124aand124b, between the channel layers124band124c, and between the channel layers124aand the substrate portion112) has a height H, i.e., the height of the inner spacers170, in a range of about 2 nm to about 30 nm. If the height H is greater than about 30 nm, the aspect ratio of the recesses R1(seeFIG.7B) may be too high; if the height H is less than about 2 nm, the gate structure220may not fill in the spaces between the channel layers, leaving voids therebetween. In some embodiments, the thicknesses Ta, Tb, Tc, and T are related to the aspect ratio (defined for recesses as the ratio of the recess height H1/width W1) of the recess R1(seeFIG.5B). In some embodiments, the aspect ratio of the recess R1is in a range of about 1 to about 5. Once the aspect ratio and the width of the recess R1are determined, the maximum value of the height H1is determined, too. The sum of the thicknesses (Ta+Tb+Tc+3T) is smaller than the maximum value of the height H1. FIGS.14-15Billustrate exemplary cross sectional views of various stages for manufacturing an integrated circuit structure100aaccording to some other embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.14-15B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. The same or similar configurations, materials, processes and/or operation as described withFIGS.1-13Bmay be employed in the following embodiments, and the detailed explanation may be omitted. After the structure as shown inFIG.10is formed, another etching process is performed to over-etch the channel layers124a,124b, and124c, such that the openings O1shown inFIG.10are enlarged to be openings O1′. In some embodiments, the channel layers124a,124b, and124care etched/recessed by an isotropic chemical etching process310. For example, the etching may be performed by an isotropic chemical etching with a plasma source and a reaction gas. The plasma source may be an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), the like, or combinations thereof. In some embodiments, by tuning the power and/or pressure of the plasma in the etching process, the profiles of the channel layers124a,124b, and124ccan be tuned. For example, the higher the channel layer (e.g., the channel layer124c), the more the etching amount of the channel layer. That is, the channel layer124cis over-etched more severely than the channel layer124a. In some embodiments, the etching process may be performed under a plasma source power of about 450 W to about 4800 W, and a pressure of about 20 mTorr to about 12000 mTorr, using O3, O2, O2/N2, O2/H2, O2/Ar, and/or O2/He as etching gases. If the plasma source power is greater than about 4800 W, the channel layers124a,124b, and124cmay be over-etched; if the plasma source power is less than about 450 W, the etching of the channel layers124a,124b, and124cmay be insufficient. If the pressure is less than about 20 mTorr, the etching of the channel layers124a,124b, and124cmay be insufficient; if the pressure is greater than about 12000 mTorr, the channel layers124a,124b, and124cmay be over-etched. Referring toFIG.15A, after the etching process310inFIG.14is completed, the structure ofFIG.14undergoes the processes similar toFIGS.11A-13A. That is, gate structures220are formed in the gate trenches GT1and the openings O1′, the gate structures220are etched back, dielectric caps230are formed above the etched-back gate structures220, openings are formed in the ILD210to expose the source/drain epitaxial structures180, and source/drain contacts240are formed in the openings. Materials and fabrication process details about the aforementioned processes/elements are similar to that shown inFIGS.11A-13A, and thus they are not repeated herein for the sake of brevity. FIG.15Bis an enlarged view of area Aa inFIG.15A. Reference is made toFIGS.15A and15B. The integrated circuit structure100aincludes the substrate110, the channel layers124a,124b, and124cover the substrate110, the gate structure220wraps each of the channel layers124a,124b, and124c, the source/drain epitaxy structures180connected to the channel layers124a,124b, and124c, and the source/drain contacts240respectively over the source/drain epitaxy structures180. The channel layer124cis closed to the source/drain contacts240, and the channel layer124ais far from the source/drain contacts240. As mentioned above, the thick channel layers124aand/or124blower the electrical resistance of the channel layers124aand/or124b, such that the driving currents passing through the channel layers124aand/or124bcan be increased. In some embodiments, the channel layer124aincludes a center portion124acand two edge portions124aeon opposite ends of the center portion124ac. That is, the edge portion124aeinterconnects the center portion124acand the source/drain epitaxial structure180. The gate structure220warps the center portion124ac, and the inner spacer material layers170are in contact with the edge portions124ae. Due to the etching process310shown inFIG.14, the edge portions124aeare thicker than the center portion124ac. The center portion124achas a thickness Ta′, and a thickness difference, which is a sum of the depths D2and D3of the recesses, is between the center portion124acand the edge portion124ae. Similarly, the channel layer124bincludes a center portion124bcand two edge portions124beon opposite ends of the center portion124bc. That is, the edge portion124beinterconnects the center portion124bcand the source/drain epitaxial structure180. The gate structure220warps the center portion124bc, and the inner spacer material layers170are in contact with the edge portions124be. Further, the gate dielectric layer222of the gate structure220extends from the inner sidewall of the edge portion124aeto the inner sidewall of the edge portion124be. Due to the etching process310shown inFIG.14, the edge portions124beare thicker than the center portion124bc. The center portion124bchas a thickness Tb′, and a thickness difference, which is a sum of the depths D4and D5of the recesses, is between the center portion124bcand the edge portion124be. Also, the channel layer124cincludes a center portion124ccand two edge portions124ceon opposite ends of the center portion124cc. That is, the edge portion124ceinterconnects the center portion124ccand the source/drain epitaxial structure180. The gate structure220warps the center portion124cc, and the inner spacer material layers170are in contact with the edge portions124ce. Further, the gate dielectric layer222of the gate structure220extends from the inner sidewall of the edge portion124beto the inner sidewall of the edge portion124ce. Due to the etching process310shown inFIG.14, the edge portions124ceare thicker than the center portion124cc. The center portion124cchas a thickness Tc′, and a thickness difference, which is a sum of the depth D6and D7of the recesses, is between the center portion124ccand the edge portion124ce. In some embodiments, the substrate portion112is also etched to form a recess with a depth D1shallower than the depths D2-D7. As mentioned above, the etching amount of the channel layers124a,124b, and124ccan be tuned, such that the depth D7(D6) is greater than the depth D5(D4), which is greater than the depth D3(D2). Therefore, the thickness Ta′ is greater than the thickness Tb′, which is greater than the thickness Tc′. Other relevant structural and manufacturing details of the integrated circuit structure inFIGS.15A-15Bare substantially the same as or similar to the integrated circuit structure inFIGS.13A-13B, and, therefore, a description in this regard will not be repeated hereinafter. FIGS.16-19Billustrate perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure100bin accordance with some embodiments of the present disclosure. The formed transistors may include a p-type transistor (such as a p-type GAA FET) and/or an n-type transistor (such as an n-type GAA FET) in accordance with some exemplary embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.16-19B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIGS.16and17Aare perspective views of some embodiments of the integrated circuit structure100bat intermediate stages during fabrication.FIGS.17B,18, and19Aare cross-sectional views of some embodiments of the integrated circuit structure100bat intermediate stages during fabrication along a first cut (e.g., cut X-X inFIG.17A), which is along a lengthwise direction of the channel and perpendicular to a top surface of the substrate.FIG.19Bis an enlarged view of area Ab inFIG.19A. Referring toFIG.16, an epitaxial stack120is formed over the substrate110. Materials and process details about the epitaxial stack120are similar to that of the epitaxial stack120discussed inFIG.1, and thus they are not repeated for the sake of brevity. The (bottom) epitaxial layer124ahas a thickness Ta, the (middle) epitaxial layer124bhas a thickness Tb, and the (top) epitaxial layer124chas a thickness Tc. InFIG.16, the thicknesses Ta, Tb, and Tc are substantially the same. In some embodiments, each of the thicknesses Ta, Tb, and Tc is in a range of about 2 nm to about 30 nm. Similarly, each of the epitaxial layers122has a thickness T. The epitaxial layers122may have substantially constant thickness T. That is, a thickness difference between two adjacent epitaxial layers122is substantially the same as a thickness difference between two adjacent epitaxial layers124a,124band/or124b,124c. Referring toFIGS.17A and17B, after the deposition process inFIG.16is complete, the structure ofFIG.16undergoes the processes similar toFIGS.2-7B. That is, the epitaxial stack120is patterned to be semiconductor fins130, isolation structure140are formed over the substrate110, dummy gate structures150are formed over the substrate110and are at least partially disposed over the fins130, gate spacers160are formed on sidewalls of the dummy gate structures150, exposed portions of the semiconductor fins130that extend laterally beyond the gate spacers160are etched to form the recesses R1, the epitaxial layers122are laterally or horizontally recessed to form the recesses R2, and inner spacer material layers170are formed to fill the recesses R2. Materials and fabrication process details about the aforementioned processes/elements are similar to that shown inFIGS.2to7B, and thus they are not repeated herein for the sake of brevity. Referring toFIG.18, after the inner spacer material layers170are formed, the structure ofFIGS.17A and17Bundergoes the process similar toFIGS.8-10. That is, source/drain epitaxial structures180are formed in the recesses R1and over the source/drain regions S/D of the semiconductor fins130, (optional CESL and) ILD210is formed over the substrate110, dummy gate structures150(as shown inFIG.17A) are removed first, and then the epitaxial layers (i.e., sacrificial layers)122(as shown inFIG.17B) are removed. Subsequently, another etching process is performed to over-etch the channel layers124a,124b, and124cto form openings O1′. The channel layers124a,124b, and124care then etched/recessed by an isotropic chemical etching process310. In some embodiments, the etching may be performed by an isotropic chemical etching with a plasma source and a reaction gas. The plasma source may be an inductively coupled plasma (ICR) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), the like, or combinations thereof. In some embodiments, by tuning the power and/or pressure of the plasma in the etching process, the profiles of the channel layers124a,124b, and124ccan be tuned. For example, the higher the channel layer (e.g., the channel layer124c), the more the etching amount of the channel layer. That is, the channel layer124cis over-etched more severely than the channel layer124a. In some embodiments, the etching process may be performed under a plasma source power of about 450 W to about 4800 W, and a pressure of about 20 mTorr to about 12000 mTorr, using O3, O2, O2/N2, O2/H2, O2/Ar, and/or O2/He as etching gases. If the plasma source power is greater than about 4800 W, the channel layers124a,124b, and124cmay be over-etched; if the plasma source power is less than about 450 W, the etching of the channel layers124a,124b, and124cmay be insufficient. If the pressure is less than about 20 mTorr, the etching of the channel layers124a,124b, and124cmay be insufficient; if the pressure is greater than about 12000 mTorr, the channel layers124a,124b, and124cmay be over-etched. Referring toFIG.19A, after the etching process310inFIG.18is complete, the structure ofFIG.18undergoes the processes similar toFIGS.11A-13A. That is, gate structures220are formed in the gate trenches GT1and the openings O1′, the gate structures220are etched back, dielectric caps230are formed above the etched-back gate structures220, openings are formed in the ILD210to expose the source/drain epitaxial structures180, and source/drain contacts240are formed in the openings. Materials and fabrication process details about the aforementioned processes/elements are similar to that shown inFIGS.11A-13A, and thus they are not repeated herein for the sake of brevity. FIG.19Bis an enlarged view of area Ab inFIG.19A. Reference is made toFIGS.19A and19B. The integrated circuit structure100bincludes the substrate110, the channel layers124a,124b, and124cover the substrate110, the gate structure220wraps each of the channel layers124a,124b, and124c, the source/drain epitaxy structures180connected to the channel layers124a,124b, and124c, and the source/drain contacts240respectively over the source/drain epitaxy structures180. The channel layer124cis closed to the source/drain contacts240, and the channel layer124ais far from the source/drain contacts240. As mentioned above, the thick channel layers124aand/or124blower the electrical resistance of the channel layers124aand/or124b, such that the driving currents passing through the channel layers124aand/or124bcan be increased. In some embodiments, the channel layer124aincludes a center portion124acand two edge portions124aeon opposite ends of the center portion124ac. The edge portions124aeare thicker than the center portion124ac. The center portion124achas a thickness Ta′, and a thickness difference, which is a sum of the depths D2and D3of the recesses, is between the center portion124acand the edge portion124ae. Similarly, the channel layer124bincludes a center portion124bcand two edge portions124beon opposite ends of the center portion124ac. The edge portions124beare thicker than the center portion124bc. The center portion124bchas a thickness Tb′, and a thickness difference, which is a sum of the depths D4and D5of the recesses, is between the center portion124bcand the edge portion124be. Also, the channel layer124cincludes a center portion124ccand two edge portions124ceon opposite ends of the center portion124cc. The edge portions124ceare thicker than the center portion124cc. The center portion124cchas a thickness Tc′, and a thickness difference, which is a sum of the depths D6and D7of the recesses, is between the center portion124ccand the edge portion124ce. In some embodiments, the substrate portion112is also etched to form a recess with a depth D1shallower than the depths D2-D7. As mentioned above, the etching amount of the channel layers124a,124b, and124ccan be tuned, such that the depth D7(D6) is greater than the depth D5(D4), which is greater than the depth D3(D2). Therefore, the thickness Ta′ is greater than the thickness Tb′, which is greater than the thickness Tc′. Other relevant structural and manufacturing details of the integrated circuit structure inFIGS.19A-19Bare substantially the same as or similar to the integrated circuit structure inFIGS.13A-13B and15A-15B, and, therefore, a description in this regard will not be repeated hereinafter. Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that the channel layers with different thicknesses can improve the driving currents of the integrated circuit structures. Another advantage is that the thicknesses of the channel layers can be determined when depositing the channel layer. Yet another advantage is that an over-etching process can be added to further fine tune the thicknesses of the channel layers. Further, the thicknesses can be determined according to different applications. According to some embodiments, a device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer. According to some embodiments, a method includes forming an epitaxial stack over a substrate. The epitaxial stack includes a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially over the substrate. A thickness of the first channel layer is greater than a thickness of the second channel layer. The epitaxial stack is patterned to be a fin structure. A dummy gate structure is formed across the fin structure such that the dummy gate structure covers a first portion of the fin structure while second portions of the fin structure are exposed. The exposed second portions of the fin structure are removed. Source/drain epitaxial structures are formed on opposite end surfaces of the first and second channel layers in the first portion of the fin structure. The dummy gate structure is removed to expose the first portion of the fin structure. The first and second sacrificial layers in the exposed first portion of the fin structure are removed while leaving the first and second channel layers in the exposed first portion of the fin structure suspended above the substrate. A gate structure is formed to surround each of the suspended first and second channel layers. According to some embodiments, a method includes forming an epitaxial stack over a substrate. The epitaxial stack comprises a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially over the substrate. The epitaxial stack is patterned into a fin structure extending along a first direction. A dummy gate structure is formed to extend across the fin structure along a second direction substantially perpendicular to the first direction. Gate spacers are respectively on opposite sides of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. The first and second sacrificial layers are selectively removed from the gate trench while leaving the first and second channel layers suspended in the gate trench. After selectively removing the first and second sacrificial layers, recesses are respectively formed in the first and second channel layers. A depth of the recess in the second channel layer is greater than a depth of the recess in the first channel layer. After forming the recesses respectively in the first and second channel layers, a gate structure is formed in the gate trench and the recesses. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 63,980 |
11942557 | It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numbers may be repeated among the figures to indicate corresponding or analogous features. DETAILED DESCRIPTION Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention. A nanosheet field effect transistor (hereinafter “FET”) may be formed from alternating layers of silicon and silicon germanium, which are then formed into nanosheets. A gate all around structure may be formed on all vertical sides and on a horizontal top surface of a section of the nanosheets. Source-drain structures may be formed at the opposite ends of the nanosheet structures. The present invention relates, generally, to the field of semiconductor manufacturing, and more particularly to fabricating a nanosheet FET with an enhanced bottom dielectric isolation using an integrated source/drain etch stop layer. Parasitic source-to-drain “punch-through” leakage through the substrate increases as the transistor gate length is scaled to 12 nm. Due to the parasitic channel below the nanosheet stack, the source drain leakage current is very challenging for nanosheet transistors to suppress. The bottom dielectric isolation (BDI) layer which separates epitaxy of the source and of the drain from touching the substrate provides a vital solution to block the leakage in the sub-nanosheet region by adding an insulator layer beneath the source drain and channel region. A bottom isolation layer intended to isolate a source drain region from a substrate may be damaged by spacer and inner spacer formation, source/drain contact patterning and epitaxial pre-cleans. This damage can erode the BDI thickness leading back to increased source-drain leakage and degradation in device performance. An enhanced bottom isolation is needed to withstand the exposure to these aggressive processes in order to ensure the isolation of source and drain region from the substrate. Alternating layers of a sacrificial semiconductor material and semiconductor channel material may be formed over a stack sacrificial layer and then formed into parallel nanosheet stacks. A sacrificial gate may be formed over the nanosheet stack, perpendicular to a length of the nanosheet stack. The stack sacrificial layer may be removed forming an opening. A first layer may be formed along an upper horizontal surface of the opening and along a lower horizontal surface of the opening. A second layer may fill a remaining portion of the opening, between two layers of the first layer. The first layer and the second layer may be referred to as an enhanced bottom dielectric isolation. Vertically aligned portions of the stack sacrificial layer and the nanosheet stack may be removed between adjacent sacrificial gates. A portion of the sacrificial semiconductor material layers of the nanosheet stack may be removed adjacent to where the portion of the nanosheet stack was removed, resulting in removal of the first layer above the second layer. An upper horizontal surface of the second layer may be exposed between adjacent sacrificial gates. The second layer protects the first layer above the substrate from several subsequent repeated processes such as wet etching and pre-cleans. An inner spacer may be formed where the portion of the sacrificial semiconductor material layers were removed. A source drain may be formed at the ends of the nanosheet stacks. The second layer and the first layer isolate the source drain from the substrate, preventing epitaxial growth from the substrate, reducing current leakage through the substrate. The sacrificial gate may be removed and a remaining portion of sacrificial semiconductor material layers of the nanosheet stack may be removed. A work function metal may be formed, filling the openings where the sacrificial material layers were removed and where the sacrificial gate was removed. Embodiments of the present invention disclose a structure and a method of forming an enhanced bottom dielectric isolation utilizing an integrated source/drain etch stop layer are described in detail below by referring to the accompanying drawings inFIGS.1-9, in accordance with an illustrative embodiment. Referring now toFIG.1, a semiconductor structure100(hereinafter “structure”) at an intermediate stage of fabrication is shown according to an exemplary embodiment.FIG.1is a cross-sectional view of the structure100. The structure100may include alternating layers of sacrificial semiconductor material and semiconductor channel material stacked one on top of another, which may collectively be referred to as a nanosheet stack. The nanosheet stack may be on a substrate10. A sacrificial gate18covered by a hard mask20may be on the nanosheet stack. It should be noted that, while a limited number of alternating layers are depicted, any number of alternating layers may be formed. The substrate10may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium arsenide. Typically, the substrate10may be approximately, but is not limited to, several hundred microns thick. In other embodiments, the substrate10may be a layered semiconductor such as a silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer, separates a base substrate from a top semiconductor layer. The alternating layers of sacrificial semiconductor material and semiconductor channel material may include a nanosheet stack sacrificial layer12(hereinafter “stack sacrificial layer”) on the substrate10, covered by a sacrificial semiconductor material layer14(hereinafter “sacrificial layer”), covered by a semiconductor channel material layer16(hereinafter “channel layer”), covered by a sacrificial layer14, covered by a channel layer16, covered by a sacrificial layer14, covered by a channel layer16. The sacrificial gate18may be covered by a gate hard mask20may be above the uppermost channel layer16. The stack sacrificial layer12, may, for example, be silicon germanium with a germanium concentration about 50 atomic percent, although percentages greater than 50 percent and less than 50 percent may be used. The stack sacrificial layer12can be formed using an epitaxial growth technique. The stack sacrificial layer12will subsequently be removed selective to the remaining alternating layers, as described below. The terms “epitaxially growing and/or depositing” and “epitaxially grown and/or deposited” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition technique, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same crystalline characteristics as the deposition surface on which it is formed. Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature for epitaxial deposition typically ranges from approximately 550° C. to approximately 900° C. Although higher temperature typically results in faster deposition, the faster deposition may result in crystal defects and film cracking. The epitaxial growth of first and second semiconductor materials that provide the sacrificial semiconductor material layers and the semiconductor channel material layers, respectively, can be performed utilizing any well-known precursor gas or gas mixture. Carrier gases like hydrogen, nitrogen, helium and argon can be used. Each sacrificial layer14is composed of a first semiconductor material which differs in composition from at least an upper portion of the substrate10, the channel layers16and the stack sacrificial layer12. In an embodiment, each sacrificial layer14may be a silicon-germanium semiconductor alloy and have a germanium concentration less than 50 atomic percent. In another example, each sacrificial layer14may have a germanium concentration ranging from about 20 atomic percent to about 40 atomic percent. Each sacrificial layer14can be formed using known deposition techniques or an epitaxial growth technique as described above. Each channel layer16is composed of a second semiconductor material which differs in composition from at least the upper portion of the substrate10, the sacrificial layers14and the stack sacrificial layer12. Each channel layer16has a different etch rate than the first semiconductor material of sacrificial layer14and has a different etch rate than the stack sacrificial layer12. The sacrificial layer14has a different etch rate than the stack sacrificial layer12. The second semiconductor material can be, for example, silicon. The second semiconductor material, for each channel layer16, can be formed using known deposition techniques or an epitaxial growth technique as described above. The alternating layers of sacrificial layer14, channel layer16and the stack sacrificial layer12can be formed by sequential epitaxial growth of the nanosheet stack sacrificial layer material and alternating layers of the first semiconductor material and the second semiconductor material. The stack sacrificial layer12may have a thickness ranging from about 5 nm to about 15 nm. The sacrificial layers14may each have a thickness ranging from about 5 nm to about 12 nm, while the channel layers16may each have a thickness ranging from about 3 nm to about 12 nm. Each sacrificial layer14may have a thickness that is the same as, or different from, a thickness of each channel layer16. In an embodiment, each sacrificial layer14has an identical thickness. In an embodiment, each channel layer16has an identical thickness. The stack sacrificial layer12, the alternating layers of sacrificial layers14and channel layers16may have been formed into nanosheet stacks, by methods known in the art, by removal of portions of each layer. A trench may be formed between each nanosheet stack by an anisotropic etching technique, such as, for example, reactive ion etching (RIE), and stopping on etching a portion of the substrate10for subsequent formation of a shallow trench isolation region (hereinafter “STI”), not shown, between each nanosheet stack. Each nanosheet stack may include the stack sacrificial layer12covered by the alternating layers of sacrificial layers14and channel layers16. InFIG.1, and only by way of an example, the nanosheet stack includes three layers of sacrificial layers14alternating with three layers of the channel layers16. The material stacks that can be employed in embodiments of the present invention are not limited to the specific embodiment illustrated inFIGS.1-9. There may be any number of nanosheet stacks on the structure100. The nanosheet stack is used to produce a gate all around device that includes vertically stacked semiconductor channel material nanosheets for a positive channel Field Effect Transistor (hereinafter “p-FET”) or a negative channel Field Effect Transistor (hereinafter “n-FET”) device. The cross-sectional view ofFIG.1runs along a length of the nanosheet stack, where the nanosheet stack runs from left to right. The cross-sectional view ofFIG.1is perpendicular to the sacrificial gate18, which crosses over the nanosheet stack perpendicular to the length of the nanosheet stack. The sacrificial gate18may include a single sacrificial material or a stack of one or more sacrificial materials. The at least one sacrificial material can be formed by forming a blanket layer (or layers) of a material (or various materials) and then patterning the material (or various materials) by lithography and an etch. The sacrificial gate18can include any material including, for example, polysilicon, amorphous silicon, or multilayered combinations thereof. The sacrificial gate18can be formed using any deposition technique including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin on techniques. Optionally, a gate dielectric layer and a gate cap may be formed as part of the sacrificial gate18in accordance with known techniques. As shown inFIG.1, there is one sacrificial gate18. In an embodiment, there may be any number of sacrificial gates18formed. In an embodiment, the sacrificial gate18is deposited with a thickness sufficient to fill, or substantially fill, the spaces between adjacent nanosheet structures, not shown, and cover an upper surface of the channel layer16of the nanosheet stack. The sacrificial gate18may be adjacent to vertical side surfaces of the nanosheet stack, not shown, including vertical side surfaces of the stack sacrificial layer12, the channel layers16and the stack sacrificial layers14. A height of the sacrificial gate18may be much thicker than the underlying structure and may have a height between 100 nm and 150 nm about the nanosheet stack. The gate hard mask20may be formed over a horizontal upper surface of the sacrificial gate18, by methods known in the art. The gate hard mask20may have vertical side surfaces which align with vertical side surfaces of the sacrificial gate18. Referring now toFIG.2, the structure100is shown according to an exemplary embodiment. As shown inFIG.2, the stack sacrificial layer12may be selectively removed and an opening22may be formed where the stack sacrificial layer12was removed. The stack sacrificial layer12may be removed selective to the substrate10, the sacrificial layers14, the channel layers16, the sacrificial gate18and the gate hard mask20. For example, a highly selective dry etch process can be used to selectively remove the stack sacrificial layer12. Referring now toFIG.3, the structure100is shown according to an exemplary embodiment. As shown inFIG.3, a first layer24and a second layer26may be formed. The first layer24may form along an upper surface of the opening22, along a lower surface of the opening22and cover exposed surfaces of the structure100. The first layer24may cover exposed horizontal surfaces of the uppermost channel layer16, vertical side surfaces of the sacrificial gate18, and vertical side surfaces and an upper surface of the gate hard mask20. The first layer24may not entirely fill the opening22, leaving an innermost portion of the opening22open for deposition of the second layer26in a remainder of the opening22, with layers of the first layer24above the second layer26and below the second layer26, between the substrate10and the lowermost sacrificial layer14. Materials for the first layer24may include, but are not limited to a low-k material, for example silicon nitride (SiN), silicon boron carbonitride (SiBCN), and silicon oxycarbonitride (SiOCN). The first layer24may be deposited using typical deposition techniques, for example, atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). The first layer24may have a thickness of about 3 nm, although thicknesses greater than and less than 3 nm may be acceptable. The second layer26may fill in a remaining portion of the opening22and cover exposed surfaces of the structure100. The second layer26may cover the first layer24over the horizontal surface of the uppermost channel layer16, cover the first layer24over the vertical side surfaces of the sacrificial gate18, and cover the first layer24on the vertical side surfaces and the upper surface of the gate hard mask20. Materials for the second layer26may include, but are not limited, silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon carbide (SiC), and aluminum oxide (AlOx). The second layer26may be deposited using typical deposition techniques, for example, atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). The second layer26may have a thickness of about 3 nm, although thicknesses greater than and less than 3 nm may be acceptable. The resulting structure may include the first layer24over the substrate10, the second layer26over the first layer24, the first layer24over the second layer26, all beneath the nanosheet stack of alternating sacrificial layers14and channel layers16. Referring now toFIG.4, the structure100is shown according to an exemplary embodiment. As shown inFIG.4, portions of the second layer26may be removed and additional material for the first layer24may be formed. The second layer26may be selectively removed from uppermost surfaces of the structure100. The second layer26may be removed from over the first layer24over the horizontal surface of the uppermost channel layer16, from over the first layer24over the vertical side surfaces of the sacrificial gate18, and from over the first layer24on the vertical side surfaces and the upper surface of the gate hard mask20. The second layer26may remain between the2first layers24below the nanosheet stack of alternating sacrificial layers14and channel layers16. The second layer26may be removed selective to the substrate10, the sacrificial layers14, the channel layers16, the sacrificial gate18and the gate hard mask20. For example, a wet etch or selective dry etching technique can be used to selectively remove the second layer26. The second layer26may remain between the2first layers24below the nanosheet stack of alternating sacrificial layers14and channel layers16due to being sandwiched between the2first layers24. Additional material for the first layer24may be formed on exposed surfaces of the structure100, resulting in a resulting first layer24which is greater than the initial deposition of the first layer24. The additional material for the first layer24may be deposited over the first layer24over the horizontal surface of the uppermost channel layer16, over the first layer24over the vertical side surfaces of the sacrificial gate18, and over the first layer24on the vertical side surfaces and the upper surface of the gate hard mask20. Material and deposition techniques may be as described above for the first layer24. Referring now toFIG.5, the structure100is shown according to an exemplary embodiment. As shown inFIG.5, portions of the first layer24and portions of the nanosheet stack may be removed. A portion of the first layer24above the gate hard mask20and above the nanosheet stack, as well has portions of the alternating sacrificial layers14and channel layers16may be removed via etching using an anisotropic etching technique, such as, for example, reactive ion etching (RIE), and stopping at the second layer26. The portions of the alternating sacrificial layers14and channel layers16are removed between adjacent sacrificial gates18, not shown. A portion of the first layer24may also be removed between adjacent sacrificial gates18. A portion of the second layer26may have an upper horizontal surface exposed between adjacent sacrificial gates18. There may be several removal steps. Remaining portions of the first layer24surrounding the sacrificial gate18, remaining portions of the alternating sacrificial layers14and channel layers16, and an additional remaining portion of the first layer24between the nanosheet stack and the second layer26may be vertically aligned. In an embodiment, the second layer26protects the first layer24between the nanosheet stack and the second layer26from processes such as etching of the source drain, nanosheet stack recess and inner spacer etch back, and pre-clean steps prior to forming an inner spacer as shown inFIG.6to prevent further etching of the first layer24above the substrate10between the sacrificial gates18. Referring now toFIG.6, the structure100is shown according to an exemplary embodiment. As shown inFIG.6, a further portion of each of the sacrificial layers14may be removed using methods known in the art. An inner spacer28may be formed within the indented cavity of the sacrificial layers14. Outer vertical sides of the inner spacer28may vertically align with the channel layers16and first layer24and inner vertical sides of the inner spacer28may vertically align with remaining portions of the sacrificial layers14. The inner spacer28may each be formed after several processes, including for example, conformally depositing or growing a dielectric and performing an isotropic etch process. The inner spacer28may include any dielectric material such as silicon nitride and may include a single layer or may include multiple layers of dielectric material. Referring now toFIG.7, the structure100is shown according to an exemplary embodiment. As shown inFIG.7, a source drain30may be formed where the vertical portion of each nanosheet stack was removed, and partially recessed. The source drain30may be epitaxially grown in a region on between adjacent sacrificial gates18and gate hard masks20. The source drain30may be in direct contact with end portions of the channel layers16of the nanosheet stack and end portions of the inner spacer28surrounding the sacrificial layers14. The source drain30may be formed over the second layer26. In an embodiment, the source drain30is formed over the second layer26. The second layer26will isolate the source drain30from the substrate10, preventing epitaxial growth from the substrate10. This critical feature withstands epitaxial patterning and pre-cleaning steps to prevent erosion and thinning. This will reduce current leakage through the substrate10. Referring now toFIGS.8and9, the structure100is shown according to an exemplary embodiment. As shown inFIGS.8and9, a dielectric34may be formed, the sacrificial gate18may be removed, the sacrificial layers14may be removed and a work function metal (hereinafter “WFM”)32may be formed. The WFM32is formed in each cavity of the nanosheet stack where the sacrificial layers14were removed, and the WFM32surrounds suspended portions of the channel layers16. The WFM32may fill a remainder of openings where the sacrificial gate18was removed between adjacent first layers24over the nanosheet stack. The WFM32may be deposited using typical deposition techniques, for example, atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). In an embodiment, the work function metal of a p-FET device may include a metal nitride, for example, titanium nitride or tantalum nitride, titanium carbide titanium aluminum carbide, or other suitable materials known in the art. In an embodiment, the work function metal of an n-FET device may include, for example, titanium aluminum carbide or other suitable materials known in the art. In an embodiment, the work function metal may include one or more layers to achieve desired device characteristics. After forming the WFM32, a chemical mechanical polishing (CMP) technique may be used to remove excess material and polish upper surfaces of the structure100such that upper horizontal surfaces of the WFM32, the first layer24and the dielectric34are coplanar. In an embodiment, forming the stack sacrificial layer12beneath the nanosheet stack of alternating sacrificial layers14and channel layers16and then replacing the stack sacrificial layer12with the second layer26between two layers of the first layer24has several benefits. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. | 27,318 |
11942558 | DETAILED DESCRIPTION Certain example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. It should be noted that the figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”). As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments, unless indicated otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. FIG.1is a plan view illustrating a semiconductor device according to example embodiments.FIG.2Ashows cross-sectional views taken along line A-A′ and line B-B′ ofFIG.1.FIG.2Bshows cross-sectional views taken along line C-C′ and line D-D′ ofFIG.1.FIG.2Cshows cross-sectional views taken along line E-E′ and line F-F′ ofFIG.1. Referring toFIGS.1and2A to2C, a first transistor TR1, a second transistor TR2and a third transistor TR3may be provided on a substrate100. The substrate100may be a semiconductor substrate. For example, the substrate100may include a silicon substrate, a germanium substrate or a silicon-on-insulator (SOI) substrate. The substrate100may include a transistor region TA. The transistor region TA may include the first to third transistors TR1-TR3, and may be a part of a memory cell region that may include a plurality of memory cells to store data. For example, a six-transistor (6T)-static random access memory (SRAM) memory cell including six transistors may be provided on the substrate100, and each of the first to third transistors TR1-TR3may be one of the six transistors included in the 6T-SRAM memory cell. The transistor region TA may include the first to third transistors TR1-TR3, and may be a part of a logic cell region including logic transistors constituting a logic circuit. For example, the transistor region TA may include the logic transistors constituting a processor core or an input/output (I/O) terminal. Each of the first to third transistors TR1-TR3may be one of the logic transistors constituting a processor core or an I/O terminal. However, example embodiments are not limited thereto. Each of the first to third transistors TR1-TR3may include a gate structure extending in a first direction d1, source and drain regions SD spaced apart from each other and having the gate structure interposed therebetween, and a channel region that connects the source and drain regions SD to each other. The gate structure may include a gate electrode, a gate insulation layer extending along a sidewall and a lower surface of the gate electrode, a gate spacer GS spaced apart from the gate electrode and having the gate insulation layer interposed therebetween, and a gate capping pattern GP that covers the gate electrode and the gate insulation layer. A lower surface of the gate spacer GS may be located at a level that is substantially the same as a level of a lower surface of the gate insulation layer. An upper surface of the gate insulation layer and an upper surface of the gate electrode may be in contact with a lower surface of the gate capping pattern GP. The gate electrode may include conductive metal nitrides and/or metals. For example, the gate electrode may include conductive metal nitrides such as TiN, WN and TaN, and metals such as Ti, W and Ta. The first to third transistors TR1-TR3may include a first gate electrode GE1, a second gate electrode GE2and a third gate electrode GE3, respectively. The first to third gate electrodes GE1-GE3may have the same work function. For example, the first to third gate electrodes GE1-GE3may include the same material. The first to third transistors TR1-TR3may include a first gate insulation pattern GI1, a second gate insulation pattern GI2and a third gate insulation pattern GI3, respectively. The first to third gate insulation patterns GI1-GI3may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a high-k dielectric layer. A dielectric constant of the high-k dielectric layer may be greater than that of a silicon oxide layer. For example, the high-k dielectric layer may include a hafnium oxide layer, an aluminum oxide layer or a tantalum oxide layer. Each of the gate spacer GS and the gate capping pattern GP may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. The transistor region TA may include an n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) region or a p-channel metal-oxide-semiconductor field effect transistor (PMOSFET) region. The first to third transistors TR1-TR3may have the same conductivity type. The first to third transistors TR1-TR3may include a first active region ACT1, a second active region ACT2and a third active region ACT3, respectively. The first to third active regions ACT1-ACT3may include a first channel region CH1, a second channel region CH2and a third channel region CH3, respectively. The first to third active regions ACT1-ACT3may include the source and drain regions SD spaced apart from each other and having the channel region interposed therebetween. Each of the source and drain regions SD may be an epitaxial pattern that is grown using the substrate100as a seed layer. When the transistor region TA is the NMOSFET region, the source and drain regions SD may include a material that provides tensile strain to the first to third channel regions CH1, CH2and CH3. For example, the source and drain regions SD may include a silicon carbide layer (SiC layer) whose lattice constant is less than that of silicon (Si), or a silicon layer whose lattice constant is substantially equal to that of the substrate100. When the transistor region TA is the PMOSFET region, the source and drain regions SD may include a material that provides compressive strain to the first to third channel regions CH1, CH2and CH3. For example, the source and drain regions SD may include a silicon germanium layer (SiGe layer) whose lattice constant is greater than that of silicon (Si). An interlayer insulating layer123may be provided on the source and drain regions SD. The gate structure may be provided in the interlayer insulating layer123. An upper surface of the interlayer insulating layer123may be substantially coplanar with an upper surface of the gate capping pattern GP. The interlayer insulating layer123may include a silicon oxide layer or a silicon oxynitride layer. The first to third transistors TR1-TR3may be configured to have threshold voltages that are different from each other. For example, the threshold voltage of the third transistor TR3may be greater than that of the first transistor TR1, and the threshold voltage of the second transistor TR2may be greater than that of the third transistor TR3. For example, the second transistor TR2may have a threshold voltage of about 0.30 V to about 0.59 V, the third transistor TR3may have a threshold voltage of about 0.21 V to about 0.29 V, and the first transistor TR1may have a threshold voltage of about 0.15 V to about 0.20 V. However, example embodiments are not limited thereto. The first to third channel regions CH1-CH3may have substantially the same doping concentrations. The gate insulation patterns of the first to third transistors TR1-TR3may include the same material and may be formed at the same time, which will be described later. Each of the second and third channel regions CH2and CH3may include a plurality of channel portions spaced apart from each other in a direction perpendicular to the substrate100. For example, the second channel region CH2may include three second channel portions NS2, and the third channel region CH3may include three third channel portions NS3. The respective number of the second and third channel portions NS2and NS3is not limited to three. The second channel portions NS2and the third channel portions NS3may be spaced apart from an upper surface of the substrate100. The number of the second channel portions NS2may be the same as the number of the third channel portions NS3. Each of the second channel portions NS2may be located at substantially the same level as each of the third channel portions NS3. The second channel portion NS2and the third channel portion NS3may have the same thickness and include the same material. For example, the second and third channel portions NS2and NS3may include at least one of Si, SiGe and Ge. The second channel portions NS2may have, for example but not limited to, the same thickness. The third channel portions NS3may have, for example but not limited to, the same thickness. The second gate electrode GE2may extend between the second channel portions NS2and between the substrate100and the second channel portion NS2that is most adjacent to the substrate100. Barrier insulation patterns106may be provided between the source and drain regions SD and the second channel portions NS2. The third gate electrode GE3may extend between the third channel portions NS3and between the substrate100and the third channel portion NS3that is most adjacent to the substrate100. The barrier insulation patterns106may be provided between the source and drain regions SD and the third channel portions NS3. The barrier insulation patterns106may be spaced apart from each other and have the second channel portions NS2or the third channel portions NS3interposed therebetween. The second gate insulation pattern GI2may extend between the second gate electrode GE2and the second channel portions NS2. The third gate insulation pattern GI3may extend between the third gate electrode GE3and the third channel portions NS3. That is, the second and third transistors TR2and TR3may be a gate-all-around field effect transistor including a channel region whose outer peripheral portion is surrounded by a gate electrode. A width of each of the third channel portions NS3may be substantially equal to each other, and a width of each of the second channel portions NS2may be substantially equal to each other. A third width W3of each of the third channel portions NS3may be greater than a second width W2of each of the second channel portions NS2in the first direction d1(e.g., in a direction of a channel width). For example, the third width W3may be about 1.2 to about 3 times greater than the second width W2. A length of each of the third channel portion NS3may be substantially equal to that of each of the second channel portions NS2in a second direction d2(e.g., in a direction of a channel length), the second direction d2crossing the first direction d1on the substrate100. Due to a difference between the third width W3and the second width W2, the threshold voltage of the second transistor TR2may be greater than that of the third transistor TR3. That is, in the case where the channel width of the transistor is decreased to a nano-sized level, an energy state of charge can be high by quantum confinement effect, and thus an energy band gap may be widened. The first channel region CH1of the first transistor TR1may have a fin shape protruding from the upper surface of the substrate100. The first channel region CH1may include the same material as the second and third channel regions CH2and CH3. A first width W1of the first channel region CH1may be less than or equal to the second width W2of the second channel region CH2(or the second channel portion NS2). However, example embodiments are not limited thereto. The threshold voltage of the first transistor TR1may be less than those of the second and third transistors TR2and TR3. According to example embodiments, a plurality of transistors having threshold voltages different from each other may be provided in a semiconductor device. For example, the plurality of transistors having different threshold voltages may be provided by varying widths of channel regions. Furthermore, a transistor including a plurality of channel portions that are spaced apart from each other in a direction perpendicular to a substrate, and a transistor including a fin-shaped channel portion may be provided together in the semiconductor device. Accordingly, the plurality of transistors having different threshold voltages may be provided in the semiconductor device. FIGS.3A,4A,5A,6A,7A and8Aare cross-sectional views taken along lines A-A′ and B-B′ ofFIG.1.FIGS.3B,4B,5B,6B,7B and8Bare cross-sectional views taken along lines C-C′ and D-D′ ofFIG.1.FIGS.3C,4C,5C,6C,7C and8Care cross-sectional views taken along lines E-E′ and F-F′ ofFIG.1. Hereinafter, a method of manufacturing a semiconductor device according to example embodiments will be described with reference toFIGS.1and3A-8C. Referring toFIGS.1and3A to3C, sacrificial layers101and first semiconductor layers102may be alternately and repeatedly stacked on a transistor region TA of a substrate100. The sacrificial layers101and the first semiconductor layers102may be repeatedly stacked three times, as shown inFIGS.3A-3C, but example embodiments are not limited thereto. For example, the sacrificial layer101may include a material having an etch selectivity with respect to the first semiconductor layer102. According to example embodiments, the sacrificial layer101may have an etch selectivity of 1:10 to 1:200 with respect to the first semiconductor layer102. For example, the sacrificial layer101may include one of SiGe, Si and Ge, and the first semiconductor layer102may include another one of SiGe, Si and Ge. The sacrificial layers101and the first semiconductor layers102may be formed by performing an epitaxial process using the substrate100as a seed layer. For example, the epitaxial process may include a chemical vapor deposition process or a molecular beam epitaxy process. The sacrificial layers101and the first semiconductor layer102may be sequentially formed in the same chamber. The sacrificial layers101and the first semiconductor layer102may be conformally formed on the substrate100. The sacrificial layers101and the first semiconductor layer102may be formed to have substantially the same thickness, but example embodiments are not limited thereto. Referring toFIGS.1and4A to4C, the sacrificial layers101and the first semiconductor layers102may be removed from a region (hereinafter referred to as a first transistor region) where a first transistor is to be formed. To remove the sacrificial layers101and the first semiconductor layers102, mask patterns may be formed to cover a region (hereinafter referred as a second transistor region) where a second transistor is to be formed and a region (hereinafter referred as a third transistor region) where a third transistor is to be formed, and a dry and/or wet etching process may be performed using the mask patterns as an etch mask. Accordingly, the substrate100may be exposed in the first transistor region. A second semiconductor layer110may be formed on the first transistor region. The second semiconductor layer110may be formed by performing a selective epitaxial process using the exposed substrate100as a seed layer. Because the second and third transistor regions are covered by the mask pattern, the epitaxial growth may not proceed. For example, the second semiconductor layer110may include the same material as the first semiconductor layer102. However, example embodiments are not limited thereto. The second semiconductor layer110may be formed to have the same height as a height of a structure formed on the second and third transistor regions. The second semiconductor layer110may be formed to have a lower height than that of the structure formed on the second and third transistor regions. The mask pattern may be removed by a subsequent ashing process. Referring toFIGS.1and5A to5C, a first, a second and a third preliminary channel regions PCH1, PCH2and PCH3may be formed on the first to third transistor regions, respectively, by performing a patterning process on the substrate100, on which the second semiconductor layer110may be formed with respect to the first transistor region. The sacrificial layers101and the first semiconductor layers102inFIGS.4B and4Cmay correspond to preliminary sacrificial patterns103and first semiconductor patterns104inFIGS.5B and5C, respectively. The first preliminary channel region PCH1may have a first width W1, and may be directly connected to the substrate100. The second and third preliminary channel regions PCH2and PCH3may have a second and a third width W2and W3, respectively. The patterning process may include an anisotropic dry etching process using a mask pattern (not shown). The third width W3may be greater than the second width W2. For example, the third width W3may be about 1.2 to about 3 times greater than the second width W2. The first width W1may be less than the second width W2, but example embodiments are not limited thereto. After performing the patterning process, capping insulating layers121may be formed on the first to third preliminary channel regions PCH1-PCH3, respectively. For example, the capping insulation layers121may be formed through a thermal oxidation process. For example, the capping insulation layer121formed on the first preliminary channel region PCH1may include a silicon oxide layer, and the capping insulation layers121formed on the second and third preliminary channel regions PCH2and PCH3may include a silicon-germanium oxide layer. Alternatively, the capping insulation layer121may be formed through a deposition process. Referring toFIGS.1and6A to6C, dummy gates131may be formed on the first to third transistor regions, respectively. The dummy gates131may be shaped in a form of, for example, a line or a bar extending in a first direction d1. Gate mask patterns135may be formed on the dummy gates131. Forming the dummy gates131and the gate mask patterns135may include sequentially forming a dummy gate layer and a gate mask layer, and sequentially patterning the dummy gate layer and the gate mask layer. The dummy gate layer may include polycrystalline silicon. The gate mask layer may include a silicon nitride layer or a silicon oxynitride layer. During a patterning process, a portion of the capping insulation layers121may be removed together with the dummy gate layer and the gate mask layer. Gate spacers GS may be formed on opposite sidewalls of the dummy gates131. The gate spacers GS may include at least one of, for example, a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. The gate spacers GS may be formed by forming a spacer layer using a deposition process such as a chemical mechanical deposition or an atomic layer deposition and subsequently performing an anisotropic etching process thereon. The preliminary channel regions PCH1-PCH3may be patterned using the gate mask patterns135and the gate spacers GS as an etch mask. A first channel region CH1may be formed by the patterning process in the first transistor region. The second preliminary channel region PCH2may be formed in the second transistor region by the patterning process. As a result, the preliminary sacrificial patterns103and the first semiconductor patterns104of the second preliminary channel region PGH2may correspond to sacrificial patterns105and second channel portions NS2, respectively. Furthermore, the preliminary sacrificial patterns103and the first semiconductor patterns104of the third preliminary channel region PCH3may correspond to sacrificial patterns105and third channel portions NS3, respectively. A length of the second channel portions NS2may be substantially equal to that of the third channel portions NS3in the second direction d2. A length of the first channel region CH1may be substantially equal to those of the second and third channel portions NS2and NS3in the second direction d2. Recess regions RS may be formed by horizontally removing a portion of the sacrificial patterns105. Formation of the recess regions RS may be performed by an etching source having an etch selectivity with respect to the sacrificial patterns105. For example, when the first channel region CH1and the second and third channel portions NS2and NS3include silicon, and the sacrificial patterns105include silicon germanium, the formation of the recess regions RS may be performed using an etching solution containing peracetic acid. Barrier insulation patterns106may be formed in the recess regions RS. The barrier insulation patterns106may be spaced apart from each other and have the second channel portions NS2or the third channel portions NS3interposed therebetween. The barrier insulation patterns106may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. Formation of the barrier insulation patterns106may include performing an anisotropic etching process after conformally forming an insulation layer on a resultant structure formed with the recess regions RS. ReferringFIGS.1and7A to7C, source and drain regions SD may be formed on opposite sidewalls of each of the dummy gates131. The source and drain regions SD may be formed by a selective epitaxial process using the substrate100as a seed layer. When the transistor region TA is an NMOSFET region, the source and drain regions SD may include a material that provides tensile stress to the channel region. For example, the source and drain regions SD may include a silicon carbide layer whose lattice constant is less than that of silicon, or a silicon layer whose lattice constant is substantially equal to that of the substrate100. When the transistor region TA is a PMOSFET region, the source and drain regions SD may include a material that provides compressive stress to the channel region. For example, the source and drain regions SD may include a silicon germanium layer whose lattice constant is greater than that of silicon. Referring toFIGS.1and8A to8C, an interlayer insulation layer123may be formed on the substrate100. Then, a portion of the interlayer insulation layer123may be removed by performing a planarization process. The planarization process may be performed until upper surfaces of the dummy gates131are exposed. The planarization process may include an etch back and/or a chemical mechanical polishing (CMP) process. When planarizing the interlayer insulating layer123, the gate mask patterns135may be removed together with the interlayer insulating layer123. For example, the interlayer insulating layer123may include a silicon oxide layer or a silicon oxynitride layer. The dummy gates131exposed by the planarization process may be selectively removed. The capping insulation layer121may be removed simultaneously with or separately from the removal of the dummy gates131. Upper surfaces of the first channel region CH1and the second and third preliminary channel regions PCH2and PCH3may be exposed by the removal of the dummy gates131. The sacrificial patterns105may be selectively removed from the second and third preliminary channel regions PCH2and PCH3. For example, when the sacrificial patterns105include SiGe and the second and third channel portions NS2and NS3include silicon (Si), the selective etching process may be performed using an etching solution containing peracetic acid. The etching solution may further include a hydrofluoric acid (HF) solution and deionized water. The first channel region CH1may include the same material as the second and third channel portions NS2and NS3. The source and drain regions SD may be covered by the barrier insulation patterns106. Accordingly, the source and drain regions SD may be protected from the etching solution used to selectively remove the sacrificial patterns105. A first trench TC1, a second trench TC2and a third trench TC3may be formed by removing the dummy gates131and the sacrificial patterns105in the first to third transistor regions. The first trench TC1may be defined by an upper surface of the first channel region CH1and the gate pacer GS. The second trench TC2may be defined by the second channel portions NS2, the gate spacer GS and the source and drain regions SD (or the barrier insulation patterns106). The second trench TC2may extend between the second channel portions NS2and between the substrate100and the second channel portion NS2that is most adjacent to the substrate100. The third trench TC3may be defined by the third channel portions NS3, the gate spacer GS and the source and drain regions SD. The third trench TC3may extend between the third channel portions NS3and between the substrate100and the third channel portion NS3that is most adjacent to the substrate100. Hereafter, the second channel portions NS2may be referred as the second channel region CH2, and the third channel portions NS3may be referred as the third channel region CH3. Referring back toFIGS.1and2A to2C, the gate insulation layer and the gate electrode may be formed in each of the first to third trenches TC1-TC3. For example, the first gate insulation pattern GI1and the first gate electrode GE1may be formed in the first trench TC1, the second gate insulation pattern GI2and the second gate electrode GE2may be formed in the second trench TC2and the third gate insulation pattern GI3and a third gate electrode GE3may be formed in the third trench TC3. More specifically, the gate insulation pattern and the gate electrode may be formed by performing a planarization process after sequentially forming a gate insulation layer and a gate conductive layer in the first to third trenches TC1-TC3. For example, the gate insulation layer may include at least one of a silicon oxide layer, a silicon oxynitride layer and a high-k dielectric layer having a dielectric constant greater than that of a silicon oxide layer. For example, the gate conductive layer may include at least one of a doped semiconductor material, a conductive metal nitride and a metal. The second gate insulation pattern GI2and the second gate electrode GE2may extend between the second channel portions NS2and between the substrate100and the second channel portion NS2that is most adjacent to the substrate100. The third gate insulation pattern GI3and the third gate electrode GE3may extend between the third channel portions NS3and between the substrate100and the third channel portion NS3that is most adjacent to the substrate100. Upper portions of the gate insulation patterns GI1-GI3and the gate electrodes GE1-GE3may be recessed. Subsequently, capping patterns GP may be formed in recessed regions of the gate insulation patterns GI1-GI3and the gate electrodes GE1-GE3. For example, the capping pattern GP may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. FIG.9is a plan view illustrating a semiconductor device according to example embodiment.FIG.10Ashows cross-sectional views taken along lines A-A′ and B-B′ ofFIG.9.FIG.10Bshows cross-sectional views taken along lines C-C′ and D-D′ ofFIG.9.FIG.10Cshows cross-sectional views taken along lines E-E′ and F-F′ ofFIG.9. A duplicated description about the above-described elements or operations may be omitted. Referring toFIGS.9and10A to10C, a first transistor TR1, a second transistor TR2and a third transistor TR3may be provided on a substrate100. The substrate100may include a transistor region TA. The first to third transistors TR1-TR3may have the same conductivity type. The first to third transistor regions TR1-TR3may include a first active region ACT1, a second active region ACT2and a third active region ACT3, respectively. The first to third active regions ACT1-ACT3may include a first channel region CH1, a second channel region CH2and a third channel region CH3, respectively. The first to third active regions ACT1-ACT3may further include source and drain regions SD spaced apart from each other and having the channel regions interposed therebetween. The source and drain regions SD may be epitaxial patterns formed using the substrate100as a seed layer. The first to third transistors TR1-TR3may be configured to have threshold voltages different from each other. For example, the threshold voltage of the second transistor TR2may be greater than that of the third transistor TR3, and the threshold voltage of the first transistor TR1may be greater than that of the second transistor TR2. For example, the first transistor TR1may have a threshold voltage of about 0.30 V to about 0.59 V, the second transistor TR2may have a threshold voltage of about 0.21 V to about 0.29 V, and the third transistor TR3may have a threshold voltage of about 0.15 V to about 0.20 V. However, example embodiments are not limited thereto. The first to third channel regions CH1-CH3may have substantially the same doping concentrations. Gate insulation layers of the first to third transistors TR1-TR3may include the same material and may be formed at the same time, which will be described in a semiconductor manufacturing method according to an example embodiment later. Each of the first to third channel regions CH1-CH3may include a plurality channel portions spaced apart from each other in a direction perpendicular to an upper surface of the substrate100. For example, the first channel region CH1may include three first channel portions NS1, the second channel region CH2may include three second channel portions NS2and the third channel region CH3may include three third channel portions NS3. The number of the channel portions NS1-NS3respectively included in each of the first to third channel regions CH1-CH3is not limited to three and may be any number that is greater than one. The number of each of the first to third channel portions NS1-NS3may be the same, but example embodiments are not limited thereto. The first to third channel portions NS1-NS3may be spaced apart from the upper surface of the substrate100. The first to third channel portions NS1-NS3may include the same material. For example, the first to third channel portions NS1-NS3may include at least one of silicon (Si), silicon germanium (SiGe) and germanium (Ge). The first gate electrode GE1may extend between the first channel portions NS1, and between the substrate100and the first channel portion NS1most adjacent to the substrate100. Barrier insulation patterns106may be provided between the source and drain regions SD and the first channel portions NS1. The barrier insulation patterns106may be spaced apart from each other and have the first channel portion NS1interposed therebetween. A fourth width W4of the first channel portion NS1may be less than a second width W2of the second channel portion NS2in a first direction d1. For example, the second width W2may be about 1.2 to about 3 times greater than the fourth width W4. A third width W3of the third channel portion NS3may be greater than the second width W2of the second channel portion NS2in the first direction d1. For example, the third width W3may be about 1.2 to about 3 times greater than the second width W2. A length of each of the first to third channel portions NS1-NS3may be substantially equal to each other in a second direction d2. Due to differences among the second to fourth widths, a threshold voltage of the first transistor TR1may be greater than that of the second transistor TR2, and a threshold voltage of the second transistor TR2may be greater than that of the third transistor TR3. According to example embodiments, a plurality of transistors having different threshold voltages may be provided in a semiconductor device. For example, the plurality of transistors having different threshold voltages may be provided by varying widths of channel regions. FIGS.11A,12A,13A and14Aare cross-sectional views taken along lines A-A′ and B-B′ ofFIG.9.FIGS.11B,12B,13B and14Bare cross-sectional views taken along lines C-C′ and D-D′ ofFIG.9.FIGS.11C,12C,13C and14Care cross-sectional views taken along lines E-E′ and F-F′ ofFIG.9. Hereinafter, a method of manufacturing a semiconductor device according to example embodiments with reference toFIGS.9and11A to14Cwill be described. Referring toFIG.9andFIGS.11A to11C, first, second and third preliminary channel regions PCH1, PCH2and PCH3may be formed on the first, second and third transistor regions, respectively, after performing a patterning process on the results that are described with reference toFIGS.3A to3C. The sacrificial layers101and the first semiconductor layers102shown inFIGS.3A to3Cmay correspond to preliminary sacrificial patterns103and first semiconductor patterns104shown inFIGS.11A to11C, respectively. The first to third preliminary channel regions PCH1-PCH3may have widths different from each other. For example, the first preliminary channel region PCH1may have a fourth width W4, and the second and third preliminary channel regions PCH2and PCH3may have second and third widths W2and W3, respectively. The third width W3may be greater than the second width W2. For example, the third width W3may be about 1.2 to about 3 times greater than the second width W2. The second width W2may be greater than the fourth width W4. For example, the second width W2may be about 1.2 to about 3 times greater than the fourth width W4. After performing the patterning process, capping insulation layers121may be formed on the first to third preliminary channel regions PCH1-PCH3. Referring toFIGS.9and12A to12C, dummy gates may be formed on the first to third transistor regions, respectively. The dummy gates131may be shaped in a form of, for example, a line or a bar extending in a first direction d1. Gate mask patterns135may be formed on the dummy gates131. The dummy gate layer may include polycrystalline silicon. The gate mask layer may include a silicon nitride layer or a silicon oxynitride layer. During the patterning process, a portion of the capping insulation layers121may be removed together with the dummy gate layer and the gate mask layer. Gate spacers GS may be formed on opposite sidewalls of the dummy gates131. The gate spacers GS may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. The preliminary channel regions PCH1-PCH3may be formed using the gate mask patterns135and the gate spacers GS as an etch mask. As a result, the first, second and third channel portions NS1, NS2and NS3and sacrificial patterns105may be formed. Recess regions RS may be formed by horizontally removing a portion of the sacrificial patterns105. Barrier insulation patterns106may be formed in each of the recess regions RS. Referring toFIGS.9and13A to13C, the source and drain regions SD may be formed on opposite sidewalls of each of the dummy gates131. The source and drain regions SD may be formed by a selective epitaxial process using the substrate100as a seed layer. When the transistor region TA is an NMOSFET region, the source and drain regions SD may include a material that provides tensile stress to the channel region. For example, the source and drain regions SD may include a silicon carbide layer whose lattice constant is less than that of silicon, or a silicon layer whose lattice constant is substantially equal to that of the substrate100. When the transistor region TA is a PMOSFET region, the source and drain regions SD may include a material that provides compressive stress to the channel region. For example, the source and drain regions SD may include a silicon germanium layer whose lattice constant is greater than that of silicon. Referring toFIGS.9and14A to14C, an interlayer insulation layer123may be formed on the substrate100. Then, a portion of the interlayer insulation layer123may be removed by performing a planarization process. The planarization process may be performed until upper surfaces of the dummy gates131are exposed. The planarization process may include an etch back and/or a chemical mechanical polishing (CMP) process. When planarizing the interlayer insulating layer123, the gate mask patterns135may be removed together with the interlayer insulating layer123. For example, the interlayer insulating layer123may include a silicon oxide layer or a silicon oxynitride layer. The dummy gates131exposed by the planarization process may be selectively removed. The capping insulation layer121may be removed simultaneously with or separately from the removal of the dummy gates131. Upper surfaces of the first to third preliminary channel regions PCH1-PCH3may be exposed by the removal of the dummy gates131. The sacrificial patterns105may be selectively removed from the first to third preliminary channel regions PCH1-PCH3. For example, when the sacrificial patterns105include SiGe and the first to third channel portions NS1-NS3include silicon (Si), the selective etching process may be performed using an etching solution containing peracetic acid. The etching solution may further include a hydrofluoric acid (HF) solution and deionized water. The source and drain regions SD may be covered by the barrier insulation patterns106. Accordingly, the source and drain regions SD may be protected from the etching solution used to selectively remove the sacrificial patterns105. A first trench TC1, a second trench TC2and a third trench TC3may be formed in the first to third transistor regions by removing the dummy gates131and the sacrificial patterns105. Referring back toFIGS.9and10A to10C, a gate insulation layer and a gate electrode may be formed in each of the first to third trenches TC1-TC3. For example, the first gate insulation pattern GI1and the first gate electrode GE1may be formed in the first trench TC1, the second gate insulation pattern GI2and the second gate electrode GE2may be formed in the second trench TC2and the third gate insulation pattern GI3and the third gate electrode GE3may be formed in the third trench TC3. More specifically, the gate insulation pattern and the gate electrode may be formed by performing a planarization process after sequentially forming a gate insulation layer and a gate conductive layer in the first to third trenches TC1-TC3. Upper portions of the gate insulation patterns GI1-GI3and the gate electrodes GE1-GE3may be recessed. Subsequently, capping patterns GP may be formed in recessed regions of the gate insulation patterns GI1-GI3and the gate electrodes GE1-GE3. For example, the capping pattern GP may include at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. FIG.15is a plan view illustrating a semiconductor device according to example embodiments.FIG.16Ashows cross-sectional views taken along lines A-A′ and B-B′ ofFIG.15.FIG.16Bshows cross-sectional views taken along lines C-C′ and D-D′ ofFIG.15.FIG.16Cshows cross-sectional views taken along lines E-E′ and F-F′ ofFIG.15. For the sake of simplification of description, the duplicated description will be omitted. Referring toFIG.15andFIGS.16A to16C, a first transistor TR1, a second transistor TR2and a third transistor TR3may be provided on a substrate100. The substrate100may include a transistor region TA. The first to third transistors TR1-TR3have the same conductivity type. The first to third transistor regions TR1-TR3may include a first active region ACT1, a second active region ACT2and a third active region ACT3, respectively. The first to third active regions ACT1-ACT3may include a first channel region CH1, a second channel region CH2and a third channel region CH3, respectively. The first to third active regions ACT1-ACT3may further include source and drain regions SD spaced apart from each other and having the channel regions interposed therebetween. The source and drain regions SD may be epitaxial patterns formed using the substrate100as a seed layer. Each of the second and third channel regions CH2and CH3may include a plurality of channel portions spaced apart from each other in a direction perpendicular to the substrate100(e.g., an upper surface of the substrate100). For example, the second channel region CH2may include three second channel portions NS2, and the third channel region CH3may include three third channel portions NS3. The number of each of the second and third channel portions NS2and NS3is not limited to three. A fifth width W5of the second channel portion NS2may be substantially equal to a sixth width W6of the third channel portion NS3in a first direction d1. Alternatively, the fifth width W5of the second channel portion NS2may be different from the sixth width W6of the third channel portion NS3in the first direction d1. The first channel region CH1of the first transistor TR1may have a fin shape protruding from the upper surface of the substrate100. The first channel region CH1may include the same material as the second and third channel regions CH2and CH3. A first width W1of the first channel region CH1may be less than or equal to the fifth width W5of the second channel region CH2in the first direction d1. However, example embodiments are not limited thereto. The first to third transistors TR1-TR3may include a first, second and third gate electrodes GE1, GE2and GE3, respectively. The first and second gate electrodes GE1and GE2may include the same material. For example, the first and second gate electrode GE1and GE2may include one of TiN, TiAlN and TiAlC. The third gate electrodes GE3may include a material having a different work function from those of the first and second gate electrodes GE1and GE2. For example, the third gate electrode GE3may include another one of TiN, TiAlN and TiAlC that is not included in the first and second gate electrodes GE1and GE2. The first to third transistors TR1-TR3may be configured to have threshold voltages different from each other. For example, the threshold voltage of the third transistor TR3may be greater than that of the second transistor TR2, and the threshold voltage of the second transistor TR2may be greater than that of the first transistor TR1. The work function of the third gate electrode GE3may be different from that of the second gate electrode GE2. Accordingly, the threshold voltage of the second transistor TR2may be different from that of the third transistor TR3. For example, the third transistor TR3may have a threshold voltage of about 0.30 V to about 0.59 V, the second transistor TR2may have a threshold voltage of about 0.21 V to about 0.29 V, and the first transistor TR1may have a threshold voltage of about 0.15 V to about 0.20 V. However, example embodiments are not limited thereto. FIG.17Ashows cross-sectional views taken along lines A-A′ and B-B′ ofFIG.15.FIG.17Bshows cross-sectional views taken along lines C-C′ and D-D′ ofFIG.15.FIG.17Cshows cross-sectional views taken along lines E-E′ and F-F′ ofFIG.15. Hereinafter, a method of manufacturing a semiconductor device according to example embodiments will be described with reference toFIGS.15and17A to17C. Referring toFIG.15andFIGS.17A to17C, first, second and third preliminary channel regions PCH1, PCH2and PCH3may be formed on the first, second and third transistor regions, respectively, after performing a patterning process on the results described with reference toFIGS.4A to4C. The sacrificial layers101and the first semiconductor layers102shown inFIGS.4B and4Cmay correspond to preliminary sacrificial patterns103and first semiconductor patterns104inFIGS.17B and17C. The second semiconductor layer110ofFIG.17Amay be patterned to have a first width W1. The second and third preliminary channel regions PCH2and PCH3may have the width that is the same as each other. For example, the second preliminary channel region PCH2may have a fifth width W5, and the third preliminary channel region PCH3may have a sixth width W6. The fifth width W5may be the same as the sixth width W6. Alternatively, the fifth width W5may be different from the sixth width W6. After performing the patterning process, capping insulation layers121may be formed on the first to third preliminary channel regions PCH1-PCH3. Hereinafter, the same processes asFIGS.6A to6C,FIGS.7A to7CandFIGS.8A to8Cmay be performed on results of the processes described above inFIGS.17A-17C. Referring back toFIG.15andFIGS.16A to16C, first to third gate insulation patterns GI1-GI3and first to third gate electrodes GE1-GE3may be formed. The first gate electrode GE1and the second gate electrode GE2may include the same material to have the same work function and may be formed at the same time. The third gate electrode GE3may include a material having a different work function from those of the first and second gate electrodes GE1and GE2. For example, the first and second gate electrodes GE1and GE2may include one of TiN, TiAlN and TiAlC, and the third gate electrode GE3may include another one of TiN, TiAlN and TiAlC. For example, the third gate electrode GE3may be formed after forming the first and second gate electrodes GE1and GE2. That is, a third transistor region may be masked by an insulation layer during formation of the first and second gate electrodes GE1and GE2, and then the third gate electrode GE3may be formed after removing the insulation layer. FIG.18is a cross-sectional view illustrating a shape of a channel region according to example embodiments. A channel region CH may include channel portions NS which is vertically spaced apart from each other. An outer peripheral surface of each of the channel portions NS may have a shape such that a corner is rounded. The shape of the channel portions NS may be formed through a surface treatment. For example, the surface treatment may include exposing the surface of the channel portions NS to a gas containing hydrogen chloride (HCl), and annealing in a hydrogen (H2) gas atmosphere. FIG.19is an equivalent circuit diagram of a CMOS SRAM cell in which transistors according to example embodiments are provided. Referring toFIG.19, the CMOS SRAM cell may include a pair of driver transistors TD1and TD2, a pair of transfer transistors TT1and TT2and a pair of load transistors TL1and TL2. The driver transistors TD1and TD2may be pull-down transistors, the transfer transistors TT1and TT2may be pass transistors, and the load transistors TL1and TL2may be pull-up transistors. The driver transistors TD1and TD2and the transfer transistors TT1and TT2may be NMOS transistors, and the load transistors TL1and TL2may be PMOS transistors. The first driver transistor TD1and the first transfer transistor TT1may be connected in series to each other. A source region of the first driver transistor TD1may be electrically connected to a ground line Vss, and a drain region of the first transfer transistor TT1may be electrically connected to a first bit line BL1. The second driver transistor TD2and the transfer transistor TT2may be connected in series to each other. A source region of the second driver transistor TD2may be electrically to the ground line Vss, and a drain region of the second transfer transistor TT2may be electrically connected to a second bit line BL2. Source and drain regions of the first load transistor TL1may be electrically connected to a power line Vcc and a drain region of the first driver transistor TD1, respectively. Source and drain regions of the second load transistor TL2may be electrically connected to the power line Vcc and a drain region of the second driver transistor TD2, respectively. The drain region of the first load transistor TL1, the drain region of the first driver transistor TD1, and a source region of the first transfer transistor TT1may be electrically connected to a first node N1. The drain region of the second load transistor TL2, the drain region of the second driver transistor TD2, and a source region of the second transfer transistor TT2may be electrically connected to a second node N2. A gate electrode of the first driver transistor TD1and a gate electrode of the first load transistor TL1may be electrically connected to the second node N2, and a gate electrode of the second driver transistor TD2and a gate electrode of the second load transistor TL2may be electrically connected to the first node N1. Gate electrodes of the first and second transfer transistors TT1and TT2may be electrically connected to a word line WL. The first driver transistor TD1, the first transfer transistor TT1, and the first load transistor TL1may be included in a first half cell H1, and the second driver transistor TD2, the second transfer transistor TT2, and the second load transistor TL2may be included in a second half cell H2. At least three of the driver transistors TD1and TD2, the transfer transistors TT1and TT2and the load transistors TL1and TL2may include first to third transistors having different voltages from each other according to example embodiments. Although a few embodiments have been shown and described, it would be appreciated by those skilled in the art that changes may be made in example embodiments without departing from the principles and spirit of the disclosure, the scope of which is defined in the claims and their equivalents. | 54,495 |
11942559 | DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying figures in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without inventive steps shall fall within a protection scope of the present application. As shown inFIG.1, the present application provides a method of preventing TFT from ESD damaging, including following steps: S1. acquiring a test data of at least one film layer of a plurality of TFTs, the test data including manufacturing parameters of each film layer and electrostatic discharge voltages that each film layer can withstand. The electrostatic discharge voltage is an average value of the actual electrostatic discharge voltage that the same film layer of a plurality of TFTs can withstand. In the test data, the same film layer corresponds to multiple sets of manufacturing parameters and a plurality of voltage thresholds, wherein the voltage threshold is a maximum electrostatic discharge voltage can be withstood. As shown inFIG.1, the TFT includes a substrate11, a gate layer12, a gate insulating layer13, an active layer14, an ohmic contact layer15, a source and drain electrode layer16, an insulating protection layer17, and a pixel electrode18stacked in sequence. S2. Data fitting the test data to obtain at least one fitting curve. Data fitting is also called curve fitting, commonly known as pull curve. It is a way of substituting existing data into a numerical formula through mathematical methods. Scientific and engineering problems can obtain a number of discrete data through methods such as sampling and experiments. Based on these data, we often hope to obtain a continuous function, that is a curve, or a denser discrete equation that is consistent with the known data. This process It is called fitting. In this embodiment of the present application, it is a linear fitting, and in other embodiments of the present application, it may also be least square fitting. S3. Acquiring a relationship between an anti-ESD capability of the TFT and the manufacturing parameters of each film layer from the fitting curve. In one embodiment, as shown inFIG.2, the circle without filling means that a thickness of the gate layer12is 7000 angstroms, and the circle stripe filling means that the thickness of the gate layer12is 4000 angstroms, when the manufacturing parameter is only the ramp angle of the gate layer12, when the ramp angle of the gate layer12ranges from 0° to 70°, the larger the angle of the ramp angle, the smaller the electrostatic discharge voltage the TFT can withstood, the smaller the ESD resistance. The test data also includes a damage ratio or a good ratio of the plurality of TFTs, the damage ratio is a ratio of a number of TFTs damaged by the electrostatic discharge voltage to the to a total number of the plurality of TFTs, the good ratio is a ratio of a number of TFTs that are not damaged by the electrostatic discharge voltage to the total number of the plurality of TFTs. Referring toFIG.3,FIG.3discloses the ordinate is changed to the damage ratio. It can be seen fromFIG.3that when the ramp angle of the gate layer is greater than 40°, the greater the ramp angle of the gate layer, the greater the damage ratio of the TFT, so when the ramp angle of the layer ranges from 0° to 40°, and the smaller the ramp angle of the gate layer, the better the ESD resistance of the TFT. As shown inFIG.4, in one embodiment, when the manufacturing parameter is only the thickness of the gate insulating layer13, the thicker the thickness of the gate insulating layer13, the greater the electrostatic discharge voltage the TFT can withstand, that is, the better the ESD resistance of the TFT. A material of the gate insulating layer13is an inorganic material. In this embodiment, the gate insulating layer13includes a first gate insulating layer (not shown) and a second gate insulating layer (not shown). The second gate insulating layer is disposed on the first gate insulating layer. As shown inFIGS.5and6, a thickness of the gate layer12is d0, an angle of the ramp angle of the gate layer12is A, a sum of thicknesses of the gate insulating layer13and the active layer14at a slope top of the gate layer12is d1, a sum of thicknesses of the gate insulating layer13and the active layer14at a ramp of the gate layer12is d2, and a sum of the thicknesses of the gate insulating layer13and the active layer14at a bottom of the gate layer is d3, wherein d2=0.773*d3+0.156*d3*cosA−0.061*d0. The present application provides a method of preventing TFTs from ESD damaging, by fitting the test data, the relationship between the anti-ESD ability of TFTs and the manufacturing parameters of each film layer is acquired, that is, the ramp angle A of the gate layer12ranges from 0° to 40°, the smaller the angle of the ramp angle A of the gate layer12, the better the ESD resistance of the TFT, the thicker the thickness of the gate insulating layer13, the better the anti-ESD ability of the TFT. The present application also provides a method of manufacturing a TFT, which includes setting manufacturing parameters of each film layer of the TFT according to a relationship between an anti-ESD capability of the TFT and the manufacturing parameters of each film layer obtained in the method of preventing components from ESD damaging of the present application. That is, the manufacturing parameters of the TFT film layer are set according to a relationship between the ESD and the film layer of the TFT, so as to prevent the TFT from ESD damaging. The present application also provides a display panel, which includes a TFT, and the TFT is manufactured by the TFT manufacturing method of the present application. Specific examples are used in the specification to illustrate the principles and embodiments of the present application. The descriptions of the above embodiment are only used to help understand the technical solutions and core ideas of the present application. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from a scope of the technical solutions of the embodiments of the present application. | 6,727 |
11942560 | Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In the present disclosure, reference to the formation or disposal of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Embodiments of the present disclosure are discussed in detail as follows. It should be appreciated, however, that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. FIG.1is a cross-sectional view of a semiconductor device structure1ain accordance with some embodiments of the present disclosure. As shown inFIG.1, the semiconductor device structure1amay include a substrate10, a channel layer20, a barrier layer30, a group III-V layer51, an electrode61and an electrode71. The semiconductor device structure1amay function as a diode component. The substrate10may include, without limitation, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate10may include, without limitation, sapphire, silicon on insulator (SOI), or other suitable materials. The channel layer20(or a nitride semiconductor layer) is disposed on the substrate10. The channel layer20may include a group III-V layer. The channel layer20may include, but is not limited to, a group III nitride, for example, a compound InxAlyGa1-x-yN, in which x+y≤1. The group III nitride further includes, but is not limited to, for example, a compound AlyGa(1-y)N, in which y≤1. The channel layer20includes a gallium nitride (GaN) layer. GaN has a band gap of about 3.4 eV. The thickness of the channel layer20ranges, but is not limited to, from about 0.5 μm to about 10 μm. The barrier layer30(or a nitride semiconductor layer) is disposed on the channel layer20. The barrier layer30may include a group III-V layer. The barrier layer30may include, but is not limited to, a group III nitride, for example, a compound InxAlyGa1-xyN, in which x+y≤1. The group III nitride further includes, but is not limited to, for example, a compound AlyGa(1-y)N, in which y≤1. The barrier layer30has a greater bandgap than that of the channel layer20. The barrier layer30includes an aluminum gallium nitride (AlGaN) layer. AlGaN has a band gap of about 4.0 eV. The thickness of the barrier layer30ranges, but is not limited to, from about 10 nm to about 100 nm. A heterojunction is formed between the barrier layer30and the channel layer20, and the polarization of the heterojunction of different nitrides forms a 2DEG region40in the channel layer20. The 2DEG region40is typically formed in a layer with a small bandgap, such as GaN. The group III-V layer51(or a nitride semiconductor layer) is disposed on the barrier layer30. The group III-V layer51is in direct contact with the barrier layer30. The group III-V layer51may include p-type dopants. It is contemplated that the group III-V layer51may include a p-doped GaN layer, p-doped AlGaN layer, p-doped AlN layer or other suitable III-V group layers. The p-type dopants may include at least one of magnesium (Mg), beryllium (Be), zinc (Zn) and cadmium (Cd). The group III-V layer51may control the concentration of the 2DEG region40. The group III-V layer51can be used to deplete the electrons of the 2DEG region40directly under the group III-V layer51. The thickness of the group III-V layer51may range from about 30 nm to about 50 nm. The thickness of the group III-V layer51may range from about 50 nm to about 70 nm. The thickness of the group III-V layer51may range from about 70 nm to about 100 nm. As shown inFIG.1, the 2DEG region40may include a region401in which some electrons are depleted and a region402in which electrons are substantially not depleted. The region401is not completely depleted. The region401may have a gradient concentration of 2DEG, e.g. with a lesser concentration abutting the electrode71and a greater concentration far from the electrode71. The region401may also be referred to as a low density 2DEG region. The region402may also be referred to as a high density 2DEG region. The group III-V layer51may have a surface511(or an upper surface), a surface512(or a side surface) and a surface513(or a side surface). The surface511may be away from the barrier layer30. The surface512is adjacent to the electrode61. The surface513is opposite to the surface512and far from the electrode61. The surface513is adjacent to the electrode71. The electrode61is disposed on the barrier layer30. The electrode61is spaced apart from the group III-V layer51. The electrode61may include titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), palladium (Pd), tungsten (W), titanium nitride (TiN) or other suitable materials. The electrode61may include a single layer structure. The electrode61may be a multilayer structure. For example, the electrode61may include a lower layer including Ti or TiN and an upper layer including Ti, Al, Ni, Cu, TiN, Au, Pt, Pd, W or an alloy thereof. The electrode61may function as a cathode of a diode. The electrode61may have a surface611. The surface611may also be referred to as an upper surface of the electrode61. The surface611of the electrode61may be elevationally the same as the surface511of the group III-V layer51. The surface611of the electrode61may be higher than the surface511of the group III-V layer51. The surface611of the electrode61may be lower than the surface511of the group III-V layer51. The electrode71is disposed on the channel layer20. The electrode71may cover the group III-V layer51. A portion of the electrode71may be disposed on the group III-V layer51. A portion of the electrode71may be in contact with the surface511of the group III-V layer51. The electrode71may be in contact with the surface513. The surface512is exposed from the electrode71. The electrode71is not in direct contact with the surface512of the group III-V layer51. The electrode71may penetrate the barrier layer30. The electrode71may extend into the barrier layer30. The electrode71may extend into the channel layer20. The electrode71may be in contact with the channel layer20. As shown inFIG.1, the electrode71may have a reversed L shape. More specifically, the electrode71may have a main portion disposed on the channel layer20and a protruding portion extending from the main portion to above the surface511of the group III-V layer51. The protruding portion of the electrode71may function as a field plate. The electrode71may include Ni, Cu, Au, Pt, Pd, W, Ti, TiN or other suitable materials. The electrode71may include a single layer structure. The electrode71may include a multilayer structure. For example, the electrode71may include a lower layer including Ni, TiN, Au, Pt, Pd, W and an upper layer including Ti, Al, Ni, Cu, TiN, Au, Pt, Pd, W or an alloy thereof. The electrode71may function as an anode of a diode. The electrode71may have a surface711. The surface711may also be referred to as an upper surface of the electrode71. The surface711of the electrode71may have a height exceeding a height of the surface611of the electrode61. The group III-V layer51, the barrier layer30and the channel layer20may function as a PIN diode A1. The electrode71and the channel layer20may function as a Schottky barrier diode A2. The PIN diode A1and the Schottky diode A2may be operated under forward and reverse bias, respectively. For example, when the semiconductor device structure1ais operated under forward bias between the electrode61and the electrode71, turn-on voltage is dominated by the Schottky diode A2, which can have a relatively low turn-on voltage than that of the PIN diode. For example, when the semiconductor device structure1ais operated under reverse bias, a relatively high depletion region is formed under the group III-V layer51. Under reverse bias, the 2DEG region40may include a region401, corresponding to relatively high depletion region, in which some electrons are depleted and a region402in which electrons are substantially not depleted. Since the current flows from region402to region401under revers bias, the current may exit the electrode71through the PIN diode A1instead of the Schottky diode A2. The relatively high depletion region401, which has a high resistance, may protect or shield the Schottky contact (which can be formed between the electrode71and the channel layer20) from overvoltage. In such case, the PIN diode A1and the 2DEG region40may provide the conductive path between the electrode61and the electrode71. That is, the breakdown voltage is dominated by the PIN diode A1, which has higher breakdown voltage than Schottky barrier diode A2. Thus, the semiconductor device structure1amay simultaneously have a lower turn-on voltage and a higher breakdown voltage. FIG.1Ais a cross-sectional view of a semiconductor device structure1a′ according to some other embodiments of the present disclosure. The semiconductor device structure1a′ has a structure similar to or the same as the semiconductor device structure1aas described and illustrated with reference toFIG.1, except that the group III-V layer51as shown inFIG.1is replaced by a dielectric layer55. The dielectric layer55may include, for example, a silicon dioxide layer. The dielectric layer55may have a thickness T2ranging from approximately 5 nm to approximately 20 nm. In the semiconductor device structure1a′, a field plate (e.g., the portion of the electrode71directly over the dielectric layer55) can be used to improve breakdown voltage (e.g. to pull up breakdown voltage). However, even with the field plate, such semiconductor device structure1a′ can still have relatively high leakage current when working or operating at a relatively low reverse bias voltage if the dielectric layer55has a relatively great thickness. Moreover, a relatively thin insulation layer (e.g., with a thickness from approximately 5 nm to approximately 20 nm) is vulnerable or subject to rupture, which can adversely affect manufacture of the semiconductor device structure1a′. Referring back toFIG.1, the semiconductor device structure1acan work effectively at a relatively less reverse bias voltage of approximately zero volt but have a relatively great breakdown voltage. In addition, the thickness of the group III-V layer51, which can deplete electrons even without any bias, can be relatively great while maintaining a low leakage current. In other words, the semiconductor device structure1acan be relatively robust. Further, the semiconductor device structure1amay have a relatively great breakdown voltage because the breakdown voltage is determined by the PIN diode A1under reverse bias. FIG.2is a cross-sectional view of a semiconductor device structure1bin accordance with some embodiments of the present disclosure. The semiconductor device structure1bhas a structure similar to or the same as the semiconductor device structure1aofFIG.1, with one difference being that the group III-V layer51is not completely covered by the electrode71′. A portion of the surface511of the group III-V layer51is exposed from the electrode71′. More specifically, a portion of the group III-V layer51is exposed from the protruding portion of the electrode71′. As shown inFIG.2, a width L1is covered by the electrode71′, and a width L2is exposed from the electrode71′. The ratio between L1and L2may range from about 30:70 to about 50:50. The ratio between L1and L2may range from about 50:50 to about 70:30. The ratio between L1and L2may range from about 70:30 to about 99:1. The ratio between the width L1and width L2may affect the performance of the device. For example, the ratio may change or affect the turn-on resistance. For example, the ratio may change or affect the leakage current. FIG.3is a cross-sectional view of a semiconductor device structure4in accordance with some embodiments of the present disclosure. The semiconductor device structure4can include a device1. The semiconductor device structure4can include a device2. The semiconductor device structure4can include a device3. The device1may include the semiconductor device structure1aas described and illustrated with reference toFIG.1. The device1may include the semiconductor device structure1aas described and illustrated with reference toFIG.2. The device1may be integrated with the device2or3. For example, the device1, the device2and the device3may share the substrate10, the channel layer20and the barrier layer30. The device2may be disposed adjacent to the device1. The device2may be separated from the device1by an isolation structure90. The device2may include a substrate10, a channel layer20, a barrier layer30, a p-doped layer52or a depletion layer52, a source and drain structure (or S/D structure)62and a gate72. The device2may be an enhancement-mode HEMT, which is preset to be in an OFF state when the gate72is in a zero bias state. The depletion layer52may be disposed on the barrier layer30. In addition, a portion of the depletion layer52may be disposed in a recess defined by the barrier layer30in order to completely deplete the 2DEG region40directly under the recess. The depletion layer52may include p-doped GaN layer, p-doped AlGaN layer, p-doped AlN layer or other suitable III-V group layers. The material of the depletion layer52may be the same as that of the group III-V layer51. At least a portion of an upper surface of the depletion layer52may be elevationally the same as the upper surface of the group III-V layer51. At least a portion of an upper surface of the depletion layer52may be elevationally the same as the upper surface of the electrode61. The source and drain structure62may be disposed on the barrier layer30. The source and drain structure62may include Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials. The material of the source and drain structure62may be the same as that of the electrode61. An upper surface of the source and drain structure62may be elevationally the same as the upper surface of the electrode61. The upper surface of the source and drain structure62may be elevationally the same as the upper surface of the group III-V layer51. The gate72may be disposed on the depletion layer52. The gate72may include Ni, Cu, Au, Pt, Pd, W, Ti, TiN or other suitable materials. The material of the gate72may be the same as that of the electrode71. At least a portion of an upper surface of the gate72may be elevationally the same as the upper surface of the electrode71. The device3may be disposed adjacent to the device1. The device3may be separated from the device1by the isolation structure90. The device3may include a substrate10, a channel layer20, a barrier layer30, a source and drain structure63and a gate73. The device3may be a depletion-mode HEMT, which is preset to be in an On state when the gate73is in a zero bias state. The source and drain structure63may be disposed on the barrier layer30. The source and drain structure63may include Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials. The material of the source and drain structure63may be the same as that of the electrode61. An upper surface of the source and drain structure63may be elevationally the same as the upper surface of the electrode61. The upper surface of the source and drain structure63may be elevationally the same as the upper surface of the group III-V layer51. The gate73may be disposed on the barrier layer30. The gate73may include Ni, Cu, Au, Pt, Pd, W, Ti, TiN or other suitable materials. The material of the gate73may be the same as that of the electrode71. An upper surface of the gate73may be lower than the upper surface of the electrode71. The semiconductor device structure4can include an integrated circuit, which can include HEMTs (e.g. devices2and3) and diodes (e.g. the device). In other words, transistors and diodes can be integrated in a monolithic GaN structure, which is beneficial to miniaturization FIG.4A,FIG.4B,FIG.4C,FIG.4DandFIG.4Eillustrate various stages of a method for manufacturing a semiconductor device structure1ain accordance with some embodiments of the present disclosure. Referring toFIG.4A, a substrate10is provided. A channel layer20, a barrier layer30and a semiconductor layer50are formed on the substrate10. The channel layer20, barrier layer30and/or semiconductor layer50may be formed by metal organic chemical vapor deposition (MOCVD), metal organic vapor-phase epitaxy (MOVPE), epitaxial growth, or other suitable processes. The semiconductor layer50may include p-type dopants. The semiconductor layer50may include p-doped GaN layer, p-doped AlGaN layer, p-doped AlN layer or other suitable semiconductor layers with p-type dopants. The p-type dopants may include at least one of Mg, Be, Zn and Cd. The semiconductor layer50may be treated by oxygen and/or nitrogen at a temperature above 600° C. in order to activate the semiconductor layer50. After the semiconductor layer50is activated, the bonding between p-type dopant and hydrogen—such as Mg—H bonding—in the semiconductor layer50may be broken, thereby providing holes to exhaust electrons in the 2DEG region40. Referring toFIG.4B, the semiconductor layer50may be patterned to form a group III-V layer51. The semiconductor layer50may be patterned by an etching process. Referring toFIG.4C, an electrode61is formed on the barrier layer30and adjacent to the group III-V layer51. The electrode61may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition process (PVD), an atomic layer deposition (ALD) process, and a sputter process or other suitable process. Referring toFIG.4D, an opening O1is formed. The opening O1may penetrate the barrier layer30. The opening O1may expose the channel layer20. The opening O1may be formed by performing one or more etching processes to remove a portion of the barrier layer30and the channel layer20. Referring toFIG.4E, an electrode71is formed to fill the opening O1and cover the upper surface of the group III-V layer51. As a result, a semiconductor device structure1ais produced. The electrode71may be formed by a CVD, PVD, ALD, sputter or other suitable processes. FIG.5A,FIG.5B,FIG.5C,FIG.5D,FIG.5E,FIG.5F,FIG.5G,FIG.5H,FIG.5IandFIG.5Jillustrate various stages of a method for manufacturing a semiconductor device structure4in accordance with some embodiments of the present disclosure. Referring toFIG.5A, a substrate10is provided. A channel layer20and a barrier layer30are formed on the substrate10. Referring toFIG.5B, an opening O2is formed. The opening O2may be formed by performing an etching process on the barrier layer30. The barrier layer30may have an upper surface corresponding to an unetched region and a lower surface corresponding to an etched region. Referring toFIG.5C, a semiconductor layer50is formed to cover the barrier layer30. The semiconductor layer50may fill the opening O2. The semiconductor layer50may include a recess R corresponding to the etched region of the barrier layer30. The semiconductor layer50may be activated by treating with oxygen and/or nitrogen. Referring toFIG.5D, a semiconductor layer50is patterned to form a group III-V layer51and an depletion layer52. Referring toFIG.5E, a conductive layer60is formed to cover the group III-V layer51, the depletion layer52and an upper surface of the barrier layer30. The conductive layer60may include Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN or other suitable materials. The conductive layer60may include a single layer or a multilayer. The process of forming the conductive layer60may be the same as or similar to that of the electrode61. Referring toFIG.5F, the conductive layer60is patterned to form the electrode61, the source and drain structure62and the source and drain structure63. The electrode61, the source and drain structure62and the source and drain structure63may have upper surfaces that are elevationally the same. Referring toFIG.5G, isolation structures90are formed to define regions of different devices, such as devices1,2and3shown inFIG.5J. A plurality of the openings may be formed, and a dielectric layer may be filled into the opening to form the isolation structure90. Referring toFIG.5H, an opening O3may be formed. The opening O3may expose the side surfaces of the barrier layer30and the channel layer20. The opening O3may expose a portion of the channel layer20. The opening O3may penetrate the barrier layer30. The opening O3may abut the group III-V layer51. Referring toFIG.5I, a conductive layer70is formed to cover the group III-V layer51, the depletion layer52, the electrode61, the source and drain structure62, the source and drain structure63and the barrier layer30. The conductive layer70may fill the opening O3. The conductive layer70may be in contact with a portion of the channel layer20. The conductive layer70may include Ti, Al, Ni, Cu, TiN, Au, Pt, Pd, W or an alloy thereof. The conductive layer70may include a single layer or a multilayer. The process of forming the conductive layer70may be the same as or similar to that of the electrode71. Referring toFIG.5J, the conductive layer70is patterned to form the electrode71, the gate72and the gate73. As a result, the devices1,2and3are formed, and the semiconductor device structure4is produced. FIG.5AtoFIG.5Jillustrate an example to integrate the process of manufacturing the diode structure, such as the device1, and the HEMT structure, such as the devices2and3. Therefore, the process for forming the semiconductor device structure4may be simplified. As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “lower,” “left,” “right” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event of circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. As used herein with respect to a given value or range, the term “about” generally refers to within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise. The term “substantially coplanar” can refer to two surfaces within micrometers (μm) of lying along a same plane, such as within 10 within within 1 or within 0.5 μm of lying along the same plane. When referring to numerical values or characteristics as “substantially” the same, the term can refer to the values lying within ±10%, ±5%, ±1%, or ±0.5% of an average of the values. The foregoing outlines features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. | 25,273 |
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